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Commit | Line | Data |
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8dd3dca3 AJ |
1 | #include "hw/hw.h" |
2 | #include "hw/boards.h" | |
3 | ||
8dd3dca3 AJ |
4 | void cpu_save(QEMUFile *f, void *opaque) |
5 | { | |
6 | int i; | |
7 | CPUARMState *env = (CPUARMState *)opaque; | |
8 | ||
9 | for (i = 0; i < 16; i++) { | |
10 | qemu_put_be32(f, env->regs[i]); | |
11 | } | |
12 | qemu_put_be32(f, cpsr_read(env)); | |
13 | qemu_put_be32(f, env->spsr); | |
14 | for (i = 0; i < 6; i++) { | |
15 | qemu_put_be32(f, env->banked_spsr[i]); | |
16 | qemu_put_be32(f, env->banked_r13[i]); | |
17 | qemu_put_be32(f, env->banked_r14[i]); | |
18 | } | |
19 | for (i = 0; i < 5; i++) { | |
20 | qemu_put_be32(f, env->usr_regs[i]); | |
21 | qemu_put_be32(f, env->fiq_regs[i]); | |
22 | } | |
23 | qemu_put_be32(f, env->cp15.c0_cpuid); | |
24 | qemu_put_be32(f, env->cp15.c0_cachetype); | |
ffe47d33 | 25 | qemu_put_be32(f, env->cp15.c0_cssel); |
8dd3dca3 AJ |
26 | qemu_put_be32(f, env->cp15.c1_sys); |
27 | qemu_put_be32(f, env->cp15.c1_coproc); | |
28 | qemu_put_be32(f, env->cp15.c1_xscaleauxcr); | |
29 | qemu_put_be32(f, env->cp15.c2_base0); | |
30 | qemu_put_be32(f, env->cp15.c2_base1); | |
ffe47d33 | 31 | qemu_put_be32(f, env->cp15.c2_control); |
8dd3dca3 | 32 | qemu_put_be32(f, env->cp15.c2_mask); |
ffe47d33 | 33 | qemu_put_be32(f, env->cp15.c2_base_mask); |
8dd3dca3 AJ |
34 | qemu_put_be32(f, env->cp15.c2_data); |
35 | qemu_put_be32(f, env->cp15.c2_insn); | |
36 | qemu_put_be32(f, env->cp15.c3); | |
37 | qemu_put_be32(f, env->cp15.c5_insn); | |
38 | qemu_put_be32(f, env->cp15.c5_data); | |
39 | for (i = 0; i < 8; i++) { | |
40 | qemu_put_be32(f, env->cp15.c6_region[i]); | |
41 | } | |
42 | qemu_put_be32(f, env->cp15.c6_insn); | |
43 | qemu_put_be32(f, env->cp15.c6_data); | |
44 | qemu_put_be32(f, env->cp15.c9_insn); | |
45 | qemu_put_be32(f, env->cp15.c9_data); | |
46 | qemu_put_be32(f, env->cp15.c13_fcse); | |
47 | qemu_put_be32(f, env->cp15.c13_context); | |
48 | qemu_put_be32(f, env->cp15.c13_tls1); | |
49 | qemu_put_be32(f, env->cp15.c13_tls2); | |
50 | qemu_put_be32(f, env->cp15.c13_tls3); | |
51 | qemu_put_be32(f, env->cp15.c15_cpar); | |
52 | ||
53 | qemu_put_be32(f, env->features); | |
54 | ||
55 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
56 | for (i = 0; i < 16; i++) { | |
57 | CPU_DoubleU u; | |
58 | u.d = env->vfp.regs[i]; | |
59 | qemu_put_be32(f, u.l.upper); | |
60 | qemu_put_be32(f, u.l.lower); | |
61 | } | |
62 | for (i = 0; i < 16; i++) { | |
63 | qemu_put_be32(f, env->vfp.xregs[i]); | |
64 | } | |
65 | ||
66 | /* TODO: Should use proper FPSCR access functions. */ | |
67 | qemu_put_be32(f, env->vfp.vec_len); | |
68 | qemu_put_be32(f, env->vfp.vec_stride); | |
69 | ||
70 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
71 | for (i = 16; i < 32; i++) { | |
72 | CPU_DoubleU u; | |
73 | u.d = env->vfp.regs[i]; | |
74 | qemu_put_be32(f, u.l.upper); | |
75 | qemu_put_be32(f, u.l.lower); | |
76 | } | |
77 | } | |
78 | } | |
79 | ||
80 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
81 | for (i = 0; i < 16; i++) { | |
82 | qemu_put_be64(f, env->iwmmxt.regs[i]); | |
83 | } | |
84 | for (i = 0; i < 16; i++) { | |
85 | qemu_put_be32(f, env->iwmmxt.cregs[i]); | |
86 | } | |
87 | } | |
88 | ||
89 | if (arm_feature(env, ARM_FEATURE_M)) { | |
90 | qemu_put_be32(f, env->v7m.other_sp); | |
91 | qemu_put_be32(f, env->v7m.vecbase); | |
92 | qemu_put_be32(f, env->v7m.basepri); | |
93 | qemu_put_be32(f, env->v7m.control); | |
94 | qemu_put_be32(f, env->v7m.current_sp); | |
95 | qemu_put_be32(f, env->v7m.exception); | |
96 | } | |
ffe47d33 PB |
97 | |
98 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { | |
99 | qemu_put_be32(f, env->teecr); | |
100 | qemu_put_be32(f, env->teehbr); | |
101 | } | |
8dd3dca3 AJ |
102 | } |
103 | ||
104 | int cpu_load(QEMUFile *f, void *opaque, int version_id) | |
105 | { | |
106 | CPUARMState *env = (CPUARMState *)opaque; | |
107 | int i; | |
ffe47d33 | 108 | uint32_t val; |
8dd3dca3 | 109 | |
b3c7724c | 110 | if (version_id != CPU_SAVE_VERSION) |
8dd3dca3 AJ |
111 | return -EINVAL; |
112 | ||
113 | for (i = 0; i < 16; i++) { | |
114 | env->regs[i] = qemu_get_be32(f); | |
115 | } | |
ffe47d33 PB |
116 | val = qemu_get_be32(f); |
117 | /* Avoid mode switch when restoring CPSR. */ | |
118 | env->uncached_cpsr = val & CPSR_M; | |
119 | cpsr_write(env, val, 0xffffffff); | |
8dd3dca3 AJ |
120 | env->spsr = qemu_get_be32(f); |
121 | for (i = 0; i < 6; i++) { | |
122 | env->banked_spsr[i] = qemu_get_be32(f); | |
123 | env->banked_r13[i] = qemu_get_be32(f); | |
124 | env->banked_r14[i] = qemu_get_be32(f); | |
125 | } | |
126 | for (i = 0; i < 5; i++) { | |
127 | env->usr_regs[i] = qemu_get_be32(f); | |
128 | env->fiq_regs[i] = qemu_get_be32(f); | |
129 | } | |
130 | env->cp15.c0_cpuid = qemu_get_be32(f); | |
131 | env->cp15.c0_cachetype = qemu_get_be32(f); | |
ffe47d33 | 132 | env->cp15.c0_cssel = qemu_get_be32(f); |
8dd3dca3 AJ |
133 | env->cp15.c1_sys = qemu_get_be32(f); |
134 | env->cp15.c1_coproc = qemu_get_be32(f); | |
135 | env->cp15.c1_xscaleauxcr = qemu_get_be32(f); | |
136 | env->cp15.c2_base0 = qemu_get_be32(f); | |
137 | env->cp15.c2_base1 = qemu_get_be32(f); | |
ffe47d33 | 138 | env->cp15.c2_control = qemu_get_be32(f); |
8dd3dca3 | 139 | env->cp15.c2_mask = qemu_get_be32(f); |
ffe47d33 | 140 | env->cp15.c2_base_mask = qemu_get_be32(f); |
8dd3dca3 AJ |
141 | env->cp15.c2_data = qemu_get_be32(f); |
142 | env->cp15.c2_insn = qemu_get_be32(f); | |
143 | env->cp15.c3 = qemu_get_be32(f); | |
144 | env->cp15.c5_insn = qemu_get_be32(f); | |
145 | env->cp15.c5_data = qemu_get_be32(f); | |
146 | for (i = 0; i < 8; i++) { | |
147 | env->cp15.c6_region[i] = qemu_get_be32(f); | |
148 | } | |
149 | env->cp15.c6_insn = qemu_get_be32(f); | |
150 | env->cp15.c6_data = qemu_get_be32(f); | |
151 | env->cp15.c9_insn = qemu_get_be32(f); | |
152 | env->cp15.c9_data = qemu_get_be32(f); | |
153 | env->cp15.c13_fcse = qemu_get_be32(f); | |
154 | env->cp15.c13_context = qemu_get_be32(f); | |
155 | env->cp15.c13_tls1 = qemu_get_be32(f); | |
156 | env->cp15.c13_tls2 = qemu_get_be32(f); | |
157 | env->cp15.c13_tls3 = qemu_get_be32(f); | |
158 | env->cp15.c15_cpar = qemu_get_be32(f); | |
159 | ||
160 | env->features = qemu_get_be32(f); | |
161 | ||
162 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
163 | for (i = 0; i < 16; i++) { | |
164 | CPU_DoubleU u; | |
165 | u.l.upper = qemu_get_be32(f); | |
166 | u.l.lower = qemu_get_be32(f); | |
167 | env->vfp.regs[i] = u.d; | |
168 | } | |
169 | for (i = 0; i < 16; i++) { | |
170 | env->vfp.xregs[i] = qemu_get_be32(f); | |
171 | } | |
172 | ||
173 | /* TODO: Should use proper FPSCR access functions. */ | |
174 | env->vfp.vec_len = qemu_get_be32(f); | |
175 | env->vfp.vec_stride = qemu_get_be32(f); | |
176 | ||
177 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
178 | for (i = 0; i < 16; i++) { | |
179 | CPU_DoubleU u; | |
180 | u.l.upper = qemu_get_be32(f); | |
181 | u.l.lower = qemu_get_be32(f); | |
182 | env->vfp.regs[i] = u.d; | |
183 | } | |
184 | } | |
185 | } | |
186 | ||
187 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
188 | for (i = 0; i < 16; i++) { | |
189 | env->iwmmxt.regs[i] = qemu_get_be64(f); | |
190 | } | |
191 | for (i = 0; i < 16; i++) { | |
192 | env->iwmmxt.cregs[i] = qemu_get_be32(f); | |
193 | } | |
194 | } | |
195 | ||
196 | if (arm_feature(env, ARM_FEATURE_M)) { | |
197 | env->v7m.other_sp = qemu_get_be32(f); | |
198 | env->v7m.vecbase = qemu_get_be32(f); | |
199 | env->v7m.basepri = qemu_get_be32(f); | |
200 | env->v7m.control = qemu_get_be32(f); | |
201 | env->v7m.current_sp = qemu_get_be32(f); | |
202 | env->v7m.exception = qemu_get_be32(f); | |
203 | } | |
204 | ||
ffe47d33 PB |
205 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
206 | env->teecr = qemu_get_be32(f); | |
207 | env->teehbr = qemu_get_be32(f); | |
208 | } | |
209 | ||
8dd3dca3 AJ |
210 | return 0; |
211 | } |