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Commit | Line | Data |
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8dd3dca3 AJ |
1 | #include "hw/hw.h" |
2 | #include "hw/boards.h" | |
3 | ||
8dd3dca3 AJ |
4 | void cpu_save(QEMUFile *f, void *opaque) |
5 | { | |
6 | int i; | |
7 | CPUARMState *env = (CPUARMState *)opaque; | |
8 | ||
9 | for (i = 0; i < 16; i++) { | |
10 | qemu_put_be32(f, env->regs[i]); | |
11 | } | |
12 | qemu_put_be32(f, cpsr_read(env)); | |
13 | qemu_put_be32(f, env->spsr); | |
14 | for (i = 0; i < 6; i++) { | |
15 | qemu_put_be32(f, env->banked_spsr[i]); | |
16 | qemu_put_be32(f, env->banked_r13[i]); | |
17 | qemu_put_be32(f, env->banked_r14[i]); | |
18 | } | |
19 | for (i = 0; i < 5; i++) { | |
20 | qemu_put_be32(f, env->usr_regs[i]); | |
21 | qemu_put_be32(f, env->fiq_regs[i]); | |
22 | } | |
23 | qemu_put_be32(f, env->cp15.c0_cpuid); | |
24 | qemu_put_be32(f, env->cp15.c0_cachetype); | |
ffe47d33 | 25 | qemu_put_be32(f, env->cp15.c0_cssel); |
8dd3dca3 AJ |
26 | qemu_put_be32(f, env->cp15.c1_sys); |
27 | qemu_put_be32(f, env->cp15.c1_coproc); | |
28 | qemu_put_be32(f, env->cp15.c1_xscaleauxcr); | |
29 | qemu_put_be32(f, env->cp15.c2_base0); | |
30 | qemu_put_be32(f, env->cp15.c2_base1); | |
ffe47d33 | 31 | qemu_put_be32(f, env->cp15.c2_control); |
8dd3dca3 | 32 | qemu_put_be32(f, env->cp15.c2_mask); |
ffe47d33 | 33 | qemu_put_be32(f, env->cp15.c2_base_mask); |
8dd3dca3 AJ |
34 | qemu_put_be32(f, env->cp15.c2_data); |
35 | qemu_put_be32(f, env->cp15.c2_insn); | |
36 | qemu_put_be32(f, env->cp15.c3); | |
37 | qemu_put_be32(f, env->cp15.c5_insn); | |
38 | qemu_put_be32(f, env->cp15.c5_data); | |
39 | for (i = 0; i < 8; i++) { | |
40 | qemu_put_be32(f, env->cp15.c6_region[i]); | |
41 | } | |
42 | qemu_put_be32(f, env->cp15.c6_insn); | |
43 | qemu_put_be32(f, env->cp15.c6_data); | |
f8bf8606 | 44 | qemu_put_be32(f, env->cp15.c7_par); |
8dd3dca3 AJ |
45 | qemu_put_be32(f, env->cp15.c9_insn); |
46 | qemu_put_be32(f, env->cp15.c9_data); | |
74594c9d PM |
47 | qemu_put_be32(f, env->cp15.c9_pmcr); |
48 | qemu_put_be32(f, env->cp15.c9_pmcnten); | |
49 | qemu_put_be32(f, env->cp15.c9_pmovsr); | |
50 | qemu_put_be32(f, env->cp15.c9_pmxevtyper); | |
51 | qemu_put_be32(f, env->cp15.c9_pmuserenr); | |
52 | qemu_put_be32(f, env->cp15.c9_pminten); | |
8dd3dca3 AJ |
53 | qemu_put_be32(f, env->cp15.c13_fcse); |
54 | qemu_put_be32(f, env->cp15.c13_context); | |
55 | qemu_put_be32(f, env->cp15.c13_tls1); | |
56 | qemu_put_be32(f, env->cp15.c13_tls2); | |
57 | qemu_put_be32(f, env->cp15.c13_tls3); | |
58 | qemu_put_be32(f, env->cp15.c15_cpar); | |
59 | ||
60 | qemu_put_be32(f, env->features); | |
61 | ||
62 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
63 | for (i = 0; i < 16; i++) { | |
64 | CPU_DoubleU u; | |
65 | u.d = env->vfp.regs[i]; | |
66 | qemu_put_be32(f, u.l.upper); | |
67 | qemu_put_be32(f, u.l.lower); | |
68 | } | |
69 | for (i = 0; i < 16; i++) { | |
70 | qemu_put_be32(f, env->vfp.xregs[i]); | |
71 | } | |
72 | ||
73 | /* TODO: Should use proper FPSCR access functions. */ | |
74 | qemu_put_be32(f, env->vfp.vec_len); | |
75 | qemu_put_be32(f, env->vfp.vec_stride); | |
76 | ||
77 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
78 | for (i = 16; i < 32; i++) { | |
79 | CPU_DoubleU u; | |
80 | u.d = env->vfp.regs[i]; | |
81 | qemu_put_be32(f, u.l.upper); | |
82 | qemu_put_be32(f, u.l.lower); | |
83 | } | |
84 | } | |
85 | } | |
86 | ||
87 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
88 | for (i = 0; i < 16; i++) { | |
89 | qemu_put_be64(f, env->iwmmxt.regs[i]); | |
90 | } | |
91 | for (i = 0; i < 16; i++) { | |
92 | qemu_put_be32(f, env->iwmmxt.cregs[i]); | |
93 | } | |
94 | } | |
95 | ||
96 | if (arm_feature(env, ARM_FEATURE_M)) { | |
97 | qemu_put_be32(f, env->v7m.other_sp); | |
98 | qemu_put_be32(f, env->v7m.vecbase); | |
99 | qemu_put_be32(f, env->v7m.basepri); | |
100 | qemu_put_be32(f, env->v7m.control); | |
101 | qemu_put_be32(f, env->v7m.current_sp); | |
102 | qemu_put_be32(f, env->v7m.exception); | |
103 | } | |
ffe47d33 PB |
104 | |
105 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { | |
106 | qemu_put_be32(f, env->teecr); | |
107 | qemu_put_be32(f, env->teehbr); | |
108 | } | |
8dd3dca3 AJ |
109 | } |
110 | ||
111 | int cpu_load(QEMUFile *f, void *opaque, int version_id) | |
112 | { | |
113 | CPUARMState *env = (CPUARMState *)opaque; | |
114 | int i; | |
ffe47d33 | 115 | uint32_t val; |
8dd3dca3 | 116 | |
b3c7724c | 117 | if (version_id != CPU_SAVE_VERSION) |
8dd3dca3 AJ |
118 | return -EINVAL; |
119 | ||
120 | for (i = 0; i < 16; i++) { | |
121 | env->regs[i] = qemu_get_be32(f); | |
122 | } | |
ffe47d33 PB |
123 | val = qemu_get_be32(f); |
124 | /* Avoid mode switch when restoring CPSR. */ | |
125 | env->uncached_cpsr = val & CPSR_M; | |
126 | cpsr_write(env, val, 0xffffffff); | |
8dd3dca3 AJ |
127 | env->spsr = qemu_get_be32(f); |
128 | for (i = 0; i < 6; i++) { | |
129 | env->banked_spsr[i] = qemu_get_be32(f); | |
130 | env->banked_r13[i] = qemu_get_be32(f); | |
131 | env->banked_r14[i] = qemu_get_be32(f); | |
132 | } | |
133 | for (i = 0; i < 5; i++) { | |
134 | env->usr_regs[i] = qemu_get_be32(f); | |
135 | env->fiq_regs[i] = qemu_get_be32(f); | |
136 | } | |
137 | env->cp15.c0_cpuid = qemu_get_be32(f); | |
138 | env->cp15.c0_cachetype = qemu_get_be32(f); | |
ffe47d33 | 139 | env->cp15.c0_cssel = qemu_get_be32(f); |
8dd3dca3 AJ |
140 | env->cp15.c1_sys = qemu_get_be32(f); |
141 | env->cp15.c1_coproc = qemu_get_be32(f); | |
142 | env->cp15.c1_xscaleauxcr = qemu_get_be32(f); | |
143 | env->cp15.c2_base0 = qemu_get_be32(f); | |
144 | env->cp15.c2_base1 = qemu_get_be32(f); | |
ffe47d33 | 145 | env->cp15.c2_control = qemu_get_be32(f); |
8dd3dca3 | 146 | env->cp15.c2_mask = qemu_get_be32(f); |
ffe47d33 | 147 | env->cp15.c2_base_mask = qemu_get_be32(f); |
8dd3dca3 AJ |
148 | env->cp15.c2_data = qemu_get_be32(f); |
149 | env->cp15.c2_insn = qemu_get_be32(f); | |
150 | env->cp15.c3 = qemu_get_be32(f); | |
151 | env->cp15.c5_insn = qemu_get_be32(f); | |
152 | env->cp15.c5_data = qemu_get_be32(f); | |
153 | for (i = 0; i < 8; i++) { | |
154 | env->cp15.c6_region[i] = qemu_get_be32(f); | |
155 | } | |
156 | env->cp15.c6_insn = qemu_get_be32(f); | |
157 | env->cp15.c6_data = qemu_get_be32(f); | |
f8bf8606 | 158 | env->cp15.c7_par = qemu_get_be32(f); |
8dd3dca3 AJ |
159 | env->cp15.c9_insn = qemu_get_be32(f); |
160 | env->cp15.c9_data = qemu_get_be32(f); | |
74594c9d PM |
161 | env->cp15.c9_pmcr = qemu_get_be32(f); |
162 | env->cp15.c9_pmcnten = qemu_get_be32(f); | |
163 | env->cp15.c9_pmovsr = qemu_get_be32(f); | |
164 | env->cp15.c9_pmxevtyper = qemu_get_be32(f); | |
165 | env->cp15.c9_pmuserenr = qemu_get_be32(f); | |
166 | env->cp15.c9_pminten = qemu_get_be32(f); | |
8dd3dca3 AJ |
167 | env->cp15.c13_fcse = qemu_get_be32(f); |
168 | env->cp15.c13_context = qemu_get_be32(f); | |
169 | env->cp15.c13_tls1 = qemu_get_be32(f); | |
170 | env->cp15.c13_tls2 = qemu_get_be32(f); | |
171 | env->cp15.c13_tls3 = qemu_get_be32(f); | |
172 | env->cp15.c15_cpar = qemu_get_be32(f); | |
173 | ||
174 | env->features = qemu_get_be32(f); | |
175 | ||
176 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
177 | for (i = 0; i < 16; i++) { | |
178 | CPU_DoubleU u; | |
179 | u.l.upper = qemu_get_be32(f); | |
180 | u.l.lower = qemu_get_be32(f); | |
181 | env->vfp.regs[i] = u.d; | |
182 | } | |
183 | for (i = 0; i < 16; i++) { | |
184 | env->vfp.xregs[i] = qemu_get_be32(f); | |
185 | } | |
186 | ||
187 | /* TODO: Should use proper FPSCR access functions. */ | |
188 | env->vfp.vec_len = qemu_get_be32(f); | |
189 | env->vfp.vec_stride = qemu_get_be32(f); | |
190 | ||
191 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
192 | for (i = 0; i < 16; i++) { | |
193 | CPU_DoubleU u; | |
194 | u.l.upper = qemu_get_be32(f); | |
195 | u.l.lower = qemu_get_be32(f); | |
196 | env->vfp.regs[i] = u.d; | |
197 | } | |
198 | } | |
199 | } | |
200 | ||
201 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
202 | for (i = 0; i < 16; i++) { | |
203 | env->iwmmxt.regs[i] = qemu_get_be64(f); | |
204 | } | |
205 | for (i = 0; i < 16; i++) { | |
206 | env->iwmmxt.cregs[i] = qemu_get_be32(f); | |
207 | } | |
208 | } | |
209 | ||
210 | if (arm_feature(env, ARM_FEATURE_M)) { | |
211 | env->v7m.other_sp = qemu_get_be32(f); | |
212 | env->v7m.vecbase = qemu_get_be32(f); | |
213 | env->v7m.basepri = qemu_get_be32(f); | |
214 | env->v7m.control = qemu_get_be32(f); | |
215 | env->v7m.current_sp = qemu_get_be32(f); | |
216 | env->v7m.exception = qemu_get_be32(f); | |
217 | } | |
218 | ||
ffe47d33 PB |
219 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
220 | env->teecr = qemu_get_be32(f); | |
221 | env->teehbr = qemu_get_be32(f); | |
222 | } | |
223 | ||
8dd3dca3 AJ |
224 | return 0; |
225 | } |