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b7bcbe95 FB |
1 | /* |
2 | * ARM helper routines | |
5fafdf24 | 3 | * |
9ee6e8bb | 4 | * Copyright (c) 2005-2007 CodeSourcery, LLC |
b7bcbe95 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
b7bcbe95 | 18 | */ |
3e457172 | 19 | #include "cpu.h" |
7b59220e | 20 | #include "helper.h" |
b7bcbe95 | 21 | |
ad69471c PB |
22 | #define SIGNBIT (uint32_t)0x80000000 |
23 | #define SIGNBIT64 ((uint64_t)1 << 63) | |
24 | ||
1ce94f81 | 25 | static void raise_exception(CPUARMState *env, int tt) |
b7bcbe95 FB |
26 | { |
27 | env->exception_index = tt; | |
1162c041 | 28 | cpu_loop_exit(env); |
b7bcbe95 FB |
29 | } |
30 | ||
9ef39277 | 31 | uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, |
8f8e3aa4 | 32 | uint32_t rn, uint32_t maxindex) |
9ee6e8bb PB |
33 | { |
34 | uint32_t val; | |
9ee6e8bb PB |
35 | uint32_t tmp; |
36 | int index; | |
37 | int shift; | |
38 | uint64_t *table; | |
39 | table = (uint64_t *)&env->vfp.regs[rn]; | |
40 | val = 0; | |
9ee6e8bb | 41 | for (shift = 0; shift < 32; shift += 8) { |
8f8e3aa4 PB |
42 | index = (ireg >> shift) & 0xff; |
43 | if (index < maxindex) { | |
3018f259 | 44 | tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; |
9ee6e8bb PB |
45 | val |= tmp << shift; |
46 | } else { | |
8f8e3aa4 | 47 | val |= def & (0xff << shift); |
9ee6e8bb PB |
48 | } |
49 | } | |
8f8e3aa4 | 50 | return val; |
9ee6e8bb PB |
51 | } |
52 | ||
b5ff1b31 FB |
53 | #if !defined(CONFIG_USER_ONLY) |
54 | ||
3e457172 BS |
55 | #include "softmmu_exec.h" |
56 | ||
b5ff1b31 | 57 | #define MMUSUFFIX _mmu |
b5ff1b31 FB |
58 | |
59 | #define SHIFT 0 | |
60 | #include "softmmu_template.h" | |
61 | ||
62 | #define SHIFT 1 | |
63 | #include "softmmu_template.h" | |
64 | ||
65 | #define SHIFT 2 | |
66 | #include "softmmu_template.h" | |
67 | ||
68 | #define SHIFT 3 | |
69 | #include "softmmu_template.h" | |
70 | ||
71 | /* try to fill the TLB and return an exception if error. If retaddr is | |
72 | NULL, it means that the function was called in C code (i.e. not | |
73 | from generated code or from helper.c) */ | |
d31dd73e | 74 | void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 75 | uintptr_t retaddr) |
b5ff1b31 FB |
76 | { |
77 | TranslationBlock *tb; | |
b5ff1b31 FB |
78 | int ret; |
79 | ||
97b348e7 | 80 | ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx); |
551bd27f | 81 | if (unlikely(ret)) { |
b5ff1b31 FB |
82 | if (retaddr) { |
83 | /* now we have a real cpu fault */ | |
20503968 | 84 | tb = tb_find_pc(retaddr); |
b5ff1b31 FB |
85 | if (tb) { |
86 | /* the PC is inside the translated code. It means that we have | |
87 | a virtual CPU fault */ | |
20503968 | 88 | cpu_restore_state(tb, env, retaddr); |
b5ff1b31 FB |
89 | } |
90 | } | |
1ce94f81 | 91 | raise_exception(env, env->exception_index); |
b5ff1b31 | 92 | } |
b5ff1b31 | 93 | } |
b5ff1b31 | 94 | #endif |
1497c961 | 95 | |
9ef39277 | 96 | uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) |
1497c961 PB |
97 | { |
98 | uint32_t res = a + b; | |
99 | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) | |
100 | env->QF = 1; | |
101 | return res; | |
102 | } | |
103 | ||
9ef39277 | 104 | uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b) |
1497c961 PB |
105 | { |
106 | uint32_t res = a + b; | |
107 | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) { | |
108 | env->QF = 1; | |
109 | res = ~(((int32_t)a >> 31) ^ SIGNBIT); | |
110 | } | |
111 | return res; | |
112 | } | |
113 | ||
9ef39277 | 114 | uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b) |
1497c961 PB |
115 | { |
116 | uint32_t res = a - b; | |
117 | if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) { | |
118 | env->QF = 1; | |
119 | res = ~(((int32_t)a >> 31) ^ SIGNBIT); | |
120 | } | |
121 | return res; | |
122 | } | |
123 | ||
9ef39277 | 124 | uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val) |
1497c961 PB |
125 | { |
126 | uint32_t res; | |
127 | if (val >= 0x40000000) { | |
128 | res = ~SIGNBIT; | |
129 | env->QF = 1; | |
130 | } else if (val <= (int32_t)0xc0000000) { | |
131 | res = SIGNBIT; | |
132 | env->QF = 1; | |
133 | } else { | |
134 | res = val << 1; | |
135 | } | |
136 | return res; | |
137 | } | |
138 | ||
9ef39277 | 139 | uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) |
1497c961 PB |
140 | { |
141 | uint32_t res = a + b; | |
142 | if (res < a) { | |
143 | env->QF = 1; | |
144 | res = ~0; | |
145 | } | |
146 | return res; | |
147 | } | |
148 | ||
9ef39277 | 149 | uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) |
1497c961 PB |
150 | { |
151 | uint32_t res = a - b; | |
152 | if (res > a) { | |
153 | env->QF = 1; | |
154 | res = 0; | |
155 | } | |
156 | return res; | |
157 | } | |
158 | ||
6ddbc6e4 | 159 | /* Signed saturation. */ |
9ef39277 | 160 | static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift) |
6ddbc6e4 PB |
161 | { |
162 | int32_t top; | |
163 | uint32_t mask; | |
164 | ||
6ddbc6e4 PB |
165 | top = val >> shift; |
166 | mask = (1u << shift) - 1; | |
167 | if (top > 0) { | |
168 | env->QF = 1; | |
169 | return mask; | |
170 | } else if (top < -1) { | |
171 | env->QF = 1; | |
172 | return ~mask; | |
173 | } | |
174 | return val; | |
175 | } | |
176 | ||
177 | /* Unsigned saturation. */ | |
9ef39277 | 178 | static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift) |
6ddbc6e4 PB |
179 | { |
180 | uint32_t max; | |
181 | ||
6ddbc6e4 PB |
182 | max = (1u << shift) - 1; |
183 | if (val < 0) { | |
184 | env->QF = 1; | |
185 | return 0; | |
186 | } else if (val > max) { | |
187 | env->QF = 1; | |
188 | return max; | |
189 | } | |
190 | return val; | |
191 | } | |
192 | ||
193 | /* Signed saturate. */ | |
9ef39277 | 194 | uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift) |
6ddbc6e4 | 195 | { |
9ef39277 | 196 | return do_ssat(env, x, shift); |
6ddbc6e4 PB |
197 | } |
198 | ||
199 | /* Dual halfword signed saturate. */ | |
9ef39277 | 200 | uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift) |
6ddbc6e4 PB |
201 | { |
202 | uint32_t res; | |
203 | ||
9ef39277 BS |
204 | res = (uint16_t)do_ssat(env, (int16_t)x, shift); |
205 | res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16; | |
6ddbc6e4 PB |
206 | return res; |
207 | } | |
208 | ||
209 | /* Unsigned saturate. */ | |
9ef39277 | 210 | uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift) |
6ddbc6e4 | 211 | { |
9ef39277 | 212 | return do_usat(env, x, shift); |
6ddbc6e4 PB |
213 | } |
214 | ||
215 | /* Dual halfword unsigned saturate. */ | |
9ef39277 | 216 | uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) |
6ddbc6e4 PB |
217 | { |
218 | uint32_t res; | |
219 | ||
9ef39277 BS |
220 | res = (uint16_t)do_usat(env, (int16_t)x, shift); |
221 | res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16; | |
6ddbc6e4 PB |
222 | return res; |
223 | } | |
d9ba4830 | 224 | |
1ce94f81 | 225 | void HELPER(wfi)(CPUARMState *env) |
d9ba4830 PB |
226 | { |
227 | env->exception_index = EXCP_HLT; | |
228 | env->halted = 1; | |
1162c041 | 229 | cpu_loop_exit(env); |
d9ba4830 PB |
230 | } |
231 | ||
1ce94f81 | 232 | void HELPER(exception)(CPUARMState *env, uint32_t excp) |
d9ba4830 PB |
233 | { |
234 | env->exception_index = excp; | |
1162c041 | 235 | cpu_loop_exit(env); |
d9ba4830 PB |
236 | } |
237 | ||
9ef39277 | 238 | uint32_t HELPER(cpsr_read)(CPUARMState *env) |
d9ba4830 PB |
239 | { |
240 | return cpsr_read(env) & ~CPSR_EXEC; | |
241 | } | |
242 | ||
1ce94f81 | 243 | void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) |
d9ba4830 PB |
244 | { |
245 | cpsr_write(env, val, mask); | |
246 | } | |
b0109805 PB |
247 | |
248 | /* Access to user mode registers from privileged modes. */ | |
9ef39277 | 249 | uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) |
b0109805 PB |
250 | { |
251 | uint32_t val; | |
252 | ||
253 | if (regno == 13) { | |
254 | val = env->banked_r13[0]; | |
255 | } else if (regno == 14) { | |
256 | val = env->banked_r14[0]; | |
257 | } else if (regno >= 8 | |
258 | && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { | |
259 | val = env->usr_regs[regno - 8]; | |
260 | } else { | |
261 | val = env->regs[regno]; | |
262 | } | |
263 | return val; | |
264 | } | |
265 | ||
1ce94f81 | 266 | void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) |
b0109805 PB |
267 | { |
268 | if (regno == 13) { | |
269 | env->banked_r13[0] = val; | |
270 | } else if (regno == 14) { | |
271 | env->banked_r14[0] = val; | |
272 | } else if (regno >= 8 | |
273 | && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { | |
274 | env->usr_regs[regno - 8] = val; | |
275 | } else { | |
276 | env->regs[regno] = val; | |
277 | } | |
278 | } | |
4b6a83fb PM |
279 | |
280 | void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value) | |
281 | { | |
282 | const ARMCPRegInfo *ri = rip; | |
283 | int excp = ri->writefn(env, ri, value); | |
284 | if (excp) { | |
1ce94f81 | 285 | raise_exception(env, excp); |
4b6a83fb PM |
286 | } |
287 | } | |
288 | ||
289 | uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip) | |
290 | { | |
291 | const ARMCPRegInfo *ri = rip; | |
292 | uint64_t value; | |
293 | int excp = ri->readfn(env, ri, &value); | |
294 | if (excp) { | |
1ce94f81 | 295 | raise_exception(env, excp); |
4b6a83fb PM |
296 | } |
297 | return value; | |
298 | } | |
299 | ||
300 | void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value) | |
301 | { | |
302 | const ARMCPRegInfo *ri = rip; | |
303 | int excp = ri->writefn(env, ri, value); | |
304 | if (excp) { | |
1ce94f81 | 305 | raise_exception(env, excp); |
4b6a83fb PM |
306 | } |
307 | } | |
308 | ||
309 | uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) | |
310 | { | |
311 | const ARMCPRegInfo *ri = rip; | |
312 | uint64_t value; | |
313 | int excp = ri->readfn(env, ri, &value); | |
314 | if (excp) { | |
1ce94f81 | 315 | raise_exception(env, excp); |
4b6a83fb PM |
316 | } |
317 | return value; | |
318 | } | |
b0109805 | 319 | |
8984bd2e PB |
320 | /* ??? Flag setting arithmetic is awkward because we need to do comparisons. |
321 | The only way to do that in TCG is a conditional branch, which clobbers | |
322 | all our temporaries. For now implement these as helper functions. */ | |
323 | ||
9ef39277 | 324 | uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b) |
8984bd2e PB |
325 | { |
326 | uint32_t result; | |
327 | if (!env->CF) { | |
328 | result = a + b; | |
329 | env->CF = result < a; | |
330 | } else { | |
331 | result = a + b + 1; | |
332 | env->CF = result <= a; | |
333 | } | |
334 | env->VF = (a ^ b ^ -1) & (a ^ result); | |
6fbe23d5 | 335 | env->NF = env->ZF = result; |
8984bd2e PB |
336 | return result; |
337 | } | |
338 | ||
9ef39277 | 339 | uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b) |
8984bd2e PB |
340 | { |
341 | uint32_t result; | |
342 | if (!env->CF) { | |
343 | result = a - b - 1; | |
344 | env->CF = a > b; | |
345 | } else { | |
346 | result = a - b; | |
347 | env->CF = a >= b; | |
348 | } | |
349 | env->VF = (a ^ b) & (a ^ result); | |
6fbe23d5 | 350 | env->NF = env->ZF = result; |
8984bd2e PB |
351 | return result; |
352 | } | |
353 | ||
354 | /* Similarly for variable shift instructions. */ | |
355 | ||
9ef39277 | 356 | uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
8984bd2e PB |
357 | { |
358 | int shift = i & 0xff; | |
359 | if (shift >= 32) { | |
360 | if (shift == 32) | |
361 | env->CF = x & 1; | |
362 | else | |
363 | env->CF = 0; | |
364 | return 0; | |
365 | } else if (shift != 0) { | |
366 | env->CF = (x >> (32 - shift)) & 1; | |
367 | return x << shift; | |
368 | } | |
369 | return x; | |
370 | } | |
371 | ||
9ef39277 | 372 | uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
8984bd2e PB |
373 | { |
374 | int shift = i & 0xff; | |
375 | if (shift >= 32) { | |
376 | if (shift == 32) | |
377 | env->CF = (x >> 31) & 1; | |
378 | else | |
379 | env->CF = 0; | |
380 | return 0; | |
381 | } else if (shift != 0) { | |
382 | env->CF = (x >> (shift - 1)) & 1; | |
383 | return x >> shift; | |
384 | } | |
385 | return x; | |
386 | } | |
387 | ||
9ef39277 | 388 | uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
8984bd2e PB |
389 | { |
390 | int shift = i & 0xff; | |
391 | if (shift >= 32) { | |
392 | env->CF = (x >> 31) & 1; | |
393 | return (int32_t)x >> 31; | |
394 | } else if (shift != 0) { | |
395 | env->CF = (x >> (shift - 1)) & 1; | |
396 | return (int32_t)x >> shift; | |
397 | } | |
398 | return x; | |
399 | } | |
400 | ||
9ef39277 | 401 | uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
8984bd2e PB |
402 | { |
403 | int shift1, shift; | |
404 | shift1 = i & 0xff; | |
405 | shift = shift1 & 0x1f; | |
406 | if (shift == 0) { | |
407 | if (shift1 != 0) | |
408 | env->CF = (x >> 31) & 1; | |
409 | return x; | |
410 | } else { | |
411 | env->CF = (x >> (shift - 1)) & 1; | |
412 | return ((uint32_t)x >> shift) | (x << (32 - shift)); | |
413 | } | |
414 | } |