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target-arm: convert sar, shl and shr helpers to TCG
[qemu.git] / target-arm / op_helper.c
CommitLineData
b7bcbe95
FB
1/*
2 * ARM helper routines
5fafdf24 3 *
9ee6e8bb 4 * Copyright (c) 2005-2007 CodeSourcery, LLC
b7bcbe95
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
b7bcbe95 18 */
3e457172 19#include "cpu.h"
7b59220e 20#include "helper.h"
b7bcbe95 21
ad69471c
PB
22#define SIGNBIT (uint32_t)0x80000000
23#define SIGNBIT64 ((uint64_t)1 << 63)
24
1ce94f81 25static void raise_exception(CPUARMState *env, int tt)
b7bcbe95
FB
26{
27 env->exception_index = tt;
1162c041 28 cpu_loop_exit(env);
b7bcbe95
FB
29}
30
9ef39277 31uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
8f8e3aa4 32 uint32_t rn, uint32_t maxindex)
9ee6e8bb
PB
33{
34 uint32_t val;
9ee6e8bb
PB
35 uint32_t tmp;
36 int index;
37 int shift;
38 uint64_t *table;
39 table = (uint64_t *)&env->vfp.regs[rn];
40 val = 0;
9ee6e8bb 41 for (shift = 0; shift < 32; shift += 8) {
8f8e3aa4
PB
42 index = (ireg >> shift) & 0xff;
43 if (index < maxindex) {
3018f259 44 tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
9ee6e8bb
PB
45 val |= tmp << shift;
46 } else {
8f8e3aa4 47 val |= def & (0xff << shift);
9ee6e8bb
PB
48 }
49 }
8f8e3aa4 50 return val;
9ee6e8bb
PB
51}
52
b5ff1b31
FB
53#if !defined(CONFIG_USER_ONLY)
54
3e457172
BS
55#include "softmmu_exec.h"
56
b5ff1b31 57#define MMUSUFFIX _mmu
b5ff1b31
FB
58
59#define SHIFT 0
60#include "softmmu_template.h"
61
62#define SHIFT 1
63#include "softmmu_template.h"
64
65#define SHIFT 2
66#include "softmmu_template.h"
67
68#define SHIFT 3
69#include "softmmu_template.h"
70
71/* try to fill the TLB and return an exception if error. If retaddr is
72 NULL, it means that the function was called in C code (i.e. not
73 from generated code or from helper.c) */
d31dd73e 74void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
20503968 75 uintptr_t retaddr)
b5ff1b31
FB
76{
77 TranslationBlock *tb;
b5ff1b31
FB
78 int ret;
79
97b348e7 80 ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
551bd27f 81 if (unlikely(ret)) {
b5ff1b31
FB
82 if (retaddr) {
83 /* now we have a real cpu fault */
20503968 84 tb = tb_find_pc(retaddr);
b5ff1b31
FB
85 if (tb) {
86 /* the PC is inside the translated code. It means that we have
87 a virtual CPU fault */
20503968 88 cpu_restore_state(tb, env, retaddr);
b5ff1b31
FB
89 }
90 }
1ce94f81 91 raise_exception(env, env->exception_index);
b5ff1b31 92 }
b5ff1b31 93}
b5ff1b31 94#endif
1497c961 95
b90372ad 96/* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
ad69471c 97 instructions into helper.c */
9ef39277 98uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
1497c961
PB
99{
100 uint32_t res = a + b;
101 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
102 env->QF = 1;
103 return res;
104}
105
9ef39277 106uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
1497c961
PB
107{
108 uint32_t res = a + b;
109 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
110 env->QF = 1;
111 res = ~(((int32_t)a >> 31) ^ SIGNBIT);
112 }
113 return res;
114}
115
9ef39277 116uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
1497c961
PB
117{
118 uint32_t res = a - b;
119 if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
120 env->QF = 1;
121 res = ~(((int32_t)a >> 31) ^ SIGNBIT);
122 }
123 return res;
124}
125
9ef39277 126uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
1497c961
PB
127{
128 uint32_t res;
129 if (val >= 0x40000000) {
130 res = ~SIGNBIT;
131 env->QF = 1;
132 } else if (val <= (int32_t)0xc0000000) {
133 res = SIGNBIT;
134 env->QF = 1;
135 } else {
136 res = val << 1;
137 }
138 return res;
139}
140
9ef39277 141uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
1497c961
PB
142{
143 uint32_t res = a + b;
144 if (res < a) {
145 env->QF = 1;
146 res = ~0;
147 }
148 return res;
149}
150
9ef39277 151uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
1497c961
PB
152{
153 uint32_t res = a - b;
154 if (res > a) {
155 env->QF = 1;
156 res = 0;
157 }
158 return res;
159}
160
6ddbc6e4 161/* Signed saturation. */
9ef39277 162static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
6ddbc6e4
PB
163{
164 int32_t top;
165 uint32_t mask;
166
6ddbc6e4
PB
167 top = val >> shift;
168 mask = (1u << shift) - 1;
169 if (top > 0) {
170 env->QF = 1;
171 return mask;
172 } else if (top < -1) {
173 env->QF = 1;
174 return ~mask;
175 }
176 return val;
177}
178
179/* Unsigned saturation. */
9ef39277 180static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
6ddbc6e4
PB
181{
182 uint32_t max;
183
6ddbc6e4
PB
184 max = (1u << shift) - 1;
185 if (val < 0) {
186 env->QF = 1;
187 return 0;
188 } else if (val > max) {
189 env->QF = 1;
190 return max;
191 }
192 return val;
193}
194
195/* Signed saturate. */
9ef39277 196uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
6ddbc6e4 197{
9ef39277 198 return do_ssat(env, x, shift);
6ddbc6e4
PB
199}
200
201/* Dual halfword signed saturate. */
9ef39277 202uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
6ddbc6e4
PB
203{
204 uint32_t res;
205
9ef39277
BS
206 res = (uint16_t)do_ssat(env, (int16_t)x, shift);
207 res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
6ddbc6e4
PB
208 return res;
209}
210
211/* Unsigned saturate. */
9ef39277 212uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
6ddbc6e4 213{
9ef39277 214 return do_usat(env, x, shift);
6ddbc6e4
PB
215}
216
217/* Dual halfword unsigned saturate. */
9ef39277 218uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
6ddbc6e4
PB
219{
220 uint32_t res;
221
9ef39277
BS
222 res = (uint16_t)do_usat(env, (int16_t)x, shift);
223 res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
6ddbc6e4
PB
224 return res;
225}
d9ba4830 226
1ce94f81 227void HELPER(wfi)(CPUARMState *env)
d9ba4830
PB
228{
229 env->exception_index = EXCP_HLT;
230 env->halted = 1;
1162c041 231 cpu_loop_exit(env);
d9ba4830
PB
232}
233
1ce94f81 234void HELPER(exception)(CPUARMState *env, uint32_t excp)
d9ba4830
PB
235{
236 env->exception_index = excp;
1162c041 237 cpu_loop_exit(env);
d9ba4830
PB
238}
239
9ef39277 240uint32_t HELPER(cpsr_read)(CPUARMState *env)
d9ba4830
PB
241{
242 return cpsr_read(env) & ~CPSR_EXEC;
243}
244
1ce94f81 245void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
d9ba4830
PB
246{
247 cpsr_write(env, val, mask);
248}
b0109805
PB
249
250/* Access to user mode registers from privileged modes. */
9ef39277 251uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
b0109805
PB
252{
253 uint32_t val;
254
255 if (regno == 13) {
256 val = env->banked_r13[0];
257 } else if (regno == 14) {
258 val = env->banked_r14[0];
259 } else if (regno >= 8
260 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
261 val = env->usr_regs[regno - 8];
262 } else {
263 val = env->regs[regno];
264 }
265 return val;
266}
267
1ce94f81 268void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
b0109805
PB
269{
270 if (regno == 13) {
271 env->banked_r13[0] = val;
272 } else if (regno == 14) {
273 env->banked_r14[0] = val;
274 } else if (regno >= 8
275 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
276 env->usr_regs[regno - 8] = val;
277 } else {
278 env->regs[regno] = val;
279 }
280}
4b6a83fb
PM
281
282void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
283{
284 const ARMCPRegInfo *ri = rip;
285 int excp = ri->writefn(env, ri, value);
286 if (excp) {
1ce94f81 287 raise_exception(env, excp);
4b6a83fb
PM
288 }
289}
290
291uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
292{
293 const ARMCPRegInfo *ri = rip;
294 uint64_t value;
295 int excp = ri->readfn(env, ri, &value);
296 if (excp) {
1ce94f81 297 raise_exception(env, excp);
4b6a83fb
PM
298 }
299 return value;
300}
301
302void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
303{
304 const ARMCPRegInfo *ri = rip;
305 int excp = ri->writefn(env, ri, value);
306 if (excp) {
1ce94f81 307 raise_exception(env, excp);
4b6a83fb
PM
308 }
309}
310
311uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
312{
313 const ARMCPRegInfo *ri = rip;
314 uint64_t value;
315 int excp = ri->readfn(env, ri, &value);
316 if (excp) {
1ce94f81 317 raise_exception(env, excp);
4b6a83fb
PM
318 }
319 return value;
320}
b0109805 321
8984bd2e
PB
322/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
323 The only way to do that in TCG is a conditional branch, which clobbers
324 all our temporaries. For now implement these as helper functions. */
325
9ef39277 326uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
8984bd2e
PB
327{
328 uint32_t result;
329 if (!env->CF) {
330 result = a + b;
331 env->CF = result < a;
332 } else {
333 result = a + b + 1;
334 env->CF = result <= a;
335 }
336 env->VF = (a ^ b ^ -1) & (a ^ result);
6fbe23d5 337 env->NF = env->ZF = result;
8984bd2e
PB
338 return result;
339}
340
9ef39277 341uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
8984bd2e
PB
342{
343 uint32_t result;
344 if (!env->CF) {
345 result = a - b - 1;
346 env->CF = a > b;
347 } else {
348 result = a - b;
349 env->CF = a >= b;
350 }
351 env->VF = (a ^ b) & (a ^ result);
6fbe23d5 352 env->NF = env->ZF = result;
8984bd2e
PB
353 return result;
354}
355
356/* Similarly for variable shift instructions. */
357
9ef39277 358uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
8984bd2e
PB
359{
360 int shift = i & 0xff;
361 if (shift >= 32) {
362 if (shift == 32)
363 env->CF = x & 1;
364 else
365 env->CF = 0;
366 return 0;
367 } else if (shift != 0) {
368 env->CF = (x >> (32 - shift)) & 1;
369 return x << shift;
370 }
371 return x;
372}
373
9ef39277 374uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
8984bd2e
PB
375{
376 int shift = i & 0xff;
377 if (shift >= 32) {
378 if (shift == 32)
379 env->CF = (x >> 31) & 1;
380 else
381 env->CF = 0;
382 return 0;
383 } else if (shift != 0) {
384 env->CF = (x >> (shift - 1)) & 1;
385 return x >> shift;
386 }
387 return x;
388}
389
9ef39277 390uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
8984bd2e
PB
391{
392 int shift = i & 0xff;
393 if (shift >= 32) {
394 env->CF = (x >> 31) & 1;
395 return (int32_t)x >> 31;
396 } else if (shift != 0) {
397 env->CF = (x >> (shift - 1)) & 1;
398 return (int32_t)x >> shift;
399 }
400 return x;
401}
402
9ef39277 403uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
8984bd2e
PB
404{
405 int shift1, shift;
406 shift1 = i & 0xff;
407 shift = shift1 & 0x1f;
408 if (shift == 0) {
409 if (shift1 != 0)
410 env->CF = (x >> 31) & 1;
411 return x;
412 } else {
413 env->CF = (x >> (shift - 1)) & 1;
414 return ((uint32_t)x >> shift) | (x << (32 - shift));
415 }
416}