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Speedup 'tb_find_slow' by using the same heuristic as during memory page lookup
[qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
9ee6e8bb
PB		 37#define ENABLE_ARCH_5J 0
38#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 42
86753403 43#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 44
2c0262af
FB		 45/* internal defines */
46typedef struct DisasContext {
0fa85d43 47 target_ulong pc;
2c0262af 48 int is_jmp;
e50e6a20
FB		 49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
9ee6e8bb
PB		 53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
2c0262af 56 struct TranslationBlock *tb;
8aaca4c0 57 int singlestep_enabled;
5899f386 58 int thumb;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
2c0262af
FB		 62} DisasContext;
63
b5ff1b31
FB		 64#if defined(CONFIG_USER_ONLY)
65#define IS_USER(s) 1
66#else
67#define IS_USER(s) (s->user)
68#endif
69
9ee6e8bb
PB		 70/* These instructions trap after executing, so defer them until after the
71 conditional executions state has been updated. */
72#define DISAS_WFI 4
73#define DISAS_SWI 5
2c0262af 74
a7812ae4 75static TCGv_ptr cpu_env;
ad69471c 76/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 77static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 78static TCGv_i32 cpu_R[16];
426f5abc
PB		 79static TCGv_i32 cpu_exclusive_addr;
80static TCGv_i32 cpu_exclusive_val;
81static TCGv_i32 cpu_exclusive_high;
82#ifdef CONFIG_USER_ONLY
83static TCGv_i32 cpu_exclusive_test;
84static TCGv_i32 cpu_exclusive_info;
85#endif
ad69471c 86
b26eefb6 87/* FIXME: These should be removed. */
a7812ae4
PB		 88static TCGv cpu_F0s, cpu_F1s;
89static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 90
2e70f6ef
PB		 91#include "gen-icount.h"
92
155c3eac
FN		 93static const char *regnames[] =
94 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
95 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
96
b26eefb6
PB		 97/* initialize TCG globals. */
98void arm_translate_init(void)
99{
155c3eac
FN		 100 int i;
101
a7812ae4
PB		 102 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
103
155c3eac
FN		 104 for (i = 0; i < 16; i++) {
105 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
106 offsetof(CPUState, regs[i]),
107 regnames[i]);
108 }
426f5abc
PB		 109 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUState, exclusive_addr), "exclusive_addr");
111 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
112 offsetof(CPUState, exclusive_val), "exclusive_val");
113 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUState, exclusive_high), "exclusive_high");
115#ifdef CONFIG_USER_ONLY
116 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_test), "exclusive_test");
118 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_info), "exclusive_info");
120#endif
155c3eac 121
a7812ae4
PB		 122#define GEN_HELPER 2
123#include "helpers.h"
b26eefb6
PB		 124}
125
b26eefb6 126static int num_temps;
b26eefb6
PB		 127
128/* Allocate a temporary variable. */
a7812ae4 129static TCGv_i32 new_tmp(void)
b26eefb6 130{
12edd4f2
FN		 131 num_temps++;
132 return tcg_temp_new_i32();
b26eefb6
PB		 133}
134
135/* Release a temporary variable. */
136static void dead_tmp(TCGv tmp)
137{
12edd4f2 138 tcg_temp_free(tmp);
b26eefb6 139 num_temps--;
b26eefb6
PB		 140}
141
d9ba4830
PB		 142static inline TCGv load_cpu_offset(int offset)
143{
144 TCGv tmp = new_tmp();
145 tcg_gen_ld_i32(tmp, cpu_env, offset);
146 return tmp;
147}
148
149#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
150
151static inline void store_cpu_offset(TCGv var, int offset)
152{
153 tcg_gen_st_i32(var, cpu_env, offset);
154 dead_tmp(var);
155}
156
157#define store_cpu_field(var, name) \
158 store_cpu_offset(var, offsetof(CPUState, name))
159
b26eefb6
PB		 160/* Set a variable to the value of a CPU register. */
161static void load_reg_var(DisasContext *s, TCGv var, int reg)
162{
163 if (reg == 15) {
164 uint32_t addr;
165 /* normaly, since we updated PC, we need only to add one insn */
166 if (s->thumb)
167 addr = (long)s->pc + 2;
168 else
169 addr = (long)s->pc + 4;
170 tcg_gen_movi_i32(var, addr);
171 } else {
155c3eac 172 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 173 }
174}
175
176/* Create a new temporary and set it to the value of a CPU register. */
177static inline TCGv load_reg(DisasContext *s, int reg)
178{
179 TCGv tmp = new_tmp();
180 load_reg_var(s, tmp, reg);
181 return tmp;
182}
183
184/* Set a CPU register. The source must be a temporary and will be
185 marked as dead. */
186static void store_reg(DisasContext *s, int reg, TCGv var)
187{
188 if (reg == 15) {
189 tcg_gen_andi_i32(var, var, ~1);
190 s->is_jmp = DISAS_JUMP;
191 }
155c3eac 192 tcg_gen_mov_i32(cpu_R[reg], var);
b26eefb6
PB		 193 dead_tmp(var);
194}
195
b26eefb6 196/* Value extensions. */
86831435
PB		 197#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
198#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 199#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
200#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
201
1497c961
PB		 202#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
203#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 204
b26eefb6 205
b75263d6
JR		 206static inline void gen_set_cpsr(TCGv var, uint32_t mask)
207{
208 TCGv tmp_mask = tcg_const_i32(mask);
209 gen_helper_cpsr_write(var, tmp_mask);
210 tcg_temp_free_i32(tmp_mask);
211}
d9ba4830
PB		 212/* Set NZCV flags from the high 4 bits of var. */
213#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
214
215static void gen_exception(int excp)
216{
217 TCGv tmp = new_tmp();
218 tcg_gen_movi_i32(tmp, excp);
219 gen_helper_exception(tmp);
220 dead_tmp(tmp);
221}
222
3670669c
PB		 223static void gen_smul_dual(TCGv a, TCGv b)
224{
225 TCGv tmp1 = new_tmp();
226 TCGv tmp2 = new_tmp();
22478e79
AZ		 227 tcg_gen_ext16s_i32(tmp1, a);
228 tcg_gen_ext16s_i32(tmp2, b);
3670669c
PB		 229 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
230 dead_tmp(tmp2);
231 tcg_gen_sari_i32(a, a, 16);
232 tcg_gen_sari_i32(b, b, 16);
233 tcg_gen_mul_i32(b, b, a);
234 tcg_gen_mov_i32(a, tmp1);
235 dead_tmp(tmp1);
236}
237
238/* Byteswap each halfword. */
239static void gen_rev16(TCGv var)
240{
241 TCGv tmp = new_tmp();
242 tcg_gen_shri_i32(tmp, var, 8);
243 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
244 tcg_gen_shli_i32(var, var, 8);
245 tcg_gen_andi_i32(var, var, 0xff00ff00);
246 tcg_gen_or_i32(var, var, tmp);
247 dead_tmp(tmp);
248}
249
250/* Byteswap low halfword and sign extend. */
251static void gen_revsh(TCGv var)
252{
253 TCGv tmp = new_tmp();
254 tcg_gen_shri_i32(tmp, var, 8);
255 tcg_gen_andi_i32(tmp, tmp, 0x00ff);
256 tcg_gen_shli_i32(var, var, 8);
257 tcg_gen_ext8s_i32(var, var);
258 tcg_gen_or_i32(var, var, tmp);
259 dead_tmp(tmp);
260}
261
262/* Unsigned bitfield extract. */
263static void gen_ubfx(TCGv var, int shift, uint32_t mask)
264{
265 if (shift)
266 tcg_gen_shri_i32(var, var, shift);
267 tcg_gen_andi_i32(var, var, mask);
268}
269
270/* Signed bitfield extract. */
271static void gen_sbfx(TCGv var, int shift, int width)
272{
273 uint32_t signbit;
274
275 if (shift)
276 tcg_gen_sari_i32(var, var, shift);
277 if (shift + width < 32) {
278 signbit = 1u << (width - 1);
279 tcg_gen_andi_i32(var, var, (1u << width) - 1);
280 tcg_gen_xori_i32(var, var, signbit);
281 tcg_gen_subi_i32(var, var, signbit);
282 }
283}
284
285/* Bitfield insertion. Insert val into base. Clobbers base and val. */
286static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
287{
3670669c 288 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 289 tcg_gen_shli_i32(val, val, shift);
290 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 291 tcg_gen_or_i32(dest, base, val);
292}
293
d9ba4830
PB		 294/* Round the top 32 bits of a 64-bit value. */
295static void gen_roundqd(TCGv a, TCGv b)
3670669c 296{
d9ba4830
PB		 297 tcg_gen_shri_i32(a, a, 31);
298 tcg_gen_add_i32(a, a, b);
3670669c
PB		 299}
300
8f01245e
PB		 301/* FIXME: Most targets have native widening multiplication.
302 It would be good to use that instead of a full wide multiply. */
5e3f878a 303/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 304static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 305{
a7812ae4
PB		 306 TCGv_i64 tmp1 = tcg_temp_new_i64();
307 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 308
309 tcg_gen_extu_i32_i64(tmp1, a);
310 dead_tmp(a);
311 tcg_gen_extu_i32_i64(tmp2, b);
312 dead_tmp(b);
313 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 314 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 315 return tmp1;
316}
317
a7812ae4 318static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 319{
a7812ae4
PB		 320 TCGv_i64 tmp1 = tcg_temp_new_i64();
321 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 322
323 tcg_gen_ext_i32_i64(tmp1, a);
324 dead_tmp(a);
325 tcg_gen_ext_i32_i64(tmp2, b);
326 dead_tmp(b);
327 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 328 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 329 return tmp1;
330}
331
8f01245e 332/* Signed 32x32->64 multiply. */
d9ba4830 333static void gen_imull(TCGv a, TCGv b)
8f01245e 334{
a7812ae4
PB		 335 TCGv_i64 tmp1 = tcg_temp_new_i64();
336 TCGv_i64 tmp2 = tcg_temp_new_i64();
8f01245e 337
d9ba4830
PB		 338 tcg_gen_ext_i32_i64(tmp1, a);
339 tcg_gen_ext_i32_i64(tmp2, b);
8f01245e 340 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 341 tcg_temp_free_i64(tmp2);
d9ba4830 342 tcg_gen_trunc_i64_i32(a, tmp1);
8f01245e 343 tcg_gen_shri_i64(tmp1, tmp1, 32);
d9ba4830 344 tcg_gen_trunc_i64_i32(b, tmp1);
b75263d6 345 tcg_temp_free_i64(tmp1);
d9ba4830 346}
d9ba4830 347
8f01245e
PB		 348/* Swap low and high halfwords. */
349static void gen_swap_half(TCGv var)
350{
351 TCGv tmp = new_tmp();
352 tcg_gen_shri_i32(tmp, var, 16);
353 tcg_gen_shli_i32(var, var, 16);
354 tcg_gen_or_i32(var, var, tmp);
3670669c 355 dead_tmp(tmp);
8f01245e
PB		 356}
357
b26eefb6
PB		 358/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
359 tmp = (t0 ^ t1) & 0x8000;
360 t0 &= ~0x8000;
361 t1 &= ~0x8000;
362 t0 = (t0 + t1) ^ tmp;
363 */
364
365static void gen_add16(TCGv t0, TCGv t1)
366{
367 TCGv tmp = new_tmp();
368 tcg_gen_xor_i32(tmp, t0, t1);
369 tcg_gen_andi_i32(tmp, tmp, 0x8000);
370 tcg_gen_andi_i32(t0, t0, ~0x8000);
371 tcg_gen_andi_i32(t1, t1, ~0x8000);
372 tcg_gen_add_i32(t0, t0, t1);
373 tcg_gen_xor_i32(t0, t0, tmp);
374 dead_tmp(tmp);
375 dead_tmp(t1);
376}
377
9a119ff6
PB		 378#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
379
b26eefb6
PB		 380/* Set CF to the top bit of var. */
381static void gen_set_CF_bit31(TCGv var)
382{
383 TCGv tmp = new_tmp();
384 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 385 gen_set_CF(tmp);
b26eefb6
PB		 386 dead_tmp(tmp);
387}
388
389/* Set N and Z flags from var. */
390static inline void gen_logic_CC(TCGv var)
391{
6fbe23d5
PB		 392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 394}
395
396/* T0 += T1 + CF. */
396e467c 397static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 398{
d9ba4830 399 TCGv tmp;
396e467c 400 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 401 tmp = load_cpu_field(CF);
396e467c 402 tcg_gen_add_i32(t0, t0, tmp);
b26eefb6
PB		 403 dead_tmp(tmp);
404}
405
e9bb4aa9
JR		 406/* dest = T0 + T1 + CF. */
407static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
408{
409 TCGv tmp;
410 tcg_gen_add_i32(dest, t0, t1);
411 tmp = load_cpu_field(CF);
412 tcg_gen_add_i32(dest, dest, tmp);
413 dead_tmp(tmp);
414}
415
3670669c
PB		 416/* dest = T0 - T1 + CF - 1. */
417static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
418{
d9ba4830 419 TCGv tmp;
3670669c 420 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 421 tmp = load_cpu_field(CF);
3670669c
PB		 422 tcg_gen_add_i32(dest, dest, tmp);
423 tcg_gen_subi_i32(dest, dest, 1);
424 dead_tmp(tmp);
425}
426
ad69471c
PB		 427/* FIXME: Implement this natively. */
428#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
429
9a119ff6 430static void shifter_out_im(TCGv var, int shift)
b26eefb6 431{
9a119ff6
PB		 432 TCGv tmp = new_tmp();
433 if (shift == 0) {
434 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 435 } else {
9a119ff6 436 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 437 if (shift != 31)
9a119ff6
PB		 438 tcg_gen_andi_i32(tmp, tmp, 1);
439 }
440 gen_set_CF(tmp);
441 dead_tmp(tmp);
442}
b26eefb6 443
9a119ff6
PB		 444/* Shift by immediate. Includes special handling for shift == 0. */
445static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
446{
447 switch (shiftop) {
448 case 0: /* LSL */
449 if (shift != 0) {
450 if (flags)
451 shifter_out_im(var, 32 - shift);
452 tcg_gen_shli_i32(var, var, shift);
453 }
454 break;
455 case 1: /* LSR */
456 if (shift == 0) {
457 if (flags) {
458 tcg_gen_shri_i32(var, var, 31);
459 gen_set_CF(var);
460 }
461 tcg_gen_movi_i32(var, 0);
462 } else {
463 if (flags)
464 shifter_out_im(var, shift - 1);
465 tcg_gen_shri_i32(var, var, shift);
466 }
467 break;
468 case 2: /* ASR */
469 if (shift == 0)
470 shift = 32;
471 if (flags)
472 shifter_out_im(var, shift - 1);
473 if (shift == 32)
474 shift = 31;
475 tcg_gen_sari_i32(var, var, shift);
476 break;
477 case 3: /* ROR/RRX */
478 if (shift != 0) {
479 if (flags)
480 shifter_out_im(var, shift - 1);
f669df27 481 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 482 } else {
d9ba4830 483 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 484 if (flags)
485 shifter_out_im(var, 0);
486 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 487 tcg_gen_shli_i32(tmp, tmp, 31);
488 tcg_gen_or_i32(var, var, tmp);
489 dead_tmp(tmp);
b26eefb6
PB		 490 }
491 }
492};
493
8984bd2e
PB		 494static inline void gen_arm_shift_reg(TCGv var, int shiftop,
495 TCGv shift, int flags)
496{
497 if (flags) {
498 switch (shiftop) {
499 case 0: gen_helper_shl_cc(var, var, shift); break;
500 case 1: gen_helper_shr_cc(var, var, shift); break;
501 case 2: gen_helper_sar_cc(var, var, shift); break;
502 case 3: gen_helper_ror_cc(var, var, shift); break;
503 }
504 } else {
505 switch (shiftop) {
506 case 0: gen_helper_shl(var, var, shift); break;
507 case 1: gen_helper_shr(var, var, shift); break;
508 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 509 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
510 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 511 }
512 }
513 dead_tmp(shift);
514}
515
6ddbc6e4
PB		 516#define PAS_OP(pfx) \
517 switch (op2) { \
518 case 0: gen_pas_helper(glue(pfx,add16)); break; \
519 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
520 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
521 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
522 case 4: gen_pas_helper(glue(pfx,add8)); break; \
523 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
524 }
d9ba4830 525static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 526{
a7812ae4 527 TCGv_ptr tmp;
6ddbc6e4
PB		 528
529 switch (op1) {
530#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
531 case 1:
a7812ae4 532 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(s)
b75263d6 535 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 536 break;
537 case 5:
a7812ae4 538 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(u)
b75263d6 541 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 542 break;
543#undef gen_pas_helper
544#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
545 case 2:
546 PAS_OP(q);
547 break;
548 case 3:
549 PAS_OP(sh);
550 break;
551 case 6:
552 PAS_OP(uq);
553 break;
554 case 7:
555 PAS_OP(uh);
556 break;
557#undef gen_pas_helper
558 }
559}
9ee6e8bb
PB		 560#undef PAS_OP
561
6ddbc6e4
PB		 562/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
563#define PAS_OP(pfx) \
ed89a2f1 564 switch (op1) { \
6ddbc6e4
PB		 565 case 0: gen_pas_helper(glue(pfx,add8)); break; \
566 case 1: gen_pas_helper(glue(pfx,add16)); break; \
567 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
568 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
569 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
570 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
571 }
d9ba4830 572static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 573{
a7812ae4 574 TCGv_ptr tmp;
6ddbc6e4 575
ed89a2f1 576 switch (op2) {
6ddbc6e4
PB		 577#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
578 case 0:
a7812ae4 579 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(s)
b75263d6 582 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 583 break;
584 case 4:
a7812ae4 585 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(u)
b75263d6 588 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 589 break;
590#undef gen_pas_helper
591#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
592 case 1:
593 PAS_OP(q);
594 break;
595 case 2:
596 PAS_OP(sh);
597 break;
598 case 5:
599 PAS_OP(uq);
600 break;
601 case 6:
602 PAS_OP(uh);
603 break;
604#undef gen_pas_helper
605 }
606}
9ee6e8bb
PB		 607#undef PAS_OP
608
d9ba4830
PB		 609static void gen_test_cc(int cc, int label)
610{
611 TCGv tmp;
612 TCGv tmp2;
d9ba4830
PB		 613 int inv;
614
d9ba4830
PB		 615 switch (cc) {
616 case 0: /* eq: Z */
6fbe23d5 617 tmp = load_cpu_field(ZF);
cb63669a 618 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 619 break;
620 case 1: /* ne: !Z */
6fbe23d5 621 tmp = load_cpu_field(ZF);
cb63669a 622 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 623 break;
624 case 2: /* cs: C */
625 tmp = load_cpu_field(CF);
cb63669a 626 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 627 break;
628 case 3: /* cc: !C */
629 tmp = load_cpu_field(CF);
cb63669a 630 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 631 break;
632 case 4: /* mi: N */
6fbe23d5 633 tmp = load_cpu_field(NF);
cb63669a 634 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 635 break;
636 case 5: /* pl: !N */
6fbe23d5 637 tmp = load_cpu_field(NF);
cb63669a 638 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 639 break;
640 case 6: /* vs: V */
641 tmp = load_cpu_field(VF);
cb63669a 642 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 643 break;
644 case 7: /* vc: !V */
645 tmp = load_cpu_field(VF);
cb63669a 646 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 647 break;
648 case 8: /* hi: C && !Z */
649 inv = gen_new_label();
650 tmp = load_cpu_field(CF);
cb63669a 651 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830 652 dead_tmp(tmp);
6fbe23d5 653 tmp = load_cpu_field(ZF);
cb63669a 654 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 655 gen_set_label(inv);
656 break;
657 case 9: /* ls: !C || Z */
658 tmp = load_cpu_field(CF);
cb63669a 659 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830 660 dead_tmp(tmp);
6fbe23d5 661 tmp = load_cpu_field(ZF);
cb63669a 662 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 663 break;
664 case 10: /* ge: N == V -> N ^ V == 0 */
665 tmp = load_cpu_field(VF);
6fbe23d5 666 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 667 tcg_gen_xor_i32(tmp, tmp, tmp2);
668 dead_tmp(tmp2);
cb63669a 669 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 670 break;
671 case 11: /* lt: N != V -> N ^ V != 0 */
672 tmp = load_cpu_field(VF);
6fbe23d5 673 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 674 tcg_gen_xor_i32(tmp, tmp, tmp2);
675 dead_tmp(tmp2);
cb63669a 676 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 677 break;
678 case 12: /* gt: !Z && N == V */
679 inv = gen_new_label();
6fbe23d5 680 tmp = load_cpu_field(ZF);
cb63669a 681 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830
PB		 682 dead_tmp(tmp);
683 tmp = load_cpu_field(VF);
6fbe23d5 684 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 685 tcg_gen_xor_i32(tmp, tmp, tmp2);
686 dead_tmp(tmp2);
cb63669a 687 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 688 gen_set_label(inv);
689 break;
690 case 13: /* le: Z || N != V */
6fbe23d5 691 tmp = load_cpu_field(ZF);
cb63669a 692 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 693 dead_tmp(tmp);
694 tmp = load_cpu_field(VF);
6fbe23d5 695 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 696 tcg_gen_xor_i32(tmp, tmp, tmp2);
697 dead_tmp(tmp2);
cb63669a 698 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 699 break;
700 default:
701 fprintf(stderr, "Bad condition code 0x%x\n", cc);
702 abort();
703 }
704 dead_tmp(tmp);
705}
2c0262af 706
b1d8e52e 707static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 708 1, /* and */
709 1, /* xor */
710 0, /* sub */
711 0, /* rsb */
712 0, /* add */
713 0, /* adc */
714 0, /* sbc */
715 0, /* rsc */
716 1, /* andl */
717 1, /* xorl */
718 0, /* cmp */
719 0, /* cmn */
720 1, /* orr */
721 1, /* mov */
722 1, /* bic */
723 1, /* mvn */
724};
3b46e624 725
d9ba4830
PB		 726/* Set PC and Thumb state from an immediate address. */
727static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 728{
b26eefb6 729 TCGv tmp;
99c475ab 730
b26eefb6 731 s->is_jmp = DISAS_UPDATE;
d9ba4830 732 if (s->thumb != (addr & 1)) {
155c3eac 733 tmp = new_tmp();
d9ba4830
PB		 734 tcg_gen_movi_i32(tmp, addr & 1);
735 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
155c3eac 736 dead_tmp(tmp);
d9ba4830 737 }
155c3eac 738 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 739}
740
741/* Set PC and Thumb state from var. var is marked as dead. */
742static inline void gen_bx(DisasContext *s, TCGv var)
743{
d9ba4830 744 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 745 tcg_gen_andi_i32(cpu_R[15], var, ~1);
746 tcg_gen_andi_i32(var, var, 1);
747 store_cpu_field(var, thumb);
d9ba4830
PB		 748}
749
21aeb343
JR		 750/* Variant of store_reg which uses branch&exchange logic when storing
751 to r15 in ARM architecture v7 and above. The source must be a temporary
752 and will be marked as dead. */
753static inline void store_reg_bx(CPUState *env, DisasContext *s,
754 int reg, TCGv var)
755{
756 if (reg == 15 && ENABLE_ARCH_7) {
757 gen_bx(s, var);
758 } else {
759 store_reg(s, reg, var);
760 }
761}
762
b0109805
PB		 763static inline TCGv gen_ld8s(TCGv addr, int index)
764{
765 TCGv tmp = new_tmp();
766 tcg_gen_qemu_ld8s(tmp, addr, index);
767 return tmp;
768}
769static inline TCGv gen_ld8u(TCGv addr, int index)
770{
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8u(tmp, addr, index);
773 return tmp;
774}
775static inline TCGv gen_ld16s(TCGv addr, int index)
776{
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld16s(tmp, addr, index);
779 return tmp;
780}
781static inline TCGv gen_ld16u(TCGv addr, int index)
782{
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16u(tmp, addr, index);
785 return tmp;
786}
787static inline TCGv gen_ld32(TCGv addr, int index)
788{
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld32u(tmp, addr, index);
791 return tmp;
792}
84496233
JR		 793static inline TCGv_i64 gen_ld64(TCGv addr, int index)
794{
795 TCGv_i64 tmp = tcg_temp_new_i64();
796 tcg_gen_qemu_ld64(tmp, addr, index);
797 return tmp;
798}
b0109805
PB		 799static inline void gen_st8(TCGv val, TCGv addr, int index)
800{
801 tcg_gen_qemu_st8(val, addr, index);
802 dead_tmp(val);
803}
804static inline void gen_st16(TCGv val, TCGv addr, int index)
805{
806 tcg_gen_qemu_st16(val, addr, index);
807 dead_tmp(val);
808}
809static inline void gen_st32(TCGv val, TCGv addr, int index)
810{
811 tcg_gen_qemu_st32(val, addr, index);
812 dead_tmp(val);
813}
84496233
JR		 814static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
815{
816 tcg_gen_qemu_st64(val, addr, index);
817 tcg_temp_free_i64(val);
818}
b5ff1b31 819
5e3f878a
PB		 820static inline void gen_set_pc_im(uint32_t val)
821{
155c3eac 822 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 823}
824
b5ff1b31
FB		 825/* Force a TB lookup after an instruction that changes the CPU state. */
826static inline void gen_lookup_tb(DisasContext *s)
827{
a6445c52 828 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 829 s->is_jmp = DISAS_UPDATE;
830}
831
b0109805
PB		 832static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
833 TCGv var)
2c0262af 834{
1e8d4eec 835 int val, rm, shift, shiftop;
b26eefb6 836 TCGv offset;
2c0262af
FB		 837
838 if (!(insn & (1 << 25))) {
839 /* immediate */
840 val = insn & 0xfff;
841 if (!(insn & (1 << 23)))
842 val = -val;
537730b9 843 if (val != 0)
b0109805 844 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 845 } else {
846 /* shift/register */
847 rm = (insn) & 0xf;
848 shift = (insn >> 7) & 0x1f;
1e8d4eec 849 shiftop = (insn >> 5) & 3;
b26eefb6 850 offset = load_reg(s, rm);
9a119ff6 851 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 852 if (!(insn & (1 << 23)))
b0109805 853 tcg_gen_sub_i32(var, var, offset);
2c0262af 854 else
b0109805 855 tcg_gen_add_i32(var, var, offset);
b26eefb6 856 dead_tmp(offset);
2c0262af
FB		 857 }
858}
859
191f9a93 860static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 861 int extra, TCGv var)
2c0262af
FB		 862{
863 int val, rm;
b26eefb6 864 TCGv offset;
3b46e624 865
2c0262af
FB		 866 if (insn & (1 << 22)) {
867 /* immediate */
868 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
869 if (!(insn & (1 << 23)))
870 val = -val;
18acad92 871 val += extra;
537730b9 872 if (val != 0)
b0109805 873 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 874 } else {
875 /* register */
191f9a93 876 if (extra)
b0109805 877 tcg_gen_addi_i32(var, var, extra);
2c0262af 878 rm = (insn) & 0xf;
b26eefb6 879 offset = load_reg(s, rm);
2c0262af 880 if (!(insn & (1 << 23)))
b0109805 881 tcg_gen_sub_i32(var, var, offset);
2c0262af 882 else
b0109805 883 tcg_gen_add_i32(var, var, offset);
b26eefb6 884 dead_tmp(offset);
2c0262af
FB		 885 }
886}
887
4373f3ce
PB		 888#define VFP_OP2(name) \
889static inline void gen_vfp_##name(int dp) \
890{ \
891 if (dp) \
892 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
893 else \
894 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 895}
896
4373f3ce
PB		 897VFP_OP2(add)
898VFP_OP2(sub)
899VFP_OP2(mul)
900VFP_OP2(div)
901
902#undef VFP_OP2
903
904static inline void gen_vfp_abs(int dp)
905{
906 if (dp)
907 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
908 else
909 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
910}
911
912static inline void gen_vfp_neg(int dp)
913{
914 if (dp)
915 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
918}
919
920static inline void gen_vfp_sqrt(int dp)
921{
922 if (dp)
923 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
924 else
925 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
926}
927
928static inline void gen_vfp_cmp(int dp)
929{
930 if (dp)
931 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
932 else
933 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
934}
935
936static inline void gen_vfp_cmpe(int dp)
937{
938 if (dp)
939 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
942}
943
944static inline void gen_vfp_F1_ld0(int dp)
945{
946 if (dp)
5b340b51 947 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 948 else
5b340b51 949 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 950}
951
952static inline void gen_vfp_uito(int dp)
953{
954 if (dp)
955 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
956 else
957 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
958}
959
960static inline void gen_vfp_sito(int dp)
961{
962 if (dp)
66230e0d 963 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 964 else
66230e0d 965 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 966}
967
968static inline void gen_vfp_toui(int dp)
969{
970 if (dp)
971 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
972 else
973 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
974}
975
976static inline void gen_vfp_touiz(int dp)
977{
978 if (dp)
979 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
982}
983
984static inline void gen_vfp_tosi(int dp)
985{
986 if (dp)
987 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
990}
991
992static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 993{
994 if (dp)
4373f3ce 995 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 996 else
4373f3ce
PB		 997 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
998}
999
1000#define VFP_GEN_FIX(name) \
1001static inline void gen_vfp_##name(int dp, int shift) \
1002{ \
b75263d6 1003 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1004 if (dp) \
b75263d6 1005 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1006 else \
b75263d6
JR		 1007 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1008 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1009}
4373f3ce
PB		 1010VFP_GEN_FIX(tosh)
1011VFP_GEN_FIX(tosl)
1012VFP_GEN_FIX(touh)
1013VFP_GEN_FIX(toul)
1014VFP_GEN_FIX(shto)
1015VFP_GEN_FIX(slto)
1016VFP_GEN_FIX(uhto)
1017VFP_GEN_FIX(ulto)
1018#undef VFP_GEN_FIX
9ee6e8bb 1019
312eea9f 1020static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1021{
1022 if (dp)
312eea9f 1023 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1024 else
312eea9f 1025 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1026}
1027
312eea9f 1028static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1029{
1030 if (dp)
312eea9f 1031 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1032 else
312eea9f 1033 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1034}
1035
8e96005d
FB		 1036static inline long
1037vfp_reg_offset (int dp, int reg)
1038{
1039 if (dp)
1040 return offsetof(CPUARMState, vfp.regs[reg]);
1041 else if (reg & 1) {
1042 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1043 + offsetof(CPU_DoubleU, l.upper);
1044 } else {
1045 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1046 + offsetof(CPU_DoubleU, l.lower);
1047 }
1048}
9ee6e8bb
PB		 1049
1050/* Return the offset of a 32-bit piece of a NEON register.
1051 zero is the least significant end of the register. */
1052static inline long
1053neon_reg_offset (int reg, int n)
1054{
1055 int sreg;
1056 sreg = reg * 2 + n;
1057 return vfp_reg_offset(0, sreg);
1058}
1059
8f8e3aa4
PB		 1060static TCGv neon_load_reg(int reg, int pass)
1061{
1062 TCGv tmp = new_tmp();
1063 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1064 return tmp;
1065}
1066
1067static void neon_store_reg(int reg, int pass, TCGv var)
1068{
1069 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1070 dead_tmp(var);
1071}
1072
a7812ae4 1073static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1074{
1075 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1076}
1077
a7812ae4 1078static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1079{
1080 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1081}
1082
4373f3ce
PB		 1083#define tcg_gen_ld_f32 tcg_gen_ld_i32
1084#define tcg_gen_ld_f64 tcg_gen_ld_i64
1085#define tcg_gen_st_f32 tcg_gen_st_i32
1086#define tcg_gen_st_f64 tcg_gen_st_i64
1087
b7bcbe95
FB		 1088static inline void gen_mov_F0_vreg(int dp, int reg)
1089{
1090 if (dp)
4373f3ce 1091 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1092 else
4373f3ce 1093 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1094}
1095
1096static inline void gen_mov_F1_vreg(int dp, int reg)
1097{
1098 if (dp)
4373f3ce 1099 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1100 else
4373f3ce 1101 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1102}
1103
1104static inline void gen_mov_vreg_F0(int dp, int reg)
1105{
1106 if (dp)
4373f3ce 1107 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1108 else
4373f3ce 1109 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1110}
1111
18c9b560
AZ		 1112#define ARM_CP_RW_BIT (1 << 20)
1113
a7812ae4 1114static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1115{
1116 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1117}
1118
a7812ae4 1119static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1120{
1121 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1122}
1123
da6b5335 1124static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1125{
da6b5335
FN		 1126 TCGv var = new_tmp();
1127 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1128 return var;
e677137d
PB		 1129}
1130
da6b5335 1131static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1132{
da6b5335 1133 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
d9968827 1134 dead_tmp(var);
e677137d
PB		 1135}
1136
1137static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1138{
1139 iwmmxt_store_reg(cpu_M0, rn);
1140}
1141
1142static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1143{
1144 iwmmxt_load_reg(cpu_M0, rn);
1145}
1146
1147static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1148{
1149 iwmmxt_load_reg(cpu_V1, rn);
1150 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1151}
1152
1153static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1154{
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1157}
1158
1159static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1160{
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1163}
1164
1165#define IWMMXT_OP(name) \
1166static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1167{ \
1168 iwmmxt_load_reg(cpu_V1, rn); \
1169 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1170}
1171
1172#define IWMMXT_OP_ENV(name) \
1173static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1174{ \
1175 iwmmxt_load_reg(cpu_V1, rn); \
1176 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1177}
1178
1179#define IWMMXT_OP_ENV_SIZE(name) \
1180IWMMXT_OP_ENV(name##b) \
1181IWMMXT_OP_ENV(name##w) \
1182IWMMXT_OP_ENV(name##l)
1183
1184#define IWMMXT_OP_ENV1(name) \
1185static inline void gen_op_iwmmxt_##name##_M0(void) \
1186{ \
1187 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1188}
1189
1190IWMMXT_OP(maddsq)
1191IWMMXT_OP(madduq)
1192IWMMXT_OP(sadb)
1193IWMMXT_OP(sadw)
1194IWMMXT_OP(mulslw)
1195IWMMXT_OP(mulshw)
1196IWMMXT_OP(mululw)
1197IWMMXT_OP(muluhw)
1198IWMMXT_OP(macsw)
1199IWMMXT_OP(macuw)
1200
1201IWMMXT_OP_ENV_SIZE(unpackl)
1202IWMMXT_OP_ENV_SIZE(unpackh)
1203
1204IWMMXT_OP_ENV1(unpacklub)
1205IWMMXT_OP_ENV1(unpackluw)
1206IWMMXT_OP_ENV1(unpacklul)
1207IWMMXT_OP_ENV1(unpackhub)
1208IWMMXT_OP_ENV1(unpackhuw)
1209IWMMXT_OP_ENV1(unpackhul)
1210IWMMXT_OP_ENV1(unpacklsb)
1211IWMMXT_OP_ENV1(unpacklsw)
1212IWMMXT_OP_ENV1(unpacklsl)
1213IWMMXT_OP_ENV1(unpackhsb)
1214IWMMXT_OP_ENV1(unpackhsw)
1215IWMMXT_OP_ENV1(unpackhsl)
1216
1217IWMMXT_OP_ENV_SIZE(cmpeq)
1218IWMMXT_OP_ENV_SIZE(cmpgtu)
1219IWMMXT_OP_ENV_SIZE(cmpgts)
1220
1221IWMMXT_OP_ENV_SIZE(mins)
1222IWMMXT_OP_ENV_SIZE(minu)
1223IWMMXT_OP_ENV_SIZE(maxs)
1224IWMMXT_OP_ENV_SIZE(maxu)
1225
1226IWMMXT_OP_ENV_SIZE(subn)
1227IWMMXT_OP_ENV_SIZE(addn)
1228IWMMXT_OP_ENV_SIZE(subu)
1229IWMMXT_OP_ENV_SIZE(addu)
1230IWMMXT_OP_ENV_SIZE(subs)
1231IWMMXT_OP_ENV_SIZE(adds)
1232
1233IWMMXT_OP_ENV(avgb0)
1234IWMMXT_OP_ENV(avgb1)
1235IWMMXT_OP_ENV(avgw0)
1236IWMMXT_OP_ENV(avgw1)
1237
1238IWMMXT_OP(msadb)
1239
1240IWMMXT_OP_ENV(packuw)
1241IWMMXT_OP_ENV(packul)
1242IWMMXT_OP_ENV(packuq)
1243IWMMXT_OP_ENV(packsw)
1244IWMMXT_OP_ENV(packsl)
1245IWMMXT_OP_ENV(packsq)
1246
e677137d
PB		 1247static void gen_op_iwmmxt_set_mup(void)
1248{
1249 TCGv tmp;
1250 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1251 tcg_gen_ori_i32(tmp, tmp, 2);
1252 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1253}
1254
1255static void gen_op_iwmmxt_set_cup(void)
1256{
1257 TCGv tmp;
1258 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259 tcg_gen_ori_i32(tmp, tmp, 1);
1260 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1261}
1262
1263static void gen_op_iwmmxt_setpsr_nz(void)
1264{
1265 TCGv tmp = new_tmp();
1266 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1267 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1268}
1269
1270static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1271{
1272 iwmmxt_load_reg(cpu_V1, rn);
86831435 1273 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1274 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1275}
1276
da6b5335 1277static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1278{
1279 int rd;
1280 uint32_t offset;
da6b5335 1281 TCGv tmp;
18c9b560
AZ		 1282
1283 rd = (insn >> 16) & 0xf;
da6b5335 1284 tmp = load_reg(s, rd);
18c9b560
AZ		 1285
1286 offset = (insn & 0xff) << ((insn >> 7) & 2);
1287 if (insn & (1 << 24)) {
1288 /* Pre indexed */
1289 if (insn & (1 << 23))
da6b5335 1290 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1291 else
da6b5335
FN		 1292 tcg_gen_addi_i32(tmp, tmp, -offset);
1293 tcg_gen_mov_i32(dest, tmp);
18c9b560 1294 if (insn & (1 << 21))
da6b5335
FN		 1295 store_reg(s, rd, tmp);
1296 else
1297 dead_tmp(tmp);
18c9b560
AZ		 1298 } else if (insn & (1 << 21)) {
1299 /* Post indexed */
da6b5335 1300 tcg_gen_mov_i32(dest, tmp);
18c9b560 1301 if (insn & (1 << 23))
da6b5335 1302 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1303 else
da6b5335
FN		 1304 tcg_gen_addi_i32(tmp, tmp, -offset);
1305 store_reg(s, rd, tmp);
18c9b560
AZ		 1306 } else if (!(insn & (1 << 23)))
1307 return 1;
1308 return 0;
1309}
1310
da6b5335 1311static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1312{
1313 int rd = (insn >> 0) & 0xf;
da6b5335 1314 TCGv tmp;
18c9b560 1315
da6b5335
FN		 1316 if (insn & (1 << 8)) {
1317 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1318 return 1;
da6b5335
FN		 1319 } else {
1320 tmp = iwmmxt_load_creg(rd);
1321 }
1322 } else {
1323 tmp = new_tmp();
1324 iwmmxt_load_reg(cpu_V0, rd);
1325 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1326 }
1327 tcg_gen_andi_i32(tmp, tmp, mask);
1328 tcg_gen_mov_i32(dest, tmp);
1329 dead_tmp(tmp);
18c9b560
AZ		 1330 return 0;
1331}
1332
1333/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1334 (ie. an undefined instruction). */
1335static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1336{
1337 int rd, wrd;
1338 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1339 TCGv addr;
1340 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1341
1342 if ((insn & 0x0e000e00) == 0x0c000000) {
1343 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1344 wrd = insn & 0xf;
1345 rdlo = (insn >> 12) & 0xf;
1346 rdhi = (insn >> 16) & 0xf;
1347 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1348 iwmmxt_load_reg(cpu_V0, wrd);
1349 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1350 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1351 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1352 } else { /* TMCRR */
da6b5335
FN		 1353 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1354 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1355 gen_op_iwmmxt_set_mup();
1356 }
1357 return 0;
1358 }
1359
1360 wrd = (insn >> 12) & 0xf;
da6b5335
FN		 1361 addr = new_tmp();
1362 if (gen_iwmmxt_address(s, insn, addr)) {
1363 dead_tmp(addr);
18c9b560 1364 return 1;
da6b5335 1365 }
18c9b560
AZ		 1366 if (insn & ARM_CP_RW_BIT) {
1367 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
da6b5335
FN		 1368 tmp = new_tmp();
1369 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1370 iwmmxt_store_creg(wrd, tmp);
18c9b560 1371 } else {
e677137d
PB		 1372 i = 1;
1373 if (insn & (1 << 8)) {
1374 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1375 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1376 i = 0;
1377 } else { /* WLDRW wRd */
da6b5335 1378 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1379 }
1380 } else {
1381 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1382 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1383 } else { /* WLDRB */
da6b5335 1384 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1385 }
1386 }
1387 if (i) {
1388 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1389 dead_tmp(tmp);
1390 }
18c9b560
AZ		 1391 gen_op_iwmmxt_movq_wRn_M0(wrd);
1392 }
1393 } else {
1394 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1395 tmp = iwmmxt_load_creg(wrd);
1396 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1397 } else {
1398 gen_op_iwmmxt_movq_M0_wRn(wrd);
e677137d
PB		 1399 tmp = new_tmp();
1400 if (insn & (1 << 8)) {
1401 if (insn & (1 << 22)) { /* WSTRD */
1402 dead_tmp(tmp);
da6b5335 1403 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1404 } else { /* WSTRW wRd */
1405 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1406 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1407 }
1408 } else {
1409 if (insn & (1 << 22)) { /* WSTRH */
1410 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1411 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1412 } else { /* WSTRB */
1413 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1414 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1415 }
1416 }
18c9b560
AZ		 1417 }
1418 }
d9968827 1419 dead_tmp(addr);
18c9b560
AZ		 1420 return 0;
1421 }
1422
1423 if ((insn & 0x0f000000) != 0x0e000000)
1424 return 1;
1425
1426 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1427 case 0x000: /* WOR */
1428 wrd = (insn >> 12) & 0xf;
1429 rd0 = (insn >> 0) & 0xf;
1430 rd1 = (insn >> 16) & 0xf;
1431 gen_op_iwmmxt_movq_M0_wRn(rd0);
1432 gen_op_iwmmxt_orq_M0_wRn(rd1);
1433 gen_op_iwmmxt_setpsr_nz();
1434 gen_op_iwmmxt_movq_wRn_M0(wrd);
1435 gen_op_iwmmxt_set_mup();
1436 gen_op_iwmmxt_set_cup();
1437 break;
1438 case 0x011: /* TMCR */
1439 if (insn & 0xf)
1440 return 1;
1441 rd = (insn >> 12) & 0xf;
1442 wrd = (insn >> 16) & 0xf;
1443 switch (wrd) {
1444 case ARM_IWMMXT_wCID:
1445 case ARM_IWMMXT_wCASF:
1446 break;
1447 case ARM_IWMMXT_wCon:
1448 gen_op_iwmmxt_set_cup();
1449 /* Fall through. */
1450 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1451 tmp = iwmmxt_load_creg(wrd);
1452 tmp2 = load_reg(s, rd);
f669df27 1453 tcg_gen_andc_i32(tmp, tmp, tmp2);
da6b5335
FN		 1454 dead_tmp(tmp2);
1455 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1456 break;
1457 case ARM_IWMMXT_wCGR0:
1458 case ARM_IWMMXT_wCGR1:
1459 case ARM_IWMMXT_wCGR2:
1460 case ARM_IWMMXT_wCGR3:
1461 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1462 tmp = load_reg(s, rd);
1463 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1464 break;
1465 default:
1466 return 1;
1467 }
1468 break;
1469 case 0x100: /* WXOR */
1470 wrd = (insn >> 12) & 0xf;
1471 rd0 = (insn >> 0) & 0xf;
1472 rd1 = (insn >> 16) & 0xf;
1473 gen_op_iwmmxt_movq_M0_wRn(rd0);
1474 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1475 gen_op_iwmmxt_setpsr_nz();
1476 gen_op_iwmmxt_movq_wRn_M0(wrd);
1477 gen_op_iwmmxt_set_mup();
1478 gen_op_iwmmxt_set_cup();
1479 break;
1480 case 0x111: /* TMRC */
1481 if (insn & 0xf)
1482 return 1;
1483 rd = (insn >> 12) & 0xf;
1484 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1485 tmp = iwmmxt_load_creg(wrd);
1486 store_reg(s, rd, tmp);
18c9b560
AZ		 1487 break;
1488 case 0x300: /* WANDN */
1489 wrd = (insn >> 12) & 0xf;
1490 rd0 = (insn >> 0) & 0xf;
1491 rd1 = (insn >> 16) & 0xf;
1492 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1493 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1494 gen_op_iwmmxt_andq_M0_wRn(rd1);
1495 gen_op_iwmmxt_setpsr_nz();
1496 gen_op_iwmmxt_movq_wRn_M0(wrd);
1497 gen_op_iwmmxt_set_mup();
1498 gen_op_iwmmxt_set_cup();
1499 break;
1500 case 0x200: /* WAND */
1501 wrd = (insn >> 12) & 0xf;
1502 rd0 = (insn >> 0) & 0xf;
1503 rd1 = (insn >> 16) & 0xf;
1504 gen_op_iwmmxt_movq_M0_wRn(rd0);
1505 gen_op_iwmmxt_andq_M0_wRn(rd1);
1506 gen_op_iwmmxt_setpsr_nz();
1507 gen_op_iwmmxt_movq_wRn_M0(wrd);
1508 gen_op_iwmmxt_set_mup();
1509 gen_op_iwmmxt_set_cup();
1510 break;
1511 case 0x810: case 0xa10: /* WMADD */
1512 wrd = (insn >> 12) & 0xf;
1513 rd0 = (insn >> 0) & 0xf;
1514 rd1 = (insn >> 16) & 0xf;
1515 gen_op_iwmmxt_movq_M0_wRn(rd0);
1516 if (insn & (1 << 21))
1517 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1518 else
1519 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1520 gen_op_iwmmxt_movq_wRn_M0(wrd);
1521 gen_op_iwmmxt_set_mup();
1522 break;
1523 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1524 wrd = (insn >> 12) & 0xf;
1525 rd0 = (insn >> 16) & 0xf;
1526 rd1 = (insn >> 0) & 0xf;
1527 gen_op_iwmmxt_movq_M0_wRn(rd0);
1528 switch ((insn >> 22) & 3) {
1529 case 0:
1530 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1531 break;
1532 case 1:
1533 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1534 break;
1535 case 2:
1536 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1537 break;
1538 case 3:
1539 return 1;
1540 }
1541 gen_op_iwmmxt_movq_wRn_M0(wrd);
1542 gen_op_iwmmxt_set_mup();
1543 gen_op_iwmmxt_set_cup();
1544 break;
1545 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1546 wrd = (insn >> 12) & 0xf;
1547 rd0 = (insn >> 16) & 0xf;
1548 rd1 = (insn >> 0) & 0xf;
1549 gen_op_iwmmxt_movq_M0_wRn(rd0);
1550 switch ((insn >> 22) & 3) {
1551 case 0:
1552 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1553 break;
1554 case 1:
1555 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1556 break;
1557 case 2:
1558 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1559 break;
1560 case 3:
1561 return 1;
1562 }
1563 gen_op_iwmmxt_movq_wRn_M0(wrd);
1564 gen_op_iwmmxt_set_mup();
1565 gen_op_iwmmxt_set_cup();
1566 break;
1567 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1568 wrd = (insn >> 12) & 0xf;
1569 rd0 = (insn >> 16) & 0xf;
1570 rd1 = (insn >> 0) & 0xf;
1571 gen_op_iwmmxt_movq_M0_wRn(rd0);
1572 if (insn & (1 << 22))
1573 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1574 else
1575 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1576 if (!(insn & (1 << 20)))
1577 gen_op_iwmmxt_addl_M0_wRn(wrd);
1578 gen_op_iwmmxt_movq_wRn_M0(wrd);
1579 gen_op_iwmmxt_set_mup();
1580 break;
1581 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1582 wrd = (insn >> 12) & 0xf;
1583 rd0 = (insn >> 16) & 0xf;
1584 rd1 = (insn >> 0) & 0xf;
1585 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1586 if (insn & (1 << 21)) {
1587 if (insn & (1 << 20))
1588 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1589 else
1590 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1591 } else {
1592 if (insn & (1 << 20))
1593 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1594 else
1595 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1596 }
18c9b560
AZ		 1597 gen_op_iwmmxt_movq_wRn_M0(wrd);
1598 gen_op_iwmmxt_set_mup();
1599 break;
1600 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1601 wrd = (insn >> 12) & 0xf;
1602 rd0 = (insn >> 16) & 0xf;
1603 rd1 = (insn >> 0) & 0xf;
1604 gen_op_iwmmxt_movq_M0_wRn(rd0);
1605 if (insn & (1 << 21))
1606 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1607 else
1608 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1609 if (!(insn & (1 << 20))) {
e677137d
PB		 1610 iwmmxt_load_reg(cpu_V1, wrd);
1611 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1612 }
1613 gen_op_iwmmxt_movq_wRn_M0(wrd);
1614 gen_op_iwmmxt_set_mup();
1615 break;
1616 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1617 wrd = (insn >> 12) & 0xf;
1618 rd0 = (insn >> 16) & 0xf;
1619 rd1 = (insn >> 0) & 0xf;
1620 gen_op_iwmmxt_movq_M0_wRn(rd0);
1621 switch ((insn >> 22) & 3) {
1622 case 0:
1623 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1624 break;
1625 case 1:
1626 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1627 break;
1628 case 2:
1629 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1630 break;
1631 case 3:
1632 return 1;
1633 }
1634 gen_op_iwmmxt_movq_wRn_M0(wrd);
1635 gen_op_iwmmxt_set_mup();
1636 gen_op_iwmmxt_set_cup();
1637 break;
1638 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1639 wrd = (insn >> 12) & 0xf;
1640 rd0 = (insn >> 16) & 0xf;
1641 rd1 = (insn >> 0) & 0xf;
1642 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1643 if (insn & (1 << 22)) {
1644 if (insn & (1 << 20))
1645 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1646 else
1647 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1648 } else {
1649 if (insn & (1 << 20))
1650 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1651 else
1652 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1653 }
18c9b560
AZ		 1654 gen_op_iwmmxt_movq_wRn_M0(wrd);
1655 gen_op_iwmmxt_set_mup();
1656 gen_op_iwmmxt_set_cup();
1657 break;
1658 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1659 wrd = (insn >> 12) & 0xf;
1660 rd0 = (insn >> 16) & 0xf;
1661 rd1 = (insn >> 0) & 0xf;
1662 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1663 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1664 tcg_gen_andi_i32(tmp, tmp, 7);
1665 iwmmxt_load_reg(cpu_V1, rd1);
1666 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1667 dead_tmp(tmp);
18c9b560
AZ		 1668 gen_op_iwmmxt_movq_wRn_M0(wrd);
1669 gen_op_iwmmxt_set_mup();
1670 break;
1671 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1672 if (((insn >> 6) & 3) == 3)
1673 return 1;
18c9b560
AZ		 1674 rd = (insn >> 12) & 0xf;
1675 wrd = (insn >> 16) & 0xf;
da6b5335 1676 tmp = load_reg(s, rd);
18c9b560
AZ		 1677 gen_op_iwmmxt_movq_M0_wRn(wrd);
1678 switch ((insn >> 6) & 3) {
1679 case 0:
da6b5335
FN		 1680 tmp2 = tcg_const_i32(0xff);
1681 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1682 break;
1683 case 1:
da6b5335
FN		 1684 tmp2 = tcg_const_i32(0xffff);
1685 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1686 break;
1687 case 2:
da6b5335
FN		 1688 tmp2 = tcg_const_i32(0xffffffff);
1689 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1690 break;
da6b5335
FN		 1691 default:
1692 TCGV_UNUSED(tmp2);
1693 TCGV_UNUSED(tmp3);
18c9b560 1694 }
da6b5335
FN		 1695 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1696 tcg_temp_free(tmp3);
1697 tcg_temp_free(tmp2);
1698 dead_tmp(tmp);
18c9b560
AZ		 1699 gen_op_iwmmxt_movq_wRn_M0(wrd);
1700 gen_op_iwmmxt_set_mup();
1701 break;
1702 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1703 rd = (insn >> 12) & 0xf;
1704 wrd = (insn >> 16) & 0xf;
da6b5335 1705 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1706 return 1;
1707 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335 1708 tmp = new_tmp();
18c9b560
AZ		 1709 switch ((insn >> 22) & 3) {
1710 case 0:
da6b5335
FN		 1711 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1712 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1713 if (insn & 8) {
1714 tcg_gen_ext8s_i32(tmp, tmp);
1715 } else {
1716 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1717 }
1718 break;
1719 case 1:
da6b5335
FN		 1720 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1721 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1722 if (insn & 8) {
1723 tcg_gen_ext16s_i32(tmp, tmp);
1724 } else {
1725 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1726 }
1727 break;
1728 case 2:
da6b5335
FN		 1729 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1730 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1731 break;
18c9b560 1732 }
da6b5335 1733 store_reg(s, rd, tmp);
18c9b560
AZ		 1734 break;
1735 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1736 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1737 return 1;
da6b5335 1738 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1739 switch ((insn >> 22) & 3) {
1740 case 0:
da6b5335 1741 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1742 break;
1743 case 1:
da6b5335 1744 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1745 break;
1746 case 2:
da6b5335 1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1748 break;
18c9b560 1749 }
da6b5335
FN		 1750 tcg_gen_shli_i32(tmp, tmp, 28);
1751 gen_set_nzcv(tmp);
1752 dead_tmp(tmp);
18c9b560
AZ		 1753 break;
1754 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1755 if (((insn >> 6) & 3) == 3)
1756 return 1;
18c9b560
AZ		 1757 rd = (insn >> 12) & 0xf;
1758 wrd = (insn >> 16) & 0xf;
da6b5335 1759 tmp = load_reg(s, rd);
18c9b560
AZ		 1760 switch ((insn >> 6) & 3) {
1761 case 0:
da6b5335 1762 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1763 break;
1764 case 1:
da6b5335 1765 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1766 break;
1767 case 2:
da6b5335 1768 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1769 break;
18c9b560 1770 }
da6b5335 1771 dead_tmp(tmp);
18c9b560
AZ		 1772 gen_op_iwmmxt_movq_wRn_M0(wrd);
1773 gen_op_iwmmxt_set_mup();
1774 break;
1775 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1776 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1777 return 1;
da6b5335
FN		 1778 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1779 tmp2 = new_tmp();
1780 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1781 switch ((insn >> 22) & 3) {
1782 case 0:
1783 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1784 tcg_gen_shli_i32(tmp2, tmp2, 4);
1785 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1786 }
1787 break;
1788 case 1:
1789 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1790 tcg_gen_shli_i32(tmp2, tmp2, 8);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1792 }
1793 break;
1794 case 2:
da6b5335
FN		 1795 tcg_gen_shli_i32(tmp2, tmp2, 16);
1796 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1797 break;
18c9b560 1798 }
da6b5335
FN		 1799 gen_set_nzcv(tmp);
1800 dead_tmp(tmp2);
1801 dead_tmp(tmp);
18c9b560
AZ		 1802 break;
1803 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1804 wrd = (insn >> 12) & 0xf;
1805 rd0 = (insn >> 16) & 0xf;
1806 gen_op_iwmmxt_movq_M0_wRn(rd0);
1807 switch ((insn >> 22) & 3) {
1808 case 0:
e677137d 1809 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1810 break;
1811 case 1:
e677137d 1812 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1813 break;
1814 case 2:
e677137d 1815 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1816 break;
1817 case 3:
1818 return 1;
1819 }
1820 gen_op_iwmmxt_movq_wRn_M0(wrd);
1821 gen_op_iwmmxt_set_mup();
1822 break;
1823 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1824 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1825 return 1;
da6b5335
FN		 1826 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1827 tmp2 = new_tmp();
1828 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1829 switch ((insn >> 22) & 3) {
1830 case 0:
1831 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1832 tcg_gen_shli_i32(tmp2, tmp2, 4);
1833 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1834 }
1835 break;
1836 case 1:
1837 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1838 tcg_gen_shli_i32(tmp2, tmp2, 8);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1840 }
1841 break;
1842 case 2:
da6b5335
FN		 1843 tcg_gen_shli_i32(tmp2, tmp2, 16);
1844 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1845 break;
18c9b560 1846 }
da6b5335
FN		 1847 gen_set_nzcv(tmp);
1848 dead_tmp(tmp2);
1849 dead_tmp(tmp);
18c9b560
AZ		 1850 break;
1851 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1852 rd = (insn >> 12) & 0xf;
1853 rd0 = (insn >> 16) & 0xf;
da6b5335 1854 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1855 return 1;
1856 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 1857 tmp = new_tmp();
18c9b560
AZ		 1858 switch ((insn >> 22) & 3) {
1859 case 0:
da6b5335 1860 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1861 break;
1862 case 1:
da6b5335 1863 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1864 break;
1865 case 2:
da6b5335 1866 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1867 break;
18c9b560 1868 }
da6b5335 1869 store_reg(s, rd, tmp);
18c9b560
AZ		 1870 break;
1871 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1872 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1873 wrd = (insn >> 12) & 0xf;
1874 rd0 = (insn >> 16) & 0xf;
1875 rd1 = (insn >> 0) & 0xf;
1876 gen_op_iwmmxt_movq_M0_wRn(rd0);
1877 switch ((insn >> 22) & 3) {
1878 case 0:
1879 if (insn & (1 << 21))
1880 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1881 else
1882 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1883 break;
1884 case 1:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1889 break;
1890 case 2:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1895 break;
1896 case 3:
1897 return 1;
1898 }
1899 gen_op_iwmmxt_movq_wRn_M0(wrd);
1900 gen_op_iwmmxt_set_mup();
1901 gen_op_iwmmxt_set_cup();
1902 break;
1903 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1904 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1905 wrd = (insn >> 12) & 0xf;
1906 rd0 = (insn >> 16) & 0xf;
1907 gen_op_iwmmxt_movq_M0_wRn(rd0);
1908 switch ((insn >> 22) & 3) {
1909 case 0:
1910 if (insn & (1 << 21))
1911 gen_op_iwmmxt_unpacklsb_M0();
1912 else
1913 gen_op_iwmmxt_unpacklub_M0();
1914 break;
1915 case 1:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsw_M0();
1918 else
1919 gen_op_iwmmxt_unpackluw_M0();
1920 break;
1921 case 2:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsl_M0();
1924 else
1925 gen_op_iwmmxt_unpacklul_M0();
1926 break;
1927 case 3:
1928 return 1;
1929 }
1930 gen_op_iwmmxt_movq_wRn_M0(wrd);
1931 gen_op_iwmmxt_set_mup();
1932 gen_op_iwmmxt_set_cup();
1933 break;
1934 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1935 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1936 wrd = (insn >> 12) & 0xf;
1937 rd0 = (insn >> 16) & 0xf;
1938 gen_op_iwmmxt_movq_M0_wRn(rd0);
1939 switch ((insn >> 22) & 3) {
1940 case 0:
1941 if (insn & (1 << 21))
1942 gen_op_iwmmxt_unpackhsb_M0();
1943 else
1944 gen_op_iwmmxt_unpackhub_M0();
1945 break;
1946 case 1:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsw_M0();
1949 else
1950 gen_op_iwmmxt_unpackhuw_M0();
1951 break;
1952 case 2:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsl_M0();
1955 else
1956 gen_op_iwmmxt_unpackhul_M0();
1957 break;
1958 case 3:
1959 return 1;
1960 }
1961 gen_op_iwmmxt_movq_wRn_M0(wrd);
1962 gen_op_iwmmxt_set_mup();
1963 gen_op_iwmmxt_set_cup();
1964 break;
1965 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1966 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1967 if (((insn >> 22) & 3) == 0)
1968 return 1;
18c9b560
AZ		 1969 wrd = (insn >> 12) & 0xf;
1970 rd0 = (insn >> 16) & 0xf;
1971 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1972 tmp = new_tmp();
1973 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1974 dead_tmp(tmp);
18c9b560 1975 return 1;
da6b5335 1976 }
18c9b560 1977 switch ((insn >> 22) & 3) {
18c9b560 1978 case 1:
da6b5335 1979 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1980 break;
1981 case 2:
da6b5335 1982 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1983 break;
1984 case 3:
da6b5335 1985 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1986 break;
1987 }
da6b5335 1988 dead_tmp(tmp);
18c9b560
AZ		 1989 gen_op_iwmmxt_movq_wRn_M0(wrd);
1990 gen_op_iwmmxt_set_mup();
1991 gen_op_iwmmxt_set_cup();
1992 break;
1993 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1994 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 1995 if (((insn >> 22) & 3) == 0)
1996 return 1;
18c9b560
AZ		 1997 wrd = (insn >> 12) & 0xf;
1998 rd0 = (insn >> 16) & 0xf;
1999 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2000 tmp = new_tmp();
2001 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2002 dead_tmp(tmp);
18c9b560 2003 return 1;
da6b5335 2004 }
18c9b560 2005 switch ((insn >> 22) & 3) {
18c9b560 2006 case 1:
da6b5335 2007 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2008 break;
2009 case 2:
da6b5335 2010 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2011 break;
2012 case 3:
da6b5335 2013 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2014 break;
2015 }
da6b5335 2016 dead_tmp(tmp);
18c9b560
AZ		 2017 gen_op_iwmmxt_movq_wRn_M0(wrd);
2018 gen_op_iwmmxt_set_mup();
2019 gen_op_iwmmxt_set_cup();
2020 break;
2021 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2022 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2023 if (((insn >> 22) & 3) == 0)
2024 return 1;
18c9b560
AZ		 2025 wrd = (insn >> 12) & 0xf;
2026 rd0 = (insn >> 16) & 0xf;
2027 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2028 tmp = new_tmp();
2029 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2030 dead_tmp(tmp);
18c9b560 2031 return 1;
da6b5335 2032 }
18c9b560 2033 switch ((insn >> 22) & 3) {
18c9b560 2034 case 1:
da6b5335 2035 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2036 break;
2037 case 2:
da6b5335 2038 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2039 break;
2040 case 3:
da6b5335 2041 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2042 break;
2043 }
da6b5335 2044 dead_tmp(tmp);
18c9b560
AZ		 2045 gen_op_iwmmxt_movq_wRn_M0(wrd);
2046 gen_op_iwmmxt_set_mup();
2047 gen_op_iwmmxt_set_cup();
2048 break;
2049 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2050 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2051 if (((insn >> 22) & 3) == 0)
2052 return 1;
18c9b560
AZ		 2053 wrd = (insn >> 12) & 0xf;
2054 rd0 = (insn >> 16) & 0xf;
2055 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2056 tmp = new_tmp();
18c9b560 2057 switch ((insn >> 22) & 3) {
18c9b560 2058 case 1:
da6b5335
FN		 2059 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2060 dead_tmp(tmp);
18c9b560 2061 return 1;
da6b5335
FN		 2062 }
2063 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2064 break;
2065 case 2:
da6b5335
FN		 2066 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2067 dead_tmp(tmp);
18c9b560 2068 return 1;
da6b5335
FN		 2069 }
2070 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2071 break;
2072 case 3:
da6b5335
FN		 2073 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2074 dead_tmp(tmp);
18c9b560 2075 return 1;
da6b5335
FN		 2076 }
2077 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2078 break;
2079 }
da6b5335 2080 dead_tmp(tmp);
18c9b560
AZ		 2081 gen_op_iwmmxt_movq_wRn_M0(wrd);
2082 gen_op_iwmmxt_set_mup();
2083 gen_op_iwmmxt_set_cup();
2084 break;
2085 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2086 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2087 wrd = (insn >> 12) & 0xf;
2088 rd0 = (insn >> 16) & 0xf;
2089 rd1 = (insn >> 0) & 0xf;
2090 gen_op_iwmmxt_movq_M0_wRn(rd0);
2091 switch ((insn >> 22) & 3) {
2092 case 0:
2093 if (insn & (1 << 21))
2094 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2095 else
2096 gen_op_iwmmxt_minub_M0_wRn(rd1);
2097 break;
2098 case 1:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2103 break;
2104 case 2:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minul_M0_wRn(rd1);
2109 break;
2110 case 3:
2111 return 1;
2112 }
2113 gen_op_iwmmxt_movq_wRn_M0(wrd);
2114 gen_op_iwmmxt_set_mup();
2115 break;
2116 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2117 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2118 wrd = (insn >> 12) & 0xf;
2119 rd0 = (insn >> 16) & 0xf;
2120 rd1 = (insn >> 0) & 0xf;
2121 gen_op_iwmmxt_movq_M0_wRn(rd0);
2122 switch ((insn >> 22) & 3) {
2123 case 0:
2124 if (insn & (1 << 21))
2125 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2126 else
2127 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2128 break;
2129 case 1:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2134 break;
2135 case 2:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2140 break;
2141 case 3:
2142 return 1;
2143 }
2144 gen_op_iwmmxt_movq_wRn_M0(wrd);
2145 gen_op_iwmmxt_set_mup();
2146 break;
2147 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2148 case 0x402: case 0x502: case 0x602: case 0x702:
2149 wrd = (insn >> 12) & 0xf;
2150 rd0 = (insn >> 16) & 0xf;
2151 rd1 = (insn >> 0) & 0xf;
2152 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2153 tmp = tcg_const_i32((insn >> 20) & 3);
2154 iwmmxt_load_reg(cpu_V1, rd1);
2155 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2156 tcg_temp_free(tmp);
18c9b560
AZ		 2157 gen_op_iwmmxt_movq_wRn_M0(wrd);
2158 gen_op_iwmmxt_set_mup();
2159 break;
2160 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2161 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2162 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2163 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2164 wrd = (insn >> 12) & 0xf;
2165 rd0 = (insn >> 16) & 0xf;
2166 rd1 = (insn >> 0) & 0xf;
2167 gen_op_iwmmxt_movq_M0_wRn(rd0);
2168 switch ((insn >> 20) & 0xf) {
2169 case 0x0:
2170 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2171 break;
2172 case 0x1:
2173 gen_op_iwmmxt_subub_M0_wRn(rd1);
2174 break;
2175 case 0x3:
2176 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2177 break;
2178 case 0x4:
2179 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2180 break;
2181 case 0x5:
2182 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2183 break;
2184 case 0x7:
2185 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2186 break;
2187 case 0x8:
2188 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2189 break;
2190 case 0x9:
2191 gen_op_iwmmxt_subul_M0_wRn(rd1);
2192 break;
2193 case 0xb:
2194 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2195 break;
2196 default:
2197 return 1;
2198 }
2199 gen_op_iwmmxt_movq_wRn_M0(wrd);
2200 gen_op_iwmmxt_set_mup();
2201 gen_op_iwmmxt_set_cup();
2202 break;
2203 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2204 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2205 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2206 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2207 wrd = (insn >> 12) & 0xf;
2208 rd0 = (insn >> 16) & 0xf;
2209 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2210 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2211 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2212 tcg_temp_free(tmp);
18c9b560
AZ		 2213 gen_op_iwmmxt_movq_wRn_M0(wrd);
2214 gen_op_iwmmxt_set_mup();
2215 gen_op_iwmmxt_set_cup();
2216 break;
2217 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2218 case 0x418: case 0x518: case 0x618: case 0x718:
2219 case 0x818: case 0x918: case 0xa18: case 0xb18:
2220 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2221 wrd = (insn >> 12) & 0xf;
2222 rd0 = (insn >> 16) & 0xf;
2223 rd1 = (insn >> 0) & 0xf;
2224 gen_op_iwmmxt_movq_M0_wRn(rd0);
2225 switch ((insn >> 20) & 0xf) {
2226 case 0x0:
2227 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2228 break;
2229 case 0x1:
2230 gen_op_iwmmxt_addub_M0_wRn(rd1);
2231 break;
2232 case 0x3:
2233 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2234 break;
2235 case 0x4:
2236 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2237 break;
2238 case 0x5:
2239 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2240 break;
2241 case 0x7:
2242 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2243 break;
2244 case 0x8:
2245 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2246 break;
2247 case 0x9:
2248 gen_op_iwmmxt_addul_M0_wRn(rd1);
2249 break;
2250 case 0xb:
2251 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2252 break;
2253 default:
2254 return 1;
2255 }
2256 gen_op_iwmmxt_movq_wRn_M0(wrd);
2257 gen_op_iwmmxt_set_mup();
2258 gen_op_iwmmxt_set_cup();
2259 break;
2260 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2261 case 0x408: case 0x508: case 0x608: case 0x708:
2262 case 0x808: case 0x908: case 0xa08: case 0xb08:
2263 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2264 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2265 return 1;
18c9b560
AZ		 2266 wrd = (insn >> 12) & 0xf;
2267 rd0 = (insn >> 16) & 0xf;
2268 rd1 = (insn >> 0) & 0xf;
2269 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2270 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2271 case 1:
2272 if (insn & (1 << 21))
2273 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2274 else
2275 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2276 break;
2277 case 2:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packul_M0_wRn(rd1);
2282 break;
2283 case 3:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2288 break;
2289 }
2290 gen_op_iwmmxt_movq_wRn_M0(wrd);
2291 gen_op_iwmmxt_set_mup();
2292 gen_op_iwmmxt_set_cup();
2293 break;
2294 case 0x201: case 0x203: case 0x205: case 0x207:
2295 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2296 case 0x211: case 0x213: case 0x215: case 0x217:
2297 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2298 wrd = (insn >> 5) & 0xf;
2299 rd0 = (insn >> 12) & 0xf;
2300 rd1 = (insn >> 0) & 0xf;
2301 if (rd0 == 0xf || rd1 == 0xf)
2302 return 1;
2303 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2304 tmp = load_reg(s, rd0);
2305 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2306 switch ((insn >> 16) & 0xf) {
2307 case 0x0: /* TMIA */
da6b5335 2308 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2309 break;
2310 case 0x8: /* TMIAPH */
da6b5335 2311 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2312 break;
2313 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2314 if (insn & (1 << 16))
da6b5335 2315 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2316 if (insn & (1 << 17))
da6b5335
FN		 2317 tcg_gen_shri_i32(tmp2, tmp2, 16);
2318 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2319 break;
2320 default:
da6b5335
FN		 2321 dead_tmp(tmp2);
2322 dead_tmp(tmp);
18c9b560
AZ		 2323 return 1;
2324 }
da6b5335
FN		 2325 dead_tmp(tmp2);
2326 dead_tmp(tmp);
18c9b560
AZ		 2327 gen_op_iwmmxt_movq_wRn_M0(wrd);
2328 gen_op_iwmmxt_set_mup();
2329 break;
2330 default:
2331 return 1;
2332 }
2333
2334 return 0;
2335}
2336
2337/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2338 (ie. an undefined instruction). */
2339static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2340{
2341 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2342 TCGv tmp, tmp2;
18c9b560
AZ		 2343
2344 if ((insn & 0x0ff00f10) == 0x0e200010) {
2345 /* Multiply with Internal Accumulate Format */
2346 rd0 = (insn >> 12) & 0xf;
2347 rd1 = insn & 0xf;
2348 acc = (insn >> 5) & 7;
2349
2350 if (acc != 0)
2351 return 1;
2352
3a554c0f
FN		 2353 tmp = load_reg(s, rd0);
2354 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2355 switch ((insn >> 16) & 0xf) {
2356 case 0x0: /* MIA */
3a554c0f 2357 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2358 break;
2359 case 0x8: /* MIAPH */
3a554c0f 2360 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2361 break;
2362 case 0xc: /* MIABB */
2363 case 0xd: /* MIABT */
2364 case 0xe: /* MIATB */
2365 case 0xf: /* MIATT */
18c9b560 2366 if (insn & (1 << 16))
3a554c0f 2367 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2368 if (insn & (1 << 17))
3a554c0f
FN		 2369 tcg_gen_shri_i32(tmp2, tmp2, 16);
2370 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2371 break;
2372 default:
2373 return 1;
2374 }
3a554c0f
FN		 2375 dead_tmp(tmp2);
2376 dead_tmp(tmp);
18c9b560
AZ		 2377
2378 gen_op_iwmmxt_movq_wRn_M0(acc);
2379 return 0;
2380 }
2381
2382 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2383 /* Internal Accumulator Access Format */
2384 rdhi = (insn >> 16) & 0xf;
2385 rdlo = (insn >> 12) & 0xf;
2386 acc = insn & 7;
2387
2388 if (acc != 0)
2389 return 1;
2390
2391 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2392 iwmmxt_load_reg(cpu_V0, acc);
2393 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2394 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2395 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2396 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2397 } else { /* MAR */
3a554c0f
FN		 2398 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2399 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2400 }
2401 return 0;
2402 }
2403
2404 return 1;
2405}
2406
c1713132
AZ		 2407/* Disassemble system coprocessor instruction. Return nonzero if
2408 instruction is not defined. */
2409static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2410{
b75263d6 2411 TCGv tmp, tmp2;
c1713132
AZ		 2412 uint32_t rd = (insn >> 12) & 0xf;
2413 uint32_t cp = (insn >> 8) & 0xf;
2414 if (IS_USER(s)) {
2415 return 1;
2416 }
2417
18c9b560 2418 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2419 if (!env->cp[cp].cp_read)
2420 return 1;
8984bd2e
PB		 2421 gen_set_pc_im(s->pc);
2422 tmp = new_tmp();
b75263d6
JR		 2423 tmp2 = tcg_const_i32(insn);
2424 gen_helper_get_cp(tmp, cpu_env, tmp2);
2425 tcg_temp_free(tmp2);
8984bd2e 2426 store_reg(s, rd, tmp);
c1713132
AZ		 2427 } else {
2428 if (!env->cp[cp].cp_write)
2429 return 1;
8984bd2e
PB		 2430 gen_set_pc_im(s->pc);
2431 tmp = load_reg(s, rd);
b75263d6
JR		 2432 tmp2 = tcg_const_i32(insn);
2433 gen_helper_set_cp(cpu_env, tmp2, tmp);
2434 tcg_temp_free(tmp2);
a60de947 2435 dead_tmp(tmp);
c1713132
AZ		 2436 }
2437 return 0;
2438}
2439
9ee6e8bb
PB		 2440static int cp15_user_ok(uint32_t insn)
2441{
2442 int cpn = (insn >> 16) & 0xf;
2443 int cpm = insn & 0xf;
2444 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2445
2446 if (cpn == 13 && cpm == 0) {
2447 /* TLS register. */
2448 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2449 return 1;
2450 }
2451 if (cpn == 7) {
2452 /* ISB, DSB, DMB. */
2453 if ((cpm == 5 && op == 4)
2454 || (cpm == 10 && (op == 4 || op == 5)))
2455 return 1;
2456 }
2457 return 0;
2458}
2459
3f26c122
RV		 2460static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2461{
2462 TCGv tmp;
2463 int cpn = (insn >> 16) & 0xf;
2464 int cpm = insn & 0xf;
2465 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2466
2467 if (!arm_feature(env, ARM_FEATURE_V6K))
2468 return 0;
2469
2470 if (!(cpn == 13 && cpm == 0))
2471 return 0;
2472
2473 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2474 switch (op) {
2475 case 2:
c5883be2 2476 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2477 break;
2478 case 3:
c5883be2 2479 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2480 break;
2481 case 4:
c5883be2 2482 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2483 break;
2484 default:
3f26c122
RV		 2485 return 0;
2486 }
2487 store_reg(s, rd, tmp);
2488
2489 } else {
2490 tmp = load_reg(s, rd);
2491 switch (op) {
2492 case 2:
c5883be2 2493 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2494 break;
2495 case 3:
c5883be2 2496 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2497 break;
2498 case 4:
c5883be2 2499 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2500 break;
2501 default:
c5883be2 2502 dead_tmp(tmp);
3f26c122
RV		 2503 return 0;
2504 }
3f26c122
RV		 2505 }
2506 return 1;
2507}
2508
b5ff1b31
FB		 2509/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2510 instruction is not defined. */
a90b7318 2511static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2512{
2513 uint32_t rd;
b75263d6 2514 TCGv tmp, tmp2;
b5ff1b31 2515
9ee6e8bb
PB		 2516 /* M profile cores use memory mapped registers instead of cp15. */
2517 if (arm_feature(env, ARM_FEATURE_M))
2518 return 1;
2519
2520 if ((insn & (1 << 25)) == 0) {
2521 if (insn & (1 << 20)) {
2522 /* mrrc */
2523 return 1;
2524 }
2525 /* mcrr. Used for block cache operations, so implement as no-op. */
2526 return 0;
2527 }
2528 if ((insn & (1 << 4)) == 0) {
2529 /* cdp */
2530 return 1;
2531 }
2532 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2533 return 1;
2534 }
9332f9da
FB		 2535 if ((insn & 0x0fff0fff) == 0x0e070f90
2536 || (insn & 0x0fff0fff) == 0x0e070f58) {
2537 /* Wait for interrupt. */
8984bd2e 2538 gen_set_pc_im(s->pc);
9ee6e8bb 2539 s->is_jmp = DISAS_WFI;
9332f9da
FB		 2540 return 0;
2541 }
b5ff1b31 2542 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2543
2544 if (cp15_tls_load_store(env, s, insn, rd))
2545 return 0;
2546
b75263d6 2547 tmp2 = tcg_const_i32(insn);
18c9b560 2548 if (insn & ARM_CP_RW_BIT) {
8984bd2e 2549 tmp = new_tmp();
b75263d6 2550 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2551 /* If the destination register is r15 then sets condition codes. */
2552 if (rd != 15)
8984bd2e
PB		 2553 store_reg(s, rd, tmp);
2554 else
2555 dead_tmp(tmp);
b5ff1b31 2556 } else {
8984bd2e 2557 tmp = load_reg(s, rd);
b75263d6 2558 gen_helper_set_cp15(cpu_env, tmp2, tmp);
8984bd2e 2559 dead_tmp(tmp);
a90b7318
AZ		 2560 /* Normally we would always end the TB here, but Linux
2561 * arch/arm/mach-pxa/sleep.S expects two instructions following
2562 * an MMU enable to execute from cache. Imitate this behaviour. */
2563 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2564 (insn & 0x0fff0fff) != 0x0e010f10)
2565 gen_lookup_tb(s);
b5ff1b31 2566 }
b75263d6 2567 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2568 return 0;
2569}
2570
9ee6e8bb
PB		 2571#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2572#define VFP_SREG(insn, bigbit, smallbit) \
2573 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2574#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2575 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2576 reg = (((insn) >> (bigbit)) & 0x0f) \
2577 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2578 } else { \
2579 if (insn & (1 << (smallbit))) \
2580 return 1; \
2581 reg = ((insn) >> (bigbit)) & 0x0f; \
2582 }} while (0)
2583
2584#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2585#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2586#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2587#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2588#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2589#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2590
4373f3ce
PB		 2591/* Move between integer and VFP cores. */
2592static TCGv gen_vfp_mrs(void)
2593{
2594 TCGv tmp = new_tmp();
2595 tcg_gen_mov_i32(tmp, cpu_F0s);
2596 return tmp;
2597}
2598
2599static void gen_vfp_msr(TCGv tmp)
2600{
2601 tcg_gen_mov_i32(cpu_F0s, tmp);
2602 dead_tmp(tmp);
2603}
2604
9ee6e8bb
PB		 2605static inline int
2606vfp_enabled(CPUState * env)
2607{
2608 return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0);
2609}
2610
ad69471c
PB		 2611static void gen_neon_dup_u8(TCGv var, int shift)
2612{
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
86831435 2616 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622}
2623
2624static void gen_neon_dup_low16(TCGv var)
2625{
2626 TCGv tmp = new_tmp();
86831435 2627 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631}
2632
2633static void gen_neon_dup_high16(TCGv var)
2634{
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640}
2641
b7bcbe95
FB		 2642/* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645{
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
312eea9f 2648 TCGv addr;
4373f3ce 2649 TCGv tmp;
ad69471c 2650 TCGv tmp2;
b7bcbe95 2651
40f137e1
PB		 2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
9ee6e8bb
PB		 2655 if (!vfp_enabled(env)) {
2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2662 return 1;
2663 }
b7bcbe95
FB		 2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
b7bcbe95
FB		 2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
9ee6e8bb
PB		 2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
b7bcbe95 2676 return 1;
9ee6e8bb
PB		 2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
18c9b560 2692 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2693 /* vfp->arm */
ad69471c 2694 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2695 switch (size) {
2696 case 0:
9ee6e8bb 2697 if (offset)
ad69471c 2698 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2699 if (insn & (1 << 23))
ad69471c 2700 gen_uxtb(tmp);
9ee6e8bb 2701 else
ad69471c 2702 gen_sxtb(tmp);
9ee6e8bb
PB		 2703 break;
2704 case 1:
9ee6e8bb
PB		 2705 if (insn & (1 << 23)) {
2706 if (offset) {
ad69471c 2707 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2708 } else {
ad69471c 2709 gen_uxth(tmp);
9ee6e8bb
PB		 2710 }
2711 } else {
2712 if (offset) {
ad69471c 2713 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2714 } else {
ad69471c 2715 gen_sxth(tmp);
9ee6e8bb
PB		 2716 }
2717 }
2718 break;
2719 case 2:
9ee6e8bb
PB		 2720 break;
2721 }
ad69471c 2722 store_reg(s, rd, tmp);
b7bcbe95
FB		 2723 } else {
2724 /* arm->vfp */
ad69471c 2725 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
ad69471c 2729 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2730 } else if (size == 1) {
ad69471c 2731 gen_neon_dup_low16(tmp);
9ee6e8bb 2732 }
cbbccffc
PB		 2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
ad69471c
PB		 2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
9ee6e8bb
PB		 2746 break;
2747 case 1:
ad69471c
PB		 2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
9ee6e8bb
PB		 2751 break;
2752 case 2:
9ee6e8bb
PB		 2753 break;
2754 }
ad69471c 2755 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2756 }
b7bcbe95 2757 }
9ee6e8bb
PB		 2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
18c9b560 2762 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
40f137e1 2766 rn >>= 1;
9ee6e8bb 2767
b7bcbe95 2768 switch (rn) {
40f137e1 2769 case ARM_VFP_FPSID:
4373f3ce 2770 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
4373f3ce 2776 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2777 break;
40f137e1 2778 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2779 if (IS_USER(s))
2780 return 1;
4373f3ce 2781 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2782 break;
40f137e1
PB		 2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
4373f3ce 2789 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2790 break;
40f137e1 2791 case ARM_VFP_FPSCR:
601d70b9 2792 if (rd == 15) {
4373f3ce
PB		 2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
b7bcbe95 2799 break;
9ee6e8bb
PB		 2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
4373f3ce 2805 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2806 break;
b7bcbe95
FB		 2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
4373f3ce 2812 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2813 }
2814 if (rd == 15) {
b5ff1b31 2815 /* Set the 4 flag bits in the CPSR. */
4373f3ce
PB		 2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
b7bcbe95
FB		 2821 } else {
2822 /* arm->vfp */
4373f3ce 2823 tmp = load_reg(s, rd);
b7bcbe95 2824 if (insn & (1 << 21)) {
40f137e1 2825 rn >>= 1;
b7bcbe95
FB		 2826 /* system register */
2827 switch (rn) {
40f137e1 2828 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2831 /* Writes are ignored. */
2832 break;
40f137e1 2833 case ARM_VFP_FPSCR:
4373f3ce
PB		 2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
b5ff1b31 2836 gen_lookup_tb(s);
b7bcbe95 2837 break;
40f137e1 2838 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2839 if (IS_USER(s))
2840 return 1;
71b3c3de
JR		 2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2844 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
4373f3ce 2849 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2850 break;
b7bcbe95
FB		 2851 default:
2852 return 1;
2853 }
2854 } else {
4373f3ce 2855 gen_vfp_msr(tmp);
b7bcbe95
FB		 2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
9ee6e8bb 2870 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2871 }
2872
2873 if (op == 15 && (rn == 15 || rn > 17)) {
2874 /* Integer or single precision destination. */
9ee6e8bb 2875 rd = VFP_SREG_D(insn);
b7bcbe95 2876 } else {
9ee6e8bb 2877 VFP_DREG_D(rd, insn);
b7bcbe95
FB		 2878 }
2879
2880 if (op == 15 && (rn == 16 || rn == 17)) {
2881 /* Integer source. */
2882 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
2883 } else {
9ee6e8bb 2884 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2885 }
2886 } else {
9ee6e8bb 2887 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2888 if (op == 15 && rn == 15) {
2889 /* Double precision destination. */
9ee6e8bb
PB		 2890 VFP_DREG_D(rd, insn);
2891 } else {
2892 rd = VFP_SREG_D(insn);
2893 }
2894 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2895 }
2896
2897 veclen = env->vfp.vec_len;
2898 if (op == 15 && rn > 3)
2899 veclen = 0;
2900
2901 /* Shut up compiler warnings. */
2902 delta_m = 0;
2903 delta_d = 0;
2904 bank_mask = 0;
3b46e624 2905
b7bcbe95
FB		 2906 if (veclen > 0) {
2907 if (dp)
2908 bank_mask = 0xc;
2909 else
2910 bank_mask = 0x18;
2911
2912 /* Figure out what type of vector operation this is. */
2913 if ((rd & bank_mask) == 0) {
2914 /* scalar */
2915 veclen = 0;
2916 } else {
2917 if (dp)
2918 delta_d = (env->vfp.vec_stride >> 1) + 1;
2919 else
2920 delta_d = env->vfp.vec_stride + 1;
2921
2922 if ((rm & bank_mask) == 0) {
2923 /* mixed scalar/vector */
2924 delta_m = 0;
2925 } else {
2926 /* vector */
2927 delta_m = delta_d;
2928 }
2929 }
2930 }
2931
2932 /* Load the initial operands. */
2933 if (op == 15) {
2934 switch (rn) {
2935 case 16:
2936 case 17:
2937 /* Integer source */
2938 gen_mov_F0_vreg(0, rm);
2939 break;
2940 case 8:
2941 case 9:
2942 /* Compare */
2943 gen_mov_F0_vreg(dp, rd);
2944 gen_mov_F1_vreg(dp, rm);
2945 break;
2946 case 10:
2947 case 11:
2948 /* Compare with zero */
2949 gen_mov_F0_vreg(dp, rd);
2950 gen_vfp_F1_ld0(dp);
2951 break;
9ee6e8bb
PB		 2952 case 20:
2953 case 21:
2954 case 22:
2955 case 23:
644ad806
PB		 2956 case 28:
2957 case 29:
2958 case 30:
2959 case 31:
9ee6e8bb
PB		 2960 /* Source and destination the same. */
2961 gen_mov_F0_vreg(dp, rd);
2962 break;
b7bcbe95
FB		 2963 default:
2964 /* One source operand. */
2965 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 2966 break;
b7bcbe95
FB		 2967 }
2968 } else {
2969 /* Two source operands. */
2970 gen_mov_F0_vreg(dp, rn);
2971 gen_mov_F1_vreg(dp, rm);
2972 }
2973
2974 for (;;) {
2975 /* Perform the calculation. */
2976 switch (op) {
2977 case 0: /* mac: fd + (fn * fm) */
2978 gen_vfp_mul(dp);
2979 gen_mov_F1_vreg(dp, rd);
2980 gen_vfp_add(dp);
2981 break;
2982 case 1: /* nmac: fd - (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_vfp_neg(dp);
2985 gen_mov_F1_vreg(dp, rd);
2986 gen_vfp_add(dp);
2987 break;
2988 case 2: /* msc: -fd + (fn * fm) */
2989 gen_vfp_mul(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_sub(dp);
2992 break;
2993 case 3: /* nmsc: -fd - (fn * fm) */
2994 gen_vfp_mul(dp);
b7bcbe95 2995 gen_vfp_neg(dp);
c9fb531a
PB		 2996 gen_mov_F1_vreg(dp, rd);
2997 gen_vfp_sub(dp);
b7bcbe95
FB		 2998 break;
2999 case 4: /* mul: fn * fm */
3000 gen_vfp_mul(dp);
3001 break;
3002 case 5: /* nmul: -(fn * fm) */
3003 gen_vfp_mul(dp);
3004 gen_vfp_neg(dp);
3005 break;
3006 case 6: /* add: fn + fm */
3007 gen_vfp_add(dp);
3008 break;
3009 case 7: /* sub: fn - fm */
3010 gen_vfp_sub(dp);
3011 break;
3012 case 8: /* div: fn / fm */
3013 gen_vfp_div(dp);
3014 break;
9ee6e8bb
PB		 3015 case 14: /* fconst */
3016 if (!arm_feature(env, ARM_FEATURE_VFP3))
3017 return 1;
3018
3019 n = (insn << 12) & 0x80000000;
3020 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3021 if (dp) {
3022 if (i & 0x40)
3023 i |= 0x3f80;
3024 else
3025 i |= 0x4000;
3026 n |= i << 16;
4373f3ce 3027 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3028 } else {
3029 if (i & 0x40)
3030 i |= 0x780;
3031 else
3032 i |= 0x800;
3033 n |= i << 19;
5b340b51 3034 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3035 }
9ee6e8bb 3036 break;
b7bcbe95
FB		 3037 case 15: /* extension space */
3038 switch (rn) {
3039 case 0: /* cpy */
3040 /* no-op */
3041 break;
3042 case 1: /* abs */
3043 gen_vfp_abs(dp);
3044 break;
3045 case 2: /* neg */
3046 gen_vfp_neg(dp);
3047 break;
3048 case 3: /* sqrt */
3049 gen_vfp_sqrt(dp);
3050 break;
60011498
PB		 3051 case 4: /* vcvtb.f32.f16 */
3052 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3053 return 1;
3054 tmp = gen_vfp_mrs();
3055 tcg_gen_ext16u_i32(tmp, tmp);
3056 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3057 dead_tmp(tmp);
3058 break;
3059 case 5: /* vcvtt.f32.f16 */
3060 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3061 return 1;
3062 tmp = gen_vfp_mrs();
3063 tcg_gen_shri_i32(tmp, tmp, 16);
3064 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3065 dead_tmp(tmp);
3066 break;
3067 case 6: /* vcvtb.f16.f32 */
3068 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3069 return 1;
3070 tmp = new_tmp();
3071 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3072 gen_mov_F0_vreg(0, rd);
3073 tmp2 = gen_vfp_mrs();
3074 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3075 tcg_gen_or_i32(tmp, tmp, tmp2);
3076 dead_tmp(tmp2);
3077 gen_vfp_msr(tmp);
3078 break;
3079 case 7: /* vcvtt.f16.f32 */
3080 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3081 return 1;
3082 tmp = new_tmp();
3083 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3084 tcg_gen_shli_i32(tmp, tmp, 16);
3085 gen_mov_F0_vreg(0, rd);
3086 tmp2 = gen_vfp_mrs();
3087 tcg_gen_ext16u_i32(tmp2, tmp2);
3088 tcg_gen_or_i32(tmp, tmp, tmp2);
3089 dead_tmp(tmp2);
3090 gen_vfp_msr(tmp);
3091 break;
b7bcbe95
FB		 3092 case 8: /* cmp */
3093 gen_vfp_cmp(dp);
3094 break;
3095 case 9: /* cmpe */
3096 gen_vfp_cmpe(dp);
3097 break;
3098 case 10: /* cmpz */
3099 gen_vfp_cmp(dp);
3100 break;
3101 case 11: /* cmpez */
3102 gen_vfp_F1_ld0(dp);
3103 gen_vfp_cmpe(dp);
3104 break;
3105 case 15: /* single<->double conversion */
3106 if (dp)
4373f3ce 3107 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3108 else
4373f3ce 3109 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3110 break;
3111 case 16: /* fuito */
3112 gen_vfp_uito(dp);
3113 break;
3114 case 17: /* fsito */
3115 gen_vfp_sito(dp);
3116 break;
9ee6e8bb
PB		 3117 case 20: /* fshto */
3118 if (!arm_feature(env, ARM_FEATURE_VFP3))
3119 return 1;
644ad806 3120 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3121 break;
3122 case 21: /* fslto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
644ad806 3125 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3126 break;
3127 case 22: /* fuhto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
644ad806 3130 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3131 break;
3132 case 23: /* fulto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
644ad806 3135 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3136 break;
b7bcbe95
FB		 3137 case 24: /* ftoui */
3138 gen_vfp_toui(dp);
3139 break;
3140 case 25: /* ftouiz */
3141 gen_vfp_touiz(dp);
3142 break;
3143 case 26: /* ftosi */
3144 gen_vfp_tosi(dp);
3145 break;
3146 case 27: /* ftosiz */
3147 gen_vfp_tosiz(dp);
3148 break;
9ee6e8bb
PB		 3149 case 28: /* ftosh */
3150 if (!arm_feature(env, ARM_FEATURE_VFP3))
3151 return 1;
644ad806 3152 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3153 break;
3154 case 29: /* ftosl */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
644ad806 3157 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3158 break;
3159 case 30: /* ftouh */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
644ad806 3162 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3163 break;
3164 case 31: /* ftoul */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
644ad806 3167 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3168 break;
b7bcbe95
FB		 3169 default: /* undefined */
3170 printf ("rn:%d\n", rn);
3171 return 1;
3172 }
3173 break;
3174 default: /* undefined */
3175 printf ("op:%d\n", op);
3176 return 1;
3177 }
3178
3179 /* Write back the result. */
3180 if (op == 15 && (rn >= 8 && rn <= 11))
3181 ; /* Comparison, do nothing. */
3182 else if (op == 15 && rn > 17)
3183 /* Integer result. */
3184 gen_mov_vreg_F0(0, rd);
3185 else if (op == 15 && rn == 15)
3186 /* conversion */
3187 gen_mov_vreg_F0(!dp, rd);
3188 else
3189 gen_mov_vreg_F0(dp, rd);
3190
3191 /* break out of the loop if we have finished */
3192 if (veclen == 0)
3193 break;
3194
3195 if (op == 15 && delta_m == 0) {
3196 /* single source one-many */
3197 while (veclen--) {
3198 rd = ((rd + delta_d) & (bank_mask - 1))
3199 | (rd & bank_mask);
3200 gen_mov_vreg_F0(dp, rd);
3201 }
3202 break;
3203 }
3204 /* Setup the next operands. */
3205 veclen--;
3206 rd = ((rd + delta_d) & (bank_mask - 1))
3207 | (rd & bank_mask);
3208
3209 if (op == 15) {
3210 /* One source operand. */
3211 rm = ((rm + delta_m) & (bank_mask - 1))
3212 | (rm & bank_mask);
3213 gen_mov_F0_vreg(dp, rm);
3214 } else {
3215 /* Two source operands. */
3216 rn = ((rn + delta_d) & (bank_mask - 1))
3217 | (rn & bank_mask);
3218 gen_mov_F0_vreg(dp, rn);
3219 if (delta_m) {
3220 rm = ((rm + delta_m) & (bank_mask - 1))
3221 | (rm & bank_mask);
3222 gen_mov_F1_vreg(dp, rm);
3223 }
3224 }
3225 }
3226 }
3227 break;
3228 case 0xc:
3229 case 0xd:
9ee6e8bb 3230 if (dp && (insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3231 /* two-register transfer */
3232 rn = (insn >> 16) & 0xf;
3233 rd = (insn >> 12) & 0xf;
3234 if (dp) {
9ee6e8bb
PB		 3235 VFP_DREG_M(rm, insn);
3236 } else {
3237 rm = VFP_SREG_M(insn);
3238 }
b7bcbe95 3239
18c9b560 3240 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3241 /* vfp->arm */
3242 if (dp) {
4373f3ce
PB		 3243 gen_mov_F0_vreg(0, rm * 2);
3244 tmp = gen_vfp_mrs();
3245 store_reg(s, rd, tmp);
3246 gen_mov_F0_vreg(0, rm * 2 + 1);
3247 tmp = gen_vfp_mrs();
3248 store_reg(s, rn, tmp);
b7bcbe95
FB		 3249 } else {
3250 gen_mov_F0_vreg(0, rm);
4373f3ce
PB		 3251 tmp = gen_vfp_mrs();
3252 store_reg(s, rn, tmp);
b7bcbe95 3253 gen_mov_F0_vreg(0, rm + 1);
4373f3ce
PB		 3254 tmp = gen_vfp_mrs();
3255 store_reg(s, rd, tmp);
b7bcbe95
FB		 3256 }
3257 } else {
3258 /* arm->vfp */
3259 if (dp) {
4373f3ce
PB		 3260 tmp = load_reg(s, rd);
3261 gen_vfp_msr(tmp);
3262 gen_mov_vreg_F0(0, rm * 2);
3263 tmp = load_reg(s, rn);
3264 gen_vfp_msr(tmp);
3265 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3266 } else {
4373f3ce
PB		 3267 tmp = load_reg(s, rn);
3268 gen_vfp_msr(tmp);
b7bcbe95 3269 gen_mov_vreg_F0(0, rm);
4373f3ce
PB		 3270 tmp = load_reg(s, rd);
3271 gen_vfp_msr(tmp);
b7bcbe95
FB		 3272 gen_mov_vreg_F0(0, rm + 1);
3273 }
3274 }
3275 } else {
3276 /* Load/store */
3277 rn = (insn >> 16) & 0xf;
3278 if (dp)
9ee6e8bb 3279 VFP_DREG_D(rd, insn);
b7bcbe95 3280 else
9ee6e8bb
PB		 3281 rd = VFP_SREG_D(insn);
3282 if (s->thumb && rn == 15) {
312eea9f
FN		 3283 addr = new_tmp();
3284 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3285 } else {
312eea9f 3286 addr = load_reg(s, rn);
9ee6e8bb 3287 }
b7bcbe95
FB		 3288 if ((insn & 0x01200000) == 0x01000000) {
3289 /* Single load/store */
3290 offset = (insn & 0xff) << 2;
3291 if ((insn & (1 << 23)) == 0)
3292 offset = -offset;
312eea9f 3293 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3294 if (insn & (1 << 20)) {
312eea9f 3295 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3296 gen_mov_vreg_F0(dp, rd);
3297 } else {
3298 gen_mov_F0_vreg(dp, rd);
312eea9f 3299 gen_vfp_st(s, dp, addr);
b7bcbe95 3300 }
312eea9f 3301 dead_tmp(addr);
b7bcbe95
FB		 3302 } else {
3303 /* load/store multiple */
3304 if (dp)
3305 n = (insn >> 1) & 0x7f;
3306 else
3307 n = insn & 0xff;
3308
3309 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3310 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3311
3312 if (dp)
3313 offset = 8;
3314 else
3315 offset = 4;
3316 for (i = 0; i < n; i++) {
18c9b560 3317 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3318 /* load */
312eea9f 3319 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3320 gen_mov_vreg_F0(dp, rd + i);
3321 } else {
3322 /* store */
3323 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3324 gen_vfp_st(s, dp, addr);
b7bcbe95 3325 }
312eea9f 3326 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3327 }
3328 if (insn & (1 << 21)) {
3329 /* writeback */
3330 if (insn & (1 << 24))
3331 offset = -offset * n;
3332 else if (dp && (insn & 1))
3333 offset = 4;
3334 else
3335 offset = 0;
3336
3337 if (offset != 0)
312eea9f
FN		 3338 tcg_gen_addi_i32(addr, addr, offset);
3339 store_reg(s, rn, addr);
3340 } else {
3341 dead_tmp(addr);
b7bcbe95
FB		 3342 }
3343 }
3344 }
3345 break;
3346 default:
3347 /* Should never happen. */
3348 return 1;
3349 }
3350 return 0;
3351}
3352
6e256c93 3353static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3354{
6e256c93
FB		 3355 TranslationBlock *tb;
3356
3357 tb = s->tb;
3358 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3359 tcg_gen_goto_tb(n);
8984bd2e 3360 gen_set_pc_im(dest);
57fec1fe 3361 tcg_gen_exit_tb((long)tb + n);
6e256c93 3362 } else {
8984bd2e 3363 gen_set_pc_im(dest);
57fec1fe 3364 tcg_gen_exit_tb(0);
6e256c93 3365 }
c53be334
FB		 3366}
3367
8aaca4c0
FB		 3368static inline void gen_jmp (DisasContext *s, uint32_t dest)
3369{
551bd27f 3370 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3371 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3372 if (s->thumb)
d9ba4830
PB		 3373 dest |= 1;
3374 gen_bx_im(s, dest);
8aaca4c0 3375 } else {
6e256c93 3376 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3377 s->is_jmp = DISAS_TB_JUMP;
3378 }
3379}
3380
d9ba4830 3381static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3382{
ee097184 3383 if (x)
d9ba4830 3384 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3385 else
d9ba4830 3386 gen_sxth(t0);
ee097184 3387 if (y)
d9ba4830 3388 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3389 else
d9ba4830
PB		 3390 gen_sxth(t1);
3391 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3392}
3393
3394/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3395static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3396 uint32_t mask;
3397
3398 mask = 0;
3399 if (flags & (1 << 0))
3400 mask |= 0xff;
3401 if (flags & (1 << 1))
3402 mask |= 0xff00;
3403 if (flags & (1 << 2))
3404 mask |= 0xff0000;
3405 if (flags & (1 << 3))
3406 mask |= 0xff000000;
9ee6e8bb 3407
2ae23e75 3408 /* Mask out undefined bits. */
9ee6e8bb
PB		 3409 mask &= ~CPSR_RESERVED;
3410 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3411 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3412 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3413 mask &= ~CPSR_IT;
9ee6e8bb 3414 /* Mask out execution state bits. */
2ae23e75 3415 if (!spsr)
e160c51c 3416 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3417 /* Mask out privileged bits. */
3418 if (IS_USER(s))
9ee6e8bb 3419 mask &= CPSR_USER;
b5ff1b31
FB		 3420 return mask;
3421}
3422
2fbac54b
FN		 3423/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3424static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3425{
d9ba4830 3426 TCGv tmp;
b5ff1b31
FB		 3427 if (spsr) {
3428 /* ??? This is also undefined in system mode. */
3429 if (IS_USER(s))
3430 return 1;
d9ba4830
PB		 3431
3432 tmp = load_cpu_field(spsr);
3433 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3434 tcg_gen_andi_i32(t0, t0, mask);
3435 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3436 store_cpu_field(tmp, spsr);
b5ff1b31 3437 } else {
2fbac54b 3438 gen_set_cpsr(t0, mask);
b5ff1b31 3439 }
2fbac54b 3440 dead_tmp(t0);
b5ff1b31
FB		 3441 gen_lookup_tb(s);
3442 return 0;
3443}
3444
2fbac54b
FN		 3445/* Returns nonzero if access to the PSR is not permitted. */
3446static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3447{
3448 TCGv tmp;
3449 tmp = new_tmp();
3450 tcg_gen_movi_i32(tmp, val);
3451 return gen_set_psr(s, mask, spsr, tmp);
3452}
3453
e9bb4aa9
JR		 3454/* Generate an old-style exception return. Marks pc as dead. */
3455static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3456{
d9ba4830 3457 TCGv tmp;
e9bb4aa9 3458 store_reg(s, 15, pc);
d9ba4830
PB		 3459 tmp = load_cpu_field(spsr);
3460 gen_set_cpsr(tmp, 0xffffffff);
3461 dead_tmp(tmp);
b5ff1b31
FB		 3462 s->is_jmp = DISAS_UPDATE;
3463}
3464
b0109805
PB		 3465/* Generate a v6 exception return. Marks both values as dead. */
3466static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3467{
b0109805
PB		 3468 gen_set_cpsr(cpsr, 0xffffffff);
3469 dead_tmp(cpsr);
3470 store_reg(s, 15, pc);
9ee6e8bb
PB		 3471 s->is_jmp = DISAS_UPDATE;
3472}
3b46e624 3473
9ee6e8bb
PB		 3474static inline void
3475gen_set_condexec (DisasContext *s)
3476{
3477 if (s->condexec_mask) {
8f01245e
PB		 3478 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3479 TCGv tmp = new_tmp();
3480 tcg_gen_movi_i32(tmp, val);
d9ba4830 3481 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3482 }
3483}
3b46e624 3484
9ee6e8bb
PB		 3485static void gen_nop_hint(DisasContext *s, int val)
3486{
3487 switch (val) {
3488 case 3: /* wfi */
8984bd2e 3489 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3490 s->is_jmp = DISAS_WFI;
3491 break;
3492 case 2: /* wfe */
3493 case 4: /* sev */
3494 /* TODO: Implement SEV and WFE. May help SMP performance. */
3495 default: /* nop */
3496 break;
3497 }
3498}
99c475ab 3499
ad69471c 3500#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3501
dd8fbd78 3502static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3503{
3504 switch (size) {
dd8fbd78
FN		 3505 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3506 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3507 case 2: tcg_gen_add_i32(t0, t0, t1); break;
9ee6e8bb
PB		 3508 default: return 1;
3509 }
3510 return 0;
3511}
3512
dd8fbd78 3513static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3514{
3515 switch (size) {
dd8fbd78
FN		 3516 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3517 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3518 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3519 default: return;
3520 }
3521}
3522
3523/* 32-bit pairwise ops end up the same as the elementwise versions. */
3524#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3525#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3526#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3527#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3528
3529/* FIXME: This is wrong. They set the wrong overflow bit. */
3530#define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3531#define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3532#define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3533#define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3534
3535#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3536 switch ((size << 1) | u) { \
3537 case 0: \
dd8fbd78 3538 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3539 break; \
3540 case 1: \
dd8fbd78 3541 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3542 break; \
3543 case 2: \
dd8fbd78 3544 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3545 break; \
3546 case 3: \
dd8fbd78 3547 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3548 break; \
3549 case 4: \
dd8fbd78 3550 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3551 break; \
3552 case 5: \
dd8fbd78 3553 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3554 break; \
3555 default: return 1; \
3556 }} while (0)
9ee6e8bb
PB		 3557
3558#define GEN_NEON_INTEGER_OP(name) do { \
3559 switch ((size << 1) | u) { \
ad69471c 3560 case 0: \
dd8fbd78 3561 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3562 break; \
3563 case 1: \
dd8fbd78 3564 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3565 break; \
3566 case 2: \
dd8fbd78 3567 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3568 break; \
3569 case 3: \
dd8fbd78 3570 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3571 break; \
3572 case 4: \
dd8fbd78 3573 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3574 break; \
3575 case 5: \
dd8fbd78 3576 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3577 break; \
9ee6e8bb
PB		 3578 default: return 1; \
3579 }} while (0)
3580
dd8fbd78 3581static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3582{
dd8fbd78
FN		 3583 TCGv tmp = new_tmp();
3584 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3585 return tmp;
9ee6e8bb
PB		 3586}
3587
dd8fbd78 3588static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3589{
dd8fbd78
FN		 3590 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3591 dead_tmp(var);
9ee6e8bb
PB		 3592}
3593
dd8fbd78 3594static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3595{
dd8fbd78 3596 TCGv tmp;
9ee6e8bb 3597 if (size == 1) {
dd8fbd78 3598 tmp = neon_load_reg(reg >> 1, reg & 1);
9ee6e8bb 3599 } else {
dd8fbd78
FN		 3600 tmp = neon_load_reg(reg >> 2, (reg >> 1) & 1);
3601 if (reg & 1) {
3602 gen_neon_dup_low16(tmp);
3603 } else {
3604 gen_neon_dup_high16(tmp);
3605 }
9ee6e8bb 3606 }
dd8fbd78 3607 return tmp;
9ee6e8bb
PB		 3608}
3609
19457615
FN		 3610static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3611{
3612 TCGv rd, rm, tmp;
3613
3614 rd = new_tmp();
3615 rm = new_tmp();
3616 tmp = new_tmp();
3617
3618 tcg_gen_andi_i32(rd, t0, 0xff);
3619 tcg_gen_shri_i32(tmp, t0, 8);
3620 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3621 tcg_gen_or_i32(rd, rd, tmp);
3622 tcg_gen_shli_i32(tmp, t1, 16);
3623 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3624 tcg_gen_or_i32(rd, rd, tmp);
3625 tcg_gen_shli_i32(tmp, t1, 8);
3626 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3627 tcg_gen_or_i32(rd, rd, tmp);
3628
3629 tcg_gen_shri_i32(rm, t0, 8);
3630 tcg_gen_andi_i32(rm, rm, 0xff);
3631 tcg_gen_shri_i32(tmp, t0, 16);
3632 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3633 tcg_gen_or_i32(rm, rm, tmp);
3634 tcg_gen_shli_i32(tmp, t1, 8);
3635 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3636 tcg_gen_or_i32(rm, rm, tmp);
3637 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3638 tcg_gen_or_i32(t1, rm, tmp);
3639 tcg_gen_mov_i32(t0, rd);
3640
3641 dead_tmp(tmp);
3642 dead_tmp(rm);
3643 dead_tmp(rd);
3644}
3645
3646static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3647{
3648 TCGv rd, rm, tmp;
3649
3650 rd = new_tmp();
3651 rm = new_tmp();
3652 tmp = new_tmp();
3653
3654 tcg_gen_andi_i32(rd, t0, 0xff);
3655 tcg_gen_shli_i32(tmp, t1, 8);
3656 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3657 tcg_gen_or_i32(rd, rd, tmp);
3658 tcg_gen_shli_i32(tmp, t0, 16);
3659 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3660 tcg_gen_or_i32(rd, rd, tmp);
3661 tcg_gen_shli_i32(tmp, t1, 24);
3662 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3663 tcg_gen_or_i32(rd, rd, tmp);
3664
3665 tcg_gen_andi_i32(rm, t1, 0xff000000);
3666 tcg_gen_shri_i32(tmp, t0, 8);
3667 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3668 tcg_gen_or_i32(rm, rm, tmp);
3669 tcg_gen_shri_i32(tmp, t1, 8);
3670 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3671 tcg_gen_or_i32(rm, rm, tmp);
3672 tcg_gen_shri_i32(tmp, t0, 16);
3673 tcg_gen_andi_i32(tmp, tmp, 0xff);
3674 tcg_gen_or_i32(t1, rm, tmp);
3675 tcg_gen_mov_i32(t0, rd);
3676
3677 dead_tmp(tmp);
3678 dead_tmp(rm);
3679 dead_tmp(rd);
3680}
3681
3682static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3683{
3684 TCGv tmp, tmp2;
3685
3686 tmp = new_tmp();
3687 tmp2 = new_tmp();
3688
3689 tcg_gen_andi_i32(tmp, t0, 0xffff);
3690 tcg_gen_shli_i32(tmp2, t1, 16);
3691 tcg_gen_or_i32(tmp, tmp, tmp2);
3692 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3693 tcg_gen_shri_i32(tmp2, t0, 16);
3694 tcg_gen_or_i32(t1, t1, tmp2);
3695 tcg_gen_mov_i32(t0, tmp);
3696
3697 dead_tmp(tmp2);
3698 dead_tmp(tmp);
3699}
3700
9ee6e8bb
PB		 3701static void gen_neon_unzip(int reg, int q, int tmp, int size)
3702{
3703 int n;
dd8fbd78 3704 TCGv t0, t1;
9ee6e8bb
PB		 3705
3706 for (n = 0; n < q + 1; n += 2) {
dd8fbd78
FN		 3707 t0 = neon_load_reg(reg, n);
3708 t1 = neon_load_reg(reg, n + 1);
9ee6e8bb 3709 switch (size) {
dd8fbd78
FN		 3710 case 0: gen_neon_unzip_u8(t0, t1); break;
3711 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
9ee6e8bb
PB		 3712 case 2: /* no-op */; break;
3713 default: abort();
3714 }
dd8fbd78
FN		 3715 neon_store_scratch(tmp + n, t0);
3716 neon_store_scratch(tmp + n + 1, t1);
9ee6e8bb
PB		 3717 }
3718}
3719
19457615
FN		 3720static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3721{
3722 TCGv rd, tmp;
3723
3724 rd = new_tmp();
3725 tmp = new_tmp();
3726
3727 tcg_gen_shli_i32(rd, t0, 8);
3728 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3729 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3730 tcg_gen_or_i32(rd, rd, tmp);
3731
3732 tcg_gen_shri_i32(t1, t1, 8);
3733 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3734 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3735 tcg_gen_or_i32(t1, t1, tmp);
3736 tcg_gen_mov_i32(t0, rd);
3737
3738 dead_tmp(tmp);
3739 dead_tmp(rd);
3740}
3741
3742static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3743{
3744 TCGv rd, tmp;
3745
3746 rd = new_tmp();
3747 tmp = new_tmp();
3748
3749 tcg_gen_shli_i32(rd, t0, 16);
3750 tcg_gen_andi_i32(tmp, t1, 0xffff);
3751 tcg_gen_or_i32(rd, rd, tmp);
3752 tcg_gen_shri_i32(t1, t1, 16);
3753 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3754 tcg_gen_or_i32(t1, t1, tmp);
3755 tcg_gen_mov_i32(t0, rd);
3756
3757 dead_tmp(tmp);
3758 dead_tmp(rd);
3759}
3760
3761
9ee6e8bb
PB		 3762static struct {
3763 int nregs;
3764 int interleave;
3765 int spacing;
3766} neon_ls_element_type[11] = {
3767 {4, 4, 1},
3768 {4, 4, 2},
3769 {4, 1, 1},
3770 {4, 2, 1},
3771 {3, 3, 1},
3772 {3, 3, 2},
3773 {3, 1, 1},
3774 {1, 1, 1},
3775 {2, 2, 1},
3776 {2, 2, 2},
3777 {2, 1, 1}
3778};
3779
3780/* Translate a NEON load/store element instruction. Return nonzero if the
3781 instruction is invalid. */
3782static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3783{
3784 int rd, rn, rm;
3785 int op;
3786 int nregs;
3787 int interleave;
84496233 3788 int spacing;
9ee6e8bb
PB		 3789 int stride;
3790 int size;
3791 int reg;
3792 int pass;
3793 int load;
3794 int shift;
9ee6e8bb 3795 int n;
1b2b1e54 3796 TCGv addr;
b0109805 3797 TCGv tmp;
8f8e3aa4 3798 TCGv tmp2;
84496233 3799 TCGv_i64 tmp64;
9ee6e8bb
PB		 3800
3801 if (!vfp_enabled(env))
3802 return 1;
3803 VFP_DREG_D(rd, insn);
3804 rn = (insn >> 16) & 0xf;
3805 rm = insn & 0xf;
3806 load = (insn & (1 << 21)) != 0;
1b2b1e54 3807 addr = new_tmp();
9ee6e8bb
PB		 3808 if ((insn & (1 << 23)) == 0) {
3809 /* Load store all elements. */
3810 op = (insn >> 8) & 0xf;
3811 size = (insn >> 6) & 3;
84496233 3812 if (op > 10)
9ee6e8bb
PB		 3813 return 1;
3814 nregs = neon_ls_element_type[op].nregs;
3815 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3816 spacing = neon_ls_element_type[op].spacing;
3817 if (size == 3 && (interleave | spacing) != 1)
3818 return 1;
dcc65026 3819 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3820 stride = (1 << size) * interleave;
3821 for (reg = 0; reg < nregs; reg++) {
3822 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3823 load_reg_var(s, addr, rn);
3824 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3825 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3826 load_reg_var(s, addr, rn);
3827 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3828 }
84496233
JR		 3829 if (size == 3) {
3830 if (load) {
3831 tmp64 = gen_ld64(addr, IS_USER(s));
3832 neon_store_reg64(tmp64, rd);
3833 tcg_temp_free_i64(tmp64);
3834 } else {
3835 tmp64 = tcg_temp_new_i64();
3836 neon_load_reg64(tmp64, rd);
3837 gen_st64(tmp64, addr, IS_USER(s));
3838 }
3839 tcg_gen_addi_i32(addr, addr, stride);
3840 } else {
3841 for (pass = 0; pass < 2; pass++) {
3842 if (size == 2) {
3843 if (load) {
3844 tmp = gen_ld32(addr, IS_USER(s));
3845 neon_store_reg(rd, pass, tmp);
3846 } else {
3847 tmp = neon_load_reg(rd, pass);
3848 gen_st32(tmp, addr, IS_USER(s));
3849 }
1b2b1e54 3850 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3851 } else if (size == 1) {
3852 if (load) {
3853 tmp = gen_ld16u(addr, IS_USER(s));
3854 tcg_gen_addi_i32(addr, addr, stride);
3855 tmp2 = gen_ld16u(addr, IS_USER(s));
3856 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3857 tcg_gen_shli_i32(tmp2, tmp2, 16);
3858 tcg_gen_or_i32(tmp, tmp, tmp2);
84496233
JR		 3859 dead_tmp(tmp2);
3860 neon_store_reg(rd, pass, tmp);
3861 } else {
3862 tmp = neon_load_reg(rd, pass);
3863 tmp2 = new_tmp();
3864 tcg_gen_shri_i32(tmp2, tmp, 16);
3865 gen_st16(tmp, addr, IS_USER(s));
3866 tcg_gen_addi_i32(addr, addr, stride);
3867 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3868 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3869 }
84496233
JR		 3870 } else /* size == 0 */ {
3871 if (load) {
3872 TCGV_UNUSED(tmp2);
3873 for (n = 0; n < 4; n++) {
3874 tmp = gen_ld8u(addr, IS_USER(s));
3875 tcg_gen_addi_i32(addr, addr, stride);
3876 if (n == 0) {
3877 tmp2 = tmp;
3878 } else {
41ba8341
PB		 3879 tcg_gen_shli_i32(tmp, tmp, n * 8);
3880 tcg_gen_or_i32(tmp2, tmp2, tmp);
84496233
JR		 3881 dead_tmp(tmp);
3882 }
9ee6e8bb 3883 }
84496233
JR		 3884 neon_store_reg(rd, pass, tmp2);
3885 } else {
3886 tmp2 = neon_load_reg(rd, pass);
3887 for (n = 0; n < 4; n++) {
3888 tmp = new_tmp();
3889 if (n == 0) {
3890 tcg_gen_mov_i32(tmp, tmp2);
3891 } else {
3892 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3893 }
3894 gen_st8(tmp, addr, IS_USER(s));
3895 tcg_gen_addi_i32(addr, addr, stride);
3896 }
3897 dead_tmp(tmp2);
9ee6e8bb
PB		 3898 }
3899 }
3900 }
3901 }
84496233 3902 rd += spacing;
9ee6e8bb
PB		 3903 }
3904 stride = nregs * 8;
3905 } else {
3906 size = (insn >> 10) & 3;
3907 if (size == 3) {
3908 /* Load single element to all lanes. */
3909 if (!load)
3910 return 1;
3911 size = (insn >> 6) & 3;
3912 nregs = ((insn >> 8) & 3) + 1;
3913 stride = (insn & (1 << 5)) ? 2 : 1;
dcc65026 3914 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3915 for (reg = 0; reg < nregs; reg++) {
3916 switch (size) {
3917 case 0:
1b2b1e54 3918 tmp = gen_ld8u(addr, IS_USER(s));
ad69471c 3919 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3920 break;
3921 case 1:
1b2b1e54 3922 tmp = gen_ld16u(addr, IS_USER(s));
ad69471c 3923 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3924 break;
3925 case 2:
1b2b1e54 3926 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 3927 break;
3928 case 3:
3929 return 1;
a50f5b91
PB		 3930 default: /* Avoid compiler warnings. */
3931 abort();
99c475ab 3932 }
1b2b1e54 3933 tcg_gen_addi_i32(addr, addr, 1 << size);
ad69471c
PB		 3934 tmp2 = new_tmp();
3935 tcg_gen_mov_i32(tmp2, tmp);
3936 neon_store_reg(rd, 0, tmp2);
3018f259 3937 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 3938 rd += stride;
3939 }
3940 stride = (1 << size) * nregs;
3941 } else {
3942 /* Single element. */
3943 pass = (insn >> 7) & 1;
3944 switch (size) {
3945 case 0:
3946 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3947 stride = 1;
3948 break;
3949 case 1:
3950 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3951 stride = (insn & (1 << 5)) ? 2 : 1;
3952 break;
3953 case 2:
3954 shift = 0;
9ee6e8bb
PB		 3955 stride = (insn & (1 << 6)) ? 2 : 1;
3956 break;
3957 default:
3958 abort();
3959 }
3960 nregs = ((insn >> 8) & 3) + 1;
dcc65026 3961 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3962 for (reg = 0; reg < nregs; reg++) {
3963 if (load) {
9ee6e8bb
PB		 3964 switch (size) {
3965 case 0:
1b2b1e54 3966 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 3967 break;
3968 case 1:
1b2b1e54 3969 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 3970 break;
3971 case 2:
1b2b1e54 3972 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 3973 break;
a50f5b91
PB		 3974 default: /* Avoid compiler warnings. */
3975 abort();
9ee6e8bb
PB		 3976 }
3977 if (size != 2) {
8f8e3aa4
PB		 3978 tmp2 = neon_load_reg(rd, pass);
3979 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3980 dead_tmp(tmp2);
9ee6e8bb 3981 }
8f8e3aa4 3982 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3983 } else { /* Store */
8f8e3aa4
PB		 3984 tmp = neon_load_reg(rd, pass);
3985 if (shift)
3986 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3987 switch (size) {
3988 case 0:
1b2b1e54 3989 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3990 break;
3991 case 1:
1b2b1e54 3992 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3993 break;
3994 case 2:
1b2b1e54 3995 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 3996 break;
99c475ab 3997 }
99c475ab 3998 }
9ee6e8bb 3999 rd += stride;
1b2b1e54 4000 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 4001 }
9ee6e8bb 4002 stride = nregs * (1 << size);
99c475ab 4003 }
9ee6e8bb 4004 }
1b2b1e54 4005 dead_tmp(addr);
9ee6e8bb 4006 if (rm != 15) {
b26eefb6
PB		 4007 TCGv base;
4008
4009 base = load_reg(s, rn);
9ee6e8bb 4010 if (rm == 13) {
b26eefb6 4011 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4012 } else {
b26eefb6
PB		 4013 TCGv index;
4014 index = load_reg(s, rm);
4015 tcg_gen_add_i32(base, base, index);
4016 dead_tmp(index);
9ee6e8bb 4017 }
b26eefb6 4018 store_reg(s, rn, base);
9ee6e8bb
PB		 4019 }
4020 return 0;
4021}
3b46e624 4022
8f8e3aa4
PB		 4023/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4024static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4025{
4026 tcg_gen_and_i32(t, t, c);
f669df27 4027 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4028 tcg_gen_or_i32(dest, t, f);
4029}
4030
a7812ae4 4031static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4032{
4033 switch (size) {
4034 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4035 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4036 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4037 default: abort();
4038 }
4039}
4040
a7812ae4 4041static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4042{
4043 switch (size) {
4044 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4045 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4046 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4047 default: abort();
4048 }
4049}
4050
a7812ae4 4051static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4052{
4053 switch (size) {
4054 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4055 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4056 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4057 default: abort();
4058 }
4059}
4060
4061static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4062 int q, int u)
4063{
4064 if (q) {
4065 if (u) {
4066 switch (size) {
4067 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4068 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4069 default: abort();
4070 }
4071 } else {
4072 switch (size) {
4073 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4074 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4075 default: abort();
4076 }
4077 }
4078 } else {
4079 if (u) {
4080 switch (size) {
4081 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4082 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4083 default: abort();
4084 }
4085 } else {
4086 switch (size) {
4087 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4088 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4089 default: abort();
4090 }
4091 }
4092 }
4093}
4094
a7812ae4 4095static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4096{
4097 if (u) {
4098 switch (size) {
4099 case 0: gen_helper_neon_widen_u8(dest, src); break;
4100 case 1: gen_helper_neon_widen_u16(dest, src); break;
4101 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4102 default: abort();
4103 }
4104 } else {
4105 switch (size) {
4106 case 0: gen_helper_neon_widen_s8(dest, src); break;
4107 case 1: gen_helper_neon_widen_s16(dest, src); break;
4108 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4109 default: abort();
4110 }
4111 }
4112 dead_tmp(src);
4113}
4114
4115static inline void gen_neon_addl(int size)
4116{
4117 switch (size) {
4118 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4119 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4120 case 2: tcg_gen_add_i64(CPU_V001); break;
4121 default: abort();
4122 }
4123}
4124
4125static inline void gen_neon_subl(int size)
4126{
4127 switch (size) {
4128 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4129 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4130 case 2: tcg_gen_sub_i64(CPU_V001); break;
4131 default: abort();
4132 }
4133}
4134
a7812ae4 4135static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4136{
4137 switch (size) {
4138 case 0: gen_helper_neon_negl_u16(var, var); break;
4139 case 1: gen_helper_neon_negl_u32(var, var); break;
4140 case 2: gen_helper_neon_negl_u64(var, var); break;
4141 default: abort();
4142 }
4143}
4144
a7812ae4 4145static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4146{
4147 switch (size) {
4148 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4149 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4150 default: abort();
4151 }
4152}
4153
a7812ae4 4154static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4155{
a7812ae4 4156 TCGv_i64 tmp;
ad69471c
PB		 4157
4158 switch ((size << 1) | u) {
4159 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4160 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4161 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4162 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4163 case 4:
4164 tmp = gen_muls_i64_i32(a, b);
4165 tcg_gen_mov_i64(dest, tmp);
4166 break;
4167 case 5:
4168 tmp = gen_mulu_i64_i32(a, b);
4169 tcg_gen_mov_i64(dest, tmp);
4170 break;
4171 default: abort();
4172 }
ad69471c
PB		 4173}
4174
9ee6e8bb
PB		 4175/* Translate a NEON data processing instruction. Return nonzero if the
4176 instruction is invalid.
ad69471c
PB		 4177 We process data in a mixture of 32-bit and 64-bit chunks.
4178 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4179
9ee6e8bb
PB		 4180static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4181{
4182 int op;
4183 int q;
4184 int rd, rn, rm;
4185 int size;
4186 int shift;
4187 int pass;
4188 int count;
4189 int pairwise;
4190 int u;
4191 int n;
ca9a32e4 4192 uint32_t imm, mask;
b75263d6 4193 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4194 TCGv_i64 tmp64;
9ee6e8bb
PB		 4195
4196 if (!vfp_enabled(env))
4197 return 1;
4198 q = (insn & (1 << 6)) != 0;
4199 u = (insn >> 24) & 1;
4200 VFP_DREG_D(rd, insn);
4201 VFP_DREG_N(rn, insn);
4202 VFP_DREG_M(rm, insn);
4203 size = (insn >> 20) & 3;
4204 if ((insn & (1 << 23)) == 0) {
4205 /* Three register same length. */
4206 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4207 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4208 || op == 10 || op == 11 || op == 16)) {
4209 /* 64-bit element instructions. */
9ee6e8bb 4210 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4211 neon_load_reg64(cpu_V0, rn + pass);
4212 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4213 switch (op) {
4214 case 1: /* VQADD */
4215 if (u) {
ad69471c 4216 gen_helper_neon_add_saturate_u64(CPU_V001);
2c0262af 4217 } else {
ad69471c 4218 gen_helper_neon_add_saturate_s64(CPU_V001);
2c0262af 4219 }
9ee6e8bb
PB		 4220 break;
4221 case 5: /* VQSUB */
4222 if (u) {
ad69471c
PB		 4223 gen_helper_neon_sub_saturate_u64(CPU_V001);
4224 } else {
4225 gen_helper_neon_sub_saturate_s64(CPU_V001);
4226 }
4227 break;
4228 case 8: /* VSHL */
4229 if (u) {
4230 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4231 } else {
4232 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4233 }
4234 break;
4235 case 9: /* VQSHL */
4236 if (u) {
4237 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4238 cpu_V0, cpu_V0);
4239 } else {
4240 gen_helper_neon_qshl_s64(cpu_V1, cpu_env,
4241 cpu_V1, cpu_V0);
4242 }
4243 break;
4244 case 10: /* VRSHL */
4245 if (u) {
4246 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4247 } else {
ad69471c
PB		 4248 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4249 }
4250 break;
4251 case 11: /* VQRSHL */
4252 if (u) {
4253 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4254 cpu_V1, cpu_V0);
4255 } else {
4256 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4257 cpu_V1, cpu_V0);
1e8d4eec 4258 }
9ee6e8bb
PB		 4259 break;
4260 case 16:
4261 if (u) {
ad69471c 4262 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4263 } else {
ad69471c 4264 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4265 }
4266 break;
4267 default:
4268 abort();
2c0262af 4269 }
ad69471c 4270 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4271 }
9ee6e8bb 4272 return 0;
2c0262af 4273 }
9ee6e8bb
PB		 4274 switch (op) {
4275 case 8: /* VSHL */
4276 case 9: /* VQSHL */
4277 case 10: /* VRSHL */
ad69471c 4278 case 11: /* VQRSHL */
9ee6e8bb 4279 {
ad69471c
PB		 4280 int rtmp;
4281 /* Shift instruction operands are reversed. */
4282 rtmp = rn;
9ee6e8bb 4283 rn = rm;
ad69471c 4284 rm = rtmp;
9ee6e8bb
PB		 4285 pairwise = 0;
4286 }
2c0262af 4287 break;
9ee6e8bb
PB		 4288 case 20: /* VPMAX */
4289 case 21: /* VPMIN */
4290 case 23: /* VPADD */
4291 pairwise = 1;
2c0262af 4292 break;
9ee6e8bb
PB		 4293 case 26: /* VPADD (float) */
4294 pairwise = (u && size < 2);
2c0262af 4295 break;
9ee6e8bb
PB		 4296 case 30: /* VPMIN/VPMAX (float) */
4297 pairwise = u;
2c0262af 4298 break;
9ee6e8bb
PB		 4299 default:
4300 pairwise = 0;
2c0262af 4301 break;
9ee6e8bb 4302 }
dd8fbd78 4303
9ee6e8bb
PB		 4304 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4305
4306 if (pairwise) {
4307 /* Pairwise. */
4308 if (q)
4309 n = (pass & 1) * 2;
2c0262af 4310 else
9ee6e8bb
PB		 4311 n = 0;
4312 if (pass < q + 1) {
dd8fbd78
FN		 4313 tmp = neon_load_reg(rn, n);
4314 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4315 } else {
dd8fbd78
FN		 4316 tmp = neon_load_reg(rm, n);
4317 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4318 }
4319 } else {
4320 /* Elementwise. */
dd8fbd78
FN		 4321 tmp = neon_load_reg(rn, pass);
4322 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4323 }
4324 switch (op) {
4325 case 0: /* VHADD */
4326 GEN_NEON_INTEGER_OP(hadd);
4327 break;
4328 case 1: /* VQADD */
ad69471c 4329 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4330 break;
9ee6e8bb
PB		 4331 case 2: /* VRHADD */
4332 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4333 break;
9ee6e8bb
PB		 4334 case 3: /* Logic ops. */
4335 switch ((u << 2) | size) {
4336 case 0: /* VAND */
dd8fbd78 4337 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4338 break;
4339 case 1: /* BIC */
f669df27 4340 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4341 break;
4342 case 2: /* VORR */
dd8fbd78 4343 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4344 break;
4345 case 3: /* VORN */
f669df27 4346 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4347 break;
4348 case 4: /* VEOR */
dd8fbd78 4349 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4350 break;
4351 case 5: /* VBSL */
dd8fbd78
FN		 4352 tmp3 = neon_load_reg(rd, pass);
4353 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4354 dead_tmp(tmp3);
9ee6e8bb
PB		 4355 break;
4356 case 6: /* VBIT */
dd8fbd78
FN		 4357 tmp3 = neon_load_reg(rd, pass);
4358 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4359 dead_tmp(tmp3);
9ee6e8bb
PB		 4360 break;
4361 case 7: /* VBIF */
dd8fbd78
FN		 4362 tmp3 = neon_load_reg(rd, pass);
4363 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4364 dead_tmp(tmp3);
9ee6e8bb 4365 break;
2c0262af
FB		 4366 }
4367 break;
9ee6e8bb
PB		 4368 case 4: /* VHSUB */
4369 GEN_NEON_INTEGER_OP(hsub);
4370 break;
4371 case 5: /* VQSUB */
ad69471c 4372 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4373 break;
9ee6e8bb
PB		 4374 case 6: /* VCGT */
4375 GEN_NEON_INTEGER_OP(cgt);
4376 break;
4377 case 7: /* VCGE */
4378 GEN_NEON_INTEGER_OP(cge);
4379 break;
4380 case 8: /* VSHL */
ad69471c 4381 GEN_NEON_INTEGER_OP(shl);
2c0262af 4382 break;
9ee6e8bb 4383 case 9: /* VQSHL */
ad69471c 4384 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4385 break;
9ee6e8bb 4386 case 10: /* VRSHL */
ad69471c 4387 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4388 break;
9ee6e8bb 4389 case 11: /* VQRSHL */
ad69471c 4390 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4391 break;
4392 case 12: /* VMAX */
4393 GEN_NEON_INTEGER_OP(max);
4394 break;
4395 case 13: /* VMIN */
4396 GEN_NEON_INTEGER_OP(min);
4397 break;
4398 case 14: /* VABD */
4399 GEN_NEON_INTEGER_OP(abd);
4400 break;
4401 case 15: /* VABA */
4402 GEN_NEON_INTEGER_OP(abd);
dd8fbd78
FN		 4403 dead_tmp(tmp2);
4404 tmp2 = neon_load_reg(rd, pass);
4405 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4406 break;
4407 case 16:
4408 if (!u) { /* VADD */
dd8fbd78 4409 if (gen_neon_add(size, tmp, tmp2))
9ee6e8bb
PB		 4410 return 1;
4411 } else { /* VSUB */
4412 switch (size) {
dd8fbd78
FN		 4413 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4414 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4415 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4416 default: return 1;
4417 }
4418 }
4419 break;
4420 case 17:
4421 if (!u) { /* VTST */
4422 switch (size) {
dd8fbd78
FN		 4423 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4424 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4425 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4426 default: return 1;
4427 }
4428 } else { /* VCEQ */
4429 switch (size) {
dd8fbd78
FN		 4430 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4431 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4432 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4433 default: return 1;
4434 }
4435 }
4436 break;
4437 case 18: /* Multiply. */
4438 switch (size) {
dd8fbd78
FN		 4439 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4440 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4441 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4442 default: return 1;
4443 }
dd8fbd78
FN		 4444 dead_tmp(tmp2);
4445 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4446 if (u) { /* VMLS */
dd8fbd78 4447 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4448 } else { /* VMLA */
dd8fbd78 4449 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4450 }
4451 break;
4452 case 19: /* VMUL */
4453 if (u) { /* polynomial */
dd8fbd78 4454 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4455 } else { /* Integer */
4456 switch (size) {
dd8fbd78
FN		 4457 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4458 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4459 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4460 default: return 1;
4461 }
4462 }
4463 break;
4464 case 20: /* VPMAX */
4465 GEN_NEON_INTEGER_OP(pmax);
4466 break;
4467 case 21: /* VPMIN */
4468 GEN_NEON_INTEGER_OP(pmin);
4469 break;
4470 case 22: /* Hultiply high. */
4471 if (!u) { /* VQDMULH */
4472 switch (size) {
dd8fbd78
FN		 4473 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4474 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4475 default: return 1;
4476 }
4477 } else { /* VQRDHMUL */
4478 switch (size) {
dd8fbd78
FN		 4479 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4480 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4481 default: return 1;
4482 }
4483 }
4484 break;
4485 case 23: /* VPADD */
4486 if (u)
4487 return 1;
4488 switch (size) {
dd8fbd78
FN		 4489 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4490 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4491 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4492 default: return 1;
4493 }
4494 break;
4495 case 26: /* Floating point arithnetic. */
4496 switch ((u << 2) | size) {
4497 case 0: /* VADD */
dd8fbd78 4498 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4499 break;
4500 case 2: /* VSUB */
dd8fbd78 4501 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4502 break;
4503 case 4: /* VPADD */
dd8fbd78 4504 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4505 break;
4506 case 6: /* VABD */
dd8fbd78 4507 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4508 break;
4509 default:
4510 return 1;
4511 }
4512 break;
4513 case 27: /* Float multiply. */
dd8fbd78 4514 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4515 if (!u) {
dd8fbd78
FN		 4516 dead_tmp(tmp2);
4517 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4518 if (size == 0) {
dd8fbd78 4519 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4520 } else {
dd8fbd78 4521 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4522 }
4523 }
4524 break;
4525 case 28: /* Float compare. */
4526 if (!u) {
dd8fbd78 4527 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4528 } else {
9ee6e8bb 4529 if (size == 0)
dd8fbd78 4530 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4531 else
dd8fbd78 4532 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4533 }
2c0262af 4534 break;
9ee6e8bb
PB		 4535 case 29: /* Float compare absolute. */
4536 if (!u)
4537 return 1;
4538 if (size == 0)
dd8fbd78 4539 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4540 else
dd8fbd78 4541 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4542 break;
9ee6e8bb
PB		 4543 case 30: /* Float min/max. */
4544 if (size == 0)
dd8fbd78 4545 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4546 else
dd8fbd78 4547 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4548 break;
4549 case 31:
4550 if (size == 0)
dd8fbd78 4551 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4552 else
dd8fbd78 4553 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4554 break;
9ee6e8bb
PB		 4555 default:
4556 abort();
2c0262af 4557 }
dd8fbd78
FN		 4558 dead_tmp(tmp2);
4559
9ee6e8bb
PB		 4560 /* Save the result. For elementwise operations we can put it
4561 straight into the destination register. For pairwise operations
4562 we have to be careful to avoid clobbering the source operands. */
4563 if (pairwise && rd == rm) {
dd8fbd78 4564 neon_store_scratch(pass, tmp);
9ee6e8bb 4565 } else {
dd8fbd78 4566 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4567 }
4568
4569 } /* for pass */
4570 if (pairwise && rd == rm) {
4571 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4572 tmp = neon_load_scratch(pass);
4573 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4574 }
4575 }
ad69471c 4576 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4577 } else if (insn & (1 << 4)) {
4578 if ((insn & 0x00380080) != 0) {
4579 /* Two registers and shift. */
4580 op = (insn >> 8) & 0xf;
4581 if (insn & (1 << 7)) {
4582 /* 64-bit shift. */
4583 size = 3;
4584 } else {
4585 size = 2;
4586 while ((insn & (1 << (size + 19))) == 0)
4587 size--;
4588 }
4589 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4590 /* To avoid excessive dumplication of ops we implement shift
4591 by immediate using the variable shift operations. */
4592 if (op < 8) {
4593 /* Shift by immediate:
4594 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4595 /* Right shifts are encoded as N - shift, where N is the
4596 element size in bits. */
4597 if (op <= 4)
4598 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4599 if (size == 3) {
4600 count = q + 1;
4601 } else {
4602 count = q ? 4: 2;
4603 }
4604 switch (size) {
4605 case 0:
4606 imm = (uint8_t) shift;
4607 imm |= imm << 8;
4608 imm |= imm << 16;
4609 break;
4610 case 1:
4611 imm = (uint16_t) shift;
4612 imm |= imm << 16;
4613 break;
4614 case 2:
4615 case 3:
4616 imm = shift;
4617 break;
4618 default:
4619 abort();
4620 }
4621
4622 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4623 if (size == 3) {
4624 neon_load_reg64(cpu_V0, rm + pass);
4625 tcg_gen_movi_i64(cpu_V1, imm);
4626 switch (op) {
4627 case 0: /* VSHR */
4628 case 1: /* VSRA */
4629 if (u)
4630 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4631 else
ad69471c 4632 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4633 break;
ad69471c
PB		 4634 case 2: /* VRSHR */
4635 case 3: /* VRSRA */
4636 if (u)
4637 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4638 else
ad69471c 4639 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4640 break;
ad69471c
PB		 4641 case 4: /* VSRI */
4642 if (!u)
4643 return 1;
4644 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4645 break;
4646 case 5: /* VSHL, VSLI */
4647 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4648 break;
4649 case 6: /* VQSHL */
4650 if (u)
4651 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4652 else
ad69471c
PB		 4653 gen_helper_neon_qshl_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4654 break;
4655 case 7: /* VQSHLU */
4656 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4657 break;
9ee6e8bb 4658 }
ad69471c
PB		 4659 if (op == 1 || op == 3) {
4660 /* Accumulate. */
4661 neon_load_reg64(cpu_V0, rd + pass);
4662 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4663 } else if (op == 4 || (op == 5 && u)) {
4664 /* Insert */
4665 cpu_abort(env, "VS[LR]I.64 not implemented");
4666 }
4667 neon_store_reg64(cpu_V0, rd + pass);
4668 } else { /* size < 3 */
4669 /* Operands in T0 and T1. */
dd8fbd78
FN		 4670 tmp = neon_load_reg(rm, pass);
4671 tmp2 = new_tmp();
4672 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4673 switch (op) {
4674 case 0: /* VSHR */
4675 case 1: /* VSRA */
4676 GEN_NEON_INTEGER_OP(shl);
4677 break;
4678 case 2: /* VRSHR */
4679 case 3: /* VRSRA */
4680 GEN_NEON_INTEGER_OP(rshl);
4681 break;
4682 case 4: /* VSRI */
4683 if (!u)
4684 return 1;
4685 GEN_NEON_INTEGER_OP(shl);
4686 break;
4687 case 5: /* VSHL, VSLI */
4688 switch (size) {
dd8fbd78
FN		 4689 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4690 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4691 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4692 default: return 1;
4693 }
4694 break;
4695 case 6: /* VQSHL */
4696 GEN_NEON_INTEGER_OP_ENV(qshl);
4697 break;
4698 case 7: /* VQSHLU */
4699 switch (size) {
dd8fbd78
FN		 4700 case 0: gen_helper_neon_qshl_u8(tmp, cpu_env, tmp, tmp2); break;
4701 case 1: gen_helper_neon_qshl_u16(tmp, cpu_env, tmp, tmp2); break;
4702 case 2: gen_helper_neon_qshl_u32(tmp, cpu_env, tmp, tmp2); break;
ad69471c
PB		 4703 default: return 1;
4704 }
4705 break;
4706 }
dd8fbd78 4707 dead_tmp(tmp2);
ad69471c
PB		 4708
4709 if (op == 1 || op == 3) {
4710 /* Accumulate. */
dd8fbd78
FN		 4711 tmp2 = neon_load_reg(rd, pass);
4712 gen_neon_add(size, tmp2, tmp);
4713 dead_tmp(tmp2);
ad69471c
PB		 4714 } else if (op == 4 || (op == 5 && u)) {
4715 /* Insert */
4716 switch (size) {
4717 case 0:
4718 if (op == 4)
ca9a32e4 4719 mask = 0xff >> -shift;
ad69471c 4720 else
ca9a32e4
JR		 4721 mask = (uint8_t)(0xff << shift);
4722 mask |= mask << 8;
4723 mask |= mask << 16;
ad69471c
PB		 4724 break;
4725 case 1:
4726 if (op == 4)
ca9a32e4 4727 mask = 0xffff >> -shift;
ad69471c 4728 else
ca9a32e4
JR		 4729 mask = (uint16_t)(0xffff << shift);
4730 mask |= mask << 16;
ad69471c
PB		 4731 break;
4732 case 2:
ca9a32e4
JR		 4733 if (shift < -31 || shift > 31) {
4734 mask = 0;
4735 } else {
4736 if (op == 4)
4737 mask = 0xffffffffu >> -shift;
4738 else
4739 mask = 0xffffffffu << shift;
4740 }
ad69471c
PB		 4741 break;
4742 default:
4743 abort();
4744 }
dd8fbd78 4745 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4746 tcg_gen_andi_i32(tmp, tmp, mask);
4747 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78
FN		 4748 tcg_gen_or_i32(tmp, tmp, tmp2);
4749 dead_tmp(tmp2);
ad69471c 4750 }
dd8fbd78 4751 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4752 }
4753 } /* for pass */
4754 } else if (op < 10) {
ad69471c 4755 /* Shift by immediate and narrow:
9ee6e8bb
PB		 4756 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4757 shift = shift - (1 << (size + 3));
4758 size++;
9ee6e8bb
PB		 4759 switch (size) {
4760 case 1:
ad69471c 4761 imm = (uint16_t)shift;
9ee6e8bb 4762 imm |= imm << 16;
ad69471c 4763 tmp2 = tcg_const_i32(imm);
a7812ae4 4764 TCGV_UNUSED_I64(tmp64);
9ee6e8bb
PB		 4765 break;
4766 case 2:
ad69471c
PB		 4767 imm = (uint32_t)shift;
4768 tmp2 = tcg_const_i32(imm);
a7812ae4 4769 TCGV_UNUSED_I64(tmp64);
4cc633c3 4770 break;
9ee6e8bb 4771 case 3:
a7812ae4
PB		 4772 tmp64 = tcg_const_i64(shift);
4773 TCGV_UNUSED(tmp2);
9ee6e8bb
PB		 4774 break;
4775 default:
4776 abort();
4777 }
4778
ad69471c
PB		 4779 for (pass = 0; pass < 2; pass++) {
4780 if (size == 3) {
4781 neon_load_reg64(cpu_V0, rm + pass);
4782 if (q) {
4783 if (u)
a7812ae4 4784 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4785 else
a7812ae4 4786 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c
PB		 4787 } else {
4788 if (u)
a7812ae4 4789 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4790 else
a7812ae4 4791 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c 4792 }
2c0262af 4793 } else {
ad69471c
PB		 4794 tmp = neon_load_reg(rm + pass, 0);
4795 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
36aa55dc
PB		 4796 tmp3 = neon_load_reg(rm + pass, 1);
4797 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4798 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
ad69471c 4799 dead_tmp(tmp);
36aa55dc 4800 dead_tmp(tmp3);
9ee6e8bb 4801 }
ad69471c
PB		 4802 tmp = new_tmp();
4803 if (op == 8 && !u) {
4804 gen_neon_narrow(size - 1, tmp, cpu_V0);
9ee6e8bb 4805 } else {
ad69471c
PB		 4806 if (op == 8)
4807 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
9ee6e8bb 4808 else
ad69471c
PB		 4809 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4810 }
2301db49 4811 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4812 } /* for pass */
b75263d6
JR		 4813 if (size == 3) {
4814 tcg_temp_free_i64(tmp64);
2301db49
JR		 4815 } else {
4816 dead_tmp(tmp2);
b75263d6 4817 }
9ee6e8bb
PB		 4818 } else if (op == 10) {
4819 /* VSHLL */
ad69471c 4820 if (q || size == 3)
9ee6e8bb 4821 return 1;
ad69471c
PB		 4822 tmp = neon_load_reg(rm, 0);
4823 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4824 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4825 if (pass == 1)
4826 tmp = tmp2;
4827
4828 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4829
9ee6e8bb
PB		 4830 if (shift != 0) {
4831 /* The shift is less than the width of the source
ad69471c
PB		 4832 type, so we can just shift the whole register. */
4833 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4834 if (size < 2 || !u) {
4835 uint64_t imm64;
4836 if (size == 0) {
4837 imm = (0xffu >> (8 - shift));
4838 imm |= imm << 16;
4839 } else {
4840 imm = 0xffff >> (16 - shift);
9ee6e8bb 4841 }
ad69471c
PB		 4842 imm64 = imm | (((uint64_t)imm) << 32);
4843 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
9ee6e8bb
PB		 4844 }
4845 }
ad69471c 4846 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 4847 }
4848 } else if (op == 15 || op == 16) {
4849 /* VCVT fixed-point. */
4850 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4851 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
9ee6e8bb
PB		 4852 if (op & 1) {
4853 if (u)
4373f3ce 4854 gen_vfp_ulto(0, shift);
9ee6e8bb 4855 else
4373f3ce 4856 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4857 } else {
4858 if (u)
4373f3ce 4859 gen_vfp_toul(0, shift);
9ee6e8bb 4860 else
4373f3ce 4861 gen_vfp_tosl(0, shift);
2c0262af 4862 }
4373f3ce 4863 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4864 }
4865 } else {
9ee6e8bb
PB		 4866 return 1;
4867 }
4868 } else { /* (insn & 0x00380080) == 0 */
4869 int invert;
4870
4871 op = (insn >> 8) & 0xf;
4872 /* One register and immediate. */
4873 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4874 invert = (insn & (1 << 5)) != 0;
4875 switch (op) {
4876 case 0: case 1:
4877 /* no-op */
4878 break;
4879 case 2: case 3:
4880 imm <<= 8;
4881 break;
4882 case 4: case 5:
4883 imm <<= 16;
4884 break;
4885 case 6: case 7:
4886 imm <<= 24;
4887 break;
4888 case 8: case 9:
4889 imm |= imm << 16;
4890 break;
4891 case 10: case 11:
4892 imm = (imm << 8) | (imm << 24);
4893 break;
4894 case 12:
8e31209e 4895 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 4896 break;
4897 case 13:
4898 imm = (imm << 16) | 0xffff;
4899 break;
4900 case 14:
4901 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4902 if (invert)
4903 imm = ~imm;
4904 break;
4905 case 15:
4906 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4907 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4908 break;
4909 }
4910 if (invert)
4911 imm = ~imm;
4912
9ee6e8bb
PB		 4913 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4914 if (op & 1 && op < 12) {
ad69471c 4915 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4916 if (invert) {
4917 /* The immediate value has already been inverted, so
4918 BIC becomes AND. */
ad69471c 4919 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 4920 } else {
ad69471c 4921 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 4922 }
9ee6e8bb 4923 } else {
ad69471c
PB		 4924 /* VMOV, VMVN. */
4925 tmp = new_tmp();
9ee6e8bb 4926 if (op == 14 && invert) {
ad69471c
PB		 4927 uint32_t val;
4928 val = 0;
9ee6e8bb
PB		 4929 for (n = 0; n < 4; n++) {
4930 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 4931 val |= 0xff << (n * 8);
9ee6e8bb 4932 }
ad69471c
PB		 4933 tcg_gen_movi_i32(tmp, val);
4934 } else {
4935 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 4936 }
9ee6e8bb 4937 }
ad69471c 4938 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4939 }
4940 }
e4b3861d 4941 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 4942 if (size != 3) {
4943 op = (insn >> 8) & 0xf;
4944 if ((insn & (1 << 6)) == 0) {
4945 /* Three registers of different lengths. */
4946 int src1_wide;
4947 int src2_wide;
4948 int prewiden;
4949 /* prewiden, src1_wide, src2_wide */
4950 static const int neon_3reg_wide[16][3] = {
4951 {1, 0, 0}, /* VADDL */
4952 {1, 1, 0}, /* VADDW */
4953 {1, 0, 0}, /* VSUBL */
4954 {1, 1, 0}, /* VSUBW */
4955 {0, 1, 1}, /* VADDHN */
4956 {0, 0, 0}, /* VABAL */
4957 {0, 1, 1}, /* VSUBHN */
4958 {0, 0, 0}, /* VABDL */
4959 {0, 0, 0}, /* VMLAL */
4960 {0, 0, 0}, /* VQDMLAL */
4961 {0, 0, 0}, /* VMLSL */
4962 {0, 0, 0}, /* VQDMLSL */
4963 {0, 0, 0}, /* Integer VMULL */
4964 {0, 0, 0}, /* VQDMULL */
4965 {0, 0, 0} /* Polynomial VMULL */
4966 };
4967
4968 prewiden = neon_3reg_wide[op][0];
4969 src1_wide = neon_3reg_wide[op][1];
4970 src2_wide = neon_3reg_wide[op][2];
4971
ad69471c
PB		 4972 if (size == 0 && (op == 9 || op == 11 || op == 13))
4973 return 1;
4974
9ee6e8bb
PB		 4975 /* Avoid overlapping operands. Wide source operands are
4976 always aligned so will never overlap with wide
4977 destinations in problematic ways. */
8f8e3aa4 4978 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 4979 tmp = neon_load_reg(rm, 1);
4980 neon_store_scratch(2, tmp);
8f8e3aa4 4981 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 4982 tmp = neon_load_reg(rn, 1);
4983 neon_store_scratch(2, tmp);
9ee6e8bb 4984 }
a50f5b91 4985 TCGV_UNUSED(tmp3);
9ee6e8bb 4986 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4987 if (src1_wide) {
4988 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 4989 TCGV_UNUSED(tmp);
9ee6e8bb 4990 } else {
ad69471c 4991 if (pass == 1 && rd == rn) {
dd8fbd78 4992 tmp = neon_load_scratch(2);
9ee6e8bb 4993 } else {
ad69471c
PB		 4994 tmp = neon_load_reg(rn, pass);
4995 }
4996 if (prewiden) {
4997 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 4998 }
4999 }
ad69471c
PB		 5000 if (src2_wide) {
5001 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5002 TCGV_UNUSED(tmp2);
9ee6e8bb 5003 } else {
ad69471c 5004 if (pass == 1 && rd == rm) {
dd8fbd78 5005 tmp2 = neon_load_scratch(2);
9ee6e8bb 5006 } else {
ad69471c
PB		 5007 tmp2 = neon_load_reg(rm, pass);
5008 }
5009 if (prewiden) {
5010 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5011 }
9ee6e8bb
PB		 5012 }
5013 switch (op) {
5014 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5015 gen_neon_addl(size);
9ee6e8bb 5016 break;
79b0e534 5017 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5018 gen_neon_subl(size);
9ee6e8bb
PB		 5019 break;
5020 case 5: case 7: /* VABAL, VABDL */
5021 switch ((size << 1) | u) {
ad69471c
PB		 5022 case 0:
5023 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5024 break;
5025 case 1:
5026 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5027 break;
5028 case 2:
5029 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5030 break;
5031 case 3:
5032 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5033 break;
5034 case 4:
5035 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5036 break;
5037 case 5:
5038 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5039 break;
9ee6e8bb
PB		 5040 default: abort();
5041 }
ad69471c
PB		 5042 dead_tmp(tmp2);
5043 dead_tmp(tmp);
9ee6e8bb
PB		 5044 break;
5045 case 8: case 9: case 10: case 11: case 12: case 13:
5046 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5047 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
dd8fbd78
FN		 5048 dead_tmp(tmp2);
5049 dead_tmp(tmp);
9ee6e8bb
PB		 5050 break;
5051 case 14: /* Polynomial VMULL */
5052 cpu_abort(env, "Polynomial VMULL not implemented");
5053
5054 default: /* 15 is RESERVED. */
5055 return 1;
5056 }
5057 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5058 /* Accumulate. */
5059 if (op == 10 || op == 11) {
ad69471c 5060 gen_neon_negl(cpu_V0, size);
9ee6e8bb
PB		 5061 }
5062
9ee6e8bb 5063 if (op != 13) {
ad69471c 5064 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb
PB		 5065 }
5066
5067 switch (op) {
5068 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
ad69471c 5069 gen_neon_addl(size);
9ee6e8bb
PB		 5070 break;
5071 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c
PB		 5072 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5073 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5074 break;
9ee6e8bb
PB		 5075 /* Fall through. */
5076 case 13: /* VQDMULL */
ad69471c 5077 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5078 break;
5079 default:
5080 abort();
5081 }
ad69471c 5082 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5083 } else if (op == 4 || op == 6) {
5084 /* Narrowing operation. */
ad69471c 5085 tmp = new_tmp();
79b0e534 5086 if (!u) {
9ee6e8bb 5087 switch (size) {
ad69471c
PB		 5088 case 0:
5089 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5090 break;
5091 case 1:
5092 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5093 break;
5094 case 2:
5095 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5096 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5097 break;
9ee6e8bb
PB		 5098 default: abort();
5099 }
5100 } else {
5101 switch (size) {
ad69471c
PB		 5102 case 0:
5103 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5104 break;
5105 case 1:
5106 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5107 break;
5108 case 2:
5109 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5110 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5111 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5112 break;
9ee6e8bb
PB		 5113 default: abort();
5114 }
5115 }
ad69471c
PB		 5116 if (pass == 0) {
5117 tmp3 = tmp;
5118 } else {
5119 neon_store_reg(rd, 0, tmp3);
5120 neon_store_reg(rd, 1, tmp);
5121 }
9ee6e8bb
PB		 5122 } else {
5123 /* Write back the result. */
ad69471c 5124 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5125 }
5126 }
5127 } else {
5128 /* Two registers and a scalar. */
5129 switch (op) {
5130 case 0: /* Integer VMLA scalar */
5131 case 1: /* Float VMLA scalar */
5132 case 4: /* Integer VMLS scalar */
5133 case 5: /* Floating point VMLS scalar */
5134 case 8: /* Integer VMUL scalar */
5135 case 9: /* Floating point VMUL scalar */
5136 case 12: /* VQDMULH scalar */
5137 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5138 tmp = neon_get_scalar(size, rm);
5139 neon_store_scratch(0, tmp);
9ee6e8bb 5140 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5141 tmp = neon_load_scratch(0);
5142 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5143 if (op == 12) {
5144 if (size == 1) {
dd8fbd78 5145 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5146 } else {
dd8fbd78 5147 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5148 }
5149 } else if (op == 13) {
5150 if (size == 1) {
dd8fbd78 5151 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5152 } else {
dd8fbd78 5153 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5154 }
5155 } else if (op & 1) {
dd8fbd78 5156 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5157 } else {
5158 switch (size) {
dd8fbd78
FN		 5159 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5160 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5161 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5162 default: return 1;
5163 }
5164 }
dd8fbd78 5165 dead_tmp(tmp2);
9ee6e8bb
PB		 5166 if (op < 8) {
5167 /* Accumulate. */
dd8fbd78 5168 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5169 switch (op) {
5170 case 0:
dd8fbd78 5171 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5172 break;
5173 case 1:
dd8fbd78 5174 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5175 break;
5176 case 4:
dd8fbd78 5177 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5178 break;
5179 case 5:
dd8fbd78 5180 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5181 break;
5182 default:
5183 abort();
5184 }
dd8fbd78 5185 dead_tmp(tmp2);
9ee6e8bb 5186 }
dd8fbd78 5187 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5188 }
5189 break;
5190 case 2: /* VMLAL sclar */
5191 case 3: /* VQDMLAL scalar */
5192 case 6: /* VMLSL scalar */
5193 case 7: /* VQDMLSL scalar */
5194 case 10: /* VMULL scalar */
5195 case 11: /* VQDMULL scalar */
ad69471c
PB		 5196 if (size == 0 && (op == 3 || op == 7 || op == 11))
5197 return 1;
5198
dd8fbd78
FN		 5199 tmp2 = neon_get_scalar(size, rm);
5200 tmp3 = neon_load_reg(rn, 1);
ad69471c 5201
9ee6e8bb 5202 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5203 if (pass == 0) {
5204 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5205 } else {
dd8fbd78 5206 tmp = tmp3;
9ee6e8bb 5207 }
ad69471c 5208 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
dd8fbd78 5209 dead_tmp(tmp);
9ee6e8bb 5210 if (op == 6 || op == 7) {
ad69471c
PB		 5211 gen_neon_negl(cpu_V0, size);
5212 }
5213 if (op != 11) {
5214 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5215 }
9ee6e8bb
PB		 5216 switch (op) {
5217 case 2: case 6:
ad69471c 5218 gen_neon_addl(size);
9ee6e8bb
PB		 5219 break;
5220 case 3: case 7:
ad69471c
PB		 5221 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5222 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5223 break;
5224 case 10:
5225 /* no-op */
5226 break;
5227 case 11:
ad69471c 5228 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5229 break;
5230 default:
5231 abort();
5232 }
ad69471c 5233 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5234 }
dd8fbd78
FN		 5235
5236 dead_tmp(tmp2);
5237
9ee6e8bb
PB		 5238 break;
5239 default: /* 14 and 15 are RESERVED */
5240 return 1;
5241 }
5242 }
5243 } else { /* size == 3 */
5244 if (!u) {
5245 /* Extract. */
9ee6e8bb 5246 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5247
5248 if (imm > 7 && !q)
5249 return 1;
5250
5251 if (imm == 0) {
5252 neon_load_reg64(cpu_V0, rn);
5253 if (q) {
5254 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5255 }
ad69471c
PB		 5256 } else if (imm == 8) {
5257 neon_load_reg64(cpu_V0, rn + 1);
5258 if (q) {
5259 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5260 }
ad69471c 5261 } else if (q) {
a7812ae4 5262 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5263 if (imm < 8) {
5264 neon_load_reg64(cpu_V0, rn);
a7812ae4 5265 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5266 } else {
5267 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5268 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5269 }
5270 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5271 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5272 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5273 if (imm < 8) {
5274 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5275 } else {
ad69471c
PB		 5276 neon_load_reg64(cpu_V1, rm + 1);
5277 imm -= 8;
9ee6e8bb 5278 }
ad69471c 5279 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5280 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5281 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5282 tcg_temp_free_i64(tmp64);
ad69471c 5283 } else {
a7812ae4 5284 /* BUGFIX */
ad69471c 5285 neon_load_reg64(cpu_V0, rn);
a7812ae4 5286 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5287 neon_load_reg64(cpu_V1, rm);
a7812ae4 5288 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5289 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5290 }
5291 neon_store_reg64(cpu_V0, rd);
5292 if (q) {
5293 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5294 }
5295 } else if ((insn & (1 << 11)) == 0) {
5296 /* Two register misc. */
5297 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5298 size = (insn >> 18) & 3;
5299 switch (op) {
5300 case 0: /* VREV64 */
5301 if (size == 3)
5302 return 1;
5303 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5304 tmp = neon_load_reg(rm, pass * 2);
5305 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5306 switch (size) {
dd8fbd78
FN		 5307 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5308 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5309 case 2: /* no-op */ break;
5310 default: abort();
5311 }
dd8fbd78 5312 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5313 if (size == 2) {
dd8fbd78 5314 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5315 } else {
9ee6e8bb 5316 switch (size) {
dd8fbd78
FN		 5317 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5318 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5319 default: abort();
5320 }
dd8fbd78 5321 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5322 }
5323 }
5324 break;
5325 case 4: case 5: /* VPADDL */
5326 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5327 if (size == 3)
5328 return 1;
ad69471c
PB		 5329 for (pass = 0; pass < q + 1; pass++) {
5330 tmp = neon_load_reg(rm, pass * 2);
5331 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5332 tmp = neon_load_reg(rm, pass * 2 + 1);
5333 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5334 switch (size) {
5335 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5336 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5337 case 2: tcg_gen_add_i64(CPU_V001); break;
5338 default: abort();
5339 }
9ee6e8bb
PB		 5340 if (op >= 12) {
5341 /* Accumulate. */
ad69471c
PB		 5342 neon_load_reg64(cpu_V1, rd + pass);
5343 gen_neon_addl(size);
9ee6e8bb 5344 }
ad69471c 5345 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5346 }
5347 break;
5348 case 33: /* VTRN */
5349 if (size == 2) {
5350 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5351 tmp = neon_load_reg(rm, n);
5352 tmp2 = neon_load_reg(rd, n + 1);
5353 neon_store_reg(rm, n, tmp2);
5354 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5355 }
5356 } else {
5357 goto elementwise;
5358 }
5359 break;
5360 case 34: /* VUZP */
5361 /* Reg Before After
5362 Rd A3 A2 A1 A0 B2 B0 A2 A0
5363 Rm B3 B2 B1 B0 B3 B1 A3 A1
5364 */
5365 if (size == 3)
5366 return 1;
5367 gen_neon_unzip(rd, q, 0, size);
5368 gen_neon_unzip(rm, q, 4, size);
5369 if (q) {
5370 static int unzip_order_q[8] =
5371 {0, 2, 4, 6, 1, 3, 5, 7};
5372 for (n = 0; n < 8; n++) {
5373 int reg = (n < 4) ? rd : rm;
dd8fbd78
FN		 5374 tmp = neon_load_scratch(unzip_order_q[n]);
5375 neon_store_reg(reg, n % 4, tmp);
9ee6e8bb
PB		 5376 }
5377 } else {
5378 static int unzip_order[4] =
5379 {0, 4, 1, 5};
5380 for (n = 0; n < 4; n++) {
5381 int reg = (n < 2) ? rd : rm;
dd8fbd78
FN		 5382 tmp = neon_load_scratch(unzip_order[n]);
5383 neon_store_reg(reg, n % 2, tmp);
9ee6e8bb
PB		 5384 }
5385 }
5386 break;
5387 case 35: /* VZIP */
5388 /* Reg Before After
5389 Rd A3 A2 A1 A0 B1 A1 B0 A0
5390 Rm B3 B2 B1 B0 B3 A3 B2 A2
5391 */
5392 if (size == 3)
5393 return 1;
5394 count = (q ? 4 : 2);
5395 for (n = 0; n < count; n++) {
dd8fbd78
FN		 5396 tmp = neon_load_reg(rd, n);
5397 tmp2 = neon_load_reg(rd, n);
9ee6e8bb 5398 switch (size) {
dd8fbd78
FN		 5399 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5400 case 1: gen_neon_zip_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5401 case 2: /* no-op */; break;
5402 default: abort();
5403 }
dd8fbd78
FN		 5404 neon_store_scratch(n * 2, tmp);
5405 neon_store_scratch(n * 2 + 1, tmp2);
9ee6e8bb
PB		 5406 }
5407 for (n = 0; n < count * 2; n++) {
5408 int reg = (n < count) ? rd : rm;
dd8fbd78
FN		 5409 tmp = neon_load_scratch(n);
5410 neon_store_reg(reg, n % count, tmp);
9ee6e8bb
PB		 5411 }
5412 break;
5413 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5414 if (size == 3)
5415 return 1;
a50f5b91 5416 TCGV_UNUSED(tmp2);
9ee6e8bb 5417 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5418 neon_load_reg64(cpu_V0, rm + pass);
5419 tmp = new_tmp();
9ee6e8bb 5420 if (op == 36 && q == 0) {
ad69471c 5421 gen_neon_narrow(size, tmp, cpu_V0);
9ee6e8bb 5422 } else if (q) {
ad69471c 5423 gen_neon_narrow_satu(size, tmp, cpu_V0);
9ee6e8bb 5424 } else {
ad69471c
PB		 5425 gen_neon_narrow_sats(size, tmp, cpu_V0);
5426 }
5427 if (pass == 0) {
5428 tmp2 = tmp;
5429 } else {
5430 neon_store_reg(rd, 0, tmp2);
5431 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5432 }
9ee6e8bb
PB		 5433 }
5434 break;
5435 case 38: /* VSHLL */
ad69471c 5436 if (q || size == 3)
9ee6e8bb 5437 return 1;
ad69471c
PB		 5438 tmp = neon_load_reg(rm, 0);
5439 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5440 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5441 if (pass == 1)
5442 tmp = tmp2;
5443 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5444 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5445 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5446 }
5447 break;
60011498
PB		 5448 case 44: /* VCVT.F16.F32 */
5449 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5450 return 1;
5451 tmp = new_tmp();
5452 tmp2 = new_tmp();
5453 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5454 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5455 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5456 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5457 tcg_gen_shli_i32(tmp2, tmp2, 16);
5458 tcg_gen_or_i32(tmp2, tmp2, tmp);
5459 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5460 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5461 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5462 neon_store_reg(rd, 0, tmp2);
5463 tmp2 = new_tmp();
5464 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5465 tcg_gen_shli_i32(tmp2, tmp2, 16);
5466 tcg_gen_or_i32(tmp2, tmp2, tmp);
5467 neon_store_reg(rd, 1, tmp2);
5468 dead_tmp(tmp);
5469 break;
5470 case 46: /* VCVT.F32.F16 */
5471 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5472 return 1;
5473 tmp3 = new_tmp();
5474 tmp = neon_load_reg(rm, 0);
5475 tmp2 = neon_load_reg(rm, 1);
5476 tcg_gen_ext16u_i32(tmp3, tmp);
5477 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5478 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5479 tcg_gen_shri_i32(tmp3, tmp, 16);
5480 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5481 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5482 dead_tmp(tmp);
5483 tcg_gen_ext16u_i32(tmp3, tmp2);
5484 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5485 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5486 tcg_gen_shri_i32(tmp3, tmp2, 16);
5487 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5488 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5489 dead_tmp(tmp2);
5490 dead_tmp(tmp3);
5491 break;
9ee6e8bb
PB		 5492 default:
5493 elementwise:
5494 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5495 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5496 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5497 neon_reg_offset(rm, pass));
dd8fbd78 5498 TCGV_UNUSED(tmp);
9ee6e8bb 5499 } else {
dd8fbd78 5500 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5501 }
5502 switch (op) {
5503 case 1: /* VREV32 */
5504 switch (size) {
dd8fbd78
FN		 5505 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5506 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5507 default: return 1;
5508 }
5509 break;
5510 case 2: /* VREV16 */
5511 if (size != 0)
5512 return 1;
dd8fbd78 5513 gen_rev16(tmp);
9ee6e8bb 5514 break;
9ee6e8bb
PB		 5515 case 8: /* CLS */
5516 switch (size) {
dd8fbd78
FN		 5517 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5518 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5519 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5520 default: return 1;
5521 }
5522 break;
5523 case 9: /* CLZ */
5524 switch (size) {
dd8fbd78
FN		 5525 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5526 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5527 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5528 default: return 1;
5529 }
5530 break;
5531 case 10: /* CNT */
5532 if (size != 0)
5533 return 1;
dd8fbd78 5534 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5535 break;
5536 case 11: /* VNOT */
5537 if (size != 0)
5538 return 1;
dd8fbd78 5539 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5540 break;
5541 case 14: /* VQABS */
5542 switch (size) {
dd8fbd78
FN		 5543 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5544 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5545 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5546 default: return 1;
5547 }
5548 break;
5549 case 15: /* VQNEG */
5550 switch (size) {
dd8fbd78
FN		 5551 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5552 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5553 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5554 default: return 1;
5555 }
5556 break;
5557 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5558 tmp2 = tcg_const_i32(0);
9ee6e8bb 5559 switch(size) {
dd8fbd78
FN		 5560 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5561 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5562 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5563 default: return 1;
5564 }
dd8fbd78 5565 tcg_temp_free(tmp2);
9ee6e8bb 5566 if (op == 19)
dd8fbd78 5567 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5568 break;
5569 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5570 tmp2 = tcg_const_i32(0);
9ee6e8bb 5571 switch(size) {
dd8fbd78
FN		 5572 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5573 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5574 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5575 default: return 1;
5576 }
dd8fbd78 5577 tcg_temp_free(tmp2);
9ee6e8bb 5578 if (op == 20)
dd8fbd78 5579 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5580 break;
5581 case 18: /* VCEQ #0 */
dd8fbd78 5582 tmp2 = tcg_const_i32(0);
9ee6e8bb 5583 switch(size) {
dd8fbd78
FN		 5584 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5585 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5586 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5587 default: return 1;
5588 }
dd8fbd78 5589 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5590 break;
5591 case 22: /* VABS */
5592 switch(size) {
dd8fbd78
FN		 5593 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5594 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5595 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5596 default: return 1;
5597 }
5598 break;
5599 case 23: /* VNEG */
ad69471c
PB		 5600 if (size == 3)
5601 return 1;
dd8fbd78
FN		 5602 tmp2 = tcg_const_i32(0);
5603 gen_neon_rsb(size, tmp, tmp2);
5604 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5605 break;
5606 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
dd8fbd78
FN		 5607 tmp2 = tcg_const_i32(0);
5608 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5609 tcg_temp_free(tmp2);
9ee6e8bb 5610 if (op == 27)
dd8fbd78 5611 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5612 break;
5613 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
dd8fbd78
FN		 5614 tmp2 = tcg_const_i32(0);
5615 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5616 tcg_temp_free(tmp2);
9ee6e8bb 5617 if (op == 28)
dd8fbd78 5618 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5619 break;
5620 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5621 tmp2 = tcg_const_i32(0);
5622 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5623 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5624 break;
5625 case 30: /* Float VABS */
4373f3ce 5626 gen_vfp_abs(0);
9ee6e8bb
PB		 5627 break;
5628 case 31: /* Float VNEG */
4373f3ce 5629 gen_vfp_neg(0);
9ee6e8bb
PB		 5630 break;
5631 case 32: /* VSWP */
dd8fbd78
FN		 5632 tmp2 = neon_load_reg(rd, pass);
5633 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5634 break;
5635 case 33: /* VTRN */
dd8fbd78 5636 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5637 switch (size) {
dd8fbd78
FN		 5638 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5639 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5640 case 2: abort();
5641 default: return 1;
5642 }
dd8fbd78 5643 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5644 break;
5645 case 56: /* Integer VRECPE */
dd8fbd78 5646 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5647 break;
5648 case 57: /* Integer VRSQRTE */
dd8fbd78 5649 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5650 break;
5651 case 58: /* Float VRECPE */
4373f3ce 5652 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5653 break;
5654 case 59: /* Float VRSQRTE */
4373f3ce 5655 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5656 break;
5657 case 60: /* VCVT.F32.S32 */
4373f3ce 5658 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5659 break;
5660 case 61: /* VCVT.F32.U32 */
4373f3ce 5661 gen_vfp_touiz(0);
9ee6e8bb
PB		 5662 break;
5663 case 62: /* VCVT.S32.F32 */
4373f3ce 5664 gen_vfp_sito(0);
9ee6e8bb
PB		 5665 break;
5666 case 63: /* VCVT.U32.F32 */
4373f3ce 5667 gen_vfp_uito(0);
9ee6e8bb
PB		 5668 break;
5669 default:
5670 /* Reserved: 21, 29, 39-56 */
5671 return 1;
5672 }
5673 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5674 tcg_gen_st_f32(cpu_F0s, cpu_env,
5675 neon_reg_offset(rd, pass));
9ee6e8bb 5676 } else {
dd8fbd78 5677 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5678 }
5679 }
5680 break;
5681 }
5682 } else if ((insn & (1 << 10)) == 0) {
5683 /* VTBL, VTBX. */
3018f259 5684 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5685 if (insn & (1 << 6)) {
8f8e3aa4 5686 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5687 } else {
8f8e3aa4
PB		 5688 tmp = new_tmp();
5689 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5690 }
8f8e3aa4 5691 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5692 tmp4 = tcg_const_i32(rn);
5693 tmp5 = tcg_const_i32(n);
5694 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
3018f259 5695 dead_tmp(tmp);
9ee6e8bb 5696 if (insn & (1 << 6)) {
8f8e3aa4 5697 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5698 } else {
8f8e3aa4
PB		 5699 tmp = new_tmp();
5700 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5701 }
8f8e3aa4 5702 tmp3 = neon_load_reg(rm, 1);
b75263d6 5703 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5704 tcg_temp_free_i32(tmp5);
5705 tcg_temp_free_i32(tmp4);
8f8e3aa4 5706 neon_store_reg(rd, 0, tmp2);
3018f259
PB		 5707 neon_store_reg(rd, 1, tmp3);
5708 dead_tmp(tmp);
9ee6e8bb
PB		 5709 } else if ((insn & 0x380) == 0) {
5710 /* VDUP */
5711 if (insn & (1 << 19)) {
dd8fbd78 5712 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5713 } else {
dd8fbd78 5714 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5715 }
5716 if (insn & (1 << 16)) {
dd8fbd78 5717 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5718 } else if (insn & (1 << 17)) {
5719 if ((insn >> 18) & 1)
dd8fbd78 5720 gen_neon_dup_high16(tmp);
9ee6e8bb 5721 else
dd8fbd78 5722 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5723 }
5724 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 5725 tmp2 = new_tmp();
5726 tcg_gen_mov_i32(tmp2, tmp);
5727 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5728 }
dd8fbd78 5729 dead_tmp(tmp);
9ee6e8bb
PB		 5730 } else {
5731 return 1;
5732 }
5733 }
5734 }
5735 return 0;
5736}
5737
fe1479c3
PB		 5738static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5739{
5740 int crn = (insn >> 16) & 0xf;
5741 int crm = insn & 0xf;
5742 int op1 = (insn >> 21) & 7;
5743 int op2 = (insn >> 5) & 7;
5744 int rt = (insn >> 12) & 0xf;
5745 TCGv tmp;
5746
5747 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5748 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5749 /* TEECR */
5750 if (IS_USER(s))
5751 return 1;
5752 tmp = load_cpu_field(teecr);
5753 store_reg(s, rt, tmp);
5754 return 0;
5755 }
5756 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5757 /* TEEHBR */
5758 if (IS_USER(s) && (env->teecr & 1))
5759 return 1;
5760 tmp = load_cpu_field(teehbr);
5761 store_reg(s, rt, tmp);
5762 return 0;
5763 }
5764 }
5765 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5766 op1, crn, crm, op2);
5767 return 1;
5768}
5769
5770static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5771{
5772 int crn = (insn >> 16) & 0xf;
5773 int crm = insn & 0xf;
5774 int op1 = (insn >> 21) & 7;
5775 int op2 = (insn >> 5) & 7;
5776 int rt = (insn >> 12) & 0xf;
5777 TCGv tmp;
5778
5779 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5780 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5781 /* TEECR */
5782 if (IS_USER(s))
5783 return 1;
5784 tmp = load_reg(s, rt);
5785 gen_helper_set_teecr(cpu_env, tmp);
5786 dead_tmp(tmp);
5787 return 0;
5788 }
5789 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5790 /* TEEHBR */
5791 if (IS_USER(s) && (env->teecr & 1))
5792 return 1;
5793 tmp = load_reg(s, rt);
5794 store_cpu_field(tmp, teehbr);
5795 return 0;
5796 }
5797 }
5798 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5799 op1, crn, crm, op2);
5800 return 1;
5801}
5802
9ee6e8bb
PB		 5803static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5804{
5805 int cpnum;
5806
5807 cpnum = (insn >> 8) & 0xf;
5808 if (arm_feature(env, ARM_FEATURE_XSCALE)
5809 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5810 return 1;
5811
5812 switch (cpnum) {
5813 case 0:
5814 case 1:
5815 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5816 return disas_iwmmxt_insn(env, s, insn);
5817 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5818 return disas_dsp_insn(env, s, insn);
5819 }
5820 return 1;
5821 case 10:
5822 case 11:
5823 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 5824 case 14:
5825 /* Coprocessors 7-15 are architecturally reserved by ARM.
5826 Unfortunately Intel decided to ignore this. */
5827 if (arm_feature(env, ARM_FEATURE_XSCALE))
5828 goto board;
5829 if (insn & (1 << 20))
5830 return disas_cp14_read(env, s, insn);
5831 else
5832 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 5833 case 15:
5834 return disas_cp15_insn (env, s, insn);
5835 default:
fe1479c3 5836 board:
9ee6e8bb
PB		 5837 /* Unknown coprocessor. See if the board has hooked it. */
5838 return disas_cp_insn (env, s, insn);
5839 }
5840}
5841
5e3f878a
PB		 5842
5843/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 5844static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 5845{
5846 TCGv tmp;
5847 tmp = new_tmp();
5848 tcg_gen_trunc_i64_i32(tmp, val);
5849 store_reg(s, rlow, tmp);
5850 tmp = new_tmp();
5851 tcg_gen_shri_i64(val, val, 32);
5852 tcg_gen_trunc_i64_i32(tmp, val);
5853 store_reg(s, rhigh, tmp);
5854}
5855
5856/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 5857static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 5858{
a7812ae4 5859 TCGv_i64 tmp;
5e3f878a
PB		 5860 TCGv tmp2;
5861
36aa55dc 5862 /* Load value and extend to 64 bits. */
a7812ae4 5863 tmp = tcg_temp_new_i64();
5e3f878a
PB		 5864 tmp2 = load_reg(s, rlow);
5865 tcg_gen_extu_i32_i64(tmp, tmp2);
5866 dead_tmp(tmp2);
5867 tcg_gen_add_i64(val, val, tmp);
b75263d6 5868 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5869}
5870
5871/* load and add a 64-bit value from a register pair. */
a7812ae4 5872static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 5873{
a7812ae4 5874 TCGv_i64 tmp;
36aa55dc
PB		 5875 TCGv tmpl;
5876 TCGv tmph;
5e3f878a
PB		 5877
5878 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 5879 tmpl = load_reg(s, rlow);
5880 tmph = load_reg(s, rhigh);
a7812ae4 5881 tmp = tcg_temp_new_i64();
36aa55dc
PB		 5882 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5883 dead_tmp(tmpl);
5884 dead_tmp(tmph);
5e3f878a 5885 tcg_gen_add_i64(val, val, tmp);
b75263d6 5886 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5887}
5888
5889/* Set N and Z flags from a 64-bit value. */
a7812ae4 5890static void gen_logicq_cc(TCGv_i64 val)
5e3f878a
PB		 5891{
5892 TCGv tmp = new_tmp();
5893 gen_helper_logicq_cc(tmp, val);
6fbe23d5
PB		 5894 gen_logic_CC(tmp);
5895 dead_tmp(tmp);
5e3f878a
PB		 5896}
5897
426f5abc
PB		 5898/* Load/Store exclusive instructions are implemented by remembering
5899 the value/address loaded, and seeing if these are the same
5900 when the store is performed. This should be is sufficient to implement
5901 the architecturally mandated semantics, and avoids having to monitor
5902 regular stores.
5903
5904 In system emulation mode only one CPU will be running at once, so
5905 this sequence is effectively atomic. In user emulation mode we
5906 throw an exception and handle the atomic operation elsewhere. */
5907static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5908 TCGv addr, int size)
5909{
5910 TCGv tmp;
5911
5912 switch (size) {
5913 case 0:
5914 tmp = gen_ld8u(addr, IS_USER(s));
5915 break;
5916 case 1:
5917 tmp = gen_ld16u(addr, IS_USER(s));
5918 break;
5919 case 2:
5920 case 3:
5921 tmp = gen_ld32(addr, IS_USER(s));
5922 break;
5923 default:
5924 abort();
5925 }
5926 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5927 store_reg(s, rt, tmp);
5928 if (size == 3) {
5929 tcg_gen_addi_i32(addr, addr, 4);
5930 tmp = gen_ld32(addr, IS_USER(s));
5931 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5932 store_reg(s, rt2, tmp);
5933 }
5934 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5935}
5936
5937static void gen_clrex(DisasContext *s)
5938{
5939 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5940}
5941
5942#ifdef CONFIG_USER_ONLY
5943static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5944 TCGv addr, int size)
5945{
5946 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5947 tcg_gen_movi_i32(cpu_exclusive_info,
5948 size | (rd << 4) | (rt << 8) | (rt2 << 12));
5949 gen_set_condexec(s);
5950 gen_set_pc_im(s->pc - 4);
5951 gen_exception(EXCP_STREX);
5952 s->is_jmp = DISAS_JUMP;
5953}
5954#else
5955static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5956 TCGv addr, int size)
5957{
5958 TCGv tmp;
5959 int done_label;
5960 int fail_label;
5961
5962 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
5963 [addr] = {Rt};
5964 {Rd} = 0;
5965 } else {
5966 {Rd} = 1;
5967 } */
5968 fail_label = gen_new_label();
5969 done_label = gen_new_label();
5970 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
5971 switch (size) {
5972 case 0:
5973 tmp = gen_ld8u(addr, IS_USER(s));
5974 break;
5975 case 1:
5976 tmp = gen_ld16u(addr, IS_USER(s));
5977 break;
5978 case 2:
5979 case 3:
5980 tmp = gen_ld32(addr, IS_USER(s));
5981 break;
5982 default:
5983 abort();
5984 }
5985 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
5986 dead_tmp(tmp);
5987 if (size == 3) {
5988 TCGv tmp2 = new_tmp();
5989 tcg_gen_addi_i32(tmp2, addr, 4);
5990 tmp = gen_ld32(addr, IS_USER(s));
5991 dead_tmp(tmp2);
5992 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
5993 dead_tmp(tmp);
5994 }
5995 tmp = load_reg(s, rt);
5996 switch (size) {
5997 case 0:
5998 gen_st8(tmp, addr, IS_USER(s));
5999 break;
6000 case 1:
6001 gen_st16(tmp, addr, IS_USER(s));
6002 break;
6003 case 2:
6004 case 3:
6005 gen_st32(tmp, addr, IS_USER(s));
6006 break;
6007 default:
6008 abort();
6009 }
6010 if (size == 3) {
6011 tcg_gen_addi_i32(addr, addr, 4);
6012 tmp = load_reg(s, rt2);
6013 gen_st32(tmp, addr, IS_USER(s));
6014 }
6015 tcg_gen_movi_i32(cpu_R[rd], 0);
6016 tcg_gen_br(done_label);
6017 gen_set_label(fail_label);
6018 tcg_gen_movi_i32(cpu_R[rd], 1);
6019 gen_set_label(done_label);
6020 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6021}
6022#endif
6023
9ee6e8bb
PB		 6024static void disas_arm_insn(CPUState * env, DisasContext *s)
6025{
6026 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6027 TCGv tmp;
3670669c 6028 TCGv tmp2;
6ddbc6e4 6029 TCGv tmp3;
b0109805 6030 TCGv addr;
a7812ae4 6031 TCGv_i64 tmp64;
9ee6e8bb
PB		 6032
6033 insn = ldl_code(s->pc);
6034 s->pc += 4;
6035
6036 /* M variants do not implement ARM mode. */
6037 if (IS_M(env))
6038 goto illegal_op;
6039 cond = insn >> 28;
6040 if (cond == 0xf){
6041 /* Unconditional instructions. */
6042 if (((insn >> 25) & 7) == 1) {
6043 /* NEON Data processing. */
6044 if (!arm_feature(env, ARM_FEATURE_NEON))
6045 goto illegal_op;
6046
6047 if (disas_neon_data_insn(env, s, insn))
6048 goto illegal_op;
6049 return;
6050 }
6051 if ((insn & 0x0f100000) == 0x04000000) {
6052 /* NEON load/store. */
6053 if (!arm_feature(env, ARM_FEATURE_NEON))
6054 goto illegal_op;
6055
6056 if (disas_neon_ls_insn(env, s, insn))
6057 goto illegal_op;
6058 return;
6059 }
6060 if ((insn & 0x0d70f000) == 0x0550f000)
6061 return; /* PLD */
6062 else if ((insn & 0x0ffffdff) == 0x01010000) {
6063 ARCH(6);
6064 /* setend */
6065 if (insn & (1 << 9)) {
6066 /* BE8 mode not implemented. */
6067 goto illegal_op;
6068 }
6069 return;
6070 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6071 switch ((insn >> 4) & 0xf) {
6072 case 1: /* clrex */
6073 ARCH(6K);
426f5abc 6074 gen_clrex(s);
9ee6e8bb
PB		 6075 return;
6076 case 4: /* dsb */
6077 case 5: /* dmb */
6078 case 6: /* isb */
6079 ARCH(7);
6080 /* We don't emulate caches so these are a no-op. */
6081 return;
6082 default:
6083 goto illegal_op;
6084 }
6085 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6086 /* srs */
c67b6b71 6087 int32_t offset;
9ee6e8bb
PB		 6088 if (IS_USER(s))
6089 goto illegal_op;
6090 ARCH(6);
6091 op1 = (insn & 0x1f);
6092 if (op1 == (env->uncached_cpsr & CPSR_M)) {
b0109805 6093 addr = load_reg(s, 13);
9ee6e8bb 6094 } else {
b0109805 6095 addr = new_tmp();
b75263d6
JR		 6096 tmp = tcg_const_i32(op1);
6097 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6098 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6099 }
6100 i = (insn >> 23) & 3;
6101 switch (i) {
6102 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6103 case 1: offset = 0; break; /* IA */
6104 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6105 case 3: offset = 4; break; /* IB */
6106 default: abort();
6107 }
6108 if (offset)
b0109805
PB		 6109 tcg_gen_addi_i32(addr, addr, offset);
6110 tmp = load_reg(s, 14);
6111 gen_st32(tmp, addr, 0);
c67b6b71 6112 tmp = load_cpu_field(spsr);
b0109805
PB		 6113 tcg_gen_addi_i32(addr, addr, 4);
6114 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6115 if (insn & (1 << 21)) {
6116 /* Base writeback. */
6117 switch (i) {
6118 case 0: offset = -8; break;
c67b6b71
FN		 6119 case 1: offset = 4; break;
6120 case 2: offset = -4; break;
9ee6e8bb
PB		 6121 case 3: offset = 0; break;
6122 default: abort();
6123 }
6124 if (offset)
c67b6b71 6125 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb 6126 if (op1 == (env->uncached_cpsr & CPSR_M)) {
c67b6b71 6127 store_reg(s, 13, addr);
9ee6e8bb 6128 } else {
b75263d6
JR		 6129 tmp = tcg_const_i32(op1);
6130 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6131 tcg_temp_free_i32(tmp);
c67b6b71 6132 dead_tmp(addr);
9ee6e8bb 6133 }
b0109805
PB		 6134 } else {
6135 dead_tmp(addr);
9ee6e8bb 6136 }
a990f58f 6137 return;
ea825eee 6138 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6139 /* rfe */
c67b6b71 6140 int32_t offset;
9ee6e8bb
PB		 6141 if (IS_USER(s))
6142 goto illegal_op;
6143 ARCH(6);
6144 rn = (insn >> 16) & 0xf;
b0109805 6145 addr = load_reg(s, rn);
9ee6e8bb
PB		 6146 i = (insn >> 23) & 3;
6147 switch (i) {
b0109805 6148 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6149 case 1: offset = 0; break; /* IA */
6150 case 2: offset = -8; break; /* DB */
b0109805 6151 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6152 default: abort();
6153 }
6154 if (offset)
b0109805
PB		 6155 tcg_gen_addi_i32(addr, addr, offset);
6156 /* Load PC into tmp and CPSR into tmp2. */
6157 tmp = gen_ld32(addr, 0);
6158 tcg_gen_addi_i32(addr, addr, 4);
6159 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6160 if (insn & (1 << 21)) {
6161 /* Base writeback. */
6162 switch (i) {
b0109805 6163 case 0: offset = -8; break;
c67b6b71
FN		 6164 case 1: offset = 4; break;
6165 case 2: offset = -4; break;
b0109805 6166 case 3: offset = 0; break;
9ee6e8bb
PB		 6167 default: abort();
6168 }
6169 if (offset)
b0109805
PB		 6170 tcg_gen_addi_i32(addr, addr, offset);
6171 store_reg(s, rn, addr);
6172 } else {
6173 dead_tmp(addr);
9ee6e8bb 6174 }
b0109805 6175 gen_rfe(s, tmp, tmp2);
c67b6b71 6176 return;
9ee6e8bb
PB		 6177 } else if ((insn & 0x0e000000) == 0x0a000000) {
6178 /* branch link and change to thumb (blx <offset>) */
6179 int32_t offset;
6180
6181 val = (uint32_t)s->pc;
d9ba4830
PB		 6182 tmp = new_tmp();
6183 tcg_gen_movi_i32(tmp, val);
6184 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6185 /* Sign-extend the 24-bit offset */
6186 offset = (((int32_t)insn) << 8) >> 8;
6187 /* offset * 4 + bit24 * 2 + (thumb bit) */
6188 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6189 /* pipeline offset */
6190 val += 4;
d9ba4830 6191 gen_bx_im(s, val);
9ee6e8bb
PB		 6192 return;
6193 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6194 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6195 /* iWMMXt register transfer. */
6196 if (env->cp15.c15_cpar & (1 << 1))
6197 if (!disas_iwmmxt_insn(env, s, insn))
6198 return;
6199 }
6200 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6201 /* Coprocessor double register transfer. */
6202 } else if ((insn & 0x0f000010) == 0x0e000010) {
6203 /* Additional coprocessor register transfer. */
7997d92f 6204 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6205 uint32_t mask;
6206 uint32_t val;
6207 /* cps (privileged) */
6208 if (IS_USER(s))
6209 return;
6210 mask = val = 0;
6211 if (insn & (1 << 19)) {
6212 if (insn & (1 << 8))
6213 mask |= CPSR_A;
6214 if (insn & (1 << 7))
6215 mask |= CPSR_I;
6216 if (insn & (1 << 6))
6217 mask |= CPSR_F;
6218 if (insn & (1 << 18))
6219 val |= mask;
6220 }
7997d92f 6221 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6222 mask |= CPSR_M;
6223 val |= (insn & 0x1f);
6224 }
6225 if (mask) {
2fbac54b 6226 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6227 }
6228 return;
6229 }
6230 goto illegal_op;
6231 }
6232 if (cond != 0xe) {
6233 /* if not always execute, we generate a conditional jump to
6234 next instruction */
6235 s->condlabel = gen_new_label();
d9ba4830 6236 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6237 s->condjmp = 1;
6238 }
6239 if ((insn & 0x0f900000) == 0x03000000) {
6240 if ((insn & (1 << 21)) == 0) {
6241 ARCH(6T2);
6242 rd = (insn >> 12) & 0xf;
6243 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6244 if ((insn & (1 << 22)) == 0) {
6245 /* MOVW */
5e3f878a
PB		 6246 tmp = new_tmp();
6247 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6248 } else {
6249 /* MOVT */
5e3f878a 6250 tmp = load_reg(s, rd);
86831435 6251 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6252 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6253 }
5e3f878a 6254 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6255 } else {
6256 if (((insn >> 12) & 0xf) != 0xf)
6257 goto illegal_op;
6258 if (((insn >> 16) & 0xf) == 0) {
6259 gen_nop_hint(s, insn & 0xff);
6260 } else {
6261 /* CPSR = immediate */
6262 val = insn & 0xff;
6263 shift = ((insn >> 8) & 0xf) * 2;
6264 if (shift)
6265 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6266 i = ((insn & (1 << 22)) != 0);
2fbac54b 6267 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6268 goto illegal_op;
6269 }
6270 }
6271 } else if ((insn & 0x0f900000) == 0x01000000
6272 && (insn & 0x00000090) != 0x00000090) {
6273 /* miscellaneous instructions */
6274 op1 = (insn >> 21) & 3;
6275 sh = (insn >> 4) & 0xf;
6276 rm = insn & 0xf;
6277 switch (sh) {
6278 case 0x0: /* move program status register */
6279 if (op1 & 1) {
6280 /* PSR = reg */
2fbac54b 6281 tmp = load_reg(s, rm);
9ee6e8bb 6282 i = ((op1 & 2) != 0);
2fbac54b 6283 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6284 goto illegal_op;
6285 } else {
6286 /* reg = PSR */
6287 rd = (insn >> 12) & 0xf;
6288 if (op1 & 2) {
6289 if (IS_USER(s))
6290 goto illegal_op;
d9ba4830 6291 tmp = load_cpu_field(spsr);
9ee6e8bb 6292 } else {
d9ba4830
PB		 6293 tmp = new_tmp();
6294 gen_helper_cpsr_read(tmp);
9ee6e8bb 6295 }
d9ba4830 6296 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6297 }
6298 break;
6299 case 0x1:
6300 if (op1 == 1) {
6301 /* branch/exchange thumb (bx). */
d9ba4830
PB		 6302 tmp = load_reg(s, rm);
6303 gen_bx(s, tmp);
9ee6e8bb
PB		 6304 } else if (op1 == 3) {
6305 /* clz */
6306 rd = (insn >> 12) & 0xf;
1497c961
PB		 6307 tmp = load_reg(s, rm);
6308 gen_helper_clz(tmp, tmp);
6309 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6310 } else {
6311 goto illegal_op;
6312 }
6313 break;
6314 case 0x2:
6315 if (op1 == 1) {
6316 ARCH(5J); /* bxj */
6317 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6318 tmp = load_reg(s, rm);
6319 gen_bx(s, tmp);
9ee6e8bb
PB		 6320 } else {
6321 goto illegal_op;
6322 }
6323 break;
6324 case 0x3:
6325 if (op1 != 1)
6326 goto illegal_op;
6327
6328 /* branch link/exchange thumb (blx) */
d9ba4830
PB		 6329 tmp = load_reg(s, rm);
6330 tmp2 = new_tmp();
6331 tcg_gen_movi_i32(tmp2, s->pc);
6332 store_reg(s, 14, tmp2);
6333 gen_bx(s, tmp);
9ee6e8bb
PB		 6334 break;
6335 case 0x5: /* saturating add/subtract */
6336 rd = (insn >> 12) & 0xf;
6337 rn = (insn >> 16) & 0xf;
b40d0353 6338 tmp = load_reg(s, rm);
5e3f878a 6339 tmp2 = load_reg(s, rn);
9ee6e8bb 6340 if (op1 & 2)
5e3f878a 6341 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6342 if (op1 & 1)
5e3f878a 6343 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6344 else
5e3f878a
PB		 6345 gen_helper_add_saturate(tmp, tmp, tmp2);
6346 dead_tmp(tmp2);
6347 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6348 break;
6349 case 7: /* bkpt */
6350 gen_set_condexec(s);
5e3f878a 6351 gen_set_pc_im(s->pc - 4);
d9ba4830 6352 gen_exception(EXCP_BKPT);
9ee6e8bb
PB		 6353 s->is_jmp = DISAS_JUMP;
6354 break;
6355 case 0x8: /* signed multiply */
6356 case 0xa:
6357 case 0xc:
6358 case 0xe:
6359 rs = (insn >> 8) & 0xf;
6360 rn = (insn >> 12) & 0xf;
6361 rd = (insn >> 16) & 0xf;
6362 if (op1 == 1) {
6363 /* (32 * 16) >> 16 */
5e3f878a
PB		 6364 tmp = load_reg(s, rm);
6365 tmp2 = load_reg(s, rs);
9ee6e8bb 6366 if (sh & 4)
5e3f878a 6367 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6368 else
5e3f878a 6369 gen_sxth(tmp2);
a7812ae4
PB		 6370 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6371 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 6372 tmp = new_tmp();
a7812ae4 6373 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6374 tcg_temp_free_i64(tmp64);
9ee6e8bb 6375 if ((sh & 2) == 0) {
5e3f878a
PB		 6376 tmp2 = load_reg(s, rn);
6377 gen_helper_add_setq(tmp, tmp, tmp2);
6378 dead_tmp(tmp2);
9ee6e8bb 6379 }
5e3f878a 6380 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6381 } else {
6382 /* 16 * 16 */
5e3f878a
PB		 6383 tmp = load_reg(s, rm);
6384 tmp2 = load_reg(s, rs);
6385 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6386 dead_tmp(tmp2);
9ee6e8bb 6387 if (op1 == 2) {
a7812ae4
PB		 6388 tmp64 = tcg_temp_new_i64();
6389 tcg_gen_ext_i32_i64(tmp64, tmp);
22478e79 6390 dead_tmp(tmp);
a7812ae4
PB		 6391 gen_addq(s, tmp64, rn, rd);
6392 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6393 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6394 } else {
6395 if (op1 == 0) {
5e3f878a
PB		 6396 tmp2 = load_reg(s, rn);
6397 gen_helper_add_setq(tmp, tmp, tmp2);
6398 dead_tmp(tmp2);
9ee6e8bb 6399 }
5e3f878a 6400 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6401 }
6402 }
6403 break;
6404 default:
6405 goto illegal_op;
6406 }
6407 } else if (((insn & 0x0e000000) == 0 &&
6408 (insn & 0x00000090) != 0x90) ||
6409 ((insn & 0x0e000000) == (1 << 25))) {
6410 int set_cc, logic_cc, shiftop;
6411
6412 op1 = (insn >> 21) & 0xf;
6413 set_cc = (insn >> 20) & 1;
6414 logic_cc = table_logic_cc[op1] & set_cc;
6415
6416 /* data processing instruction */
6417 if (insn & (1 << 25)) {
6418 /* immediate operand */
6419 val = insn & 0xff;
6420 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6421 if (shift) {
9ee6e8bb 6422 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9
JR		 6423 }
6424 tmp2 = new_tmp();
6425 tcg_gen_movi_i32(tmp2, val);
6426 if (logic_cc && shift) {
6427 gen_set_CF_bit31(tmp2);
6428 }
9ee6e8bb
PB		 6429 } else {
6430 /* register */
6431 rm = (insn) & 0xf;
e9bb4aa9 6432 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6433 shiftop = (insn >> 5) & 3;
6434 if (!(insn & (1 << 4))) {
6435 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6436 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6437 } else {
6438 rs = (insn >> 8) & 0xf;
8984bd2e 6439 tmp = load_reg(s, rs);
e9bb4aa9 6440 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6441 }
6442 }
6443 if (op1 != 0x0f && op1 != 0x0d) {
6444 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6445 tmp = load_reg(s, rn);
6446 } else {
6447 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6448 }
6449 rd = (insn >> 12) & 0xf;
6450 switch(op1) {
6451 case 0x00:
e9bb4aa9
JR		 6452 tcg_gen_and_i32(tmp, tmp, tmp2);
6453 if (logic_cc) {
6454 gen_logic_CC(tmp);
6455 }
21aeb343 6456 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6457 break;
6458 case 0x01:
e9bb4aa9
JR		 6459 tcg_gen_xor_i32(tmp, tmp, tmp2);
6460 if (logic_cc) {
6461 gen_logic_CC(tmp);
6462 }
21aeb343 6463 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6464 break;
6465 case 0x02:
6466 if (set_cc && rd == 15) {
6467 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6468 if (IS_USER(s)) {
9ee6e8bb 6469 goto illegal_op;
e9bb4aa9
JR		 6470 }
6471 gen_helper_sub_cc(tmp, tmp, tmp2);
6472 gen_exception_return(s, tmp);
9ee6e8bb 6473 } else {
e9bb4aa9
JR		 6474 if (set_cc) {
6475 gen_helper_sub_cc(tmp, tmp, tmp2);
6476 } else {
6477 tcg_gen_sub_i32(tmp, tmp, tmp2);
6478 }
21aeb343 6479 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6480 }
6481 break;
6482 case 0x03:
e9bb4aa9
JR		 6483 if (set_cc) {
6484 gen_helper_sub_cc(tmp, tmp2, tmp);
6485 } else {
6486 tcg_gen_sub_i32(tmp, tmp2, tmp);
6487 }
21aeb343 6488 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6489 break;
6490 case 0x04:
e9bb4aa9
JR		 6491 if (set_cc) {
6492 gen_helper_add_cc(tmp, tmp, tmp2);
6493 } else {
6494 tcg_gen_add_i32(tmp, tmp, tmp2);
6495 }
21aeb343 6496 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6497 break;
6498 case 0x05:
e9bb4aa9
JR		 6499 if (set_cc) {
6500 gen_helper_adc_cc(tmp, tmp, tmp2);
6501 } else {
6502 gen_add_carry(tmp, tmp, tmp2);
6503 }
21aeb343 6504 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6505 break;
6506 case 0x06:
e9bb4aa9
JR		 6507 if (set_cc) {
6508 gen_helper_sbc_cc(tmp, tmp, tmp2);
6509 } else {
6510 gen_sub_carry(tmp, tmp, tmp2);
6511 }
21aeb343 6512 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6513 break;
6514 case 0x07:
e9bb4aa9
JR		 6515 if (set_cc) {
6516 gen_helper_sbc_cc(tmp, tmp2, tmp);
6517 } else {
6518 gen_sub_carry(tmp, tmp2, tmp);
6519 }
21aeb343 6520 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6521 break;
6522 case 0x08:
6523 if (set_cc) {
e9bb4aa9
JR		 6524 tcg_gen_and_i32(tmp, tmp, tmp2);
6525 gen_logic_CC(tmp);
9ee6e8bb 6526 }
e9bb4aa9 6527 dead_tmp(tmp);
9ee6e8bb
PB		 6528 break;
6529 case 0x09:
6530 if (set_cc) {
e9bb4aa9
JR		 6531 tcg_gen_xor_i32(tmp, tmp, tmp2);
6532 gen_logic_CC(tmp);
9ee6e8bb 6533 }
e9bb4aa9 6534 dead_tmp(tmp);
9ee6e8bb
PB		 6535 break;
6536 case 0x0a:
6537 if (set_cc) {
e9bb4aa9 6538 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6539 }
e9bb4aa9 6540 dead_tmp(tmp);
9ee6e8bb
PB		 6541 break;
6542 case 0x0b:
6543 if (set_cc) {
e9bb4aa9 6544 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6545 }
e9bb4aa9 6546 dead_tmp(tmp);
9ee6e8bb
PB		 6547 break;
6548 case 0x0c:
e9bb4aa9
JR		 6549 tcg_gen_or_i32(tmp, tmp, tmp2);
6550 if (logic_cc) {
6551 gen_logic_CC(tmp);
6552 }
21aeb343 6553 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6554 break;
6555 case 0x0d:
6556 if (logic_cc && rd == 15) {
6557 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6558 if (IS_USER(s)) {
9ee6e8bb 6559 goto illegal_op;
e9bb4aa9
JR		 6560 }
6561 gen_exception_return(s, tmp2);
9ee6e8bb 6562 } else {
e9bb4aa9
JR		 6563 if (logic_cc) {
6564 gen_logic_CC(tmp2);
6565 }
21aeb343 6566 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6567 }
6568 break;
6569 case 0x0e:
f669df27 6570 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6571 if (logic_cc) {
6572 gen_logic_CC(tmp);
6573 }
21aeb343 6574 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6575 break;
6576 default:
6577 case 0x0f:
e9bb4aa9
JR		 6578 tcg_gen_not_i32(tmp2, tmp2);
6579 if (logic_cc) {
6580 gen_logic_CC(tmp2);
6581 }
21aeb343 6582 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6583 break;
6584 }
e9bb4aa9
JR		 6585 if (op1 != 0x0f && op1 != 0x0d) {
6586 dead_tmp(tmp2);
6587 }
9ee6e8bb
PB		 6588 } else {
6589 /* other instructions */
6590 op1 = (insn >> 24) & 0xf;
6591 switch(op1) {
6592 case 0x0:
6593 case 0x1:
6594 /* multiplies, extra load/stores */
6595 sh = (insn >> 5) & 3;
6596 if (sh == 0) {
6597 if (op1 == 0x0) {
6598 rd = (insn >> 16) & 0xf;
6599 rn = (insn >> 12) & 0xf;
6600 rs = (insn >> 8) & 0xf;
6601 rm = (insn) & 0xf;
6602 op1 = (insn >> 20) & 0xf;
6603 switch (op1) {
6604 case 0: case 1: case 2: case 3: case 6:
6605 /* 32 bit mul */
5e3f878a
PB		 6606 tmp = load_reg(s, rs);
6607 tmp2 = load_reg(s, rm);
6608 tcg_gen_mul_i32(tmp, tmp, tmp2);
6609 dead_tmp(tmp2);
9ee6e8bb
PB		 6610 if (insn & (1 << 22)) {
6611 /* Subtract (mls) */
6612 ARCH(6T2);
5e3f878a
PB		 6613 tmp2 = load_reg(s, rn);
6614 tcg_gen_sub_i32(tmp, tmp2, tmp);
6615 dead_tmp(tmp2);
9ee6e8bb
PB		 6616 } else if (insn & (1 << 21)) {
6617 /* Add */
5e3f878a
PB		 6618 tmp2 = load_reg(s, rn);
6619 tcg_gen_add_i32(tmp, tmp, tmp2);
6620 dead_tmp(tmp2);
9ee6e8bb
PB		 6621 }
6622 if (insn & (1 << 20))
5e3f878a
PB		 6623 gen_logic_CC(tmp);
6624 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6625 break;
6626 default:
6627 /* 64 bit mul */
5e3f878a
PB		 6628 tmp = load_reg(s, rs);
6629 tmp2 = load_reg(s, rm);
9ee6e8bb 6630 if (insn & (1 << 22))
a7812ae4 6631 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6632 else
a7812ae4 6633 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
9ee6e8bb 6634 if (insn & (1 << 21)) /* mult accumulate */
a7812ae4 6635 gen_addq(s, tmp64, rn, rd);
9ee6e8bb
PB		 6636 if (!(insn & (1 << 23))) { /* double accumulate */
6637 ARCH(6);
a7812ae4
PB		 6638 gen_addq_lo(s, tmp64, rn);
6639 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 6640 }
6641 if (insn & (1 << 20))
a7812ae4
PB		 6642 gen_logicq_cc(tmp64);
6643 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6644 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6645 break;
6646 }
6647 } else {
6648 rn = (insn >> 16) & 0xf;
6649 rd = (insn >> 12) & 0xf;
6650 if (insn & (1 << 23)) {
6651 /* load/store exclusive */
86753403
PB		 6652 op1 = (insn >> 21) & 0x3;
6653 if (op1)
a47f43d2 6654 ARCH(6K);
86753403
PB		 6655 else
6656 ARCH(6);
3174f8e9 6657 addr = tcg_temp_local_new_i32();
98a46317 6658 load_reg_var(s, addr, rn);
9ee6e8bb 6659 if (insn & (1 << 20)) {
86753403
PB		 6660 switch (op1) {
6661 case 0: /* ldrex */
426f5abc 6662 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6663 break;
6664 case 1: /* ldrexd */
426f5abc 6665 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6666 break;
6667 case 2: /* ldrexb */
426f5abc 6668 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6669 break;
6670 case 3: /* ldrexh */
426f5abc 6671 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6672 break;
6673 default:
6674 abort();
6675 }
9ee6e8bb
PB		 6676 } else {
6677 rm = insn & 0xf;
86753403
PB		 6678 switch (op1) {
6679 case 0: /* strex */
426f5abc 6680 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6681 break;
6682 case 1: /* strexd */
502e64fe 6683 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6684 break;
6685 case 2: /* strexb */
426f5abc 6686 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6687 break;
6688 case 3: /* strexh */
426f5abc 6689 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6690 break;
6691 default:
6692 abort();
6693 }
9ee6e8bb 6694 }
3174f8e9 6695 tcg_temp_free(addr);
9ee6e8bb
PB		 6696 } else {
6697 /* SWP instruction */
6698 rm = (insn) & 0xf;
6699
8984bd2e
PB		 6700 /* ??? This is not really atomic. However we know
6701 we never have multiple CPUs running in parallel,
6702 so it is good enough. */
6703 addr = load_reg(s, rn);
6704 tmp = load_reg(s, rm);
9ee6e8bb 6705 if (insn & (1 << 22)) {
8984bd2e
PB		 6706 tmp2 = gen_ld8u(addr, IS_USER(s));
6707 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6708 } else {
8984bd2e
PB		 6709 tmp2 = gen_ld32(addr, IS_USER(s));
6710 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6711 }
8984bd2e
PB		 6712 dead_tmp(addr);
6713 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6714 }
6715 }
6716 } else {
6717 int address_offset;
6718 int load;
6719 /* Misc load/store */
6720 rn = (insn >> 16) & 0xf;
6721 rd = (insn >> 12) & 0xf;
b0109805 6722 addr = load_reg(s, rn);
9ee6e8bb 6723 if (insn & (1 << 24))
b0109805 6724 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6725 address_offset = 0;
6726 if (insn & (1 << 20)) {
6727 /* load */
6728 switch(sh) {
6729 case 1:
b0109805 6730 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6731 break;
6732 case 2:
b0109805 6733 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6734 break;
6735 default:
6736 case 3:
b0109805 6737 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6738 break;
6739 }
6740 load = 1;
6741 } else if (sh & 2) {
6742 /* doubleword */
6743 if (sh & 1) {
6744 /* store */
b0109805
PB		 6745 tmp = load_reg(s, rd);
6746 gen_st32(tmp, addr, IS_USER(s));
6747 tcg_gen_addi_i32(addr, addr, 4);
6748 tmp = load_reg(s, rd + 1);
6749 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6750 load = 0;
6751 } else {
6752 /* load */
b0109805
PB		 6753 tmp = gen_ld32(addr, IS_USER(s));
6754 store_reg(s, rd, tmp);
6755 tcg_gen_addi_i32(addr, addr, 4);
6756 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6757 rd++;
6758 load = 1;
6759 }
6760 address_offset = -4;
6761 } else {
6762 /* store */
b0109805
PB		 6763 tmp = load_reg(s, rd);
6764 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6765 load = 0;
6766 }
6767 /* Perform base writeback before the loaded value to
6768 ensure correct behavior with overlapping index registers.
6769 ldrd with base writeback is is undefined if the
6770 destination and index registers overlap. */
6771 if (!(insn & (1 << 24))) {
b0109805
PB		 6772 gen_add_datah_offset(s, insn, address_offset, addr);
6773 store_reg(s, rn, addr);
9ee6e8bb
PB		 6774 } else if (insn & (1 << 21)) {
6775 if (address_offset)
b0109805
PB		 6776 tcg_gen_addi_i32(addr, addr, address_offset);
6777 store_reg(s, rn, addr);
6778 } else {
6779 dead_tmp(addr);
9ee6e8bb
PB		 6780 }
6781 if (load) {
6782 /* Complete the load. */
b0109805 6783 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6784 }
6785 }
6786 break;
6787 case 0x4:
6788 case 0x5:
6789 goto do_ldst;
6790 case 0x6:
6791 case 0x7:
6792 if (insn & (1 << 4)) {
6793 ARCH(6);
6794 /* Armv6 Media instructions. */
6795 rm = insn & 0xf;
6796 rn = (insn >> 16) & 0xf;
2c0262af 6797 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6798 rs = (insn >> 8) & 0xf;
6799 switch ((insn >> 23) & 3) {
6800 case 0: /* Parallel add/subtract. */
6801 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6802 tmp = load_reg(s, rn);
6803 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6804 sh = (insn >> 5) & 7;
6805 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6806 goto illegal_op;
6ddbc6e4
PB		 6807 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6808 dead_tmp(tmp2);
6809 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6810 break;
6811 case 1:
6812 if ((insn & 0x00700020) == 0) {
6c95676b 6813 /* Halfword pack. */
3670669c
PB		 6814 tmp = load_reg(s, rn);
6815 tmp2 = load_reg(s, rm);
9ee6e8bb 6816 shift = (insn >> 7) & 0x1f;
3670669c
PB		 6817 if (insn & (1 << 6)) {
6818 /* pkhtb */
22478e79
AZ		 6819 if (shift == 0)
6820 shift = 31;
6821 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 6822 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 6823 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 6824 } else {
6825 /* pkhbt */
22478e79
AZ		 6826 if (shift)
6827 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 6828 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 6829 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6830 }
6831 tcg_gen_or_i32(tmp, tmp, tmp2);
22478e79 6832 dead_tmp(tmp2);
3670669c 6833 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6834 } else if ((insn & 0x00200020) == 0x00200000) {
6835 /* [us]sat */
6ddbc6e4 6836 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6837 shift = (insn >> 7) & 0x1f;
6838 if (insn & (1 << 6)) {
6839 if (shift == 0)
6840 shift = 31;
6ddbc6e4 6841 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6842 } else {
6ddbc6e4 6843 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6844 }
6845 sh = (insn >> 16) & 0x1f;
6846 if (sh != 0) {
b75263d6 6847 tmp2 = tcg_const_i32(sh);
9ee6e8bb 6848 if (insn & (1 << 22))
b75263d6 6849 gen_helper_usat(tmp, tmp, tmp2);
9ee6e8bb 6850 else
b75263d6
JR		 6851 gen_helper_ssat(tmp, tmp, tmp2);
6852 tcg_temp_free_i32(tmp2);
9ee6e8bb 6853 }
6ddbc6e4 6854 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6855 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6856 /* [us]sat16 */
6ddbc6e4 6857 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6858 sh = (insn >> 16) & 0x1f;
6859 if (sh != 0) {
b75263d6 6860 tmp2 = tcg_const_i32(sh);
9ee6e8bb 6861 if (insn & (1 << 22))
b75263d6 6862 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 6863 else
b75263d6
JR		 6864 gen_helper_ssat16(tmp, tmp, tmp2);
6865 tcg_temp_free_i32(tmp2);
9ee6e8bb 6866 }
6ddbc6e4 6867 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6868 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6869 /* Select bytes. */
6ddbc6e4
PB		 6870 tmp = load_reg(s, rn);
6871 tmp2 = load_reg(s, rm);
6872 tmp3 = new_tmp();
6873 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6874 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6875 dead_tmp(tmp3);
6876 dead_tmp(tmp2);
6877 store_reg(s, rd, tmp);
9ee6e8bb 6878 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6879 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6880 shift = (insn >> 10) & 3;
6881 /* ??? In many cases it's not neccessary to do a
6882 rotate, a shift is sufficient. */
6883 if (shift != 0)
f669df27 6884 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6885 op1 = (insn >> 20) & 7;
6886 switch (op1) {
5e3f878a
PB		 6887 case 0: gen_sxtb16(tmp); break;
6888 case 2: gen_sxtb(tmp); break;
6889 case 3: gen_sxth(tmp); break;
6890 case 4: gen_uxtb16(tmp); break;
6891 case 6: gen_uxtb(tmp); break;
6892 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 6893 default: goto illegal_op;
6894 }
6895 if (rn != 15) {
5e3f878a 6896 tmp2 = load_reg(s, rn);
9ee6e8bb 6897 if ((op1 & 3) == 0) {
5e3f878a 6898 gen_add16(tmp, tmp2);
9ee6e8bb 6899 } else {
5e3f878a
PB		 6900 tcg_gen_add_i32(tmp, tmp, tmp2);
6901 dead_tmp(tmp2);
9ee6e8bb
PB		 6902 }
6903 }
6c95676b 6904 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6905 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6906 /* rev */
b0109805 6907 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6908 if (insn & (1 << 22)) {
6909 if (insn & (1 << 7)) {
b0109805 6910 gen_revsh(tmp);
9ee6e8bb
PB		 6911 } else {
6912 ARCH(6T2);
b0109805 6913 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 6914 }
6915 } else {
6916 if (insn & (1 << 7))
b0109805 6917 gen_rev16(tmp);
9ee6e8bb 6918 else
66896cb8 6919 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 6920 }
b0109805 6921 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6922 } else {
6923 goto illegal_op;
6924 }
6925 break;
6926 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 6927 tmp = load_reg(s, rm);
6928 tmp2 = load_reg(s, rs);
9ee6e8bb
PB		 6929 if (insn & (1 << 20)) {
6930 /* Signed multiply most significant [accumulate]. */
a7812ae4 6931 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6932 if (insn & (1 << 5))
a7812ae4
PB		 6933 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
6934 tcg_gen_shri_i64(tmp64, tmp64, 32);
5e3f878a 6935 tmp = new_tmp();
a7812ae4 6936 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6937 tcg_temp_free_i64(tmp64);
955a7dd5
AZ		 6938 if (rd != 15) {
6939 tmp2 = load_reg(s, rd);
9ee6e8bb 6940 if (insn & (1 << 6)) {
5e3f878a 6941 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 6942 } else {
5e3f878a 6943 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 6944 }
5e3f878a 6945 dead_tmp(tmp2);
9ee6e8bb 6946 }
955a7dd5 6947 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6948 } else {
6949 if (insn & (1 << 5))
5e3f878a
PB		 6950 gen_swap_half(tmp2);
6951 gen_smul_dual(tmp, tmp2);
6952 /* This addition cannot overflow. */
6953 if (insn & (1 << 6)) {
6954 tcg_gen_sub_i32(tmp, tmp, tmp2);
6955 } else {
6956 tcg_gen_add_i32(tmp, tmp, tmp2);
6957 }
6958 dead_tmp(tmp2);
9ee6e8bb 6959 if (insn & (1 << 22)) {
5e3f878a 6960 /* smlald, smlsld */
a7812ae4
PB		 6961 tmp64 = tcg_temp_new_i64();
6962 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 6963 dead_tmp(tmp);
a7812ae4
PB		 6964 gen_addq(s, tmp64, rd, rn);
6965 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 6966 tcg_temp_free_i64(tmp64);
9ee6e8bb 6967 } else {
5e3f878a 6968 /* smuad, smusd, smlad, smlsd */
22478e79 6969 if (rd != 15)
9ee6e8bb 6970 {
22478e79 6971 tmp2 = load_reg(s, rd);
5e3f878a
PB		 6972 gen_helper_add_setq(tmp, tmp, tmp2);
6973 dead_tmp(tmp2);
9ee6e8bb 6974 }
22478e79 6975 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6976 }
6977 }
6978 break;
6979 case 3:
6980 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6981 switch (op1) {
6982 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 6983 ARCH(6);
6984 tmp = load_reg(s, rm);
6985 tmp2 = load_reg(s, rs);
6986 gen_helper_usad8(tmp, tmp, tmp2);
6987 dead_tmp(tmp2);
ded9d295
AZ		 6988 if (rd != 15) {
6989 tmp2 = load_reg(s, rd);
6ddbc6e4
PB		 6990 tcg_gen_add_i32(tmp, tmp, tmp2);
6991 dead_tmp(tmp2);
9ee6e8bb 6992 }
ded9d295 6993 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6994 break;
6995 case 0x20: case 0x24: case 0x28: case 0x2c:
6996 /* Bitfield insert/clear. */
6997 ARCH(6T2);
6998 shift = (insn >> 7) & 0x1f;
6999 i = (insn >> 16) & 0x1f;
7000 i = i + 1 - shift;
7001 if (rm == 15) {
5e3f878a
PB		 7002 tmp = new_tmp();
7003 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7004 } else {
5e3f878a 7005 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7006 }
7007 if (i != 32) {
5e3f878a 7008 tmp2 = load_reg(s, rd);
8f8e3aa4 7009 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
5e3f878a 7010 dead_tmp(tmp2);
9ee6e8bb 7011 }
5e3f878a 7012 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7013 break;
7014 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7015 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7016 ARCH(6T2);
5e3f878a 7017 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7018 shift = (insn >> 7) & 0x1f;
7019 i = ((insn >> 16) & 0x1f) + 1;
7020 if (shift + i > 32)
7021 goto illegal_op;
7022 if (i < 32) {
7023 if (op1 & 0x20) {
5e3f878a 7024 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7025 } else {
5e3f878a 7026 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7027 }
7028 }
5e3f878a 7029 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7030 break;
7031 default:
7032 goto illegal_op;
7033 }
7034 break;
7035 }
7036 break;
7037 }
7038 do_ldst:
7039 /* Check for undefined extension instructions
7040 * per the ARM Bible IE:
7041 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7042 */
7043 sh = (0xf << 20) | (0xf << 4);
7044 if (op1 == 0x7 && ((insn & sh) == sh))
7045 {
7046 goto illegal_op;
7047 }
7048 /* load/store byte/word */
7049 rn = (insn >> 16) & 0xf;
7050 rd = (insn >> 12) & 0xf;
b0109805 7051 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7052 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7053 if (insn & (1 << 24))
b0109805 7054 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7055 if (insn & (1 << 20)) {
7056 /* load */
9ee6e8bb 7057 if (insn & (1 << 22)) {
b0109805 7058 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7059 } else {
b0109805 7060 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7061 }
9ee6e8bb
PB		 7062 } else {
7063 /* store */
b0109805 7064 tmp = load_reg(s, rd);
9ee6e8bb 7065 if (insn & (1 << 22))
b0109805 7066 gen_st8(tmp, tmp2, i);
9ee6e8bb 7067 else
b0109805 7068 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7069 }
7070 if (!(insn & (1 << 24))) {
b0109805
PB		 7071 gen_add_data_offset(s, insn, tmp2);
7072 store_reg(s, rn, tmp2);
7073 } else if (insn & (1 << 21)) {
7074 store_reg(s, rn, tmp2);
7075 } else {
7076 dead_tmp(tmp2);
9ee6e8bb
PB		 7077 }
7078 if (insn & (1 << 20)) {
7079 /* Complete the load. */
7080 if (rd == 15)
b0109805 7081 gen_bx(s, tmp);
9ee6e8bb 7082 else
b0109805 7083 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7084 }
7085 break;
7086 case 0x08:
7087 case 0x09:
7088 {
7089 int j, n, user, loaded_base;
b0109805 7090 TCGv loaded_var;
9ee6e8bb
PB		 7091 /* load/store multiple words */
7092 /* XXX: store correct base if write back */
7093 user = 0;
7094 if (insn & (1 << 22)) {
7095 if (IS_USER(s))
7096 goto illegal_op; /* only usable in supervisor mode */
7097
7098 if ((insn & (1 << 15)) == 0)
7099 user = 1;
7100 }
7101 rn = (insn >> 16) & 0xf;
b0109805 7102 addr = load_reg(s, rn);
9ee6e8bb
PB		 7103
7104 /* compute total size */
7105 loaded_base = 0;
a50f5b91 7106 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7107 n = 0;
7108 for(i=0;i<16;i++) {
7109 if (insn & (1 << i))
7110 n++;
7111 }
7112 /* XXX: test invalid n == 0 case ? */
7113 if (insn & (1 << 23)) {
7114 if (insn & (1 << 24)) {
7115 /* pre increment */
b0109805 7116 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7117 } else {
7118 /* post increment */
7119 }
7120 } else {
7121 if (insn & (1 << 24)) {
7122 /* pre decrement */
b0109805 7123 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7124 } else {
7125 /* post decrement */
7126 if (n != 1)
b0109805 7127 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7128 }
7129 }
7130 j = 0;
7131 for(i=0;i<16;i++) {
7132 if (insn & (1 << i)) {
7133 if (insn & (1 << 20)) {
7134 /* load */
b0109805 7135 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7136 if (i == 15) {
b0109805 7137 gen_bx(s, tmp);
9ee6e8bb 7138 } else if (user) {
b75263d6
JR		 7139 tmp2 = tcg_const_i32(i);
7140 gen_helper_set_user_reg(tmp2, tmp);
7141 tcg_temp_free_i32(tmp2);
b0109805 7142 dead_tmp(tmp);
9ee6e8bb 7143 } else if (i == rn) {
b0109805 7144 loaded_var = tmp;
9ee6e8bb
PB		 7145 loaded_base = 1;
7146 } else {
b0109805 7147 store_reg(s, i, tmp);
9ee6e8bb
PB		 7148 }
7149 } else {
7150 /* store */
7151 if (i == 15) {
7152 /* special case: r15 = PC + 8 */
7153 val = (long)s->pc + 4;
b0109805
PB		 7154 tmp = new_tmp();
7155 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7156 } else if (user) {
b0109805 7157 tmp = new_tmp();
b75263d6
JR		 7158 tmp2 = tcg_const_i32(i);
7159 gen_helper_get_user_reg(tmp, tmp2);
7160 tcg_temp_free_i32(tmp2);
9ee6e8bb 7161 } else {
b0109805 7162 tmp = load_reg(s, i);
9ee6e8bb 7163 }
b0109805 7164 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7165 }
7166 j++;
7167 /* no need to add after the last transfer */
7168 if (j != n)
b0109805 7169 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7170 }
7171 }
7172 if (insn & (1 << 21)) {
7173 /* write back */
7174 if (insn & (1 << 23)) {
7175 if (insn & (1 << 24)) {
7176 /* pre increment */
7177 } else {
7178 /* post increment */
b0109805 7179 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7180 }
7181 } else {
7182 if (insn & (1 << 24)) {
7183 /* pre decrement */
7184 if (n != 1)
b0109805 7185 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7186 } else {
7187 /* post decrement */
b0109805 7188 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7189 }
7190 }
b0109805
PB		 7191 store_reg(s, rn, addr);
7192 } else {
7193 dead_tmp(addr);
9ee6e8bb
PB		 7194 }
7195 if (loaded_base) {
b0109805 7196 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7197 }
7198 if ((insn & (1 << 22)) && !user) {
7199 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7200 tmp = load_cpu_field(spsr);
7201 gen_set_cpsr(tmp, 0xffffffff);
7202 dead_tmp(tmp);
9ee6e8bb
PB		 7203 s->is_jmp = DISAS_UPDATE;
7204 }
7205 }
7206 break;
7207 case 0xa:
7208 case 0xb:
7209 {
7210 int32_t offset;
7211
7212 /* branch (and link) */
7213 val = (int32_t)s->pc;
7214 if (insn & (1 << 24)) {
5e3f878a
PB		 7215 tmp = new_tmp();
7216 tcg_gen_movi_i32(tmp, val);
7217 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7218 }
7219 offset = (((int32_t)insn << 8) >> 8);
7220 val += (offset << 2) + 4;
7221 gen_jmp(s, val);
7222 }
7223 break;
7224 case 0xc:
7225 case 0xd:
7226 case 0xe:
7227 /* Coprocessor. */
7228 if (disas_coproc_insn(env, s, insn))
7229 goto illegal_op;
7230 break;
7231 case 0xf:
7232 /* swi */
5e3f878a 7233 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7234 s->is_jmp = DISAS_SWI;
7235 break;
7236 default:
7237 illegal_op:
7238 gen_set_condexec(s);
5e3f878a 7239 gen_set_pc_im(s->pc - 4);
d9ba4830 7240 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 7241 s->is_jmp = DISAS_JUMP;
7242 break;
7243 }
7244 }
7245}
7246
7247/* Return true if this is a Thumb-2 logical op. */
7248static int
7249thumb2_logic_op(int op)
7250{
7251 return (op < 8);
7252}
7253
7254/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7255 then set condition code flags based on the result of the operation.
7256 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7257 to the high bit of T1.
7258 Returns zero if the opcode is valid. */
7259
7260static int
396e467c 7261gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7262{
7263 int logic_cc;
7264
7265 logic_cc = 0;
7266 switch (op) {
7267 case 0: /* and */
396e467c 7268 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7269 logic_cc = conds;
7270 break;
7271 case 1: /* bic */
f669df27 7272 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7273 logic_cc = conds;
7274 break;
7275 case 2: /* orr */
396e467c 7276 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7277 logic_cc = conds;
7278 break;
7279 case 3: /* orn */
396e467c
FN		 7280 tcg_gen_not_i32(t1, t1);
7281 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7282 logic_cc = conds;
7283 break;
7284 case 4: /* eor */
396e467c 7285 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7286 logic_cc = conds;
7287 break;
7288 case 8: /* add */
7289 if (conds)
396e467c 7290 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7291 else
396e467c 7292 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7293 break;
7294 case 10: /* adc */
7295 if (conds)
396e467c 7296 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7297 else
396e467c 7298 gen_adc(t0, t1);
9ee6e8bb
PB		 7299 break;
7300 case 11: /* sbc */
7301 if (conds)
396e467c 7302 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7303 else
396e467c 7304 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7305 break;
7306 case 13: /* sub */
7307 if (conds)
396e467c 7308 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7309 else
396e467c 7310 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7311 break;
7312 case 14: /* rsb */
7313 if (conds)
396e467c 7314 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7315 else
396e467c 7316 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7317 break;
7318 default: /* 5, 6, 7, 9, 12, 15. */
7319 return 1;
7320 }
7321 if (logic_cc) {
396e467c 7322 gen_logic_CC(t0);
9ee6e8bb 7323 if (shifter_out)
396e467c 7324 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7325 }
7326 return 0;
7327}
7328
7329/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7330 is not legal. */
7331static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7332{
b0109805 7333 uint32_t insn, imm, shift, offset;
9ee6e8bb 7334 uint32_t rd, rn, rm, rs;
b26eefb6 7335 TCGv tmp;
6ddbc6e4
PB		 7336 TCGv tmp2;
7337 TCGv tmp3;
b0109805 7338 TCGv addr;
a7812ae4 7339 TCGv_i64 tmp64;
9ee6e8bb
PB		 7340 int op;
7341 int shiftop;
7342 int conds;
7343 int logic_cc;
7344
7345 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7346 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7347 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7348 16-bit instructions to get correct prefetch abort behavior. */
7349 insn = insn_hw1;
7350 if ((insn & (1 << 12)) == 0) {
7351 /* Second half of blx. */
7352 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7353 tmp = load_reg(s, 14);
7354 tcg_gen_addi_i32(tmp, tmp, offset);
7355 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7356
d9ba4830 7357 tmp2 = new_tmp();
b0109805 7358 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7359 store_reg(s, 14, tmp2);
7360 gen_bx(s, tmp);
9ee6e8bb
PB		 7361 return 0;
7362 }
7363 if (insn & (1 << 11)) {
7364 /* Second half of bl. */
7365 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7366 tmp = load_reg(s, 14);
6a0d8a1d 7367 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7368
d9ba4830 7369 tmp2 = new_tmp();
b0109805 7370 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7371 store_reg(s, 14, tmp2);
7372 gen_bx(s, tmp);
9ee6e8bb
PB		 7373 return 0;
7374 }
7375 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7376 /* Instruction spans a page boundary. Implement it as two
7377 16-bit instructions in case the second half causes an
7378 prefetch abort. */
7379 offset = ((int32_t)insn << 21) >> 9;
396e467c 7380 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7381 return 0;
7382 }
7383 /* Fall through to 32-bit decode. */
7384 }
7385
7386 insn = lduw_code(s->pc);
7387 s->pc += 2;
7388 insn |= (uint32_t)insn_hw1 << 16;
7389
7390 if ((insn & 0xf800e800) != 0xf000e800) {
7391 ARCH(6T2);
7392 }
7393
7394 rn = (insn >> 16) & 0xf;
7395 rs = (insn >> 12) & 0xf;
7396 rd = (insn >> 8) & 0xf;
7397 rm = insn & 0xf;
7398 switch ((insn >> 25) & 0xf) {
7399 case 0: case 1: case 2: case 3:
7400 /* 16-bit instructions. Should never happen. */
7401 abort();
7402 case 4:
7403 if (insn & (1 << 22)) {
7404 /* Other load/store, table branch. */
7405 if (insn & 0x01200000) {
7406 /* Load/store doubleword. */
7407 if (rn == 15) {
b0109805
PB		 7408 addr = new_tmp();
7409 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7410 } else {
b0109805 7411 addr = load_reg(s, rn);
9ee6e8bb
PB		 7412 }
7413 offset = (insn & 0xff) * 4;
7414 if ((insn & (1 << 23)) == 0)
7415 offset = -offset;
7416 if (insn & (1 << 24)) {
b0109805 7417 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7418 offset = 0;
7419 }
7420 if (insn & (1 << 20)) {
7421 /* ldrd */
b0109805
PB		 7422 tmp = gen_ld32(addr, IS_USER(s));
7423 store_reg(s, rs, tmp);
7424 tcg_gen_addi_i32(addr, addr, 4);
7425 tmp = gen_ld32(addr, IS_USER(s));
7426 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7427 } else {
7428 /* strd */
b0109805
PB		 7429 tmp = load_reg(s, rs);
7430 gen_st32(tmp, addr, IS_USER(s));
7431 tcg_gen_addi_i32(addr, addr, 4);
7432 tmp = load_reg(s, rd);
7433 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7434 }
7435 if (insn & (1 << 21)) {
7436 /* Base writeback. */
7437 if (rn == 15)
7438 goto illegal_op;
b0109805
PB		 7439 tcg_gen_addi_i32(addr, addr, offset - 4);
7440 store_reg(s, rn, addr);
7441 } else {
7442 dead_tmp(addr);
9ee6e8bb
PB		 7443 }
7444 } else if ((insn & (1 << 23)) == 0) {
7445 /* Load/store exclusive word. */
3174f8e9 7446 addr = tcg_temp_local_new();
98a46317 7447 load_reg_var(s, addr, rn);
426f5abc 7448 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7449 if (insn & (1 << 20)) {
426f5abc 7450 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7451 } else {
426f5abc 7452 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7453 }
3174f8e9 7454 tcg_temp_free(addr);
9ee6e8bb
PB		 7455 } else if ((insn & (1 << 6)) == 0) {
7456 /* Table Branch. */
7457 if (rn == 15) {
b0109805
PB		 7458 addr = new_tmp();
7459 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7460 } else {
b0109805 7461 addr = load_reg(s, rn);
9ee6e8bb 7462 }
b26eefb6 7463 tmp = load_reg(s, rm);
b0109805 7464 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7465 if (insn & (1 << 4)) {
7466 /* tbh */
b0109805 7467 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7468 dead_tmp(tmp);
b0109805 7469 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7470 } else { /* tbb */
b26eefb6 7471 dead_tmp(tmp);
b0109805 7472 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7473 }
b0109805
PB		 7474 dead_tmp(addr);
7475 tcg_gen_shli_i32(tmp, tmp, 1);
7476 tcg_gen_addi_i32(tmp, tmp, s->pc);
7477 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7478 } else {
7479 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7480 ARCH(7);
9ee6e8bb 7481 op = (insn >> 4) & 0x3;
426f5abc
PB		 7482 if (op == 2) {
7483 goto illegal_op;
7484 }
3174f8e9 7485 addr = tcg_temp_local_new();
98a46317 7486 load_reg_var(s, addr, rn);
9ee6e8bb 7487 if (insn & (1 << 20)) {
426f5abc 7488 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7489 } else {
426f5abc 7490 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7491 }
3174f8e9 7492 tcg_temp_free(addr);
9ee6e8bb
PB		 7493 }
7494 } else {
7495 /* Load/store multiple, RFE, SRS. */
7496 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7497 /* Not available in user mode. */
b0109805 7498 if (IS_USER(s))
9ee6e8bb
PB		 7499 goto illegal_op;
7500 if (insn & (1 << 20)) {
7501 /* rfe */
b0109805
PB		 7502 addr = load_reg(s, rn);
7503 if ((insn & (1 << 24)) == 0)
7504 tcg_gen_addi_i32(addr, addr, -8);
7505 /* Load PC into tmp and CPSR into tmp2. */
7506 tmp = gen_ld32(addr, 0);
7507 tcg_gen_addi_i32(addr, addr, 4);
7508 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7509 if (insn & (1 << 21)) {
7510 /* Base writeback. */
b0109805
PB		 7511 if (insn & (1 << 24)) {
7512 tcg_gen_addi_i32(addr, addr, 4);
7513 } else {
7514 tcg_gen_addi_i32(addr, addr, -4);
7515 }
7516 store_reg(s, rn, addr);
7517 } else {
7518 dead_tmp(addr);
9ee6e8bb 7519 }
b0109805 7520 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7521 } else {
7522 /* srs */
7523 op = (insn & 0x1f);
7524 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7525 addr = load_reg(s, 13);
9ee6e8bb 7526 } else {
b0109805 7527 addr = new_tmp();
b75263d6
JR		 7528 tmp = tcg_const_i32(op);
7529 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7530 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7531 }
7532 if ((insn & (1 << 24)) == 0) {
b0109805 7533 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7534 }
b0109805
PB		 7535 tmp = load_reg(s, 14);
7536 gen_st32(tmp, addr, 0);
7537 tcg_gen_addi_i32(addr, addr, 4);
7538 tmp = new_tmp();
7539 gen_helper_cpsr_read(tmp);
7540 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7541 if (insn & (1 << 21)) {
7542 if ((insn & (1 << 24)) == 0) {
b0109805 7543 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7544 } else {
b0109805 7545 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7546 }
7547 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7548 store_reg(s, 13, addr);
9ee6e8bb 7549 } else {
b75263d6
JR		 7550 tmp = tcg_const_i32(op);
7551 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7552 tcg_temp_free_i32(tmp);
9ee6e8bb 7553 }
b0109805
PB		 7554 } else {
7555 dead_tmp(addr);
9ee6e8bb
PB		 7556 }
7557 }
7558 } else {
7559 int i;
7560 /* Load/store multiple. */
b0109805 7561 addr = load_reg(s, rn);
9ee6e8bb
PB		 7562 offset = 0;
7563 for (i = 0; i < 16; i++) {
7564 if (insn & (1 << i))
7565 offset += 4;
7566 }
7567 if (insn & (1 << 24)) {
b0109805 7568 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7569 }
7570
7571 for (i = 0; i < 16; i++) {
7572 if ((insn & (1 << i)) == 0)
7573 continue;
7574 if (insn & (1 << 20)) {
7575 /* Load. */
b0109805 7576 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7577 if (i == 15) {
b0109805 7578 gen_bx(s, tmp);
9ee6e8bb 7579 } else {
b0109805 7580 store_reg(s, i, tmp);
9ee6e8bb
PB		 7581 }
7582 } else {
7583 /* Store. */
b0109805
PB		 7584 tmp = load_reg(s, i);
7585 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7586 }
b0109805 7587 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7588 }
7589 if (insn & (1 << 21)) {
7590 /* Base register writeback. */
7591 if (insn & (1 << 24)) {
b0109805 7592 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7593 }
7594 /* Fault if writeback register is in register list. */
7595 if (insn & (1 << rn))
7596 goto illegal_op;
b0109805
PB		 7597 store_reg(s, rn, addr);
7598 } else {
7599 dead_tmp(addr);
9ee6e8bb
PB		 7600 }
7601 }
7602 }
7603 break;
7604 case 5: /* Data processing register constant shift. */
3174f8e9
FN		 7605 if (rn == 15) {
7606 tmp = new_tmp();
7607 tcg_gen_movi_i32(tmp, 0);
7608 } else {
7609 tmp = load_reg(s, rn);
7610 }
7611 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7612 op = (insn >> 21) & 0xf;
7613 shiftop = (insn >> 4) & 3;
7614 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7615 conds = (insn & (1 << 20)) != 0;
7616 logic_cc = (conds && thumb2_logic_op(op));
3174f8e9
FN		 7617 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7618 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
9ee6e8bb 7619 goto illegal_op;
3174f8e9
FN		 7620 dead_tmp(tmp2);
7621 if (rd != 15) {
7622 store_reg(s, rd, tmp);
7623 } else {
7624 dead_tmp(tmp);
7625 }
9ee6e8bb
PB		 7626 break;
7627 case 13: /* Misc data processing. */
7628 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7629 if (op < 4 && (insn & 0xf000) != 0xf000)
7630 goto illegal_op;
7631 switch (op) {
7632 case 0: /* Register controlled shift. */
8984bd2e
PB		 7633 tmp = load_reg(s, rn);
7634 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7635 if ((insn & 0x70) != 0)
7636 goto illegal_op;
7637 op = (insn >> 21) & 3;
8984bd2e
PB		 7638 logic_cc = (insn & (1 << 20)) != 0;
7639 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7640 if (logic_cc)
7641 gen_logic_CC(tmp);
21aeb343 7642 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7643 break;
7644 case 1: /* Sign/zero extend. */
5e3f878a 7645 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7646 shift = (insn >> 4) & 3;
7647 /* ??? In many cases it's not neccessary to do a
7648 rotate, a shift is sufficient. */
7649 if (shift != 0)
f669df27 7650 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7651 op = (insn >> 20) & 7;
7652 switch (op) {
5e3f878a
PB		 7653 case 0: gen_sxth(tmp); break;
7654 case 1: gen_uxth(tmp); break;
7655 case 2: gen_sxtb16(tmp); break;
7656 case 3: gen_uxtb16(tmp); break;
7657 case 4: gen_sxtb(tmp); break;
7658 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7659 default: goto illegal_op;
7660 }
7661 if (rn != 15) {
5e3f878a 7662 tmp2 = load_reg(s, rn);
9ee6e8bb 7663 if ((op >> 1) == 1) {
5e3f878a 7664 gen_add16(tmp, tmp2);
9ee6e8bb 7665 } else {
5e3f878a
PB		 7666 tcg_gen_add_i32(tmp, tmp, tmp2);
7667 dead_tmp(tmp2);
9ee6e8bb
PB		 7668 }
7669 }
5e3f878a 7670 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7671 break;
7672 case 2: /* SIMD add/subtract. */
7673 op = (insn >> 20) & 7;
7674 shift = (insn >> 4) & 7;
7675 if ((op & 3) == 3 || (shift & 3) == 3)
7676 goto illegal_op;
6ddbc6e4
PB		 7677 tmp = load_reg(s, rn);
7678 tmp2 = load_reg(s, rm);
7679 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7680 dead_tmp(tmp2);
7681 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7682 break;
7683 case 3: /* Other data processing. */
7684 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7685 if (op < 4) {
7686 /* Saturating add/subtract. */
d9ba4830
PB		 7687 tmp = load_reg(s, rn);
7688 tmp2 = load_reg(s, rm);
9ee6e8bb 7689 if (op & 2)
d9ba4830 7690 gen_helper_double_saturate(tmp, tmp);
9ee6e8bb 7691 if (op & 1)
d9ba4830 7692 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7693 else
d9ba4830
PB		 7694 gen_helper_add_saturate(tmp, tmp, tmp2);
7695 dead_tmp(tmp2);
9ee6e8bb 7696 } else {
d9ba4830 7697 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7698 switch (op) {
7699 case 0x0a: /* rbit */
d9ba4830 7700 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7701 break;
7702 case 0x08: /* rev */
66896cb8 7703 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7704 break;
7705 case 0x09: /* rev16 */
d9ba4830 7706 gen_rev16(tmp);
9ee6e8bb
PB		 7707 break;
7708 case 0x0b: /* revsh */
d9ba4830 7709 gen_revsh(tmp);
9ee6e8bb
PB		 7710 break;
7711 case 0x10: /* sel */
d9ba4830 7712 tmp2 = load_reg(s, rm);
6ddbc6e4
PB		 7713 tmp3 = new_tmp();
7714 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7715 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6ddbc6e4 7716 dead_tmp(tmp3);
d9ba4830 7717 dead_tmp(tmp2);
9ee6e8bb
PB		 7718 break;
7719 case 0x18: /* clz */
d9ba4830 7720 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7721 break;
7722 default:
7723 goto illegal_op;
7724 }
7725 }
d9ba4830 7726 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7727 break;
7728 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7729 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7730 tmp = load_reg(s, rn);
7731 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7732 switch ((insn >> 20) & 7) {
7733 case 0: /* 32 x 32 -> 32 */
d9ba4830
PB		 7734 tcg_gen_mul_i32(tmp, tmp, tmp2);
7735 dead_tmp(tmp2);
9ee6e8bb 7736 if (rs != 15) {
d9ba4830 7737 tmp2 = load_reg(s, rs);
9ee6e8bb 7738 if (op)
d9ba4830 7739 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7740 else
d9ba4830
PB		 7741 tcg_gen_add_i32(tmp, tmp, tmp2);
7742 dead_tmp(tmp2);
9ee6e8bb 7743 }
9ee6e8bb
PB		 7744 break;
7745 case 1: /* 16 x 16 -> 32 */
d9ba4830
PB		 7746 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7747 dead_tmp(tmp2);
9ee6e8bb 7748 if (rs != 15) {
d9ba4830
PB		 7749 tmp2 = load_reg(s, rs);
7750 gen_helper_add_setq(tmp, tmp, tmp2);
7751 dead_tmp(tmp2);
9ee6e8bb 7752 }
9ee6e8bb
PB		 7753 break;
7754 case 2: /* Dual multiply add. */
7755 case 4: /* Dual multiply subtract. */
7756 if (op)
d9ba4830
PB		 7757 gen_swap_half(tmp2);
7758 gen_smul_dual(tmp, tmp2);
9ee6e8bb
PB		 7759 /* This addition cannot overflow. */
7760 if (insn & (1 << 22)) {
d9ba4830 7761 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7762 } else {
d9ba4830 7763 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 7764 }
d9ba4830 7765 dead_tmp(tmp2);
9ee6e8bb
PB		 7766 if (rs != 15)
7767 {
d9ba4830
PB		 7768 tmp2 = load_reg(s, rs);
7769 gen_helper_add_setq(tmp, tmp, tmp2);
7770 dead_tmp(tmp2);
9ee6e8bb 7771 }
9ee6e8bb
PB		 7772 break;
7773 case 3: /* 32 * 16 -> 32msb */
7774 if (op)
d9ba4830 7775 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7776 else
d9ba4830 7777 gen_sxth(tmp2);
a7812ae4
PB		 7778 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7779 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 7780 tmp = new_tmp();
a7812ae4 7781 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 7782 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7783 if (rs != 15)
7784 {
d9ba4830
PB		 7785 tmp2 = load_reg(s, rs);
7786 gen_helper_add_setq(tmp, tmp, tmp2);
7787 dead_tmp(tmp2);
9ee6e8bb 7788 }
9ee6e8bb
PB		 7789 break;
7790 case 5: case 6: /* 32 * 32 -> 32msb */
d9ba4830
PB		 7791 gen_imull(tmp, tmp2);
7792 if (insn & (1 << 5)) {
7793 gen_roundqd(tmp, tmp2);
7794 dead_tmp(tmp2);
7795 } else {
7796 dead_tmp(tmp);
7797 tmp = tmp2;
7798 }
9ee6e8bb 7799 if (rs != 15) {
d9ba4830 7800 tmp2 = load_reg(s, rs);
9ee6e8bb 7801 if (insn & (1 << 21)) {
d9ba4830 7802 tcg_gen_add_i32(tmp, tmp, tmp2);
99c475ab 7803 } else {
d9ba4830 7804 tcg_gen_sub_i32(tmp, tmp2, tmp);
99c475ab 7805 }
d9ba4830 7806 dead_tmp(tmp2);
2c0262af 7807 }
9ee6e8bb
PB		 7808 break;
7809 case 7: /* Unsigned sum of absolute differences. */
d9ba4830
PB		 7810 gen_helper_usad8(tmp, tmp, tmp2);
7811 dead_tmp(tmp2);
9ee6e8bb 7812 if (rs != 15) {
d9ba4830
PB		 7813 tmp2 = load_reg(s, rs);
7814 tcg_gen_add_i32(tmp, tmp, tmp2);
7815 dead_tmp(tmp2);
5fd46862 7816 }
9ee6e8bb 7817 break;
2c0262af 7818 }
d9ba4830 7819 store_reg(s, rd, tmp);
2c0262af 7820 break;
9ee6e8bb
PB		 7821 case 6: case 7: /* 64-bit multiply, Divide. */
7822 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7823 tmp = load_reg(s, rn);
7824 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7825 if ((op & 0x50) == 0x10) {
7826 /* sdiv, udiv */
7827 if (!arm_feature(env, ARM_FEATURE_DIV))
7828 goto illegal_op;
7829 if (op & 0x20)
5e3f878a 7830 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7831 else
5e3f878a
PB		 7832 gen_helper_sdiv(tmp, tmp, tmp2);
7833 dead_tmp(tmp2);
7834 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7835 } else if ((op & 0xe) == 0xc) {
7836 /* Dual multiply accumulate long. */
7837 if (op & 1)
5e3f878a
PB		 7838 gen_swap_half(tmp2);
7839 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7840 if (op & 0x10) {
5e3f878a 7841 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7842 } else {
5e3f878a 7843 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7844 }
5e3f878a 7845 dead_tmp(tmp2);
a7812ae4
PB		 7846 /* BUGFIX */
7847 tmp64 = tcg_temp_new_i64();
7848 tcg_gen_ext_i32_i64(tmp64, tmp);
7849 dead_tmp(tmp);
7850 gen_addq(s, tmp64, rs, rd);
7851 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7852 tcg_temp_free_i64(tmp64);
2c0262af 7853 } else {
9ee6e8bb
PB		 7854 if (op & 0x20) {
7855 /* Unsigned 64-bit multiply */
a7812ae4 7856 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7857 } else {
9ee6e8bb
PB		 7858 if (op & 8) {
7859 /* smlalxy */
5e3f878a
PB		 7860 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7861 dead_tmp(tmp2);
a7812ae4
PB		 7862 tmp64 = tcg_temp_new_i64();
7863 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7864 dead_tmp(tmp);
9ee6e8bb
PB		 7865 } else {
7866 /* Signed 64-bit multiply */
a7812ae4 7867 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7868 }
b5ff1b31 7869 }
9ee6e8bb
PB		 7870 if (op & 4) {
7871 /* umaal */
a7812ae4
PB		 7872 gen_addq_lo(s, tmp64, rs);
7873 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 7874 } else if (op & 0x40) {
7875 /* 64-bit accumulate. */
a7812ae4 7876 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 7877 }
a7812ae4 7878 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7879 tcg_temp_free_i64(tmp64);
5fd46862 7880 }
2c0262af 7881 break;
9ee6e8bb
PB		 7882 }
7883 break;
7884 case 6: case 7: case 14: case 15:
7885 /* Coprocessor. */
7886 if (((insn >> 24) & 3) == 3) {
7887 /* Translate into the equivalent ARM encoding. */
7888 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7889 if (disas_neon_data_insn(env, s, insn))
7890 goto illegal_op;
7891 } else {
7892 if (insn & (1 << 28))
7893 goto illegal_op;
7894 if (disas_coproc_insn (env, s, insn))
7895 goto illegal_op;
7896 }
7897 break;
7898 case 8: case 9: case 10: case 11:
7899 if (insn & (1 << 15)) {
7900 /* Branches, misc control. */
7901 if (insn & 0x5000) {
7902 /* Unconditional branch. */
7903 /* signextend(hw1[10:0]) -> offset[:12]. */
7904 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7905 /* hw1[10:0] -> offset[11:1]. */
7906 offset |= (insn & 0x7ff) << 1;
7907 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7908 offset[24:22] already have the same value because of the
7909 sign extension above. */
7910 offset ^= ((~insn) & (1 << 13)) << 10;
7911 offset ^= ((~insn) & (1 << 11)) << 11;
7912
9ee6e8bb
PB		 7913 if (insn & (1 << 14)) {
7914 /* Branch and link. */
3174f8e9 7915 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 7916 }
3b46e624 7917
b0109805 7918 offset += s->pc;
9ee6e8bb
PB		 7919 if (insn & (1 << 12)) {
7920 /* b/bl */
b0109805 7921 gen_jmp(s, offset);
9ee6e8bb
PB		 7922 } else {
7923 /* blx */
b0109805
PB		 7924 offset &= ~(uint32_t)2;
7925 gen_bx_im(s, offset);
2c0262af 7926 }
9ee6e8bb
PB		 7927 } else if (((insn >> 23) & 7) == 7) {
7928 /* Misc control */
7929 if (insn & (1 << 13))
7930 goto illegal_op;
7931
7932 if (insn & (1 << 26)) {
7933 /* Secure monitor call (v6Z) */
7934 goto illegal_op; /* not implemented. */
2c0262af 7935 } else {
9ee6e8bb
PB		 7936 op = (insn >> 20) & 7;
7937 switch (op) {
7938 case 0: /* msr cpsr. */
7939 if (IS_M(env)) {
8984bd2e
PB		 7940 tmp = load_reg(s, rn);
7941 addr = tcg_const_i32(insn & 0xff);
7942 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6
JR		 7943 tcg_temp_free_i32(addr);
7944 dead_tmp(tmp);
9ee6e8bb
PB		 7945 gen_lookup_tb(s);
7946 break;
7947 }
7948 /* fall through */
7949 case 1: /* msr spsr. */
7950 if (IS_M(env))
7951 goto illegal_op;
2fbac54b
FN		 7952 tmp = load_reg(s, rn);
7953 if (gen_set_psr(s,
9ee6e8bb 7954 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 7955 op == 1, tmp))
9ee6e8bb
PB		 7956 goto illegal_op;
7957 break;
7958 case 2: /* cps, nop-hint. */
7959 if (((insn >> 8) & 7) == 0) {
7960 gen_nop_hint(s, insn & 0xff);
7961 }
7962 /* Implemented as NOP in user mode. */
7963 if (IS_USER(s))
7964 break;
7965 offset = 0;
7966 imm = 0;
7967 if (insn & (1 << 10)) {
7968 if (insn & (1 << 7))
7969 offset |= CPSR_A;
7970 if (insn & (1 << 6))
7971 offset |= CPSR_I;
7972 if (insn & (1 << 5))
7973 offset |= CPSR_F;
7974 if (insn & (1 << 9))
7975 imm = CPSR_A | CPSR_I | CPSR_F;
7976 }
7977 if (insn & (1 << 8)) {
7978 offset |= 0x1f;
7979 imm |= (insn & 0x1f);
7980 }
7981 if (offset) {
2fbac54b 7982 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 7983 }
7984 break;
7985 case 3: /* Special control operations. */
426f5abc 7986 ARCH(7);
9ee6e8bb
PB		 7987 op = (insn >> 4) & 0xf;
7988 switch (op) {
7989 case 2: /* clrex */
426f5abc 7990 gen_clrex(s);
9ee6e8bb
PB		 7991 break;
7992 case 4: /* dsb */
7993 case 5: /* dmb */
7994 case 6: /* isb */
7995 /* These execute as NOPs. */
9ee6e8bb
PB		 7996 break;
7997 default:
7998 goto illegal_op;
7999 }
8000 break;
8001 case 4: /* bxj */
8002 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8003 tmp = load_reg(s, rn);
8004 gen_bx(s, tmp);
9ee6e8bb
PB		 8005 break;
8006 case 5: /* Exception return. */
b8b45b68
RV		 8007 if (IS_USER(s)) {
8008 goto illegal_op;
8009 }
8010 if (rn != 14 || rd != 15) {
8011 goto illegal_op;
8012 }
8013 tmp = load_reg(s, rn);
8014 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8015 gen_exception_return(s, tmp);
8016 break;
9ee6e8bb 8017 case 6: /* mrs cpsr. */
8984bd2e 8018 tmp = new_tmp();
9ee6e8bb 8019 if (IS_M(env)) {
8984bd2e
PB		 8020 addr = tcg_const_i32(insn & 0xff);
8021 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8022 tcg_temp_free_i32(addr);
9ee6e8bb 8023 } else {
8984bd2e 8024 gen_helper_cpsr_read(tmp);
9ee6e8bb 8025 }
8984bd2e 8026 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8027 break;
8028 case 7: /* mrs spsr. */
8029 /* Not accessible in user mode. */
8030 if (IS_USER(s) || IS_M(env))
8031 goto illegal_op;
d9ba4830
PB		 8032 tmp = load_cpu_field(spsr);
8033 store_reg(s, rd, tmp);
9ee6e8bb 8034 break;
2c0262af
FB		 8035 }
8036 }
9ee6e8bb
PB		 8037 } else {
8038 /* Conditional branch. */
8039 op = (insn >> 22) & 0xf;
8040 /* Generate a conditional jump to next instruction. */
8041 s->condlabel = gen_new_label();
d9ba4830 8042 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8043 s->condjmp = 1;
8044
8045 /* offset[11:1] = insn[10:0] */
8046 offset = (insn & 0x7ff) << 1;
8047 /* offset[17:12] = insn[21:16]. */
8048 offset |= (insn & 0x003f0000) >> 4;
8049 /* offset[31:20] = insn[26]. */
8050 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8051 /* offset[18] = insn[13]. */
8052 offset |= (insn & (1 << 13)) << 5;
8053 /* offset[19] = insn[11]. */
8054 offset |= (insn & (1 << 11)) << 8;
8055
8056 /* jump to the offset */
b0109805 8057 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8058 }
8059 } else {
8060 /* Data processing immediate. */
8061 if (insn & (1 << 25)) {
8062 if (insn & (1 << 24)) {
8063 if (insn & (1 << 20))
8064 goto illegal_op;
8065 /* Bitfield/Saturate. */
8066 op = (insn >> 21) & 7;
8067 imm = insn & 0x1f;
8068 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4
PB		 8069 if (rn == 15) {
8070 tmp = new_tmp();
8071 tcg_gen_movi_i32(tmp, 0);
8072 } else {
8073 tmp = load_reg(s, rn);
8074 }
9ee6e8bb
PB		 8075 switch (op) {
8076 case 2: /* Signed bitfield extract. */
8077 imm++;
8078 if (shift + imm > 32)
8079 goto illegal_op;
8080 if (imm < 32)
6ddbc6e4 8081 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8082 break;
8083 case 6: /* Unsigned bitfield extract. */
8084 imm++;
8085 if (shift + imm > 32)
8086 goto illegal_op;
8087 if (imm < 32)
6ddbc6e4 8088 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8089 break;
8090 case 3: /* Bitfield insert/clear. */
8091 if (imm < shift)
8092 goto illegal_op;
8093 imm = imm + 1 - shift;
8094 if (imm != 32) {
6ddbc6e4 8095 tmp2 = load_reg(s, rd);
8f8e3aa4 8096 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
6ddbc6e4 8097 dead_tmp(tmp2);
9ee6e8bb
PB		 8098 }
8099 break;
8100 case 7:
8101 goto illegal_op;
8102 default: /* Saturate. */
9ee6e8bb
PB		 8103 if (shift) {
8104 if (op & 1)
6ddbc6e4 8105 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8106 else
6ddbc6e4 8107 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8108 }
6ddbc6e4 8109 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8110 if (op & 4) {
8111 /* Unsigned. */
9ee6e8bb 8112 if ((op & 1) && shift == 0)
6ddbc6e4 8113 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8114 else
6ddbc6e4 8115 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8116 } else {
9ee6e8bb 8117 /* Signed. */
9ee6e8bb 8118 if ((op & 1) && shift == 0)
6ddbc6e4 8119 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8120 else
6ddbc6e4 8121 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8122 }
b75263d6 8123 tcg_temp_free_i32(tmp2);
9ee6e8bb 8124 break;
2c0262af 8125 }
6ddbc6e4 8126 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8127 } else {
8128 imm = ((insn & 0x04000000) >> 15)
8129 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8130 if (insn & (1 << 22)) {
8131 /* 16-bit immediate. */
8132 imm |= (insn >> 4) & 0xf000;
8133 if (insn & (1 << 23)) {
8134 /* movt */
5e3f878a 8135 tmp = load_reg(s, rd);
86831435 8136 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8137 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8138 } else {
9ee6e8bb 8139 /* movw */
5e3f878a
PB		 8140 tmp = new_tmp();
8141 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8142 }
8143 } else {
9ee6e8bb
PB		 8144 /* Add/sub 12-bit immediate. */
8145 if (rn == 15) {
b0109805 8146 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8147 if (insn & (1 << 23))
b0109805 8148 offset -= imm;
9ee6e8bb 8149 else
b0109805 8150 offset += imm;
5e3f878a
PB		 8151 tmp = new_tmp();
8152 tcg_gen_movi_i32(tmp, offset);
2c0262af 8153 } else {
5e3f878a 8154 tmp = load_reg(s, rn);
9ee6e8bb 8155 if (insn & (1 << 23))
5e3f878a 8156 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8157 else
5e3f878a 8158 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8159 }
9ee6e8bb 8160 }
5e3f878a 8161 store_reg(s, rd, tmp);
191abaa2 8162 }
9ee6e8bb
PB		 8163 } else {
8164 int shifter_out = 0;
8165 /* modified 12-bit immediate. */
8166 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8167 imm = (insn & 0xff);
8168 switch (shift) {
8169 case 0: /* XY */
8170 /* Nothing to do. */
8171 break;
8172 case 1: /* 00XY00XY */
8173 imm |= imm << 16;
8174 break;
8175 case 2: /* XY00XY00 */
8176 imm |= imm << 16;
8177 imm <<= 8;
8178 break;
8179 case 3: /* XYXYXYXY */
8180 imm |= imm << 16;
8181 imm |= imm << 8;
8182 break;
8183 default: /* Rotated constant. */
8184 shift = (shift << 1) | (imm >> 7);
8185 imm |= 0x80;
8186 imm = imm << (32 - shift);
8187 shifter_out = 1;
8188 break;
b5ff1b31 8189 }
3174f8e9
FN		 8190 tmp2 = new_tmp();
8191 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8192 rn = (insn >> 16) & 0xf;
3174f8e9
FN		 8193 if (rn == 15) {
8194 tmp = new_tmp();
8195 tcg_gen_movi_i32(tmp, 0);
8196 } else {
8197 tmp = load_reg(s, rn);
8198 }
9ee6e8bb
PB		 8199 op = (insn >> 21) & 0xf;
8200 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8201 shifter_out, tmp, tmp2))
9ee6e8bb 8202 goto illegal_op;
3174f8e9 8203 dead_tmp(tmp2);
9ee6e8bb
PB		 8204 rd = (insn >> 8) & 0xf;
8205 if (rd != 15) {
3174f8e9
FN		 8206 store_reg(s, rd, tmp);
8207 } else {
8208 dead_tmp(tmp);
2c0262af 8209 }
2c0262af 8210 }
9ee6e8bb
PB		 8211 }
8212 break;
8213 case 12: /* Load/store single data item. */
8214 {
8215 int postinc = 0;
8216 int writeback = 0;
b0109805 8217 int user;
9ee6e8bb
PB		 8218 if ((insn & 0x01100000) == 0x01000000) {
8219 if (disas_neon_ls_insn(env, s, insn))
c1713132 8220 goto illegal_op;
9ee6e8bb
PB		 8221 break;
8222 }
b0109805 8223 user = IS_USER(s);
9ee6e8bb 8224 if (rn == 15) {
b0109805 8225 addr = new_tmp();
9ee6e8bb
PB		 8226 /* PC relative. */
8227 /* s->pc has already been incremented by 4. */
8228 imm = s->pc & 0xfffffffc;
8229 if (insn & (1 << 23))
8230 imm += insn & 0xfff;
8231 else
8232 imm -= insn & 0xfff;
b0109805 8233 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8234 } else {
b0109805 8235 addr = load_reg(s, rn);
9ee6e8bb
PB		 8236 if (insn & (1 << 23)) {
8237 /* Positive offset. */
8238 imm = insn & 0xfff;
b0109805 8239 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8240 } else {
8241 op = (insn >> 8) & 7;
8242 imm = insn & 0xff;
8243 switch (op) {
8244 case 0: case 8: /* Shifted Register. */
8245 shift = (insn >> 4) & 0xf;
8246 if (shift > 3)
18c9b560 8247 goto illegal_op;
b26eefb6 8248 tmp = load_reg(s, rm);
9ee6e8bb 8249 if (shift)
b26eefb6 8250 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8251 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8252 dead_tmp(tmp);
9ee6e8bb
PB		 8253 break;
8254 case 4: /* Negative offset. */
b0109805 8255 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb
PB		 8256 break;
8257 case 6: /* User privilege. */
b0109805
PB		 8258 tcg_gen_addi_i32(addr, addr, imm);
8259 user = 1;
9ee6e8bb
PB		 8260 break;
8261 case 1: /* Post-decrement. */
8262 imm = -imm;
8263 /* Fall through. */
8264 case 3: /* Post-increment. */
9ee6e8bb
PB		 8265 postinc = 1;
8266 writeback = 1;
8267 break;
8268 case 5: /* Pre-decrement. */
8269 imm = -imm;
8270 /* Fall through. */
8271 case 7: /* Pre-increment. */
b0109805 8272 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8273 writeback = 1;
8274 break;
8275 default:
b7bcbe95 8276 goto illegal_op;
9ee6e8bb
PB		 8277 }
8278 }
8279 }
8280 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8281 if (insn & (1 << 20)) {
8282 /* Load. */
8283 if (rs == 15 && op != 2) {
8284 if (op & 2)
b5ff1b31 8285 goto illegal_op;
9ee6e8bb
PB		 8286 /* Memory hint. Implemented as NOP. */
8287 } else {
8288 switch (op) {
b0109805
PB		 8289 case 0: tmp = gen_ld8u(addr, user); break;
8290 case 4: tmp = gen_ld8s(addr, user); break;
8291 case 1: tmp = gen_ld16u(addr, user); break;
8292 case 5: tmp = gen_ld16s(addr, user); break;
8293 case 2: tmp = gen_ld32(addr, user); break;
9ee6e8bb
PB		 8294 default: goto illegal_op;
8295 }
8296 if (rs == 15) {
b0109805 8297 gen_bx(s, tmp);
9ee6e8bb 8298 } else {
b0109805 8299 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8300 }
8301 }
8302 } else {
8303 /* Store. */
8304 if (rs == 15)
b7bcbe95 8305 goto illegal_op;
b0109805 8306 tmp = load_reg(s, rs);
9ee6e8bb 8307 switch (op) {
b0109805
PB		 8308 case 0: gen_st8(tmp, addr, user); break;
8309 case 1: gen_st16(tmp, addr, user); break;
8310 case 2: gen_st32(tmp, addr, user); break;
9ee6e8bb 8311 default: goto illegal_op;
b7bcbe95 8312 }
2c0262af 8313 }
9ee6e8bb 8314 if (postinc)
b0109805
PB		 8315 tcg_gen_addi_i32(addr, addr, imm);
8316 if (writeback) {
8317 store_reg(s, rn, addr);
8318 } else {
8319 dead_tmp(addr);
8320 }
9ee6e8bb
PB		 8321 }
8322 break;
8323 default:
8324 goto illegal_op;
2c0262af 8325 }
9ee6e8bb
PB		 8326 return 0;
8327illegal_op:
8328 return 1;
2c0262af
FB		 8329}
8330
9ee6e8bb 8331static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8332{
8333 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8334 int32_t offset;
8335 int i;
b26eefb6 8336 TCGv tmp;
d9ba4830 8337 TCGv tmp2;
b0109805 8338 TCGv addr;
99c475ab 8339
9ee6e8bb
PB		 8340 if (s->condexec_mask) {
8341 cond = s->condexec_cond;
bedd2912
JB		 8342 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8343 s->condlabel = gen_new_label();
8344 gen_test_cc(cond ^ 1, s->condlabel);
8345 s->condjmp = 1;
8346 }
9ee6e8bb
PB		 8347 }
8348
b5ff1b31 8349 insn = lduw_code(s->pc);
99c475ab 8350 s->pc += 2;
b5ff1b31 8351
99c475ab
FB		 8352 switch (insn >> 12) {
8353 case 0: case 1:
396e467c 8354
99c475ab
FB		 8355 rd = insn & 7;
8356 op = (insn >> 11) & 3;
8357 if (op == 3) {
8358 /* add/subtract */
8359 rn = (insn >> 3) & 7;
396e467c 8360 tmp = load_reg(s, rn);
99c475ab
FB		 8361 if (insn & (1 << 10)) {
8362 /* immediate */
396e467c
FN		 8363 tmp2 = new_tmp();
8364 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8365 } else {
8366 /* reg */
8367 rm = (insn >> 6) & 7;
396e467c 8368 tmp2 = load_reg(s, rm);
99c475ab 8369 }
9ee6e8bb
PB		 8370 if (insn & (1 << 9)) {
8371 if (s->condexec_mask)
396e467c 8372 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8373 else
396e467c 8374 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8375 } else {
8376 if (s->condexec_mask)
396e467c 8377 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8378 else
396e467c 8379 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8380 }
396e467c
FN		 8381 dead_tmp(tmp2);
8382 store_reg(s, rd, tmp);
99c475ab
FB		 8383 } else {
8384 /* shift immediate */
8385 rm = (insn >> 3) & 7;
8386 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8387 tmp = load_reg(s, rm);
8388 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8389 if (!s->condexec_mask)
8390 gen_logic_CC(tmp);
8391 store_reg(s, rd, tmp);
99c475ab
FB		 8392 }
8393 break;
8394 case 2: case 3:
8395 /* arithmetic large immediate */
8396 op = (insn >> 11) & 3;
8397 rd = (insn >> 8) & 0x7;
396e467c
FN		 8398 if (op == 0) { /* mov */
8399 tmp = new_tmp();
8400 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8401 if (!s->condexec_mask)
396e467c
FN		 8402 gen_logic_CC(tmp);
8403 store_reg(s, rd, tmp);
8404 } else {
8405 tmp = load_reg(s, rd);
8406 tmp2 = new_tmp();
8407 tcg_gen_movi_i32(tmp2, insn & 0xff);
8408 switch (op) {
8409 case 1: /* cmp */
8410 gen_helper_sub_cc(tmp, tmp, tmp2);
8411 dead_tmp(tmp);
8412 dead_tmp(tmp2);
8413 break;
8414 case 2: /* add */
8415 if (s->condexec_mask)
8416 tcg_gen_add_i32(tmp, tmp, tmp2);
8417 else
8418 gen_helper_add_cc(tmp, tmp, tmp2);
8419 dead_tmp(tmp2);
8420 store_reg(s, rd, tmp);
8421 break;
8422 case 3: /* sub */
8423 if (s->condexec_mask)
8424 tcg_gen_sub_i32(tmp, tmp, tmp2);
8425 else
8426 gen_helper_sub_cc(tmp, tmp, tmp2);
8427 dead_tmp(tmp2);
8428 store_reg(s, rd, tmp);
8429 break;
8430 }
99c475ab 8431 }
99c475ab
FB		 8432 break;
8433 case 4:
8434 if (insn & (1 << 11)) {
8435 rd = (insn >> 8) & 7;
5899f386
FB		 8436 /* load pc-relative. Bit 1 of PC is ignored. */
8437 val = s->pc + 2 + ((insn & 0xff) * 4);
8438 val &= ~(uint32_t)2;
b0109805
PB		 8439 addr = new_tmp();
8440 tcg_gen_movi_i32(addr, val);
8441 tmp = gen_ld32(addr, IS_USER(s));
8442 dead_tmp(addr);
8443 store_reg(s, rd, tmp);
99c475ab
FB		 8444 break;
8445 }
8446 if (insn & (1 << 10)) {
8447 /* data processing extended or blx */
8448 rd = (insn & 7) | ((insn >> 4) & 8);
8449 rm = (insn >> 3) & 0xf;
8450 op = (insn >> 8) & 3;
8451 switch (op) {
8452 case 0: /* add */
396e467c
FN		 8453 tmp = load_reg(s, rd);
8454 tmp2 = load_reg(s, rm);
8455 tcg_gen_add_i32(tmp, tmp, tmp2);
8456 dead_tmp(tmp2);
8457 store_reg(s, rd, tmp);
99c475ab
FB		 8458 break;
8459 case 1: /* cmp */
396e467c
FN		 8460 tmp = load_reg(s, rd);
8461 tmp2 = load_reg(s, rm);
8462 gen_helper_sub_cc(tmp, tmp, tmp2);
8463 dead_tmp(tmp2);
8464 dead_tmp(tmp);
99c475ab
FB		 8465 break;
8466 case 2: /* mov/cpy */
396e467c
FN		 8467 tmp = load_reg(s, rm);
8468 store_reg(s, rd, tmp);
99c475ab
FB		 8469 break;
8470 case 3:/* branch [and link] exchange thumb register */
b0109805 8471 tmp = load_reg(s, rm);
99c475ab
FB		 8472 if (insn & (1 << 7)) {
8473 val = (uint32_t)s->pc | 1;
b0109805
PB		 8474 tmp2 = new_tmp();
8475 tcg_gen_movi_i32(tmp2, val);
8476 store_reg(s, 14, tmp2);
99c475ab 8477 }
d9ba4830 8478 gen_bx(s, tmp);
99c475ab
FB		 8479 break;
8480 }
8481 break;
8482 }
8483
8484 /* data processing register */
8485 rd = insn & 7;
8486 rm = (insn >> 3) & 7;
8487 op = (insn >> 6) & 0xf;
8488 if (op == 2 || op == 3 || op == 4 || op == 7) {
8489 /* the shift/rotate ops want the operands backwards */
8490 val = rm;
8491 rm = rd;
8492 rd = val;
8493 val = 1;
8494 } else {
8495 val = 0;
8496 }
8497
396e467c
FN		 8498 if (op == 9) { /* neg */
8499 tmp = new_tmp();
8500 tcg_gen_movi_i32(tmp, 0);
8501 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8502 tmp = load_reg(s, rd);
8503 } else {
8504 TCGV_UNUSED(tmp);
8505 }
99c475ab 8506
396e467c 8507 tmp2 = load_reg(s, rm);
5899f386 8508 switch (op) {
99c475ab 8509 case 0x0: /* and */
396e467c 8510 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8511 if (!s->condexec_mask)
396e467c 8512 gen_logic_CC(tmp);
99c475ab
FB		 8513 break;
8514 case 0x1: /* eor */
396e467c 8515 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8516 if (!s->condexec_mask)
396e467c 8517 gen_logic_CC(tmp);
99c475ab
FB		 8518 break;
8519 case 0x2: /* lsl */
9ee6e8bb 8520 if (s->condexec_mask) {
396e467c 8521 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8522 } else {
396e467c
FN		 8523 gen_helper_shl_cc(tmp2, tmp2, tmp);
8524 gen_logic_CC(tmp2);
9ee6e8bb 8525 }
99c475ab
FB		 8526 break;
8527 case 0x3: /* lsr */
9ee6e8bb 8528 if (s->condexec_mask) {
396e467c 8529 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8530 } else {
396e467c
FN		 8531 gen_helper_shr_cc(tmp2, tmp2, tmp);
8532 gen_logic_CC(tmp2);
9ee6e8bb 8533 }
99c475ab
FB		 8534 break;
8535 case 0x4: /* asr */
9ee6e8bb 8536 if (s->condexec_mask) {
396e467c 8537 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8538 } else {
396e467c
FN		 8539 gen_helper_sar_cc(tmp2, tmp2, tmp);
8540 gen_logic_CC(tmp2);
9ee6e8bb 8541 }
99c475ab
FB		 8542 break;
8543 case 0x5: /* adc */
9ee6e8bb 8544 if (s->condexec_mask)
396e467c 8545 gen_adc(tmp, tmp2);
9ee6e8bb 8546 else
396e467c 8547 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8548 break;
8549 case 0x6: /* sbc */
9ee6e8bb 8550 if (s->condexec_mask)
396e467c 8551 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8552 else
396e467c 8553 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8554 break;
8555 case 0x7: /* ror */
9ee6e8bb 8556 if (s->condexec_mask) {
f669df27
AJ		 8557 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8558 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8559 } else {
396e467c
FN		 8560 gen_helper_ror_cc(tmp2, tmp2, tmp);
8561 gen_logic_CC(tmp2);
9ee6e8bb 8562 }
99c475ab
FB		 8563 break;
8564 case 0x8: /* tst */
396e467c
FN		 8565 tcg_gen_and_i32(tmp, tmp, tmp2);
8566 gen_logic_CC(tmp);
99c475ab 8567 rd = 16;
5899f386 8568 break;
99c475ab 8569 case 0x9: /* neg */
9ee6e8bb 8570 if (s->condexec_mask)
396e467c 8571 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8572 else
396e467c 8573 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8574 break;
8575 case 0xa: /* cmp */
396e467c 8576 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8577 rd = 16;
8578 break;
8579 case 0xb: /* cmn */
396e467c 8580 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8581 rd = 16;
8582 break;
8583 case 0xc: /* orr */
396e467c 8584 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8585 if (!s->condexec_mask)
396e467c 8586 gen_logic_CC(tmp);
99c475ab
FB		 8587 break;
8588 case 0xd: /* mul */
7b2919a0 8589 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8590 if (!s->condexec_mask)
396e467c 8591 gen_logic_CC(tmp);
99c475ab
FB		 8592 break;
8593 case 0xe: /* bic */
f669df27 8594 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8595 if (!s->condexec_mask)
396e467c 8596 gen_logic_CC(tmp);
99c475ab
FB		 8597 break;
8598 case 0xf: /* mvn */
396e467c 8599 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8600 if (!s->condexec_mask)
396e467c 8601 gen_logic_CC(tmp2);
99c475ab 8602 val = 1;
5899f386 8603 rm = rd;
99c475ab
FB		 8604 break;
8605 }
8606 if (rd != 16) {
396e467c
FN		 8607 if (val) {
8608 store_reg(s, rm, tmp2);
8609 if (op != 0xf)
8610 dead_tmp(tmp);
8611 } else {
8612 store_reg(s, rd, tmp);
8613 dead_tmp(tmp2);
8614 }
8615 } else {
8616 dead_tmp(tmp);
8617 dead_tmp(tmp2);
99c475ab
FB		 8618 }
8619 break;
8620
8621 case 5:
8622 /* load/store register offset. */
8623 rd = insn & 7;
8624 rn = (insn >> 3) & 7;
8625 rm = (insn >> 6) & 7;
8626 op = (insn >> 9) & 7;
b0109805 8627 addr = load_reg(s, rn);
b26eefb6 8628 tmp = load_reg(s, rm);
b0109805 8629 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8630 dead_tmp(tmp);
99c475ab
FB		 8631
8632 if (op < 3) /* store */
b0109805 8633 tmp = load_reg(s, rd);
99c475ab
FB		 8634
8635 switch (op) {
8636 case 0: /* str */
b0109805 8637 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8638 break;
8639 case 1: /* strh */
b0109805 8640 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8641 break;
8642 case 2: /* strb */
b0109805 8643 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8644 break;
8645 case 3: /* ldrsb */
b0109805 8646 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8647 break;
8648 case 4: /* ldr */
b0109805 8649 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8650 break;
8651 case 5: /* ldrh */
b0109805 8652 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8653 break;
8654 case 6: /* ldrb */
b0109805 8655 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8656 break;
8657 case 7: /* ldrsh */
b0109805 8658 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8659 break;
8660 }
8661 if (op >= 3) /* load */
b0109805
PB		 8662 store_reg(s, rd, tmp);
8663 dead_tmp(addr);
99c475ab
FB		 8664 break;
8665
8666 case 6:
8667 /* load/store word immediate offset */
8668 rd = insn & 7;
8669 rn = (insn >> 3) & 7;
b0109805 8670 addr = load_reg(s, rn);
99c475ab 8671 val = (insn >> 4) & 0x7c;
b0109805 8672 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8673
8674 if (insn & (1 << 11)) {
8675 /* load */
b0109805
PB		 8676 tmp = gen_ld32(addr, IS_USER(s));
8677 store_reg(s, rd, tmp);
99c475ab
FB		 8678 } else {
8679 /* store */
b0109805
PB		 8680 tmp = load_reg(s, rd);
8681 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8682 }
b0109805 8683 dead_tmp(addr);
99c475ab
FB		 8684 break;
8685
8686 case 7:
8687 /* load/store byte immediate offset */
8688 rd = insn & 7;
8689 rn = (insn >> 3) & 7;
b0109805 8690 addr = load_reg(s, rn);
99c475ab 8691 val = (insn >> 6) & 0x1f;
b0109805 8692 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8693
8694 if (insn & (1 << 11)) {
8695 /* load */
b0109805
PB		 8696 tmp = gen_ld8u(addr, IS_USER(s));
8697 store_reg(s, rd, tmp);
99c475ab
FB		 8698 } else {
8699 /* store */
b0109805
PB		 8700 tmp = load_reg(s, rd);
8701 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8702 }
b0109805 8703 dead_tmp(addr);
99c475ab
FB		 8704 break;
8705
8706 case 8:
8707 /* load/store halfword immediate offset */
8708 rd = insn & 7;
8709 rn = (insn >> 3) & 7;
b0109805 8710 addr = load_reg(s, rn);
99c475ab 8711 val = (insn >> 5) & 0x3e;
b0109805 8712 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8713
8714 if (insn & (1 << 11)) {
8715 /* load */
b0109805
PB		 8716 tmp = gen_ld16u(addr, IS_USER(s));
8717 store_reg(s, rd, tmp);
99c475ab
FB		 8718 } else {
8719 /* store */
b0109805
PB		 8720 tmp = load_reg(s, rd);
8721 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8722 }
b0109805 8723 dead_tmp(addr);
99c475ab
FB		 8724 break;
8725
8726 case 9:
8727 /* load/store from stack */
8728 rd = (insn >> 8) & 7;
b0109805 8729 addr = load_reg(s, 13);
99c475ab 8730 val = (insn & 0xff) * 4;
b0109805 8731 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8732
8733 if (insn & (1 << 11)) {
8734 /* load */
b0109805
PB		 8735 tmp = gen_ld32(addr, IS_USER(s));
8736 store_reg(s, rd, tmp);
99c475ab
FB		 8737 } else {
8738 /* store */
b0109805
PB		 8739 tmp = load_reg(s, rd);
8740 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8741 }
b0109805 8742 dead_tmp(addr);
99c475ab
FB		 8743 break;
8744
8745 case 10:
8746 /* add to high reg */
8747 rd = (insn >> 8) & 7;
5899f386
FB		 8748 if (insn & (1 << 11)) {
8749 /* SP */
5e3f878a 8750 tmp = load_reg(s, 13);
5899f386
FB		 8751 } else {
8752 /* PC. bit 1 is ignored. */
5e3f878a
PB		 8753 tmp = new_tmp();
8754 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8755 }
99c475ab 8756 val = (insn & 0xff) * 4;
5e3f878a
PB		 8757 tcg_gen_addi_i32(tmp, tmp, val);
8758 store_reg(s, rd, tmp);
99c475ab
FB		 8759 break;
8760
8761 case 11:
8762 /* misc */
8763 op = (insn >> 8) & 0xf;
8764 switch (op) {
8765 case 0:
8766 /* adjust stack pointer */
b26eefb6 8767 tmp = load_reg(s, 13);
99c475ab
FB		 8768 val = (insn & 0x7f) * 4;
8769 if (insn & (1 << 7))
6a0d8a1d 8770 val = -(int32_t)val;
b26eefb6
PB		 8771 tcg_gen_addi_i32(tmp, tmp, val);
8772 store_reg(s, 13, tmp);
99c475ab
FB		 8773 break;
8774
9ee6e8bb
PB		 8775 case 2: /* sign/zero extend. */
8776 ARCH(6);
8777 rd = insn & 7;
8778 rm = (insn >> 3) & 7;
b0109805 8779 tmp = load_reg(s, rm);
9ee6e8bb 8780 switch ((insn >> 6) & 3) {
b0109805
PB		 8781 case 0: gen_sxth(tmp); break;
8782 case 1: gen_sxtb(tmp); break;
8783 case 2: gen_uxth(tmp); break;
8784 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8785 }
b0109805 8786 store_reg(s, rd, tmp);
9ee6e8bb 8787 break;
99c475ab
FB		 8788 case 4: case 5: case 0xc: case 0xd:
8789 /* push/pop */
b0109805 8790 addr = load_reg(s, 13);
5899f386
FB		 8791 if (insn & (1 << 8))
8792 offset = 4;
99c475ab 8793 else
5899f386
FB		 8794 offset = 0;
8795 for (i = 0; i < 8; i++) {
8796 if (insn & (1 << i))
8797 offset += 4;
8798 }
8799 if ((insn & (1 << 11)) == 0) {
b0109805 8800 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8801 }
99c475ab
FB		 8802 for (i = 0; i < 8; i++) {
8803 if (insn & (1 << i)) {
8804 if (insn & (1 << 11)) {
8805 /* pop */
b0109805
PB		 8806 tmp = gen_ld32(addr, IS_USER(s));
8807 store_reg(s, i, tmp);
99c475ab
FB		 8808 } else {
8809 /* push */
b0109805
PB		 8810 tmp = load_reg(s, i);
8811 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8812 }
5899f386 8813 /* advance to the next address. */
b0109805 8814 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8815 }
8816 }
a50f5b91 8817 TCGV_UNUSED(tmp);
99c475ab
FB		 8818 if (insn & (1 << 8)) {
8819 if (insn & (1 << 11)) {
8820 /* pop pc */
b0109805 8821 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8822 /* don't set the pc until the rest of the instruction
8823 has completed */
8824 } else {
8825 /* push lr */
b0109805
PB		 8826 tmp = load_reg(s, 14);
8827 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8828 }
b0109805 8829 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8830 }
5899f386 8831 if ((insn & (1 << 11)) == 0) {
b0109805 8832 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8833 }
99c475ab 8834 /* write back the new stack pointer */
b0109805 8835 store_reg(s, 13, addr);
99c475ab
FB		 8836 /* set the new PC value */
8837 if ((insn & 0x0900) == 0x0900)
b0109805 8838 gen_bx(s, tmp);
99c475ab
FB		 8839 break;
8840
9ee6e8bb
PB		 8841 case 1: case 3: case 9: case 11: /* czb */
8842 rm = insn & 7;
d9ba4830 8843 tmp = load_reg(s, rm);
9ee6e8bb
PB		 8844 s->condlabel = gen_new_label();
8845 s->condjmp = 1;
8846 if (insn & (1 << 11))
cb63669a 8847 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 8848 else
cb63669a 8849 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
d9ba4830 8850 dead_tmp(tmp);
9ee6e8bb
PB		 8851 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8852 val = (uint32_t)s->pc + 2;
8853 val += offset;
8854 gen_jmp(s, val);
8855 break;
8856
8857 case 15: /* IT, nop-hint. */
8858 if ((insn & 0xf) == 0) {
8859 gen_nop_hint(s, (insn >> 4) & 0xf);
8860 break;
8861 }
8862 /* If Then. */
8863 s->condexec_cond = (insn >> 4) & 0xe;
8864 s->condexec_mask = insn & 0x1f;
8865 /* No actual code generated for this insn, just setup state. */
8866 break;
8867
06c949e6 8868 case 0xe: /* bkpt */
9ee6e8bb 8869 gen_set_condexec(s);
5e3f878a 8870 gen_set_pc_im(s->pc - 2);
d9ba4830 8871 gen_exception(EXCP_BKPT);
06c949e6
PB		 8872 s->is_jmp = DISAS_JUMP;
8873 break;
8874
9ee6e8bb
PB		 8875 case 0xa: /* rev */
8876 ARCH(6);
8877 rn = (insn >> 3) & 0x7;
8878 rd = insn & 0x7;
b0109805 8879 tmp = load_reg(s, rn);
9ee6e8bb 8880 switch ((insn >> 6) & 3) {
66896cb8 8881 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 8882 case 1: gen_rev16(tmp); break;
8883 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 8884 default: goto illegal_op;
8885 }
b0109805 8886 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8887 break;
8888
8889 case 6: /* cps */
8890 ARCH(6);
8891 if (IS_USER(s))
8892 break;
8893 if (IS_M(env)) {
8984bd2e 8894 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 8895 /* PRIMASK */
8984bd2e
PB		 8896 if (insn & 1) {
8897 addr = tcg_const_i32(16);
8898 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8899 tcg_temp_free_i32(addr);
8984bd2e 8900 }
9ee6e8bb 8901 /* FAULTMASK */
8984bd2e
PB		 8902 if (insn & 2) {
8903 addr = tcg_const_i32(17);
8904 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8905 tcg_temp_free_i32(addr);
8984bd2e 8906 }
b75263d6 8907 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8908 gen_lookup_tb(s);
8909 } else {
8910 if (insn & (1 << 4))
8911 shift = CPSR_A | CPSR_I | CPSR_F;
8912 else
8913 shift = 0;
fa26df03 8914 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 8915 }
8916 break;
8917
99c475ab
FB		 8918 default:
8919 goto undef;
8920 }
8921 break;
8922
8923 case 12:
8924 /* load/store multiple */
8925 rn = (insn >> 8) & 0x7;
b0109805 8926 addr = load_reg(s, rn);
99c475ab
FB		 8927 for (i = 0; i < 8; i++) {
8928 if (insn & (1 << i)) {
99c475ab
FB		 8929 if (insn & (1 << 11)) {
8930 /* load */
b0109805
PB		 8931 tmp = gen_ld32(addr, IS_USER(s));
8932 store_reg(s, i, tmp);
99c475ab
FB		 8933 } else {
8934 /* store */
b0109805
PB		 8935 tmp = load_reg(s, i);
8936 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8937 }
5899f386 8938 /* advance to the next address */
b0109805 8939 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8940 }
8941 }
5899f386 8942 /* Base register writeback. */
b0109805
PB		 8943 if ((insn & (1 << rn)) == 0) {
8944 store_reg(s, rn, addr);
8945 } else {
8946 dead_tmp(addr);
8947 }
99c475ab
FB		 8948 break;
8949
8950 case 13:
8951 /* conditional branch or swi */
8952 cond = (insn >> 8) & 0xf;
8953 if (cond == 0xe)
8954 goto undef;
8955
8956 if (cond == 0xf) {
8957 /* swi */
9ee6e8bb 8958 gen_set_condexec(s);
422ebf69 8959 gen_set_pc_im(s->pc);
9ee6e8bb 8960 s->is_jmp = DISAS_SWI;
99c475ab
FB		 8961 break;
8962 }
8963 /* generate a conditional jump to next instruction */
e50e6a20 8964 s->condlabel = gen_new_label();
d9ba4830 8965 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 8966 s->condjmp = 1;
99c475ab
FB		 8967
8968 /* jump to the offset */
5899f386 8969 val = (uint32_t)s->pc + 2;
99c475ab 8970 offset = ((int32_t)insn << 24) >> 24;
5899f386 8971 val += offset << 1;
8aaca4c0 8972 gen_jmp(s, val);
99c475ab
FB		 8973 break;
8974
8975 case 14:
358bf29e 8976 if (insn & (1 << 11)) {
9ee6e8bb
PB		 8977 if (disas_thumb2_insn(env, s, insn))
8978 goto undef32;
358bf29e
PB		 8979 break;
8980 }
9ee6e8bb 8981 /* unconditional branch */
99c475ab
FB		 8982 val = (uint32_t)s->pc;
8983 offset = ((int32_t)insn << 21) >> 21;
8984 val += (offset << 1) + 2;
8aaca4c0 8985 gen_jmp(s, val);
99c475ab
FB		 8986 break;
8987
8988 case 15:
9ee6e8bb 8989 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 8990 goto undef32;
9ee6e8bb 8991 break;
99c475ab
FB		 8992 }
8993 return;
9ee6e8bb
PB		 8994undef32:
8995 gen_set_condexec(s);
5e3f878a 8996 gen_set_pc_im(s->pc - 4);
d9ba4830 8997 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 8998 s->is_jmp = DISAS_JUMP;
8999 return;
9000illegal_op:
99c475ab 9001undef:
9ee6e8bb 9002 gen_set_condexec(s);
5e3f878a 9003 gen_set_pc_im(s->pc - 2);
d9ba4830 9004 gen_exception(EXCP_UDEF);
99c475ab
FB		 9005 s->is_jmp = DISAS_JUMP;
9006}
9007
2c0262af
FB		 9008/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9009 basic block 'tb'. If search_pc is TRUE, also generate PC
9010 information for each intermediate instruction. */
2cfc5f17
TS		 9011static inline void gen_intermediate_code_internal(CPUState *env,
9012 TranslationBlock *tb,
9013 int search_pc)
2c0262af
FB		 9014{
9015 DisasContext dc1, *dc = &dc1;
a1d1bb31 9016 CPUBreakpoint *bp;
2c0262af
FB		 9017 uint16_t *gen_opc_end;
9018 int j, lj;
0fa85d43 9019 target_ulong pc_start;
b5ff1b31 9020 uint32_t next_page_start;
2e70f6ef
PB		 9021 int num_insns;
9022 int max_insns;
3b46e624 9023
2c0262af 9024 /* generate intermediate code */
b26eefb6 9025 num_temps = 0;
b26eefb6 9026
0fa85d43 9027 pc_start = tb->pc;
3b46e624 9028
2c0262af
FB		 9029 dc->tb = tb;
9030
2c0262af 9031 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9032
9033 dc->is_jmp = DISAS_NEXT;
9034 dc->pc = pc_start;
8aaca4c0 9035 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9036 dc->condjmp = 0;
5899f386 9037 dc->thumb = env->thumb;
9ee6e8bb
PB		 9038 dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
9039 dc->condexec_cond = env->condexec_bits >> 4;
b5ff1b31 9040#if !defined(CONFIG_USER_ONLY)
9ee6e8bb
PB		 9041 if (IS_M(env)) {
9042 dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
9043 } else {
9044 dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
9045 }
b5ff1b31 9046#endif
a7812ae4
PB		 9047 cpu_F0s = tcg_temp_new_i32();
9048 cpu_F1s = tcg_temp_new_i32();
9049 cpu_F0d = tcg_temp_new_i64();
9050 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9051 cpu_V0 = cpu_F0d;
9052 cpu_V1 = cpu_F1d;
e677137d 9053 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9054 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9055 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9056 lj = -1;
2e70f6ef
PB		 9057 num_insns = 0;
9058 max_insns = tb->cflags & CF_COUNT_MASK;
9059 if (max_insns == 0)
9060 max_insns = CF_COUNT_MASK;
9061
9062 gen_icount_start();
9ee6e8bb
PB		 9063 /* Reset the conditional execution bits immediately. This avoids
9064 complications trying to do it at the end of the block. */
9065 if (env->condexec_bits)
8f01245e
PB		 9066 {
9067 TCGv tmp = new_tmp();
9068 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9069 store_cpu_field(tmp, condexec_bits);
8f01245e 9070 }
2c0262af 9071 do {
fbb4a2e3
PB		 9072#ifdef CONFIG_USER_ONLY
9073 /* Intercept jump to the magic kernel page. */
9074 if (dc->pc >= 0xffff0000) {
9075 /* We always get here via a jump, so know we are not in a
9076 conditional execution block. */
9077 gen_exception(EXCP_KERNEL_TRAP);
9078 dc->is_jmp = DISAS_UPDATE;
9079 break;
9080 }
9081#else
9ee6e8bb
PB		 9082 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9083 /* We always get here via a jump, so know we are not in a
9084 conditional execution block. */
d9ba4830 9085 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9086 dc->is_jmp = DISAS_UPDATE;
9087 break;
9ee6e8bb
PB		 9088 }
9089#endif
9090
72cf2d4f
BS		 9091 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9092 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9093 if (bp->pc == dc->pc) {
9ee6e8bb 9094 gen_set_condexec(dc);
5e3f878a 9095 gen_set_pc_im(dc->pc);
d9ba4830 9096 gen_exception(EXCP_DEBUG);
1fddef4b 9097 dc->is_jmp = DISAS_JUMP;
9ee6e8bb
PB		 9098 /* Advance PC so that clearing the breakpoint will
9099 invalidate this TB. */
9100 dc->pc += 2;
9101 goto done_generating;
1fddef4b
FB		 9102 break;
9103 }
9104 }
9105 }
2c0262af
FB		 9106 if (search_pc) {
9107 j = gen_opc_ptr - gen_opc_buf;
9108 if (lj < j) {
9109 lj++;
9110 while (lj < j)
9111 gen_opc_instr_start[lj++] = 0;
9112 }
0fa85d43 9113 gen_opc_pc[lj] = dc->pc;
2c0262af 9114 gen_opc_instr_start[lj] = 1;
2e70f6ef 9115 gen_opc_icount[lj] = num_insns;
2c0262af 9116 }
e50e6a20 9117
2e70f6ef
PB		 9118 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9119 gen_io_start();
9120
9ee6e8bb
PB		 9121 if (env->thumb) {
9122 disas_thumb_insn(env, dc);
9123 if (dc->condexec_mask) {
9124 dc->condexec_cond = (dc->condexec_cond & 0xe)
9125 | ((dc->condexec_mask >> 4) & 1);
9126 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9127 if (dc->condexec_mask == 0) {
9128 dc->condexec_cond = 0;
9129 }
9130 }
9131 } else {
9132 disas_arm_insn(env, dc);
9133 }
b26eefb6
PB		 9134 if (num_temps) {
9135 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9136 num_temps = 0;
9137 }
e50e6a20
FB		 9138
9139 if (dc->condjmp && !dc->is_jmp) {
9140 gen_set_label(dc->condlabel);
9141 dc->condjmp = 0;
9142 }
aaf2d97d 9143 /* Translation stops when a conditional branch is encountered.
e50e6a20 9144 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9145 * Also stop translation when a page boundary is reached. This
bf20dc07 9146 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9147 num_insns ++;
1fddef4b
FB		 9148 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9149 !env->singlestep_enabled &&
1b530a6d 9150 !singlestep &&
2e70f6ef
PB		 9151 dc->pc < next_page_start &&
9152 num_insns < max_insns);
9153
9154 if (tb->cflags & CF_LAST_IO) {
9155 if (dc->condjmp) {
9156 /* FIXME: This can theoretically happen with self-modifying
9157 code. */
9158 cpu_abort(env, "IO on conditional branch instruction");
9159 }
9160 gen_io_end();
9161 }
9ee6e8bb 9162
b5ff1b31 9163 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9164 instruction was a conditional branch or trap, and the PC has
9165 already been written. */
551bd27f 9166 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9167 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9168 if (dc->condjmp) {
9ee6e8bb
PB		 9169 gen_set_condexec(dc);
9170 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9171 gen_exception(EXCP_SWI);
9ee6e8bb 9172 } else {
d9ba4830 9173 gen_exception(EXCP_DEBUG);
9ee6e8bb 9174 }
e50e6a20
FB		 9175 gen_set_label(dc->condlabel);
9176 }
9177 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9178 gen_set_pc_im(dc->pc);
e50e6a20 9179 dc->condjmp = 0;
8aaca4c0 9180 }
9ee6e8bb
PB		 9181 gen_set_condexec(dc);
9182 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9183 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9184 } else {
9185 /* FIXME: Single stepping a WFI insn will not halt
9186 the CPU. */
d9ba4830 9187 gen_exception(EXCP_DEBUG);
9ee6e8bb 9188 }
8aaca4c0 9189 } else {
9ee6e8bb
PB		 9190 /* While branches must always occur at the end of an IT block,
9191 there are a few other things that can cause us to terminate
9192 the TB in the middel of an IT block:
9193 - Exception generating instructions (bkpt, swi, undefined).
9194 - Page boundaries.
9195 - Hardware watchpoints.
9196 Hardware breakpoints have already been handled and skip this code.
9197 */
9198 gen_set_condexec(dc);
8aaca4c0 9199 switch(dc->is_jmp) {
8aaca4c0 9200 case DISAS_NEXT:
6e256c93 9201 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9202 break;
9203 default:
9204 case DISAS_JUMP:
9205 case DISAS_UPDATE:
9206 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9207 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9208 break;
9209 case DISAS_TB_JUMP:
9210 /* nothing more to generate */
9211 break;
9ee6e8bb 9212 case DISAS_WFI:
d9ba4830 9213 gen_helper_wfi();
9ee6e8bb
PB		 9214 break;
9215 case DISAS_SWI:
d9ba4830 9216 gen_exception(EXCP_SWI);
9ee6e8bb 9217 break;
8aaca4c0 9218 }
e50e6a20
FB		 9219 if (dc->condjmp) {
9220 gen_set_label(dc->condlabel);
9ee6e8bb 9221 gen_set_condexec(dc);
6e256c93 9222 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9223 dc->condjmp = 0;
9224 }
2c0262af 9225 }
2e70f6ef 9226
9ee6e8bb 9227done_generating:
2e70f6ef 9228 gen_icount_end(tb, num_insns);
2c0262af
FB		 9229 *gen_opc_ptr = INDEX_op_end;
9230
9231#ifdef DEBUG_DISAS
8fec2b8c 9232 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9233 qemu_log("----------------\n");
9234 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9235 log_target_disas(pc_start, dc->pc - pc_start, env->thumb);
9236 qemu_log("\n");
2c0262af
FB		 9237 }
9238#endif
b5ff1b31
FB		 9239 if (search_pc) {
9240 j = gen_opc_ptr - gen_opc_buf;
9241 lj++;
9242 while (lj <= j)
9243 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9244 } else {
2c0262af 9245 tb->size = dc->pc - pc_start;
2e70f6ef 9246 tb->icount = num_insns;
b5ff1b31 9247 }
2c0262af
FB		 9248}
9249
2cfc5f17 9250void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9251{
2cfc5f17 9252 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9253}
9254
2cfc5f17 9255void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9256{
2cfc5f17 9257 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9258}
9259
b5ff1b31
FB		 9260static const char *cpu_mode_names[16] = {
9261 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9262 "???", "???", "???", "und", "???", "???", "???", "sys"
9263};
9ee6e8bb 9264
9a78eead 9265void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9266 int flags)
2c0262af
FB		 9267{
9268 int i;
06e80fc9 9269#if 0
bc380d17 9270 union {
b7bcbe95
FB		 9271 uint32_t i;
9272 float s;
9273 } s0, s1;
9274 CPU_DoubleU d;
a94a6abf
PB		 9275 /* ??? This assumes float64 and double have the same layout.
9276 Oh well, it's only debug dumps. */
9277 union {
9278 float64 f64;
9279 double d;
9280 } d0;
06e80fc9 9281#endif
b5ff1b31 9282 uint32_t psr;
2c0262af
FB		 9283
9284 for(i=0;i<16;i++) {
7fe48483 9285 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9286 if ((i % 4) == 3)
7fe48483 9287 cpu_fprintf(f, "\n");
2c0262af 9288 else
7fe48483 9289 cpu_fprintf(f, " ");
2c0262af 9290 }
b5ff1b31 9291 psr = cpsr_read(env);
687fa640
TS		 9292 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9293 psr,
b5ff1b31
FB		 9294 psr & (1 << 31) ? 'N' : '-',
9295 psr & (1 << 30) ? 'Z' : '-',
9296 psr & (1 << 29) ? 'C' : '-',
9297 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9298 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9299 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9300
5e3f878a 9301#if 0
b7bcbe95 9302 for (i = 0; i < 16; i++) {
8e96005d
FB		 9303 d.d = env->vfp.regs[i];
9304 s0.i = d.l.lower;
9305 s1.i = d.l.upper;
a94a6abf
PB		 9306 d0.f64 = d.d;
9307 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9308 i * 2, (int)s0.i, s0.s,
a94a6abf 9309 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9310 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9311 d0.d);
b7bcbe95 9312 }
40f137e1 9313 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9314#endif
2c0262af 9315}
a6b025d3 9316
d2856f1a
AJ		 9317void gen_pc_load(CPUState *env, TranslationBlock *tb,
9318 unsigned long searched_pc, int pc_pos, void *puc)
9319{
9320 env->regs[15] = gen_opc_pc[pc_pos];
9321}
Qemu copy for testing