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target-arm: Fix decoding of preload and memory hint space
[qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
9ee6e8bb
PB		 37#define ENABLE_ARCH_5J 0
38#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 42
86753403 43#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 44
2c0262af
FB		 45/* internal defines */
46typedef struct DisasContext {
0fa85d43 47 target_ulong pc;
2c0262af 48 int is_jmp;
e50e6a20
FB		 49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
9ee6e8bb
PB		 53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
2c0262af 56 struct TranslationBlock *tb;
8aaca4c0 57 int singlestep_enabled;
5899f386 58 int thumb;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
5df8bac1 62 int vfp_enabled;
69d1fc22
PM		 63 int vec_len;
64 int vec_stride;
2c0262af
FB		 65} DisasContext;
66
e12ce78d
PM		 67static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
b5ff1b31
FB		 69#if defined(CONFIG_USER_ONLY)
70#define IS_USER(s) 1
71#else
72#define IS_USER(s) (s->user)
73#endif
74
9ee6e8bb
PB		 75/* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77#define DISAS_WFI 4
78#define DISAS_SWI 5
2c0262af 79
a7812ae4 80static TCGv_ptr cpu_env;
ad69471c 81/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 82static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 83static TCGv_i32 cpu_R[16];
426f5abc
PB		 84static TCGv_i32 cpu_exclusive_addr;
85static TCGv_i32 cpu_exclusive_val;
86static TCGv_i32 cpu_exclusive_high;
87#ifdef CONFIG_USER_ONLY
88static TCGv_i32 cpu_exclusive_test;
89static TCGv_i32 cpu_exclusive_info;
90#endif
ad69471c 91
b26eefb6 92/* FIXME: These should be removed. */
a7812ae4
PB		 93static TCGv cpu_F0s, cpu_F1s;
94static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 95
2e70f6ef
PB		 96#include "gen-icount.h"
97
155c3eac
FN		 98static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
b26eefb6
PB		 102/* initialize TCG globals. */
103void arm_translate_init(void)
104{
155c3eac
FN		 105 int i;
106
a7812ae4
PB		 107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
155c3eac
FN		 109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
426f5abc
PB		 114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120#ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125#endif
155c3eac 126
a7812ae4
PB		 127#define GEN_HELPER 2
128#include "helpers.h"
b26eefb6
PB		 129}
130
b26eefb6 131static int num_temps;
b26eefb6
PB		 132
133/* Allocate a temporary variable. */
a7812ae4 134static TCGv_i32 new_tmp(void)
b26eefb6 135{
12edd4f2
FN		 136 num_temps++;
137 return tcg_temp_new_i32();
b26eefb6
PB		 138}
139
140/* Release a temporary variable. */
141static void dead_tmp(TCGv tmp)
142{
12edd4f2 143 tcg_temp_free(tmp);
b26eefb6 144 num_temps--;
b26eefb6
PB		 145}
146
d9ba4830
PB		 147static inline TCGv load_cpu_offset(int offset)
148{
149 TCGv tmp = new_tmp();
150 tcg_gen_ld_i32(tmp, cpu_env, offset);
151 return tmp;
152}
153
154#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
155
156static inline void store_cpu_offset(TCGv var, int offset)
157{
158 tcg_gen_st_i32(var, cpu_env, offset);
159 dead_tmp(var);
160}
161
162#define store_cpu_field(var, name) \
163 store_cpu_offset(var, offsetof(CPUState, name))
164
b26eefb6
PB		 165/* Set a variable to the value of a CPU register. */
166static void load_reg_var(DisasContext *s, TCGv var, int reg)
167{
168 if (reg == 15) {
169 uint32_t addr;
170 /* normaly, since we updated PC, we need only to add one insn */
171 if (s->thumb)
172 addr = (long)s->pc + 2;
173 else
174 addr = (long)s->pc + 4;
175 tcg_gen_movi_i32(var, addr);
176 } else {
155c3eac 177 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 178 }
179}
180
181/* Create a new temporary and set it to the value of a CPU register. */
182static inline TCGv load_reg(DisasContext *s, int reg)
183{
184 TCGv tmp = new_tmp();
185 load_reg_var(s, tmp, reg);
186 return tmp;
187}
188
189/* Set a CPU register. The source must be a temporary and will be
190 marked as dead. */
191static void store_reg(DisasContext *s, int reg, TCGv var)
192{
193 if (reg == 15) {
194 tcg_gen_andi_i32(var, var, ~1);
195 s->is_jmp = DISAS_JUMP;
196 }
155c3eac 197 tcg_gen_mov_i32(cpu_R[reg], var);
b26eefb6
PB		 198 dead_tmp(var);
199}
200
b26eefb6 201/* Value extensions. */
86831435
PB		 202#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
203#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 204#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
205#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
206
1497c961
PB		 207#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
208#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 209
b26eefb6 210
b75263d6
JR		 211static inline void gen_set_cpsr(TCGv var, uint32_t mask)
212{
213 TCGv tmp_mask = tcg_const_i32(mask);
214 gen_helper_cpsr_write(var, tmp_mask);
215 tcg_temp_free_i32(tmp_mask);
216}
d9ba4830
PB		 217/* Set NZCV flags from the high 4 bits of var. */
218#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
219
220static void gen_exception(int excp)
221{
222 TCGv tmp = new_tmp();
223 tcg_gen_movi_i32(tmp, excp);
224 gen_helper_exception(tmp);
225 dead_tmp(tmp);
226}
227
3670669c
PB		 228static void gen_smul_dual(TCGv a, TCGv b)
229{
230 TCGv tmp1 = new_tmp();
231 TCGv tmp2 = new_tmp();
22478e79
AZ		 232 tcg_gen_ext16s_i32(tmp1, a);
233 tcg_gen_ext16s_i32(tmp2, b);
3670669c
PB		 234 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
235 dead_tmp(tmp2);
236 tcg_gen_sari_i32(a, a, 16);
237 tcg_gen_sari_i32(b, b, 16);
238 tcg_gen_mul_i32(b, b, a);
239 tcg_gen_mov_i32(a, tmp1);
240 dead_tmp(tmp1);
241}
242
243/* Byteswap each halfword. */
244static void gen_rev16(TCGv var)
245{
246 TCGv tmp = new_tmp();
247 tcg_gen_shri_i32(tmp, var, 8);
248 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
249 tcg_gen_shli_i32(var, var, 8);
250 tcg_gen_andi_i32(var, var, 0xff00ff00);
251 tcg_gen_or_i32(var, var, tmp);
252 dead_tmp(tmp);
253}
254
255/* Byteswap low halfword and sign extend. */
256static void gen_revsh(TCGv var)
257{
1a855029
AJ		 258 tcg_gen_ext16u_i32(var, var);
259 tcg_gen_bswap16_i32(var, var);
260 tcg_gen_ext16s_i32(var, var);
3670669c
PB		 261}
262
263/* Unsigned bitfield extract. */
264static void gen_ubfx(TCGv var, int shift, uint32_t mask)
265{
266 if (shift)
267 tcg_gen_shri_i32(var, var, shift);
268 tcg_gen_andi_i32(var, var, mask);
269}
270
271/* Signed bitfield extract. */
272static void gen_sbfx(TCGv var, int shift, int width)
273{
274 uint32_t signbit;
275
276 if (shift)
277 tcg_gen_sari_i32(var, var, shift);
278 if (shift + width < 32) {
279 signbit = 1u << (width - 1);
280 tcg_gen_andi_i32(var, var, (1u << width) - 1);
281 tcg_gen_xori_i32(var, var, signbit);
282 tcg_gen_subi_i32(var, var, signbit);
283 }
284}
285
286/* Bitfield insertion. Insert val into base. Clobbers base and val. */
287static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
288{
3670669c 289 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 290 tcg_gen_shli_i32(val, val, shift);
291 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 292 tcg_gen_or_i32(dest, base, val);
293}
294
838fa72d
AJ		 295/* Return (b << 32) + a. Mark inputs as dead */
296static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
3670669c 297{
838fa72d
AJ		 298 TCGv_i64 tmp64 = tcg_temp_new_i64();
299
300 tcg_gen_extu_i32_i64(tmp64, b);
301 dead_tmp(b);
302 tcg_gen_shli_i64(tmp64, tmp64, 32);
303 tcg_gen_add_i64(a, tmp64, a);
304
305 tcg_temp_free_i64(tmp64);
306 return a;
307}
308
309/* Return (b << 32) - a. Mark inputs as dead. */
310static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
311{
312 TCGv_i64 tmp64 = tcg_temp_new_i64();
313
314 tcg_gen_extu_i32_i64(tmp64, b);
315 dead_tmp(b);
316 tcg_gen_shli_i64(tmp64, tmp64, 32);
317 tcg_gen_sub_i64(a, tmp64, a);
318
319 tcg_temp_free_i64(tmp64);
320 return a;
3670669c
PB		 321}
322
8f01245e
PB		 323/* FIXME: Most targets have native widening multiplication.
324 It would be good to use that instead of a full wide multiply. */
5e3f878a 325/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 326static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 327{
a7812ae4
PB		 328 TCGv_i64 tmp1 = tcg_temp_new_i64();
329 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 330
331 tcg_gen_extu_i32_i64(tmp1, a);
332 dead_tmp(a);
333 tcg_gen_extu_i32_i64(tmp2, b);
334 dead_tmp(b);
335 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 336 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 337 return tmp1;
338}
339
a7812ae4 340static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 341{
a7812ae4
PB		 342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 350 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 351 return tmp1;
352}
353
8f01245e
PB		 354/* Swap low and high halfwords. */
355static void gen_swap_half(TCGv var)
356{
357 TCGv tmp = new_tmp();
358 tcg_gen_shri_i32(tmp, var, 16);
359 tcg_gen_shli_i32(var, var, 16);
360 tcg_gen_or_i32(var, var, tmp);
3670669c 361 dead_tmp(tmp);
8f01245e
PB		 362}
363
b26eefb6
PB		 364/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
365 tmp = (t0 ^ t1) & 0x8000;
366 t0 &= ~0x8000;
367 t1 &= ~0x8000;
368 t0 = (t0 + t1) ^ tmp;
369 */
370
371static void gen_add16(TCGv t0, TCGv t1)
372{
373 TCGv tmp = new_tmp();
374 tcg_gen_xor_i32(tmp, t0, t1);
375 tcg_gen_andi_i32(tmp, tmp, 0x8000);
376 tcg_gen_andi_i32(t0, t0, ~0x8000);
377 tcg_gen_andi_i32(t1, t1, ~0x8000);
378 tcg_gen_add_i32(t0, t0, t1);
379 tcg_gen_xor_i32(t0, t0, tmp);
380 dead_tmp(tmp);
381 dead_tmp(t1);
382}
383
9a119ff6
PB		 384#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
385
b26eefb6
PB		 386/* Set CF to the top bit of var. */
387static void gen_set_CF_bit31(TCGv var)
388{
389 TCGv tmp = new_tmp();
390 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 391 gen_set_CF(tmp);
b26eefb6
PB		 392 dead_tmp(tmp);
393}
394
395/* Set N and Z flags from var. */
396static inline void gen_logic_CC(TCGv var)
397{
6fbe23d5
PB		 398 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
399 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 400}
401
402/* T0 += T1 + CF. */
396e467c 403static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 404{
d9ba4830 405 TCGv tmp;
396e467c 406 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 407 tmp = load_cpu_field(CF);
396e467c 408 tcg_gen_add_i32(t0, t0, tmp);
b26eefb6
PB		 409 dead_tmp(tmp);
410}
411
e9bb4aa9
JR		 412/* dest = T0 + T1 + CF. */
413static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
414{
415 TCGv tmp;
416 tcg_gen_add_i32(dest, t0, t1);
417 tmp = load_cpu_field(CF);
418 tcg_gen_add_i32(dest, dest, tmp);
419 dead_tmp(tmp);
420}
421
3670669c
PB		 422/* dest = T0 - T1 + CF - 1. */
423static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
424{
d9ba4830 425 TCGv tmp;
3670669c 426 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 427 tmp = load_cpu_field(CF);
3670669c
PB		 428 tcg_gen_add_i32(dest, dest, tmp);
429 tcg_gen_subi_i32(dest, dest, 1);
430 dead_tmp(tmp);
431}
432
ad69471c
PB		 433/* FIXME: Implement this natively. */
434#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
435
9a119ff6 436static void shifter_out_im(TCGv var, int shift)
b26eefb6 437{
9a119ff6
PB		 438 TCGv tmp = new_tmp();
439 if (shift == 0) {
440 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 441 } else {
9a119ff6 442 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 443 if (shift != 31)
9a119ff6
PB		 444 tcg_gen_andi_i32(tmp, tmp, 1);
445 }
446 gen_set_CF(tmp);
447 dead_tmp(tmp);
448}
b26eefb6 449
9a119ff6
PB		 450/* Shift by immediate. Includes special handling for shift == 0. */
451static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
452{
453 switch (shiftop) {
454 case 0: /* LSL */
455 if (shift != 0) {
456 if (flags)
457 shifter_out_im(var, 32 - shift);
458 tcg_gen_shli_i32(var, var, shift);
459 }
460 break;
461 case 1: /* LSR */
462 if (shift == 0) {
463 if (flags) {
464 tcg_gen_shri_i32(var, var, 31);
465 gen_set_CF(var);
466 }
467 tcg_gen_movi_i32(var, 0);
468 } else {
469 if (flags)
470 shifter_out_im(var, shift - 1);
471 tcg_gen_shri_i32(var, var, shift);
472 }
473 break;
474 case 2: /* ASR */
475 if (shift == 0)
476 shift = 32;
477 if (flags)
478 shifter_out_im(var, shift - 1);
479 if (shift == 32)
480 shift = 31;
481 tcg_gen_sari_i32(var, var, shift);
482 break;
483 case 3: /* ROR/RRX */
484 if (shift != 0) {
485 if (flags)
486 shifter_out_im(var, shift - 1);
f669df27 487 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 488 } else {
d9ba4830 489 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 490 if (flags)
491 shifter_out_im(var, 0);
492 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 493 tcg_gen_shli_i32(tmp, tmp, 31);
494 tcg_gen_or_i32(var, var, tmp);
495 dead_tmp(tmp);
b26eefb6
PB		 496 }
497 }
498};
499
8984bd2e
PB		 500static inline void gen_arm_shift_reg(TCGv var, int shiftop,
501 TCGv shift, int flags)
502{
503 if (flags) {
504 switch (shiftop) {
505 case 0: gen_helper_shl_cc(var, var, shift); break;
506 case 1: gen_helper_shr_cc(var, var, shift); break;
507 case 2: gen_helper_sar_cc(var, var, shift); break;
508 case 3: gen_helper_ror_cc(var, var, shift); break;
509 }
510 } else {
511 switch (shiftop) {
512 case 0: gen_helper_shl(var, var, shift); break;
513 case 1: gen_helper_shr(var, var, shift); break;
514 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 515 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
516 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 517 }
518 }
519 dead_tmp(shift);
520}
521
6ddbc6e4
PB		 522#define PAS_OP(pfx) \
523 switch (op2) { \
524 case 0: gen_pas_helper(glue(pfx,add16)); break; \
525 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
526 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
527 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
528 case 4: gen_pas_helper(glue(pfx,add8)); break; \
529 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 }
d9ba4830 531static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 532{
a7812ae4 533 TCGv_ptr tmp;
6ddbc6e4
PB		 534
535 switch (op1) {
536#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 case 1:
a7812ae4 538 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(s)
b75263d6 541 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 542 break;
543 case 5:
a7812ae4 544 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 545 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
546 PAS_OP(u)
b75263d6 547 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 548 break;
549#undef gen_pas_helper
550#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 case 2:
552 PAS_OP(q);
553 break;
554 case 3:
555 PAS_OP(sh);
556 break;
557 case 6:
558 PAS_OP(uq);
559 break;
560 case 7:
561 PAS_OP(uh);
562 break;
563#undef gen_pas_helper
564 }
565}
9ee6e8bb
PB		 566#undef PAS_OP
567
6ddbc6e4
PB		 568/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
569#define PAS_OP(pfx) \
ed89a2f1 570 switch (op1) { \
6ddbc6e4
PB		 571 case 0: gen_pas_helper(glue(pfx,add8)); break; \
572 case 1: gen_pas_helper(glue(pfx,add16)); break; \
573 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
574 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
575 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
576 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 }
d9ba4830 578static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 579{
a7812ae4 580 TCGv_ptr tmp;
6ddbc6e4 581
ed89a2f1 582 switch (op2) {
6ddbc6e4
PB		 583#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 case 0:
a7812ae4 585 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(s)
b75263d6 588 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 589 break;
590 case 4:
a7812ae4 591 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 592 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
593 PAS_OP(u)
b75263d6 594 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 595 break;
596#undef gen_pas_helper
597#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 1:
599 PAS_OP(q);
600 break;
601 case 2:
602 PAS_OP(sh);
603 break;
604 case 5:
605 PAS_OP(uq);
606 break;
607 case 6:
608 PAS_OP(uh);
609 break;
610#undef gen_pas_helper
611 }
612}
9ee6e8bb
PB		 613#undef PAS_OP
614
d9ba4830
PB		 615static void gen_test_cc(int cc, int label)
616{
617 TCGv tmp;
618 TCGv tmp2;
d9ba4830
PB		 619 int inv;
620
d9ba4830
PB		 621 switch (cc) {
622 case 0: /* eq: Z */
6fbe23d5 623 tmp = load_cpu_field(ZF);
cb63669a 624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 625 break;
626 case 1: /* ne: !Z */
6fbe23d5 627 tmp = load_cpu_field(ZF);
cb63669a 628 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 629 break;
630 case 2: /* cs: C */
631 tmp = load_cpu_field(CF);
cb63669a 632 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 633 break;
634 case 3: /* cc: !C */
635 tmp = load_cpu_field(CF);
cb63669a 636 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 637 break;
638 case 4: /* mi: N */
6fbe23d5 639 tmp = load_cpu_field(NF);
cb63669a 640 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 641 break;
642 case 5: /* pl: !N */
6fbe23d5 643 tmp = load_cpu_field(NF);
cb63669a 644 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 645 break;
646 case 6: /* vs: V */
647 tmp = load_cpu_field(VF);
cb63669a 648 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 649 break;
650 case 7: /* vc: !V */
651 tmp = load_cpu_field(VF);
cb63669a 652 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 653 break;
654 case 8: /* hi: C && !Z */
655 inv = gen_new_label();
656 tmp = load_cpu_field(CF);
cb63669a 657 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830 658 dead_tmp(tmp);
6fbe23d5 659 tmp = load_cpu_field(ZF);
cb63669a 660 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 661 gen_set_label(inv);
662 break;
663 case 9: /* ls: !C || Z */
664 tmp = load_cpu_field(CF);
cb63669a 665 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830 666 dead_tmp(tmp);
6fbe23d5 667 tmp = load_cpu_field(ZF);
cb63669a 668 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 669 break;
670 case 10: /* ge: N == V -> N ^ V == 0 */
671 tmp = load_cpu_field(VF);
6fbe23d5 672 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 673 tcg_gen_xor_i32(tmp, tmp, tmp2);
674 dead_tmp(tmp2);
cb63669a 675 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 676 break;
677 case 11: /* lt: N != V -> N ^ V != 0 */
678 tmp = load_cpu_field(VF);
6fbe23d5 679 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 680 tcg_gen_xor_i32(tmp, tmp, tmp2);
681 dead_tmp(tmp2);
cb63669a 682 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 683 break;
684 case 12: /* gt: !Z && N == V */
685 inv = gen_new_label();
6fbe23d5 686 tmp = load_cpu_field(ZF);
cb63669a 687 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830
PB		 688 dead_tmp(tmp);
689 tmp = load_cpu_field(VF);
6fbe23d5 690 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 691 tcg_gen_xor_i32(tmp, tmp, tmp2);
692 dead_tmp(tmp2);
cb63669a 693 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 694 gen_set_label(inv);
695 break;
696 case 13: /* le: Z || N != V */
6fbe23d5 697 tmp = load_cpu_field(ZF);
cb63669a 698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 699 dead_tmp(tmp);
700 tmp = load_cpu_field(VF);
6fbe23d5 701 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 702 tcg_gen_xor_i32(tmp, tmp, tmp2);
703 dead_tmp(tmp2);
cb63669a 704 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 705 break;
706 default:
707 fprintf(stderr, "Bad condition code 0x%x\n", cc);
708 abort();
709 }
710 dead_tmp(tmp);
711}
2c0262af 712
b1d8e52e 713static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 714 1, /* and */
715 1, /* xor */
716 0, /* sub */
717 0, /* rsb */
718 0, /* add */
719 0, /* adc */
720 0, /* sbc */
721 0, /* rsc */
722 1, /* andl */
723 1, /* xorl */
724 0, /* cmp */
725 0, /* cmn */
726 1, /* orr */
727 1, /* mov */
728 1, /* bic */
729 1, /* mvn */
730};
3b46e624 731
d9ba4830
PB		 732/* Set PC and Thumb state from an immediate address. */
733static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 734{
b26eefb6 735 TCGv tmp;
99c475ab 736
b26eefb6 737 s->is_jmp = DISAS_UPDATE;
d9ba4830 738 if (s->thumb != (addr & 1)) {
155c3eac 739 tmp = new_tmp();
d9ba4830
PB		 740 tcg_gen_movi_i32(tmp, addr & 1);
741 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
155c3eac 742 dead_tmp(tmp);
d9ba4830 743 }
155c3eac 744 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 745}
746
747/* Set PC and Thumb state from var. var is marked as dead. */
748static inline void gen_bx(DisasContext *s, TCGv var)
749{
d9ba4830 750 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 751 tcg_gen_andi_i32(cpu_R[15], var, ~1);
752 tcg_gen_andi_i32(var, var, 1);
753 store_cpu_field(var, thumb);
d9ba4830
PB		 754}
755
21aeb343
JR		 756/* Variant of store_reg which uses branch&exchange logic when storing
757 to r15 in ARM architecture v7 and above. The source must be a temporary
758 and will be marked as dead. */
759static inline void store_reg_bx(CPUState *env, DisasContext *s,
760 int reg, TCGv var)
761{
762 if (reg == 15 && ENABLE_ARCH_7) {
763 gen_bx(s, var);
764 } else {
765 store_reg(s, reg, var);
766 }
767}
768
b0109805
PB		 769static inline TCGv gen_ld8s(TCGv addr, int index)
770{
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8s(tmp, addr, index);
773 return tmp;
774}
775static inline TCGv gen_ld8u(TCGv addr, int index)
776{
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld8u(tmp, addr, index);
779 return tmp;
780}
781static inline TCGv gen_ld16s(TCGv addr, int index)
782{
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16s(tmp, addr, index);
785 return tmp;
786}
787static inline TCGv gen_ld16u(TCGv addr, int index)
788{
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld16u(tmp, addr, index);
791 return tmp;
792}
793static inline TCGv gen_ld32(TCGv addr, int index)
794{
795 TCGv tmp = new_tmp();
796 tcg_gen_qemu_ld32u(tmp, addr, index);
797 return tmp;
798}
84496233
JR		 799static inline TCGv_i64 gen_ld64(TCGv addr, int index)
800{
801 TCGv_i64 tmp = tcg_temp_new_i64();
802 tcg_gen_qemu_ld64(tmp, addr, index);
803 return tmp;
804}
b0109805
PB		 805static inline void gen_st8(TCGv val, TCGv addr, int index)
806{
807 tcg_gen_qemu_st8(val, addr, index);
808 dead_tmp(val);
809}
810static inline void gen_st16(TCGv val, TCGv addr, int index)
811{
812 tcg_gen_qemu_st16(val, addr, index);
813 dead_tmp(val);
814}
815static inline void gen_st32(TCGv val, TCGv addr, int index)
816{
817 tcg_gen_qemu_st32(val, addr, index);
818 dead_tmp(val);
819}
84496233
JR		 820static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
821{
822 tcg_gen_qemu_st64(val, addr, index);
823 tcg_temp_free_i64(val);
824}
b5ff1b31 825
5e3f878a
PB		 826static inline void gen_set_pc_im(uint32_t val)
827{
155c3eac 828 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 829}
830
b5ff1b31
FB		 831/* Force a TB lookup after an instruction that changes the CPU state. */
832static inline void gen_lookup_tb(DisasContext *s)
833{
a6445c52 834 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 835 s->is_jmp = DISAS_UPDATE;
836}
837
b0109805
PB		 838static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
839 TCGv var)
2c0262af 840{
1e8d4eec 841 int val, rm, shift, shiftop;
b26eefb6 842 TCGv offset;
2c0262af
FB		 843
844 if (!(insn & (1 << 25))) {
845 /* immediate */
846 val = insn & 0xfff;
847 if (!(insn & (1 << 23)))
848 val = -val;
537730b9 849 if (val != 0)
b0109805 850 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 851 } else {
852 /* shift/register */
853 rm = (insn) & 0xf;
854 shift = (insn >> 7) & 0x1f;
1e8d4eec 855 shiftop = (insn >> 5) & 3;
b26eefb6 856 offset = load_reg(s, rm);
9a119ff6 857 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 858 if (!(insn & (1 << 23)))
b0109805 859 tcg_gen_sub_i32(var, var, offset);
2c0262af 860 else
b0109805 861 tcg_gen_add_i32(var, var, offset);
b26eefb6 862 dead_tmp(offset);
2c0262af
FB		 863 }
864}
865
191f9a93 866static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 867 int extra, TCGv var)
2c0262af
FB		 868{
869 int val, rm;
b26eefb6 870 TCGv offset;
3b46e624 871
2c0262af
FB		 872 if (insn & (1 << 22)) {
873 /* immediate */
874 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
875 if (!(insn & (1 << 23)))
876 val = -val;
18acad92 877 val += extra;
537730b9 878 if (val != 0)
b0109805 879 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 880 } else {
881 /* register */
191f9a93 882 if (extra)
b0109805 883 tcg_gen_addi_i32(var, var, extra);
2c0262af 884 rm = (insn) & 0xf;
b26eefb6 885 offset = load_reg(s, rm);
2c0262af 886 if (!(insn & (1 << 23)))
b0109805 887 tcg_gen_sub_i32(var, var, offset);
2c0262af 888 else
b0109805 889 tcg_gen_add_i32(var, var, offset);
b26eefb6 890 dead_tmp(offset);
2c0262af
FB		 891 }
892}
893
4373f3ce
PB		 894#define VFP_OP2(name) \
895static inline void gen_vfp_##name(int dp) \
896{ \
897 if (dp) \
898 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 else \
900 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 901}
902
4373f3ce
PB		 903VFP_OP2(add)
904VFP_OP2(sub)
905VFP_OP2(mul)
906VFP_OP2(div)
907
908#undef VFP_OP2
909
910static inline void gen_vfp_abs(int dp)
911{
912 if (dp)
913 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
914 else
915 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
916}
917
918static inline void gen_vfp_neg(int dp)
919{
920 if (dp)
921 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
922 else
923 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
924}
925
926static inline void gen_vfp_sqrt(int dp)
927{
928 if (dp)
929 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
930 else
931 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
932}
933
934static inline void gen_vfp_cmp(int dp)
935{
936 if (dp)
937 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
938 else
939 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
940}
941
942static inline void gen_vfp_cmpe(int dp)
943{
944 if (dp)
945 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
946 else
947 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
948}
949
950static inline void gen_vfp_F1_ld0(int dp)
951{
952 if (dp)
5b340b51 953 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 954 else
5b340b51 955 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 956}
957
958static inline void gen_vfp_uito(int dp)
959{
960 if (dp)
961 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
962 else
963 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
964}
965
966static inline void gen_vfp_sito(int dp)
967{
968 if (dp)
66230e0d 969 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 970 else
66230e0d 971 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 972}
973
974static inline void gen_vfp_toui(int dp)
975{
976 if (dp)
977 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
980}
981
982static inline void gen_vfp_touiz(int dp)
983{
984 if (dp)
985 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
986 else
987 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
988}
989
990static inline void gen_vfp_tosi(int dp)
991{
992 if (dp)
993 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
994 else
995 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
996}
997
998static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 999{
1000 if (dp)
4373f3ce 1001 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 1002 else
4373f3ce
PB		 1003 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1004}
1005
1006#define VFP_GEN_FIX(name) \
1007static inline void gen_vfp_##name(int dp, int shift) \
1008{ \
b75263d6 1009 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1010 if (dp) \
b75263d6 1011 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1012 else \
b75263d6
JR		 1013 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1014 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1015}
4373f3ce
PB		 1016VFP_GEN_FIX(tosh)
1017VFP_GEN_FIX(tosl)
1018VFP_GEN_FIX(touh)
1019VFP_GEN_FIX(toul)
1020VFP_GEN_FIX(shto)
1021VFP_GEN_FIX(slto)
1022VFP_GEN_FIX(uhto)
1023VFP_GEN_FIX(ulto)
1024#undef VFP_GEN_FIX
9ee6e8bb 1025
312eea9f 1026static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1027{
1028 if (dp)
312eea9f 1029 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1030 else
312eea9f 1031 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1032}
1033
312eea9f 1034static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1035{
1036 if (dp)
312eea9f 1037 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1038 else
312eea9f 1039 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1040}
1041
8e96005d
FB		 1042static inline long
1043vfp_reg_offset (int dp, int reg)
1044{
1045 if (dp)
1046 return offsetof(CPUARMState, vfp.regs[reg]);
1047 else if (reg & 1) {
1048 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1049 + offsetof(CPU_DoubleU, l.upper);
1050 } else {
1051 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1052 + offsetof(CPU_DoubleU, l.lower);
1053 }
1054}
9ee6e8bb
PB		 1055
1056/* Return the offset of a 32-bit piece of a NEON register.
1057 zero is the least significant end of the register. */
1058static inline long
1059neon_reg_offset (int reg, int n)
1060{
1061 int sreg;
1062 sreg = reg * 2 + n;
1063 return vfp_reg_offset(0, sreg);
1064}
1065
8f8e3aa4
PB		 1066static TCGv neon_load_reg(int reg, int pass)
1067{
1068 TCGv tmp = new_tmp();
1069 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1070 return tmp;
1071}
1072
1073static void neon_store_reg(int reg, int pass, TCGv var)
1074{
1075 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1076 dead_tmp(var);
1077}
1078
a7812ae4 1079static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1080{
1081 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1082}
1083
a7812ae4 1084static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1085{
1086 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1087}
1088
4373f3ce
PB		 1089#define tcg_gen_ld_f32 tcg_gen_ld_i32
1090#define tcg_gen_ld_f64 tcg_gen_ld_i64
1091#define tcg_gen_st_f32 tcg_gen_st_i32
1092#define tcg_gen_st_f64 tcg_gen_st_i64
1093
b7bcbe95
FB		 1094static inline void gen_mov_F0_vreg(int dp, int reg)
1095{
1096 if (dp)
4373f3ce 1097 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1098 else
4373f3ce 1099 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1100}
1101
1102static inline void gen_mov_F1_vreg(int dp, int reg)
1103{
1104 if (dp)
4373f3ce 1105 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1106 else
4373f3ce 1107 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1108}
1109
1110static inline void gen_mov_vreg_F0(int dp, int reg)
1111{
1112 if (dp)
4373f3ce 1113 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1114 else
4373f3ce 1115 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1116}
1117
18c9b560
AZ		 1118#define ARM_CP_RW_BIT (1 << 20)
1119
a7812ae4 1120static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1121{
1122 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1123}
1124
a7812ae4 1125static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1126{
1127 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1128}
1129
da6b5335 1130static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1131{
da6b5335
FN		 1132 TCGv var = new_tmp();
1133 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1134 return var;
e677137d
PB		 1135}
1136
da6b5335 1137static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1138{
da6b5335 1139 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
d9968827 1140 dead_tmp(var);
e677137d
PB		 1141}
1142
1143static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1144{
1145 iwmmxt_store_reg(cpu_M0, rn);
1146}
1147
1148static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1149{
1150 iwmmxt_load_reg(cpu_M0, rn);
1151}
1152
1153static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1154{
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1157}
1158
1159static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1160{
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1163}
1164
1165static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1166{
1167 iwmmxt_load_reg(cpu_V1, rn);
1168 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1169}
1170
1171#define IWMMXT_OP(name) \
1172static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173{ \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176}
1177
1178#define IWMMXT_OP_ENV(name) \
1179static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1180{ \
1181 iwmmxt_load_reg(cpu_V1, rn); \
1182 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183}
1184
1185#define IWMMXT_OP_ENV_SIZE(name) \
1186IWMMXT_OP_ENV(name##b) \
1187IWMMXT_OP_ENV(name##w) \
1188IWMMXT_OP_ENV(name##l)
1189
1190#define IWMMXT_OP_ENV1(name) \
1191static inline void gen_op_iwmmxt_##name##_M0(void) \
1192{ \
1193 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1194}
1195
1196IWMMXT_OP(maddsq)
1197IWMMXT_OP(madduq)
1198IWMMXT_OP(sadb)
1199IWMMXT_OP(sadw)
1200IWMMXT_OP(mulslw)
1201IWMMXT_OP(mulshw)
1202IWMMXT_OP(mululw)
1203IWMMXT_OP(muluhw)
1204IWMMXT_OP(macsw)
1205IWMMXT_OP(macuw)
1206
1207IWMMXT_OP_ENV_SIZE(unpackl)
1208IWMMXT_OP_ENV_SIZE(unpackh)
1209
1210IWMMXT_OP_ENV1(unpacklub)
1211IWMMXT_OP_ENV1(unpackluw)
1212IWMMXT_OP_ENV1(unpacklul)
1213IWMMXT_OP_ENV1(unpackhub)
1214IWMMXT_OP_ENV1(unpackhuw)
1215IWMMXT_OP_ENV1(unpackhul)
1216IWMMXT_OP_ENV1(unpacklsb)
1217IWMMXT_OP_ENV1(unpacklsw)
1218IWMMXT_OP_ENV1(unpacklsl)
1219IWMMXT_OP_ENV1(unpackhsb)
1220IWMMXT_OP_ENV1(unpackhsw)
1221IWMMXT_OP_ENV1(unpackhsl)
1222
1223IWMMXT_OP_ENV_SIZE(cmpeq)
1224IWMMXT_OP_ENV_SIZE(cmpgtu)
1225IWMMXT_OP_ENV_SIZE(cmpgts)
1226
1227IWMMXT_OP_ENV_SIZE(mins)
1228IWMMXT_OP_ENV_SIZE(minu)
1229IWMMXT_OP_ENV_SIZE(maxs)
1230IWMMXT_OP_ENV_SIZE(maxu)
1231
1232IWMMXT_OP_ENV_SIZE(subn)
1233IWMMXT_OP_ENV_SIZE(addn)
1234IWMMXT_OP_ENV_SIZE(subu)
1235IWMMXT_OP_ENV_SIZE(addu)
1236IWMMXT_OP_ENV_SIZE(subs)
1237IWMMXT_OP_ENV_SIZE(adds)
1238
1239IWMMXT_OP_ENV(avgb0)
1240IWMMXT_OP_ENV(avgb1)
1241IWMMXT_OP_ENV(avgw0)
1242IWMMXT_OP_ENV(avgw1)
1243
1244IWMMXT_OP(msadb)
1245
1246IWMMXT_OP_ENV(packuw)
1247IWMMXT_OP_ENV(packul)
1248IWMMXT_OP_ENV(packuq)
1249IWMMXT_OP_ENV(packsw)
1250IWMMXT_OP_ENV(packsl)
1251IWMMXT_OP_ENV(packsq)
1252
e677137d
PB		 1253static void gen_op_iwmmxt_set_mup(void)
1254{
1255 TCGv tmp;
1256 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1257 tcg_gen_ori_i32(tmp, tmp, 2);
1258 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259}
1260
1261static void gen_op_iwmmxt_set_cup(void)
1262{
1263 TCGv tmp;
1264 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1265 tcg_gen_ori_i32(tmp, tmp, 1);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1267}
1268
1269static void gen_op_iwmmxt_setpsr_nz(void)
1270{
1271 TCGv tmp = new_tmp();
1272 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1273 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1274}
1275
1276static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1277{
1278 iwmmxt_load_reg(cpu_V1, rn);
86831435 1279 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1280 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1281}
1282
da6b5335 1283static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1284{
1285 int rd;
1286 uint32_t offset;
da6b5335 1287 TCGv tmp;
18c9b560
AZ		 1288
1289 rd = (insn >> 16) & 0xf;
da6b5335 1290 tmp = load_reg(s, rd);
18c9b560
AZ		 1291
1292 offset = (insn & 0xff) << ((insn >> 7) & 2);
1293 if (insn & (1 << 24)) {
1294 /* Pre indexed */
1295 if (insn & (1 << 23))
da6b5335 1296 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1297 else
da6b5335
FN		 1298 tcg_gen_addi_i32(tmp, tmp, -offset);
1299 tcg_gen_mov_i32(dest, tmp);
18c9b560 1300 if (insn & (1 << 21))
da6b5335
FN		 1301 store_reg(s, rd, tmp);
1302 else
1303 dead_tmp(tmp);
18c9b560
AZ		 1304 } else if (insn & (1 << 21)) {
1305 /* Post indexed */
da6b5335 1306 tcg_gen_mov_i32(dest, tmp);
18c9b560 1307 if (insn & (1 << 23))
da6b5335 1308 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1309 else
da6b5335
FN		 1310 tcg_gen_addi_i32(tmp, tmp, -offset);
1311 store_reg(s, rd, tmp);
18c9b560
AZ		 1312 } else if (!(insn & (1 << 23)))
1313 return 1;
1314 return 0;
1315}
1316
da6b5335 1317static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1318{
1319 int rd = (insn >> 0) & 0xf;
da6b5335 1320 TCGv tmp;
18c9b560 1321
da6b5335
FN		 1322 if (insn & (1 << 8)) {
1323 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1324 return 1;
da6b5335
FN		 1325 } else {
1326 tmp = iwmmxt_load_creg(rd);
1327 }
1328 } else {
1329 tmp = new_tmp();
1330 iwmmxt_load_reg(cpu_V0, rd);
1331 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1332 }
1333 tcg_gen_andi_i32(tmp, tmp, mask);
1334 tcg_gen_mov_i32(dest, tmp);
1335 dead_tmp(tmp);
18c9b560
AZ		 1336 return 0;
1337}
1338
1339/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1340 (ie. an undefined instruction). */
1341static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1342{
1343 int rd, wrd;
1344 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1345 TCGv addr;
1346 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1347
1348 if ((insn & 0x0e000e00) == 0x0c000000) {
1349 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1350 wrd = insn & 0xf;
1351 rdlo = (insn >> 12) & 0xf;
1352 rdhi = (insn >> 16) & 0xf;
1353 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1354 iwmmxt_load_reg(cpu_V0, wrd);
1355 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1356 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1357 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1358 } else { /* TMCRR */
da6b5335
FN		 1359 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1360 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1361 gen_op_iwmmxt_set_mup();
1362 }
1363 return 0;
1364 }
1365
1366 wrd = (insn >> 12) & 0xf;
da6b5335
FN		 1367 addr = new_tmp();
1368 if (gen_iwmmxt_address(s, insn, addr)) {
1369 dead_tmp(addr);
18c9b560 1370 return 1;
da6b5335 1371 }
18c9b560
AZ		 1372 if (insn & ARM_CP_RW_BIT) {
1373 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
da6b5335
FN		 1374 tmp = new_tmp();
1375 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1376 iwmmxt_store_creg(wrd, tmp);
18c9b560 1377 } else {
e677137d
PB		 1378 i = 1;
1379 if (insn & (1 << 8)) {
1380 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1381 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1382 i = 0;
1383 } else { /* WLDRW wRd */
da6b5335 1384 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1385 }
1386 } else {
1387 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1388 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1389 } else { /* WLDRB */
da6b5335 1390 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1391 }
1392 }
1393 if (i) {
1394 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1395 dead_tmp(tmp);
1396 }
18c9b560
AZ		 1397 gen_op_iwmmxt_movq_wRn_M0(wrd);
1398 }
1399 } else {
1400 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1401 tmp = iwmmxt_load_creg(wrd);
1402 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1403 } else {
1404 gen_op_iwmmxt_movq_M0_wRn(wrd);
e677137d
PB		 1405 tmp = new_tmp();
1406 if (insn & (1 << 8)) {
1407 if (insn & (1 << 22)) { /* WSTRD */
1408 dead_tmp(tmp);
da6b5335 1409 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1410 } else { /* WSTRW wRd */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1412 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1413 }
1414 } else {
1415 if (insn & (1 << 22)) { /* WSTRH */
1416 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1417 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1418 } else { /* WSTRB */
1419 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1420 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1421 }
1422 }
18c9b560
AZ		 1423 }
1424 }
d9968827 1425 dead_tmp(addr);
18c9b560
AZ		 1426 return 0;
1427 }
1428
1429 if ((insn & 0x0f000000) != 0x0e000000)
1430 return 1;
1431
1432 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1433 case 0x000: /* WOR */
1434 wrd = (insn >> 12) & 0xf;
1435 rd0 = (insn >> 0) & 0xf;
1436 rd1 = (insn >> 16) & 0xf;
1437 gen_op_iwmmxt_movq_M0_wRn(rd0);
1438 gen_op_iwmmxt_orq_M0_wRn(rd1);
1439 gen_op_iwmmxt_setpsr_nz();
1440 gen_op_iwmmxt_movq_wRn_M0(wrd);
1441 gen_op_iwmmxt_set_mup();
1442 gen_op_iwmmxt_set_cup();
1443 break;
1444 case 0x011: /* TMCR */
1445 if (insn & 0xf)
1446 return 1;
1447 rd = (insn >> 12) & 0xf;
1448 wrd = (insn >> 16) & 0xf;
1449 switch (wrd) {
1450 case ARM_IWMMXT_wCID:
1451 case ARM_IWMMXT_wCASF:
1452 break;
1453 case ARM_IWMMXT_wCon:
1454 gen_op_iwmmxt_set_cup();
1455 /* Fall through. */
1456 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1457 tmp = iwmmxt_load_creg(wrd);
1458 tmp2 = load_reg(s, rd);
f669df27 1459 tcg_gen_andc_i32(tmp, tmp, tmp2);
da6b5335
FN		 1460 dead_tmp(tmp2);
1461 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1462 break;
1463 case ARM_IWMMXT_wCGR0:
1464 case ARM_IWMMXT_wCGR1:
1465 case ARM_IWMMXT_wCGR2:
1466 case ARM_IWMMXT_wCGR3:
1467 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1468 tmp = load_reg(s, rd);
1469 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1470 break;
1471 default:
1472 return 1;
1473 }
1474 break;
1475 case 0x100: /* WXOR */
1476 wrd = (insn >> 12) & 0xf;
1477 rd0 = (insn >> 0) & 0xf;
1478 rd1 = (insn >> 16) & 0xf;
1479 gen_op_iwmmxt_movq_M0_wRn(rd0);
1480 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1481 gen_op_iwmmxt_setpsr_nz();
1482 gen_op_iwmmxt_movq_wRn_M0(wrd);
1483 gen_op_iwmmxt_set_mup();
1484 gen_op_iwmmxt_set_cup();
1485 break;
1486 case 0x111: /* TMRC */
1487 if (insn & 0xf)
1488 return 1;
1489 rd = (insn >> 12) & 0xf;
1490 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1491 tmp = iwmmxt_load_creg(wrd);
1492 store_reg(s, rd, tmp);
18c9b560
AZ		 1493 break;
1494 case 0x300: /* WANDN */
1495 wrd = (insn >> 12) & 0xf;
1496 rd0 = (insn >> 0) & 0xf;
1497 rd1 = (insn >> 16) & 0xf;
1498 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1499 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1500 gen_op_iwmmxt_andq_M0_wRn(rd1);
1501 gen_op_iwmmxt_setpsr_nz();
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 gen_op_iwmmxt_set_mup();
1504 gen_op_iwmmxt_set_cup();
1505 break;
1506 case 0x200: /* WAND */
1507 wrd = (insn >> 12) & 0xf;
1508 rd0 = (insn >> 0) & 0xf;
1509 rd1 = (insn >> 16) & 0xf;
1510 gen_op_iwmmxt_movq_M0_wRn(rd0);
1511 gen_op_iwmmxt_andq_M0_wRn(rd1);
1512 gen_op_iwmmxt_setpsr_nz();
1513 gen_op_iwmmxt_movq_wRn_M0(wrd);
1514 gen_op_iwmmxt_set_mup();
1515 gen_op_iwmmxt_set_cup();
1516 break;
1517 case 0x810: case 0xa10: /* WMADD */
1518 wrd = (insn >> 12) & 0xf;
1519 rd0 = (insn >> 0) & 0xf;
1520 rd1 = (insn >> 16) & 0xf;
1521 gen_op_iwmmxt_movq_M0_wRn(rd0);
1522 if (insn & (1 << 21))
1523 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1524 else
1525 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1526 gen_op_iwmmxt_movq_wRn_M0(wrd);
1527 gen_op_iwmmxt_set_mup();
1528 break;
1529 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1530 wrd = (insn >> 12) & 0xf;
1531 rd0 = (insn >> 16) & 0xf;
1532 rd1 = (insn >> 0) & 0xf;
1533 gen_op_iwmmxt_movq_M0_wRn(rd0);
1534 switch ((insn >> 22) & 3) {
1535 case 0:
1536 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1537 break;
1538 case 1:
1539 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1540 break;
1541 case 2:
1542 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1543 break;
1544 case 3:
1545 return 1;
1546 }
1547 gen_op_iwmmxt_movq_wRn_M0(wrd);
1548 gen_op_iwmmxt_set_mup();
1549 gen_op_iwmmxt_set_cup();
1550 break;
1551 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1552 wrd = (insn >> 12) & 0xf;
1553 rd0 = (insn >> 16) & 0xf;
1554 rd1 = (insn >> 0) & 0xf;
1555 gen_op_iwmmxt_movq_M0_wRn(rd0);
1556 switch ((insn >> 22) & 3) {
1557 case 0:
1558 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1559 break;
1560 case 1:
1561 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1562 break;
1563 case 2:
1564 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1565 break;
1566 case 3:
1567 return 1;
1568 }
1569 gen_op_iwmmxt_movq_wRn_M0(wrd);
1570 gen_op_iwmmxt_set_mup();
1571 gen_op_iwmmxt_set_cup();
1572 break;
1573 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 16) & 0xf;
1576 rd1 = (insn >> 0) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 if (insn & (1 << 22))
1579 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1580 else
1581 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1582 if (!(insn & (1 << 20)))
1583 gen_op_iwmmxt_addl_M0_wRn(wrd);
1584 gen_op_iwmmxt_movq_wRn_M0(wrd);
1585 gen_op_iwmmxt_set_mup();
1586 break;
1587 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1588 wrd = (insn >> 12) & 0xf;
1589 rd0 = (insn >> 16) & 0xf;
1590 rd1 = (insn >> 0) & 0xf;
1591 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1592 if (insn & (1 << 21)) {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1597 } else {
1598 if (insn & (1 << 20))
1599 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1600 else
1601 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1602 }
18c9b560
AZ		 1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 if (insn & (1 << 21))
1612 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1613 else
1614 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1615 if (!(insn & (1 << 20))) {
e677137d
PB		 1616 iwmmxt_load_reg(cpu_V1, wrd);
1617 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1618 }
1619 gen_op_iwmmxt_movq_wRn_M0(wrd);
1620 gen_op_iwmmxt_set_mup();
1621 break;
1622 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 16) & 0xf;
1625 rd1 = (insn >> 0) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 switch ((insn >> 22) & 3) {
1628 case 0:
1629 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1630 break;
1631 case 1:
1632 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1633 break;
1634 case 2:
1635 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1636 break;
1637 case 3:
1638 return 1;
1639 }
1640 gen_op_iwmmxt_movq_wRn_M0(wrd);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1643 break;
1644 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1645 wrd = (insn >> 12) & 0xf;
1646 rd0 = (insn >> 16) & 0xf;
1647 rd1 = (insn >> 0) & 0xf;
1648 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1649 if (insn & (1 << 22)) {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1654 } else {
1655 if (insn & (1 << 20))
1656 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1657 else
1658 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1659 }
18c9b560
AZ		 1660 gen_op_iwmmxt_movq_wRn_M0(wrd);
1661 gen_op_iwmmxt_set_mup();
1662 gen_op_iwmmxt_set_cup();
1663 break;
1664 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1665 wrd = (insn >> 12) & 0xf;
1666 rd0 = (insn >> 16) & 0xf;
1667 rd1 = (insn >> 0) & 0xf;
1668 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1669 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1670 tcg_gen_andi_i32(tmp, tmp, 7);
1671 iwmmxt_load_reg(cpu_V1, rd1);
1672 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1673 dead_tmp(tmp);
18c9b560
AZ		 1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 break;
1677 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1678 if (((insn >> 6) & 3) == 3)
1679 return 1;
18c9b560
AZ		 1680 rd = (insn >> 12) & 0xf;
1681 wrd = (insn >> 16) & 0xf;
da6b5335 1682 tmp = load_reg(s, rd);
18c9b560
AZ		 1683 gen_op_iwmmxt_movq_M0_wRn(wrd);
1684 switch ((insn >> 6) & 3) {
1685 case 0:
da6b5335
FN		 1686 tmp2 = tcg_const_i32(0xff);
1687 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1688 break;
1689 case 1:
da6b5335
FN		 1690 tmp2 = tcg_const_i32(0xffff);
1691 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1692 break;
1693 case 2:
da6b5335
FN		 1694 tmp2 = tcg_const_i32(0xffffffff);
1695 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1696 break;
da6b5335
FN		 1697 default:
1698 TCGV_UNUSED(tmp2);
1699 TCGV_UNUSED(tmp3);
18c9b560 1700 }
da6b5335
FN		 1701 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1702 tcg_temp_free(tmp3);
1703 tcg_temp_free(tmp2);
1704 dead_tmp(tmp);
18c9b560
AZ		 1705 gen_op_iwmmxt_movq_wRn_M0(wrd);
1706 gen_op_iwmmxt_set_mup();
1707 break;
1708 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1709 rd = (insn >> 12) & 0xf;
1710 wrd = (insn >> 16) & 0xf;
da6b5335 1711 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1712 return 1;
1713 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335 1714 tmp = new_tmp();
18c9b560
AZ		 1715 switch ((insn >> 22) & 3) {
1716 case 0:
da6b5335
FN		 1717 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1718 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1719 if (insn & 8) {
1720 tcg_gen_ext8s_i32(tmp, tmp);
1721 } else {
1722 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1723 }
1724 break;
1725 case 1:
da6b5335
FN		 1726 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1727 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1728 if (insn & 8) {
1729 tcg_gen_ext16s_i32(tmp, tmp);
1730 } else {
1731 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1732 }
1733 break;
1734 case 2:
da6b5335
FN		 1735 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1736 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1737 break;
18c9b560 1738 }
da6b5335 1739 store_reg(s, rd, tmp);
18c9b560
AZ		 1740 break;
1741 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1742 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1743 return 1;
da6b5335 1744 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1745 switch ((insn >> 22) & 3) {
1746 case 0:
da6b5335 1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1748 break;
1749 case 1:
da6b5335 1750 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1751 break;
1752 case 2:
da6b5335 1753 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1754 break;
18c9b560 1755 }
da6b5335
FN		 1756 tcg_gen_shli_i32(tmp, tmp, 28);
1757 gen_set_nzcv(tmp);
1758 dead_tmp(tmp);
18c9b560
AZ		 1759 break;
1760 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1761 if (((insn >> 6) & 3) == 3)
1762 return 1;
18c9b560
AZ		 1763 rd = (insn >> 12) & 0xf;
1764 wrd = (insn >> 16) & 0xf;
da6b5335 1765 tmp = load_reg(s, rd);
18c9b560
AZ		 1766 switch ((insn >> 6) & 3) {
1767 case 0:
da6b5335 1768 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1769 break;
1770 case 1:
da6b5335 1771 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1772 break;
1773 case 2:
da6b5335 1774 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1775 break;
18c9b560 1776 }
da6b5335 1777 dead_tmp(tmp);
18c9b560
AZ		 1778 gen_op_iwmmxt_movq_wRn_M0(wrd);
1779 gen_op_iwmmxt_set_mup();
1780 break;
1781 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1782 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1783 return 1;
da6b5335
FN		 1784 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1785 tmp2 = new_tmp();
1786 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1787 switch ((insn >> 22) & 3) {
1788 case 0:
1789 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1790 tcg_gen_shli_i32(tmp2, tmp2, 4);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1792 }
1793 break;
1794 case 1:
1795 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1796 tcg_gen_shli_i32(tmp2, tmp2, 8);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1798 }
1799 break;
1800 case 2:
da6b5335
FN		 1801 tcg_gen_shli_i32(tmp2, tmp2, 16);
1802 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1803 break;
18c9b560 1804 }
da6b5335
FN		 1805 gen_set_nzcv(tmp);
1806 dead_tmp(tmp2);
1807 dead_tmp(tmp);
18c9b560
AZ		 1808 break;
1809 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 16) & 0xf;
1812 gen_op_iwmmxt_movq_M0_wRn(rd0);
1813 switch ((insn >> 22) & 3) {
1814 case 0:
e677137d 1815 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1816 break;
1817 case 1:
e677137d 1818 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1819 break;
1820 case 2:
e677137d 1821 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1822 break;
1823 case 3:
1824 return 1;
1825 }
1826 gen_op_iwmmxt_movq_wRn_M0(wrd);
1827 gen_op_iwmmxt_set_mup();
1828 break;
1829 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1830 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1831 return 1;
da6b5335
FN		 1832 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1833 tmp2 = new_tmp();
1834 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1835 switch ((insn >> 22) & 3) {
1836 case 0:
1837 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1838 tcg_gen_shli_i32(tmp2, tmp2, 4);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1840 }
1841 break;
1842 case 1:
1843 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1844 tcg_gen_shli_i32(tmp2, tmp2, 8);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1846 }
1847 break;
1848 case 2:
da6b5335
FN		 1849 tcg_gen_shli_i32(tmp2, tmp2, 16);
1850 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1851 break;
18c9b560 1852 }
da6b5335
FN		 1853 gen_set_nzcv(tmp);
1854 dead_tmp(tmp2);
1855 dead_tmp(tmp);
18c9b560
AZ		 1856 break;
1857 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1858 rd = (insn >> 12) & 0xf;
1859 rd0 = (insn >> 16) & 0xf;
da6b5335 1860 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1861 return 1;
1862 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 1863 tmp = new_tmp();
18c9b560
AZ		 1864 switch ((insn >> 22) & 3) {
1865 case 0:
da6b5335 1866 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1867 break;
1868 case 1:
da6b5335 1869 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1870 break;
1871 case 2:
da6b5335 1872 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1873 break;
18c9b560 1874 }
da6b5335 1875 store_reg(s, rd, tmp);
18c9b560
AZ		 1876 break;
1877 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1878 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1879 wrd = (insn >> 12) & 0xf;
1880 rd0 = (insn >> 16) & 0xf;
1881 rd1 = (insn >> 0) & 0xf;
1882 gen_op_iwmmxt_movq_M0_wRn(rd0);
1883 switch ((insn >> 22) & 3) {
1884 case 0:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1889 break;
1890 case 1:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1895 break;
1896 case 2:
1897 if (insn & (1 << 21))
1898 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1899 else
1900 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 gen_op_iwmmxt_set_cup();
1908 break;
1909 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1910 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1911 wrd = (insn >> 12) & 0xf;
1912 rd0 = (insn >> 16) & 0xf;
1913 gen_op_iwmmxt_movq_M0_wRn(rd0);
1914 switch ((insn >> 22) & 3) {
1915 case 0:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsb_M0();
1918 else
1919 gen_op_iwmmxt_unpacklub_M0();
1920 break;
1921 case 1:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsw_M0();
1924 else
1925 gen_op_iwmmxt_unpackluw_M0();
1926 break;
1927 case 2:
1928 if (insn & (1 << 21))
1929 gen_op_iwmmxt_unpacklsl_M0();
1930 else
1931 gen_op_iwmmxt_unpacklul_M0();
1932 break;
1933 case 3:
1934 return 1;
1935 }
1936 gen_op_iwmmxt_movq_wRn_M0(wrd);
1937 gen_op_iwmmxt_set_mup();
1938 gen_op_iwmmxt_set_cup();
1939 break;
1940 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1941 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1942 wrd = (insn >> 12) & 0xf;
1943 rd0 = (insn >> 16) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 switch ((insn >> 22) & 3) {
1946 case 0:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsb_M0();
1949 else
1950 gen_op_iwmmxt_unpackhub_M0();
1951 break;
1952 case 1:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsw_M0();
1955 else
1956 gen_op_iwmmxt_unpackhuw_M0();
1957 break;
1958 case 2:
1959 if (insn & (1 << 21))
1960 gen_op_iwmmxt_unpackhsl_M0();
1961 else
1962 gen_op_iwmmxt_unpackhul_M0();
1963 break;
1964 case 3:
1965 return 1;
1966 }
1967 gen_op_iwmmxt_movq_wRn_M0(wrd);
1968 gen_op_iwmmxt_set_mup();
1969 gen_op_iwmmxt_set_cup();
1970 break;
1971 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1972 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1973 if (((insn >> 22) & 3) == 0)
1974 return 1;
18c9b560
AZ		 1975 wrd = (insn >> 12) & 0xf;
1976 rd0 = (insn >> 16) & 0xf;
1977 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1978 tmp = new_tmp();
1979 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1980 dead_tmp(tmp);
18c9b560 1981 return 1;
da6b5335 1982 }
18c9b560 1983 switch ((insn >> 22) & 3) {
18c9b560 1984 case 1:
da6b5335 1985 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1986 break;
1987 case 2:
da6b5335 1988 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1989 break;
1990 case 3:
da6b5335 1991 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1992 break;
1993 }
da6b5335 1994 dead_tmp(tmp);
18c9b560
AZ		 1995 gen_op_iwmmxt_movq_wRn_M0(wrd);
1996 gen_op_iwmmxt_set_mup();
1997 gen_op_iwmmxt_set_cup();
1998 break;
1999 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2000 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 2001 if (((insn >> 22) & 3) == 0)
2002 return 1;
18c9b560
AZ		 2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2006 tmp = new_tmp();
2007 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2008 dead_tmp(tmp);
18c9b560 2009 return 1;
da6b5335 2010 }
18c9b560 2011 switch ((insn >> 22) & 3) {
18c9b560 2012 case 1:
da6b5335 2013 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2014 break;
2015 case 2:
da6b5335 2016 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2017 break;
2018 case 3:
da6b5335 2019 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2020 break;
2021 }
da6b5335 2022 dead_tmp(tmp);
18c9b560
AZ		 2023 gen_op_iwmmxt_movq_wRn_M0(wrd);
2024 gen_op_iwmmxt_set_mup();
2025 gen_op_iwmmxt_set_cup();
2026 break;
2027 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2028 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2029 if (((insn >> 22) & 3) == 0)
2030 return 1;
18c9b560
AZ		 2031 wrd = (insn >> 12) & 0xf;
2032 rd0 = (insn >> 16) & 0xf;
2033 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2034 tmp = new_tmp();
2035 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2036 dead_tmp(tmp);
18c9b560 2037 return 1;
da6b5335 2038 }
18c9b560 2039 switch ((insn >> 22) & 3) {
18c9b560 2040 case 1:
da6b5335 2041 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2042 break;
2043 case 2:
da6b5335 2044 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2045 break;
2046 case 3:
da6b5335 2047 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2048 break;
2049 }
da6b5335 2050 dead_tmp(tmp);
18c9b560
AZ		 2051 gen_op_iwmmxt_movq_wRn_M0(wrd);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2054 break;
2055 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2056 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2057 if (((insn >> 22) & 3) == 0)
2058 return 1;
18c9b560
AZ		 2059 wrd = (insn >> 12) & 0xf;
2060 rd0 = (insn >> 16) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2062 tmp = new_tmp();
18c9b560 2063 switch ((insn >> 22) & 3) {
18c9b560 2064 case 1:
da6b5335
FN		 2065 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2066 dead_tmp(tmp);
18c9b560 2067 return 1;
da6b5335
FN		 2068 }
2069 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2070 break;
2071 case 2:
da6b5335
FN		 2072 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2073 dead_tmp(tmp);
18c9b560 2074 return 1;
da6b5335
FN		 2075 }
2076 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2077 break;
2078 case 3:
da6b5335
FN		 2079 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2080 dead_tmp(tmp);
18c9b560 2081 return 1;
da6b5335
FN		 2082 }
2083 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2084 break;
2085 }
da6b5335 2086 dead_tmp(tmp);
18c9b560
AZ		 2087 gen_op_iwmmxt_movq_wRn_M0(wrd);
2088 gen_op_iwmmxt_set_mup();
2089 gen_op_iwmmxt_set_cup();
2090 break;
2091 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2092 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2093 wrd = (insn >> 12) & 0xf;
2094 rd0 = (insn >> 16) & 0xf;
2095 rd1 = (insn >> 0) & 0xf;
2096 gen_op_iwmmxt_movq_M0_wRn(rd0);
2097 switch ((insn >> 22) & 3) {
2098 case 0:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minub_M0_wRn(rd1);
2103 break;
2104 case 1:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2109 break;
2110 case 2:
2111 if (insn & (1 << 21))
2112 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2113 else
2114 gen_op_iwmmxt_minul_M0_wRn(rd1);
2115 break;
2116 case 3:
2117 return 1;
2118 }
2119 gen_op_iwmmxt_movq_wRn_M0(wrd);
2120 gen_op_iwmmxt_set_mup();
2121 break;
2122 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2123 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2124 wrd = (insn >> 12) & 0xf;
2125 rd0 = (insn >> 16) & 0xf;
2126 rd1 = (insn >> 0) & 0xf;
2127 gen_op_iwmmxt_movq_M0_wRn(rd0);
2128 switch ((insn >> 22) & 3) {
2129 case 0:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2134 break;
2135 case 1:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2140 break;
2141 case 2:
2142 if (insn & (1 << 21))
2143 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2144 else
2145 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2146 break;
2147 case 3:
2148 return 1;
2149 }
2150 gen_op_iwmmxt_movq_wRn_M0(wrd);
2151 gen_op_iwmmxt_set_mup();
2152 break;
2153 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2154 case 0x402: case 0x502: case 0x602: case 0x702:
2155 wrd = (insn >> 12) & 0xf;
2156 rd0 = (insn >> 16) & 0xf;
2157 rd1 = (insn >> 0) & 0xf;
2158 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2159 tmp = tcg_const_i32((insn >> 20) & 3);
2160 iwmmxt_load_reg(cpu_V1, rd1);
2161 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2162 tcg_temp_free(tmp);
18c9b560
AZ		 2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 break;
2166 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2167 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2168 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2169 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2170 wrd = (insn >> 12) & 0xf;
2171 rd0 = (insn >> 16) & 0xf;
2172 rd1 = (insn >> 0) & 0xf;
2173 gen_op_iwmmxt_movq_M0_wRn(rd0);
2174 switch ((insn >> 20) & 0xf) {
2175 case 0x0:
2176 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2177 break;
2178 case 0x1:
2179 gen_op_iwmmxt_subub_M0_wRn(rd1);
2180 break;
2181 case 0x3:
2182 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2183 break;
2184 case 0x4:
2185 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2186 break;
2187 case 0x5:
2188 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2189 break;
2190 case 0x7:
2191 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2192 break;
2193 case 0x8:
2194 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2195 break;
2196 case 0x9:
2197 gen_op_iwmmxt_subul_M0_wRn(rd1);
2198 break;
2199 case 0xb:
2200 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2201 break;
2202 default:
2203 return 1;
2204 }
2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
2206 gen_op_iwmmxt_set_mup();
2207 gen_op_iwmmxt_set_cup();
2208 break;
2209 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2210 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2211 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2212 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2216 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2217 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2218 tcg_temp_free(tmp);
18c9b560
AZ		 2219 gen_op_iwmmxt_movq_wRn_M0(wrd);
2220 gen_op_iwmmxt_set_mup();
2221 gen_op_iwmmxt_set_cup();
2222 break;
2223 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2224 case 0x418: case 0x518: case 0x618: case 0x718:
2225 case 0x818: case 0x918: case 0xa18: case 0xb18:
2226 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2227 wrd = (insn >> 12) & 0xf;
2228 rd0 = (insn >> 16) & 0xf;
2229 rd1 = (insn >> 0) & 0xf;
2230 gen_op_iwmmxt_movq_M0_wRn(rd0);
2231 switch ((insn >> 20) & 0xf) {
2232 case 0x0:
2233 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2234 break;
2235 case 0x1:
2236 gen_op_iwmmxt_addub_M0_wRn(rd1);
2237 break;
2238 case 0x3:
2239 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2240 break;
2241 case 0x4:
2242 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2243 break;
2244 case 0x5:
2245 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2246 break;
2247 case 0x7:
2248 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2249 break;
2250 case 0x8:
2251 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2252 break;
2253 case 0x9:
2254 gen_op_iwmmxt_addul_M0_wRn(rd1);
2255 break;
2256 case 0xb:
2257 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2258 break;
2259 default:
2260 return 1;
2261 }
2262 gen_op_iwmmxt_movq_wRn_M0(wrd);
2263 gen_op_iwmmxt_set_mup();
2264 gen_op_iwmmxt_set_cup();
2265 break;
2266 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2267 case 0x408: case 0x508: case 0x608: case 0x708:
2268 case 0x808: case 0x908: case 0xa08: case 0xb08:
2269 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2270 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2271 return 1;
18c9b560
AZ		 2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2276 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2277 case 1:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2282 break;
2283 case 2:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packul_M0_wRn(rd1);
2288 break;
2289 case 3:
2290 if (insn & (1 << 21))
2291 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2292 else
2293 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2294 break;
2295 }
2296 gen_op_iwmmxt_movq_wRn_M0(wrd);
2297 gen_op_iwmmxt_set_mup();
2298 gen_op_iwmmxt_set_cup();
2299 break;
2300 case 0x201: case 0x203: case 0x205: case 0x207:
2301 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2302 case 0x211: case 0x213: case 0x215: case 0x217:
2303 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2304 wrd = (insn >> 5) & 0xf;
2305 rd0 = (insn >> 12) & 0xf;
2306 rd1 = (insn >> 0) & 0xf;
2307 if (rd0 == 0xf || rd1 == 0xf)
2308 return 1;
2309 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2310 tmp = load_reg(s, rd0);
2311 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2312 switch ((insn >> 16) & 0xf) {
2313 case 0x0: /* TMIA */
da6b5335 2314 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2315 break;
2316 case 0x8: /* TMIAPH */
da6b5335 2317 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2318 break;
2319 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2320 if (insn & (1 << 16))
da6b5335 2321 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2322 if (insn & (1 << 17))
da6b5335
FN		 2323 tcg_gen_shri_i32(tmp2, tmp2, 16);
2324 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2325 break;
2326 default:
da6b5335
FN		 2327 dead_tmp(tmp2);
2328 dead_tmp(tmp);
18c9b560
AZ		 2329 return 1;
2330 }
da6b5335
FN		 2331 dead_tmp(tmp2);
2332 dead_tmp(tmp);
18c9b560
AZ		 2333 gen_op_iwmmxt_movq_wRn_M0(wrd);
2334 gen_op_iwmmxt_set_mup();
2335 break;
2336 default:
2337 return 1;
2338 }
2339
2340 return 0;
2341}
2342
2343/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2344 (ie. an undefined instruction). */
2345static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2346{
2347 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2348 TCGv tmp, tmp2;
18c9b560
AZ		 2349
2350 if ((insn & 0x0ff00f10) == 0x0e200010) {
2351 /* Multiply with Internal Accumulate Format */
2352 rd0 = (insn >> 12) & 0xf;
2353 rd1 = insn & 0xf;
2354 acc = (insn >> 5) & 7;
2355
2356 if (acc != 0)
2357 return 1;
2358
3a554c0f
FN		 2359 tmp = load_reg(s, rd0);
2360 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2361 switch ((insn >> 16) & 0xf) {
2362 case 0x0: /* MIA */
3a554c0f 2363 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2364 break;
2365 case 0x8: /* MIAPH */
3a554c0f 2366 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2367 break;
2368 case 0xc: /* MIABB */
2369 case 0xd: /* MIABT */
2370 case 0xe: /* MIATB */
2371 case 0xf: /* MIATT */
18c9b560 2372 if (insn & (1 << 16))
3a554c0f 2373 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2374 if (insn & (1 << 17))
3a554c0f
FN		 2375 tcg_gen_shri_i32(tmp2, tmp2, 16);
2376 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2377 break;
2378 default:
2379 return 1;
2380 }
3a554c0f
FN		 2381 dead_tmp(tmp2);
2382 dead_tmp(tmp);
18c9b560
AZ		 2383
2384 gen_op_iwmmxt_movq_wRn_M0(acc);
2385 return 0;
2386 }
2387
2388 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2389 /* Internal Accumulator Access Format */
2390 rdhi = (insn >> 16) & 0xf;
2391 rdlo = (insn >> 12) & 0xf;
2392 acc = insn & 7;
2393
2394 if (acc != 0)
2395 return 1;
2396
2397 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2398 iwmmxt_load_reg(cpu_V0, acc);
2399 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2400 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2401 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2402 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2403 } else { /* MAR */
3a554c0f
FN		 2404 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2405 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2406 }
2407 return 0;
2408 }
2409
2410 return 1;
2411}
2412
c1713132
AZ		 2413/* Disassemble system coprocessor instruction. Return nonzero if
2414 instruction is not defined. */
2415static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2416{
b75263d6 2417 TCGv tmp, tmp2;
c1713132
AZ		 2418 uint32_t rd = (insn >> 12) & 0xf;
2419 uint32_t cp = (insn >> 8) & 0xf;
2420 if (IS_USER(s)) {
2421 return 1;
2422 }
2423
18c9b560 2424 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2425 if (!env->cp[cp].cp_read)
2426 return 1;
8984bd2e
PB		 2427 gen_set_pc_im(s->pc);
2428 tmp = new_tmp();
b75263d6
JR		 2429 tmp2 = tcg_const_i32(insn);
2430 gen_helper_get_cp(tmp, cpu_env, tmp2);
2431 tcg_temp_free(tmp2);
8984bd2e 2432 store_reg(s, rd, tmp);
c1713132
AZ		 2433 } else {
2434 if (!env->cp[cp].cp_write)
2435 return 1;
8984bd2e
PB		 2436 gen_set_pc_im(s->pc);
2437 tmp = load_reg(s, rd);
b75263d6
JR		 2438 tmp2 = tcg_const_i32(insn);
2439 gen_helper_set_cp(cpu_env, tmp2, tmp);
2440 tcg_temp_free(tmp2);
a60de947 2441 dead_tmp(tmp);
c1713132
AZ		 2442 }
2443 return 0;
2444}
2445
9ee6e8bb
PB		 2446static int cp15_user_ok(uint32_t insn)
2447{
2448 int cpn = (insn >> 16) & 0xf;
2449 int cpm = insn & 0xf;
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2451
2452 if (cpn == 13 && cpm == 0) {
2453 /* TLS register. */
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2455 return 1;
2456 }
2457 if (cpn == 7) {
2458 /* ISB, DSB, DMB. */
2459 if ((cpm == 5 && op == 4)
2460 || (cpm == 10 && (op == 4 || op == 5)))
2461 return 1;
2462 }
2463 return 0;
2464}
2465
3f26c122
RV		 2466static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2467{
2468 TCGv tmp;
2469 int cpn = (insn >> 16) & 0xf;
2470 int cpm = insn & 0xf;
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2472
2473 if (!arm_feature(env, ARM_FEATURE_V6K))
2474 return 0;
2475
2476 if (!(cpn == 13 && cpm == 0))
2477 return 0;
2478
2479 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2480 switch (op) {
2481 case 2:
c5883be2 2482 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2483 break;
2484 case 3:
c5883be2 2485 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2486 break;
2487 case 4:
c5883be2 2488 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2489 break;
2490 default:
3f26c122
RV		 2491 return 0;
2492 }
2493 store_reg(s, rd, tmp);
2494
2495 } else {
2496 tmp = load_reg(s, rd);
2497 switch (op) {
2498 case 2:
c5883be2 2499 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2500 break;
2501 case 3:
c5883be2 2502 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2503 break;
2504 case 4:
c5883be2 2505 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2506 break;
2507 default:
c5883be2 2508 dead_tmp(tmp);
3f26c122
RV		 2509 return 0;
2510 }
3f26c122
RV		 2511 }
2512 return 1;
2513}
2514
b5ff1b31
FB		 2515/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2516 instruction is not defined. */
a90b7318 2517static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2518{
2519 uint32_t rd;
b75263d6 2520 TCGv tmp, tmp2;
b5ff1b31 2521
9ee6e8bb
PB		 2522 /* M profile cores use memory mapped registers instead of cp15. */
2523 if (arm_feature(env, ARM_FEATURE_M))
2524 return 1;
2525
2526 if ((insn & (1 << 25)) == 0) {
2527 if (insn & (1 << 20)) {
2528 /* mrrc */
2529 return 1;
2530 }
2531 /* mcrr. Used for block cache operations, so implement as no-op. */
2532 return 0;
2533 }
2534 if ((insn & (1 << 4)) == 0) {
2535 /* cdp */
2536 return 1;
2537 }
2538 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2539 return 1;
2540 }
9332f9da
FB		 2541 if ((insn & 0x0fff0fff) == 0x0e070f90
2542 || (insn & 0x0fff0fff) == 0x0e070f58) {
2543 /* Wait for interrupt. */
8984bd2e 2544 gen_set_pc_im(s->pc);
9ee6e8bb 2545 s->is_jmp = DISAS_WFI;
9332f9da
FB		 2546 return 0;
2547 }
b5ff1b31 2548 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2549
2550 if (cp15_tls_load_store(env, s, insn, rd))
2551 return 0;
2552
b75263d6 2553 tmp2 = tcg_const_i32(insn);
18c9b560 2554 if (insn & ARM_CP_RW_BIT) {
8984bd2e 2555 tmp = new_tmp();
b75263d6 2556 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2557 /* If the destination register is r15 then sets condition codes. */
2558 if (rd != 15)
8984bd2e
PB		 2559 store_reg(s, rd, tmp);
2560 else
2561 dead_tmp(tmp);
b5ff1b31 2562 } else {
8984bd2e 2563 tmp = load_reg(s, rd);
b75263d6 2564 gen_helper_set_cp15(cpu_env, tmp2, tmp);
8984bd2e 2565 dead_tmp(tmp);
a90b7318
AZ		 2566 /* Normally we would always end the TB here, but Linux
2567 * arch/arm/mach-pxa/sleep.S expects two instructions following
2568 * an MMU enable to execute from cache. Imitate this behaviour. */
2569 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2570 (insn & 0x0fff0fff) != 0x0e010f10)
2571 gen_lookup_tb(s);
b5ff1b31 2572 }
b75263d6 2573 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2574 return 0;
2575}
2576
9ee6e8bb
PB		 2577#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2578#define VFP_SREG(insn, bigbit, smallbit) \
2579 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2580#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2581 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2582 reg = (((insn) >> (bigbit)) & 0x0f) \
2583 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2584 } else { \
2585 if (insn & (1 << (smallbit))) \
2586 return 1; \
2587 reg = ((insn) >> (bigbit)) & 0x0f; \
2588 }} while (0)
2589
2590#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2591#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2592#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2593#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2594#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2595#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2596
4373f3ce
PB		 2597/* Move between integer and VFP cores. */
2598static TCGv gen_vfp_mrs(void)
2599{
2600 TCGv tmp = new_tmp();
2601 tcg_gen_mov_i32(tmp, cpu_F0s);
2602 return tmp;
2603}
2604
2605static void gen_vfp_msr(TCGv tmp)
2606{
2607 tcg_gen_mov_i32(cpu_F0s, tmp);
2608 dead_tmp(tmp);
2609}
2610
ad69471c
PB		 2611static void gen_neon_dup_u8(TCGv var, int shift)
2612{
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
86831435 2616 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622}
2623
2624static void gen_neon_dup_low16(TCGv var)
2625{
2626 TCGv tmp = new_tmp();
86831435 2627 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631}
2632
2633static void gen_neon_dup_high16(TCGv var)
2634{
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640}
2641
b7bcbe95
FB		 2642/* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645{
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
312eea9f 2648 TCGv addr;
4373f3ce 2649 TCGv tmp;
ad69471c 2650 TCGv tmp2;
b7bcbe95 2651
40f137e1
PB		 2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
5df8bac1 2655 if (!s->vfp_enabled) {
9ee6e8bb 2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2662 return 1;
2663 }
b7bcbe95
FB		 2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
b7bcbe95
FB		 2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
9ee6e8bb
PB		 2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
b7bcbe95 2676 return 1;
9ee6e8bb
PB		 2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
18c9b560 2692 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2693 /* vfp->arm */
ad69471c 2694 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2695 switch (size) {
2696 case 0:
9ee6e8bb 2697 if (offset)
ad69471c 2698 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2699 if (insn & (1 << 23))
ad69471c 2700 gen_uxtb(tmp);
9ee6e8bb 2701 else
ad69471c 2702 gen_sxtb(tmp);
9ee6e8bb
PB		 2703 break;
2704 case 1:
9ee6e8bb
PB		 2705 if (insn & (1 << 23)) {
2706 if (offset) {
ad69471c 2707 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2708 } else {
ad69471c 2709 gen_uxth(tmp);
9ee6e8bb
PB		 2710 }
2711 } else {
2712 if (offset) {
ad69471c 2713 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2714 } else {
ad69471c 2715 gen_sxth(tmp);
9ee6e8bb
PB		 2716 }
2717 }
2718 break;
2719 case 2:
9ee6e8bb
PB		 2720 break;
2721 }
ad69471c 2722 store_reg(s, rd, tmp);
b7bcbe95
FB		 2723 } else {
2724 /* arm->vfp */
ad69471c 2725 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
ad69471c 2729 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2730 } else if (size == 1) {
ad69471c 2731 gen_neon_dup_low16(tmp);
9ee6e8bb 2732 }
cbbccffc
PB		 2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
ad69471c
PB		 2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
9ee6e8bb
PB		 2746 break;
2747 case 1:
ad69471c
PB		 2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
9ee6e8bb
PB		 2751 break;
2752 case 2:
9ee6e8bb
PB		 2753 break;
2754 }
ad69471c 2755 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2756 }
b7bcbe95 2757 }
9ee6e8bb
PB		 2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
18c9b560 2762 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
40f137e1 2766 rn >>= 1;
9ee6e8bb 2767
b7bcbe95 2768 switch (rn) {
40f137e1 2769 case ARM_VFP_FPSID:
4373f3ce 2770 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
4373f3ce 2776 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2777 break;
40f137e1 2778 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2779 if (IS_USER(s))
2780 return 1;
4373f3ce 2781 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2782 break;
40f137e1
PB		 2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
4373f3ce 2789 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2790 break;
40f137e1 2791 case ARM_VFP_FPSCR:
601d70b9 2792 if (rd == 15) {
4373f3ce
PB		 2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
b7bcbe95 2799 break;
9ee6e8bb
PB		 2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
4373f3ce 2805 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2806 break;
b7bcbe95
FB		 2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
4373f3ce 2812 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2813 }
2814 if (rd == 15) {
b5ff1b31 2815 /* Set the 4 flag bits in the CPSR. */
4373f3ce
PB		 2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
b7bcbe95
FB		 2821 } else {
2822 /* arm->vfp */
4373f3ce 2823 tmp = load_reg(s, rd);
b7bcbe95 2824 if (insn & (1 << 21)) {
40f137e1 2825 rn >>= 1;
b7bcbe95
FB		 2826 /* system register */
2827 switch (rn) {
40f137e1 2828 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2831 /* Writes are ignored. */
2832 break;
40f137e1 2833 case ARM_VFP_FPSCR:
4373f3ce
PB		 2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
b5ff1b31 2836 gen_lookup_tb(s);
b7bcbe95 2837 break;
40f137e1 2838 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2839 if (IS_USER(s))
2840 return 1;
71b3c3de
JR		 2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2844 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
4373f3ce 2849 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2850 break;
b7bcbe95
FB		 2851 default:
2852 return 1;
2853 }
2854 } else {
4373f3ce 2855 gen_vfp_msr(tmp);
b7bcbe95
FB		 2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
9ee6e8bb 2870 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2871 }
2872
04595bf6 2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
b7bcbe95 2874 /* Integer or single precision destination. */
9ee6e8bb 2875 rd = VFP_SREG_D(insn);
b7bcbe95 2876 } else {
9ee6e8bb 2877 VFP_DREG_D(rd, insn);
b7bcbe95 2878 }
04595bf6
PM		 2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
b7bcbe95 2885 } else {
9ee6e8bb 2886 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2887 }
2888 } else {
9ee6e8bb 2889 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
9ee6e8bb
PB		 2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
04595bf6
PM		 2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
9ee6e8bb 2899 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2900 }
2901
69d1fc22 2902 veclen = s->vec_len;
b7bcbe95
FB		 2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
3b46e624 2910
b7bcbe95
FB		 2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
69d1fc22 2923 delta_d = (s->vec_stride >> 1) + 1;
b7bcbe95 2924 else
69d1fc22 2925 delta_d = s->vec_stride + 1;
b7bcbe95
FB		 2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
9ee6e8bb
PB		 2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
644ad806
PB		 2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
9ee6e8bb
PB		 2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
b7bcbe95
FB		 2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 2971 break;
b7bcbe95
FB		 2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
b7bcbe95 3000 gen_vfp_neg(dp);
c9fb531a
PB		 3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
b7bcbe95
FB		 3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
9ee6e8bb
PB		 3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
4373f3ce 3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
5b340b51 3039 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3040 }
9ee6e8bb 3041 break;
b7bcbe95
FB		 3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
60011498
PB		 3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
b7bcbe95
FB		 3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
4373f3ce 3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3113 else
4373f3ce 3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
9ee6e8bb
PB		 3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
644ad806 3125 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
644ad806 3130 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
644ad806 3135 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
644ad806 3140 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3141 break;
b7bcbe95
FB		 3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
9ee6e8bb
PB		 3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
644ad806 3157 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
644ad806 3162 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
644ad806 3167 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
644ad806 3172 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3173 break;
b7bcbe95
FB		 3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
04595bf6
PM		 3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
b7bcbe95
FB		 3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
9ee6e8bb 3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
9ee6e8bb
PB		 3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
b7bcbe95 3244
18c9b560 3245 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3246 /* vfp->arm */
3247 if (dp) {
4373f3ce
PB		 3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
b7bcbe95
FB		 3254 } else {
3255 gen_mov_F0_vreg(0, rm);
4373f3ce
PB		 3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
b7bcbe95 3258 gen_mov_F0_vreg(0, rm + 1);
4373f3ce
PB		 3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
b7bcbe95
FB		 3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
4373f3ce
PB		 3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3271 } else {
4373f3ce
PB		 3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
b7bcbe95 3274 gen_mov_vreg_F0(0, rm);
4373f3ce
PB		 3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
b7bcbe95
FB		 3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
9ee6e8bb 3284 VFP_DREG_D(rd, insn);
b7bcbe95 3285 else
9ee6e8bb
PB		 3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
312eea9f
FN		 3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3290 } else {
312eea9f 3291 addr = load_reg(s, rn);
9ee6e8bb 3292 }
b7bcbe95
FB		 3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
312eea9f 3298 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3299 if (insn & (1 << 20)) {
312eea9f 3300 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
312eea9f 3304 gen_vfp_st(s, dp, addr);
b7bcbe95 3305 }
312eea9f 3306 dead_tmp(addr);
b7bcbe95
FB		 3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
18c9b560 3322 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3323 /* load */
312eea9f 3324 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3329 gen_vfp_st(s, dp, addr);
b7bcbe95 3330 }
312eea9f 3331 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
312eea9f
FN		 3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
b7bcbe95
FB		 3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356}
3357
6e256c93 3358static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3359{
6e256c93
FB		 3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3364 tcg_gen_goto_tb(n);
8984bd2e 3365 gen_set_pc_im(dest);
57fec1fe 3366 tcg_gen_exit_tb((long)tb + n);
6e256c93 3367 } else {
8984bd2e 3368 gen_set_pc_im(dest);
57fec1fe 3369 tcg_gen_exit_tb(0);
6e256c93 3370 }
c53be334
FB		 3371}
3372
8aaca4c0
FB		 3373static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374{
551bd27f 3375 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3376 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3377 if (s->thumb)
d9ba4830
PB		 3378 dest |= 1;
3379 gen_bx_im(s, dest);
8aaca4c0 3380 } else {
6e256c93 3381 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384}
3385
d9ba4830 3386static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3387{
ee097184 3388 if (x)
d9ba4830 3389 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3390 else
d9ba4830 3391 gen_sxth(t0);
ee097184 3392 if (y)
d9ba4830 3393 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3394 else
d9ba4830
PB		 3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3397}
3398
3399/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3400static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
9ee6e8bb 3412
2ae23e75 3413 /* Mask out undefined bits. */
9ee6e8bb
PB		 3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3416 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3418 mask &= ~CPSR_IT;
9ee6e8bb 3419 /* Mask out execution state bits. */
2ae23e75 3420 if (!spsr)
e160c51c 3421 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
9ee6e8bb 3424 mask &= CPSR_USER;
b5ff1b31
FB		 3425 return mask;
3426}
3427
2fbac54b
FN		 3428/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3430{
d9ba4830 3431 TCGv tmp;
b5ff1b31
FB		 3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
d9ba4830
PB		 3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3441 store_cpu_field(tmp, spsr);
b5ff1b31 3442 } else {
2fbac54b 3443 gen_set_cpsr(t0, mask);
b5ff1b31 3444 }
2fbac54b 3445 dead_tmp(t0);
b5ff1b31
FB		 3446 gen_lookup_tb(s);
3447 return 0;
3448}
3449
2fbac54b
FN		 3450/* Returns nonzero if access to the PSR is not permitted. */
3451static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452{
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457}
3458
e9bb4aa9
JR		 3459/* Generate an old-style exception return. Marks pc as dead. */
3460static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3461{
d9ba4830 3462 TCGv tmp;
e9bb4aa9 3463 store_reg(s, 15, pc);
d9ba4830
PB		 3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
b5ff1b31
FB		 3467 s->is_jmp = DISAS_UPDATE;
3468}
3469
b0109805
PB		 3470/* Generate a v6 exception return. Marks both values as dead. */
3471static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3472{
b0109805
PB		 3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
9ee6e8bb
PB		 3476 s->is_jmp = DISAS_UPDATE;
3477}
3b46e624 3478
9ee6e8bb
PB		 3479static inline void
3480gen_set_condexec (DisasContext *s)
3481{
3482 if (s->condexec_mask) {
8f01245e
PB		 3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
d9ba4830 3486 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3487 }
3488}
3b46e624 3489
bc4a0de0
PM		 3490static void gen_exception_insn(DisasContext *s, int offset, int excp)
3491{
3492 gen_set_condexec(s);
3493 gen_set_pc_im(s->pc - offset);
3494 gen_exception(excp);
3495 s->is_jmp = DISAS_JUMP;
3496}
3497
9ee6e8bb
PB		 3498static void gen_nop_hint(DisasContext *s, int val)
3499{
3500 switch (val) {
3501 case 3: /* wfi */
8984bd2e 3502 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3503 s->is_jmp = DISAS_WFI;
3504 break;
3505 case 2: /* wfe */
3506 case 4: /* sev */
3507 /* TODO: Implement SEV and WFE. May help SMP performance. */
3508 default: /* nop */
3509 break;
3510 }
3511}
99c475ab 3512
ad69471c 3513#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3514
dd8fbd78 3515static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3516{
3517 switch (size) {
dd8fbd78
FN		 3518 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3519 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3520 case 2: tcg_gen_add_i32(t0, t0, t1); break;
9ee6e8bb
PB		 3521 default: return 1;
3522 }
3523 return 0;
3524}
3525
dd8fbd78 3526static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3527{
3528 switch (size) {
dd8fbd78
FN		 3529 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3530 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3531 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3532 default: return;
3533 }
3534}
3535
3536/* 32-bit pairwise ops end up the same as the elementwise versions. */
3537#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3538#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3539#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3540#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3541
ad69471c
PB		 3542#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3543 switch ((size << 1) | u) { \
3544 case 0: \
dd8fbd78 3545 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3546 break; \
3547 case 1: \
dd8fbd78 3548 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3549 break; \
3550 case 2: \
dd8fbd78 3551 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3552 break; \
3553 case 3: \
dd8fbd78 3554 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3555 break; \
3556 case 4: \
dd8fbd78 3557 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3558 break; \
3559 case 5: \
dd8fbd78 3560 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3561 break; \
3562 default: return 1; \
3563 }} while (0)
9ee6e8bb
PB		 3564
3565#define GEN_NEON_INTEGER_OP(name) do { \
3566 switch ((size << 1) | u) { \
ad69471c 3567 case 0: \
dd8fbd78 3568 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3569 break; \
3570 case 1: \
dd8fbd78 3571 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3572 break; \
3573 case 2: \
dd8fbd78 3574 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3575 break; \
3576 case 3: \
dd8fbd78 3577 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3578 break; \
3579 case 4: \
dd8fbd78 3580 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3581 break; \
3582 case 5: \
dd8fbd78 3583 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3584 break; \
9ee6e8bb
PB		 3585 default: return 1; \
3586 }} while (0)
3587
dd8fbd78 3588static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3589{
dd8fbd78
FN		 3590 TCGv tmp = new_tmp();
3591 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3592 return tmp;
9ee6e8bb
PB		 3593}
3594
dd8fbd78 3595static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3596{
dd8fbd78
FN		 3597 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3598 dead_tmp(var);
9ee6e8bb
PB		 3599}
3600
dd8fbd78 3601static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3602{
dd8fbd78 3603 TCGv tmp;
9ee6e8bb 3604 if (size == 1) {
0fad6efc
PM		 3605 tmp = neon_load_reg(reg & 7, reg >> 4);
3606 if (reg & 8) {
dd8fbd78 3607 gen_neon_dup_high16(tmp);
0fad6efc
PM		 3608 } else {
3609 gen_neon_dup_low16(tmp);
dd8fbd78 3610 }
0fad6efc
PM		 3611 } else {
3612 tmp = neon_load_reg(reg & 15, reg >> 4);
9ee6e8bb 3613 }
dd8fbd78 3614 return tmp;
9ee6e8bb
PB		 3615}
3616
19457615
FN		 3617static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3618{
3619 TCGv rd, rm, tmp;
3620
3621 rd = new_tmp();
3622 rm = new_tmp();
3623 tmp = new_tmp();
3624
3625 tcg_gen_andi_i32(rd, t0, 0xff);
3626 tcg_gen_shri_i32(tmp, t0, 8);
3627 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3628 tcg_gen_or_i32(rd, rd, tmp);
3629 tcg_gen_shli_i32(tmp, t1, 16);
3630 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3631 tcg_gen_or_i32(rd, rd, tmp);
3632 tcg_gen_shli_i32(tmp, t1, 8);
3633 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3634 tcg_gen_or_i32(rd, rd, tmp);
3635
3636 tcg_gen_shri_i32(rm, t0, 8);
3637 tcg_gen_andi_i32(rm, rm, 0xff);
3638 tcg_gen_shri_i32(tmp, t0, 16);
3639 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3640 tcg_gen_or_i32(rm, rm, tmp);
3641 tcg_gen_shli_i32(tmp, t1, 8);
3642 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3643 tcg_gen_or_i32(rm, rm, tmp);
3644 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3645 tcg_gen_or_i32(t1, rm, tmp);
3646 tcg_gen_mov_i32(t0, rd);
3647
3648 dead_tmp(tmp);
3649 dead_tmp(rm);
3650 dead_tmp(rd);
3651}
3652
3653static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3654{
3655 TCGv rd, rm, tmp;
3656
3657 rd = new_tmp();
3658 rm = new_tmp();
3659 tmp = new_tmp();
3660
3661 tcg_gen_andi_i32(rd, t0, 0xff);
3662 tcg_gen_shli_i32(tmp, t1, 8);
3663 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3664 tcg_gen_or_i32(rd, rd, tmp);
3665 tcg_gen_shli_i32(tmp, t0, 16);
3666 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3667 tcg_gen_or_i32(rd, rd, tmp);
3668 tcg_gen_shli_i32(tmp, t1, 24);
3669 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3670 tcg_gen_or_i32(rd, rd, tmp);
3671
3672 tcg_gen_andi_i32(rm, t1, 0xff000000);
3673 tcg_gen_shri_i32(tmp, t0, 8);
3674 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3675 tcg_gen_or_i32(rm, rm, tmp);
3676 tcg_gen_shri_i32(tmp, t1, 8);
3677 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3678 tcg_gen_or_i32(rm, rm, tmp);
3679 tcg_gen_shri_i32(tmp, t0, 16);
3680 tcg_gen_andi_i32(tmp, tmp, 0xff);
3681 tcg_gen_or_i32(t1, rm, tmp);
3682 tcg_gen_mov_i32(t0, rd);
3683
3684 dead_tmp(tmp);
3685 dead_tmp(rm);
3686 dead_tmp(rd);
3687}
3688
3689static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3690{
3691 TCGv tmp, tmp2;
3692
3693 tmp = new_tmp();
3694 tmp2 = new_tmp();
3695
3696 tcg_gen_andi_i32(tmp, t0, 0xffff);
3697 tcg_gen_shli_i32(tmp2, t1, 16);
3698 tcg_gen_or_i32(tmp, tmp, tmp2);
3699 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3700 tcg_gen_shri_i32(tmp2, t0, 16);
3701 tcg_gen_or_i32(t1, t1, tmp2);
3702 tcg_gen_mov_i32(t0, tmp);
3703
3704 dead_tmp(tmp2);
3705 dead_tmp(tmp);
3706}
3707
9ee6e8bb
PB		 3708static void gen_neon_unzip(int reg, int q, int tmp, int size)
3709{
3710 int n;
dd8fbd78 3711 TCGv t0, t1;
9ee6e8bb
PB		 3712
3713 for (n = 0; n < q + 1; n += 2) {
dd8fbd78
FN		 3714 t0 = neon_load_reg(reg, n);
3715 t1 = neon_load_reg(reg, n + 1);
9ee6e8bb 3716 switch (size) {
dd8fbd78
FN		 3717 case 0: gen_neon_unzip_u8(t0, t1); break;
3718 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
9ee6e8bb
PB		 3719 case 2: /* no-op */; break;
3720 default: abort();
3721 }
dd8fbd78
FN		 3722 neon_store_scratch(tmp + n, t0);
3723 neon_store_scratch(tmp + n + 1, t1);
9ee6e8bb
PB		 3724 }
3725}
3726
19457615
FN		 3727static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3728{
3729 TCGv rd, tmp;
3730
3731 rd = new_tmp();
3732 tmp = new_tmp();
3733
3734 tcg_gen_shli_i32(rd, t0, 8);
3735 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3736 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3737 tcg_gen_or_i32(rd, rd, tmp);
3738
3739 tcg_gen_shri_i32(t1, t1, 8);
3740 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3741 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3742 tcg_gen_or_i32(t1, t1, tmp);
3743 tcg_gen_mov_i32(t0, rd);
3744
3745 dead_tmp(tmp);
3746 dead_tmp(rd);
3747}
3748
3749static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3750{
3751 TCGv rd, tmp;
3752
3753 rd = new_tmp();
3754 tmp = new_tmp();
3755
3756 tcg_gen_shli_i32(rd, t0, 16);
3757 tcg_gen_andi_i32(tmp, t1, 0xffff);
3758 tcg_gen_or_i32(rd, rd, tmp);
3759 tcg_gen_shri_i32(t1, t1, 16);
3760 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3761 tcg_gen_or_i32(t1, t1, tmp);
3762 tcg_gen_mov_i32(t0, rd);
3763
3764 dead_tmp(tmp);
3765 dead_tmp(rd);
3766}
3767
3768
9ee6e8bb
PB		 3769static struct {
3770 int nregs;
3771 int interleave;
3772 int spacing;
3773} neon_ls_element_type[11] = {
3774 {4, 4, 1},
3775 {4, 4, 2},
3776 {4, 1, 1},
3777 {4, 2, 1},
3778 {3, 3, 1},
3779 {3, 3, 2},
3780 {3, 1, 1},
3781 {1, 1, 1},
3782 {2, 2, 1},
3783 {2, 2, 2},
3784 {2, 1, 1}
3785};
3786
3787/* Translate a NEON load/store element instruction. Return nonzero if the
3788 instruction is invalid. */
3789static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3790{
3791 int rd, rn, rm;
3792 int op;
3793 int nregs;
3794 int interleave;
84496233 3795 int spacing;
9ee6e8bb
PB		 3796 int stride;
3797 int size;
3798 int reg;
3799 int pass;
3800 int load;
3801 int shift;
9ee6e8bb 3802 int n;
1b2b1e54 3803 TCGv addr;
b0109805 3804 TCGv tmp;
8f8e3aa4 3805 TCGv tmp2;
84496233 3806 TCGv_i64 tmp64;
9ee6e8bb 3807
5df8bac1 3808 if (!s->vfp_enabled)
9ee6e8bb
PB		 3809 return 1;
3810 VFP_DREG_D(rd, insn);
3811 rn = (insn >> 16) & 0xf;
3812 rm = insn & 0xf;
3813 load = (insn & (1 << 21)) != 0;
1b2b1e54 3814 addr = new_tmp();
9ee6e8bb
PB		 3815 if ((insn & (1 << 23)) == 0) {
3816 /* Load store all elements. */
3817 op = (insn >> 8) & 0xf;
3818 size = (insn >> 6) & 3;
84496233 3819 if (op > 10)
9ee6e8bb
PB		 3820 return 1;
3821 nregs = neon_ls_element_type[op].nregs;
3822 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3823 spacing = neon_ls_element_type[op].spacing;
3824 if (size == 3 && (interleave | spacing) != 1)
3825 return 1;
dcc65026 3826 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3827 stride = (1 << size) * interleave;
3828 for (reg = 0; reg < nregs; reg++) {
3829 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3830 load_reg_var(s, addr, rn);
3831 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3832 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3833 load_reg_var(s, addr, rn);
3834 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3835 }
84496233
JR		 3836 if (size == 3) {
3837 if (load) {
3838 tmp64 = gen_ld64(addr, IS_USER(s));
3839 neon_store_reg64(tmp64, rd);
3840 tcg_temp_free_i64(tmp64);
3841 } else {
3842 tmp64 = tcg_temp_new_i64();
3843 neon_load_reg64(tmp64, rd);
3844 gen_st64(tmp64, addr, IS_USER(s));
3845 }
3846 tcg_gen_addi_i32(addr, addr, stride);
3847 } else {
3848 for (pass = 0; pass < 2; pass++) {
3849 if (size == 2) {
3850 if (load) {
3851 tmp = gen_ld32(addr, IS_USER(s));
3852 neon_store_reg(rd, pass, tmp);
3853 } else {
3854 tmp = neon_load_reg(rd, pass);
3855 gen_st32(tmp, addr, IS_USER(s));
3856 }
1b2b1e54 3857 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3858 } else if (size == 1) {
3859 if (load) {
3860 tmp = gen_ld16u(addr, IS_USER(s));
3861 tcg_gen_addi_i32(addr, addr, stride);
3862 tmp2 = gen_ld16u(addr, IS_USER(s));
3863 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3864 tcg_gen_shli_i32(tmp2, tmp2, 16);
3865 tcg_gen_or_i32(tmp, tmp, tmp2);
84496233
JR		 3866 dead_tmp(tmp2);
3867 neon_store_reg(rd, pass, tmp);
3868 } else {
3869 tmp = neon_load_reg(rd, pass);
3870 tmp2 = new_tmp();
3871 tcg_gen_shri_i32(tmp2, tmp, 16);
3872 gen_st16(tmp, addr, IS_USER(s));
3873 tcg_gen_addi_i32(addr, addr, stride);
3874 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3875 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3876 }
84496233
JR		 3877 } else /* size == 0 */ {
3878 if (load) {
3879 TCGV_UNUSED(tmp2);
3880 for (n = 0; n < 4; n++) {
3881 tmp = gen_ld8u(addr, IS_USER(s));
3882 tcg_gen_addi_i32(addr, addr, stride);
3883 if (n == 0) {
3884 tmp2 = tmp;
3885 } else {
41ba8341
PB		 3886 tcg_gen_shli_i32(tmp, tmp, n * 8);
3887 tcg_gen_or_i32(tmp2, tmp2, tmp);
84496233
JR		 3888 dead_tmp(tmp);
3889 }
9ee6e8bb 3890 }
84496233
JR		 3891 neon_store_reg(rd, pass, tmp2);
3892 } else {
3893 tmp2 = neon_load_reg(rd, pass);
3894 for (n = 0; n < 4; n++) {
3895 tmp = new_tmp();
3896 if (n == 0) {
3897 tcg_gen_mov_i32(tmp, tmp2);
3898 } else {
3899 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3900 }
3901 gen_st8(tmp, addr, IS_USER(s));
3902 tcg_gen_addi_i32(addr, addr, stride);
3903 }
3904 dead_tmp(tmp2);
9ee6e8bb
PB		 3905 }
3906 }
3907 }
3908 }
84496233 3909 rd += spacing;
9ee6e8bb
PB		 3910 }
3911 stride = nregs * 8;
3912 } else {
3913 size = (insn >> 10) & 3;
3914 if (size == 3) {
3915 /* Load single element to all lanes. */
3916 if (!load)
3917 return 1;
3918 size = (insn >> 6) & 3;
3919 nregs = ((insn >> 8) & 3) + 1;
3920 stride = (insn & (1 << 5)) ? 2 : 1;
dcc65026 3921 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3922 for (reg = 0; reg < nregs; reg++) {
3923 switch (size) {
3924 case 0:
1b2b1e54 3925 tmp = gen_ld8u(addr, IS_USER(s));
ad69471c 3926 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3927 break;
3928 case 1:
1b2b1e54 3929 tmp = gen_ld16u(addr, IS_USER(s));
ad69471c 3930 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3931 break;
3932 case 2:
1b2b1e54 3933 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 3934 break;
3935 case 3:
3936 return 1;
a50f5b91
PB		 3937 default: /* Avoid compiler warnings. */
3938 abort();
99c475ab 3939 }
1b2b1e54 3940 tcg_gen_addi_i32(addr, addr, 1 << size);
ad69471c
PB		 3941 tmp2 = new_tmp();
3942 tcg_gen_mov_i32(tmp2, tmp);
3943 neon_store_reg(rd, 0, tmp2);
3018f259 3944 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 3945 rd += stride;
3946 }
3947 stride = (1 << size) * nregs;
3948 } else {
3949 /* Single element. */
3950 pass = (insn >> 7) & 1;
3951 switch (size) {
3952 case 0:
3953 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3954 stride = 1;
3955 break;
3956 case 1:
3957 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3958 stride = (insn & (1 << 5)) ? 2 : 1;
3959 break;
3960 case 2:
3961 shift = 0;
9ee6e8bb
PB		 3962 stride = (insn & (1 << 6)) ? 2 : 1;
3963 break;
3964 default:
3965 abort();
3966 }
3967 nregs = ((insn >> 8) & 3) + 1;
dcc65026 3968 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3969 for (reg = 0; reg < nregs; reg++) {
3970 if (load) {
9ee6e8bb
PB		 3971 switch (size) {
3972 case 0:
1b2b1e54 3973 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 3974 break;
3975 case 1:
1b2b1e54 3976 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 3977 break;
3978 case 2:
1b2b1e54 3979 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 3980 break;
a50f5b91
PB		 3981 default: /* Avoid compiler warnings. */
3982 abort();
9ee6e8bb
PB		 3983 }
3984 if (size != 2) {
8f8e3aa4
PB		 3985 tmp2 = neon_load_reg(rd, pass);
3986 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3987 dead_tmp(tmp2);
9ee6e8bb 3988 }
8f8e3aa4 3989 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3990 } else { /* Store */
8f8e3aa4
PB		 3991 tmp = neon_load_reg(rd, pass);
3992 if (shift)
3993 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3994 switch (size) {
3995 case 0:
1b2b1e54 3996 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3997 break;
3998 case 1:
1b2b1e54 3999 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 4000 break;
4001 case 2:
1b2b1e54 4002 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 4003 break;
99c475ab 4004 }
99c475ab 4005 }
9ee6e8bb 4006 rd += stride;
1b2b1e54 4007 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 4008 }
9ee6e8bb 4009 stride = nregs * (1 << size);
99c475ab 4010 }
9ee6e8bb 4011 }
1b2b1e54 4012 dead_tmp(addr);
9ee6e8bb 4013 if (rm != 15) {
b26eefb6
PB		 4014 TCGv base;
4015
4016 base = load_reg(s, rn);
9ee6e8bb 4017 if (rm == 13) {
b26eefb6 4018 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4019 } else {
b26eefb6
PB		 4020 TCGv index;
4021 index = load_reg(s, rm);
4022 tcg_gen_add_i32(base, base, index);
4023 dead_tmp(index);
9ee6e8bb 4024 }
b26eefb6 4025 store_reg(s, rn, base);
9ee6e8bb
PB		 4026 }
4027 return 0;
4028}
3b46e624 4029
8f8e3aa4
PB		 4030/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4031static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4032{
4033 tcg_gen_and_i32(t, t, c);
f669df27 4034 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4035 tcg_gen_or_i32(dest, t, f);
4036}
4037
a7812ae4 4038static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4039{
4040 switch (size) {
4041 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4042 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4043 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4044 default: abort();
4045 }
4046}
4047
a7812ae4 4048static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4049{
4050 switch (size) {
4051 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4052 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4053 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4054 default: abort();
4055 }
4056}
4057
a7812ae4 4058static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4059{
4060 switch (size) {
4061 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4062 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4063 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4064 default: abort();
4065 }
4066}
4067
4068static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4069 int q, int u)
4070{
4071 if (q) {
4072 if (u) {
4073 switch (size) {
4074 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4075 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4076 default: abort();
4077 }
4078 } else {
4079 switch (size) {
4080 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4081 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4082 default: abort();
4083 }
4084 }
4085 } else {
4086 if (u) {
4087 switch (size) {
4088 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4089 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4090 default: abort();
4091 }
4092 } else {
4093 switch (size) {
4094 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4095 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4096 default: abort();
4097 }
4098 }
4099 }
4100}
4101
a7812ae4 4102static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4103{
4104 if (u) {
4105 switch (size) {
4106 case 0: gen_helper_neon_widen_u8(dest, src); break;
4107 case 1: gen_helper_neon_widen_u16(dest, src); break;
4108 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4109 default: abort();
4110 }
4111 } else {
4112 switch (size) {
4113 case 0: gen_helper_neon_widen_s8(dest, src); break;
4114 case 1: gen_helper_neon_widen_s16(dest, src); break;
4115 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4116 default: abort();
4117 }
4118 }
4119 dead_tmp(src);
4120}
4121
4122static inline void gen_neon_addl(int size)
4123{
4124 switch (size) {
4125 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4126 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4127 case 2: tcg_gen_add_i64(CPU_V001); break;
4128 default: abort();
4129 }
4130}
4131
4132static inline void gen_neon_subl(int size)
4133{
4134 switch (size) {
4135 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4136 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4137 case 2: tcg_gen_sub_i64(CPU_V001); break;
4138 default: abort();
4139 }
4140}
4141
a7812ae4 4142static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4143{
4144 switch (size) {
4145 case 0: gen_helper_neon_negl_u16(var, var); break;
4146 case 1: gen_helper_neon_negl_u32(var, var); break;
4147 case 2: gen_helper_neon_negl_u64(var, var); break;
4148 default: abort();
4149 }
4150}
4151
a7812ae4 4152static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4153{
4154 switch (size) {
4155 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4156 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4157 default: abort();
4158 }
4159}
4160
a7812ae4 4161static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4162{
a7812ae4 4163 TCGv_i64 tmp;
ad69471c
PB		 4164
4165 switch ((size << 1) | u) {
4166 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4167 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4168 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4169 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4170 case 4:
4171 tmp = gen_muls_i64_i32(a, b);
4172 tcg_gen_mov_i64(dest, tmp);
4173 break;
4174 case 5:
4175 tmp = gen_mulu_i64_i32(a, b);
4176 tcg_gen_mov_i64(dest, tmp);
4177 break;
4178 default: abort();
4179 }
c6067f04
CL		 4180
4181 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4182 Don't forget to clean them now. */
4183 if (size < 2) {
4184 dead_tmp(a);
4185 dead_tmp(b);
4186 }
ad69471c
PB		 4187}
4188
9ee6e8bb
PB		 4189/* Translate a NEON data processing instruction. Return nonzero if the
4190 instruction is invalid.
ad69471c
PB		 4191 We process data in a mixture of 32-bit and 64-bit chunks.
4192 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4193
9ee6e8bb
PB		 4194static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4195{
4196 int op;
4197 int q;
4198 int rd, rn, rm;
4199 int size;
4200 int shift;
4201 int pass;
4202 int count;
4203 int pairwise;
4204 int u;
4205 int n;
ca9a32e4 4206 uint32_t imm, mask;
b75263d6 4207 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4208 TCGv_i64 tmp64;
9ee6e8bb 4209
5df8bac1 4210 if (!s->vfp_enabled)
9ee6e8bb
PB		 4211 return 1;
4212 q = (insn & (1 << 6)) != 0;
4213 u = (insn >> 24) & 1;
4214 VFP_DREG_D(rd, insn);
4215 VFP_DREG_N(rn, insn);
4216 VFP_DREG_M(rm, insn);
4217 size = (insn >> 20) & 3;
4218 if ((insn & (1 << 23)) == 0) {
4219 /* Three register same length. */
4220 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4221 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4222 || op == 10 || op == 11 || op == 16)) {
4223 /* 64-bit element instructions. */
9ee6e8bb 4224 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4225 neon_load_reg64(cpu_V0, rn + pass);
4226 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4227 switch (op) {
4228 case 1: /* VQADD */
4229 if (u) {
72902672
CL		 4230 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4231 cpu_V0, cpu_V1);
2c0262af 4232 } else {
72902672
CL		 4233 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4234 cpu_V0, cpu_V1);
2c0262af 4235 }
9ee6e8bb
PB		 4236 break;
4237 case 5: /* VQSUB */
4238 if (u) {
72902672
CL		 4239 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4240 cpu_V0, cpu_V1);
ad69471c 4241 } else {
72902672
CL		 4242 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4243 cpu_V0, cpu_V1);
ad69471c
PB		 4244 }
4245 break;
4246 case 8: /* VSHL */
4247 if (u) {
4248 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4249 } else {
4250 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4251 }
4252 break;
4253 case 9: /* VQSHL */
4254 if (u) {
4255 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
def126ce 4256 cpu_V1, cpu_V0);
ad69471c 4257 } else {
def126ce 4258 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
ad69471c
PB		 4259 cpu_V1, cpu_V0);
4260 }
4261 break;
4262 case 10: /* VRSHL */
4263 if (u) {
4264 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4265 } else {
ad69471c
PB		 4266 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4267 }
4268 break;
4269 case 11: /* VQRSHL */
4270 if (u) {
4271 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4272 cpu_V1, cpu_V0);
4273 } else {
4274 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4275 cpu_V1, cpu_V0);
1e8d4eec 4276 }
9ee6e8bb
PB		 4277 break;
4278 case 16:
4279 if (u) {
ad69471c 4280 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4281 } else {
ad69471c 4282 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4283 }
4284 break;
4285 default:
4286 abort();
2c0262af 4287 }
ad69471c 4288 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4289 }
9ee6e8bb 4290 return 0;
2c0262af 4291 }
9ee6e8bb
PB		 4292 switch (op) {
4293 case 8: /* VSHL */
4294 case 9: /* VQSHL */
4295 case 10: /* VRSHL */
ad69471c 4296 case 11: /* VQRSHL */
9ee6e8bb 4297 {
ad69471c
PB		 4298 int rtmp;
4299 /* Shift instruction operands are reversed. */
4300 rtmp = rn;
9ee6e8bb 4301 rn = rm;
ad69471c 4302 rm = rtmp;
9ee6e8bb
PB		 4303 pairwise = 0;
4304 }
2c0262af 4305 break;
9ee6e8bb
PB		 4306 case 20: /* VPMAX */
4307 case 21: /* VPMIN */
4308 case 23: /* VPADD */
4309 pairwise = 1;
2c0262af 4310 break;
9ee6e8bb
PB		 4311 case 26: /* VPADD (float) */
4312 pairwise = (u && size < 2);
2c0262af 4313 break;
9ee6e8bb
PB		 4314 case 30: /* VPMIN/VPMAX (float) */
4315 pairwise = u;
2c0262af 4316 break;
9ee6e8bb
PB		 4317 default:
4318 pairwise = 0;
2c0262af 4319 break;
9ee6e8bb 4320 }
dd8fbd78 4321
9ee6e8bb
PB		 4322 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4323
4324 if (pairwise) {
4325 /* Pairwise. */
4326 if (q)
4327 n = (pass & 1) * 2;
2c0262af 4328 else
9ee6e8bb
PB		 4329 n = 0;
4330 if (pass < q + 1) {
dd8fbd78
FN		 4331 tmp = neon_load_reg(rn, n);
4332 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4333 } else {
dd8fbd78
FN		 4334 tmp = neon_load_reg(rm, n);
4335 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4336 }
4337 } else {
4338 /* Elementwise. */
dd8fbd78
FN		 4339 tmp = neon_load_reg(rn, pass);
4340 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4341 }
4342 switch (op) {
4343 case 0: /* VHADD */
4344 GEN_NEON_INTEGER_OP(hadd);
4345 break;
4346 case 1: /* VQADD */
ad69471c 4347 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4348 break;
9ee6e8bb
PB		 4349 case 2: /* VRHADD */
4350 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4351 break;
9ee6e8bb
PB		 4352 case 3: /* Logic ops. */
4353 switch ((u << 2) | size) {
4354 case 0: /* VAND */
dd8fbd78 4355 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4356 break;
4357 case 1: /* BIC */
f669df27 4358 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4359 break;
4360 case 2: /* VORR */
dd8fbd78 4361 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4362 break;
4363 case 3: /* VORN */
f669df27 4364 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4365 break;
4366 case 4: /* VEOR */
dd8fbd78 4367 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4368 break;
4369 case 5: /* VBSL */
dd8fbd78
FN		 4370 tmp3 = neon_load_reg(rd, pass);
4371 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4372 dead_tmp(tmp3);
9ee6e8bb
PB		 4373 break;
4374 case 6: /* VBIT */
dd8fbd78
FN		 4375 tmp3 = neon_load_reg(rd, pass);
4376 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4377 dead_tmp(tmp3);
9ee6e8bb
PB		 4378 break;
4379 case 7: /* VBIF */
dd8fbd78
FN		 4380 tmp3 = neon_load_reg(rd, pass);
4381 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4382 dead_tmp(tmp3);
9ee6e8bb 4383 break;
2c0262af
FB		 4384 }
4385 break;
9ee6e8bb
PB		 4386 case 4: /* VHSUB */
4387 GEN_NEON_INTEGER_OP(hsub);
4388 break;
4389 case 5: /* VQSUB */
ad69471c 4390 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4391 break;
9ee6e8bb
PB		 4392 case 6: /* VCGT */
4393 GEN_NEON_INTEGER_OP(cgt);
4394 break;
4395 case 7: /* VCGE */
4396 GEN_NEON_INTEGER_OP(cge);
4397 break;
4398 case 8: /* VSHL */
ad69471c 4399 GEN_NEON_INTEGER_OP(shl);
2c0262af 4400 break;
9ee6e8bb 4401 case 9: /* VQSHL */
ad69471c 4402 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4403 break;
9ee6e8bb 4404 case 10: /* VRSHL */
ad69471c 4405 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4406 break;
9ee6e8bb 4407 case 11: /* VQRSHL */
ad69471c 4408 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4409 break;
4410 case 12: /* VMAX */
4411 GEN_NEON_INTEGER_OP(max);
4412 break;
4413 case 13: /* VMIN */
4414 GEN_NEON_INTEGER_OP(min);
4415 break;
4416 case 14: /* VABD */
4417 GEN_NEON_INTEGER_OP(abd);
4418 break;
4419 case 15: /* VABA */
4420 GEN_NEON_INTEGER_OP(abd);
dd8fbd78
FN		 4421 dead_tmp(tmp2);
4422 tmp2 = neon_load_reg(rd, pass);
4423 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4424 break;
4425 case 16:
4426 if (!u) { /* VADD */
dd8fbd78 4427 if (gen_neon_add(size, tmp, tmp2))
9ee6e8bb
PB		 4428 return 1;
4429 } else { /* VSUB */
4430 switch (size) {
dd8fbd78
FN		 4431 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4432 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4433 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4434 default: return 1;
4435 }
4436 }
4437 break;
4438 case 17:
4439 if (!u) { /* VTST */
4440 switch (size) {
dd8fbd78
FN		 4441 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4442 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4443 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4444 default: return 1;
4445 }
4446 } else { /* VCEQ */
4447 switch (size) {
dd8fbd78
FN		 4448 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4449 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4450 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4451 default: return 1;
4452 }
4453 }
4454 break;
4455 case 18: /* Multiply. */
4456 switch (size) {
dd8fbd78
FN		 4457 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4458 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4459 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4460 default: return 1;
4461 }
dd8fbd78
FN		 4462 dead_tmp(tmp2);
4463 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4464 if (u) { /* VMLS */
dd8fbd78 4465 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4466 } else { /* VMLA */
dd8fbd78 4467 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4468 }
4469 break;
4470 case 19: /* VMUL */
4471 if (u) { /* polynomial */
dd8fbd78 4472 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4473 } else { /* Integer */
4474 switch (size) {
dd8fbd78
FN		 4475 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4476 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4477 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4478 default: return 1;
4479 }
4480 }
4481 break;
4482 case 20: /* VPMAX */
4483 GEN_NEON_INTEGER_OP(pmax);
4484 break;
4485 case 21: /* VPMIN */
4486 GEN_NEON_INTEGER_OP(pmin);
4487 break;
4488 case 22: /* Hultiply high. */
4489 if (!u) { /* VQDMULH */
4490 switch (size) {
dd8fbd78
FN		 4491 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4492 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4493 default: return 1;
4494 }
4495 } else { /* VQRDHMUL */
4496 switch (size) {
dd8fbd78
FN		 4497 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4498 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4499 default: return 1;
4500 }
4501 }
4502 break;
4503 case 23: /* VPADD */
4504 if (u)
4505 return 1;
4506 switch (size) {
dd8fbd78
FN		 4507 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4508 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4509 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4510 default: return 1;
4511 }
4512 break;
4513 case 26: /* Floating point arithnetic. */
4514 switch ((u << 2) | size) {
4515 case 0: /* VADD */
dd8fbd78 4516 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4517 break;
4518 case 2: /* VSUB */
dd8fbd78 4519 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4520 break;
4521 case 4: /* VPADD */
dd8fbd78 4522 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4523 break;
4524 case 6: /* VABD */
dd8fbd78 4525 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4526 break;
4527 default:
4528 return 1;
4529 }
4530 break;
4531 case 27: /* Float multiply. */
dd8fbd78 4532 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4533 if (!u) {
dd8fbd78
FN		 4534 dead_tmp(tmp2);
4535 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4536 if (size == 0) {
dd8fbd78 4537 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4538 } else {
dd8fbd78 4539 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4540 }
4541 }
4542 break;
4543 case 28: /* Float compare. */
4544 if (!u) {
dd8fbd78 4545 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4546 } else {
9ee6e8bb 4547 if (size == 0)
dd8fbd78 4548 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4549 else
dd8fbd78 4550 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4551 }
2c0262af 4552 break;
9ee6e8bb
PB		 4553 case 29: /* Float compare absolute. */
4554 if (!u)
4555 return 1;
4556 if (size == 0)
dd8fbd78 4557 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4558 else
dd8fbd78 4559 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4560 break;
9ee6e8bb
PB		 4561 case 30: /* Float min/max. */
4562 if (size == 0)
dd8fbd78 4563 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4564 else
dd8fbd78 4565 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4566 break;
4567 case 31:
4568 if (size == 0)
dd8fbd78 4569 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4570 else
dd8fbd78 4571 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4572 break;
9ee6e8bb
PB		 4573 default:
4574 abort();
2c0262af 4575 }
dd8fbd78
FN		 4576 dead_tmp(tmp2);
4577
9ee6e8bb
PB		 4578 /* Save the result. For elementwise operations we can put it
4579 straight into the destination register. For pairwise operations
4580 we have to be careful to avoid clobbering the source operands. */
4581 if (pairwise && rd == rm) {
dd8fbd78 4582 neon_store_scratch(pass, tmp);
9ee6e8bb 4583 } else {
dd8fbd78 4584 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4585 }
4586
4587 } /* for pass */
4588 if (pairwise && rd == rm) {
4589 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4590 tmp = neon_load_scratch(pass);
4591 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4592 }
4593 }
ad69471c 4594 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4595 } else if (insn & (1 << 4)) {
4596 if ((insn & 0x00380080) != 0) {
4597 /* Two registers and shift. */
4598 op = (insn >> 8) & 0xf;
4599 if (insn & (1 << 7)) {
4600 /* 64-bit shift. */
4601 size = 3;
4602 } else {
4603 size = 2;
4604 while ((insn & (1 << (size + 19))) == 0)
4605 size--;
4606 }
4607 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4608 /* To avoid excessive dumplication of ops we implement shift
4609 by immediate using the variable shift operations. */
4610 if (op < 8) {
4611 /* Shift by immediate:
4612 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4613 /* Right shifts are encoded as N - shift, where N is the
4614 element size in bits. */
4615 if (op <= 4)
4616 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4617 if (size == 3) {
4618 count = q + 1;
4619 } else {
4620 count = q ? 4: 2;
4621 }
4622 switch (size) {
4623 case 0:
4624 imm = (uint8_t) shift;
4625 imm |= imm << 8;
4626 imm |= imm << 16;
4627 break;
4628 case 1:
4629 imm = (uint16_t) shift;
4630 imm |= imm << 16;
4631 break;
4632 case 2:
4633 case 3:
4634 imm = shift;
4635 break;
4636 default:
4637 abort();
4638 }
4639
4640 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4641 if (size == 3) {
4642 neon_load_reg64(cpu_V0, rm + pass);
4643 tcg_gen_movi_i64(cpu_V1, imm);
4644 switch (op) {
4645 case 0: /* VSHR */
4646 case 1: /* VSRA */
4647 if (u)
4648 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4649 else
ad69471c 4650 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4651 break;
ad69471c
PB		 4652 case 2: /* VRSHR */
4653 case 3: /* VRSRA */
4654 if (u)
4655 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4656 else
ad69471c 4657 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4658 break;
ad69471c
PB		 4659 case 4: /* VSRI */
4660 if (!u)
4661 return 1;
4662 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4663 break;
4664 case 5: /* VSHL, VSLI */
4665 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4666 break;
0322b26e
PM		 4667 case 6: /* VQSHLU */
4668 if (u) {
4669 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4670 cpu_V0, cpu_V1);
4671 } else {
4672 return 1;
4673 }
ad69471c 4674 break;
0322b26e
PM		 4675 case 7: /* VQSHL */
4676 if (u) {
4677 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4678 cpu_V0, cpu_V1);
4679 } else {
4680 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4681 cpu_V0, cpu_V1);
4682 }
9ee6e8bb 4683 break;
9ee6e8bb 4684 }
ad69471c
PB		 4685 if (op == 1 || op == 3) {
4686 /* Accumulate. */
5371cb81 4687 neon_load_reg64(cpu_V1, rd + pass);
ad69471c
PB		 4688 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4689 } else if (op == 4 || (op == 5 && u)) {
4690 /* Insert */
4691 cpu_abort(env, "VS[LR]I.64 not implemented");
4692 }
4693 neon_store_reg64(cpu_V0, rd + pass);
4694 } else { /* size < 3 */
4695 /* Operands in T0 and T1. */
dd8fbd78
FN		 4696 tmp = neon_load_reg(rm, pass);
4697 tmp2 = new_tmp();
4698 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4699 switch (op) {
4700 case 0: /* VSHR */
4701 case 1: /* VSRA */
4702 GEN_NEON_INTEGER_OP(shl);
4703 break;
4704 case 2: /* VRSHR */
4705 case 3: /* VRSRA */
4706 GEN_NEON_INTEGER_OP(rshl);
4707 break;
4708 case 4: /* VSRI */
4709 if (!u)
4710 return 1;
4711 GEN_NEON_INTEGER_OP(shl);
4712 break;
4713 case 5: /* VSHL, VSLI */
4714 switch (size) {
dd8fbd78
FN		 4715 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4716 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4717 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4718 default: return 1;
4719 }
4720 break;
0322b26e
PM		 4721 case 6: /* VQSHLU */
4722 if (!u) {
4723 return 1;
4724 }
ad69471c 4725 switch (size) {
0322b26e
PM		 4726 case 0:
4727 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4728 tmp, tmp2);
4729 break;
4730 case 1:
4731 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4732 tmp, tmp2);
4733 break;
4734 case 2:
4735 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4736 tmp, tmp2);
4737 break;
4738 default:
4739 return 1;
ad69471c
PB		 4740 }
4741 break;
0322b26e
PM		 4742 case 7: /* VQSHL */
4743 GEN_NEON_INTEGER_OP_ENV(qshl);
4744 break;
ad69471c 4745 }
dd8fbd78 4746 dead_tmp(tmp2);
ad69471c
PB		 4747
4748 if (op == 1 || op == 3) {
4749 /* Accumulate. */
dd8fbd78 4750 tmp2 = neon_load_reg(rd, pass);
5371cb81 4751 gen_neon_add(size, tmp, tmp2);
dd8fbd78 4752 dead_tmp(tmp2);
ad69471c
PB		 4753 } else if (op == 4 || (op == 5 && u)) {
4754 /* Insert */
4755 switch (size) {
4756 case 0:
4757 if (op == 4)
ca9a32e4 4758 mask = 0xff >> -shift;
ad69471c 4759 else
ca9a32e4
JR		 4760 mask = (uint8_t)(0xff << shift);
4761 mask |= mask << 8;
4762 mask |= mask << 16;
ad69471c
PB		 4763 break;
4764 case 1:
4765 if (op == 4)
ca9a32e4 4766 mask = 0xffff >> -shift;
ad69471c 4767 else
ca9a32e4
JR		 4768 mask = (uint16_t)(0xffff << shift);
4769 mask |= mask << 16;
ad69471c
PB		 4770 break;
4771 case 2:
ca9a32e4
JR		 4772 if (shift < -31 || shift > 31) {
4773 mask = 0;
4774 } else {
4775 if (op == 4)
4776 mask = 0xffffffffu >> -shift;
4777 else
4778 mask = 0xffffffffu << shift;
4779 }
ad69471c
PB		 4780 break;
4781 default:
4782 abort();
4783 }
dd8fbd78 4784 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4785 tcg_gen_andi_i32(tmp, tmp, mask);
4786 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78
FN		 4787 tcg_gen_or_i32(tmp, tmp, tmp2);
4788 dead_tmp(tmp2);
ad69471c 4789 }
dd8fbd78 4790 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4791 }
4792 } /* for pass */
4793 } else if (op < 10) {
ad69471c 4794 /* Shift by immediate and narrow:
9ee6e8bb
PB		 4795 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4796 shift = shift - (1 << (size + 3));
4797 size++;
9ee6e8bb
PB		 4798 switch (size) {
4799 case 1:
ad69471c 4800 imm = (uint16_t)shift;
9ee6e8bb 4801 imm |= imm << 16;
ad69471c 4802 tmp2 = tcg_const_i32(imm);
a7812ae4 4803 TCGV_UNUSED_I64(tmp64);
9ee6e8bb
PB		 4804 break;
4805 case 2:
ad69471c
PB		 4806 imm = (uint32_t)shift;
4807 tmp2 = tcg_const_i32(imm);
a7812ae4 4808 TCGV_UNUSED_I64(tmp64);
4cc633c3 4809 break;
9ee6e8bb 4810 case 3:
a7812ae4
PB		 4811 tmp64 = tcg_const_i64(shift);
4812 TCGV_UNUSED(tmp2);
9ee6e8bb
PB		 4813 break;
4814 default:
4815 abort();
4816 }
4817
ad69471c
PB		 4818 for (pass = 0; pass < 2; pass++) {
4819 if (size == 3) {
4820 neon_load_reg64(cpu_V0, rm + pass);
4821 if (q) {
4822 if (u)
a7812ae4 4823 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4824 else
a7812ae4 4825 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c
PB		 4826 } else {
4827 if (u)
a7812ae4 4828 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4829 else
a7812ae4 4830 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c 4831 }
2c0262af 4832 } else {
ad69471c
PB		 4833 tmp = neon_load_reg(rm + pass, 0);
4834 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
36aa55dc
PB		 4835 tmp3 = neon_load_reg(rm + pass, 1);
4836 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4837 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
ad69471c 4838 dead_tmp(tmp);
36aa55dc 4839 dead_tmp(tmp3);
9ee6e8bb 4840 }
ad69471c
PB		 4841 tmp = new_tmp();
4842 if (op == 8 && !u) {
4843 gen_neon_narrow(size - 1, tmp, cpu_V0);
9ee6e8bb 4844 } else {
ad69471c
PB		 4845 if (op == 8)
4846 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
9ee6e8bb 4847 else
ad69471c
PB		 4848 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4849 }
2301db49 4850 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4851 } /* for pass */
b75263d6
JR		 4852 if (size == 3) {
4853 tcg_temp_free_i64(tmp64);
2301db49 4854 } else {
c6067f04 4855 tcg_temp_free_i32(tmp2);
b75263d6 4856 }
9ee6e8bb
PB		 4857 } else if (op == 10) {
4858 /* VSHLL */
ad69471c 4859 if (q || size == 3)
9ee6e8bb 4860 return 1;
ad69471c
PB		 4861 tmp = neon_load_reg(rm, 0);
4862 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4863 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4864 if (pass == 1)
4865 tmp = tmp2;
4866
4867 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4868
9ee6e8bb
PB		 4869 if (shift != 0) {
4870 /* The shift is less than the width of the source
ad69471c
PB		 4871 type, so we can just shift the whole register. */
4872 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4873 if (size < 2 || !u) {
4874 uint64_t imm64;
4875 if (size == 0) {
4876 imm = (0xffu >> (8 - shift));
4877 imm |= imm << 16;
4878 } else {
4879 imm = 0xffff >> (16 - shift);
9ee6e8bb 4880 }
ad69471c
PB		 4881 imm64 = imm | (((uint64_t)imm) << 32);
4882 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
9ee6e8bb
PB		 4883 }
4884 }
ad69471c 4885 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 4886 }
f73534a5 4887 } else if (op >= 14) {
9ee6e8bb 4888 /* VCVT fixed-point. */
f73534a5
PM		 4889 /* We have already masked out the must-be-1 top bit of imm6,
4890 * hence this 32-shift where the ARM ARM has 64-imm6.
4891 */
4892 shift = 32 - shift;
9ee6e8bb 4893 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4894 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
f73534a5 4895 if (!(op & 1)) {
9ee6e8bb 4896 if (u)
4373f3ce 4897 gen_vfp_ulto(0, shift);
9ee6e8bb 4898 else
4373f3ce 4899 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4900 } else {
4901 if (u)
4373f3ce 4902 gen_vfp_toul(0, shift);
9ee6e8bb 4903 else
4373f3ce 4904 gen_vfp_tosl(0, shift);
2c0262af 4905 }
4373f3ce 4906 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4907 }
4908 } else {
9ee6e8bb
PB		 4909 return 1;
4910 }
4911 } else { /* (insn & 0x00380080) == 0 */
4912 int invert;
4913
4914 op = (insn >> 8) & 0xf;
4915 /* One register and immediate. */
4916 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4917 invert = (insn & (1 << 5)) != 0;
4918 switch (op) {
4919 case 0: case 1:
4920 /* no-op */
4921 break;
4922 case 2: case 3:
4923 imm <<= 8;
4924 break;
4925 case 4: case 5:
4926 imm <<= 16;
4927 break;
4928 case 6: case 7:
4929 imm <<= 24;
4930 break;
4931 case 8: case 9:
4932 imm |= imm << 16;
4933 break;
4934 case 10: case 11:
4935 imm = (imm << 8) | (imm << 24);
4936 break;
4937 case 12:
8e31209e 4938 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 4939 break;
4940 case 13:
4941 imm = (imm << 16) | 0xffff;
4942 break;
4943 case 14:
4944 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4945 if (invert)
4946 imm = ~imm;
4947 break;
4948 case 15:
4949 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4950 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4951 break;
4952 }
4953 if (invert)
4954 imm = ~imm;
4955
9ee6e8bb
PB		 4956 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4957 if (op & 1 && op < 12) {
ad69471c 4958 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4959 if (invert) {
4960 /* The immediate value has already been inverted, so
4961 BIC becomes AND. */
ad69471c 4962 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 4963 } else {
ad69471c 4964 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 4965 }
9ee6e8bb 4966 } else {
ad69471c
PB		 4967 /* VMOV, VMVN. */
4968 tmp = new_tmp();
9ee6e8bb 4969 if (op == 14 && invert) {
ad69471c
PB		 4970 uint32_t val;
4971 val = 0;
9ee6e8bb
PB		 4972 for (n = 0; n < 4; n++) {
4973 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 4974 val |= 0xff << (n * 8);
9ee6e8bb 4975 }
ad69471c
PB		 4976 tcg_gen_movi_i32(tmp, val);
4977 } else {
4978 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 4979 }
9ee6e8bb 4980 }
ad69471c 4981 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4982 }
4983 }
e4b3861d 4984 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 4985 if (size != 3) {
4986 op = (insn >> 8) & 0xf;
4987 if ((insn & (1 << 6)) == 0) {
4988 /* Three registers of different lengths. */
4989 int src1_wide;
4990 int src2_wide;
4991 int prewiden;
4992 /* prewiden, src1_wide, src2_wide */
4993 static const int neon_3reg_wide[16][3] = {
4994 {1, 0, 0}, /* VADDL */
4995 {1, 1, 0}, /* VADDW */
4996 {1, 0, 0}, /* VSUBL */
4997 {1, 1, 0}, /* VSUBW */
4998 {0, 1, 1}, /* VADDHN */
4999 {0, 0, 0}, /* VABAL */
5000 {0, 1, 1}, /* VSUBHN */
5001 {0, 0, 0}, /* VABDL */
5002 {0, 0, 0}, /* VMLAL */
5003 {0, 0, 0}, /* VQDMLAL */
5004 {0, 0, 0}, /* VMLSL */
5005 {0, 0, 0}, /* VQDMLSL */
5006 {0, 0, 0}, /* Integer VMULL */
5007 {0, 0, 0}, /* VQDMULL */
5008 {0, 0, 0} /* Polynomial VMULL */
5009 };
5010
5011 prewiden = neon_3reg_wide[op][0];
5012 src1_wide = neon_3reg_wide[op][1];
5013 src2_wide = neon_3reg_wide[op][2];
5014
ad69471c
PB		 5015 if (size == 0 && (op == 9 || op == 11 || op == 13))
5016 return 1;
5017
9ee6e8bb
PB		 5018 /* Avoid overlapping operands. Wide source operands are
5019 always aligned so will never overlap with wide
5020 destinations in problematic ways. */
8f8e3aa4 5021 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 5022 tmp = neon_load_reg(rm, 1);
5023 neon_store_scratch(2, tmp);
8f8e3aa4 5024 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 5025 tmp = neon_load_reg(rn, 1);
5026 neon_store_scratch(2, tmp);
9ee6e8bb 5027 }
a50f5b91 5028 TCGV_UNUSED(tmp3);
9ee6e8bb 5029 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5030 if (src1_wide) {
5031 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 5032 TCGV_UNUSED(tmp);
9ee6e8bb 5033 } else {
ad69471c 5034 if (pass == 1 && rd == rn) {
dd8fbd78 5035 tmp = neon_load_scratch(2);
9ee6e8bb 5036 } else {
ad69471c
PB		 5037 tmp = neon_load_reg(rn, pass);
5038 }
5039 if (prewiden) {
5040 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 5041 }
5042 }
ad69471c
PB		 5043 if (src2_wide) {
5044 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5045 TCGV_UNUSED(tmp2);
9ee6e8bb 5046 } else {
ad69471c 5047 if (pass == 1 && rd == rm) {
dd8fbd78 5048 tmp2 = neon_load_scratch(2);
9ee6e8bb 5049 } else {
ad69471c
PB		 5050 tmp2 = neon_load_reg(rm, pass);
5051 }
5052 if (prewiden) {
5053 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5054 }
9ee6e8bb
PB		 5055 }
5056 switch (op) {
5057 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5058 gen_neon_addl(size);
9ee6e8bb 5059 break;
79b0e534 5060 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5061 gen_neon_subl(size);
9ee6e8bb
PB		 5062 break;
5063 case 5: case 7: /* VABAL, VABDL */
5064 switch ((size << 1) | u) {
ad69471c
PB		 5065 case 0:
5066 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5067 break;
5068 case 1:
5069 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5070 break;
5071 case 2:
5072 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5073 break;
5074 case 3:
5075 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5076 break;
5077 case 4:
5078 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5079 break;
5080 case 5:
5081 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5082 break;
9ee6e8bb
PB		 5083 default: abort();
5084 }
ad69471c
PB		 5085 dead_tmp(tmp2);
5086 dead_tmp(tmp);
9ee6e8bb
PB		 5087 break;
5088 case 8: case 9: case 10: case 11: case 12: case 13:
5089 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5090 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb
PB		 5091 break;
5092 case 14: /* Polynomial VMULL */
5093 cpu_abort(env, "Polynomial VMULL not implemented");
5094
5095 default: /* 15 is RESERVED. */
5096 return 1;
5097 }
5098 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5099 /* Accumulate. */
5100 if (op == 10 || op == 11) {
ad69471c 5101 gen_neon_negl(cpu_V0, size);
9ee6e8bb
PB		 5102 }
5103
9ee6e8bb 5104 if (op != 13) {
ad69471c 5105 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb
PB		 5106 }
5107
5108 switch (op) {
5109 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
ad69471c 5110 gen_neon_addl(size);
9ee6e8bb
PB		 5111 break;
5112 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c
PB		 5113 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5114 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5115 break;
9ee6e8bb
PB		 5116 /* Fall through. */
5117 case 13: /* VQDMULL */
ad69471c 5118 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5119 break;
5120 default:
5121 abort();
5122 }
ad69471c 5123 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5124 } else if (op == 4 || op == 6) {
5125 /* Narrowing operation. */
ad69471c 5126 tmp = new_tmp();
79b0e534 5127 if (!u) {
9ee6e8bb 5128 switch (size) {
ad69471c
PB		 5129 case 0:
5130 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5131 break;
5132 case 1:
5133 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5134 break;
5135 case 2:
5136 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5137 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5138 break;
9ee6e8bb
PB		 5139 default: abort();
5140 }
5141 } else {
5142 switch (size) {
ad69471c
PB		 5143 case 0:
5144 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5145 break;
5146 case 1:
5147 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5148 break;
5149 case 2:
5150 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5151 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5152 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5153 break;
9ee6e8bb
PB		 5154 default: abort();
5155 }
5156 }
ad69471c
PB		 5157 if (pass == 0) {
5158 tmp3 = tmp;
5159 } else {
5160 neon_store_reg(rd, 0, tmp3);
5161 neon_store_reg(rd, 1, tmp);
5162 }
9ee6e8bb
PB		 5163 } else {
5164 /* Write back the result. */
ad69471c 5165 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5166 }
5167 }
5168 } else {
5169 /* Two registers and a scalar. */
5170 switch (op) {
5171 case 0: /* Integer VMLA scalar */
5172 case 1: /* Float VMLA scalar */
5173 case 4: /* Integer VMLS scalar */
5174 case 5: /* Floating point VMLS scalar */
5175 case 8: /* Integer VMUL scalar */
5176 case 9: /* Floating point VMUL scalar */
5177 case 12: /* VQDMULH scalar */
5178 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5179 tmp = neon_get_scalar(size, rm);
5180 neon_store_scratch(0, tmp);
9ee6e8bb 5181 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5182 tmp = neon_load_scratch(0);
5183 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5184 if (op == 12) {
5185 if (size == 1) {
dd8fbd78 5186 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5187 } else {
dd8fbd78 5188 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5189 }
5190 } else if (op == 13) {
5191 if (size == 1) {
dd8fbd78 5192 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5193 } else {
dd8fbd78 5194 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5195 }
5196 } else if (op & 1) {
dd8fbd78 5197 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5198 } else {
5199 switch (size) {
dd8fbd78
FN		 5200 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5201 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5202 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5203 default: return 1;
5204 }
5205 }
dd8fbd78 5206 dead_tmp(tmp2);
9ee6e8bb
PB		 5207 if (op < 8) {
5208 /* Accumulate. */
dd8fbd78 5209 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5210 switch (op) {
5211 case 0:
dd8fbd78 5212 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5213 break;
5214 case 1:
dd8fbd78 5215 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5216 break;
5217 case 4:
dd8fbd78 5218 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5219 break;
5220 case 5:
dd8fbd78 5221 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5222 break;
5223 default:
5224 abort();
5225 }
dd8fbd78 5226 dead_tmp(tmp2);
9ee6e8bb 5227 }
dd8fbd78 5228 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5229 }
5230 break;
5231 case 2: /* VMLAL sclar */
5232 case 3: /* VQDMLAL scalar */
5233 case 6: /* VMLSL scalar */
5234 case 7: /* VQDMLSL scalar */
5235 case 10: /* VMULL scalar */
5236 case 11: /* VQDMULL scalar */
ad69471c
PB		 5237 if (size == 0 && (op == 3 || op == 7 || op == 11))
5238 return 1;
5239
dd8fbd78 5240 tmp2 = neon_get_scalar(size, rm);
c6067f04
CL		 5241 /* We need a copy of tmp2 because gen_neon_mull
5242 * deletes it during pass 0. */
5243 tmp4 = new_tmp();
5244 tcg_gen_mov_i32(tmp4, tmp2);
dd8fbd78 5245 tmp3 = neon_load_reg(rn, 1);
ad69471c 5246
9ee6e8bb 5247 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5248 if (pass == 0) {
5249 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5250 } else {
dd8fbd78 5251 tmp = tmp3;
c6067f04 5252 tmp2 = tmp4;
9ee6e8bb 5253 }
ad69471c 5254 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb 5255 if (op == 6 || op == 7) {
ad69471c
PB		 5256 gen_neon_negl(cpu_V0, size);
5257 }
5258 if (op != 11) {
5259 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5260 }
9ee6e8bb
PB		 5261 switch (op) {
5262 case 2: case 6:
ad69471c 5263 gen_neon_addl(size);
9ee6e8bb
PB		 5264 break;
5265 case 3: case 7:
ad69471c
PB		 5266 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5267 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5268 break;
5269 case 10:
5270 /* no-op */
5271 break;
5272 case 11:
ad69471c 5273 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5274 break;
5275 default:
5276 abort();
5277 }
ad69471c 5278 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5279 }
dd8fbd78 5280
dd8fbd78 5281
9ee6e8bb
PB		 5282 break;
5283 default: /* 14 and 15 are RESERVED */
5284 return 1;
5285 }
5286 }
5287 } else { /* size == 3 */
5288 if (!u) {
5289 /* Extract. */
9ee6e8bb 5290 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5291
5292 if (imm > 7 && !q)
5293 return 1;
5294
5295 if (imm == 0) {
5296 neon_load_reg64(cpu_V0, rn);
5297 if (q) {
5298 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5299 }
ad69471c
PB		 5300 } else if (imm == 8) {
5301 neon_load_reg64(cpu_V0, rn + 1);
5302 if (q) {
5303 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5304 }
ad69471c 5305 } else if (q) {
a7812ae4 5306 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5307 if (imm < 8) {
5308 neon_load_reg64(cpu_V0, rn);
a7812ae4 5309 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5310 } else {
5311 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5312 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5313 }
5314 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5315 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5316 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5317 if (imm < 8) {
5318 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5319 } else {
ad69471c
PB		 5320 neon_load_reg64(cpu_V1, rm + 1);
5321 imm -= 8;
9ee6e8bb 5322 }
ad69471c 5323 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5324 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5325 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5326 tcg_temp_free_i64(tmp64);
ad69471c 5327 } else {
a7812ae4 5328 /* BUGFIX */
ad69471c 5329 neon_load_reg64(cpu_V0, rn);
a7812ae4 5330 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5331 neon_load_reg64(cpu_V1, rm);
a7812ae4 5332 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5333 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5334 }
5335 neon_store_reg64(cpu_V0, rd);
5336 if (q) {
5337 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5338 }
5339 } else if ((insn & (1 << 11)) == 0) {
5340 /* Two register misc. */
5341 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5342 size = (insn >> 18) & 3;
5343 switch (op) {
5344 case 0: /* VREV64 */
5345 if (size == 3)
5346 return 1;
5347 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5348 tmp = neon_load_reg(rm, pass * 2);
5349 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5350 switch (size) {
dd8fbd78
FN		 5351 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5352 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5353 case 2: /* no-op */ break;
5354 default: abort();
5355 }
dd8fbd78 5356 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5357 if (size == 2) {
dd8fbd78 5358 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5359 } else {
9ee6e8bb 5360 switch (size) {
dd8fbd78
FN		 5361 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5362 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5363 default: abort();
5364 }
dd8fbd78 5365 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5366 }
5367 }
5368 break;
5369 case 4: case 5: /* VPADDL */
5370 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5371 if (size == 3)
5372 return 1;
ad69471c
PB		 5373 for (pass = 0; pass < q + 1; pass++) {
5374 tmp = neon_load_reg(rm, pass * 2);
5375 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5376 tmp = neon_load_reg(rm, pass * 2 + 1);
5377 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5378 switch (size) {
5379 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5380 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5381 case 2: tcg_gen_add_i64(CPU_V001); break;
5382 default: abort();
5383 }
9ee6e8bb
PB		 5384 if (op >= 12) {
5385 /* Accumulate. */
ad69471c
PB		 5386 neon_load_reg64(cpu_V1, rd + pass);
5387 gen_neon_addl(size);
9ee6e8bb 5388 }
ad69471c 5389 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5390 }
5391 break;
5392 case 33: /* VTRN */
5393 if (size == 2) {
5394 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5395 tmp = neon_load_reg(rm, n);
5396 tmp2 = neon_load_reg(rd, n + 1);
5397 neon_store_reg(rm, n, tmp2);
5398 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5399 }
5400 } else {
5401 goto elementwise;
5402 }
5403 break;
5404 case 34: /* VUZP */
5405 /* Reg Before After
5406 Rd A3 A2 A1 A0 B2 B0 A2 A0
5407 Rm B3 B2 B1 B0 B3 B1 A3 A1
5408 */
5409 if (size == 3)
5410 return 1;
5411 gen_neon_unzip(rd, q, 0, size);
5412 gen_neon_unzip(rm, q, 4, size);
5413 if (q) {
5414 static int unzip_order_q[8] =
5415 {0, 2, 4, 6, 1, 3, 5, 7};
5416 for (n = 0; n < 8; n++) {
5417 int reg = (n < 4) ? rd : rm;
dd8fbd78
FN		 5418 tmp = neon_load_scratch(unzip_order_q[n]);
5419 neon_store_reg(reg, n % 4, tmp);
9ee6e8bb
PB		 5420 }
5421 } else {
5422 static int unzip_order[4] =
5423 {0, 4, 1, 5};
5424 for (n = 0; n < 4; n++) {
5425 int reg = (n < 2) ? rd : rm;
dd8fbd78
FN		 5426 tmp = neon_load_scratch(unzip_order[n]);
5427 neon_store_reg(reg, n % 2, tmp);
9ee6e8bb
PB		 5428 }
5429 }
5430 break;
5431 case 35: /* VZIP */
5432 /* Reg Before After
5433 Rd A3 A2 A1 A0 B1 A1 B0 A0
5434 Rm B3 B2 B1 B0 B3 A3 B2 A2
5435 */
5436 if (size == 3)
5437 return 1;
5438 count = (q ? 4 : 2);
5439 for (n = 0; n < count; n++) {
dd8fbd78
FN		 5440 tmp = neon_load_reg(rd, n);
5441 tmp2 = neon_load_reg(rd, n);
9ee6e8bb 5442 switch (size) {
dd8fbd78
FN		 5443 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5444 case 1: gen_neon_zip_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5445 case 2: /* no-op */; break;
5446 default: abort();
5447 }
dd8fbd78
FN		 5448 neon_store_scratch(n * 2, tmp);
5449 neon_store_scratch(n * 2 + 1, tmp2);
9ee6e8bb
PB		 5450 }
5451 for (n = 0; n < count * 2; n++) {
5452 int reg = (n < count) ? rd : rm;
dd8fbd78
FN		 5453 tmp = neon_load_scratch(n);
5454 neon_store_reg(reg, n % count, tmp);
9ee6e8bb
PB		 5455 }
5456 break;
5457 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5458 if (size == 3)
5459 return 1;
a50f5b91 5460 TCGV_UNUSED(tmp2);
9ee6e8bb 5461 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5462 neon_load_reg64(cpu_V0, rm + pass);
5463 tmp = new_tmp();
9ee6e8bb 5464 if (op == 36 && q == 0) {
ad69471c 5465 gen_neon_narrow(size, tmp, cpu_V0);
9ee6e8bb 5466 } else if (q) {
ad69471c 5467 gen_neon_narrow_satu(size, tmp, cpu_V0);
9ee6e8bb 5468 } else {
ad69471c
PB		 5469 gen_neon_narrow_sats(size, tmp, cpu_V0);
5470 }
5471 if (pass == 0) {
5472 tmp2 = tmp;
5473 } else {
5474 neon_store_reg(rd, 0, tmp2);
5475 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5476 }
9ee6e8bb
PB		 5477 }
5478 break;
5479 case 38: /* VSHLL */
ad69471c 5480 if (q || size == 3)
9ee6e8bb 5481 return 1;
ad69471c
PB		 5482 tmp = neon_load_reg(rm, 0);
5483 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5484 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5485 if (pass == 1)
5486 tmp = tmp2;
5487 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5488 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5489 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5490 }
5491 break;
60011498
PB		 5492 case 44: /* VCVT.F16.F32 */
5493 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5494 return 1;
5495 tmp = new_tmp();
5496 tmp2 = new_tmp();
5497 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5498 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5499 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5500 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5501 tcg_gen_shli_i32(tmp2, tmp2, 16);
5502 tcg_gen_or_i32(tmp2, tmp2, tmp);
5503 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5504 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5505 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5506 neon_store_reg(rd, 0, tmp2);
5507 tmp2 = new_tmp();
5508 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5509 tcg_gen_shli_i32(tmp2, tmp2, 16);
5510 tcg_gen_or_i32(tmp2, tmp2, tmp);
5511 neon_store_reg(rd, 1, tmp2);
5512 dead_tmp(tmp);
5513 break;
5514 case 46: /* VCVT.F32.F16 */
5515 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5516 return 1;
5517 tmp3 = new_tmp();
5518 tmp = neon_load_reg(rm, 0);
5519 tmp2 = neon_load_reg(rm, 1);
5520 tcg_gen_ext16u_i32(tmp3, tmp);
5521 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5522 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5523 tcg_gen_shri_i32(tmp3, tmp, 16);
5524 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5525 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5526 dead_tmp(tmp);
5527 tcg_gen_ext16u_i32(tmp3, tmp2);
5528 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5529 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5530 tcg_gen_shri_i32(tmp3, tmp2, 16);
5531 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5532 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5533 dead_tmp(tmp2);
5534 dead_tmp(tmp3);
5535 break;
9ee6e8bb
PB		 5536 default:
5537 elementwise:
5538 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5539 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5540 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5541 neon_reg_offset(rm, pass));
dd8fbd78 5542 TCGV_UNUSED(tmp);
9ee6e8bb 5543 } else {
dd8fbd78 5544 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5545 }
5546 switch (op) {
5547 case 1: /* VREV32 */
5548 switch (size) {
dd8fbd78
FN		 5549 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5550 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5551 default: return 1;
5552 }
5553 break;
5554 case 2: /* VREV16 */
5555 if (size != 0)
5556 return 1;
dd8fbd78 5557 gen_rev16(tmp);
9ee6e8bb 5558 break;
9ee6e8bb
PB		 5559 case 8: /* CLS */
5560 switch (size) {
dd8fbd78
FN		 5561 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5562 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5563 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5564 default: return 1;
5565 }
5566 break;
5567 case 9: /* CLZ */
5568 switch (size) {
dd8fbd78
FN		 5569 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5570 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5571 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5572 default: return 1;
5573 }
5574 break;
5575 case 10: /* CNT */
5576 if (size != 0)
5577 return 1;
dd8fbd78 5578 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5579 break;
5580 case 11: /* VNOT */
5581 if (size != 0)
5582 return 1;
dd8fbd78 5583 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5584 break;
5585 case 14: /* VQABS */
5586 switch (size) {
dd8fbd78
FN		 5587 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5588 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5589 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5590 default: return 1;
5591 }
5592 break;
5593 case 15: /* VQNEG */
5594 switch (size) {
dd8fbd78
FN		 5595 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5596 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5597 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5598 default: return 1;
5599 }
5600 break;
5601 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5602 tmp2 = tcg_const_i32(0);
9ee6e8bb 5603 switch(size) {
dd8fbd78
FN		 5604 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5605 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5606 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5607 default: return 1;
5608 }
dd8fbd78 5609 tcg_temp_free(tmp2);
9ee6e8bb 5610 if (op == 19)
dd8fbd78 5611 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5612 break;
5613 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5614 tmp2 = tcg_const_i32(0);
9ee6e8bb 5615 switch(size) {
dd8fbd78
FN		 5616 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5617 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5618 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5619 default: return 1;
5620 }
dd8fbd78 5621 tcg_temp_free(tmp2);
9ee6e8bb 5622 if (op == 20)
dd8fbd78 5623 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5624 break;
5625 case 18: /* VCEQ #0 */
dd8fbd78 5626 tmp2 = tcg_const_i32(0);
9ee6e8bb 5627 switch(size) {
dd8fbd78
FN		 5628 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5629 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5630 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5631 default: return 1;
5632 }
dd8fbd78 5633 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5634 break;
5635 case 22: /* VABS */
5636 switch(size) {
dd8fbd78
FN		 5637 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5638 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5639 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5640 default: return 1;
5641 }
5642 break;
5643 case 23: /* VNEG */
ad69471c
PB		 5644 if (size == 3)
5645 return 1;
dd8fbd78
FN		 5646 tmp2 = tcg_const_i32(0);
5647 gen_neon_rsb(size, tmp, tmp2);
5648 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5649 break;
5650 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
dd8fbd78
FN		 5651 tmp2 = tcg_const_i32(0);
5652 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5653 tcg_temp_free(tmp2);
9ee6e8bb 5654 if (op == 27)
dd8fbd78 5655 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5656 break;
5657 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
dd8fbd78
FN		 5658 tmp2 = tcg_const_i32(0);
5659 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5660 tcg_temp_free(tmp2);
9ee6e8bb 5661 if (op == 28)
dd8fbd78 5662 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5663 break;
5664 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5665 tmp2 = tcg_const_i32(0);
5666 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5667 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5668 break;
5669 case 30: /* Float VABS */
4373f3ce 5670 gen_vfp_abs(0);
9ee6e8bb
PB		 5671 break;
5672 case 31: /* Float VNEG */
4373f3ce 5673 gen_vfp_neg(0);
9ee6e8bb
PB		 5674 break;
5675 case 32: /* VSWP */
dd8fbd78
FN		 5676 tmp2 = neon_load_reg(rd, pass);
5677 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5678 break;
5679 case 33: /* VTRN */
dd8fbd78 5680 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5681 switch (size) {
dd8fbd78
FN		 5682 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5683 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5684 case 2: abort();
5685 default: return 1;
5686 }
dd8fbd78 5687 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5688 break;
5689 case 56: /* Integer VRECPE */
dd8fbd78 5690 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5691 break;
5692 case 57: /* Integer VRSQRTE */
dd8fbd78 5693 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5694 break;
5695 case 58: /* Float VRECPE */
4373f3ce 5696 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5697 break;
5698 case 59: /* Float VRSQRTE */
4373f3ce 5699 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5700 break;
5701 case 60: /* VCVT.F32.S32 */
d3587ef8 5702 gen_vfp_sito(0);
9ee6e8bb
PB		 5703 break;
5704 case 61: /* VCVT.F32.U32 */
d3587ef8 5705 gen_vfp_uito(0);
9ee6e8bb
PB		 5706 break;
5707 case 62: /* VCVT.S32.F32 */
d3587ef8 5708 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5709 break;
5710 case 63: /* VCVT.U32.F32 */
d3587ef8 5711 gen_vfp_touiz(0);
9ee6e8bb
PB		 5712 break;
5713 default:
5714 /* Reserved: 21, 29, 39-56 */
5715 return 1;
5716 }
5717 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5718 tcg_gen_st_f32(cpu_F0s, cpu_env,
5719 neon_reg_offset(rd, pass));
9ee6e8bb 5720 } else {
dd8fbd78 5721 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5722 }
5723 }
5724 break;
5725 }
5726 } else if ((insn & (1 << 10)) == 0) {
5727 /* VTBL, VTBX. */
3018f259 5728 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5729 if (insn & (1 << 6)) {
8f8e3aa4 5730 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5731 } else {
8f8e3aa4
PB		 5732 tmp = new_tmp();
5733 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5734 }
8f8e3aa4 5735 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5736 tmp4 = tcg_const_i32(rn);
5737 tmp5 = tcg_const_i32(n);
5738 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
3018f259 5739 dead_tmp(tmp);
9ee6e8bb 5740 if (insn & (1 << 6)) {
8f8e3aa4 5741 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5742 } else {
8f8e3aa4
PB		 5743 tmp = new_tmp();
5744 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5745 }
8f8e3aa4 5746 tmp3 = neon_load_reg(rm, 1);
b75263d6 5747 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5748 tcg_temp_free_i32(tmp5);
5749 tcg_temp_free_i32(tmp4);
8f8e3aa4 5750 neon_store_reg(rd, 0, tmp2);
3018f259
PB		 5751 neon_store_reg(rd, 1, tmp3);
5752 dead_tmp(tmp);
9ee6e8bb
PB		 5753 } else if ((insn & 0x380) == 0) {
5754 /* VDUP */
5755 if (insn & (1 << 19)) {
dd8fbd78 5756 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5757 } else {
dd8fbd78 5758 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5759 }
5760 if (insn & (1 << 16)) {
dd8fbd78 5761 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5762 } else if (insn & (1 << 17)) {
5763 if ((insn >> 18) & 1)
dd8fbd78 5764 gen_neon_dup_high16(tmp);
9ee6e8bb 5765 else
dd8fbd78 5766 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5767 }
5768 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 5769 tmp2 = new_tmp();
5770 tcg_gen_mov_i32(tmp2, tmp);
5771 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5772 }
dd8fbd78 5773 dead_tmp(tmp);
9ee6e8bb
PB		 5774 } else {
5775 return 1;
5776 }
5777 }
5778 }
5779 return 0;
5780}
5781
fe1479c3
PB		 5782static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5783{
5784 int crn = (insn >> 16) & 0xf;
5785 int crm = insn & 0xf;
5786 int op1 = (insn >> 21) & 7;
5787 int op2 = (insn >> 5) & 7;
5788 int rt = (insn >> 12) & 0xf;
5789 TCGv tmp;
5790
5791 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5792 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5793 /* TEECR */
5794 if (IS_USER(s))
5795 return 1;
5796 tmp = load_cpu_field(teecr);
5797 store_reg(s, rt, tmp);
5798 return 0;
5799 }
5800 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5801 /* TEEHBR */
5802 if (IS_USER(s) && (env->teecr & 1))
5803 return 1;
5804 tmp = load_cpu_field(teehbr);
5805 store_reg(s, rt, tmp);
5806 return 0;
5807 }
5808 }
5809 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5810 op1, crn, crm, op2);
5811 return 1;
5812}
5813
5814static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5815{
5816 int crn = (insn >> 16) & 0xf;
5817 int crm = insn & 0xf;
5818 int op1 = (insn >> 21) & 7;
5819 int op2 = (insn >> 5) & 7;
5820 int rt = (insn >> 12) & 0xf;
5821 TCGv tmp;
5822
5823 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5824 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5825 /* TEECR */
5826 if (IS_USER(s))
5827 return 1;
5828 tmp = load_reg(s, rt);
5829 gen_helper_set_teecr(cpu_env, tmp);
5830 dead_tmp(tmp);
5831 return 0;
5832 }
5833 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5834 /* TEEHBR */
5835 if (IS_USER(s) && (env->teecr & 1))
5836 return 1;
5837 tmp = load_reg(s, rt);
5838 store_cpu_field(tmp, teehbr);
5839 return 0;
5840 }
5841 }
5842 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5843 op1, crn, crm, op2);
5844 return 1;
5845}
5846
9ee6e8bb
PB		 5847static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5848{
5849 int cpnum;
5850
5851 cpnum = (insn >> 8) & 0xf;
5852 if (arm_feature(env, ARM_FEATURE_XSCALE)
5853 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5854 return 1;
5855
5856 switch (cpnum) {
5857 case 0:
5858 case 1:
5859 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5860 return disas_iwmmxt_insn(env, s, insn);
5861 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5862 return disas_dsp_insn(env, s, insn);
5863 }
5864 return 1;
5865 case 10:
5866 case 11:
5867 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 5868 case 14:
5869 /* Coprocessors 7-15 are architecturally reserved by ARM.
5870 Unfortunately Intel decided to ignore this. */
5871 if (arm_feature(env, ARM_FEATURE_XSCALE))
5872 goto board;
5873 if (insn & (1 << 20))
5874 return disas_cp14_read(env, s, insn);
5875 else
5876 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 5877 case 15:
5878 return disas_cp15_insn (env, s, insn);
5879 default:
fe1479c3 5880 board:
9ee6e8bb
PB		 5881 /* Unknown coprocessor. See if the board has hooked it. */
5882 return disas_cp_insn (env, s, insn);
5883 }
5884}
5885
5e3f878a
PB		 5886
5887/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 5888static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 5889{
5890 TCGv tmp;
5891 tmp = new_tmp();
5892 tcg_gen_trunc_i64_i32(tmp, val);
5893 store_reg(s, rlow, tmp);
5894 tmp = new_tmp();
5895 tcg_gen_shri_i64(val, val, 32);
5896 tcg_gen_trunc_i64_i32(tmp, val);
5897 store_reg(s, rhigh, tmp);
5898}
5899
5900/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 5901static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 5902{
a7812ae4 5903 TCGv_i64 tmp;
5e3f878a
PB		 5904 TCGv tmp2;
5905
36aa55dc 5906 /* Load value and extend to 64 bits. */
a7812ae4 5907 tmp = tcg_temp_new_i64();
5e3f878a
PB		 5908 tmp2 = load_reg(s, rlow);
5909 tcg_gen_extu_i32_i64(tmp, tmp2);
5910 dead_tmp(tmp2);
5911 tcg_gen_add_i64(val, val, tmp);
b75263d6 5912 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5913}
5914
5915/* load and add a 64-bit value from a register pair. */
a7812ae4 5916static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 5917{
a7812ae4 5918 TCGv_i64 tmp;
36aa55dc
PB		 5919 TCGv tmpl;
5920 TCGv tmph;
5e3f878a
PB		 5921
5922 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 5923 tmpl = load_reg(s, rlow);
5924 tmph = load_reg(s, rhigh);
a7812ae4 5925 tmp = tcg_temp_new_i64();
36aa55dc
PB		 5926 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5927 dead_tmp(tmpl);
5928 dead_tmp(tmph);
5e3f878a 5929 tcg_gen_add_i64(val, val, tmp);
b75263d6 5930 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5931}
5932
5933/* Set N and Z flags from a 64-bit value. */
a7812ae4 5934static void gen_logicq_cc(TCGv_i64 val)
5e3f878a
PB		 5935{
5936 TCGv tmp = new_tmp();
5937 gen_helper_logicq_cc(tmp, val);
6fbe23d5
PB		 5938 gen_logic_CC(tmp);
5939 dead_tmp(tmp);
5e3f878a
PB		 5940}
5941
426f5abc
PB		 5942/* Load/Store exclusive instructions are implemented by remembering
5943 the value/address loaded, and seeing if these are the same
5944 when the store is performed. This should be is sufficient to implement
5945 the architecturally mandated semantics, and avoids having to monitor
5946 regular stores.
5947
5948 In system emulation mode only one CPU will be running at once, so
5949 this sequence is effectively atomic. In user emulation mode we
5950 throw an exception and handle the atomic operation elsewhere. */
5951static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5952 TCGv addr, int size)
5953{
5954 TCGv tmp;
5955
5956 switch (size) {
5957 case 0:
5958 tmp = gen_ld8u(addr, IS_USER(s));
5959 break;
5960 case 1:
5961 tmp = gen_ld16u(addr, IS_USER(s));
5962 break;
5963 case 2:
5964 case 3:
5965 tmp = gen_ld32(addr, IS_USER(s));
5966 break;
5967 default:
5968 abort();
5969 }
5970 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5971 store_reg(s, rt, tmp);
5972 if (size == 3) {
2c9adbda
PM		 5973 TCGv tmp2 = new_tmp();
5974 tcg_gen_addi_i32(tmp2, addr, 4);
5975 tmp = gen_ld32(tmp2, IS_USER(s));
5976 dead_tmp(tmp2);
426f5abc
PB		 5977 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5978 store_reg(s, rt2, tmp);
5979 }
5980 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5981}
5982
5983static void gen_clrex(DisasContext *s)
5984{
5985 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5986}
5987
5988#ifdef CONFIG_USER_ONLY
5989static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5990 TCGv addr, int size)
5991{
5992 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5993 tcg_gen_movi_i32(cpu_exclusive_info,
5994 size | (rd << 4) | (rt << 8) | (rt2 << 12));
bc4a0de0 5995 gen_exception_insn(s, 4, EXCP_STREX);
426f5abc
PB		 5996}
5997#else
5998static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5999 TCGv addr, int size)
6000{
6001 TCGv tmp;
6002 int done_label;
6003 int fail_label;
6004
6005 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6006 [addr] = {Rt};
6007 {Rd} = 0;
6008 } else {
6009 {Rd} = 1;
6010 } */
6011 fail_label = gen_new_label();
6012 done_label = gen_new_label();
6013 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6014 switch (size) {
6015 case 0:
6016 tmp = gen_ld8u(addr, IS_USER(s));
6017 break;
6018 case 1:
6019 tmp = gen_ld16u(addr, IS_USER(s));
6020 break;
6021 case 2:
6022 case 3:
6023 tmp = gen_ld32(addr, IS_USER(s));
6024 break;
6025 default:
6026 abort();
6027 }
6028 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6029 dead_tmp(tmp);
6030 if (size == 3) {
6031 TCGv tmp2 = new_tmp();
6032 tcg_gen_addi_i32(tmp2, addr, 4);
2c9adbda 6033 tmp = gen_ld32(tmp2, IS_USER(s));
426f5abc
PB		 6034 dead_tmp(tmp2);
6035 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6036 dead_tmp(tmp);
6037 }
6038 tmp = load_reg(s, rt);
6039 switch (size) {
6040 case 0:
6041 gen_st8(tmp, addr, IS_USER(s));
6042 break;
6043 case 1:
6044 gen_st16(tmp, addr, IS_USER(s));
6045 break;
6046 case 2:
6047 case 3:
6048 gen_st32(tmp, addr, IS_USER(s));
6049 break;
6050 default:
6051 abort();
6052 }
6053 if (size == 3) {
6054 tcg_gen_addi_i32(addr, addr, 4);
6055 tmp = load_reg(s, rt2);
6056 gen_st32(tmp, addr, IS_USER(s));
6057 }
6058 tcg_gen_movi_i32(cpu_R[rd], 0);
6059 tcg_gen_br(done_label);
6060 gen_set_label(fail_label);
6061 tcg_gen_movi_i32(cpu_R[rd], 1);
6062 gen_set_label(done_label);
6063 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6064}
6065#endif
6066
9ee6e8bb
PB		 6067static void disas_arm_insn(CPUState * env, DisasContext *s)
6068{
6069 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6070 TCGv tmp;
3670669c 6071 TCGv tmp2;
6ddbc6e4 6072 TCGv tmp3;
b0109805 6073 TCGv addr;
a7812ae4 6074 TCGv_i64 tmp64;
9ee6e8bb
PB		 6075
6076 insn = ldl_code(s->pc);
6077 s->pc += 4;
6078
6079 /* M variants do not implement ARM mode. */
6080 if (IS_M(env))
6081 goto illegal_op;
6082 cond = insn >> 28;
6083 if (cond == 0xf){
6084 /* Unconditional instructions. */
6085 if (((insn >> 25) & 7) == 1) {
6086 /* NEON Data processing. */
6087 if (!arm_feature(env, ARM_FEATURE_NEON))
6088 goto illegal_op;
6089
6090 if (disas_neon_data_insn(env, s, insn))
6091 goto illegal_op;
6092 return;
6093 }
6094 if ((insn & 0x0f100000) == 0x04000000) {
6095 /* NEON load/store. */
6096 if (!arm_feature(env, ARM_FEATURE_NEON))
6097 goto illegal_op;
6098
6099 if (disas_neon_ls_insn(env, s, insn))
6100 goto illegal_op;
6101 return;
6102 }
3d185e5d
PM		 6103 if (((insn & 0x0f30f000) == 0x0510f000) ||
6104 ((insn & 0x0f30f010) == 0x0710f000)) {
6105 if ((insn & (1 << 22)) == 0) {
6106 /* PLDW; v7MP */
6107 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6108 goto illegal_op;
6109 }
6110 }
6111 /* Otherwise PLD; v5TE+ */
6112 return;
6113 }
6114 if (((insn & 0x0f70f000) == 0x0450f000) ||
6115 ((insn & 0x0f70f010) == 0x0650f000)) {
6116 ARCH(7);
6117 return; /* PLI; V7 */
6118 }
6119 if (((insn & 0x0f700000) == 0x04100000) ||
6120 ((insn & 0x0f700010) == 0x06100000)) {
6121 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6122 goto illegal_op;
6123 }
6124 return; /* v7MP: Unallocated memory hint: must NOP */
6125 }
6126
6127 if ((insn & 0x0ffffdff) == 0x01010000) {
9ee6e8bb
PB		 6128 ARCH(6);
6129 /* setend */
6130 if (insn & (1 << 9)) {
6131 /* BE8 mode not implemented. */
6132 goto illegal_op;
6133 }
6134 return;
6135 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6136 switch ((insn >> 4) & 0xf) {
6137 case 1: /* clrex */
6138 ARCH(6K);
426f5abc 6139 gen_clrex(s);
9ee6e8bb
PB		 6140 return;
6141 case 4: /* dsb */
6142 case 5: /* dmb */
6143 case 6: /* isb */
6144 ARCH(7);
6145 /* We don't emulate caches so these are a no-op. */
6146 return;
6147 default:
6148 goto illegal_op;
6149 }
6150 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6151 /* srs */
c67b6b71 6152 int32_t offset;
9ee6e8bb
PB		 6153 if (IS_USER(s))
6154 goto illegal_op;
6155 ARCH(6);
6156 op1 = (insn & 0x1f);
39ea3d4e
PM		 6157 addr = new_tmp();
6158 tmp = tcg_const_i32(op1);
6159 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6160 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6161 i = (insn >> 23) & 3;
6162 switch (i) {
6163 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6164 case 1: offset = 0; break; /* IA */
6165 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6166 case 3: offset = 4; break; /* IB */
6167 default: abort();
6168 }
6169 if (offset)
b0109805
PB		 6170 tcg_gen_addi_i32(addr, addr, offset);
6171 tmp = load_reg(s, 14);
6172 gen_st32(tmp, addr, 0);
c67b6b71 6173 tmp = load_cpu_field(spsr);
b0109805
PB		 6174 tcg_gen_addi_i32(addr, addr, 4);
6175 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6176 if (insn & (1 << 21)) {
6177 /* Base writeback. */
6178 switch (i) {
6179 case 0: offset = -8; break;
c67b6b71
FN		 6180 case 1: offset = 4; break;
6181 case 2: offset = -4; break;
9ee6e8bb
PB		 6182 case 3: offset = 0; break;
6183 default: abort();
6184 }
6185 if (offset)
c67b6b71 6186 tcg_gen_addi_i32(addr, addr, offset);
39ea3d4e
PM		 6187 tmp = tcg_const_i32(op1);
6188 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6189 tcg_temp_free_i32(tmp);
6190 dead_tmp(addr);
b0109805
PB		 6191 } else {
6192 dead_tmp(addr);
9ee6e8bb 6193 }
a990f58f 6194 return;
ea825eee 6195 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6196 /* rfe */
c67b6b71 6197 int32_t offset;
9ee6e8bb
PB		 6198 if (IS_USER(s))
6199 goto illegal_op;
6200 ARCH(6);
6201 rn = (insn >> 16) & 0xf;
b0109805 6202 addr = load_reg(s, rn);
9ee6e8bb
PB		 6203 i = (insn >> 23) & 3;
6204 switch (i) {
b0109805 6205 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6206 case 1: offset = 0; break; /* IA */
6207 case 2: offset = -8; break; /* DB */
b0109805 6208 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6209 default: abort();
6210 }
6211 if (offset)
b0109805
PB		 6212 tcg_gen_addi_i32(addr, addr, offset);
6213 /* Load PC into tmp and CPSR into tmp2. */
6214 tmp = gen_ld32(addr, 0);
6215 tcg_gen_addi_i32(addr, addr, 4);
6216 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6217 if (insn & (1 << 21)) {
6218 /* Base writeback. */
6219 switch (i) {
b0109805 6220 case 0: offset = -8; break;
c67b6b71
FN		 6221 case 1: offset = 4; break;
6222 case 2: offset = -4; break;
b0109805 6223 case 3: offset = 0; break;
9ee6e8bb
PB		 6224 default: abort();
6225 }
6226 if (offset)
b0109805
PB		 6227 tcg_gen_addi_i32(addr, addr, offset);
6228 store_reg(s, rn, addr);
6229 } else {
6230 dead_tmp(addr);
9ee6e8bb 6231 }
b0109805 6232 gen_rfe(s, tmp, tmp2);
c67b6b71 6233 return;
9ee6e8bb
PB		 6234 } else if ((insn & 0x0e000000) == 0x0a000000) {
6235 /* branch link and change to thumb (blx <offset>) */
6236 int32_t offset;
6237
6238 val = (uint32_t)s->pc;
d9ba4830
PB		 6239 tmp = new_tmp();
6240 tcg_gen_movi_i32(tmp, val);
6241 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6242 /* Sign-extend the 24-bit offset */
6243 offset = (((int32_t)insn) << 8) >> 8;
6244 /* offset * 4 + bit24 * 2 + (thumb bit) */
6245 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6246 /* pipeline offset */
6247 val += 4;
d9ba4830 6248 gen_bx_im(s, val);
9ee6e8bb
PB		 6249 return;
6250 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6251 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6252 /* iWMMXt register transfer. */
6253 if (env->cp15.c15_cpar & (1 << 1))
6254 if (!disas_iwmmxt_insn(env, s, insn))
6255 return;
6256 }
6257 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6258 /* Coprocessor double register transfer. */
6259 } else if ((insn & 0x0f000010) == 0x0e000010) {
6260 /* Additional coprocessor register transfer. */
7997d92f 6261 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6262 uint32_t mask;
6263 uint32_t val;
6264 /* cps (privileged) */
6265 if (IS_USER(s))
6266 return;
6267 mask = val = 0;
6268 if (insn & (1 << 19)) {
6269 if (insn & (1 << 8))
6270 mask |= CPSR_A;
6271 if (insn & (1 << 7))
6272 mask |= CPSR_I;
6273 if (insn & (1 << 6))
6274 mask |= CPSR_F;
6275 if (insn & (1 << 18))
6276 val |= mask;
6277 }
7997d92f 6278 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6279 mask |= CPSR_M;
6280 val |= (insn & 0x1f);
6281 }
6282 if (mask) {
2fbac54b 6283 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6284 }
6285 return;
6286 }
6287 goto illegal_op;
6288 }
6289 if (cond != 0xe) {
6290 /* if not always execute, we generate a conditional jump to
6291 next instruction */
6292 s->condlabel = gen_new_label();
d9ba4830 6293 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6294 s->condjmp = 1;
6295 }
6296 if ((insn & 0x0f900000) == 0x03000000) {
6297 if ((insn & (1 << 21)) == 0) {
6298 ARCH(6T2);
6299 rd = (insn >> 12) & 0xf;
6300 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6301 if ((insn & (1 << 22)) == 0) {
6302 /* MOVW */
5e3f878a
PB		 6303 tmp = new_tmp();
6304 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6305 } else {
6306 /* MOVT */
5e3f878a 6307 tmp = load_reg(s, rd);
86831435 6308 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6309 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6310 }
5e3f878a 6311 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6312 } else {
6313 if (((insn >> 12) & 0xf) != 0xf)
6314 goto illegal_op;
6315 if (((insn >> 16) & 0xf) == 0) {
6316 gen_nop_hint(s, insn & 0xff);
6317 } else {
6318 /* CPSR = immediate */
6319 val = insn & 0xff;
6320 shift = ((insn >> 8) & 0xf) * 2;
6321 if (shift)
6322 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6323 i = ((insn & (1 << 22)) != 0);
2fbac54b 6324 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6325 goto illegal_op;
6326 }
6327 }
6328 } else if ((insn & 0x0f900000) == 0x01000000
6329 && (insn & 0x00000090) != 0x00000090) {
6330 /* miscellaneous instructions */
6331 op1 = (insn >> 21) & 3;
6332 sh = (insn >> 4) & 0xf;
6333 rm = insn & 0xf;
6334 switch (sh) {
6335 case 0x0: /* move program status register */
6336 if (op1 & 1) {
6337 /* PSR = reg */
2fbac54b 6338 tmp = load_reg(s, rm);
9ee6e8bb 6339 i = ((op1 & 2) != 0);
2fbac54b 6340 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6341 goto illegal_op;
6342 } else {
6343 /* reg = PSR */
6344 rd = (insn >> 12) & 0xf;
6345 if (op1 & 2) {
6346 if (IS_USER(s))
6347 goto illegal_op;
d9ba4830 6348 tmp = load_cpu_field(spsr);
9ee6e8bb 6349 } else {
d9ba4830
PB		 6350 tmp = new_tmp();
6351 gen_helper_cpsr_read(tmp);
9ee6e8bb 6352 }
d9ba4830 6353 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6354 }
6355 break;
6356 case 0x1:
6357 if (op1 == 1) {
6358 /* branch/exchange thumb (bx). */
d9ba4830
PB		 6359 tmp = load_reg(s, rm);
6360 gen_bx(s, tmp);
9ee6e8bb
PB		 6361 } else if (op1 == 3) {
6362 /* clz */
6363 rd = (insn >> 12) & 0xf;
1497c961
PB		 6364 tmp = load_reg(s, rm);
6365 gen_helper_clz(tmp, tmp);
6366 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6367 } else {
6368 goto illegal_op;
6369 }
6370 break;
6371 case 0x2:
6372 if (op1 == 1) {
6373 ARCH(5J); /* bxj */
6374 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6375 tmp = load_reg(s, rm);
6376 gen_bx(s, tmp);
9ee6e8bb
PB		 6377 } else {
6378 goto illegal_op;
6379 }
6380 break;
6381 case 0x3:
6382 if (op1 != 1)
6383 goto illegal_op;
6384
6385 /* branch link/exchange thumb (blx) */
d9ba4830
PB		 6386 tmp = load_reg(s, rm);
6387 tmp2 = new_tmp();
6388 tcg_gen_movi_i32(tmp2, s->pc);
6389 store_reg(s, 14, tmp2);
6390 gen_bx(s, tmp);
9ee6e8bb
PB		 6391 break;
6392 case 0x5: /* saturating add/subtract */
6393 rd = (insn >> 12) & 0xf;
6394 rn = (insn >> 16) & 0xf;
b40d0353 6395 tmp = load_reg(s, rm);
5e3f878a 6396 tmp2 = load_reg(s, rn);
9ee6e8bb 6397 if (op1 & 2)
5e3f878a 6398 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6399 if (op1 & 1)
5e3f878a 6400 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6401 else
5e3f878a
PB		 6402 gen_helper_add_saturate(tmp, tmp, tmp2);
6403 dead_tmp(tmp2);
6404 store_reg(s, rd, tmp);
9ee6e8bb 6405 break;
49e14940
AL		 6406 case 7:
6407 /* SMC instruction (op1 == 3)
6408 and undefined instructions (op1 == 0 || op1 == 2)
6409 will trap */
6410 if (op1 != 1) {
6411 goto illegal_op;
6412 }
6413 /* bkpt */
bc4a0de0 6414 gen_exception_insn(s, 4, EXCP_BKPT);
9ee6e8bb
PB		 6415 break;
6416 case 0x8: /* signed multiply */
6417 case 0xa:
6418 case 0xc:
6419 case 0xe:
6420 rs = (insn >> 8) & 0xf;
6421 rn = (insn >> 12) & 0xf;
6422 rd = (insn >> 16) & 0xf;
6423 if (op1 == 1) {
6424 /* (32 * 16) >> 16 */
5e3f878a
PB		 6425 tmp = load_reg(s, rm);
6426 tmp2 = load_reg(s, rs);
9ee6e8bb 6427 if (sh & 4)
5e3f878a 6428 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6429 else
5e3f878a 6430 gen_sxth(tmp2);
a7812ae4
PB		 6431 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6432 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 6433 tmp = new_tmp();
a7812ae4 6434 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6435 tcg_temp_free_i64(tmp64);
9ee6e8bb 6436 if ((sh & 2) == 0) {
5e3f878a
PB		 6437 tmp2 = load_reg(s, rn);
6438 gen_helper_add_setq(tmp, tmp, tmp2);
6439 dead_tmp(tmp2);
9ee6e8bb 6440 }
5e3f878a 6441 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6442 } else {
6443 /* 16 * 16 */
5e3f878a
PB		 6444 tmp = load_reg(s, rm);
6445 tmp2 = load_reg(s, rs);
6446 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6447 dead_tmp(tmp2);
9ee6e8bb 6448 if (op1 == 2) {
a7812ae4
PB		 6449 tmp64 = tcg_temp_new_i64();
6450 tcg_gen_ext_i32_i64(tmp64, tmp);
22478e79 6451 dead_tmp(tmp);
a7812ae4
PB		 6452 gen_addq(s, tmp64, rn, rd);
6453 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6454 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6455 } else {
6456 if (op1 == 0) {
5e3f878a
PB		 6457 tmp2 = load_reg(s, rn);
6458 gen_helper_add_setq(tmp, tmp, tmp2);
6459 dead_tmp(tmp2);
9ee6e8bb 6460 }
5e3f878a 6461 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6462 }
6463 }
6464 break;
6465 default:
6466 goto illegal_op;
6467 }
6468 } else if (((insn & 0x0e000000) == 0 &&
6469 (insn & 0x00000090) != 0x90) ||
6470 ((insn & 0x0e000000) == (1 << 25))) {
6471 int set_cc, logic_cc, shiftop;
6472
6473 op1 = (insn >> 21) & 0xf;
6474 set_cc = (insn >> 20) & 1;
6475 logic_cc = table_logic_cc[op1] & set_cc;
6476
6477 /* data processing instruction */
6478 if (insn & (1 << 25)) {
6479 /* immediate operand */
6480 val = insn & 0xff;
6481 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6482 if (shift) {
9ee6e8bb 6483 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9
JR		 6484 }
6485 tmp2 = new_tmp();
6486 tcg_gen_movi_i32(tmp2, val);
6487 if (logic_cc && shift) {
6488 gen_set_CF_bit31(tmp2);
6489 }
9ee6e8bb
PB		 6490 } else {
6491 /* register */
6492 rm = (insn) & 0xf;
e9bb4aa9 6493 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6494 shiftop = (insn >> 5) & 3;
6495 if (!(insn & (1 << 4))) {
6496 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6497 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6498 } else {
6499 rs = (insn >> 8) & 0xf;
8984bd2e 6500 tmp = load_reg(s, rs);
e9bb4aa9 6501 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6502 }
6503 }
6504 if (op1 != 0x0f && op1 != 0x0d) {
6505 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6506 tmp = load_reg(s, rn);
6507 } else {
6508 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6509 }
6510 rd = (insn >> 12) & 0xf;
6511 switch(op1) {
6512 case 0x00:
e9bb4aa9
JR		 6513 tcg_gen_and_i32(tmp, tmp, tmp2);
6514 if (logic_cc) {
6515 gen_logic_CC(tmp);
6516 }
21aeb343 6517 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6518 break;
6519 case 0x01:
e9bb4aa9
JR		 6520 tcg_gen_xor_i32(tmp, tmp, tmp2);
6521 if (logic_cc) {
6522 gen_logic_CC(tmp);
6523 }
21aeb343 6524 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6525 break;
6526 case 0x02:
6527 if (set_cc && rd == 15) {
6528 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6529 if (IS_USER(s)) {
9ee6e8bb 6530 goto illegal_op;
e9bb4aa9
JR		 6531 }
6532 gen_helper_sub_cc(tmp, tmp, tmp2);
6533 gen_exception_return(s, tmp);
9ee6e8bb 6534 } else {
e9bb4aa9
JR		 6535 if (set_cc) {
6536 gen_helper_sub_cc(tmp, tmp, tmp2);
6537 } else {
6538 tcg_gen_sub_i32(tmp, tmp, tmp2);
6539 }
21aeb343 6540 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6541 }
6542 break;
6543 case 0x03:
e9bb4aa9
JR		 6544 if (set_cc) {
6545 gen_helper_sub_cc(tmp, tmp2, tmp);
6546 } else {
6547 tcg_gen_sub_i32(tmp, tmp2, tmp);
6548 }
21aeb343 6549 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6550 break;
6551 case 0x04:
e9bb4aa9
JR		 6552 if (set_cc) {
6553 gen_helper_add_cc(tmp, tmp, tmp2);
6554 } else {
6555 tcg_gen_add_i32(tmp, tmp, tmp2);
6556 }
21aeb343 6557 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6558 break;
6559 case 0x05:
e9bb4aa9
JR		 6560 if (set_cc) {
6561 gen_helper_adc_cc(tmp, tmp, tmp2);
6562 } else {
6563 gen_add_carry(tmp, tmp, tmp2);
6564 }
21aeb343 6565 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6566 break;
6567 case 0x06:
e9bb4aa9
JR		 6568 if (set_cc) {
6569 gen_helper_sbc_cc(tmp, tmp, tmp2);
6570 } else {
6571 gen_sub_carry(tmp, tmp, tmp2);
6572 }
21aeb343 6573 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6574 break;
6575 case 0x07:
e9bb4aa9
JR		 6576 if (set_cc) {
6577 gen_helper_sbc_cc(tmp, tmp2, tmp);
6578 } else {
6579 gen_sub_carry(tmp, tmp2, tmp);
6580 }
21aeb343 6581 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6582 break;
6583 case 0x08:
6584 if (set_cc) {
e9bb4aa9
JR		 6585 tcg_gen_and_i32(tmp, tmp, tmp2);
6586 gen_logic_CC(tmp);
9ee6e8bb 6587 }
e9bb4aa9 6588 dead_tmp(tmp);
9ee6e8bb
PB		 6589 break;
6590 case 0x09:
6591 if (set_cc) {
e9bb4aa9
JR		 6592 tcg_gen_xor_i32(tmp, tmp, tmp2);
6593 gen_logic_CC(tmp);
9ee6e8bb 6594 }
e9bb4aa9 6595 dead_tmp(tmp);
9ee6e8bb
PB		 6596 break;
6597 case 0x0a:
6598 if (set_cc) {
e9bb4aa9 6599 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6600 }
e9bb4aa9 6601 dead_tmp(tmp);
9ee6e8bb
PB		 6602 break;
6603 case 0x0b:
6604 if (set_cc) {
e9bb4aa9 6605 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6606 }
e9bb4aa9 6607 dead_tmp(tmp);
9ee6e8bb
PB		 6608 break;
6609 case 0x0c:
e9bb4aa9
JR		 6610 tcg_gen_or_i32(tmp, tmp, tmp2);
6611 if (logic_cc) {
6612 gen_logic_CC(tmp);
6613 }
21aeb343 6614 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6615 break;
6616 case 0x0d:
6617 if (logic_cc && rd == 15) {
6618 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6619 if (IS_USER(s)) {
9ee6e8bb 6620 goto illegal_op;
e9bb4aa9
JR		 6621 }
6622 gen_exception_return(s, tmp2);
9ee6e8bb 6623 } else {
e9bb4aa9
JR		 6624 if (logic_cc) {
6625 gen_logic_CC(tmp2);
6626 }
21aeb343 6627 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6628 }
6629 break;
6630 case 0x0e:
f669df27 6631 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6632 if (logic_cc) {
6633 gen_logic_CC(tmp);
6634 }
21aeb343 6635 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6636 break;
6637 default:
6638 case 0x0f:
e9bb4aa9
JR		 6639 tcg_gen_not_i32(tmp2, tmp2);
6640 if (logic_cc) {
6641 gen_logic_CC(tmp2);
6642 }
21aeb343 6643 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6644 break;
6645 }
e9bb4aa9
JR		 6646 if (op1 != 0x0f && op1 != 0x0d) {
6647 dead_tmp(tmp2);
6648 }
9ee6e8bb
PB		 6649 } else {
6650 /* other instructions */
6651 op1 = (insn >> 24) & 0xf;
6652 switch(op1) {
6653 case 0x0:
6654 case 0x1:
6655 /* multiplies, extra load/stores */
6656 sh = (insn >> 5) & 3;
6657 if (sh == 0) {
6658 if (op1 == 0x0) {
6659 rd = (insn >> 16) & 0xf;
6660 rn = (insn >> 12) & 0xf;
6661 rs = (insn >> 8) & 0xf;
6662 rm = (insn) & 0xf;
6663 op1 = (insn >> 20) & 0xf;
6664 switch (op1) {
6665 case 0: case 1: case 2: case 3: case 6:
6666 /* 32 bit mul */
5e3f878a
PB		 6667 tmp = load_reg(s, rs);
6668 tmp2 = load_reg(s, rm);
6669 tcg_gen_mul_i32(tmp, tmp, tmp2);
6670 dead_tmp(tmp2);
9ee6e8bb
PB		 6671 if (insn & (1 << 22)) {
6672 /* Subtract (mls) */
6673 ARCH(6T2);
5e3f878a
PB		 6674 tmp2 = load_reg(s, rn);
6675 tcg_gen_sub_i32(tmp, tmp2, tmp);
6676 dead_tmp(tmp2);
9ee6e8bb
PB		 6677 } else if (insn & (1 << 21)) {
6678 /* Add */
5e3f878a
PB		 6679 tmp2 = load_reg(s, rn);
6680 tcg_gen_add_i32(tmp, tmp, tmp2);
6681 dead_tmp(tmp2);
9ee6e8bb
PB		 6682 }
6683 if (insn & (1 << 20))
5e3f878a
PB		 6684 gen_logic_CC(tmp);
6685 store_reg(s, rd, tmp);
9ee6e8bb 6686 break;
8aac08b1
AJ		 6687 case 4:
6688 /* 64 bit mul double accumulate (UMAAL) */
6689 ARCH(6);
6690 tmp = load_reg(s, rs);
6691 tmp2 = load_reg(s, rm);
6692 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6693 gen_addq_lo(s, tmp64, rn);
6694 gen_addq_lo(s, tmp64, rd);
6695 gen_storeq_reg(s, rn, rd, tmp64);
6696 tcg_temp_free_i64(tmp64);
6697 break;
6698 case 8: case 9: case 10: case 11:
6699 case 12: case 13: case 14: case 15:
6700 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
5e3f878a
PB		 6701 tmp = load_reg(s, rs);
6702 tmp2 = load_reg(s, rm);
8aac08b1 6703 if (insn & (1 << 22)) {
a7812ae4 6704 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8aac08b1 6705 } else {
a7812ae4 6706 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8aac08b1
AJ		 6707 }
6708 if (insn & (1 << 21)) { /* mult accumulate */
a7812ae4 6709 gen_addq(s, tmp64, rn, rd);
9ee6e8bb 6710 }
8aac08b1 6711 if (insn & (1 << 20)) {
a7812ae4 6712 gen_logicq_cc(tmp64);
8aac08b1 6713 }
a7812ae4 6714 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6715 tcg_temp_free_i64(tmp64);
9ee6e8bb 6716 break;
8aac08b1
AJ		 6717 default:
6718 goto illegal_op;
9ee6e8bb
PB		 6719 }
6720 } else {
6721 rn = (insn >> 16) & 0xf;
6722 rd = (insn >> 12) & 0xf;
6723 if (insn & (1 << 23)) {
6724 /* load/store exclusive */
86753403
PB		 6725 op1 = (insn >> 21) & 0x3;
6726 if (op1)
a47f43d2 6727 ARCH(6K);
86753403
PB		 6728 else
6729 ARCH(6);
3174f8e9 6730 addr = tcg_temp_local_new_i32();
98a46317 6731 load_reg_var(s, addr, rn);
9ee6e8bb 6732 if (insn & (1 << 20)) {
86753403
PB		 6733 switch (op1) {
6734 case 0: /* ldrex */
426f5abc 6735 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6736 break;
6737 case 1: /* ldrexd */
426f5abc 6738 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6739 break;
6740 case 2: /* ldrexb */
426f5abc 6741 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6742 break;
6743 case 3: /* ldrexh */
426f5abc 6744 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6745 break;
6746 default:
6747 abort();
6748 }
9ee6e8bb
PB		 6749 } else {
6750 rm = insn & 0xf;
86753403
PB		 6751 switch (op1) {
6752 case 0: /* strex */
426f5abc 6753 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6754 break;
6755 case 1: /* strexd */
502e64fe 6756 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6757 break;
6758 case 2: /* strexb */
426f5abc 6759 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6760 break;
6761 case 3: /* strexh */
426f5abc 6762 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6763 break;
6764 default:
6765 abort();
6766 }
9ee6e8bb 6767 }
3174f8e9 6768 tcg_temp_free(addr);
9ee6e8bb
PB		 6769 } else {
6770 /* SWP instruction */
6771 rm = (insn) & 0xf;
6772
8984bd2e
PB		 6773 /* ??? This is not really atomic. However we know
6774 we never have multiple CPUs running in parallel,
6775 so it is good enough. */
6776 addr = load_reg(s, rn);
6777 tmp = load_reg(s, rm);
9ee6e8bb 6778 if (insn & (1 << 22)) {
8984bd2e
PB		 6779 tmp2 = gen_ld8u(addr, IS_USER(s));
6780 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6781 } else {
8984bd2e
PB		 6782 tmp2 = gen_ld32(addr, IS_USER(s));
6783 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6784 }
8984bd2e
PB		 6785 dead_tmp(addr);
6786 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6787 }
6788 }
6789 } else {
6790 int address_offset;
6791 int load;
6792 /* Misc load/store */
6793 rn = (insn >> 16) & 0xf;
6794 rd = (insn >> 12) & 0xf;
b0109805 6795 addr = load_reg(s, rn);
9ee6e8bb 6796 if (insn & (1 << 24))
b0109805 6797 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6798 address_offset = 0;
6799 if (insn & (1 << 20)) {
6800 /* load */
6801 switch(sh) {
6802 case 1:
b0109805 6803 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6804 break;
6805 case 2:
b0109805 6806 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6807 break;
6808 default:
6809 case 3:
b0109805 6810 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6811 break;
6812 }
6813 load = 1;
6814 } else if (sh & 2) {
6815 /* doubleword */
6816 if (sh & 1) {
6817 /* store */
b0109805
PB		 6818 tmp = load_reg(s, rd);
6819 gen_st32(tmp, addr, IS_USER(s));
6820 tcg_gen_addi_i32(addr, addr, 4);
6821 tmp = load_reg(s, rd + 1);
6822 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6823 load = 0;
6824 } else {
6825 /* load */
b0109805
PB		 6826 tmp = gen_ld32(addr, IS_USER(s));
6827 store_reg(s, rd, tmp);
6828 tcg_gen_addi_i32(addr, addr, 4);
6829 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6830 rd++;
6831 load = 1;
6832 }
6833 address_offset = -4;
6834 } else {
6835 /* store */
b0109805
PB		 6836 tmp = load_reg(s, rd);
6837 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6838 load = 0;
6839 }
6840 /* Perform base writeback before the loaded value to
6841 ensure correct behavior with overlapping index registers.
6842 ldrd with base writeback is is undefined if the
6843 destination and index registers overlap. */
6844 if (!(insn & (1 << 24))) {
b0109805
PB		 6845 gen_add_datah_offset(s, insn, address_offset, addr);
6846 store_reg(s, rn, addr);
9ee6e8bb
PB		 6847 } else if (insn & (1 << 21)) {
6848 if (address_offset)
b0109805
PB		 6849 tcg_gen_addi_i32(addr, addr, address_offset);
6850 store_reg(s, rn, addr);
6851 } else {
6852 dead_tmp(addr);
9ee6e8bb
PB		 6853 }
6854 if (load) {
6855 /* Complete the load. */
b0109805 6856 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6857 }
6858 }
6859 break;
6860 case 0x4:
6861 case 0x5:
6862 goto do_ldst;
6863 case 0x6:
6864 case 0x7:
6865 if (insn & (1 << 4)) {
6866 ARCH(6);
6867 /* Armv6 Media instructions. */
6868 rm = insn & 0xf;
6869 rn = (insn >> 16) & 0xf;
2c0262af 6870 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6871 rs = (insn >> 8) & 0xf;
6872 switch ((insn >> 23) & 3) {
6873 case 0: /* Parallel add/subtract. */
6874 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6875 tmp = load_reg(s, rn);
6876 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6877 sh = (insn >> 5) & 7;
6878 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6879 goto illegal_op;
6ddbc6e4
PB		 6880 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6881 dead_tmp(tmp2);
6882 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6883 break;
6884 case 1:
6885 if ((insn & 0x00700020) == 0) {
6c95676b 6886 /* Halfword pack. */
3670669c
PB		 6887 tmp = load_reg(s, rn);
6888 tmp2 = load_reg(s, rm);
9ee6e8bb 6889 shift = (insn >> 7) & 0x1f;
3670669c
PB		 6890 if (insn & (1 << 6)) {
6891 /* pkhtb */
22478e79
AZ		 6892 if (shift == 0)
6893 shift = 31;
6894 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 6895 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 6896 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 6897 } else {
6898 /* pkhbt */
22478e79
AZ		 6899 if (shift)
6900 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 6901 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 6902 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6903 }
6904 tcg_gen_or_i32(tmp, tmp, tmp2);
22478e79 6905 dead_tmp(tmp2);
3670669c 6906 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6907 } else if ((insn & 0x00200020) == 0x00200000) {
6908 /* [us]sat */
6ddbc6e4 6909 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6910 shift = (insn >> 7) & 0x1f;
6911 if (insn & (1 << 6)) {
6912 if (shift == 0)
6913 shift = 31;
6ddbc6e4 6914 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6915 } else {
6ddbc6e4 6916 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6917 }
6918 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 6919 tmp2 = tcg_const_i32(sh);
6920 if (insn & (1 << 22))
6921 gen_helper_usat(tmp, tmp, tmp2);
6922 else
6923 gen_helper_ssat(tmp, tmp, tmp2);
6924 tcg_temp_free_i32(tmp2);
6ddbc6e4 6925 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6926 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6927 /* [us]sat16 */
6ddbc6e4 6928 tmp = load_reg(s, rm);
9ee6e8bb 6929 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 6930 tmp2 = tcg_const_i32(sh);
6931 if (insn & (1 << 22))
6932 gen_helper_usat16(tmp, tmp, tmp2);
6933 else
6934 gen_helper_ssat16(tmp, tmp, tmp2);
6935 tcg_temp_free_i32(tmp2);
6ddbc6e4 6936 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6937 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6938 /* Select bytes. */
6ddbc6e4
PB		 6939 tmp = load_reg(s, rn);
6940 tmp2 = load_reg(s, rm);
6941 tmp3 = new_tmp();
6942 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6943 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6944 dead_tmp(tmp3);
6945 dead_tmp(tmp2);
6946 store_reg(s, rd, tmp);
9ee6e8bb 6947 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6948 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6949 shift = (insn >> 10) & 3;
6950 /* ??? In many cases it's not neccessary to do a
6951 rotate, a shift is sufficient. */
6952 if (shift != 0)
f669df27 6953 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6954 op1 = (insn >> 20) & 7;
6955 switch (op1) {
5e3f878a
PB		 6956 case 0: gen_sxtb16(tmp); break;
6957 case 2: gen_sxtb(tmp); break;
6958 case 3: gen_sxth(tmp); break;
6959 case 4: gen_uxtb16(tmp); break;
6960 case 6: gen_uxtb(tmp); break;
6961 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 6962 default: goto illegal_op;
6963 }
6964 if (rn != 15) {
5e3f878a 6965 tmp2 = load_reg(s, rn);
9ee6e8bb 6966 if ((op1 & 3) == 0) {
5e3f878a 6967 gen_add16(tmp, tmp2);
9ee6e8bb 6968 } else {
5e3f878a
PB		 6969 tcg_gen_add_i32(tmp, tmp, tmp2);
6970 dead_tmp(tmp2);
9ee6e8bb
PB		 6971 }
6972 }
6c95676b 6973 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6974 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6975 /* rev */
b0109805 6976 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6977 if (insn & (1 << 22)) {
6978 if (insn & (1 << 7)) {
b0109805 6979 gen_revsh(tmp);
9ee6e8bb
PB		 6980 } else {
6981 ARCH(6T2);
b0109805 6982 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 6983 }
6984 } else {
6985 if (insn & (1 << 7))
b0109805 6986 gen_rev16(tmp);
9ee6e8bb 6987 else
66896cb8 6988 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 6989 }
b0109805 6990 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6991 } else {
6992 goto illegal_op;
6993 }
6994 break;
6995 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 6996 tmp = load_reg(s, rm);
6997 tmp2 = load_reg(s, rs);
9ee6e8bb 6998 if (insn & (1 << 20)) {
838fa72d
AJ		 6999 /* Signed multiply most significant [accumulate].
7000 (SMMUL, SMMLA, SMMLS) */
a7812ae4 7001 tmp64 = gen_muls_i64_i32(tmp, tmp2);
838fa72d 7002
955a7dd5 7003 if (rd != 15) {
838fa72d 7004 tmp = load_reg(s, rd);
9ee6e8bb 7005 if (insn & (1 << 6)) {
838fa72d 7006 tmp64 = gen_subq_msw(tmp64, tmp);
9ee6e8bb 7007 } else {
838fa72d 7008 tmp64 = gen_addq_msw(tmp64, tmp);
9ee6e8bb
PB		 7009 }
7010 }
838fa72d
AJ		 7011 if (insn & (1 << 5)) {
7012 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7013 }
7014 tcg_gen_shri_i64(tmp64, tmp64, 32);
7015 tmp = new_tmp();
7016 tcg_gen_trunc_i64_i32(tmp, tmp64);
7017 tcg_temp_free_i64(tmp64);
955a7dd5 7018 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7019 } else {
7020 if (insn & (1 << 5))
5e3f878a
PB		 7021 gen_swap_half(tmp2);
7022 gen_smul_dual(tmp, tmp2);
7023 /* This addition cannot overflow. */
7024 if (insn & (1 << 6)) {
7025 tcg_gen_sub_i32(tmp, tmp, tmp2);
7026 } else {
7027 tcg_gen_add_i32(tmp, tmp, tmp2);
7028 }
7029 dead_tmp(tmp2);
9ee6e8bb 7030 if (insn & (1 << 22)) {
5e3f878a 7031 /* smlald, smlsld */
a7812ae4
PB		 7032 tmp64 = tcg_temp_new_i64();
7033 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7034 dead_tmp(tmp);
a7812ae4
PB		 7035 gen_addq(s, tmp64, rd, rn);
7036 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 7037 tcg_temp_free_i64(tmp64);
9ee6e8bb 7038 } else {
5e3f878a 7039 /* smuad, smusd, smlad, smlsd */
22478e79 7040 if (rd != 15)
9ee6e8bb 7041 {
22478e79 7042 tmp2 = load_reg(s, rd);
5e3f878a
PB		 7043 gen_helper_add_setq(tmp, tmp, tmp2);
7044 dead_tmp(tmp2);
9ee6e8bb 7045 }
22478e79 7046 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7047 }
7048 }
7049 break;
7050 case 3:
7051 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7052 switch (op1) {
7053 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 7054 ARCH(6);
7055 tmp = load_reg(s, rm);
7056 tmp2 = load_reg(s, rs);
7057 gen_helper_usad8(tmp, tmp, tmp2);
7058 dead_tmp(tmp2);
ded9d295
AZ		 7059 if (rd != 15) {
7060 tmp2 = load_reg(s, rd);
6ddbc6e4
PB		 7061 tcg_gen_add_i32(tmp, tmp, tmp2);
7062 dead_tmp(tmp2);
9ee6e8bb 7063 }
ded9d295 7064 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7065 break;
7066 case 0x20: case 0x24: case 0x28: case 0x2c:
7067 /* Bitfield insert/clear. */
7068 ARCH(6T2);
7069 shift = (insn >> 7) & 0x1f;
7070 i = (insn >> 16) & 0x1f;
7071 i = i + 1 - shift;
7072 if (rm == 15) {
5e3f878a
PB		 7073 tmp = new_tmp();
7074 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7075 } else {
5e3f878a 7076 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7077 }
7078 if (i != 32) {
5e3f878a 7079 tmp2 = load_reg(s, rd);
8f8e3aa4 7080 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
5e3f878a 7081 dead_tmp(tmp2);
9ee6e8bb 7082 }
5e3f878a 7083 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7084 break;
7085 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7086 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7087 ARCH(6T2);
5e3f878a 7088 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7089 shift = (insn >> 7) & 0x1f;
7090 i = ((insn >> 16) & 0x1f) + 1;
7091 if (shift + i > 32)
7092 goto illegal_op;
7093 if (i < 32) {
7094 if (op1 & 0x20) {
5e3f878a 7095 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7096 } else {
5e3f878a 7097 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7098 }
7099 }
5e3f878a 7100 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7101 break;
7102 default:
7103 goto illegal_op;
7104 }
7105 break;
7106 }
7107 break;
7108 }
7109 do_ldst:
7110 /* Check for undefined extension instructions
7111 * per the ARM Bible IE:
7112 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7113 */
7114 sh = (0xf << 20) | (0xf << 4);
7115 if (op1 == 0x7 && ((insn & sh) == sh))
7116 {
7117 goto illegal_op;
7118 }
7119 /* load/store byte/word */
7120 rn = (insn >> 16) & 0xf;
7121 rd = (insn >> 12) & 0xf;
b0109805 7122 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7123 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7124 if (insn & (1 << 24))
b0109805 7125 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7126 if (insn & (1 << 20)) {
7127 /* load */
9ee6e8bb 7128 if (insn & (1 << 22)) {
b0109805 7129 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7130 } else {
b0109805 7131 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7132 }
9ee6e8bb
PB		 7133 } else {
7134 /* store */
b0109805 7135 tmp = load_reg(s, rd);
9ee6e8bb 7136 if (insn & (1 << 22))
b0109805 7137 gen_st8(tmp, tmp2, i);
9ee6e8bb 7138 else
b0109805 7139 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7140 }
7141 if (!(insn & (1 << 24))) {
b0109805
PB		 7142 gen_add_data_offset(s, insn, tmp2);
7143 store_reg(s, rn, tmp2);
7144 } else if (insn & (1 << 21)) {
7145 store_reg(s, rn, tmp2);
7146 } else {
7147 dead_tmp(tmp2);
9ee6e8bb
PB		 7148 }
7149 if (insn & (1 << 20)) {
7150 /* Complete the load. */
7151 if (rd == 15)
b0109805 7152 gen_bx(s, tmp);
9ee6e8bb 7153 else
b0109805 7154 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7155 }
7156 break;
7157 case 0x08:
7158 case 0x09:
7159 {
7160 int j, n, user, loaded_base;
b0109805 7161 TCGv loaded_var;
9ee6e8bb
PB		 7162 /* load/store multiple words */
7163 /* XXX: store correct base if write back */
7164 user = 0;
7165 if (insn & (1 << 22)) {
7166 if (IS_USER(s))
7167 goto illegal_op; /* only usable in supervisor mode */
7168
7169 if ((insn & (1 << 15)) == 0)
7170 user = 1;
7171 }
7172 rn = (insn >> 16) & 0xf;
b0109805 7173 addr = load_reg(s, rn);
9ee6e8bb
PB		 7174
7175 /* compute total size */
7176 loaded_base = 0;
a50f5b91 7177 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7178 n = 0;
7179 for(i=0;i<16;i++) {
7180 if (insn & (1 << i))
7181 n++;
7182 }
7183 /* XXX: test invalid n == 0 case ? */
7184 if (insn & (1 << 23)) {
7185 if (insn & (1 << 24)) {
7186 /* pre increment */
b0109805 7187 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7188 } else {
7189 /* post increment */
7190 }
7191 } else {
7192 if (insn & (1 << 24)) {
7193 /* pre decrement */
b0109805 7194 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7195 } else {
7196 /* post decrement */
7197 if (n != 1)
b0109805 7198 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7199 }
7200 }
7201 j = 0;
7202 for(i=0;i<16;i++) {
7203 if (insn & (1 << i)) {
7204 if (insn & (1 << 20)) {
7205 /* load */
b0109805 7206 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7207 if (i == 15) {
b0109805 7208 gen_bx(s, tmp);
9ee6e8bb 7209 } else if (user) {
b75263d6
JR		 7210 tmp2 = tcg_const_i32(i);
7211 gen_helper_set_user_reg(tmp2, tmp);
7212 tcg_temp_free_i32(tmp2);
b0109805 7213 dead_tmp(tmp);
9ee6e8bb 7214 } else if (i == rn) {
b0109805 7215 loaded_var = tmp;
9ee6e8bb
PB		 7216 loaded_base = 1;
7217 } else {
b0109805 7218 store_reg(s, i, tmp);
9ee6e8bb
PB		 7219 }
7220 } else {
7221 /* store */
7222 if (i == 15) {
7223 /* special case: r15 = PC + 8 */
7224 val = (long)s->pc + 4;
b0109805
PB		 7225 tmp = new_tmp();
7226 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7227 } else if (user) {
b0109805 7228 tmp = new_tmp();
b75263d6
JR		 7229 tmp2 = tcg_const_i32(i);
7230 gen_helper_get_user_reg(tmp, tmp2);
7231 tcg_temp_free_i32(tmp2);
9ee6e8bb 7232 } else {
b0109805 7233 tmp = load_reg(s, i);
9ee6e8bb 7234 }
b0109805 7235 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7236 }
7237 j++;
7238 /* no need to add after the last transfer */
7239 if (j != n)
b0109805 7240 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7241 }
7242 }
7243 if (insn & (1 << 21)) {
7244 /* write back */
7245 if (insn & (1 << 23)) {
7246 if (insn & (1 << 24)) {
7247 /* pre increment */
7248 } else {
7249 /* post increment */
b0109805 7250 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7251 }
7252 } else {
7253 if (insn & (1 << 24)) {
7254 /* pre decrement */
7255 if (n != 1)
b0109805 7256 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7257 } else {
7258 /* post decrement */
b0109805 7259 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7260 }
7261 }
b0109805
PB		 7262 store_reg(s, rn, addr);
7263 } else {
7264 dead_tmp(addr);
9ee6e8bb
PB		 7265 }
7266 if (loaded_base) {
b0109805 7267 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7268 }
7269 if ((insn & (1 << 22)) && !user) {
7270 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7271 tmp = load_cpu_field(spsr);
7272 gen_set_cpsr(tmp, 0xffffffff);
7273 dead_tmp(tmp);
9ee6e8bb
PB		 7274 s->is_jmp = DISAS_UPDATE;
7275 }
7276 }
7277 break;
7278 case 0xa:
7279 case 0xb:
7280 {
7281 int32_t offset;
7282
7283 /* branch (and link) */
7284 val = (int32_t)s->pc;
7285 if (insn & (1 << 24)) {
5e3f878a
PB		 7286 tmp = new_tmp();
7287 tcg_gen_movi_i32(tmp, val);
7288 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7289 }
7290 offset = (((int32_t)insn << 8) >> 8);
7291 val += (offset << 2) + 4;
7292 gen_jmp(s, val);
7293 }
7294 break;
7295 case 0xc:
7296 case 0xd:
7297 case 0xe:
7298 /* Coprocessor. */
7299 if (disas_coproc_insn(env, s, insn))
7300 goto illegal_op;
7301 break;
7302 case 0xf:
7303 /* swi */
5e3f878a 7304 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7305 s->is_jmp = DISAS_SWI;
7306 break;
7307 default:
7308 illegal_op:
bc4a0de0 7309 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 7310 break;
7311 }
7312 }
7313}
7314
7315/* Return true if this is a Thumb-2 logical op. */
7316static int
7317thumb2_logic_op(int op)
7318{
7319 return (op < 8);
7320}
7321
7322/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7323 then set condition code flags based on the result of the operation.
7324 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7325 to the high bit of T1.
7326 Returns zero if the opcode is valid. */
7327
7328static int
396e467c 7329gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7330{
7331 int logic_cc;
7332
7333 logic_cc = 0;
7334 switch (op) {
7335 case 0: /* and */
396e467c 7336 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7337 logic_cc = conds;
7338 break;
7339 case 1: /* bic */
f669df27 7340 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7341 logic_cc = conds;
7342 break;
7343 case 2: /* orr */
396e467c 7344 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7345 logic_cc = conds;
7346 break;
7347 case 3: /* orn */
396e467c
FN		 7348 tcg_gen_not_i32(t1, t1);
7349 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7350 logic_cc = conds;
7351 break;
7352 case 4: /* eor */
396e467c 7353 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7354 logic_cc = conds;
7355 break;
7356 case 8: /* add */
7357 if (conds)
396e467c 7358 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7359 else
396e467c 7360 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7361 break;
7362 case 10: /* adc */
7363 if (conds)
396e467c 7364 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7365 else
396e467c 7366 gen_adc(t0, t1);
9ee6e8bb
PB		 7367 break;
7368 case 11: /* sbc */
7369 if (conds)
396e467c 7370 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7371 else
396e467c 7372 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7373 break;
7374 case 13: /* sub */
7375 if (conds)
396e467c 7376 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7377 else
396e467c 7378 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7379 break;
7380 case 14: /* rsb */
7381 if (conds)
396e467c 7382 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7383 else
396e467c 7384 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7385 break;
7386 default: /* 5, 6, 7, 9, 12, 15. */
7387 return 1;
7388 }
7389 if (logic_cc) {
396e467c 7390 gen_logic_CC(t0);
9ee6e8bb 7391 if (shifter_out)
396e467c 7392 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7393 }
7394 return 0;
7395}
7396
7397/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7398 is not legal. */
7399static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7400{
b0109805 7401 uint32_t insn, imm, shift, offset;
9ee6e8bb 7402 uint32_t rd, rn, rm, rs;
b26eefb6 7403 TCGv tmp;
6ddbc6e4
PB		 7404 TCGv tmp2;
7405 TCGv tmp3;
b0109805 7406 TCGv addr;
a7812ae4 7407 TCGv_i64 tmp64;
9ee6e8bb
PB		 7408 int op;
7409 int shiftop;
7410 int conds;
7411 int logic_cc;
7412
7413 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7414 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7415 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7416 16-bit instructions to get correct prefetch abort behavior. */
7417 insn = insn_hw1;
7418 if ((insn & (1 << 12)) == 0) {
7419 /* Second half of blx. */
7420 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7421 tmp = load_reg(s, 14);
7422 tcg_gen_addi_i32(tmp, tmp, offset);
7423 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7424
d9ba4830 7425 tmp2 = new_tmp();
b0109805 7426 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7427 store_reg(s, 14, tmp2);
7428 gen_bx(s, tmp);
9ee6e8bb
PB		 7429 return 0;
7430 }
7431 if (insn & (1 << 11)) {
7432 /* Second half of bl. */
7433 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7434 tmp = load_reg(s, 14);
6a0d8a1d 7435 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7436
d9ba4830 7437 tmp2 = new_tmp();
b0109805 7438 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7439 store_reg(s, 14, tmp2);
7440 gen_bx(s, tmp);
9ee6e8bb
PB		 7441 return 0;
7442 }
7443 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7444 /* Instruction spans a page boundary. Implement it as two
7445 16-bit instructions in case the second half causes an
7446 prefetch abort. */
7447 offset = ((int32_t)insn << 21) >> 9;
396e467c 7448 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7449 return 0;
7450 }
7451 /* Fall through to 32-bit decode. */
7452 }
7453
7454 insn = lduw_code(s->pc);
7455 s->pc += 2;
7456 insn |= (uint32_t)insn_hw1 << 16;
7457
7458 if ((insn & 0xf800e800) != 0xf000e800) {
7459 ARCH(6T2);
7460 }
7461
7462 rn = (insn >> 16) & 0xf;
7463 rs = (insn >> 12) & 0xf;
7464 rd = (insn >> 8) & 0xf;
7465 rm = insn & 0xf;
7466 switch ((insn >> 25) & 0xf) {
7467 case 0: case 1: case 2: case 3:
7468 /* 16-bit instructions. Should never happen. */
7469 abort();
7470 case 4:
7471 if (insn & (1 << 22)) {
7472 /* Other load/store, table branch. */
7473 if (insn & 0x01200000) {
7474 /* Load/store doubleword. */
7475 if (rn == 15) {
b0109805
PB		 7476 addr = new_tmp();
7477 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7478 } else {
b0109805 7479 addr = load_reg(s, rn);
9ee6e8bb
PB		 7480 }
7481 offset = (insn & 0xff) * 4;
7482 if ((insn & (1 << 23)) == 0)
7483 offset = -offset;
7484 if (insn & (1 << 24)) {
b0109805 7485 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7486 offset = 0;
7487 }
7488 if (insn & (1 << 20)) {
7489 /* ldrd */
b0109805
PB		 7490 tmp = gen_ld32(addr, IS_USER(s));
7491 store_reg(s, rs, tmp);
7492 tcg_gen_addi_i32(addr, addr, 4);
7493 tmp = gen_ld32(addr, IS_USER(s));
7494 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7495 } else {
7496 /* strd */
b0109805
PB		 7497 tmp = load_reg(s, rs);
7498 gen_st32(tmp, addr, IS_USER(s));
7499 tcg_gen_addi_i32(addr, addr, 4);
7500 tmp = load_reg(s, rd);
7501 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7502 }
7503 if (insn & (1 << 21)) {
7504 /* Base writeback. */
7505 if (rn == 15)
7506 goto illegal_op;
b0109805
PB		 7507 tcg_gen_addi_i32(addr, addr, offset - 4);
7508 store_reg(s, rn, addr);
7509 } else {
7510 dead_tmp(addr);
9ee6e8bb
PB		 7511 }
7512 } else if ((insn & (1 << 23)) == 0) {
7513 /* Load/store exclusive word. */
3174f8e9 7514 addr = tcg_temp_local_new();
98a46317 7515 load_reg_var(s, addr, rn);
426f5abc 7516 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7517 if (insn & (1 << 20)) {
426f5abc 7518 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7519 } else {
426f5abc 7520 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7521 }
3174f8e9 7522 tcg_temp_free(addr);
9ee6e8bb
PB		 7523 } else if ((insn & (1 << 6)) == 0) {
7524 /* Table Branch. */
7525 if (rn == 15) {
b0109805
PB		 7526 addr = new_tmp();
7527 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7528 } else {
b0109805 7529 addr = load_reg(s, rn);
9ee6e8bb 7530 }
b26eefb6 7531 tmp = load_reg(s, rm);
b0109805 7532 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7533 if (insn & (1 << 4)) {
7534 /* tbh */
b0109805 7535 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7536 dead_tmp(tmp);
b0109805 7537 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7538 } else { /* tbb */
b26eefb6 7539 dead_tmp(tmp);
b0109805 7540 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7541 }
b0109805
PB		 7542 dead_tmp(addr);
7543 tcg_gen_shli_i32(tmp, tmp, 1);
7544 tcg_gen_addi_i32(tmp, tmp, s->pc);
7545 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7546 } else {
7547 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7548 ARCH(7);
9ee6e8bb 7549 op = (insn >> 4) & 0x3;
426f5abc
PB		 7550 if (op == 2) {
7551 goto illegal_op;
7552 }
3174f8e9 7553 addr = tcg_temp_local_new();
98a46317 7554 load_reg_var(s, addr, rn);
9ee6e8bb 7555 if (insn & (1 << 20)) {
426f5abc 7556 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7557 } else {
426f5abc 7558 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7559 }
3174f8e9 7560 tcg_temp_free(addr);
9ee6e8bb
PB		 7561 }
7562 } else {
7563 /* Load/store multiple, RFE, SRS. */
7564 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7565 /* Not available in user mode. */
b0109805 7566 if (IS_USER(s))
9ee6e8bb
PB		 7567 goto illegal_op;
7568 if (insn & (1 << 20)) {
7569 /* rfe */
b0109805
PB		 7570 addr = load_reg(s, rn);
7571 if ((insn & (1 << 24)) == 0)
7572 tcg_gen_addi_i32(addr, addr, -8);
7573 /* Load PC into tmp and CPSR into tmp2. */
7574 tmp = gen_ld32(addr, 0);
7575 tcg_gen_addi_i32(addr, addr, 4);
7576 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7577 if (insn & (1 << 21)) {
7578 /* Base writeback. */
b0109805
PB		 7579 if (insn & (1 << 24)) {
7580 tcg_gen_addi_i32(addr, addr, 4);
7581 } else {
7582 tcg_gen_addi_i32(addr, addr, -4);
7583 }
7584 store_reg(s, rn, addr);
7585 } else {
7586 dead_tmp(addr);
9ee6e8bb 7587 }
b0109805 7588 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7589 } else {
7590 /* srs */
7591 op = (insn & 0x1f);
39ea3d4e
PM		 7592 addr = new_tmp();
7593 tmp = tcg_const_i32(op);
7594 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7595 tcg_temp_free_i32(tmp);
9ee6e8bb 7596 if ((insn & (1 << 24)) == 0) {
b0109805 7597 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7598 }
b0109805
PB		 7599 tmp = load_reg(s, 14);
7600 gen_st32(tmp, addr, 0);
7601 tcg_gen_addi_i32(addr, addr, 4);
7602 tmp = new_tmp();
7603 gen_helper_cpsr_read(tmp);
7604 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7605 if (insn & (1 << 21)) {
7606 if ((insn & (1 << 24)) == 0) {
b0109805 7607 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7608 } else {
b0109805 7609 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb 7610 }
39ea3d4e
PM		 7611 tmp = tcg_const_i32(op);
7612 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7613 tcg_temp_free_i32(tmp);
b0109805
PB		 7614 } else {
7615 dead_tmp(addr);
9ee6e8bb
PB		 7616 }
7617 }
7618 } else {
7619 int i;
7620 /* Load/store multiple. */
b0109805 7621 addr = load_reg(s, rn);
9ee6e8bb
PB		 7622 offset = 0;
7623 for (i = 0; i < 16; i++) {
7624 if (insn & (1 << i))
7625 offset += 4;
7626 }
7627 if (insn & (1 << 24)) {
b0109805 7628 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7629 }
7630
7631 for (i = 0; i < 16; i++) {
7632 if ((insn & (1 << i)) == 0)
7633 continue;
7634 if (insn & (1 << 20)) {
7635 /* Load. */
b0109805 7636 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7637 if (i == 15) {
b0109805 7638 gen_bx(s, tmp);
9ee6e8bb 7639 } else {
b0109805 7640 store_reg(s, i, tmp);
9ee6e8bb
PB		 7641 }
7642 } else {
7643 /* Store. */
b0109805
PB		 7644 tmp = load_reg(s, i);
7645 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7646 }
b0109805 7647 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7648 }
7649 if (insn & (1 << 21)) {
7650 /* Base register writeback. */
7651 if (insn & (1 << 24)) {
b0109805 7652 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7653 }
7654 /* Fault if writeback register is in register list. */
7655 if (insn & (1 << rn))
7656 goto illegal_op;
b0109805
PB		 7657 store_reg(s, rn, addr);
7658 } else {
7659 dead_tmp(addr);
9ee6e8bb
PB		 7660 }
7661 }
7662 }
7663 break;
2af9ab77
JB		 7664 case 5:
7665
9ee6e8bb 7666 op = (insn >> 21) & 0xf;
2af9ab77
JB		 7667 if (op == 6) {
7668 /* Halfword pack. */
7669 tmp = load_reg(s, rn);
7670 tmp2 = load_reg(s, rm);
7671 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7672 if (insn & (1 << 5)) {
7673 /* pkhtb */
7674 if (shift == 0)
7675 shift = 31;
7676 tcg_gen_sari_i32(tmp2, tmp2, shift);
7677 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7678 tcg_gen_ext16u_i32(tmp2, tmp2);
7679 } else {
7680 /* pkhbt */
7681 if (shift)
7682 tcg_gen_shli_i32(tmp2, tmp2, shift);
7683 tcg_gen_ext16u_i32(tmp, tmp);
7684 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7685 }
7686 tcg_gen_or_i32(tmp, tmp, tmp2);
7687 dead_tmp(tmp2);
3174f8e9
FN		 7688 store_reg(s, rd, tmp);
7689 } else {
2af9ab77
JB		 7690 /* Data processing register constant shift. */
7691 if (rn == 15) {
7692 tmp = new_tmp();
7693 tcg_gen_movi_i32(tmp, 0);
7694 } else {
7695 tmp = load_reg(s, rn);
7696 }
7697 tmp2 = load_reg(s, rm);
7698
7699 shiftop = (insn >> 4) & 3;
7700 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7701 conds = (insn & (1 << 20)) != 0;
7702 logic_cc = (conds && thumb2_logic_op(op));
7703 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7704 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7705 goto illegal_op;
7706 dead_tmp(tmp2);
7707 if (rd != 15) {
7708 store_reg(s, rd, tmp);
7709 } else {
7710 dead_tmp(tmp);
7711 }
3174f8e9 7712 }
9ee6e8bb
PB		 7713 break;
7714 case 13: /* Misc data processing. */
7715 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7716 if (op < 4 && (insn & 0xf000) != 0xf000)
7717 goto illegal_op;
7718 switch (op) {
7719 case 0: /* Register controlled shift. */
8984bd2e
PB		 7720 tmp = load_reg(s, rn);
7721 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7722 if ((insn & 0x70) != 0)
7723 goto illegal_op;
7724 op = (insn >> 21) & 3;
8984bd2e
PB		 7725 logic_cc = (insn & (1 << 20)) != 0;
7726 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7727 if (logic_cc)
7728 gen_logic_CC(tmp);
21aeb343 7729 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7730 break;
7731 case 1: /* Sign/zero extend. */
5e3f878a 7732 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7733 shift = (insn >> 4) & 3;
7734 /* ??? In many cases it's not neccessary to do a
7735 rotate, a shift is sufficient. */
7736 if (shift != 0)
f669df27 7737 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7738 op = (insn >> 20) & 7;
7739 switch (op) {
5e3f878a
PB		 7740 case 0: gen_sxth(tmp); break;
7741 case 1: gen_uxth(tmp); break;
7742 case 2: gen_sxtb16(tmp); break;
7743 case 3: gen_uxtb16(tmp); break;
7744 case 4: gen_sxtb(tmp); break;
7745 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7746 default: goto illegal_op;
7747 }
7748 if (rn != 15) {
5e3f878a 7749 tmp2 = load_reg(s, rn);
9ee6e8bb 7750 if ((op >> 1) == 1) {
5e3f878a 7751 gen_add16(tmp, tmp2);
9ee6e8bb 7752 } else {
5e3f878a
PB		 7753 tcg_gen_add_i32(tmp, tmp, tmp2);
7754 dead_tmp(tmp2);
9ee6e8bb
PB		 7755 }
7756 }
5e3f878a 7757 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7758 break;
7759 case 2: /* SIMD add/subtract. */
7760 op = (insn >> 20) & 7;
7761 shift = (insn >> 4) & 7;
7762 if ((op & 3) == 3 || (shift & 3) == 3)
7763 goto illegal_op;
6ddbc6e4
PB		 7764 tmp = load_reg(s, rn);
7765 tmp2 = load_reg(s, rm);
7766 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7767 dead_tmp(tmp2);
7768 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7769 break;
7770 case 3: /* Other data processing. */
7771 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7772 if (op < 4) {
7773 /* Saturating add/subtract. */
d9ba4830
PB		 7774 tmp = load_reg(s, rn);
7775 tmp2 = load_reg(s, rm);
9ee6e8bb 7776 if (op & 1)
4809c612
JB		 7777 gen_helper_double_saturate(tmp, tmp);
7778 if (op & 2)
d9ba4830 7779 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7780 else
d9ba4830
PB		 7781 gen_helper_add_saturate(tmp, tmp, tmp2);
7782 dead_tmp(tmp2);
9ee6e8bb 7783 } else {
d9ba4830 7784 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7785 switch (op) {
7786 case 0x0a: /* rbit */
d9ba4830 7787 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7788 break;
7789 case 0x08: /* rev */
66896cb8 7790 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7791 break;
7792 case 0x09: /* rev16 */
d9ba4830 7793 gen_rev16(tmp);
9ee6e8bb
PB		 7794 break;
7795 case 0x0b: /* revsh */
d9ba4830 7796 gen_revsh(tmp);
9ee6e8bb
PB		 7797 break;
7798 case 0x10: /* sel */
d9ba4830 7799 tmp2 = load_reg(s, rm);
6ddbc6e4
PB		 7800 tmp3 = new_tmp();
7801 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7802 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6ddbc6e4 7803 dead_tmp(tmp3);
d9ba4830 7804 dead_tmp(tmp2);
9ee6e8bb
PB		 7805 break;
7806 case 0x18: /* clz */
d9ba4830 7807 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7808 break;
7809 default:
7810 goto illegal_op;
7811 }
7812 }
d9ba4830 7813 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7814 break;
7815 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7816 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7817 tmp = load_reg(s, rn);
7818 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7819 switch ((insn >> 20) & 7) {
7820 case 0: /* 32 x 32 -> 32 */
d9ba4830
PB		 7821 tcg_gen_mul_i32(tmp, tmp, tmp2);
7822 dead_tmp(tmp2);
9ee6e8bb 7823 if (rs != 15) {
d9ba4830 7824 tmp2 = load_reg(s, rs);
9ee6e8bb 7825 if (op)
d9ba4830 7826 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7827 else
d9ba4830
PB		 7828 tcg_gen_add_i32(tmp, tmp, tmp2);
7829 dead_tmp(tmp2);
9ee6e8bb 7830 }
9ee6e8bb
PB		 7831 break;
7832 case 1: /* 16 x 16 -> 32 */
d9ba4830
PB		 7833 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7834 dead_tmp(tmp2);
9ee6e8bb 7835 if (rs != 15) {
d9ba4830
PB		 7836 tmp2 = load_reg(s, rs);
7837 gen_helper_add_setq(tmp, tmp, tmp2);
7838 dead_tmp(tmp2);
9ee6e8bb 7839 }
9ee6e8bb
PB		 7840 break;
7841 case 2: /* Dual multiply add. */
7842 case 4: /* Dual multiply subtract. */
7843 if (op)
d9ba4830
PB		 7844 gen_swap_half(tmp2);
7845 gen_smul_dual(tmp, tmp2);
9ee6e8bb
PB		 7846 /* This addition cannot overflow. */
7847 if (insn & (1 << 22)) {
d9ba4830 7848 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7849 } else {
d9ba4830 7850 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 7851 }
d9ba4830 7852 dead_tmp(tmp2);
9ee6e8bb
PB		 7853 if (rs != 15)
7854 {
d9ba4830
PB		 7855 tmp2 = load_reg(s, rs);
7856 gen_helper_add_setq(tmp, tmp, tmp2);
7857 dead_tmp(tmp2);
9ee6e8bb 7858 }
9ee6e8bb
PB		 7859 break;
7860 case 3: /* 32 * 16 -> 32msb */
7861 if (op)
d9ba4830 7862 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7863 else
d9ba4830 7864 gen_sxth(tmp2);
a7812ae4
PB		 7865 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7866 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 7867 tmp = new_tmp();
a7812ae4 7868 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 7869 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7870 if (rs != 15)
7871 {
d9ba4830
PB		 7872 tmp2 = load_reg(s, rs);
7873 gen_helper_add_setq(tmp, tmp, tmp2);
7874 dead_tmp(tmp2);
9ee6e8bb 7875 }
9ee6e8bb 7876 break;
838fa72d
AJ		 7877 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7878 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7879 if (rs != 15) {
838fa72d
AJ		 7880 tmp = load_reg(s, rs);
7881 if (insn & (1 << 20)) {
7882 tmp64 = gen_addq_msw(tmp64, tmp);
99c475ab 7883 } else {
838fa72d 7884 tmp64 = gen_subq_msw(tmp64, tmp);
99c475ab 7885 }
2c0262af 7886 }
838fa72d
AJ		 7887 if (insn & (1 << 4)) {
7888 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7889 }
7890 tcg_gen_shri_i64(tmp64, tmp64, 32);
7891 tmp = new_tmp();
7892 tcg_gen_trunc_i64_i32(tmp, tmp64);
7893 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7894 break;
7895 case 7: /* Unsigned sum of absolute differences. */
d9ba4830
PB		 7896 gen_helper_usad8(tmp, tmp, tmp2);
7897 dead_tmp(tmp2);
9ee6e8bb 7898 if (rs != 15) {
d9ba4830
PB		 7899 tmp2 = load_reg(s, rs);
7900 tcg_gen_add_i32(tmp, tmp, tmp2);
7901 dead_tmp(tmp2);
5fd46862 7902 }
9ee6e8bb 7903 break;
2c0262af 7904 }
d9ba4830 7905 store_reg(s, rd, tmp);
2c0262af 7906 break;
9ee6e8bb
PB		 7907 case 6: case 7: /* 64-bit multiply, Divide. */
7908 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7909 tmp = load_reg(s, rn);
7910 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7911 if ((op & 0x50) == 0x10) {
7912 /* sdiv, udiv */
7913 if (!arm_feature(env, ARM_FEATURE_DIV))
7914 goto illegal_op;
7915 if (op & 0x20)
5e3f878a 7916 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7917 else
5e3f878a
PB		 7918 gen_helper_sdiv(tmp, tmp, tmp2);
7919 dead_tmp(tmp2);
7920 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7921 } else if ((op & 0xe) == 0xc) {
7922 /* Dual multiply accumulate long. */
7923 if (op & 1)
5e3f878a
PB		 7924 gen_swap_half(tmp2);
7925 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7926 if (op & 0x10) {
5e3f878a 7927 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7928 } else {
5e3f878a 7929 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7930 }
5e3f878a 7931 dead_tmp(tmp2);
a7812ae4
PB		 7932 /* BUGFIX */
7933 tmp64 = tcg_temp_new_i64();
7934 tcg_gen_ext_i32_i64(tmp64, tmp);
7935 dead_tmp(tmp);
7936 gen_addq(s, tmp64, rs, rd);
7937 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7938 tcg_temp_free_i64(tmp64);
2c0262af 7939 } else {
9ee6e8bb
PB		 7940 if (op & 0x20) {
7941 /* Unsigned 64-bit multiply */
a7812ae4 7942 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7943 } else {
9ee6e8bb
PB		 7944 if (op & 8) {
7945 /* smlalxy */
5e3f878a
PB		 7946 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7947 dead_tmp(tmp2);
a7812ae4
PB		 7948 tmp64 = tcg_temp_new_i64();
7949 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7950 dead_tmp(tmp);
9ee6e8bb
PB		 7951 } else {
7952 /* Signed 64-bit multiply */
a7812ae4 7953 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7954 }
b5ff1b31 7955 }
9ee6e8bb
PB		 7956 if (op & 4) {
7957 /* umaal */
a7812ae4
PB		 7958 gen_addq_lo(s, tmp64, rs);
7959 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 7960 } else if (op & 0x40) {
7961 /* 64-bit accumulate. */
a7812ae4 7962 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 7963 }
a7812ae4 7964 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7965 tcg_temp_free_i64(tmp64);
5fd46862 7966 }
2c0262af 7967 break;
9ee6e8bb
PB		 7968 }
7969 break;
7970 case 6: case 7: case 14: case 15:
7971 /* Coprocessor. */
7972 if (((insn >> 24) & 3) == 3) {
7973 /* Translate into the equivalent ARM encoding. */
7974 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7975 if (disas_neon_data_insn(env, s, insn))
7976 goto illegal_op;
7977 } else {
7978 if (insn & (1 << 28))
7979 goto illegal_op;
7980 if (disas_coproc_insn (env, s, insn))
7981 goto illegal_op;
7982 }
7983 break;
7984 case 8: case 9: case 10: case 11:
7985 if (insn & (1 << 15)) {
7986 /* Branches, misc control. */
7987 if (insn & 0x5000) {
7988 /* Unconditional branch. */
7989 /* signextend(hw1[10:0]) -> offset[:12]. */
7990 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7991 /* hw1[10:0] -> offset[11:1]. */
7992 offset |= (insn & 0x7ff) << 1;
7993 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7994 offset[24:22] already have the same value because of the
7995 sign extension above. */
7996 offset ^= ((~insn) & (1 << 13)) << 10;
7997 offset ^= ((~insn) & (1 << 11)) << 11;
7998
9ee6e8bb
PB		 7999 if (insn & (1 << 14)) {
8000 /* Branch and link. */
3174f8e9 8001 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 8002 }
3b46e624 8003
b0109805 8004 offset += s->pc;
9ee6e8bb
PB		 8005 if (insn & (1 << 12)) {
8006 /* b/bl */
b0109805 8007 gen_jmp(s, offset);
9ee6e8bb
PB		 8008 } else {
8009 /* blx */
b0109805
PB		 8010 offset &= ~(uint32_t)2;
8011 gen_bx_im(s, offset);
2c0262af 8012 }
9ee6e8bb
PB		 8013 } else if (((insn >> 23) & 7) == 7) {
8014 /* Misc control */
8015 if (insn & (1 << 13))
8016 goto illegal_op;
8017
8018 if (insn & (1 << 26)) {
8019 /* Secure monitor call (v6Z) */
8020 goto illegal_op; /* not implemented. */
2c0262af 8021 } else {
9ee6e8bb
PB		 8022 op = (insn >> 20) & 7;
8023 switch (op) {
8024 case 0: /* msr cpsr. */
8025 if (IS_M(env)) {
8984bd2e
PB		 8026 tmp = load_reg(s, rn);
8027 addr = tcg_const_i32(insn & 0xff);
8028 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6
JR		 8029 tcg_temp_free_i32(addr);
8030 dead_tmp(tmp);
9ee6e8bb
PB		 8031 gen_lookup_tb(s);
8032 break;
8033 }
8034 /* fall through */
8035 case 1: /* msr spsr. */
8036 if (IS_M(env))
8037 goto illegal_op;
2fbac54b
FN		 8038 tmp = load_reg(s, rn);
8039 if (gen_set_psr(s,
9ee6e8bb 8040 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 8041 op == 1, tmp))
9ee6e8bb
PB		 8042 goto illegal_op;
8043 break;
8044 case 2: /* cps, nop-hint. */
8045 if (((insn >> 8) & 7) == 0) {
8046 gen_nop_hint(s, insn & 0xff);
8047 }
8048 /* Implemented as NOP in user mode. */
8049 if (IS_USER(s))
8050 break;
8051 offset = 0;
8052 imm = 0;
8053 if (insn & (1 << 10)) {
8054 if (insn & (1 << 7))
8055 offset |= CPSR_A;
8056 if (insn & (1 << 6))
8057 offset |= CPSR_I;
8058 if (insn & (1 << 5))
8059 offset |= CPSR_F;
8060 if (insn & (1 << 9))
8061 imm = CPSR_A | CPSR_I | CPSR_F;
8062 }
8063 if (insn & (1 << 8)) {
8064 offset |= 0x1f;
8065 imm |= (insn & 0x1f);
8066 }
8067 if (offset) {
2fbac54b 8068 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 8069 }
8070 break;
8071 case 3: /* Special control operations. */
426f5abc 8072 ARCH(7);
9ee6e8bb
PB		 8073 op = (insn >> 4) & 0xf;
8074 switch (op) {
8075 case 2: /* clrex */
426f5abc 8076 gen_clrex(s);
9ee6e8bb
PB		 8077 break;
8078 case 4: /* dsb */
8079 case 5: /* dmb */
8080 case 6: /* isb */
8081 /* These execute as NOPs. */
9ee6e8bb
PB		 8082 break;
8083 default:
8084 goto illegal_op;
8085 }
8086 break;
8087 case 4: /* bxj */
8088 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8089 tmp = load_reg(s, rn);
8090 gen_bx(s, tmp);
9ee6e8bb
PB		 8091 break;
8092 case 5: /* Exception return. */
b8b45b68
RV		 8093 if (IS_USER(s)) {
8094 goto illegal_op;
8095 }
8096 if (rn != 14 || rd != 15) {
8097 goto illegal_op;
8098 }
8099 tmp = load_reg(s, rn);
8100 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8101 gen_exception_return(s, tmp);
8102 break;
9ee6e8bb 8103 case 6: /* mrs cpsr. */
8984bd2e 8104 tmp = new_tmp();
9ee6e8bb 8105 if (IS_M(env)) {
8984bd2e
PB		 8106 addr = tcg_const_i32(insn & 0xff);
8107 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8108 tcg_temp_free_i32(addr);
9ee6e8bb 8109 } else {
8984bd2e 8110 gen_helper_cpsr_read(tmp);
9ee6e8bb 8111 }
8984bd2e 8112 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8113 break;
8114 case 7: /* mrs spsr. */
8115 /* Not accessible in user mode. */
8116 if (IS_USER(s) || IS_M(env))
8117 goto illegal_op;
d9ba4830
PB		 8118 tmp = load_cpu_field(spsr);
8119 store_reg(s, rd, tmp);
9ee6e8bb 8120 break;
2c0262af
FB		 8121 }
8122 }
9ee6e8bb
PB		 8123 } else {
8124 /* Conditional branch. */
8125 op = (insn >> 22) & 0xf;
8126 /* Generate a conditional jump to next instruction. */
8127 s->condlabel = gen_new_label();
d9ba4830 8128 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8129 s->condjmp = 1;
8130
8131 /* offset[11:1] = insn[10:0] */
8132 offset = (insn & 0x7ff) << 1;
8133 /* offset[17:12] = insn[21:16]. */
8134 offset |= (insn & 0x003f0000) >> 4;
8135 /* offset[31:20] = insn[26]. */
8136 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8137 /* offset[18] = insn[13]. */
8138 offset |= (insn & (1 << 13)) << 5;
8139 /* offset[19] = insn[11]. */
8140 offset |= (insn & (1 << 11)) << 8;
8141
8142 /* jump to the offset */
b0109805 8143 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8144 }
8145 } else {
8146 /* Data processing immediate. */
8147 if (insn & (1 << 25)) {
8148 if (insn & (1 << 24)) {
8149 if (insn & (1 << 20))
8150 goto illegal_op;
8151 /* Bitfield/Saturate. */
8152 op = (insn >> 21) & 7;
8153 imm = insn & 0x1f;
8154 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4
PB		 8155 if (rn == 15) {
8156 tmp = new_tmp();
8157 tcg_gen_movi_i32(tmp, 0);
8158 } else {
8159 tmp = load_reg(s, rn);
8160 }
9ee6e8bb
PB		 8161 switch (op) {
8162 case 2: /* Signed bitfield extract. */
8163 imm++;
8164 if (shift + imm > 32)
8165 goto illegal_op;
8166 if (imm < 32)
6ddbc6e4 8167 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8168 break;
8169 case 6: /* Unsigned bitfield extract. */
8170 imm++;
8171 if (shift + imm > 32)
8172 goto illegal_op;
8173 if (imm < 32)
6ddbc6e4 8174 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8175 break;
8176 case 3: /* Bitfield insert/clear. */
8177 if (imm < shift)
8178 goto illegal_op;
8179 imm = imm + 1 - shift;
8180 if (imm != 32) {
6ddbc6e4 8181 tmp2 = load_reg(s, rd);
8f8e3aa4 8182 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
6ddbc6e4 8183 dead_tmp(tmp2);
9ee6e8bb
PB		 8184 }
8185 break;
8186 case 7:
8187 goto illegal_op;
8188 default: /* Saturate. */
9ee6e8bb
PB		 8189 if (shift) {
8190 if (op & 1)
6ddbc6e4 8191 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8192 else
6ddbc6e4 8193 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8194 }
6ddbc6e4 8195 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8196 if (op & 4) {
8197 /* Unsigned. */
9ee6e8bb 8198 if ((op & 1) && shift == 0)
6ddbc6e4 8199 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8200 else
6ddbc6e4 8201 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8202 } else {
9ee6e8bb 8203 /* Signed. */
9ee6e8bb 8204 if ((op & 1) && shift == 0)
6ddbc6e4 8205 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8206 else
6ddbc6e4 8207 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8208 }
b75263d6 8209 tcg_temp_free_i32(tmp2);
9ee6e8bb 8210 break;
2c0262af 8211 }
6ddbc6e4 8212 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8213 } else {
8214 imm = ((insn & 0x04000000) >> 15)
8215 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8216 if (insn & (1 << 22)) {
8217 /* 16-bit immediate. */
8218 imm |= (insn >> 4) & 0xf000;
8219 if (insn & (1 << 23)) {
8220 /* movt */
5e3f878a 8221 tmp = load_reg(s, rd);
86831435 8222 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8223 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8224 } else {
9ee6e8bb 8225 /* movw */
5e3f878a
PB		 8226 tmp = new_tmp();
8227 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8228 }
8229 } else {
9ee6e8bb
PB		 8230 /* Add/sub 12-bit immediate. */
8231 if (rn == 15) {
b0109805 8232 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8233 if (insn & (1 << 23))
b0109805 8234 offset -= imm;
9ee6e8bb 8235 else
b0109805 8236 offset += imm;
5e3f878a
PB		 8237 tmp = new_tmp();
8238 tcg_gen_movi_i32(tmp, offset);
2c0262af 8239 } else {
5e3f878a 8240 tmp = load_reg(s, rn);
9ee6e8bb 8241 if (insn & (1 << 23))
5e3f878a 8242 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8243 else
5e3f878a 8244 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8245 }
9ee6e8bb 8246 }
5e3f878a 8247 store_reg(s, rd, tmp);
191abaa2 8248 }
9ee6e8bb
PB		 8249 } else {
8250 int shifter_out = 0;
8251 /* modified 12-bit immediate. */
8252 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8253 imm = (insn & 0xff);
8254 switch (shift) {
8255 case 0: /* XY */
8256 /* Nothing to do. */
8257 break;
8258 case 1: /* 00XY00XY */
8259 imm |= imm << 16;
8260 break;
8261 case 2: /* XY00XY00 */
8262 imm |= imm << 16;
8263 imm <<= 8;
8264 break;
8265 case 3: /* XYXYXYXY */
8266 imm |= imm << 16;
8267 imm |= imm << 8;
8268 break;
8269 default: /* Rotated constant. */
8270 shift = (shift << 1) | (imm >> 7);
8271 imm |= 0x80;
8272 imm = imm << (32 - shift);
8273 shifter_out = 1;
8274 break;
b5ff1b31 8275 }
3174f8e9
FN		 8276 tmp2 = new_tmp();
8277 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8278 rn = (insn >> 16) & 0xf;
3174f8e9
FN		 8279 if (rn == 15) {
8280 tmp = new_tmp();
8281 tcg_gen_movi_i32(tmp, 0);
8282 } else {
8283 tmp = load_reg(s, rn);
8284 }
9ee6e8bb
PB		 8285 op = (insn >> 21) & 0xf;
8286 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8287 shifter_out, tmp, tmp2))
9ee6e8bb 8288 goto illegal_op;
3174f8e9 8289 dead_tmp(tmp2);
9ee6e8bb
PB		 8290 rd = (insn >> 8) & 0xf;
8291 if (rd != 15) {
3174f8e9
FN		 8292 store_reg(s, rd, tmp);
8293 } else {
8294 dead_tmp(tmp);
2c0262af 8295 }
2c0262af 8296 }
9ee6e8bb
PB		 8297 }
8298 break;
8299 case 12: /* Load/store single data item. */
8300 {
8301 int postinc = 0;
8302 int writeback = 0;
b0109805 8303 int user;
9ee6e8bb
PB		 8304 if ((insn & 0x01100000) == 0x01000000) {
8305 if (disas_neon_ls_insn(env, s, insn))
c1713132 8306 goto illegal_op;
9ee6e8bb
PB		 8307 break;
8308 }
b0109805 8309 user = IS_USER(s);
9ee6e8bb 8310 if (rn == 15) {
b0109805 8311 addr = new_tmp();
9ee6e8bb
PB		 8312 /* PC relative. */
8313 /* s->pc has already been incremented by 4. */
8314 imm = s->pc & 0xfffffffc;
8315 if (insn & (1 << 23))
8316 imm += insn & 0xfff;
8317 else
8318 imm -= insn & 0xfff;
b0109805 8319 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8320 } else {
b0109805 8321 addr = load_reg(s, rn);
9ee6e8bb
PB		 8322 if (insn & (1 << 23)) {
8323 /* Positive offset. */
8324 imm = insn & 0xfff;
b0109805 8325 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8326 } else {
8327 op = (insn >> 8) & 7;
8328 imm = insn & 0xff;
8329 switch (op) {
8330 case 0: case 8: /* Shifted Register. */
8331 shift = (insn >> 4) & 0xf;
8332 if (shift > 3)
18c9b560 8333 goto illegal_op;
b26eefb6 8334 tmp = load_reg(s, rm);
9ee6e8bb 8335 if (shift)
b26eefb6 8336 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8337 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8338 dead_tmp(tmp);
9ee6e8bb
PB		 8339 break;
8340 case 4: /* Negative offset. */
b0109805 8341 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb
PB		 8342 break;
8343 case 6: /* User privilege. */
b0109805
PB		 8344 tcg_gen_addi_i32(addr, addr, imm);
8345 user = 1;
9ee6e8bb
PB		 8346 break;
8347 case 1: /* Post-decrement. */
8348 imm = -imm;
8349 /* Fall through. */
8350 case 3: /* Post-increment. */
9ee6e8bb
PB		 8351 postinc = 1;
8352 writeback = 1;
8353 break;
8354 case 5: /* Pre-decrement. */
8355 imm = -imm;
8356 /* Fall through. */
8357 case 7: /* Pre-increment. */
b0109805 8358 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8359 writeback = 1;
8360 break;
8361 default:
b7bcbe95 8362 goto illegal_op;
9ee6e8bb
PB		 8363 }
8364 }
8365 }
8366 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8367 if (insn & (1 << 20)) {
8368 /* Load. */
8369 if (rs == 15 && op != 2) {
8370 if (op & 2)
b5ff1b31 8371 goto illegal_op;
9ee6e8bb
PB		 8372 /* Memory hint. Implemented as NOP. */
8373 } else {
8374 switch (op) {
b0109805
PB		 8375 case 0: tmp = gen_ld8u(addr, user); break;
8376 case 4: tmp = gen_ld8s(addr, user); break;
8377 case 1: tmp = gen_ld16u(addr, user); break;
8378 case 5: tmp = gen_ld16s(addr, user); break;
8379 case 2: tmp = gen_ld32(addr, user); break;
9ee6e8bb
PB		 8380 default: goto illegal_op;
8381 }
8382 if (rs == 15) {
b0109805 8383 gen_bx(s, tmp);
9ee6e8bb 8384 } else {
b0109805 8385 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8386 }
8387 }
8388 } else {
8389 /* Store. */
8390 if (rs == 15)
b7bcbe95 8391 goto illegal_op;
b0109805 8392 tmp = load_reg(s, rs);
9ee6e8bb 8393 switch (op) {
b0109805
PB		 8394 case 0: gen_st8(tmp, addr, user); break;
8395 case 1: gen_st16(tmp, addr, user); break;
8396 case 2: gen_st32(tmp, addr, user); break;
9ee6e8bb 8397 default: goto illegal_op;
b7bcbe95 8398 }
2c0262af 8399 }
9ee6e8bb 8400 if (postinc)
b0109805
PB		 8401 tcg_gen_addi_i32(addr, addr, imm);
8402 if (writeback) {
8403 store_reg(s, rn, addr);
8404 } else {
8405 dead_tmp(addr);
8406 }
9ee6e8bb
PB		 8407 }
8408 break;
8409 default:
8410 goto illegal_op;
2c0262af 8411 }
9ee6e8bb
PB		 8412 return 0;
8413illegal_op:
8414 return 1;
2c0262af
FB		 8415}
8416
9ee6e8bb 8417static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8418{
8419 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8420 int32_t offset;
8421 int i;
b26eefb6 8422 TCGv tmp;
d9ba4830 8423 TCGv tmp2;
b0109805 8424 TCGv addr;
99c475ab 8425
9ee6e8bb
PB		 8426 if (s->condexec_mask) {
8427 cond = s->condexec_cond;
bedd2912
JB		 8428 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8429 s->condlabel = gen_new_label();
8430 gen_test_cc(cond ^ 1, s->condlabel);
8431 s->condjmp = 1;
8432 }
9ee6e8bb
PB		 8433 }
8434
b5ff1b31 8435 insn = lduw_code(s->pc);
99c475ab 8436 s->pc += 2;
b5ff1b31 8437
99c475ab
FB		 8438 switch (insn >> 12) {
8439 case 0: case 1:
396e467c 8440
99c475ab
FB		 8441 rd = insn & 7;
8442 op = (insn >> 11) & 3;
8443 if (op == 3) {
8444 /* add/subtract */
8445 rn = (insn >> 3) & 7;
396e467c 8446 tmp = load_reg(s, rn);
99c475ab
FB		 8447 if (insn & (1 << 10)) {
8448 /* immediate */
396e467c
FN		 8449 tmp2 = new_tmp();
8450 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8451 } else {
8452 /* reg */
8453 rm = (insn >> 6) & 7;
396e467c 8454 tmp2 = load_reg(s, rm);
99c475ab 8455 }
9ee6e8bb
PB		 8456 if (insn & (1 << 9)) {
8457 if (s->condexec_mask)
396e467c 8458 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8459 else
396e467c 8460 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8461 } else {
8462 if (s->condexec_mask)
396e467c 8463 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8464 else
396e467c 8465 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8466 }
396e467c
FN		 8467 dead_tmp(tmp2);
8468 store_reg(s, rd, tmp);
99c475ab
FB		 8469 } else {
8470 /* shift immediate */
8471 rm = (insn >> 3) & 7;
8472 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8473 tmp = load_reg(s, rm);
8474 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8475 if (!s->condexec_mask)
8476 gen_logic_CC(tmp);
8477 store_reg(s, rd, tmp);
99c475ab
FB		 8478 }
8479 break;
8480 case 2: case 3:
8481 /* arithmetic large immediate */
8482 op = (insn >> 11) & 3;
8483 rd = (insn >> 8) & 0x7;
396e467c
FN		 8484 if (op == 0) { /* mov */
8485 tmp = new_tmp();
8486 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8487 if (!s->condexec_mask)
396e467c
FN		 8488 gen_logic_CC(tmp);
8489 store_reg(s, rd, tmp);
8490 } else {
8491 tmp = load_reg(s, rd);
8492 tmp2 = new_tmp();
8493 tcg_gen_movi_i32(tmp2, insn & 0xff);
8494 switch (op) {
8495 case 1: /* cmp */
8496 gen_helper_sub_cc(tmp, tmp, tmp2);
8497 dead_tmp(tmp);
8498 dead_tmp(tmp2);
8499 break;
8500 case 2: /* add */
8501 if (s->condexec_mask)
8502 tcg_gen_add_i32(tmp, tmp, tmp2);
8503 else
8504 gen_helper_add_cc(tmp, tmp, tmp2);
8505 dead_tmp(tmp2);
8506 store_reg(s, rd, tmp);
8507 break;
8508 case 3: /* sub */
8509 if (s->condexec_mask)
8510 tcg_gen_sub_i32(tmp, tmp, tmp2);
8511 else
8512 gen_helper_sub_cc(tmp, tmp, tmp2);
8513 dead_tmp(tmp2);
8514 store_reg(s, rd, tmp);
8515 break;
8516 }
99c475ab 8517 }
99c475ab
FB		 8518 break;
8519 case 4:
8520 if (insn & (1 << 11)) {
8521 rd = (insn >> 8) & 7;
5899f386
FB		 8522 /* load pc-relative. Bit 1 of PC is ignored. */
8523 val = s->pc + 2 + ((insn & 0xff) * 4);
8524 val &= ~(uint32_t)2;
b0109805
PB		 8525 addr = new_tmp();
8526 tcg_gen_movi_i32(addr, val);
8527 tmp = gen_ld32(addr, IS_USER(s));
8528 dead_tmp(addr);
8529 store_reg(s, rd, tmp);
99c475ab
FB		 8530 break;
8531 }
8532 if (insn & (1 << 10)) {
8533 /* data processing extended or blx */
8534 rd = (insn & 7) | ((insn >> 4) & 8);
8535 rm = (insn >> 3) & 0xf;
8536 op = (insn >> 8) & 3;
8537 switch (op) {
8538 case 0: /* add */
396e467c
FN		 8539 tmp = load_reg(s, rd);
8540 tmp2 = load_reg(s, rm);
8541 tcg_gen_add_i32(tmp, tmp, tmp2);
8542 dead_tmp(tmp2);
8543 store_reg(s, rd, tmp);
99c475ab
FB		 8544 break;
8545 case 1: /* cmp */
396e467c
FN		 8546 tmp = load_reg(s, rd);
8547 tmp2 = load_reg(s, rm);
8548 gen_helper_sub_cc(tmp, tmp, tmp2);
8549 dead_tmp(tmp2);
8550 dead_tmp(tmp);
99c475ab
FB		 8551 break;
8552 case 2: /* mov/cpy */
396e467c
FN		 8553 tmp = load_reg(s, rm);
8554 store_reg(s, rd, tmp);
99c475ab
FB		 8555 break;
8556 case 3:/* branch [and link] exchange thumb register */
b0109805 8557 tmp = load_reg(s, rm);
99c475ab
FB		 8558 if (insn & (1 << 7)) {
8559 val = (uint32_t)s->pc | 1;
b0109805
PB		 8560 tmp2 = new_tmp();
8561 tcg_gen_movi_i32(tmp2, val);
8562 store_reg(s, 14, tmp2);
99c475ab 8563 }
d9ba4830 8564 gen_bx(s, tmp);
99c475ab
FB		 8565 break;
8566 }
8567 break;
8568 }
8569
8570 /* data processing register */
8571 rd = insn & 7;
8572 rm = (insn >> 3) & 7;
8573 op = (insn >> 6) & 0xf;
8574 if (op == 2 || op == 3 || op == 4 || op == 7) {
8575 /* the shift/rotate ops want the operands backwards */
8576 val = rm;
8577 rm = rd;
8578 rd = val;
8579 val = 1;
8580 } else {
8581 val = 0;
8582 }
8583
396e467c
FN		 8584 if (op == 9) { /* neg */
8585 tmp = new_tmp();
8586 tcg_gen_movi_i32(tmp, 0);
8587 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8588 tmp = load_reg(s, rd);
8589 } else {
8590 TCGV_UNUSED(tmp);
8591 }
99c475ab 8592
396e467c 8593 tmp2 = load_reg(s, rm);
5899f386 8594 switch (op) {
99c475ab 8595 case 0x0: /* and */
396e467c 8596 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8597 if (!s->condexec_mask)
396e467c 8598 gen_logic_CC(tmp);
99c475ab
FB		 8599 break;
8600 case 0x1: /* eor */
396e467c 8601 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8602 if (!s->condexec_mask)
396e467c 8603 gen_logic_CC(tmp);
99c475ab
FB		 8604 break;
8605 case 0x2: /* lsl */
9ee6e8bb 8606 if (s->condexec_mask) {
396e467c 8607 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8608 } else {
396e467c
FN		 8609 gen_helper_shl_cc(tmp2, tmp2, tmp);
8610 gen_logic_CC(tmp2);
9ee6e8bb 8611 }
99c475ab
FB		 8612 break;
8613 case 0x3: /* lsr */
9ee6e8bb 8614 if (s->condexec_mask) {
396e467c 8615 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8616 } else {
396e467c
FN		 8617 gen_helper_shr_cc(tmp2, tmp2, tmp);
8618 gen_logic_CC(tmp2);
9ee6e8bb 8619 }
99c475ab
FB		 8620 break;
8621 case 0x4: /* asr */
9ee6e8bb 8622 if (s->condexec_mask) {
396e467c 8623 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8624 } else {
396e467c
FN		 8625 gen_helper_sar_cc(tmp2, tmp2, tmp);
8626 gen_logic_CC(tmp2);
9ee6e8bb 8627 }
99c475ab
FB		 8628 break;
8629 case 0x5: /* adc */
9ee6e8bb 8630 if (s->condexec_mask)
396e467c 8631 gen_adc(tmp, tmp2);
9ee6e8bb 8632 else
396e467c 8633 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8634 break;
8635 case 0x6: /* sbc */
9ee6e8bb 8636 if (s->condexec_mask)
396e467c 8637 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8638 else
396e467c 8639 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8640 break;
8641 case 0x7: /* ror */
9ee6e8bb 8642 if (s->condexec_mask) {
f669df27
AJ		 8643 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8644 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8645 } else {
396e467c
FN		 8646 gen_helper_ror_cc(tmp2, tmp2, tmp);
8647 gen_logic_CC(tmp2);
9ee6e8bb 8648 }
99c475ab
FB		 8649 break;
8650 case 0x8: /* tst */
396e467c
FN		 8651 tcg_gen_and_i32(tmp, tmp, tmp2);
8652 gen_logic_CC(tmp);
99c475ab 8653 rd = 16;
5899f386 8654 break;
99c475ab 8655 case 0x9: /* neg */
9ee6e8bb 8656 if (s->condexec_mask)
396e467c 8657 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8658 else
396e467c 8659 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8660 break;
8661 case 0xa: /* cmp */
396e467c 8662 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8663 rd = 16;
8664 break;
8665 case 0xb: /* cmn */
396e467c 8666 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8667 rd = 16;
8668 break;
8669 case 0xc: /* orr */
396e467c 8670 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8671 if (!s->condexec_mask)
396e467c 8672 gen_logic_CC(tmp);
99c475ab
FB		 8673 break;
8674 case 0xd: /* mul */
7b2919a0 8675 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8676 if (!s->condexec_mask)
396e467c 8677 gen_logic_CC(tmp);
99c475ab
FB		 8678 break;
8679 case 0xe: /* bic */
f669df27 8680 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8681 if (!s->condexec_mask)
396e467c 8682 gen_logic_CC(tmp);
99c475ab
FB		 8683 break;
8684 case 0xf: /* mvn */
396e467c 8685 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8686 if (!s->condexec_mask)
396e467c 8687 gen_logic_CC(tmp2);
99c475ab 8688 val = 1;
5899f386 8689 rm = rd;
99c475ab
FB		 8690 break;
8691 }
8692 if (rd != 16) {
396e467c
FN		 8693 if (val) {
8694 store_reg(s, rm, tmp2);
8695 if (op != 0xf)
8696 dead_tmp(tmp);
8697 } else {
8698 store_reg(s, rd, tmp);
8699 dead_tmp(tmp2);
8700 }
8701 } else {
8702 dead_tmp(tmp);
8703 dead_tmp(tmp2);
99c475ab
FB		 8704 }
8705 break;
8706
8707 case 5:
8708 /* load/store register offset. */
8709 rd = insn & 7;
8710 rn = (insn >> 3) & 7;
8711 rm = (insn >> 6) & 7;
8712 op = (insn >> 9) & 7;
b0109805 8713 addr = load_reg(s, rn);
b26eefb6 8714 tmp = load_reg(s, rm);
b0109805 8715 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8716 dead_tmp(tmp);
99c475ab
FB		 8717
8718 if (op < 3) /* store */
b0109805 8719 tmp = load_reg(s, rd);
99c475ab
FB		 8720
8721 switch (op) {
8722 case 0: /* str */
b0109805 8723 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8724 break;
8725 case 1: /* strh */
b0109805 8726 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8727 break;
8728 case 2: /* strb */
b0109805 8729 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8730 break;
8731 case 3: /* ldrsb */
b0109805 8732 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8733 break;
8734 case 4: /* ldr */
b0109805 8735 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8736 break;
8737 case 5: /* ldrh */
b0109805 8738 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8739 break;
8740 case 6: /* ldrb */
b0109805 8741 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8742 break;
8743 case 7: /* ldrsh */
b0109805 8744 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8745 break;
8746 }
8747 if (op >= 3) /* load */
b0109805
PB		 8748 store_reg(s, rd, tmp);
8749 dead_tmp(addr);
99c475ab
FB		 8750 break;
8751
8752 case 6:
8753 /* load/store word immediate offset */
8754 rd = insn & 7;
8755 rn = (insn >> 3) & 7;
b0109805 8756 addr = load_reg(s, rn);
99c475ab 8757 val = (insn >> 4) & 0x7c;
b0109805 8758 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8759
8760 if (insn & (1 << 11)) {
8761 /* load */
b0109805
PB		 8762 tmp = gen_ld32(addr, IS_USER(s));
8763 store_reg(s, rd, tmp);
99c475ab
FB		 8764 } else {
8765 /* store */
b0109805
PB		 8766 tmp = load_reg(s, rd);
8767 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8768 }
b0109805 8769 dead_tmp(addr);
99c475ab
FB		 8770 break;
8771
8772 case 7:
8773 /* load/store byte immediate offset */
8774 rd = insn & 7;
8775 rn = (insn >> 3) & 7;
b0109805 8776 addr = load_reg(s, rn);
99c475ab 8777 val = (insn >> 6) & 0x1f;
b0109805 8778 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8779
8780 if (insn & (1 << 11)) {
8781 /* load */
b0109805
PB		 8782 tmp = gen_ld8u(addr, IS_USER(s));
8783 store_reg(s, rd, tmp);
99c475ab
FB		 8784 } else {
8785 /* store */
b0109805
PB		 8786 tmp = load_reg(s, rd);
8787 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8788 }
b0109805 8789 dead_tmp(addr);
99c475ab
FB		 8790 break;
8791
8792 case 8:
8793 /* load/store halfword immediate offset */
8794 rd = insn & 7;
8795 rn = (insn >> 3) & 7;
b0109805 8796 addr = load_reg(s, rn);
99c475ab 8797 val = (insn >> 5) & 0x3e;
b0109805 8798 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8799
8800 if (insn & (1 << 11)) {
8801 /* load */
b0109805
PB		 8802 tmp = gen_ld16u(addr, IS_USER(s));
8803 store_reg(s, rd, tmp);
99c475ab
FB		 8804 } else {
8805 /* store */
b0109805
PB		 8806 tmp = load_reg(s, rd);
8807 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8808 }
b0109805 8809 dead_tmp(addr);
99c475ab
FB		 8810 break;
8811
8812 case 9:
8813 /* load/store from stack */
8814 rd = (insn >> 8) & 7;
b0109805 8815 addr = load_reg(s, 13);
99c475ab 8816 val = (insn & 0xff) * 4;
b0109805 8817 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8818
8819 if (insn & (1 << 11)) {
8820 /* load */
b0109805
PB		 8821 tmp = gen_ld32(addr, IS_USER(s));
8822 store_reg(s, rd, tmp);
99c475ab
FB		 8823 } else {
8824 /* store */
b0109805
PB		 8825 tmp = load_reg(s, rd);
8826 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8827 }
b0109805 8828 dead_tmp(addr);
99c475ab
FB		 8829 break;
8830
8831 case 10:
8832 /* add to high reg */
8833 rd = (insn >> 8) & 7;
5899f386
FB		 8834 if (insn & (1 << 11)) {
8835 /* SP */
5e3f878a 8836 tmp = load_reg(s, 13);
5899f386
FB		 8837 } else {
8838 /* PC. bit 1 is ignored. */
5e3f878a
PB		 8839 tmp = new_tmp();
8840 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8841 }
99c475ab 8842 val = (insn & 0xff) * 4;
5e3f878a
PB		 8843 tcg_gen_addi_i32(tmp, tmp, val);
8844 store_reg(s, rd, tmp);
99c475ab
FB		 8845 break;
8846
8847 case 11:
8848 /* misc */
8849 op = (insn >> 8) & 0xf;
8850 switch (op) {
8851 case 0:
8852 /* adjust stack pointer */
b26eefb6 8853 tmp = load_reg(s, 13);
99c475ab
FB		 8854 val = (insn & 0x7f) * 4;
8855 if (insn & (1 << 7))
6a0d8a1d 8856 val = -(int32_t)val;
b26eefb6
PB		 8857 tcg_gen_addi_i32(tmp, tmp, val);
8858 store_reg(s, 13, tmp);
99c475ab
FB		 8859 break;
8860
9ee6e8bb
PB		 8861 case 2: /* sign/zero extend. */
8862 ARCH(6);
8863 rd = insn & 7;
8864 rm = (insn >> 3) & 7;
b0109805 8865 tmp = load_reg(s, rm);
9ee6e8bb 8866 switch ((insn >> 6) & 3) {
b0109805
PB		 8867 case 0: gen_sxth(tmp); break;
8868 case 1: gen_sxtb(tmp); break;
8869 case 2: gen_uxth(tmp); break;
8870 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8871 }
b0109805 8872 store_reg(s, rd, tmp);
9ee6e8bb 8873 break;
99c475ab
FB		 8874 case 4: case 5: case 0xc: case 0xd:
8875 /* push/pop */
b0109805 8876 addr = load_reg(s, 13);
5899f386
FB		 8877 if (insn & (1 << 8))
8878 offset = 4;
99c475ab 8879 else
5899f386
FB		 8880 offset = 0;
8881 for (i = 0; i < 8; i++) {
8882 if (insn & (1 << i))
8883 offset += 4;
8884 }
8885 if ((insn & (1 << 11)) == 0) {
b0109805 8886 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8887 }
99c475ab
FB		 8888 for (i = 0; i < 8; i++) {
8889 if (insn & (1 << i)) {
8890 if (insn & (1 << 11)) {
8891 /* pop */
b0109805
PB		 8892 tmp = gen_ld32(addr, IS_USER(s));
8893 store_reg(s, i, tmp);
99c475ab
FB		 8894 } else {
8895 /* push */
b0109805
PB		 8896 tmp = load_reg(s, i);
8897 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8898 }
5899f386 8899 /* advance to the next address. */
b0109805 8900 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8901 }
8902 }
a50f5b91 8903 TCGV_UNUSED(tmp);
99c475ab
FB		 8904 if (insn & (1 << 8)) {
8905 if (insn & (1 << 11)) {
8906 /* pop pc */
b0109805 8907 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8908 /* don't set the pc until the rest of the instruction
8909 has completed */
8910 } else {
8911 /* push lr */
b0109805
PB		 8912 tmp = load_reg(s, 14);
8913 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8914 }
b0109805 8915 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8916 }
5899f386 8917 if ((insn & (1 << 11)) == 0) {
b0109805 8918 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8919 }
99c475ab 8920 /* write back the new stack pointer */
b0109805 8921 store_reg(s, 13, addr);
99c475ab
FB		 8922 /* set the new PC value */
8923 if ((insn & 0x0900) == 0x0900)
b0109805 8924 gen_bx(s, tmp);
99c475ab
FB		 8925 break;
8926
9ee6e8bb
PB		 8927 case 1: case 3: case 9: case 11: /* czb */
8928 rm = insn & 7;
d9ba4830 8929 tmp = load_reg(s, rm);
9ee6e8bb
PB		 8930 s->condlabel = gen_new_label();
8931 s->condjmp = 1;
8932 if (insn & (1 << 11))
cb63669a 8933 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 8934 else
cb63669a 8935 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
d9ba4830 8936 dead_tmp(tmp);
9ee6e8bb
PB		 8937 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8938 val = (uint32_t)s->pc + 2;
8939 val += offset;
8940 gen_jmp(s, val);
8941 break;
8942
8943 case 15: /* IT, nop-hint. */
8944 if ((insn & 0xf) == 0) {
8945 gen_nop_hint(s, (insn >> 4) & 0xf);
8946 break;
8947 }
8948 /* If Then. */
8949 s->condexec_cond = (insn >> 4) & 0xe;
8950 s->condexec_mask = insn & 0x1f;
8951 /* No actual code generated for this insn, just setup state. */
8952 break;
8953
06c949e6 8954 case 0xe: /* bkpt */
bc4a0de0 8955 gen_exception_insn(s, 2, EXCP_BKPT);
06c949e6
PB		 8956 break;
8957
9ee6e8bb
PB		 8958 case 0xa: /* rev */
8959 ARCH(6);
8960 rn = (insn >> 3) & 0x7;
8961 rd = insn & 0x7;
b0109805 8962 tmp = load_reg(s, rn);
9ee6e8bb 8963 switch ((insn >> 6) & 3) {
66896cb8 8964 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 8965 case 1: gen_rev16(tmp); break;
8966 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 8967 default: goto illegal_op;
8968 }
b0109805 8969 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8970 break;
8971
8972 case 6: /* cps */
8973 ARCH(6);
8974 if (IS_USER(s))
8975 break;
8976 if (IS_M(env)) {
8984bd2e 8977 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 8978 /* PRIMASK */
8984bd2e
PB		 8979 if (insn & 1) {
8980 addr = tcg_const_i32(16);
8981 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8982 tcg_temp_free_i32(addr);
8984bd2e 8983 }
9ee6e8bb 8984 /* FAULTMASK */
8984bd2e
PB		 8985 if (insn & 2) {
8986 addr = tcg_const_i32(17);
8987 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8988 tcg_temp_free_i32(addr);
8984bd2e 8989 }
b75263d6 8990 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8991 gen_lookup_tb(s);
8992 } else {
8993 if (insn & (1 << 4))
8994 shift = CPSR_A | CPSR_I | CPSR_F;
8995 else
8996 shift = 0;
fa26df03 8997 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 8998 }
8999 break;
9000
99c475ab
FB		 9001 default:
9002 goto undef;
9003 }
9004 break;
9005
9006 case 12:
9007 /* load/store multiple */
9008 rn = (insn >> 8) & 0x7;
b0109805 9009 addr = load_reg(s, rn);
99c475ab
FB		 9010 for (i = 0; i < 8; i++) {
9011 if (insn & (1 << i)) {
99c475ab
FB		 9012 if (insn & (1 << 11)) {
9013 /* load */
b0109805
PB		 9014 tmp = gen_ld32(addr, IS_USER(s));
9015 store_reg(s, i, tmp);
99c475ab
FB		 9016 } else {
9017 /* store */
b0109805
PB		 9018 tmp = load_reg(s, i);
9019 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9020 }
5899f386 9021 /* advance to the next address */
b0109805 9022 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9023 }
9024 }
5899f386 9025 /* Base register writeback. */
b0109805
PB		 9026 if ((insn & (1 << rn)) == 0) {
9027 store_reg(s, rn, addr);
9028 } else {
9029 dead_tmp(addr);
9030 }
99c475ab
FB		 9031 break;
9032
9033 case 13:
9034 /* conditional branch or swi */
9035 cond = (insn >> 8) & 0xf;
9036 if (cond == 0xe)
9037 goto undef;
9038
9039 if (cond == 0xf) {
9040 /* swi */
422ebf69 9041 gen_set_pc_im(s->pc);
9ee6e8bb 9042 s->is_jmp = DISAS_SWI;
99c475ab
FB		 9043 break;
9044 }
9045 /* generate a conditional jump to next instruction */
e50e6a20 9046 s->condlabel = gen_new_label();
d9ba4830 9047 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 9048 s->condjmp = 1;
99c475ab
FB		 9049
9050 /* jump to the offset */
5899f386 9051 val = (uint32_t)s->pc + 2;
99c475ab 9052 offset = ((int32_t)insn << 24) >> 24;
5899f386 9053 val += offset << 1;
8aaca4c0 9054 gen_jmp(s, val);
99c475ab
FB		 9055 break;
9056
9057 case 14:
358bf29e 9058 if (insn & (1 << 11)) {
9ee6e8bb
PB		 9059 if (disas_thumb2_insn(env, s, insn))
9060 goto undef32;
358bf29e
PB		 9061 break;
9062 }
9ee6e8bb 9063 /* unconditional branch */
99c475ab
FB		 9064 val = (uint32_t)s->pc;
9065 offset = ((int32_t)insn << 21) >> 21;
9066 val += (offset << 1) + 2;
8aaca4c0 9067 gen_jmp(s, val);
99c475ab
FB		 9068 break;
9069
9070 case 15:
9ee6e8bb 9071 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 9072 goto undef32;
9ee6e8bb 9073 break;
99c475ab
FB		 9074 }
9075 return;
9ee6e8bb 9076undef32:
bc4a0de0 9077 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 9078 return;
9079illegal_op:
99c475ab 9080undef:
bc4a0de0 9081 gen_exception_insn(s, 2, EXCP_UDEF);
99c475ab
FB		 9082}
9083
2c0262af
FB		 9084/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9085 basic block 'tb'. If search_pc is TRUE, also generate PC
9086 information for each intermediate instruction. */
2cfc5f17
TS		 9087static inline void gen_intermediate_code_internal(CPUState *env,
9088 TranslationBlock *tb,
9089 int search_pc)
2c0262af
FB		 9090{
9091 DisasContext dc1, *dc = &dc1;
a1d1bb31 9092 CPUBreakpoint *bp;
2c0262af
FB		 9093 uint16_t *gen_opc_end;
9094 int j, lj;
0fa85d43 9095 target_ulong pc_start;
b5ff1b31 9096 uint32_t next_page_start;
2e70f6ef
PB		 9097 int num_insns;
9098 int max_insns;
3b46e624 9099
2c0262af 9100 /* generate intermediate code */
b26eefb6 9101 num_temps = 0;
b26eefb6 9102
0fa85d43 9103 pc_start = tb->pc;
3b46e624 9104
2c0262af
FB		 9105 dc->tb = tb;
9106
2c0262af 9107 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9108
9109 dc->is_jmp = DISAS_NEXT;
9110 dc->pc = pc_start;
8aaca4c0 9111 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9112 dc->condjmp = 0;
7204ab88 9113 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
98eac7ca
PM		 9114 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9115 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
b5ff1b31 9116#if !defined(CONFIG_USER_ONLY)
61f74d6a 9117 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
b5ff1b31 9118#endif
5df8bac1 9119 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
69d1fc22
PM		 9120 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9121 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
a7812ae4
PB		 9122 cpu_F0s = tcg_temp_new_i32();
9123 cpu_F1s = tcg_temp_new_i32();
9124 cpu_F0d = tcg_temp_new_i64();
9125 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9126 cpu_V0 = cpu_F0d;
9127 cpu_V1 = cpu_F1d;
e677137d 9128 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9129 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9130 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9131 lj = -1;
2e70f6ef
PB		 9132 num_insns = 0;
9133 max_insns = tb->cflags & CF_COUNT_MASK;
9134 if (max_insns == 0)
9135 max_insns = CF_COUNT_MASK;
9136
9137 gen_icount_start();
e12ce78d
PM		 9138
9139 /* A note on handling of the condexec (IT) bits:
9140 *
9141 * We want to avoid the overhead of having to write the updated condexec
9142 * bits back to the CPUState for every instruction in an IT block. So:
9143 * (1) if the condexec bits are not already zero then we write
9144 * zero back into the CPUState now. This avoids complications trying
9145 * to do it at the end of the block. (For example if we don't do this
9146 * it's hard to identify whether we can safely skip writing condexec
9147 * at the end of the TB, which we definitely want to do for the case
9148 * where a TB doesn't do anything with the IT state at all.)
9149 * (2) if we are going to leave the TB then we call gen_set_condexec()
9150 * which will write the correct value into CPUState if zero is wrong.
9151 * This is done both for leaving the TB at the end, and for leaving
9152 * it because of an exception we know will happen, which is done in
9153 * gen_exception_insn(). The latter is necessary because we need to
9154 * leave the TB with the PC/IT state just prior to execution of the
9155 * instruction which caused the exception.
9156 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9157 * then the CPUState will be wrong and we need to reset it.
9158 * This is handled in the same way as restoration of the
9159 * PC in these situations: we will be called again with search_pc=1
9160 * and generate a mapping of the condexec bits for each PC in
9161 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9162 * the condexec bits.
9163 *
9164 * Note that there are no instructions which can read the condexec
9165 * bits, and none which can write non-static values to them, so
9166 * we don't need to care about whether CPUState is correct in the
9167 * middle of a TB.
9168 */
9169
9ee6e8bb
PB		 9170 /* Reset the conditional execution bits immediately. This avoids
9171 complications trying to do it at the end of the block. */
98eac7ca 9172 if (dc->condexec_mask || dc->condexec_cond)
8f01245e
PB		 9173 {
9174 TCGv tmp = new_tmp();
9175 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9176 store_cpu_field(tmp, condexec_bits);
8f01245e 9177 }
2c0262af 9178 do {
fbb4a2e3
PB		 9179#ifdef CONFIG_USER_ONLY
9180 /* Intercept jump to the magic kernel page. */
9181 if (dc->pc >= 0xffff0000) {
9182 /* We always get here via a jump, so know we are not in a
9183 conditional execution block. */
9184 gen_exception(EXCP_KERNEL_TRAP);
9185 dc->is_jmp = DISAS_UPDATE;
9186 break;
9187 }
9188#else
9ee6e8bb
PB		 9189 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9190 /* We always get here via a jump, so know we are not in a
9191 conditional execution block. */
d9ba4830 9192 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9193 dc->is_jmp = DISAS_UPDATE;
9194 break;
9ee6e8bb
PB		 9195 }
9196#endif
9197
72cf2d4f
BS		 9198 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9199 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9200 if (bp->pc == dc->pc) {
bc4a0de0 9201 gen_exception_insn(dc, 0, EXCP_DEBUG);
9ee6e8bb
PB		 9202 /* Advance PC so that clearing the breakpoint will
9203 invalidate this TB. */
9204 dc->pc += 2;
9205 goto done_generating;
1fddef4b
FB		 9206 break;
9207 }
9208 }
9209 }
2c0262af
FB		 9210 if (search_pc) {
9211 j = gen_opc_ptr - gen_opc_buf;
9212 if (lj < j) {
9213 lj++;
9214 while (lj < j)
9215 gen_opc_instr_start[lj++] = 0;
9216 }
0fa85d43 9217 gen_opc_pc[lj] = dc->pc;
e12ce78d 9218 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
2c0262af 9219 gen_opc_instr_start[lj] = 1;
2e70f6ef 9220 gen_opc_icount[lj] = num_insns;
2c0262af 9221 }
e50e6a20 9222
2e70f6ef
PB		 9223 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9224 gen_io_start();
9225
5642463a
PM		 9226 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9227 tcg_gen_debug_insn_start(dc->pc);
9228 }
9229
7204ab88 9230 if (dc->thumb) {
9ee6e8bb
PB		 9231 disas_thumb_insn(env, dc);
9232 if (dc->condexec_mask) {
9233 dc->condexec_cond = (dc->condexec_cond & 0xe)
9234 | ((dc->condexec_mask >> 4) & 1);
9235 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9236 if (dc->condexec_mask == 0) {
9237 dc->condexec_cond = 0;
9238 }
9239 }
9240 } else {
9241 disas_arm_insn(env, dc);
9242 }
b26eefb6
PB		 9243 if (num_temps) {
9244 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9245 num_temps = 0;
9246 }
e50e6a20
FB		 9247
9248 if (dc->condjmp && !dc->is_jmp) {
9249 gen_set_label(dc->condlabel);
9250 dc->condjmp = 0;
9251 }
aaf2d97d 9252 /* Translation stops when a conditional branch is encountered.
e50e6a20 9253 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9254 * Also stop translation when a page boundary is reached. This
bf20dc07 9255 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9256 num_insns ++;
1fddef4b
FB		 9257 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9258 !env->singlestep_enabled &&
1b530a6d 9259 !singlestep &&
2e70f6ef
PB		 9260 dc->pc < next_page_start &&
9261 num_insns < max_insns);
9262
9263 if (tb->cflags & CF_LAST_IO) {
9264 if (dc->condjmp) {
9265 /* FIXME: This can theoretically happen with self-modifying
9266 code. */
9267 cpu_abort(env, "IO on conditional branch instruction");
9268 }
9269 gen_io_end();
9270 }
9ee6e8bb 9271
b5ff1b31 9272 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9273 instruction was a conditional branch or trap, and the PC has
9274 already been written. */
551bd27f 9275 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9276 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9277 if (dc->condjmp) {
9ee6e8bb
PB		 9278 gen_set_condexec(dc);
9279 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9280 gen_exception(EXCP_SWI);
9ee6e8bb 9281 } else {
d9ba4830 9282 gen_exception(EXCP_DEBUG);
9ee6e8bb 9283 }
e50e6a20
FB		 9284 gen_set_label(dc->condlabel);
9285 }
9286 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9287 gen_set_pc_im(dc->pc);
e50e6a20 9288 dc->condjmp = 0;
8aaca4c0 9289 }
9ee6e8bb
PB		 9290 gen_set_condexec(dc);
9291 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9292 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9293 } else {
9294 /* FIXME: Single stepping a WFI insn will not halt
9295 the CPU. */
d9ba4830 9296 gen_exception(EXCP_DEBUG);
9ee6e8bb 9297 }
8aaca4c0 9298 } else {
9ee6e8bb
PB		 9299 /* While branches must always occur at the end of an IT block,
9300 there are a few other things that can cause us to terminate
9301 the TB in the middel of an IT block:
9302 - Exception generating instructions (bkpt, swi, undefined).
9303 - Page boundaries.
9304 - Hardware watchpoints.
9305 Hardware breakpoints have already been handled and skip this code.
9306 */
9307 gen_set_condexec(dc);
8aaca4c0 9308 switch(dc->is_jmp) {
8aaca4c0 9309 case DISAS_NEXT:
6e256c93 9310 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9311 break;
9312 default:
9313 case DISAS_JUMP:
9314 case DISAS_UPDATE:
9315 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9316 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9317 break;
9318 case DISAS_TB_JUMP:
9319 /* nothing more to generate */
9320 break;
9ee6e8bb 9321 case DISAS_WFI:
d9ba4830 9322 gen_helper_wfi();
9ee6e8bb
PB		 9323 break;
9324 case DISAS_SWI:
d9ba4830 9325 gen_exception(EXCP_SWI);
9ee6e8bb 9326 break;
8aaca4c0 9327 }
e50e6a20
FB		 9328 if (dc->condjmp) {
9329 gen_set_label(dc->condlabel);
9ee6e8bb 9330 gen_set_condexec(dc);
6e256c93 9331 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9332 dc->condjmp = 0;
9333 }
2c0262af 9334 }
2e70f6ef 9335
9ee6e8bb 9336done_generating:
2e70f6ef 9337 gen_icount_end(tb, num_insns);
2c0262af
FB		 9338 *gen_opc_ptr = INDEX_op_end;
9339
9340#ifdef DEBUG_DISAS
8fec2b8c 9341 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9342 qemu_log("----------------\n");
9343 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7204ab88 9344 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
93fcfe39 9345 qemu_log("\n");
2c0262af
FB		 9346 }
9347#endif
b5ff1b31
FB		 9348 if (search_pc) {
9349 j = gen_opc_ptr - gen_opc_buf;
9350 lj++;
9351 while (lj <= j)
9352 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9353 } else {
2c0262af 9354 tb->size = dc->pc - pc_start;
2e70f6ef 9355 tb->icount = num_insns;
b5ff1b31 9356 }
2c0262af
FB		 9357}
9358
2cfc5f17 9359void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9360{
2cfc5f17 9361 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9362}
9363
2cfc5f17 9364void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9365{
2cfc5f17 9366 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9367}
9368
b5ff1b31
FB		 9369static const char *cpu_mode_names[16] = {
9370 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9371 "???", "???", "???", "und", "???", "???", "???", "sys"
9372};
9ee6e8bb 9373
9a78eead 9374void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9375 int flags)
2c0262af
FB		 9376{
9377 int i;
06e80fc9 9378#if 0
bc380d17 9379 union {
b7bcbe95
FB		 9380 uint32_t i;
9381 float s;
9382 } s0, s1;
9383 CPU_DoubleU d;
a94a6abf
PB		 9384 /* ??? This assumes float64 and double have the same layout.
9385 Oh well, it's only debug dumps. */
9386 union {
9387 float64 f64;
9388 double d;
9389 } d0;
06e80fc9 9390#endif
b5ff1b31 9391 uint32_t psr;
2c0262af
FB		 9392
9393 for(i=0;i<16;i++) {
7fe48483 9394 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9395 if ((i % 4) == 3)
7fe48483 9396 cpu_fprintf(f, "\n");
2c0262af 9397 else
7fe48483 9398 cpu_fprintf(f, " ");
2c0262af 9399 }
b5ff1b31 9400 psr = cpsr_read(env);
687fa640
TS		 9401 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9402 psr,
b5ff1b31
FB		 9403 psr & (1 << 31) ? 'N' : '-',
9404 psr & (1 << 30) ? 'Z' : '-',
9405 psr & (1 << 29) ? 'C' : '-',
9406 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9407 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9408 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9409
5e3f878a 9410#if 0
b7bcbe95 9411 for (i = 0; i < 16; i++) {
8e96005d
FB		 9412 d.d = env->vfp.regs[i];
9413 s0.i = d.l.lower;
9414 s1.i = d.l.upper;
a94a6abf
PB		 9415 d0.f64 = d.d;
9416 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9417 i * 2, (int)s0.i, s0.s,
a94a6abf 9418 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9419 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9420 d0.d);
b7bcbe95 9421 }
40f137e1 9422 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9423#endif
2c0262af 9424}
a6b025d3 9425
d2856f1a
AJ		 9426void gen_pc_load(CPUState *env, TranslationBlock *tb,
9427 unsigned long searched_pc, int pc_pos, void *puc)
9428{
9429 env->regs[15] = gen_opc_pc[pc_pos];
e12ce78d 9430 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
d2856f1a 9431}
Qemu copy for testing