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target-arm: Handle UNDEF cases for Neon invalid modified-immediates
[qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
be5e7a76
DES		 37#define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38#define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39/* currently all emulated v5 cores are also v5TE, so don't bother */
40#define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
9ee6e8bb
PB		 41#define ENABLE_ARCH_5J 0
42#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 46
86753403 47#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 48
2c0262af
FB		 49/* internal defines */
50typedef struct DisasContext {
0fa85d43 51 target_ulong pc;
2c0262af 52 int is_jmp;
e50e6a20
FB		 53 /* Nonzero if this instruction has been conditionally skipped. */
54 int condjmp;
55 /* The label that will be jumped to when the instruction is skipped. */
56 int condlabel;
9ee6e8bb
PB		 57 /* Thumb-2 condtional execution bits. */
58 int condexec_mask;
59 int condexec_cond;
2c0262af 60 struct TranslationBlock *tb;
8aaca4c0 61 int singlestep_enabled;
5899f386 62 int thumb;
b5ff1b31
FB		 63#if !defined(CONFIG_USER_ONLY)
64 int user;
65#endif
5df8bac1 66 int vfp_enabled;
69d1fc22
PM		 67 int vec_len;
68 int vec_stride;
2c0262af
FB		 69} DisasContext;
70
e12ce78d
PM		 71static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
72
b5ff1b31
FB		 73#if defined(CONFIG_USER_ONLY)
74#define IS_USER(s) 1
75#else
76#define IS_USER(s) (s->user)
77#endif
78
9ee6e8bb
PB		 79/* These instructions trap after executing, so defer them until after the
80 conditional executions state has been updated. */
81#define DISAS_WFI 4
82#define DISAS_SWI 5
2c0262af 83
a7812ae4 84static TCGv_ptr cpu_env;
ad69471c 85/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 86static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 87static TCGv_i32 cpu_R[16];
426f5abc
PB		 88static TCGv_i32 cpu_exclusive_addr;
89static TCGv_i32 cpu_exclusive_val;
90static TCGv_i32 cpu_exclusive_high;
91#ifdef CONFIG_USER_ONLY
92static TCGv_i32 cpu_exclusive_test;
93static TCGv_i32 cpu_exclusive_info;
94#endif
ad69471c 95
b26eefb6 96/* FIXME: These should be removed. */
a7812ae4
PB		 97static TCGv cpu_F0s, cpu_F1s;
98static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 99
2e70f6ef
PB		 100#include "gen-icount.h"
101
155c3eac
FN		 102static const char *regnames[] =
103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
105
b26eefb6
PB		 106/* initialize TCG globals. */
107void arm_translate_init(void)
108{
155c3eac
FN		 109 int i;
110
a7812ae4
PB		 111 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
112
155c3eac
FN		 113 for (i = 0; i < 16; i++) {
114 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, regs[i]),
116 regnames[i]);
117 }
426f5abc
PB		 118 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_addr), "exclusive_addr");
120 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
121 offsetof(CPUState, exclusive_val), "exclusive_val");
122 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, exclusive_high), "exclusive_high");
124#ifdef CONFIG_USER_ONLY
125 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
126 offsetof(CPUState, exclusive_test), "exclusive_test");
127 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
128 offsetof(CPUState, exclusive_info), "exclusive_info");
129#endif
155c3eac 130
a7812ae4
PB		 131#define GEN_HELPER 2
132#include "helpers.h"
b26eefb6
PB		 133}
134
d9ba4830
PB		 135static inline TCGv load_cpu_offset(int offset)
136{
7d1b0095 137 TCGv tmp = tcg_temp_new_i32();
d9ba4830
PB		 138 tcg_gen_ld_i32(tmp, cpu_env, offset);
139 return tmp;
140}
141
142#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
143
144static inline void store_cpu_offset(TCGv var, int offset)
145{
146 tcg_gen_st_i32(var, cpu_env, offset);
7d1b0095 147 tcg_temp_free_i32(var);
d9ba4830
PB		 148}
149
150#define store_cpu_field(var, name) \
151 store_cpu_offset(var, offsetof(CPUState, name))
152
b26eefb6
PB		 153/* Set a variable to the value of a CPU register. */
154static void load_reg_var(DisasContext *s, TCGv var, int reg)
155{
156 if (reg == 15) {
157 uint32_t addr;
158 /* normaly, since we updated PC, we need only to add one insn */
159 if (s->thumb)
160 addr = (long)s->pc + 2;
161 else
162 addr = (long)s->pc + 4;
163 tcg_gen_movi_i32(var, addr);
164 } else {
155c3eac 165 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 166 }
167}
168
169/* Create a new temporary and set it to the value of a CPU register. */
170static inline TCGv load_reg(DisasContext *s, int reg)
171{
7d1b0095 172 TCGv tmp = tcg_temp_new_i32();
b26eefb6
PB		 173 load_reg_var(s, tmp, reg);
174 return tmp;
175}
176
177/* Set a CPU register. The source must be a temporary and will be
178 marked as dead. */
179static void store_reg(DisasContext *s, int reg, TCGv var)
180{
181 if (reg == 15) {
182 tcg_gen_andi_i32(var, var, ~1);
183 s->is_jmp = DISAS_JUMP;
184 }
155c3eac 185 tcg_gen_mov_i32(cpu_R[reg], var);
7d1b0095 186 tcg_temp_free_i32(var);
b26eefb6
PB		 187}
188
b26eefb6 189/* Value extensions. */
86831435
PB		 190#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 192#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
193#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
194
1497c961
PB		 195#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
196#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 197
b26eefb6 198
b75263d6
JR		 199static inline void gen_set_cpsr(TCGv var, uint32_t mask)
200{
201 TCGv tmp_mask = tcg_const_i32(mask);
202 gen_helper_cpsr_write(var, tmp_mask);
203 tcg_temp_free_i32(tmp_mask);
204}
d9ba4830
PB		 205/* Set NZCV flags from the high 4 bits of var. */
206#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
207
208static void gen_exception(int excp)
209{
7d1b0095 210 TCGv tmp = tcg_temp_new_i32();
d9ba4830
PB		 211 tcg_gen_movi_i32(tmp, excp);
212 gen_helper_exception(tmp);
7d1b0095 213 tcg_temp_free_i32(tmp);
d9ba4830
PB		 214}
215
3670669c
PB		 216static void gen_smul_dual(TCGv a, TCGv b)
217{
7d1b0095
PM		 218 TCGv tmp1 = tcg_temp_new_i32();
219 TCGv tmp2 = tcg_temp_new_i32();
22478e79
AZ		 220 tcg_gen_ext16s_i32(tmp1, a);
221 tcg_gen_ext16s_i32(tmp2, b);
3670669c 222 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
7d1b0095 223 tcg_temp_free_i32(tmp2);
3670669c
PB		 224 tcg_gen_sari_i32(a, a, 16);
225 tcg_gen_sari_i32(b, b, 16);
226 tcg_gen_mul_i32(b, b, a);
227 tcg_gen_mov_i32(a, tmp1);
7d1b0095 228 tcg_temp_free_i32(tmp1);
3670669c
PB		 229}
230
231/* Byteswap each halfword. */
232static void gen_rev16(TCGv var)
233{
7d1b0095 234 TCGv tmp = tcg_temp_new_i32();
3670669c
PB		 235 tcg_gen_shri_i32(tmp, var, 8);
236 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
237 tcg_gen_shli_i32(var, var, 8);
238 tcg_gen_andi_i32(var, var, 0xff00ff00);
239 tcg_gen_or_i32(var, var, tmp);
7d1b0095 240 tcg_temp_free_i32(tmp);
3670669c
PB		 241}
242
243/* Byteswap low halfword and sign extend. */
244static void gen_revsh(TCGv var)
245{
1a855029
AJ		 246 tcg_gen_ext16u_i32(var, var);
247 tcg_gen_bswap16_i32(var, var);
248 tcg_gen_ext16s_i32(var, var);
3670669c
PB		 249}
250
251/* Unsigned bitfield extract. */
252static void gen_ubfx(TCGv var, int shift, uint32_t mask)
253{
254 if (shift)
255 tcg_gen_shri_i32(var, var, shift);
256 tcg_gen_andi_i32(var, var, mask);
257}
258
259/* Signed bitfield extract. */
260static void gen_sbfx(TCGv var, int shift, int width)
261{
262 uint32_t signbit;
263
264 if (shift)
265 tcg_gen_sari_i32(var, var, shift);
266 if (shift + width < 32) {
267 signbit = 1u << (width - 1);
268 tcg_gen_andi_i32(var, var, (1u << width) - 1);
269 tcg_gen_xori_i32(var, var, signbit);
270 tcg_gen_subi_i32(var, var, signbit);
271 }
272}
273
274/* Bitfield insertion. Insert val into base. Clobbers base and val. */
275static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
276{
3670669c 277 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 278 tcg_gen_shli_i32(val, val, shift);
279 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 280 tcg_gen_or_i32(dest, base, val);
281}
282
838fa72d
AJ		 283/* Return (b << 32) + a. Mark inputs as dead */
284static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
3670669c 285{
838fa72d
AJ		 286 TCGv_i64 tmp64 = tcg_temp_new_i64();
287
288 tcg_gen_extu_i32_i64(tmp64, b);
7d1b0095 289 tcg_temp_free_i32(b);
838fa72d
AJ		 290 tcg_gen_shli_i64(tmp64, tmp64, 32);
291 tcg_gen_add_i64(a, tmp64, a);
292
293 tcg_temp_free_i64(tmp64);
294 return a;
295}
296
297/* Return (b << 32) - a. Mark inputs as dead. */
298static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
299{
300 TCGv_i64 tmp64 = tcg_temp_new_i64();
301
302 tcg_gen_extu_i32_i64(tmp64, b);
7d1b0095 303 tcg_temp_free_i32(b);
838fa72d
AJ		 304 tcg_gen_shli_i64(tmp64, tmp64, 32);
305 tcg_gen_sub_i64(a, tmp64, a);
306
307 tcg_temp_free_i64(tmp64);
308 return a;
3670669c
PB		 309}
310
8f01245e
PB		 311/* FIXME: Most targets have native widening multiplication.
312 It would be good to use that instead of a full wide multiply. */
5e3f878a 313/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 314static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 315{
a7812ae4
PB		 316 TCGv_i64 tmp1 = tcg_temp_new_i64();
317 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 318
319 tcg_gen_extu_i32_i64(tmp1, a);
7d1b0095 320 tcg_temp_free_i32(a);
5e3f878a 321 tcg_gen_extu_i32_i64(tmp2, b);
7d1b0095 322 tcg_temp_free_i32(b);
5e3f878a 323 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 324 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 325 return tmp1;
326}
327
a7812ae4 328static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 329{
a7812ae4
PB		 330 TCGv_i64 tmp1 = tcg_temp_new_i64();
331 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 332
333 tcg_gen_ext_i32_i64(tmp1, a);
7d1b0095 334 tcg_temp_free_i32(a);
5e3f878a 335 tcg_gen_ext_i32_i64(tmp2, b);
7d1b0095 336 tcg_temp_free_i32(b);
5e3f878a 337 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 338 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 339 return tmp1;
340}
341
8f01245e
PB		 342/* Swap low and high halfwords. */
343static void gen_swap_half(TCGv var)
344{
7d1b0095 345 TCGv tmp = tcg_temp_new_i32();
8f01245e
PB		 346 tcg_gen_shri_i32(tmp, var, 16);
347 tcg_gen_shli_i32(var, var, 16);
348 tcg_gen_or_i32(var, var, tmp);
7d1b0095 349 tcg_temp_free_i32(tmp);
8f01245e
PB		 350}
351
b26eefb6
PB		 352/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
353 tmp = (t0 ^ t1) & 0x8000;
354 t0 &= ~0x8000;
355 t1 &= ~0x8000;
356 t0 = (t0 + t1) ^ tmp;
357 */
358
359static void gen_add16(TCGv t0, TCGv t1)
360{
7d1b0095 361 TCGv tmp = tcg_temp_new_i32();
b26eefb6
PB		 362 tcg_gen_xor_i32(tmp, t0, t1);
363 tcg_gen_andi_i32(tmp, tmp, 0x8000);
364 tcg_gen_andi_i32(t0, t0, ~0x8000);
365 tcg_gen_andi_i32(t1, t1, ~0x8000);
366 tcg_gen_add_i32(t0, t0, t1);
367 tcg_gen_xor_i32(t0, t0, tmp);
7d1b0095
PM		 368 tcg_temp_free_i32(tmp);
369 tcg_temp_free_i32(t1);
b26eefb6
PB		 370}
371
9a119ff6
PB		 372#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
373
b26eefb6
PB		 374/* Set CF to the top bit of var. */
375static void gen_set_CF_bit31(TCGv var)
376{
7d1b0095 377 TCGv tmp = tcg_temp_new_i32();
b26eefb6 378 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 379 gen_set_CF(tmp);
7d1b0095 380 tcg_temp_free_i32(tmp);
b26eefb6
PB		 381}
382
383/* Set N and Z flags from var. */
384static inline void gen_logic_CC(TCGv var)
385{
6fbe23d5
PB		 386 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
387 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 388}
389
390/* T0 += T1 + CF. */
396e467c 391static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 392{
d9ba4830 393 TCGv tmp;
396e467c 394 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 395 tmp = load_cpu_field(CF);
396e467c 396 tcg_gen_add_i32(t0, t0, tmp);
7d1b0095 397 tcg_temp_free_i32(tmp);
b26eefb6
PB		 398}
399
e9bb4aa9
JR		 400/* dest = T0 + T1 + CF. */
401static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
402{
403 TCGv tmp;
404 tcg_gen_add_i32(dest, t0, t1);
405 tmp = load_cpu_field(CF);
406 tcg_gen_add_i32(dest, dest, tmp);
7d1b0095 407 tcg_temp_free_i32(tmp);
e9bb4aa9
JR		 408}
409
3670669c
PB		 410/* dest = T0 - T1 + CF - 1. */
411static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
412{
d9ba4830 413 TCGv tmp;
3670669c 414 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 415 tmp = load_cpu_field(CF);
3670669c
PB		 416 tcg_gen_add_i32(dest, dest, tmp);
417 tcg_gen_subi_i32(dest, dest, 1);
7d1b0095 418 tcg_temp_free_i32(tmp);
3670669c
PB		 419}
420
ad69471c
PB		 421/* FIXME: Implement this natively. */
422#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
423
9a119ff6 424static void shifter_out_im(TCGv var, int shift)
b26eefb6 425{
7d1b0095 426 TCGv tmp = tcg_temp_new_i32();
9a119ff6
PB		 427 if (shift == 0) {
428 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 429 } else {
9a119ff6 430 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 431 if (shift != 31)
9a119ff6
PB		 432 tcg_gen_andi_i32(tmp, tmp, 1);
433 }
434 gen_set_CF(tmp);
7d1b0095 435 tcg_temp_free_i32(tmp);
9a119ff6 436}
b26eefb6 437
9a119ff6
PB		 438/* Shift by immediate. Includes special handling for shift == 0. */
439static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
440{
441 switch (shiftop) {
442 case 0: /* LSL */
443 if (shift != 0) {
444 if (flags)
445 shifter_out_im(var, 32 - shift);
446 tcg_gen_shli_i32(var, var, shift);
447 }
448 break;
449 case 1: /* LSR */
450 if (shift == 0) {
451 if (flags) {
452 tcg_gen_shri_i32(var, var, 31);
453 gen_set_CF(var);
454 }
455 tcg_gen_movi_i32(var, 0);
456 } else {
457 if (flags)
458 shifter_out_im(var, shift - 1);
459 tcg_gen_shri_i32(var, var, shift);
460 }
461 break;
462 case 2: /* ASR */
463 if (shift == 0)
464 shift = 32;
465 if (flags)
466 shifter_out_im(var, shift - 1);
467 if (shift == 32)
468 shift = 31;
469 tcg_gen_sari_i32(var, var, shift);
470 break;
471 case 3: /* ROR/RRX */
472 if (shift != 0) {
473 if (flags)
474 shifter_out_im(var, shift - 1);
f669df27 475 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 476 } else {
d9ba4830 477 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 478 if (flags)
479 shifter_out_im(var, 0);
480 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 481 tcg_gen_shli_i32(tmp, tmp, 31);
482 tcg_gen_or_i32(var, var, tmp);
7d1b0095 483 tcg_temp_free_i32(tmp);
b26eefb6
PB		 484 }
485 }
486};
487
8984bd2e
PB		 488static inline void gen_arm_shift_reg(TCGv var, int shiftop,
489 TCGv shift, int flags)
490{
491 if (flags) {
492 switch (shiftop) {
493 case 0: gen_helper_shl_cc(var, var, shift); break;
494 case 1: gen_helper_shr_cc(var, var, shift); break;
495 case 2: gen_helper_sar_cc(var, var, shift); break;
496 case 3: gen_helper_ror_cc(var, var, shift); break;
497 }
498 } else {
499 switch (shiftop) {
500 case 0: gen_helper_shl(var, var, shift); break;
501 case 1: gen_helper_shr(var, var, shift); break;
502 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 503 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
504 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 505 }
506 }
7d1b0095 507 tcg_temp_free_i32(shift);
8984bd2e
PB		 508}
509
6ddbc6e4
PB		 510#define PAS_OP(pfx) \
511 switch (op2) { \
512 case 0: gen_pas_helper(glue(pfx,add16)); break; \
513 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
514 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
515 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
516 case 4: gen_pas_helper(glue(pfx,add8)); break; \
517 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
518 }
d9ba4830 519static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 520{
a7812ae4 521 TCGv_ptr tmp;
6ddbc6e4
PB		 522
523 switch (op1) {
524#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
525 case 1:
a7812ae4 526 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 527 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
528 PAS_OP(s)
b75263d6 529 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 530 break;
531 case 5:
a7812ae4 532 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(u)
b75263d6 535 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 536 break;
537#undef gen_pas_helper
538#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
539 case 2:
540 PAS_OP(q);
541 break;
542 case 3:
543 PAS_OP(sh);
544 break;
545 case 6:
546 PAS_OP(uq);
547 break;
548 case 7:
549 PAS_OP(uh);
550 break;
551#undef gen_pas_helper
552 }
553}
9ee6e8bb
PB		 554#undef PAS_OP
555
6ddbc6e4
PB		 556/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
557#define PAS_OP(pfx) \
ed89a2f1 558 switch (op1) { \
6ddbc6e4
PB		 559 case 0: gen_pas_helper(glue(pfx,add8)); break; \
560 case 1: gen_pas_helper(glue(pfx,add16)); break; \
561 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
562 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
563 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
564 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
565 }
d9ba4830 566static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 567{
a7812ae4 568 TCGv_ptr tmp;
6ddbc6e4 569
ed89a2f1 570 switch (op2) {
6ddbc6e4
PB		 571#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
572 case 0:
a7812ae4 573 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 574 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
575 PAS_OP(s)
b75263d6 576 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 577 break;
578 case 4:
a7812ae4 579 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(u)
b75263d6 582 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 583 break;
584#undef gen_pas_helper
585#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
586 case 1:
587 PAS_OP(q);
588 break;
589 case 2:
590 PAS_OP(sh);
591 break;
592 case 5:
593 PAS_OP(uq);
594 break;
595 case 6:
596 PAS_OP(uh);
597 break;
598#undef gen_pas_helper
599 }
600}
9ee6e8bb
PB		 601#undef PAS_OP
602
d9ba4830
PB		 603static void gen_test_cc(int cc, int label)
604{
605 TCGv tmp;
606 TCGv tmp2;
d9ba4830
PB		 607 int inv;
608
d9ba4830
PB		 609 switch (cc) {
610 case 0: /* eq: Z */
6fbe23d5 611 tmp = load_cpu_field(ZF);
cb63669a 612 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 613 break;
614 case 1: /* ne: !Z */
6fbe23d5 615 tmp = load_cpu_field(ZF);
cb63669a 616 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 617 break;
618 case 2: /* cs: C */
619 tmp = load_cpu_field(CF);
cb63669a 620 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 621 break;
622 case 3: /* cc: !C */
623 tmp = load_cpu_field(CF);
cb63669a 624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 625 break;
626 case 4: /* mi: N */
6fbe23d5 627 tmp = load_cpu_field(NF);
cb63669a 628 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 629 break;
630 case 5: /* pl: !N */
6fbe23d5 631 tmp = load_cpu_field(NF);
cb63669a 632 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 633 break;
634 case 6: /* vs: V */
635 tmp = load_cpu_field(VF);
cb63669a 636 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 637 break;
638 case 7: /* vc: !V */
639 tmp = load_cpu_field(VF);
cb63669a 640 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 641 break;
642 case 8: /* hi: C && !Z */
643 inv = gen_new_label();
644 tmp = load_cpu_field(CF);
cb63669a 645 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
7d1b0095 646 tcg_temp_free_i32(tmp);
6fbe23d5 647 tmp = load_cpu_field(ZF);
cb63669a 648 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 649 gen_set_label(inv);
650 break;
651 case 9: /* ls: !C || Z */
652 tmp = load_cpu_field(CF);
cb63669a 653 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
7d1b0095 654 tcg_temp_free_i32(tmp);
6fbe23d5 655 tmp = load_cpu_field(ZF);
cb63669a 656 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 657 break;
658 case 10: /* ge: N == V -> N ^ V == 0 */
659 tmp = load_cpu_field(VF);
6fbe23d5 660 tmp2 = load_cpu_field(NF);
d9ba4830 661 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 662 tcg_temp_free_i32(tmp2);
cb63669a 663 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 664 break;
665 case 11: /* lt: N != V -> N ^ V != 0 */
666 tmp = load_cpu_field(VF);
6fbe23d5 667 tmp2 = load_cpu_field(NF);
d9ba4830 668 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 669 tcg_temp_free_i32(tmp2);
cb63669a 670 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 671 break;
672 case 12: /* gt: !Z && N == V */
673 inv = gen_new_label();
6fbe23d5 674 tmp = load_cpu_field(ZF);
cb63669a 675 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
7d1b0095 676 tcg_temp_free_i32(tmp);
d9ba4830 677 tmp = load_cpu_field(VF);
6fbe23d5 678 tmp2 = load_cpu_field(NF);
d9ba4830 679 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 680 tcg_temp_free_i32(tmp2);
cb63669a 681 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 682 gen_set_label(inv);
683 break;
684 case 13: /* le: Z || N != V */
6fbe23d5 685 tmp = load_cpu_field(ZF);
cb63669a 686 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
7d1b0095 687 tcg_temp_free_i32(tmp);
d9ba4830 688 tmp = load_cpu_field(VF);
6fbe23d5 689 tmp2 = load_cpu_field(NF);
d9ba4830 690 tcg_gen_xor_i32(tmp, tmp, tmp2);
7d1b0095 691 tcg_temp_free_i32(tmp2);
cb63669a 692 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 693 break;
694 default:
695 fprintf(stderr, "Bad condition code 0x%x\n", cc);
696 abort();
697 }
7d1b0095 698 tcg_temp_free_i32(tmp);
d9ba4830 699}
2c0262af 700
b1d8e52e 701static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 702 1, /* and */
703 1, /* xor */
704 0, /* sub */
705 0, /* rsb */
706 0, /* add */
707 0, /* adc */
708 0, /* sbc */
709 0, /* rsc */
710 1, /* andl */
711 1, /* xorl */
712 0, /* cmp */
713 0, /* cmn */
714 1, /* orr */
715 1, /* mov */
716 1, /* bic */
717 1, /* mvn */
718};
3b46e624 719
d9ba4830
PB		 720/* Set PC and Thumb state from an immediate address. */
721static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 722{
b26eefb6 723 TCGv tmp;
99c475ab 724
b26eefb6 725 s->is_jmp = DISAS_UPDATE;
d9ba4830 726 if (s->thumb != (addr & 1)) {
7d1b0095 727 tmp = tcg_temp_new_i32();
d9ba4830
PB		 728 tcg_gen_movi_i32(tmp, addr & 1);
729 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
7d1b0095 730 tcg_temp_free_i32(tmp);
d9ba4830 731 }
155c3eac 732 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 733}
734
735/* Set PC and Thumb state from var. var is marked as dead. */
736static inline void gen_bx(DisasContext *s, TCGv var)
737{
d9ba4830 738 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 739 tcg_gen_andi_i32(cpu_R[15], var, ~1);
740 tcg_gen_andi_i32(var, var, 1);
741 store_cpu_field(var, thumb);
d9ba4830
PB		 742}
743
21aeb343
JR		 744/* Variant of store_reg which uses branch&exchange logic when storing
745 to r15 in ARM architecture v7 and above. The source must be a temporary
746 and will be marked as dead. */
747static inline void store_reg_bx(CPUState *env, DisasContext *s,
748 int reg, TCGv var)
749{
750 if (reg == 15 && ENABLE_ARCH_7) {
751 gen_bx(s, var);
752 } else {
753 store_reg(s, reg, var);
754 }
755}
756
be5e7a76
DES		 757/* Variant of store_reg which uses branch&exchange logic when storing
758 * to r15 in ARM architecture v5T and above. This is used for storing
759 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
760 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
761static inline void store_reg_from_load(CPUState *env, DisasContext *s,
762 int reg, TCGv var)
763{
764 if (reg == 15 && ENABLE_ARCH_5) {
765 gen_bx(s, var);
766 } else {
767 store_reg(s, reg, var);
768 }
769}
770
b0109805
PB		 771static inline TCGv gen_ld8s(TCGv addr, int index)
772{
7d1b0095 773 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 774 tcg_gen_qemu_ld8s(tmp, addr, index);
775 return tmp;
776}
777static inline TCGv gen_ld8u(TCGv addr, int index)
778{
7d1b0095 779 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 780 tcg_gen_qemu_ld8u(tmp, addr, index);
781 return tmp;
782}
783static inline TCGv gen_ld16s(TCGv addr, int index)
784{
7d1b0095 785 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 786 tcg_gen_qemu_ld16s(tmp, addr, index);
787 return tmp;
788}
789static inline TCGv gen_ld16u(TCGv addr, int index)
790{
7d1b0095 791 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 792 tcg_gen_qemu_ld16u(tmp, addr, index);
793 return tmp;
794}
795static inline TCGv gen_ld32(TCGv addr, int index)
796{
7d1b0095 797 TCGv tmp = tcg_temp_new_i32();
b0109805
PB		 798 tcg_gen_qemu_ld32u(tmp, addr, index);
799 return tmp;
800}
84496233
JR		 801static inline TCGv_i64 gen_ld64(TCGv addr, int index)
802{
803 TCGv_i64 tmp = tcg_temp_new_i64();
804 tcg_gen_qemu_ld64(tmp, addr, index);
805 return tmp;
806}
b0109805
PB		 807static inline void gen_st8(TCGv val, TCGv addr, int index)
808{
809 tcg_gen_qemu_st8(val, addr, index);
7d1b0095 810 tcg_temp_free_i32(val);
b0109805
PB		 811}
812static inline void gen_st16(TCGv val, TCGv addr, int index)
813{
814 tcg_gen_qemu_st16(val, addr, index);
7d1b0095 815 tcg_temp_free_i32(val);
b0109805
PB		 816}
817static inline void gen_st32(TCGv val, TCGv addr, int index)
818{
819 tcg_gen_qemu_st32(val, addr, index);
7d1b0095 820 tcg_temp_free_i32(val);
b0109805 821}
84496233
JR		 822static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
823{
824 tcg_gen_qemu_st64(val, addr, index);
825 tcg_temp_free_i64(val);
826}
b5ff1b31 827
5e3f878a
PB		 828static inline void gen_set_pc_im(uint32_t val)
829{
155c3eac 830 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 831}
832
b5ff1b31
FB		 833/* Force a TB lookup after an instruction that changes the CPU state. */
834static inline void gen_lookup_tb(DisasContext *s)
835{
a6445c52 836 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 837 s->is_jmp = DISAS_UPDATE;
838}
839
b0109805
PB		 840static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
841 TCGv var)
2c0262af 842{
1e8d4eec 843 int val, rm, shift, shiftop;
b26eefb6 844 TCGv offset;
2c0262af
FB		 845
846 if (!(insn & (1 << 25))) {
847 /* immediate */
848 val = insn & 0xfff;
849 if (!(insn & (1 << 23)))
850 val = -val;
537730b9 851 if (val != 0)
b0109805 852 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 853 } else {
854 /* shift/register */
855 rm = (insn) & 0xf;
856 shift = (insn >> 7) & 0x1f;
1e8d4eec 857 shiftop = (insn >> 5) & 3;
b26eefb6 858 offset = load_reg(s, rm);
9a119ff6 859 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 860 if (!(insn & (1 << 23)))
b0109805 861 tcg_gen_sub_i32(var, var, offset);
2c0262af 862 else
b0109805 863 tcg_gen_add_i32(var, var, offset);
7d1b0095 864 tcg_temp_free_i32(offset);
2c0262af
FB		 865 }
866}
867
191f9a93 868static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 869 int extra, TCGv var)
2c0262af
FB		 870{
871 int val, rm;
b26eefb6 872 TCGv offset;
3b46e624 873
2c0262af
FB		 874 if (insn & (1 << 22)) {
875 /* immediate */
876 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
877 if (!(insn & (1 << 23)))
878 val = -val;
18acad92 879 val += extra;
537730b9 880 if (val != 0)
b0109805 881 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 882 } else {
883 /* register */
191f9a93 884 if (extra)
b0109805 885 tcg_gen_addi_i32(var, var, extra);
2c0262af 886 rm = (insn) & 0xf;
b26eefb6 887 offset = load_reg(s, rm);
2c0262af 888 if (!(insn & (1 << 23)))
b0109805 889 tcg_gen_sub_i32(var, var, offset);
2c0262af 890 else
b0109805 891 tcg_gen_add_i32(var, var, offset);
7d1b0095 892 tcg_temp_free_i32(offset);
2c0262af
FB		 893 }
894}
895
4373f3ce
PB		 896#define VFP_OP2(name) \
897static inline void gen_vfp_##name(int dp) \
898{ \
899 if (dp) \
900 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
901 else \
902 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 903}
904
4373f3ce
PB		 905VFP_OP2(add)
906VFP_OP2(sub)
907VFP_OP2(mul)
908VFP_OP2(div)
909
910#undef VFP_OP2
911
912static inline void gen_vfp_abs(int dp)
913{
914 if (dp)
915 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
918}
919
920static inline void gen_vfp_neg(int dp)
921{
922 if (dp)
923 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
924 else
925 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
926}
927
928static inline void gen_vfp_sqrt(int dp)
929{
930 if (dp)
931 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
932 else
933 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
934}
935
936static inline void gen_vfp_cmp(int dp)
937{
938 if (dp)
939 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
942}
943
944static inline void gen_vfp_cmpe(int dp)
945{
946 if (dp)
947 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
948 else
949 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
950}
951
952static inline void gen_vfp_F1_ld0(int dp)
953{
954 if (dp)
5b340b51 955 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 956 else
5b340b51 957 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 958}
959
960static inline void gen_vfp_uito(int dp)
961{
962 if (dp)
963 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
964 else
965 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
966}
967
968static inline void gen_vfp_sito(int dp)
969{
970 if (dp)
66230e0d 971 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 972 else
66230e0d 973 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 974}
975
976static inline void gen_vfp_toui(int dp)
977{
978 if (dp)
979 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
982}
983
984static inline void gen_vfp_touiz(int dp)
985{
986 if (dp)
987 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
990}
991
992static inline void gen_vfp_tosi(int dp)
993{
994 if (dp)
995 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
996 else
997 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
998}
999
1000static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 1001{
1002 if (dp)
4373f3ce 1003 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 1004 else
4373f3ce
PB		 1005 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1006}
1007
1008#define VFP_GEN_FIX(name) \
1009static inline void gen_vfp_##name(int dp, int shift) \
1010{ \
b75263d6 1011 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1012 if (dp) \
b75263d6 1013 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1014 else \
b75263d6
JR		 1015 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1016 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1017}
4373f3ce
PB		 1018VFP_GEN_FIX(tosh)
1019VFP_GEN_FIX(tosl)
1020VFP_GEN_FIX(touh)
1021VFP_GEN_FIX(toul)
1022VFP_GEN_FIX(shto)
1023VFP_GEN_FIX(slto)
1024VFP_GEN_FIX(uhto)
1025VFP_GEN_FIX(ulto)
1026#undef VFP_GEN_FIX
9ee6e8bb 1027
312eea9f 1028static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1029{
1030 if (dp)
312eea9f 1031 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1032 else
312eea9f 1033 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1034}
1035
312eea9f 1036static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1037{
1038 if (dp)
312eea9f 1039 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1040 else
312eea9f 1041 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1042}
1043
8e96005d
FB		 1044static inline long
1045vfp_reg_offset (int dp, int reg)
1046{
1047 if (dp)
1048 return offsetof(CPUARMState, vfp.regs[reg]);
1049 else if (reg & 1) {
1050 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1051 + offsetof(CPU_DoubleU, l.upper);
1052 } else {
1053 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1054 + offsetof(CPU_DoubleU, l.lower);
1055 }
1056}
9ee6e8bb
PB		 1057
1058/* Return the offset of a 32-bit piece of a NEON register.
1059 zero is the least significant end of the register. */
1060static inline long
1061neon_reg_offset (int reg, int n)
1062{
1063 int sreg;
1064 sreg = reg * 2 + n;
1065 return vfp_reg_offset(0, sreg);
1066}
1067
8f8e3aa4
PB		 1068static TCGv neon_load_reg(int reg, int pass)
1069{
7d1b0095 1070 TCGv tmp = tcg_temp_new_i32();
8f8e3aa4
PB		 1071 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1072 return tmp;
1073}
1074
1075static void neon_store_reg(int reg, int pass, TCGv var)
1076{
1077 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
7d1b0095 1078 tcg_temp_free_i32(var);
8f8e3aa4
PB		 1079}
1080
a7812ae4 1081static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1082{
1083 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1084}
1085
a7812ae4 1086static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1087{
1088 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1089}
1090
4373f3ce
PB		 1091#define tcg_gen_ld_f32 tcg_gen_ld_i32
1092#define tcg_gen_ld_f64 tcg_gen_ld_i64
1093#define tcg_gen_st_f32 tcg_gen_st_i32
1094#define tcg_gen_st_f64 tcg_gen_st_i64
1095
b7bcbe95
FB		 1096static inline void gen_mov_F0_vreg(int dp, int reg)
1097{
1098 if (dp)
4373f3ce 1099 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1100 else
4373f3ce 1101 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1102}
1103
1104static inline void gen_mov_F1_vreg(int dp, int reg)
1105{
1106 if (dp)
4373f3ce 1107 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1108 else
4373f3ce 1109 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1110}
1111
1112static inline void gen_mov_vreg_F0(int dp, int reg)
1113{
1114 if (dp)
4373f3ce 1115 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1116 else
4373f3ce 1117 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1118}
1119
18c9b560
AZ		 1120#define ARM_CP_RW_BIT (1 << 20)
1121
a7812ae4 1122static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1123{
1124 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1125}
1126
a7812ae4 1127static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1128{
1129 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1130}
1131
da6b5335 1132static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1133{
7d1b0095 1134 TCGv var = tcg_temp_new_i32();
da6b5335
FN		 1135 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1136 return var;
e677137d
PB		 1137}
1138
da6b5335 1139static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1140{
da6b5335 1141 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
7d1b0095 1142 tcg_temp_free_i32(var);
e677137d
PB		 1143}
1144
1145static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1146{
1147 iwmmxt_store_reg(cpu_M0, rn);
1148}
1149
1150static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1151{
1152 iwmmxt_load_reg(cpu_M0, rn);
1153}
1154
1155static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1156{
1157 iwmmxt_load_reg(cpu_V1, rn);
1158 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1159}
1160
1161static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1162{
1163 iwmmxt_load_reg(cpu_V1, rn);
1164 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1165}
1166
1167static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1168{
1169 iwmmxt_load_reg(cpu_V1, rn);
1170 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1171}
1172
1173#define IWMMXT_OP(name) \
1174static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1175{ \
1176 iwmmxt_load_reg(cpu_V1, rn); \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1178}
1179
947a2fa2
PM		 1180#define IWMMXT_OP_SIZE(name) \
1181IWMMXT_OP(name##b) \
1182IWMMXT_OP(name##w) \
1183IWMMXT_OP(name##l)
e677137d 1184
947a2fa2 1185#define IWMMXT_OP_1(name) \
e677137d
PB		 1186static inline void gen_op_iwmmxt_##name##_M0(void) \
1187{ \
947a2fa2 1188 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \
e677137d
PB		 1189}
1190
1191IWMMXT_OP(maddsq)
1192IWMMXT_OP(madduq)
1193IWMMXT_OP(sadb)
1194IWMMXT_OP(sadw)
1195IWMMXT_OP(mulslw)
1196IWMMXT_OP(mulshw)
1197IWMMXT_OP(mululw)
1198IWMMXT_OP(muluhw)
1199IWMMXT_OP(macsw)
1200IWMMXT_OP(macuw)
1201
947a2fa2
PM		 1202IWMMXT_OP_SIZE(unpackl)
1203IWMMXT_OP_SIZE(unpackh)
1204
1205IWMMXT_OP_1(unpacklub)
1206IWMMXT_OP_1(unpackluw)
1207IWMMXT_OP_1(unpacklul)
1208IWMMXT_OP_1(unpackhub)
1209IWMMXT_OP_1(unpackhuw)
1210IWMMXT_OP_1(unpackhul)
1211IWMMXT_OP_1(unpacklsb)
1212IWMMXT_OP_1(unpacklsw)
1213IWMMXT_OP_1(unpacklsl)
1214IWMMXT_OP_1(unpackhsb)
1215IWMMXT_OP_1(unpackhsw)
1216IWMMXT_OP_1(unpackhsl)
1217
1218IWMMXT_OP_SIZE(cmpeq)
1219IWMMXT_OP_SIZE(cmpgtu)
1220IWMMXT_OP_SIZE(cmpgts)
1221
1222IWMMXT_OP_SIZE(mins)
1223IWMMXT_OP_SIZE(minu)
1224IWMMXT_OP_SIZE(maxs)
1225IWMMXT_OP_SIZE(maxu)
1226
1227IWMMXT_OP_SIZE(subn)
1228IWMMXT_OP_SIZE(addn)
1229IWMMXT_OP_SIZE(subu)
1230IWMMXT_OP_SIZE(addu)
1231IWMMXT_OP_SIZE(subs)
1232IWMMXT_OP_SIZE(adds)
1233
1234IWMMXT_OP(avgb0)
1235IWMMXT_OP(avgb1)
1236IWMMXT_OP(avgw0)
1237IWMMXT_OP(avgw1)
e677137d
PB		 1238
1239IWMMXT_OP(msadb)
1240
947a2fa2
PM		 1241IWMMXT_OP(packuw)
1242IWMMXT_OP(packul)
1243IWMMXT_OP(packuq)
1244IWMMXT_OP(packsw)
1245IWMMXT_OP(packsl)
1246IWMMXT_OP(packsq)
e677137d 1247
e677137d
PB		 1248static void gen_op_iwmmxt_set_mup(void)
1249{
1250 TCGv tmp;
1251 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1252 tcg_gen_ori_i32(tmp, tmp, 2);
1253 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1254}
1255
1256static void gen_op_iwmmxt_set_cup(void)
1257{
1258 TCGv tmp;
1259 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1260 tcg_gen_ori_i32(tmp, tmp, 1);
1261 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1262}
1263
1264static void gen_op_iwmmxt_setpsr_nz(void)
1265{
7d1b0095 1266 TCGv tmp = tcg_temp_new_i32();
e677137d
PB		 1267 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1268 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1269}
1270
1271static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1272{
1273 iwmmxt_load_reg(cpu_V1, rn);
86831435 1274 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1275 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1276}
1277
da6b5335 1278static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1279{
1280 int rd;
1281 uint32_t offset;
da6b5335 1282 TCGv tmp;
18c9b560
AZ		 1283
1284 rd = (insn >> 16) & 0xf;
da6b5335 1285 tmp = load_reg(s, rd);
18c9b560
AZ		 1286
1287 offset = (insn & 0xff) << ((insn >> 7) & 2);
1288 if (insn & (1 << 24)) {
1289 /* Pre indexed */
1290 if (insn & (1 << 23))
da6b5335 1291 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1292 else
da6b5335
FN		 1293 tcg_gen_addi_i32(tmp, tmp, -offset);
1294 tcg_gen_mov_i32(dest, tmp);
18c9b560 1295 if (insn & (1 << 21))
da6b5335
FN		 1296 store_reg(s, rd, tmp);
1297 else
7d1b0095 1298 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1299 } else if (insn & (1 << 21)) {
1300 /* Post indexed */
da6b5335 1301 tcg_gen_mov_i32(dest, tmp);
18c9b560 1302 if (insn & (1 << 23))
da6b5335 1303 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1304 else
da6b5335
FN		 1305 tcg_gen_addi_i32(tmp, tmp, -offset);
1306 store_reg(s, rd, tmp);
18c9b560
AZ		 1307 } else if (!(insn & (1 << 23)))
1308 return 1;
1309 return 0;
1310}
1311
da6b5335 1312static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1313{
1314 int rd = (insn >> 0) & 0xf;
da6b5335 1315 TCGv tmp;
18c9b560 1316
da6b5335
FN		 1317 if (insn & (1 << 8)) {
1318 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1319 return 1;
da6b5335
FN		 1320 } else {
1321 tmp = iwmmxt_load_creg(rd);
1322 }
1323 } else {
7d1b0095 1324 tmp = tcg_temp_new_i32();
da6b5335
FN		 1325 iwmmxt_load_reg(cpu_V0, rd);
1326 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1327 }
1328 tcg_gen_andi_i32(tmp, tmp, mask);
1329 tcg_gen_mov_i32(dest, tmp);
7d1b0095 1330 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1331 return 0;
1332}
1333
1334/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1335 (ie. an undefined instruction). */
1336static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1337{
1338 int rd, wrd;
1339 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1340 TCGv addr;
1341 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1342
1343 if ((insn & 0x0e000e00) == 0x0c000000) {
1344 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1345 wrd = insn & 0xf;
1346 rdlo = (insn >> 12) & 0xf;
1347 rdhi = (insn >> 16) & 0xf;
1348 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1349 iwmmxt_load_reg(cpu_V0, wrd);
1350 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1351 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1352 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1353 } else { /* TMCRR */
da6b5335
FN		 1354 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1355 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1356 gen_op_iwmmxt_set_mup();
1357 }
1358 return 0;
1359 }
1360
1361 wrd = (insn >> 12) & 0xf;
7d1b0095 1362 addr = tcg_temp_new_i32();
da6b5335 1363 if (gen_iwmmxt_address(s, insn, addr)) {
7d1b0095 1364 tcg_temp_free_i32(addr);
18c9b560 1365 return 1;
da6b5335 1366 }
18c9b560
AZ		 1367 if (insn & ARM_CP_RW_BIT) {
1368 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
7d1b0095 1369 tmp = tcg_temp_new_i32();
da6b5335
FN		 1370 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1371 iwmmxt_store_creg(wrd, tmp);
18c9b560 1372 } else {
e677137d
PB		 1373 i = 1;
1374 if (insn & (1 << 8)) {
1375 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1376 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1377 i = 0;
1378 } else { /* WLDRW wRd */
da6b5335 1379 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1380 }
1381 } else {
1382 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1383 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1384 } else { /* WLDRB */
da6b5335 1385 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1386 }
1387 }
1388 if (i) {
1389 tcg_gen_extu_i32_i64(cpu_M0, tmp);
7d1b0095 1390 tcg_temp_free_i32(tmp);
e677137d 1391 }
18c9b560
AZ		 1392 gen_op_iwmmxt_movq_wRn_M0(wrd);
1393 }
1394 } else {
1395 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1396 tmp = iwmmxt_load_creg(wrd);
1397 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1398 } else {
1399 gen_op_iwmmxt_movq_M0_wRn(wrd);
7d1b0095 1400 tmp = tcg_temp_new_i32();
e677137d
PB		 1401 if (insn & (1 << 8)) {
1402 if (insn & (1 << 22)) { /* WSTRD */
7d1b0095 1403 tcg_temp_free_i32(tmp);
da6b5335 1404 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1405 } else { /* WSTRW wRd */
1406 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1407 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1408 }
1409 } else {
1410 if (insn & (1 << 22)) { /* WSTRH */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1412 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1413 } else { /* WSTRB */
1414 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1415 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1416 }
1417 }
18c9b560
AZ		 1418 }
1419 }
7d1b0095 1420 tcg_temp_free_i32(addr);
18c9b560
AZ		 1421 return 0;
1422 }
1423
1424 if ((insn & 0x0f000000) != 0x0e000000)
1425 return 1;
1426
1427 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1428 case 0x000: /* WOR */
1429 wrd = (insn >> 12) & 0xf;
1430 rd0 = (insn >> 0) & 0xf;
1431 rd1 = (insn >> 16) & 0xf;
1432 gen_op_iwmmxt_movq_M0_wRn(rd0);
1433 gen_op_iwmmxt_orq_M0_wRn(rd1);
1434 gen_op_iwmmxt_setpsr_nz();
1435 gen_op_iwmmxt_movq_wRn_M0(wrd);
1436 gen_op_iwmmxt_set_mup();
1437 gen_op_iwmmxt_set_cup();
1438 break;
1439 case 0x011: /* TMCR */
1440 if (insn & 0xf)
1441 return 1;
1442 rd = (insn >> 12) & 0xf;
1443 wrd = (insn >> 16) & 0xf;
1444 switch (wrd) {
1445 case ARM_IWMMXT_wCID:
1446 case ARM_IWMMXT_wCASF:
1447 break;
1448 case ARM_IWMMXT_wCon:
1449 gen_op_iwmmxt_set_cup();
1450 /* Fall through. */
1451 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1452 tmp = iwmmxt_load_creg(wrd);
1453 tmp2 = load_reg(s, rd);
f669df27 1454 tcg_gen_andc_i32(tmp, tmp, tmp2);
7d1b0095 1455 tcg_temp_free_i32(tmp2);
da6b5335 1456 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1457 break;
1458 case ARM_IWMMXT_wCGR0:
1459 case ARM_IWMMXT_wCGR1:
1460 case ARM_IWMMXT_wCGR2:
1461 case ARM_IWMMXT_wCGR3:
1462 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1463 tmp = load_reg(s, rd);
1464 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1465 break;
1466 default:
1467 return 1;
1468 }
1469 break;
1470 case 0x100: /* WXOR */
1471 wrd = (insn >> 12) & 0xf;
1472 rd0 = (insn >> 0) & 0xf;
1473 rd1 = (insn >> 16) & 0xf;
1474 gen_op_iwmmxt_movq_M0_wRn(rd0);
1475 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1476 gen_op_iwmmxt_setpsr_nz();
1477 gen_op_iwmmxt_movq_wRn_M0(wrd);
1478 gen_op_iwmmxt_set_mup();
1479 gen_op_iwmmxt_set_cup();
1480 break;
1481 case 0x111: /* TMRC */
1482 if (insn & 0xf)
1483 return 1;
1484 rd = (insn >> 12) & 0xf;
1485 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1486 tmp = iwmmxt_load_creg(wrd);
1487 store_reg(s, rd, tmp);
18c9b560
AZ		 1488 break;
1489 case 0x300: /* WANDN */
1490 wrd = (insn >> 12) & 0xf;
1491 rd0 = (insn >> 0) & 0xf;
1492 rd1 = (insn >> 16) & 0xf;
1493 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1494 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1495 gen_op_iwmmxt_andq_M0_wRn(rd1);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1500 break;
1501 case 0x200: /* WAND */
1502 wrd = (insn >> 12) & 0xf;
1503 rd0 = (insn >> 0) & 0xf;
1504 rd1 = (insn >> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0);
1506 gen_op_iwmmxt_andq_M0_wRn(rd1);
1507 gen_op_iwmmxt_setpsr_nz();
1508 gen_op_iwmmxt_movq_wRn_M0(wrd);
1509 gen_op_iwmmxt_set_mup();
1510 gen_op_iwmmxt_set_cup();
1511 break;
1512 case 0x810: case 0xa10: /* WMADD */
1513 wrd = (insn >> 12) & 0xf;
1514 rd0 = (insn >> 0) & 0xf;
1515 rd1 = (insn >> 16) & 0xf;
1516 gen_op_iwmmxt_movq_M0_wRn(rd0);
1517 if (insn & (1 << 21))
1518 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1519 else
1520 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1521 gen_op_iwmmxt_movq_wRn_M0(wrd);
1522 gen_op_iwmmxt_set_mup();
1523 break;
1524 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1525 wrd = (insn >> 12) & 0xf;
1526 rd0 = (insn >> 16) & 0xf;
1527 rd1 = (insn >> 0) & 0xf;
1528 gen_op_iwmmxt_movq_M0_wRn(rd0);
1529 switch ((insn >> 22) & 3) {
1530 case 0:
1531 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1532 break;
1533 case 1:
1534 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1535 break;
1536 case 2:
1537 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1538 break;
1539 case 3:
1540 return 1;
1541 }
1542 gen_op_iwmmxt_movq_wRn_M0(wrd);
1543 gen_op_iwmmxt_set_mup();
1544 gen_op_iwmmxt_set_cup();
1545 break;
1546 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1547 wrd = (insn >> 12) & 0xf;
1548 rd0 = (insn >> 16) & 0xf;
1549 rd1 = (insn >> 0) & 0xf;
1550 gen_op_iwmmxt_movq_M0_wRn(rd0);
1551 switch ((insn >> 22) & 3) {
1552 case 0:
1553 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1554 break;
1555 case 1:
1556 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1557 break;
1558 case 2:
1559 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1560 break;
1561 case 3:
1562 return 1;
1563 }
1564 gen_op_iwmmxt_movq_wRn_M0(wrd);
1565 gen_op_iwmmxt_set_mup();
1566 gen_op_iwmmxt_set_cup();
1567 break;
1568 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1569 wrd = (insn >> 12) & 0xf;
1570 rd0 = (insn >> 16) & 0xf;
1571 rd1 = (insn >> 0) & 0xf;
1572 gen_op_iwmmxt_movq_M0_wRn(rd0);
1573 if (insn & (1 << 22))
1574 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1575 else
1576 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1577 if (!(insn & (1 << 20)))
1578 gen_op_iwmmxt_addl_M0_wRn(wrd);
1579 gen_op_iwmmxt_movq_wRn_M0(wrd);
1580 gen_op_iwmmxt_set_mup();
1581 break;
1582 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1583 wrd = (insn >> 12) & 0xf;
1584 rd0 = (insn >> 16) & 0xf;
1585 rd1 = (insn >> 0) & 0xf;
1586 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1587 if (insn & (1 << 21)) {
1588 if (insn & (1 << 20))
1589 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1590 else
1591 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1592 } else {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1597 }
18c9b560
AZ		 1598 gen_op_iwmmxt_movq_wRn_M0(wrd);
1599 gen_op_iwmmxt_set_mup();
1600 break;
1601 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1602 wrd = (insn >> 12) & 0xf;
1603 rd0 = (insn >> 16) & 0xf;
1604 rd1 = (insn >> 0) & 0xf;
1605 gen_op_iwmmxt_movq_M0_wRn(rd0);
1606 if (insn & (1 << 21))
1607 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1608 else
1609 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1610 if (!(insn & (1 << 20))) {
e677137d
PB		 1611 iwmmxt_load_reg(cpu_V1, wrd);
1612 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1613 }
1614 gen_op_iwmmxt_movq_wRn_M0(wrd);
1615 gen_op_iwmmxt_set_mup();
1616 break;
1617 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1618 wrd = (insn >> 12) & 0xf;
1619 rd0 = (insn >> 16) & 0xf;
1620 rd1 = (insn >> 0) & 0xf;
1621 gen_op_iwmmxt_movq_M0_wRn(rd0);
1622 switch ((insn >> 22) & 3) {
1623 case 0:
1624 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1625 break;
1626 case 1:
1627 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1628 break;
1629 case 2:
1630 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1631 break;
1632 case 3:
1633 return 1;
1634 }
1635 gen_op_iwmmxt_movq_wRn_M0(wrd);
1636 gen_op_iwmmxt_set_mup();
1637 gen_op_iwmmxt_set_cup();
1638 break;
1639 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1640 wrd = (insn >> 12) & 0xf;
1641 rd0 = (insn >> 16) & 0xf;
1642 rd1 = (insn >> 0) & 0xf;
1643 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1644 if (insn & (1 << 22)) {
1645 if (insn & (1 << 20))
1646 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1647 else
1648 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1649 } else {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1654 }
18c9b560
AZ		 1655 gen_op_iwmmxt_movq_wRn_M0(wrd);
1656 gen_op_iwmmxt_set_mup();
1657 gen_op_iwmmxt_set_cup();
1658 break;
1659 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1660 wrd = (insn >> 12) & 0xf;
1661 rd0 = (insn >> 16) & 0xf;
1662 rd1 = (insn >> 0) & 0xf;
1663 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1664 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1665 tcg_gen_andi_i32(tmp, tmp, 7);
1666 iwmmxt_load_reg(cpu_V1, rd1);
1667 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
7d1b0095 1668 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1669 gen_op_iwmmxt_movq_wRn_M0(wrd);
1670 gen_op_iwmmxt_set_mup();
1671 break;
1672 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1673 if (((insn >> 6) & 3) == 3)
1674 return 1;
18c9b560
AZ		 1675 rd = (insn >> 12) & 0xf;
1676 wrd = (insn >> 16) & 0xf;
da6b5335 1677 tmp = load_reg(s, rd);
18c9b560
AZ		 1678 gen_op_iwmmxt_movq_M0_wRn(wrd);
1679 switch ((insn >> 6) & 3) {
1680 case 0:
da6b5335
FN		 1681 tmp2 = tcg_const_i32(0xff);
1682 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1683 break;
1684 case 1:
da6b5335
FN		 1685 tmp2 = tcg_const_i32(0xffff);
1686 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1687 break;
1688 case 2:
da6b5335
FN		 1689 tmp2 = tcg_const_i32(0xffffffff);
1690 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1691 break;
da6b5335
FN		 1692 default:
1693 TCGV_UNUSED(tmp2);
1694 TCGV_UNUSED(tmp3);
18c9b560 1695 }
da6b5335
FN		 1696 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1697 tcg_temp_free(tmp3);
1698 tcg_temp_free(tmp2);
7d1b0095 1699 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1700 gen_op_iwmmxt_movq_wRn_M0(wrd);
1701 gen_op_iwmmxt_set_mup();
1702 break;
1703 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1704 rd = (insn >> 12) & 0xf;
1705 wrd = (insn >> 16) & 0xf;
da6b5335 1706 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1707 return 1;
1708 gen_op_iwmmxt_movq_M0_wRn(wrd);
7d1b0095 1709 tmp = tcg_temp_new_i32();
18c9b560
AZ		 1710 switch ((insn >> 22) & 3) {
1711 case 0:
da6b5335
FN		 1712 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1713 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1714 if (insn & 8) {
1715 tcg_gen_ext8s_i32(tmp, tmp);
1716 } else {
1717 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1718 }
1719 break;
1720 case 1:
da6b5335
FN		 1721 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1722 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1723 if (insn & 8) {
1724 tcg_gen_ext16s_i32(tmp, tmp);
1725 } else {
1726 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1727 }
1728 break;
1729 case 2:
da6b5335
FN		 1730 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1731 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1732 break;
18c9b560 1733 }
da6b5335 1734 store_reg(s, rd, tmp);
18c9b560
AZ		 1735 break;
1736 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1737 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1738 return 1;
da6b5335 1739 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1740 switch ((insn >> 22) & 3) {
1741 case 0:
da6b5335 1742 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1743 break;
1744 case 1:
da6b5335 1745 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1746 break;
1747 case 2:
da6b5335 1748 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1749 break;
18c9b560 1750 }
da6b5335
FN		 1751 tcg_gen_shli_i32(tmp, tmp, 28);
1752 gen_set_nzcv(tmp);
7d1b0095 1753 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1754 break;
1755 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1756 if (((insn >> 6) & 3) == 3)
1757 return 1;
18c9b560
AZ		 1758 rd = (insn >> 12) & 0xf;
1759 wrd = (insn >> 16) & 0xf;
da6b5335 1760 tmp = load_reg(s, rd);
18c9b560
AZ		 1761 switch ((insn >> 6) & 3) {
1762 case 0:
da6b5335 1763 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1764 break;
1765 case 1:
da6b5335 1766 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1767 break;
1768 case 2:
da6b5335 1769 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1770 break;
18c9b560 1771 }
7d1b0095 1772 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1773 gen_op_iwmmxt_movq_wRn_M0(wrd);
1774 gen_op_iwmmxt_set_mup();
1775 break;
1776 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1777 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1778 return 1;
da6b5335 1779 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
7d1b0095 1780 tmp2 = tcg_temp_new_i32();
da6b5335 1781 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1782 switch ((insn >> 22) & 3) {
1783 case 0:
1784 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1785 tcg_gen_shli_i32(tmp2, tmp2, 4);
1786 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1787 }
1788 break;
1789 case 1:
1790 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1791 tcg_gen_shli_i32(tmp2, tmp2, 8);
1792 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1793 }
1794 break;
1795 case 2:
da6b5335
FN		 1796 tcg_gen_shli_i32(tmp2, tmp2, 16);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1798 break;
18c9b560 1799 }
da6b5335 1800 gen_set_nzcv(tmp);
7d1b0095
PM		 1801 tcg_temp_free_i32(tmp2);
1802 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1803 break;
1804 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1805 wrd = (insn >> 12) & 0xf;
1806 rd0 = (insn >> 16) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0);
1808 switch ((insn >> 22) & 3) {
1809 case 0:
e677137d 1810 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1811 break;
1812 case 1:
e677137d 1813 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1814 break;
1815 case 2:
e677137d 1816 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1817 break;
1818 case 3:
1819 return 1;
1820 }
1821 gen_op_iwmmxt_movq_wRn_M0(wrd);
1822 gen_op_iwmmxt_set_mup();
1823 break;
1824 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1825 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1826 return 1;
da6b5335 1827 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
7d1b0095 1828 tmp2 = tcg_temp_new_i32();
da6b5335 1829 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1830 switch ((insn >> 22) & 3) {
1831 case 0:
1832 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1833 tcg_gen_shli_i32(tmp2, tmp2, 4);
1834 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1835 }
1836 break;
1837 case 1:
1838 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1839 tcg_gen_shli_i32(tmp2, tmp2, 8);
1840 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1841 }
1842 break;
1843 case 2:
da6b5335
FN		 1844 tcg_gen_shli_i32(tmp2, tmp2, 16);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1846 break;
18c9b560 1847 }
da6b5335 1848 gen_set_nzcv(tmp);
7d1b0095
PM		 1849 tcg_temp_free_i32(tmp2);
1850 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1851 break;
1852 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1853 rd = (insn >> 12) & 0xf;
1854 rd0 = (insn >> 16) & 0xf;
da6b5335 1855 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1856 return 1;
1857 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1858 tmp = tcg_temp_new_i32();
18c9b560
AZ		 1859 switch ((insn >> 22) & 3) {
1860 case 0:
da6b5335 1861 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1862 break;
1863 case 1:
da6b5335 1864 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1865 break;
1866 case 2:
da6b5335 1867 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1868 break;
18c9b560 1869 }
da6b5335 1870 store_reg(s, rd, tmp);
18c9b560
AZ		 1871 break;
1872 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1873 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1874 wrd = (insn >> 12) & 0xf;
1875 rd0 = (insn >> 16) & 0xf;
1876 rd1 = (insn >> 0) & 0xf;
1877 gen_op_iwmmxt_movq_M0_wRn(rd0);
1878 switch ((insn >> 22) & 3) {
1879 case 0:
1880 if (insn & (1 << 21))
1881 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1882 else
1883 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1884 break;
1885 case 1:
1886 if (insn & (1 << 21))
1887 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1888 else
1889 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1890 break;
1891 case 2:
1892 if (insn & (1 << 21))
1893 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1894 else
1895 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1896 break;
1897 case 3:
1898 return 1;
1899 }
1900 gen_op_iwmmxt_movq_wRn_M0(wrd);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1903 break;
1904 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1905 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1906 wrd = (insn >> 12) & 0xf;
1907 rd0 = (insn >> 16) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0);
1909 switch ((insn >> 22) & 3) {
1910 case 0:
1911 if (insn & (1 << 21))
1912 gen_op_iwmmxt_unpacklsb_M0();
1913 else
1914 gen_op_iwmmxt_unpacklub_M0();
1915 break;
1916 case 1:
1917 if (insn & (1 << 21))
1918 gen_op_iwmmxt_unpacklsw_M0();
1919 else
1920 gen_op_iwmmxt_unpackluw_M0();
1921 break;
1922 case 2:
1923 if (insn & (1 << 21))
1924 gen_op_iwmmxt_unpacklsl_M0();
1925 else
1926 gen_op_iwmmxt_unpacklul_M0();
1927 break;
1928 case 3:
1929 return 1;
1930 }
1931 gen_op_iwmmxt_movq_wRn_M0(wrd);
1932 gen_op_iwmmxt_set_mup();
1933 gen_op_iwmmxt_set_cup();
1934 break;
1935 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1936 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1937 wrd = (insn >> 12) & 0xf;
1938 rd0 = (insn >> 16) & 0xf;
1939 gen_op_iwmmxt_movq_M0_wRn(rd0);
1940 switch ((insn >> 22) & 3) {
1941 case 0:
1942 if (insn & (1 << 21))
1943 gen_op_iwmmxt_unpackhsb_M0();
1944 else
1945 gen_op_iwmmxt_unpackhub_M0();
1946 break;
1947 case 1:
1948 if (insn & (1 << 21))
1949 gen_op_iwmmxt_unpackhsw_M0();
1950 else
1951 gen_op_iwmmxt_unpackhuw_M0();
1952 break;
1953 case 2:
1954 if (insn & (1 << 21))
1955 gen_op_iwmmxt_unpackhsl_M0();
1956 else
1957 gen_op_iwmmxt_unpackhul_M0();
1958 break;
1959 case 3:
1960 return 1;
1961 }
1962 gen_op_iwmmxt_movq_wRn_M0(wrd);
1963 gen_op_iwmmxt_set_mup();
1964 gen_op_iwmmxt_set_cup();
1965 break;
1966 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1967 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1968 if (((insn >> 22) & 3) == 0)
1969 return 1;
18c9b560
AZ		 1970 wrd = (insn >> 12) & 0xf;
1971 rd0 = (insn >> 16) & 0xf;
1972 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 1973 tmp = tcg_temp_new_i32();
da6b5335 1974 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 1975 tcg_temp_free_i32(tmp);
18c9b560 1976 return 1;
da6b5335 1977 }
18c9b560 1978 switch ((insn >> 22) & 3) {
18c9b560 1979 case 1:
947a2fa2 1980 gen_helper_iwmmxt_srlw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 1981 break;
1982 case 2:
947a2fa2 1983 gen_helper_iwmmxt_srll(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 1984 break;
1985 case 3:
947a2fa2 1986 gen_helper_iwmmxt_srlq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 1987 break;
1988 }
7d1b0095 1989 tcg_temp_free_i32(tmp);
18c9b560
AZ		 1990 gen_op_iwmmxt_movq_wRn_M0(wrd);
1991 gen_op_iwmmxt_set_mup();
1992 gen_op_iwmmxt_set_cup();
1993 break;
1994 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1995 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 1996 if (((insn >> 22) & 3) == 0)
1997 return 1;
18c9b560
AZ		 1998 wrd = (insn >> 12) & 0xf;
1999 rd0 = (insn >> 16) & 0xf;
2000 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2001 tmp = tcg_temp_new_i32();
da6b5335 2002 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 2003 tcg_temp_free_i32(tmp);
18c9b560 2004 return 1;
da6b5335 2005 }
18c9b560 2006 switch ((insn >> 22) & 3) {
18c9b560 2007 case 1:
947a2fa2 2008 gen_helper_iwmmxt_sraw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2009 break;
2010 case 2:
947a2fa2 2011 gen_helper_iwmmxt_sral(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2012 break;
2013 case 3:
947a2fa2 2014 gen_helper_iwmmxt_sraq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2015 break;
2016 }
7d1b0095 2017 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2018 gen_op_iwmmxt_movq_wRn_M0(wrd);
2019 gen_op_iwmmxt_set_mup();
2020 gen_op_iwmmxt_set_cup();
2021 break;
2022 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2023 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2024 if (((insn >> 22) & 3) == 0)
2025 return 1;
18c9b560
AZ		 2026 wrd = (insn >> 12) & 0xf;
2027 rd0 = (insn >> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2029 tmp = tcg_temp_new_i32();
da6b5335 2030 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
7d1b0095 2031 tcg_temp_free_i32(tmp);
18c9b560 2032 return 1;
da6b5335 2033 }
18c9b560 2034 switch ((insn >> 22) & 3) {
18c9b560 2035 case 1:
947a2fa2 2036 gen_helper_iwmmxt_sllw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2037 break;
2038 case 2:
947a2fa2 2039 gen_helper_iwmmxt_slll(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2040 break;
2041 case 3:
947a2fa2 2042 gen_helper_iwmmxt_sllq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2043 break;
2044 }
7d1b0095 2045 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2046 gen_op_iwmmxt_movq_wRn_M0(wrd);
2047 gen_op_iwmmxt_set_mup();
2048 gen_op_iwmmxt_set_cup();
2049 break;
2050 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2051 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2052 if (((insn >> 22) & 3) == 0)
2053 return 1;
18c9b560
AZ		 2054 wrd = (insn >> 12) & 0xf;
2055 rd0 = (insn >> 16) & 0xf;
2056 gen_op_iwmmxt_movq_M0_wRn(rd0);
7d1b0095 2057 tmp = tcg_temp_new_i32();
18c9b560 2058 switch ((insn >> 22) & 3) {
18c9b560 2059 case 1:
da6b5335 2060 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
7d1b0095 2061 tcg_temp_free_i32(tmp);
18c9b560 2062 return 1;
da6b5335 2063 }
947a2fa2 2064 gen_helper_iwmmxt_rorw(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2065 break;
2066 case 2:
da6b5335 2067 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
7d1b0095 2068 tcg_temp_free_i32(tmp);
18c9b560 2069 return 1;
da6b5335 2070 }
947a2fa2 2071 gen_helper_iwmmxt_rorl(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2072 break;
2073 case 3:
da6b5335 2074 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
7d1b0095 2075 tcg_temp_free_i32(tmp);
18c9b560 2076 return 1;
da6b5335 2077 }
947a2fa2 2078 gen_helper_iwmmxt_rorq(cpu_M0, cpu_M0, tmp);
18c9b560
AZ		 2079 break;
2080 }
7d1b0095 2081 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2082 gen_op_iwmmxt_movq_wRn_M0(wrd);
2083 gen_op_iwmmxt_set_mup();
2084 gen_op_iwmmxt_set_cup();
2085 break;
2086 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2087 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2088 wrd = (insn >> 12) & 0xf;
2089 rd0 = (insn >> 16) & 0xf;
2090 rd1 = (insn >> 0) & 0xf;
2091 gen_op_iwmmxt_movq_M0_wRn(rd0);
2092 switch ((insn >> 22) & 3) {
2093 case 0:
2094 if (insn & (1 << 21))
2095 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2096 else
2097 gen_op_iwmmxt_minub_M0_wRn(rd1);
2098 break;
2099 case 1:
2100 if (insn & (1 << 21))
2101 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2102 else
2103 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2104 break;
2105 case 2:
2106 if (insn & (1 << 21))
2107 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2108 else
2109 gen_op_iwmmxt_minul_M0_wRn(rd1);
2110 break;
2111 case 3:
2112 return 1;
2113 }
2114 gen_op_iwmmxt_movq_wRn_M0(wrd);
2115 gen_op_iwmmxt_set_mup();
2116 break;
2117 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2118 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2119 wrd = (insn >> 12) & 0xf;
2120 rd0 = (insn >> 16) & 0xf;
2121 rd1 = (insn >> 0) & 0xf;
2122 gen_op_iwmmxt_movq_M0_wRn(rd0);
2123 switch ((insn >> 22) & 3) {
2124 case 0:
2125 if (insn & (1 << 21))
2126 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2127 else
2128 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2129 break;
2130 case 1:
2131 if (insn & (1 << 21))
2132 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2133 else
2134 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2135 break;
2136 case 2:
2137 if (insn & (1 << 21))
2138 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2139 else
2140 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2141 break;
2142 case 3:
2143 return 1;
2144 }
2145 gen_op_iwmmxt_movq_wRn_M0(wrd);
2146 gen_op_iwmmxt_set_mup();
2147 break;
2148 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2149 case 0x402: case 0x502: case 0x602: case 0x702:
2150 wrd = (insn >> 12) & 0xf;
2151 rd0 = (insn >> 16) & 0xf;
2152 rd1 = (insn >> 0) & 0xf;
2153 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2154 tmp = tcg_const_i32((insn >> 20) & 3);
2155 iwmmxt_load_reg(cpu_V1, rd1);
2156 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2157 tcg_temp_free(tmp);
18c9b560
AZ		 2158 gen_op_iwmmxt_movq_wRn_M0(wrd);
2159 gen_op_iwmmxt_set_mup();
2160 break;
2161 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2162 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2163 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2164 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2165 wrd = (insn >> 12) & 0xf;
2166 rd0 = (insn >> 16) & 0xf;
2167 rd1 = (insn >> 0) & 0xf;
2168 gen_op_iwmmxt_movq_M0_wRn(rd0);
2169 switch ((insn >> 20) & 0xf) {
2170 case 0x0:
2171 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2172 break;
2173 case 0x1:
2174 gen_op_iwmmxt_subub_M0_wRn(rd1);
2175 break;
2176 case 0x3:
2177 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2178 break;
2179 case 0x4:
2180 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2181 break;
2182 case 0x5:
2183 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2184 break;
2185 case 0x7:
2186 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2187 break;
2188 case 0x8:
2189 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2190 break;
2191 case 0x9:
2192 gen_op_iwmmxt_subul_M0_wRn(rd1);
2193 break;
2194 case 0xb:
2195 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2196 break;
2197 default:
2198 return 1;
2199 }
2200 gen_op_iwmmxt_movq_wRn_M0(wrd);
2201 gen_op_iwmmxt_set_mup();
2202 gen_op_iwmmxt_set_cup();
2203 break;
2204 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2205 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2206 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2207 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2208 wrd = (insn >> 12) & 0xf;
2209 rd0 = (insn >> 16) & 0xf;
2210 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2211 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
947a2fa2 2212 gen_helper_iwmmxt_shufh(cpu_M0, cpu_M0, tmp);
da6b5335 2213 tcg_temp_free(tmp);
18c9b560
AZ		 2214 gen_op_iwmmxt_movq_wRn_M0(wrd);
2215 gen_op_iwmmxt_set_mup();
2216 gen_op_iwmmxt_set_cup();
2217 break;
2218 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2219 case 0x418: case 0x518: case 0x618: case 0x718:
2220 case 0x818: case 0x918: case 0xa18: case 0xb18:
2221 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2222 wrd = (insn >> 12) & 0xf;
2223 rd0 = (insn >> 16) & 0xf;
2224 rd1 = (insn >> 0) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0);
2226 switch ((insn >> 20) & 0xf) {
2227 case 0x0:
2228 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2229 break;
2230 case 0x1:
2231 gen_op_iwmmxt_addub_M0_wRn(rd1);
2232 break;
2233 case 0x3:
2234 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2235 break;
2236 case 0x4:
2237 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2238 break;
2239 case 0x5:
2240 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2241 break;
2242 case 0x7:
2243 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2244 break;
2245 case 0x8:
2246 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2247 break;
2248 case 0x9:
2249 gen_op_iwmmxt_addul_M0_wRn(rd1);
2250 break;
2251 case 0xb:
2252 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2253 break;
2254 default:
2255 return 1;
2256 }
2257 gen_op_iwmmxt_movq_wRn_M0(wrd);
2258 gen_op_iwmmxt_set_mup();
2259 gen_op_iwmmxt_set_cup();
2260 break;
2261 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2262 case 0x408: case 0x508: case 0x608: case 0x708:
2263 case 0x808: case 0x908: case 0xa08: case 0xb08:
2264 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2265 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2266 return 1;
18c9b560
AZ		 2267 wrd = (insn >> 12) & 0xf;
2268 rd0 = (insn >> 16) & 0xf;
2269 rd1 = (insn >> 0) & 0xf;
2270 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2271 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2272 case 1:
2273 if (insn & (1 << 21))
2274 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2275 else
2276 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2277 break;
2278 case 2:
2279 if (insn & (1 << 21))
2280 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2281 else
2282 gen_op_iwmmxt_packul_M0_wRn(rd1);
2283 break;
2284 case 3:
2285 if (insn & (1 << 21))
2286 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2287 else
2288 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2289 break;
2290 }
2291 gen_op_iwmmxt_movq_wRn_M0(wrd);
2292 gen_op_iwmmxt_set_mup();
2293 gen_op_iwmmxt_set_cup();
2294 break;
2295 case 0x201: case 0x203: case 0x205: case 0x207:
2296 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2297 case 0x211: case 0x213: case 0x215: case 0x217:
2298 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2299 wrd = (insn >> 5) & 0xf;
2300 rd0 = (insn >> 12) & 0xf;
2301 rd1 = (insn >> 0) & 0xf;
2302 if (rd0 == 0xf || rd1 == 0xf)
2303 return 1;
2304 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2305 tmp = load_reg(s, rd0);
2306 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2307 switch ((insn >> 16) & 0xf) {
2308 case 0x0: /* TMIA */
da6b5335 2309 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2310 break;
2311 case 0x8: /* TMIAPH */
da6b5335 2312 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2313 break;
2314 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2315 if (insn & (1 << 16))
da6b5335 2316 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2317 if (insn & (1 << 17))
da6b5335
FN		 2318 tcg_gen_shri_i32(tmp2, tmp2, 16);
2319 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2320 break;
2321 default:
7d1b0095
PM		 2322 tcg_temp_free_i32(tmp2);
2323 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2324 return 1;
2325 }
7d1b0095
PM		 2326 tcg_temp_free_i32(tmp2);
2327 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2328 gen_op_iwmmxt_movq_wRn_M0(wrd);
2329 gen_op_iwmmxt_set_mup();
2330 break;
2331 default:
2332 return 1;
2333 }
2334
2335 return 0;
2336}
2337
2338/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2339 (ie. an undefined instruction). */
2340static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2341{
2342 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2343 TCGv tmp, tmp2;
18c9b560
AZ		 2344
2345 if ((insn & 0x0ff00f10) == 0x0e200010) {
2346 /* Multiply with Internal Accumulate Format */
2347 rd0 = (insn >> 12) & 0xf;
2348 rd1 = insn & 0xf;
2349 acc = (insn >> 5) & 7;
2350
2351 if (acc != 0)
2352 return 1;
2353
3a554c0f
FN		 2354 tmp = load_reg(s, rd0);
2355 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2356 switch ((insn >> 16) & 0xf) {
2357 case 0x0: /* MIA */
3a554c0f 2358 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2359 break;
2360 case 0x8: /* MIAPH */
3a554c0f 2361 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2362 break;
2363 case 0xc: /* MIABB */
2364 case 0xd: /* MIABT */
2365 case 0xe: /* MIATB */
2366 case 0xf: /* MIATT */
18c9b560 2367 if (insn & (1 << 16))
3a554c0f 2368 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2369 if (insn & (1 << 17))
3a554c0f
FN		 2370 tcg_gen_shri_i32(tmp2, tmp2, 16);
2371 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2372 break;
2373 default:
2374 return 1;
2375 }
7d1b0095
PM		 2376 tcg_temp_free_i32(tmp2);
2377 tcg_temp_free_i32(tmp);
18c9b560
AZ		 2378
2379 gen_op_iwmmxt_movq_wRn_M0(acc);
2380 return 0;
2381 }
2382
2383 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2384 /* Internal Accumulator Access Format */
2385 rdhi = (insn >> 16) & 0xf;
2386 rdlo = (insn >> 12) & 0xf;
2387 acc = insn & 7;
2388
2389 if (acc != 0)
2390 return 1;
2391
2392 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2393 iwmmxt_load_reg(cpu_V0, acc);
2394 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2395 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2396 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2397 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2398 } else { /* MAR */
3a554c0f
FN		 2399 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2400 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2401 }
2402 return 0;
2403 }
2404
2405 return 1;
2406}
2407
c1713132
AZ		 2408/* Disassemble system coprocessor instruction. Return nonzero if
2409 instruction is not defined. */
2410static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2411{
b75263d6 2412 TCGv tmp, tmp2;
c1713132
AZ		 2413 uint32_t rd = (insn >> 12) & 0xf;
2414 uint32_t cp = (insn >> 8) & 0xf;
2415 if (IS_USER(s)) {
2416 return 1;
2417 }
2418
18c9b560 2419 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2420 if (!env->cp[cp].cp_read)
2421 return 1;
8984bd2e 2422 gen_set_pc_im(s->pc);
7d1b0095 2423 tmp = tcg_temp_new_i32();
b75263d6
JR		 2424 tmp2 = tcg_const_i32(insn);
2425 gen_helper_get_cp(tmp, cpu_env, tmp2);
2426 tcg_temp_free(tmp2);
8984bd2e 2427 store_reg(s, rd, tmp);
c1713132
AZ		 2428 } else {
2429 if (!env->cp[cp].cp_write)
2430 return 1;
8984bd2e
PB		 2431 gen_set_pc_im(s->pc);
2432 tmp = load_reg(s, rd);
b75263d6
JR		 2433 tmp2 = tcg_const_i32(insn);
2434 gen_helper_set_cp(cpu_env, tmp2, tmp);
2435 tcg_temp_free(tmp2);
7d1b0095 2436 tcg_temp_free_i32(tmp);
c1713132
AZ		 2437 }
2438 return 0;
2439}
2440
9ee6e8bb
PB		 2441static int cp15_user_ok(uint32_t insn)
2442{
2443 int cpn = (insn >> 16) & 0xf;
2444 int cpm = insn & 0xf;
2445 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2446
2447 if (cpn == 13 && cpm == 0) {
2448 /* TLS register. */
2449 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2450 return 1;
2451 }
2452 if (cpn == 7) {
2453 /* ISB, DSB, DMB. */
2454 if ((cpm == 5 && op == 4)
2455 || (cpm == 10 && (op == 4 || op == 5)))
2456 return 1;
2457 }
2458 return 0;
2459}
2460
3f26c122
RV		 2461static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2462{
2463 TCGv tmp;
2464 int cpn = (insn >> 16) & 0xf;
2465 int cpm = insn & 0xf;
2466 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2467
2468 if (!arm_feature(env, ARM_FEATURE_V6K))
2469 return 0;
2470
2471 if (!(cpn == 13 && cpm == 0))
2472 return 0;
2473
2474 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2475 switch (op) {
2476 case 2:
c5883be2 2477 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2478 break;
2479 case 3:
c5883be2 2480 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2481 break;
2482 case 4:
c5883be2 2483 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2484 break;
2485 default:
3f26c122
RV		 2486 return 0;
2487 }
2488 store_reg(s, rd, tmp);
2489
2490 } else {
2491 tmp = load_reg(s, rd);
2492 switch (op) {
2493 case 2:
c5883be2 2494 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2495 break;
2496 case 3:
c5883be2 2497 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2498 break;
2499 case 4:
c5883be2 2500 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2501 break;
2502 default:
7d1b0095 2503 tcg_temp_free_i32(tmp);
3f26c122
RV		 2504 return 0;
2505 }
3f26c122
RV		 2506 }
2507 return 1;
2508}
2509
b5ff1b31
FB		 2510/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2511 instruction is not defined. */
a90b7318 2512static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2513{
2514 uint32_t rd;
b75263d6 2515 TCGv tmp, tmp2;
b5ff1b31 2516
9ee6e8bb
PB		 2517 /* M profile cores use memory mapped registers instead of cp15. */
2518 if (arm_feature(env, ARM_FEATURE_M))
2519 return 1;
2520
2521 if ((insn & (1 << 25)) == 0) {
2522 if (insn & (1 << 20)) {
2523 /* mrrc */
2524 return 1;
2525 }
2526 /* mcrr. Used for block cache operations, so implement as no-op. */
2527 return 0;
2528 }
2529 if ((insn & (1 << 4)) == 0) {
2530 /* cdp */
2531 return 1;
2532 }
2533 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2534 return 1;
2535 }
cc688901
PM		 2536
2537 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2538 * instructions rather than a separate instruction.
2539 */
2540 if ((insn & 0x0fff0fff) == 0x0e070f90) {
2541 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2542 * In v7, this must NOP.
2543 */
2544 if (!arm_feature(env, ARM_FEATURE_V7)) {
2545 /* Wait for interrupt. */
2546 gen_set_pc_im(s->pc);
2547 s->is_jmp = DISAS_WFI;
2548 }
9332f9da
FB		 2549 return 0;
2550 }
cc688901
PM		 2551
2552 if ((insn & 0x0fff0fff) == 0x0e070f58) {
2553 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2554 * so this is slightly over-broad.
2555 */
2556 if (!arm_feature(env, ARM_FEATURE_V6)) {
2557 /* Wait for interrupt. */
2558 gen_set_pc_im(s->pc);
2559 s->is_jmp = DISAS_WFI;
2560 return 0;
2561 }
2562 /* Otherwise fall through to handle via helper function.
2563 * In particular, on v7 and some v6 cores this is one of
2564 * the VA-PA registers.
2565 */
2566 }
2567
b5ff1b31 2568 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2569
2570 if (cp15_tls_load_store(env, s, insn, rd))
2571 return 0;
2572
b75263d6 2573 tmp2 = tcg_const_i32(insn);
18c9b560 2574 if (insn & ARM_CP_RW_BIT) {
7d1b0095 2575 tmp = tcg_temp_new_i32();
b75263d6 2576 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2577 /* If the destination register is r15 then sets condition codes. */
2578 if (rd != 15)
8984bd2e
PB		 2579 store_reg(s, rd, tmp);
2580 else
7d1b0095 2581 tcg_temp_free_i32(tmp);
b5ff1b31 2582 } else {
8984bd2e 2583 tmp = load_reg(s, rd);
b75263d6 2584 gen_helper_set_cp15(cpu_env, tmp2, tmp);
7d1b0095 2585 tcg_temp_free_i32(tmp);
a90b7318
AZ		 2586 /* Normally we would always end the TB here, but Linux
2587 * arch/arm/mach-pxa/sleep.S expects two instructions following
2588 * an MMU enable to execute from cache. Imitate this behaviour. */
2589 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2590 (insn & 0x0fff0fff) != 0x0e010f10)
2591 gen_lookup_tb(s);
b5ff1b31 2592 }
b75263d6 2593 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2594 return 0;
2595}
2596
9ee6e8bb
PB		 2597#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2598#define VFP_SREG(insn, bigbit, smallbit) \
2599 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2600#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2601 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2602 reg = (((insn) >> (bigbit)) & 0x0f) \
2603 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2604 } else { \
2605 if (insn & (1 << (smallbit))) \
2606 return 1; \
2607 reg = ((insn) >> (bigbit)) & 0x0f; \
2608 }} while (0)
2609
2610#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2611#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2612#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2613#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2614#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2615#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2616
4373f3ce
PB		 2617/* Move between integer and VFP cores. */
2618static TCGv gen_vfp_mrs(void)
2619{
7d1b0095 2620 TCGv tmp = tcg_temp_new_i32();
4373f3ce
PB		 2621 tcg_gen_mov_i32(tmp, cpu_F0s);
2622 return tmp;
2623}
2624
2625static void gen_vfp_msr(TCGv tmp)
2626{
2627 tcg_gen_mov_i32(cpu_F0s, tmp);
7d1b0095 2628 tcg_temp_free_i32(tmp);
4373f3ce
PB		 2629}
2630
ad69471c
PB		 2631static void gen_neon_dup_u8(TCGv var, int shift)
2632{
7d1b0095 2633 TCGv tmp = tcg_temp_new_i32();
ad69471c
PB		 2634 if (shift)
2635 tcg_gen_shri_i32(var, var, shift);
86831435 2636 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2637 tcg_gen_shli_i32(tmp, var, 8);
2638 tcg_gen_or_i32(var, var, tmp);
2639 tcg_gen_shli_i32(tmp, var, 16);
2640 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2641 tcg_temp_free_i32(tmp);
ad69471c
PB		 2642}
2643
2644static void gen_neon_dup_low16(TCGv var)
2645{
7d1b0095 2646 TCGv tmp = tcg_temp_new_i32();
86831435 2647 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2648 tcg_gen_shli_i32(tmp, var, 16);
2649 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2650 tcg_temp_free_i32(tmp);
ad69471c
PB		 2651}
2652
2653static void gen_neon_dup_high16(TCGv var)
2654{
7d1b0095 2655 TCGv tmp = tcg_temp_new_i32();
ad69471c
PB		 2656 tcg_gen_andi_i32(var, var, 0xffff0000);
2657 tcg_gen_shri_i32(tmp, var, 16);
2658 tcg_gen_or_i32(var, var, tmp);
7d1b0095 2659 tcg_temp_free_i32(tmp);
ad69471c
PB		 2660}
2661
8e18cde3
PM		 2662static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
2663{
2664 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2665 TCGv tmp;
2666 switch (size) {
2667 case 0:
2668 tmp = gen_ld8u(addr, IS_USER(s));
2669 gen_neon_dup_u8(tmp, 0);
2670 break;
2671 case 1:
2672 tmp = gen_ld16u(addr, IS_USER(s));
2673 gen_neon_dup_low16(tmp);
2674 break;
2675 case 2:
2676 tmp = gen_ld32(addr, IS_USER(s));
2677 break;
2678 default: /* Avoid compiler warnings. */
2679 abort();
2680 }
2681 return tmp;
2682}
2683
b7bcbe95
FB		 2684/* Disassemble a VFP instruction. Returns nonzero if an error occured
2685 (ie. an undefined instruction). */
2686static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2687{
2688 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2689 int dp, veclen;
312eea9f 2690 TCGv addr;
4373f3ce 2691 TCGv tmp;
ad69471c 2692 TCGv tmp2;
b7bcbe95 2693
40f137e1
PB		 2694 if (!arm_feature(env, ARM_FEATURE_VFP))
2695 return 1;
2696
5df8bac1 2697 if (!s->vfp_enabled) {
9ee6e8bb 2698 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2699 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2700 return 1;
2701 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2702 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2703 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2704 return 1;
2705 }
b7bcbe95
FB		 2706 dp = ((insn & 0xf00) == 0xb00);
2707 switch ((insn >> 24) & 0xf) {
2708 case 0xe:
2709 if (insn & (1 << 4)) {
2710 /* single register transfer */
b7bcbe95
FB		 2711 rd = (insn >> 12) & 0xf;
2712 if (dp) {
9ee6e8bb
PB		 2713 int size;
2714 int pass;
2715
2716 VFP_DREG_N(rn, insn);
2717 if (insn & 0xf)
b7bcbe95 2718 return 1;
9ee6e8bb
PB		 2719 if (insn & 0x00c00060
2720 && !arm_feature(env, ARM_FEATURE_NEON))
2721 return 1;
2722
2723 pass = (insn >> 21) & 1;
2724 if (insn & (1 << 22)) {
2725 size = 0;
2726 offset = ((insn >> 5) & 3) * 8;
2727 } else if (insn & (1 << 5)) {
2728 size = 1;
2729 offset = (insn & (1 << 6)) ? 16 : 0;
2730 } else {
2731 size = 2;
2732 offset = 0;
2733 }
18c9b560 2734 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2735 /* vfp->arm */
ad69471c 2736 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2737 switch (size) {
2738 case 0:
9ee6e8bb 2739 if (offset)
ad69471c 2740 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2741 if (insn & (1 << 23))
ad69471c 2742 gen_uxtb(tmp);
9ee6e8bb 2743 else
ad69471c 2744 gen_sxtb(tmp);
9ee6e8bb
PB		 2745 break;
2746 case 1:
9ee6e8bb
PB		 2747 if (insn & (1 << 23)) {
2748 if (offset) {
ad69471c 2749 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2750 } else {
ad69471c 2751 gen_uxth(tmp);
9ee6e8bb
PB		 2752 }
2753 } else {
2754 if (offset) {
ad69471c 2755 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2756 } else {
ad69471c 2757 gen_sxth(tmp);
9ee6e8bb
PB		 2758 }
2759 }
2760 break;
2761 case 2:
9ee6e8bb
PB		 2762 break;
2763 }
ad69471c 2764 store_reg(s, rd, tmp);
b7bcbe95
FB		 2765 } else {
2766 /* arm->vfp */
ad69471c 2767 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2768 if (insn & (1 << 23)) {
2769 /* VDUP */
2770 if (size == 0) {
ad69471c 2771 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2772 } else if (size == 1) {
ad69471c 2773 gen_neon_dup_low16(tmp);
9ee6e8bb 2774 }
cbbccffc 2775 for (n = 0; n <= pass * 2; n++) {
7d1b0095 2776 tmp2 = tcg_temp_new_i32();
cbbccffc
PB		 2777 tcg_gen_mov_i32(tmp2, tmp);
2778 neon_store_reg(rn, n, tmp2);
2779 }
2780 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2781 } else {
2782 /* VMOV */
2783 switch (size) {
2784 case 0:
ad69471c
PB		 2785 tmp2 = neon_load_reg(rn, pass);
2786 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
7d1b0095 2787 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 2788 break;
2789 case 1:
ad69471c
PB		 2790 tmp2 = neon_load_reg(rn, pass);
2791 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
7d1b0095 2792 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 2793 break;
2794 case 2:
9ee6e8bb
PB		 2795 break;
2796 }
ad69471c 2797 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2798 }
b7bcbe95 2799 }
9ee6e8bb
PB		 2800 } else { /* !dp */
2801 if ((insn & 0x6f) != 0x00)
2802 return 1;
2803 rn = VFP_SREG_N(insn);
18c9b560 2804 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2805 /* vfp->arm */
2806 if (insn & (1 << 21)) {
2807 /* system register */
40f137e1 2808 rn >>= 1;
9ee6e8bb 2809
b7bcbe95 2810 switch (rn) {
40f137e1 2811 case ARM_VFP_FPSID:
4373f3ce 2812 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2813 VFP3 restricts all id registers to privileged
2814 accesses. */
2815 if (IS_USER(s)
2816 && arm_feature(env, ARM_FEATURE_VFP3))
2817 return 1;
4373f3ce 2818 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2819 break;
40f137e1 2820 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2821 if (IS_USER(s))
2822 return 1;
4373f3ce 2823 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2824 break;
40f137e1
PB		 2825 case ARM_VFP_FPINST:
2826 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2827 /* Not present in VFP3. */
2828 if (IS_USER(s)
2829 || arm_feature(env, ARM_FEATURE_VFP3))
2830 return 1;
4373f3ce 2831 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2832 break;
40f137e1 2833 case ARM_VFP_FPSCR:
601d70b9 2834 if (rd == 15) {
4373f3ce
PB		 2835 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2836 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2837 } else {
7d1b0095 2838 tmp = tcg_temp_new_i32();
4373f3ce
PB		 2839 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2840 }
b7bcbe95 2841 break;
9ee6e8bb
PB		 2842 case ARM_VFP_MVFR0:
2843 case ARM_VFP_MVFR1:
2844 if (IS_USER(s)
2845 || !arm_feature(env, ARM_FEATURE_VFP3))
2846 return 1;
4373f3ce 2847 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2848 break;
b7bcbe95
FB		 2849 default:
2850 return 1;
2851 }
2852 } else {
2853 gen_mov_F0_vreg(0, rn);
4373f3ce 2854 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2855 }
2856 if (rd == 15) {
b5ff1b31 2857 /* Set the 4 flag bits in the CPSR. */
4373f3ce 2858 gen_set_nzcv(tmp);
7d1b0095 2859 tcg_temp_free_i32(tmp);
4373f3ce
PB		 2860 } else {
2861 store_reg(s, rd, tmp);
2862 }
b7bcbe95
FB		 2863 } else {
2864 /* arm->vfp */
4373f3ce 2865 tmp = load_reg(s, rd);
b7bcbe95 2866 if (insn & (1 << 21)) {
40f137e1 2867 rn >>= 1;
b7bcbe95
FB		 2868 /* system register */
2869 switch (rn) {
40f137e1 2870 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2871 case ARM_VFP_MVFR0:
2872 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2873 /* Writes are ignored. */
2874 break;
40f137e1 2875 case ARM_VFP_FPSCR:
4373f3ce 2876 gen_helper_vfp_set_fpscr(cpu_env, tmp);
7d1b0095 2877 tcg_temp_free_i32(tmp);
b5ff1b31 2878 gen_lookup_tb(s);
b7bcbe95 2879 break;
40f137e1 2880 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2881 if (IS_USER(s))
2882 return 1;
71b3c3de
JR		 2883 /* TODO: VFP subarchitecture support.
2884 * For now, keep the EN bit only */
2885 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2886 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2887 gen_lookup_tb(s);
2888 break;
2889 case ARM_VFP_FPINST:
2890 case ARM_VFP_FPINST2:
4373f3ce 2891 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2892 break;
b7bcbe95
FB		 2893 default:
2894 return 1;
2895 }
2896 } else {
4373f3ce 2897 gen_vfp_msr(tmp);
b7bcbe95
FB		 2898 gen_mov_vreg_F0(0, rn);
2899 }
2900 }
2901 }
2902 } else {
2903 /* data processing */
2904 /* The opcode is in bits 23, 21, 20 and 6. */
2905 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2906 if (dp) {
2907 if (op == 15) {
2908 /* rn is opcode */
2909 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2910 } else {
2911 /* rn is register number */
9ee6e8bb 2912 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2913 }
2914
04595bf6 2915 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
b7bcbe95 2916 /* Integer or single precision destination. */
9ee6e8bb 2917 rd = VFP_SREG_D(insn);
b7bcbe95 2918 } else {
9ee6e8bb 2919 VFP_DREG_D(rd, insn);
b7bcbe95 2920 }
04595bf6
PM		 2921 if (op == 15 &&
2922 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2923 /* VCVT from int is always from S reg regardless of dp bit.
2924 * VCVT with immediate frac_bits has same format as SREG_M
2925 */
2926 rm = VFP_SREG_M(insn);
b7bcbe95 2927 } else {
9ee6e8bb 2928 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2929 }
2930 } else {
9ee6e8bb 2931 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2932 if (op == 15 && rn == 15) {
2933 /* Double precision destination. */
9ee6e8bb
PB		 2934 VFP_DREG_D(rd, insn);
2935 } else {
2936 rd = VFP_SREG_D(insn);
2937 }
04595bf6
PM		 2938 /* NB that we implicitly rely on the encoding for the frac_bits
2939 * in VCVT of fixed to float being the same as that of an SREG_M
2940 */
9ee6e8bb 2941 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2942 }
2943
69d1fc22 2944 veclen = s->vec_len;
b7bcbe95
FB		 2945 if (op == 15 && rn > 3)
2946 veclen = 0;
2947
2948 /* Shut up compiler warnings. */
2949 delta_m = 0;
2950 delta_d = 0;
2951 bank_mask = 0;
3b46e624 2952
b7bcbe95
FB		 2953 if (veclen > 0) {
2954 if (dp)
2955 bank_mask = 0xc;
2956 else
2957 bank_mask = 0x18;
2958
2959 /* Figure out what type of vector operation this is. */
2960 if ((rd & bank_mask) == 0) {
2961 /* scalar */
2962 veclen = 0;
2963 } else {
2964 if (dp)
69d1fc22 2965 delta_d = (s->vec_stride >> 1) + 1;
b7bcbe95 2966 else
69d1fc22 2967 delta_d = s->vec_stride + 1;
b7bcbe95
FB		 2968
2969 if ((rm & bank_mask) == 0) {
2970 /* mixed scalar/vector */
2971 delta_m = 0;
2972 } else {
2973 /* vector */
2974 delta_m = delta_d;
2975 }
2976 }
2977 }
2978
2979 /* Load the initial operands. */
2980 if (op == 15) {
2981 switch (rn) {
2982 case 16:
2983 case 17:
2984 /* Integer source */
2985 gen_mov_F0_vreg(0, rm);
2986 break;
2987 case 8:
2988 case 9:
2989 /* Compare */
2990 gen_mov_F0_vreg(dp, rd);
2991 gen_mov_F1_vreg(dp, rm);
2992 break;
2993 case 10:
2994 case 11:
2995 /* Compare with zero */
2996 gen_mov_F0_vreg(dp, rd);
2997 gen_vfp_F1_ld0(dp);
2998 break;
9ee6e8bb
PB		 2999 case 20:
3000 case 21:
3001 case 22:
3002 case 23:
644ad806
PB		 3003 case 28:
3004 case 29:
3005 case 30:
3006 case 31:
9ee6e8bb
PB		 3007 /* Source and destination the same. */
3008 gen_mov_F0_vreg(dp, rd);
3009 break;
b7bcbe95
FB		 3010 default:
3011 /* One source operand. */
3012 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 3013 break;
b7bcbe95
FB		 3014 }
3015 } else {
3016 /* Two source operands. */
3017 gen_mov_F0_vreg(dp, rn);
3018 gen_mov_F1_vreg(dp, rm);
3019 }
3020
3021 for (;;) {
3022 /* Perform the calculation. */
3023 switch (op) {
3024 case 0: /* mac: fd + (fn * fm) */
3025 gen_vfp_mul(dp);
3026 gen_mov_F1_vreg(dp, rd);
3027 gen_vfp_add(dp);
3028 break;
3029 case 1: /* nmac: fd - (fn * fm) */
3030 gen_vfp_mul(dp);
3031 gen_vfp_neg(dp);
3032 gen_mov_F1_vreg(dp, rd);
3033 gen_vfp_add(dp);
3034 break;
3035 case 2: /* msc: -fd + (fn * fm) */
3036 gen_vfp_mul(dp);
3037 gen_mov_F1_vreg(dp, rd);
3038 gen_vfp_sub(dp);
3039 break;
3040 case 3: /* nmsc: -fd - (fn * fm) */
3041 gen_vfp_mul(dp);
b7bcbe95 3042 gen_vfp_neg(dp);
c9fb531a
PB		 3043 gen_mov_F1_vreg(dp, rd);
3044 gen_vfp_sub(dp);
b7bcbe95
FB		 3045 break;
3046 case 4: /* mul: fn * fm */
3047 gen_vfp_mul(dp);
3048 break;
3049 case 5: /* nmul: -(fn * fm) */
3050 gen_vfp_mul(dp);
3051 gen_vfp_neg(dp);
3052 break;
3053 case 6: /* add: fn + fm */
3054 gen_vfp_add(dp);
3055 break;
3056 case 7: /* sub: fn - fm */
3057 gen_vfp_sub(dp);
3058 break;
3059 case 8: /* div: fn / fm */
3060 gen_vfp_div(dp);
3061 break;
9ee6e8bb
PB		 3062 case 14: /* fconst */
3063 if (!arm_feature(env, ARM_FEATURE_VFP3))
3064 return 1;
3065
3066 n = (insn << 12) & 0x80000000;
3067 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3068 if (dp) {
3069 if (i & 0x40)
3070 i |= 0x3f80;
3071 else
3072 i |= 0x4000;
3073 n |= i << 16;
4373f3ce 3074 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3075 } else {
3076 if (i & 0x40)
3077 i |= 0x780;
3078 else
3079 i |= 0x800;
3080 n |= i << 19;
5b340b51 3081 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3082 }
9ee6e8bb 3083 break;
b7bcbe95
FB		 3084 case 15: /* extension space */
3085 switch (rn) {
3086 case 0: /* cpy */
3087 /* no-op */
3088 break;
3089 case 1: /* abs */
3090 gen_vfp_abs(dp);
3091 break;
3092 case 2: /* neg */
3093 gen_vfp_neg(dp);
3094 break;
3095 case 3: /* sqrt */
3096 gen_vfp_sqrt(dp);
3097 break;
60011498
PB		 3098 case 4: /* vcvtb.f32.f16 */
3099 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3100 return 1;
3101 tmp = gen_vfp_mrs();
3102 tcg_gen_ext16u_i32(tmp, tmp);
3103 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
7d1b0095 3104 tcg_temp_free_i32(tmp);
60011498
PB		 3105 break;
3106 case 5: /* vcvtt.f32.f16 */
3107 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3108 return 1;
3109 tmp = gen_vfp_mrs();
3110 tcg_gen_shri_i32(tmp, tmp, 16);
3111 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
7d1b0095 3112 tcg_temp_free_i32(tmp);
60011498
PB		 3113 break;
3114 case 6: /* vcvtb.f16.f32 */
3115 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3116 return 1;
7d1b0095 3117 tmp = tcg_temp_new_i32();
60011498
PB		 3118 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3119 gen_mov_F0_vreg(0, rd);
3120 tmp2 = gen_vfp_mrs();
3121 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3122 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3123 tcg_temp_free_i32(tmp2);
60011498
PB		 3124 gen_vfp_msr(tmp);
3125 break;
3126 case 7: /* vcvtt.f16.f32 */
3127 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3128 return 1;
7d1b0095 3129 tmp = tcg_temp_new_i32();
60011498
PB		 3130 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3131 tcg_gen_shli_i32(tmp, tmp, 16);
3132 gen_mov_F0_vreg(0, rd);
3133 tmp2 = gen_vfp_mrs();
3134 tcg_gen_ext16u_i32(tmp2, tmp2);
3135 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3136 tcg_temp_free_i32(tmp2);
60011498
PB		 3137 gen_vfp_msr(tmp);
3138 break;
b7bcbe95
FB		 3139 case 8: /* cmp */
3140 gen_vfp_cmp(dp);
3141 break;
3142 case 9: /* cmpe */
3143 gen_vfp_cmpe(dp);
3144 break;
3145 case 10: /* cmpz */
3146 gen_vfp_cmp(dp);
3147 break;
3148 case 11: /* cmpez */
3149 gen_vfp_F1_ld0(dp);
3150 gen_vfp_cmpe(dp);
3151 break;
3152 case 15: /* single<->double conversion */
3153 if (dp)
4373f3ce 3154 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3155 else
4373f3ce 3156 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3157 break;
3158 case 16: /* fuito */
3159 gen_vfp_uito(dp);
3160 break;
3161 case 17: /* fsito */
3162 gen_vfp_sito(dp);
3163 break;
9ee6e8bb
PB		 3164 case 20: /* fshto */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
644ad806 3167 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3168 break;
3169 case 21: /* fslto */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
644ad806 3172 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3173 break;
3174 case 22: /* fuhto */
3175 if (!arm_feature(env, ARM_FEATURE_VFP3))
3176 return 1;
644ad806 3177 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3178 break;
3179 case 23: /* fulto */
3180 if (!arm_feature(env, ARM_FEATURE_VFP3))
3181 return 1;
644ad806 3182 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3183 break;
b7bcbe95
FB		 3184 case 24: /* ftoui */
3185 gen_vfp_toui(dp);
3186 break;
3187 case 25: /* ftouiz */
3188 gen_vfp_touiz(dp);
3189 break;
3190 case 26: /* ftosi */
3191 gen_vfp_tosi(dp);
3192 break;
3193 case 27: /* ftosiz */
3194 gen_vfp_tosiz(dp);
3195 break;
9ee6e8bb
PB		 3196 case 28: /* ftosh */
3197 if (!arm_feature(env, ARM_FEATURE_VFP3))
3198 return 1;
644ad806 3199 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3200 break;
3201 case 29: /* ftosl */
3202 if (!arm_feature(env, ARM_FEATURE_VFP3))
3203 return 1;
644ad806 3204 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3205 break;
3206 case 30: /* ftouh */
3207 if (!arm_feature(env, ARM_FEATURE_VFP3))
3208 return 1;
644ad806 3209 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3210 break;
3211 case 31: /* ftoul */
3212 if (!arm_feature(env, ARM_FEATURE_VFP3))
3213 return 1;
644ad806 3214 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3215 break;
b7bcbe95
FB		 3216 default: /* undefined */
3217 printf ("rn:%d\n", rn);
3218 return 1;
3219 }
3220 break;
3221 default: /* undefined */
3222 printf ("op:%d\n", op);
3223 return 1;
3224 }
3225
3226 /* Write back the result. */
3227 if (op == 15 && (rn >= 8 && rn <= 11))
3228 ; /* Comparison, do nothing. */
04595bf6
PM		 3229 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3230 /* VCVT double to int: always integer result. */
b7bcbe95
FB		 3231 gen_mov_vreg_F0(0, rd);
3232 else if (op == 15 && rn == 15)
3233 /* conversion */
3234 gen_mov_vreg_F0(!dp, rd);
3235 else
3236 gen_mov_vreg_F0(dp, rd);
3237
3238 /* break out of the loop if we have finished */
3239 if (veclen == 0)
3240 break;
3241
3242 if (op == 15 && delta_m == 0) {
3243 /* single source one-many */
3244 while (veclen--) {
3245 rd = ((rd + delta_d) & (bank_mask - 1))
3246 | (rd & bank_mask);
3247 gen_mov_vreg_F0(dp, rd);
3248 }
3249 break;
3250 }
3251 /* Setup the next operands. */
3252 veclen--;
3253 rd = ((rd + delta_d) & (bank_mask - 1))
3254 | (rd & bank_mask);
3255
3256 if (op == 15) {
3257 /* One source operand. */
3258 rm = ((rm + delta_m) & (bank_mask - 1))
3259 | (rm & bank_mask);
3260 gen_mov_F0_vreg(dp, rm);
3261 } else {
3262 /* Two source operands. */
3263 rn = ((rn + delta_d) & (bank_mask - 1))
3264 | (rn & bank_mask);
3265 gen_mov_F0_vreg(dp, rn);
3266 if (delta_m) {
3267 rm = ((rm + delta_m) & (bank_mask - 1))
3268 | (rm & bank_mask);
3269 gen_mov_F1_vreg(dp, rm);
3270 }
3271 }
3272 }
3273 }
3274 break;
3275 case 0xc:
3276 case 0xd:
8387da81 3277 if ((insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3278 /* two-register transfer */
3279 rn = (insn >> 16) & 0xf;
3280 rd = (insn >> 12) & 0xf;
3281 if (dp) {
9ee6e8bb
PB		 3282 VFP_DREG_M(rm, insn);
3283 } else {
3284 rm = VFP_SREG_M(insn);
3285 }
b7bcbe95 3286
18c9b560 3287 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3288 /* vfp->arm */
3289 if (dp) {
4373f3ce
PB		 3290 gen_mov_F0_vreg(0, rm * 2);
3291 tmp = gen_vfp_mrs();
3292 store_reg(s, rd, tmp);
3293 gen_mov_F0_vreg(0, rm * 2 + 1);
3294 tmp = gen_vfp_mrs();
3295 store_reg(s, rn, tmp);
b7bcbe95
FB		 3296 } else {
3297 gen_mov_F0_vreg(0, rm);
4373f3ce 3298 tmp = gen_vfp_mrs();
8387da81 3299 store_reg(s, rd, tmp);
b7bcbe95 3300 gen_mov_F0_vreg(0, rm + 1);
4373f3ce 3301 tmp = gen_vfp_mrs();
8387da81 3302 store_reg(s, rn, tmp);
b7bcbe95
FB		 3303 }
3304 } else {
3305 /* arm->vfp */
3306 if (dp) {
4373f3ce
PB		 3307 tmp = load_reg(s, rd);
3308 gen_vfp_msr(tmp);
3309 gen_mov_vreg_F0(0, rm * 2);
3310 tmp = load_reg(s, rn);
3311 gen_vfp_msr(tmp);
3312 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3313 } else {
8387da81 3314 tmp = load_reg(s, rd);
4373f3ce 3315 gen_vfp_msr(tmp);
b7bcbe95 3316 gen_mov_vreg_F0(0, rm);
8387da81 3317 tmp = load_reg(s, rn);
4373f3ce 3318 gen_vfp_msr(tmp);
b7bcbe95
FB		 3319 gen_mov_vreg_F0(0, rm + 1);
3320 }
3321 }
3322 } else {
3323 /* Load/store */
3324 rn = (insn >> 16) & 0xf;
3325 if (dp)
9ee6e8bb 3326 VFP_DREG_D(rd, insn);
b7bcbe95 3327 else
9ee6e8bb
PB		 3328 rd = VFP_SREG_D(insn);
3329 if (s->thumb && rn == 15) {
7d1b0095 3330 addr = tcg_temp_new_i32();
312eea9f 3331 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3332 } else {
312eea9f 3333 addr = load_reg(s, rn);
9ee6e8bb 3334 }
b7bcbe95
FB		 3335 if ((insn & 0x01200000) == 0x01000000) {
3336 /* Single load/store */
3337 offset = (insn & 0xff) << 2;
3338 if ((insn & (1 << 23)) == 0)
3339 offset = -offset;
312eea9f 3340 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3341 if (insn & (1 << 20)) {
312eea9f 3342 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3343 gen_mov_vreg_F0(dp, rd);
3344 } else {
3345 gen_mov_F0_vreg(dp, rd);
312eea9f 3346 gen_vfp_st(s, dp, addr);
b7bcbe95 3347 }
7d1b0095 3348 tcg_temp_free_i32(addr);
b7bcbe95
FB		 3349 } else {
3350 /* load/store multiple */
3351 if (dp)
3352 n = (insn >> 1) & 0x7f;
3353 else
3354 n = insn & 0xff;
3355
3356 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3357 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3358
3359 if (dp)
3360 offset = 8;
3361 else
3362 offset = 4;
3363 for (i = 0; i < n; i++) {
18c9b560 3364 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3365 /* load */
312eea9f 3366 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3367 gen_mov_vreg_F0(dp, rd + i);
3368 } else {
3369 /* store */
3370 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3371 gen_vfp_st(s, dp, addr);
b7bcbe95 3372 }
312eea9f 3373 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3374 }
3375 if (insn & (1 << 21)) {
3376 /* writeback */
3377 if (insn & (1 << 24))
3378 offset = -offset * n;
3379 else if (dp && (insn & 1))
3380 offset = 4;
3381 else
3382 offset = 0;
3383
3384 if (offset != 0)
312eea9f
FN		 3385 tcg_gen_addi_i32(addr, addr, offset);
3386 store_reg(s, rn, addr);
3387 } else {
7d1b0095 3388 tcg_temp_free_i32(addr);
b7bcbe95
FB		 3389 }
3390 }
3391 }
3392 break;
3393 default:
3394 /* Should never happen. */
3395 return 1;
3396 }
3397 return 0;
3398}
3399
6e256c93 3400static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3401{
6e256c93
FB		 3402 TranslationBlock *tb;
3403
3404 tb = s->tb;
3405 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3406 tcg_gen_goto_tb(n);
8984bd2e 3407 gen_set_pc_im(dest);
4b4a72e5 3408 tcg_gen_exit_tb((tcg_target_long)tb + n);
6e256c93 3409 } else {
8984bd2e 3410 gen_set_pc_im(dest);
57fec1fe 3411 tcg_gen_exit_tb(0);
6e256c93 3412 }
c53be334
FB		 3413}
3414
8aaca4c0
FB		 3415static inline void gen_jmp (DisasContext *s, uint32_t dest)
3416{
551bd27f 3417 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3418 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3419 if (s->thumb)
d9ba4830
PB		 3420 dest |= 1;
3421 gen_bx_im(s, dest);
8aaca4c0 3422 } else {
6e256c93 3423 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3424 s->is_jmp = DISAS_TB_JUMP;
3425 }
3426}
3427
d9ba4830 3428static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3429{
ee097184 3430 if (x)
d9ba4830 3431 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3432 else
d9ba4830 3433 gen_sxth(t0);
ee097184 3434 if (y)
d9ba4830 3435 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3436 else
d9ba4830
PB		 3437 gen_sxth(t1);
3438 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3439}
3440
3441/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3442static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3443 uint32_t mask;
3444
3445 mask = 0;
3446 if (flags & (1 << 0))
3447 mask |= 0xff;
3448 if (flags & (1 << 1))
3449 mask |= 0xff00;
3450 if (flags & (1 << 2))
3451 mask |= 0xff0000;
3452 if (flags & (1 << 3))
3453 mask |= 0xff000000;
9ee6e8bb 3454
2ae23e75 3455 /* Mask out undefined bits. */
9ee6e8bb 3456 mask &= ~CPSR_RESERVED;
be5e7a76
DES		 3457 if (!arm_feature(env, ARM_FEATURE_V4T))
3458 mask &= ~CPSR_T;
3459 if (!arm_feature(env, ARM_FEATURE_V5))
3460 mask &= ~CPSR_Q; /* V5TE in reality*/
9ee6e8bb 3461 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3462 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3463 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3464 mask &= ~CPSR_IT;
9ee6e8bb 3465 /* Mask out execution state bits. */
2ae23e75 3466 if (!spsr)
e160c51c 3467 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3468 /* Mask out privileged bits. */
3469 if (IS_USER(s))
9ee6e8bb 3470 mask &= CPSR_USER;
b5ff1b31
FB		 3471 return mask;
3472}
3473
2fbac54b
FN		 3474/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3475static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3476{
d9ba4830 3477 TCGv tmp;
b5ff1b31
FB		 3478 if (spsr) {
3479 /* ??? This is also undefined in system mode. */
3480 if (IS_USER(s))
3481 return 1;
d9ba4830
PB		 3482
3483 tmp = load_cpu_field(spsr);
3484 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3485 tcg_gen_andi_i32(t0, t0, mask);
3486 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3487 store_cpu_field(tmp, spsr);
b5ff1b31 3488 } else {
2fbac54b 3489 gen_set_cpsr(t0, mask);
b5ff1b31 3490 }
7d1b0095 3491 tcg_temp_free_i32(t0);
b5ff1b31
FB		 3492 gen_lookup_tb(s);
3493 return 0;
3494}
3495
2fbac54b
FN		 3496/* Returns nonzero if access to the PSR is not permitted. */
3497static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3498{
3499 TCGv tmp;
7d1b0095 3500 tmp = tcg_temp_new_i32();
2fbac54b
FN		 3501 tcg_gen_movi_i32(tmp, val);
3502 return gen_set_psr(s, mask, spsr, tmp);
3503}
3504
e9bb4aa9
JR		 3505/* Generate an old-style exception return. Marks pc as dead. */
3506static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3507{
d9ba4830 3508 TCGv tmp;
e9bb4aa9 3509 store_reg(s, 15, pc);
d9ba4830
PB		 3510 tmp = load_cpu_field(spsr);
3511 gen_set_cpsr(tmp, 0xffffffff);
7d1b0095 3512 tcg_temp_free_i32(tmp);
b5ff1b31
FB		 3513 s->is_jmp = DISAS_UPDATE;
3514}
3515
b0109805
PB		 3516/* Generate a v6 exception return. Marks both values as dead. */
3517static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3518{
b0109805 3519 gen_set_cpsr(cpsr, 0xffffffff);
7d1b0095 3520 tcg_temp_free_i32(cpsr);
b0109805 3521 store_reg(s, 15, pc);
9ee6e8bb
PB		 3522 s->is_jmp = DISAS_UPDATE;
3523}
3b46e624 3524
9ee6e8bb
PB		 3525static inline void
3526gen_set_condexec (DisasContext *s)
3527{
3528 if (s->condexec_mask) {
8f01245e 3529 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
7d1b0095 3530 TCGv tmp = tcg_temp_new_i32();
8f01245e 3531 tcg_gen_movi_i32(tmp, val);
d9ba4830 3532 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3533 }
3534}
3b46e624 3535
bc4a0de0
PM		 3536static void gen_exception_insn(DisasContext *s, int offset, int excp)
3537{
3538 gen_set_condexec(s);
3539 gen_set_pc_im(s->pc - offset);
3540 gen_exception(excp);
3541 s->is_jmp = DISAS_JUMP;
3542}
3543
9ee6e8bb
PB		 3544static void gen_nop_hint(DisasContext *s, int val)
3545{
3546 switch (val) {
3547 case 3: /* wfi */
8984bd2e 3548 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3549 s->is_jmp = DISAS_WFI;
3550 break;
3551 case 2: /* wfe */
3552 case 4: /* sev */
3553 /* TODO: Implement SEV and WFE. May help SMP performance. */
3554 default: /* nop */
3555 break;
3556 }
3557}
99c475ab 3558
ad69471c 3559#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3560
62698be3 3561static inline void gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3562{
3563 switch (size) {
dd8fbd78
FN		 3564 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3565 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3566 case 2: tcg_gen_add_i32(t0, t0, t1); break;
62698be3 3567 default: abort();
9ee6e8bb 3568 }
9ee6e8bb
PB		 3569}
3570
dd8fbd78 3571static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3572{
3573 switch (size) {
dd8fbd78
FN		 3574 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3575 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3576 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3577 default: return;
3578 }
3579}
3580
3581/* 32-bit pairwise ops end up the same as the elementwise versions. */
3582#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3583#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3584#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3585#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3586
ad69471c
PB		 3587#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3588 switch ((size << 1) | u) { \
3589 case 0: \
dd8fbd78 3590 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3591 break; \
3592 case 1: \
dd8fbd78 3593 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3594 break; \
3595 case 2: \
dd8fbd78 3596 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3597 break; \
3598 case 3: \
dd8fbd78 3599 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3600 break; \
3601 case 4: \
dd8fbd78 3602 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3603 break; \
3604 case 5: \
dd8fbd78 3605 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3606 break; \
3607 default: return 1; \
3608 }} while (0)
9ee6e8bb
PB		 3609
3610#define GEN_NEON_INTEGER_OP(name) do { \
3611 switch ((size << 1) | u) { \
ad69471c 3612 case 0: \
dd8fbd78 3613 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3614 break; \
3615 case 1: \
dd8fbd78 3616 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3617 break; \
3618 case 2: \
dd8fbd78 3619 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3620 break; \
3621 case 3: \
dd8fbd78 3622 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3623 break; \
3624 case 4: \
dd8fbd78 3625 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3626 break; \
3627 case 5: \
dd8fbd78 3628 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3629 break; \
9ee6e8bb
PB		 3630 default: return 1; \
3631 }} while (0)
3632
dd8fbd78 3633static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3634{
7d1b0095 3635 TCGv tmp = tcg_temp_new_i32();
dd8fbd78
FN		 3636 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3637 return tmp;
9ee6e8bb
PB		 3638}
3639
dd8fbd78 3640static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3641{
dd8fbd78 3642 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
7d1b0095 3643 tcg_temp_free_i32(var);
9ee6e8bb
PB		 3644}
3645
dd8fbd78 3646static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3647{
dd8fbd78 3648 TCGv tmp;
9ee6e8bb 3649 if (size == 1) {
0fad6efc
PM		 3650 tmp = neon_load_reg(reg & 7, reg >> 4);
3651 if (reg & 8) {
dd8fbd78 3652 gen_neon_dup_high16(tmp);
0fad6efc
PM		 3653 } else {
3654 gen_neon_dup_low16(tmp);
dd8fbd78 3655 }
0fad6efc
PM		 3656 } else {
3657 tmp = neon_load_reg(reg & 15, reg >> 4);
9ee6e8bb 3658 }
dd8fbd78 3659 return tmp;
9ee6e8bb
PB		 3660}
3661
02acedf9 3662static int gen_neon_unzip(int rd, int rm, int size, int q)
19457615 3663{
02acedf9
PM		 3664 TCGv tmp, tmp2;
3665 if (size == 3 || (!q && size == 2)) {
3666 return 1;
3667 }
3668 tmp = tcg_const_i32(rd);
3669 tmp2 = tcg_const_i32(rm);
3670 if (q) {
3671 switch (size) {
3672 case 0:
2a3f75b4 3673 gen_helper_neon_qunzip8(tmp, tmp2);
02acedf9
PM		 3674 break;
3675 case 1:
2a3f75b4 3676 gen_helper_neon_qunzip16(tmp, tmp2);
02acedf9
PM		 3677 break;
3678 case 2:
2a3f75b4 3679 gen_helper_neon_qunzip32(tmp, tmp2);
02acedf9
PM		 3680 break;
3681 default:
3682 abort();
3683 }
3684 } else {
3685 switch (size) {
3686 case 0:
2a3f75b4 3687 gen_helper_neon_unzip8(tmp, tmp2);
02acedf9
PM		 3688 break;
3689 case 1:
2a3f75b4 3690 gen_helper_neon_unzip16(tmp, tmp2);
02acedf9
PM		 3691 break;
3692 default:
3693 abort();
3694 }
3695 }
3696 tcg_temp_free_i32(tmp);
3697 tcg_temp_free_i32(tmp2);
3698 return 0;
19457615
FN		 3699}
3700
d68a6f3a 3701static int gen_neon_zip(int rd, int rm, int size, int q)
19457615
FN		 3702{
3703 TCGv tmp, tmp2;
d68a6f3a
PM		 3704 if (size == 3 || (!q && size == 2)) {
3705 return 1;
3706 }
3707 tmp = tcg_const_i32(rd);
3708 tmp2 = tcg_const_i32(rm);
3709 if (q) {
3710 switch (size) {
3711 case 0:
2a3f75b4 3712 gen_helper_neon_qzip8(tmp, tmp2);
d68a6f3a
PM		 3713 break;
3714 case 1:
2a3f75b4 3715 gen_helper_neon_qzip16(tmp, tmp2);
d68a6f3a
PM		 3716 break;
3717 case 2:
2a3f75b4 3718 gen_helper_neon_qzip32(tmp, tmp2);
d68a6f3a
PM		 3719 break;
3720 default:
3721 abort();
3722 }
3723 } else {
3724 switch (size) {
3725 case 0:
2a3f75b4 3726 gen_helper_neon_zip8(tmp, tmp2);
d68a6f3a
PM		 3727 break;
3728 case 1:
2a3f75b4 3729 gen_helper_neon_zip16(tmp, tmp2);
d68a6f3a
PM		 3730 break;
3731 default:
3732 abort();
3733 }
3734 }
3735 tcg_temp_free_i32(tmp);
3736 tcg_temp_free_i32(tmp2);
3737 return 0;
19457615
FN		 3738}
3739
19457615
FN		 3740static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3741{
3742 TCGv rd, tmp;
3743
7d1b0095
PM		 3744 rd = tcg_temp_new_i32();
3745 tmp = tcg_temp_new_i32();
19457615
FN		 3746
3747 tcg_gen_shli_i32(rd, t0, 8);
3748 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3749 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3750 tcg_gen_or_i32(rd, rd, tmp);
3751
3752 tcg_gen_shri_i32(t1, t1, 8);
3753 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3754 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3755 tcg_gen_or_i32(t1, t1, tmp);
3756 tcg_gen_mov_i32(t0, rd);
3757
7d1b0095
PM		 3758 tcg_temp_free_i32(tmp);
3759 tcg_temp_free_i32(rd);
19457615
FN		 3760}
3761
3762static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3763{
3764 TCGv rd, tmp;
3765
7d1b0095
PM		 3766 rd = tcg_temp_new_i32();
3767 tmp = tcg_temp_new_i32();
19457615
FN		 3768
3769 tcg_gen_shli_i32(rd, t0, 16);
3770 tcg_gen_andi_i32(tmp, t1, 0xffff);
3771 tcg_gen_or_i32(rd, rd, tmp);
3772 tcg_gen_shri_i32(t1, t1, 16);
3773 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3774 tcg_gen_or_i32(t1, t1, tmp);
3775 tcg_gen_mov_i32(t0, rd);
3776
7d1b0095
PM		 3777 tcg_temp_free_i32(tmp);
3778 tcg_temp_free_i32(rd);
19457615
FN		 3779}
3780
3781
9ee6e8bb
PB		 3782static struct {
3783 int nregs;
3784 int interleave;
3785 int spacing;
3786} neon_ls_element_type[11] = {
3787 {4, 4, 1},
3788 {4, 4, 2},
3789 {4, 1, 1},
3790 {4, 2, 1},
3791 {3, 3, 1},
3792 {3, 3, 2},
3793 {3, 1, 1},
3794 {1, 1, 1},
3795 {2, 2, 1},
3796 {2, 2, 2},
3797 {2, 1, 1}
3798};
3799
3800/* Translate a NEON load/store element instruction. Return nonzero if the
3801 instruction is invalid. */
3802static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3803{
3804 int rd, rn, rm;
3805 int op;
3806 int nregs;
3807 int interleave;
84496233 3808 int spacing;
9ee6e8bb
PB		 3809 int stride;
3810 int size;
3811 int reg;
3812 int pass;
3813 int load;
3814 int shift;
9ee6e8bb 3815 int n;
1b2b1e54 3816 TCGv addr;
b0109805 3817 TCGv tmp;
8f8e3aa4 3818 TCGv tmp2;
84496233 3819 TCGv_i64 tmp64;
9ee6e8bb 3820
5df8bac1 3821 if (!s->vfp_enabled)
9ee6e8bb
PB		 3822 return 1;
3823 VFP_DREG_D(rd, insn);
3824 rn = (insn >> 16) & 0xf;
3825 rm = insn & 0xf;
3826 load = (insn & (1 << 21)) != 0;
3827 if ((insn & (1 << 23)) == 0) {
3828 /* Load store all elements. */
3829 op = (insn >> 8) & 0xf;
3830 size = (insn >> 6) & 3;
84496233 3831 if (op > 10)
9ee6e8bb
PB		 3832 return 1;
3833 nregs = neon_ls_element_type[op].nregs;
3834 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3835 spacing = neon_ls_element_type[op].spacing;
3836 if (size == 3 && (interleave | spacing) != 1)
3837 return 1;
e318a60b 3838 addr = tcg_temp_new_i32();
dcc65026 3839 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3840 stride = (1 << size) * interleave;
3841 for (reg = 0; reg < nregs; reg++) {
3842 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3843 load_reg_var(s, addr, rn);
3844 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3845 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3846 load_reg_var(s, addr, rn);
3847 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3848 }
84496233
JR		 3849 if (size == 3) {
3850 if (load) {
3851 tmp64 = gen_ld64(addr, IS_USER(s));
3852 neon_store_reg64(tmp64, rd);
3853 tcg_temp_free_i64(tmp64);
3854 } else {
3855 tmp64 = tcg_temp_new_i64();
3856 neon_load_reg64(tmp64, rd);
3857 gen_st64(tmp64, addr, IS_USER(s));
3858 }
3859 tcg_gen_addi_i32(addr, addr, stride);
3860 } else {
3861 for (pass = 0; pass < 2; pass++) {
3862 if (size == 2) {
3863 if (load) {
3864 tmp = gen_ld32(addr, IS_USER(s));
3865 neon_store_reg(rd, pass, tmp);
3866 } else {
3867 tmp = neon_load_reg(rd, pass);
3868 gen_st32(tmp, addr, IS_USER(s));
3869 }
1b2b1e54 3870 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3871 } else if (size == 1) {
3872 if (load) {
3873 tmp = gen_ld16u(addr, IS_USER(s));
3874 tcg_gen_addi_i32(addr, addr, stride);
3875 tmp2 = gen_ld16u(addr, IS_USER(s));
3876 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3877 tcg_gen_shli_i32(tmp2, tmp2, 16);
3878 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 3879 tcg_temp_free_i32(tmp2);
84496233
JR		 3880 neon_store_reg(rd, pass, tmp);
3881 } else {
3882 tmp = neon_load_reg(rd, pass);
7d1b0095 3883 tmp2 = tcg_temp_new_i32();
84496233
JR		 3884 tcg_gen_shri_i32(tmp2, tmp, 16);
3885 gen_st16(tmp, addr, IS_USER(s));
3886 tcg_gen_addi_i32(addr, addr, stride);
3887 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3888 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3889 }
84496233
JR		 3890 } else /* size == 0 */ {
3891 if (load) {
3892 TCGV_UNUSED(tmp2);
3893 for (n = 0; n < 4; n++) {
3894 tmp = gen_ld8u(addr, IS_USER(s));
3895 tcg_gen_addi_i32(addr, addr, stride);
3896 if (n == 0) {
3897 tmp2 = tmp;
3898 } else {
41ba8341
PB		 3899 tcg_gen_shli_i32(tmp, tmp, n * 8);
3900 tcg_gen_or_i32(tmp2, tmp2, tmp);
7d1b0095 3901 tcg_temp_free_i32(tmp);
84496233 3902 }
9ee6e8bb 3903 }
84496233
JR		 3904 neon_store_reg(rd, pass, tmp2);
3905 } else {
3906 tmp2 = neon_load_reg(rd, pass);
3907 for (n = 0; n < 4; n++) {
7d1b0095 3908 tmp = tcg_temp_new_i32();
84496233
JR		 3909 if (n == 0) {
3910 tcg_gen_mov_i32(tmp, tmp2);
3911 } else {
3912 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3913 }
3914 gen_st8(tmp, addr, IS_USER(s));
3915 tcg_gen_addi_i32(addr, addr, stride);
3916 }
7d1b0095 3917 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 3918 }
3919 }
3920 }
3921 }
84496233 3922 rd += spacing;
9ee6e8bb 3923 }
e318a60b 3924 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 3925 stride = nregs * 8;
3926 } else {
3927 size = (insn >> 10) & 3;
3928 if (size == 3) {
3929 /* Load single element to all lanes. */
8e18cde3
PM		 3930 int a = (insn >> 4) & 1;
3931 if (!load) {
9ee6e8bb 3932 return 1;
8e18cde3 3933 }
9ee6e8bb
PB		 3934 size = (insn >> 6) & 3;
3935 nregs = ((insn >> 8) & 3) + 1;
8e18cde3
PM		 3936
3937 if (size == 3) {
3938 if (nregs != 4 || a == 0) {
9ee6e8bb 3939 return 1;
99c475ab 3940 }
8e18cde3
PM		 3941 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3942 size = 2;
3943 }
3944 if (nregs == 1 && a == 1 && size == 0) {
3945 return 1;
3946 }
3947 if (nregs == 3 && a == 1) {
3948 return 1;
3949 }
e318a60b 3950 addr = tcg_temp_new_i32();
8e18cde3
PM		 3951 load_reg_var(s, addr, rn);
3952 if (nregs == 1) {
3953 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
3954 tmp = gen_load_and_replicate(s, addr, size);
3955 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3956 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3957 if (insn & (1 << 5)) {
3958 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
3959 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
3960 }
3961 tcg_temp_free_i32(tmp);
3962 } else {
3963 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
3964 stride = (insn & (1 << 5)) ? 2 : 1;
3965 for (reg = 0; reg < nregs; reg++) {
3966 tmp = gen_load_and_replicate(s, addr, size);
3967 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3968 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3969 tcg_temp_free_i32(tmp);
3970 tcg_gen_addi_i32(addr, addr, 1 << size);
3971 rd += stride;
3972 }
9ee6e8bb 3973 }
e318a60b 3974 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 3975 stride = (1 << size) * nregs;
3976 } else {
3977 /* Single element. */
3978 pass = (insn >> 7) & 1;
3979 switch (size) {
3980 case 0:
3981 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3982 stride = 1;
3983 break;
3984 case 1:
3985 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3986 stride = (insn & (1 << 5)) ? 2 : 1;
3987 break;
3988 case 2:
3989 shift = 0;
9ee6e8bb
PB		 3990 stride = (insn & (1 << 6)) ? 2 : 1;
3991 break;
3992 default:
3993 abort();
3994 }
3995 nregs = ((insn >> 8) & 3) + 1;
e318a60b 3996 addr = tcg_temp_new_i32();
dcc65026 3997 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3998 for (reg = 0; reg < nregs; reg++) {
3999 if (load) {
9ee6e8bb
PB		 4000 switch (size) {
4001 case 0:
1b2b1e54 4002 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 4003 break;
4004 case 1:
1b2b1e54 4005 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 4006 break;
4007 case 2:
1b2b1e54 4008 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 4009 break;
a50f5b91
PB		 4010 default: /* Avoid compiler warnings. */
4011 abort();
9ee6e8bb
PB		 4012 }
4013 if (size != 2) {
8f8e3aa4
PB		 4014 tmp2 = neon_load_reg(rd, pass);
4015 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
7d1b0095 4016 tcg_temp_free_i32(tmp2);
9ee6e8bb 4017 }
8f8e3aa4 4018 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4019 } else { /* Store */
8f8e3aa4
PB		 4020 tmp = neon_load_reg(rd, pass);
4021 if (shift)
4022 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 4023 switch (size) {
4024 case 0:
1b2b1e54 4025 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 4026 break;
4027 case 1:
1b2b1e54 4028 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 4029 break;
4030 case 2:
1b2b1e54 4031 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 4032 break;
99c475ab 4033 }
99c475ab 4034 }
9ee6e8bb 4035 rd += stride;
1b2b1e54 4036 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 4037 }
e318a60b 4038 tcg_temp_free_i32(addr);
9ee6e8bb 4039 stride = nregs * (1 << size);
99c475ab 4040 }
9ee6e8bb
PB		 4041 }
4042 if (rm != 15) {
b26eefb6
PB		 4043 TCGv base;
4044
4045 base = load_reg(s, rn);
9ee6e8bb 4046 if (rm == 13) {
b26eefb6 4047 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4048 } else {
b26eefb6
PB		 4049 TCGv index;
4050 index = load_reg(s, rm);
4051 tcg_gen_add_i32(base, base, index);
7d1b0095 4052 tcg_temp_free_i32(index);
9ee6e8bb 4053 }
b26eefb6 4054 store_reg(s, rn, base);
9ee6e8bb
PB		 4055 }
4056 return 0;
4057}
3b46e624 4058
8f8e3aa4
PB		 4059/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4060static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4061{
4062 tcg_gen_and_i32(t, t, c);
f669df27 4063 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4064 tcg_gen_or_i32(dest, t, f);
4065}
4066
a7812ae4 4067static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4068{
4069 switch (size) {
4070 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4071 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4072 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4073 default: abort();
4074 }
4075}
4076
a7812ae4 4077static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4078{
4079 switch (size) {
2a3f75b4
PM		 4080 case 0: gen_helper_neon_narrow_sat_s8(dest, src); break;
4081 case 1: gen_helper_neon_narrow_sat_s16(dest, src); break;
4082 case 2: gen_helper_neon_narrow_sat_s32(dest, src); break;
ad69471c
PB		 4083 default: abort();
4084 }
4085}
4086
a7812ae4 4087static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4088{
4089 switch (size) {
2a3f75b4
PM		 4090 case 0: gen_helper_neon_narrow_sat_u8(dest, src); break;
4091 case 1: gen_helper_neon_narrow_sat_u16(dest, src); break;
4092 case 2: gen_helper_neon_narrow_sat_u32(dest, src); break;
ad69471c
PB		 4093 default: abort();
4094 }
4095}
4096
af1bbf30
JR		 4097static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4098{
4099 switch (size) {
2a3f75b4
PM		 4100 case 0: gen_helper_neon_unarrow_sat8(dest, src); break;
4101 case 1: gen_helper_neon_unarrow_sat16(dest, src); break;
4102 case 2: gen_helper_neon_unarrow_sat32(dest, src); break;
af1bbf30
JR		 4103 default: abort();
4104 }
4105}
4106
ad69471c
PB		 4107static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4108 int q, int u)
4109{
4110 if (q) {
4111 if (u) {
4112 switch (size) {
4113 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4114 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4115 default: abort();
4116 }
4117 } else {
4118 switch (size) {
4119 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4120 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4121 default: abort();
4122 }
4123 }
4124 } else {
4125 if (u) {
4126 switch (size) {
b408a9b0
CL		 4127 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4128 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
ad69471c
PB		 4129 default: abort();
4130 }
4131 } else {
4132 switch (size) {
4133 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4134 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4135 default: abort();
4136 }
4137 }
4138 }
4139}
4140
a7812ae4 4141static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4142{
4143 if (u) {
4144 switch (size) {
4145 case 0: gen_helper_neon_widen_u8(dest, src); break;
4146 case 1: gen_helper_neon_widen_u16(dest, src); break;
4147 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4148 default: abort();
4149 }
4150 } else {
4151 switch (size) {
4152 case 0: gen_helper_neon_widen_s8(dest, src); break;
4153 case 1: gen_helper_neon_widen_s16(dest, src); break;
4154 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4155 default: abort();
4156 }
4157 }
7d1b0095 4158 tcg_temp_free_i32(src);
ad69471c
PB		 4159}
4160
4161static inline void gen_neon_addl(int size)
4162{
4163 switch (size) {
4164 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4165 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4166 case 2: tcg_gen_add_i64(CPU_V001); break;
4167 default: abort();
4168 }
4169}
4170
4171static inline void gen_neon_subl(int size)
4172{
4173 switch (size) {
4174 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4175 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4176 case 2: tcg_gen_sub_i64(CPU_V001); break;
4177 default: abort();
4178 }
4179}
4180
a7812ae4 4181static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4182{
4183 switch (size) {
4184 case 0: gen_helper_neon_negl_u16(var, var); break;
4185 case 1: gen_helper_neon_negl_u32(var, var); break;
4186 case 2: gen_helper_neon_negl_u64(var, var); break;
4187 default: abort();
4188 }
4189}
4190
a7812ae4 4191static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4192{
4193 switch (size) {
2a3f75b4
PM		 4194 case 1: gen_helper_neon_addl_saturate_s32(op0, op0, op1); break;
4195 case 2: gen_helper_neon_addl_saturate_s64(op0, op0, op1); break;
ad69471c
PB		 4196 default: abort();
4197 }
4198}
4199
a7812ae4 4200static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4201{
a7812ae4 4202 TCGv_i64 tmp;
ad69471c
PB		 4203
4204 switch ((size << 1) | u) {
4205 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4206 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4207 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4208 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4209 case 4:
4210 tmp = gen_muls_i64_i32(a, b);
4211 tcg_gen_mov_i64(dest, tmp);
7d2aabe2 4212 tcg_temp_free_i64(tmp);
ad69471c
PB		 4213 break;
4214 case 5:
4215 tmp = gen_mulu_i64_i32(a, b);
4216 tcg_gen_mov_i64(dest, tmp);
7d2aabe2 4217 tcg_temp_free_i64(tmp);
ad69471c
PB		 4218 break;
4219 default: abort();
4220 }
c6067f04
CL		 4221
4222 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4223 Don't forget to clean them now. */
4224 if (size < 2) {
7d1b0095
PM		 4225 tcg_temp_free_i32(a);
4226 tcg_temp_free_i32(b);
c6067f04 4227 }
ad69471c
PB		 4228}
4229
c33171c7
PM		 4230static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
4231{
4232 if (op) {
4233 if (u) {
4234 gen_neon_unarrow_sats(size, dest, src);
4235 } else {
4236 gen_neon_narrow(size, dest, src);
4237 }
4238 } else {
4239 if (u) {
4240 gen_neon_narrow_satu(size, dest, src);
4241 } else {
4242 gen_neon_narrow_sats(size, dest, src);
4243 }
4244 }
4245}
4246
62698be3
PM		 4247/* Symbolic constants for op fields for Neon 3-register same-length.
4248 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4249 * table A7-9.
4250 */
4251#define NEON_3R_VHADD 0
4252#define NEON_3R_VQADD 1
4253#define NEON_3R_VRHADD 2
4254#define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4255#define NEON_3R_VHSUB 4
4256#define NEON_3R_VQSUB 5
4257#define NEON_3R_VCGT 6
4258#define NEON_3R_VCGE 7
4259#define NEON_3R_VSHL 8
4260#define NEON_3R_VQSHL 9
4261#define NEON_3R_VRSHL 10
4262#define NEON_3R_VQRSHL 11
4263#define NEON_3R_VMAX 12
4264#define NEON_3R_VMIN 13
4265#define NEON_3R_VABD 14
4266#define NEON_3R_VABA 15
4267#define NEON_3R_VADD_VSUB 16
4268#define NEON_3R_VTST_VCEQ 17
4269#define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4270#define NEON_3R_VMUL 19
4271#define NEON_3R_VPMAX 20
4272#define NEON_3R_VPMIN 21
4273#define NEON_3R_VQDMULH_VQRDMULH 22
4274#define NEON_3R_VPADD 23
4275#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4276#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4277#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4278#define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4279#define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4280#define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
4281
4282static const uint8_t neon_3r_sizes[] = {
4283 [NEON_3R_VHADD] = 0x7,
4284 [NEON_3R_VQADD] = 0xf,
4285 [NEON_3R_VRHADD] = 0x7,
4286 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4287 [NEON_3R_VHSUB] = 0x7,
4288 [NEON_3R_VQSUB] = 0xf,
4289 [NEON_3R_VCGT] = 0x7,
4290 [NEON_3R_VCGE] = 0x7,
4291 [NEON_3R_VSHL] = 0xf,
4292 [NEON_3R_VQSHL] = 0xf,
4293 [NEON_3R_VRSHL] = 0xf,
4294 [NEON_3R_VQRSHL] = 0xf,
4295 [NEON_3R_VMAX] = 0x7,
4296 [NEON_3R_VMIN] = 0x7,
4297 [NEON_3R_VABD] = 0x7,
4298 [NEON_3R_VABA] = 0x7,
4299 [NEON_3R_VADD_VSUB] = 0xf,
4300 [NEON_3R_VTST_VCEQ] = 0x7,
4301 [NEON_3R_VML] = 0x7,
4302 [NEON_3R_VMUL] = 0x7,
4303 [NEON_3R_VPMAX] = 0x7,
4304 [NEON_3R_VPMIN] = 0x7,
4305 [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
4306 [NEON_3R_VPADD] = 0x7,
4307 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
4308 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
4309 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
4310 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
4311 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
4312 [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
4313};
4314
9ee6e8bb
PB		 4315/* Translate a NEON data processing instruction. Return nonzero if the
4316 instruction is invalid.
ad69471c
PB		 4317 We process data in a mixture of 32-bit and 64-bit chunks.
4318 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4319
9ee6e8bb
PB		 4320static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4321{
4322 int op;
4323 int q;
4324 int rd, rn, rm;
4325 int size;
4326 int shift;
4327 int pass;
4328 int count;
4329 int pairwise;
4330 int u;
ca9a32e4 4331 uint32_t imm, mask;
b75263d6 4332 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4333 TCGv_i64 tmp64;
9ee6e8bb 4334
5df8bac1 4335 if (!s->vfp_enabled)
9ee6e8bb
PB		 4336 return 1;
4337 q = (insn & (1 << 6)) != 0;
4338 u = (insn >> 24) & 1;
4339 VFP_DREG_D(rd, insn);
4340 VFP_DREG_N(rn, insn);
4341 VFP_DREG_M(rm, insn);
4342 size = (insn >> 20) & 3;
4343 if ((insn & (1 << 23)) == 0) {
4344 /* Three register same length. */
4345 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
62698be3
PM		 4346 /* Catch invalid op and bad size combinations: UNDEF */
4347 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
4348 return 1;
4349 }
25f84f79
PM		 4350 /* All insns of this form UNDEF for either this condition or the
4351 * superset of cases "Q==1"; we catch the latter later.
4352 */
4353 if (q && ((rd | rn | rm) & 1)) {
4354 return 1;
4355 }
62698be3
PM		 4356 if (size == 3 && op != NEON_3R_LOGIC) {
4357 /* 64-bit element instructions. */
9ee6e8bb 4358 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4359 neon_load_reg64(cpu_V0, rn + pass);
4360 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb 4361 switch (op) {
62698be3 4362 case NEON_3R_VQADD:
9ee6e8bb 4363 if (u) {
2a3f75b4 4364 gen_helper_neon_qadd_u64(cpu_V0, cpu_V0, cpu_V1);
2c0262af 4365 } else {
2a3f75b4 4366 gen_helper_neon_qadd_s64(cpu_V0, cpu_V0, cpu_V1);
2c0262af 4367 }
9ee6e8bb 4368 break;
62698be3 4369 case NEON_3R_VQSUB:
9ee6e8bb 4370 if (u) {
2a3f75b4 4371 gen_helper_neon_qsub_u64(cpu_V0, cpu_V0, cpu_V1);
ad69471c 4372 } else {
2a3f75b4 4373 gen_helper_neon_qsub_s64(cpu_V0, cpu_V0, cpu_V1);
ad69471c
PB		 4374 }
4375 break;
62698be3 4376 case NEON_3R_VSHL:
ad69471c
PB		 4377 if (u) {
4378 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4379 } else {
4380 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4381 }
4382 break;
62698be3 4383 case NEON_3R_VQSHL:
ad69471c 4384 if (u) {
2a3f75b4 4385 gen_helper_neon_qshl_u64(cpu_V0, cpu_V1, cpu_V0);
ad69471c 4386 } else {
2a3f75b4 4387 gen_helper_neon_qshl_s64(cpu_V0, cpu_V1, cpu_V0);
ad69471c
PB		 4388 }
4389 break;
62698be3 4390 case NEON_3R_VRSHL:
ad69471c
PB		 4391 if (u) {
4392 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4393 } else {
ad69471c
PB		 4394 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4395 }
4396 break;
62698be3 4397 case NEON_3R_VQRSHL:
ad69471c 4398 if (u) {
2a3f75b4 4399 gen_helper_neon_qrshl_u64(cpu_V0, cpu_V1, cpu_V0);
ad69471c 4400 } else {
2a3f75b4 4401 gen_helper_neon_qrshl_s64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4402 }
9ee6e8bb 4403 break;
62698be3 4404 case NEON_3R_VADD_VSUB:
9ee6e8bb 4405 if (u) {
ad69471c 4406 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4407 } else {
ad69471c 4408 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4409 }
4410 break;
4411 default:
4412 abort();
2c0262af 4413 }
ad69471c 4414 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4415 }
9ee6e8bb 4416 return 0;
2c0262af 4417 }
25f84f79 4418 pairwise = 0;
9ee6e8bb 4419 switch (op) {
62698be3
PM		 4420 case NEON_3R_VSHL:
4421 case NEON_3R_VQSHL:
4422 case NEON_3R_VRSHL:
4423 case NEON_3R_VQRSHL:
9ee6e8bb 4424 {
ad69471c
PB		 4425 int rtmp;
4426 /* Shift instruction operands are reversed. */
4427 rtmp = rn;
9ee6e8bb 4428 rn = rm;
ad69471c 4429 rm = rtmp;
9ee6e8bb 4430 }
2c0262af 4431 break;
25f84f79
PM		 4432 case NEON_3R_VPADD:
4433 if (u) {
4434 return 1;
4435 }
4436 /* Fall through */
62698be3
PM		 4437 case NEON_3R_VPMAX:
4438 case NEON_3R_VPMIN:
9ee6e8bb 4439 pairwise = 1;
2c0262af 4440 break;
25f84f79
PM		 4441 case NEON_3R_FLOAT_ARITH:
4442 pairwise = (u && size < 2); /* if VPADD (float) */
4443 break;
4444 case NEON_3R_FLOAT_MINMAX:
4445 pairwise = u; /* if VPMIN/VPMAX (float) */
4446 break;
4447 case NEON_3R_FLOAT_CMP:
4448 if (!u && size) {
4449 /* no encoding for U=0 C=1x */
4450 return 1;
4451 }
4452 break;
4453 case NEON_3R_FLOAT_ACMP:
4454 if (!u) {
4455 return 1;
4456 }
4457 break;
4458 case NEON_3R_VRECPS_VRSQRTS:
4459 if (u) {
4460 return 1;
4461 }
2c0262af 4462 break;
25f84f79
PM		 4463 case NEON_3R_VMUL:
4464 if (u && (size != 0)) {
4465 /* UNDEF on invalid size for polynomial subcase */
4466 return 1;
4467 }
2c0262af 4468 break;
9ee6e8bb 4469 default:
2c0262af 4470 break;
9ee6e8bb 4471 }
dd8fbd78 4472
25f84f79
PM		 4473 if (pairwise && q) {
4474 /* All the pairwise insns UNDEF if Q is set */
4475 return 1;
4476 }
4477
9ee6e8bb
PB		 4478 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4479
4480 if (pairwise) {
4481 /* Pairwise. */
a5a14945
JR		 4482 if (pass < 1) {
4483 tmp = neon_load_reg(rn, 0);
4484 tmp2 = neon_load_reg(rn, 1);
9ee6e8bb 4485 } else {
a5a14945
JR		 4486 tmp = neon_load_reg(rm, 0);
4487 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb
PB		 4488 }
4489 } else {
4490 /* Elementwise. */
dd8fbd78
FN		 4491 tmp = neon_load_reg(rn, pass);
4492 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4493 }
4494 switch (op) {
62698be3 4495 case NEON_3R_VHADD:
9ee6e8bb
PB		 4496 GEN_NEON_INTEGER_OP(hadd);
4497 break;
62698be3 4498 case NEON_3R_VQADD:
2a3f75b4 4499 GEN_NEON_INTEGER_OP(qadd);
2c0262af 4500 break;
62698be3 4501 case NEON_3R_VRHADD:
9ee6e8bb 4502 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4503 break;
62698be3 4504 case NEON_3R_LOGIC: /* Logic ops. */
9ee6e8bb
PB		 4505 switch ((u << 2) | size) {
4506 case 0: /* VAND */
dd8fbd78 4507 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4508 break;
4509 case 1: /* BIC */
f669df27 4510 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4511 break;
4512 case 2: /* VORR */
dd8fbd78 4513 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4514 break;
4515 case 3: /* VORN */
f669df27 4516 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4517 break;
4518 case 4: /* VEOR */
dd8fbd78 4519 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4520 break;
4521 case 5: /* VBSL */
dd8fbd78
FN		 4522 tmp3 = neon_load_reg(rd, pass);
4523 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
7d1b0095 4524 tcg_temp_free_i32(tmp3);
9ee6e8bb
PB		 4525 break;
4526 case 6: /* VBIT */
dd8fbd78
FN		 4527 tmp3 = neon_load_reg(rd, pass);
4528 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
7d1b0095 4529 tcg_temp_free_i32(tmp3);
9ee6e8bb
PB		 4530 break;
4531 case 7: /* VBIF */
dd8fbd78
FN		 4532 tmp3 = neon_load_reg(rd, pass);
4533 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
7d1b0095 4534 tcg_temp_free_i32(tmp3);
9ee6e8bb 4535 break;
2c0262af
FB		 4536 }
4537 break;
62698be3 4538 case NEON_3R_VHSUB:
9ee6e8bb
PB		 4539 GEN_NEON_INTEGER_OP(hsub);
4540 break;
62698be3 4541 case NEON_3R_VQSUB:
2a3f75b4 4542 GEN_NEON_INTEGER_OP(qsub);
2c0262af 4543 break;
62698be3 4544 case NEON_3R_VCGT:
9ee6e8bb
PB		 4545 GEN_NEON_INTEGER_OP(cgt);
4546 break;
62698be3 4547 case NEON_3R_VCGE:
9ee6e8bb
PB		 4548 GEN_NEON_INTEGER_OP(cge);
4549 break;
62698be3 4550 case NEON_3R_VSHL:
ad69471c 4551 GEN_NEON_INTEGER_OP(shl);
2c0262af 4552 break;
62698be3 4553 case NEON_3R_VQSHL:
2a3f75b4 4554 GEN_NEON_INTEGER_OP(qshl);
2c0262af 4555 break;
62698be3 4556 case NEON_3R_VRSHL:
ad69471c 4557 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4558 break;
62698be3 4559 case NEON_3R_VQRSHL:
2a3f75b4 4560 GEN_NEON_INTEGER_OP(qrshl);
9ee6e8bb 4561 break;
62698be3 4562 case NEON_3R_VMAX:
9ee6e8bb
PB		 4563 GEN_NEON_INTEGER_OP(max);
4564 break;
62698be3 4565 case NEON_3R_VMIN:
9ee6e8bb
PB		 4566 GEN_NEON_INTEGER_OP(min);
4567 break;
62698be3 4568 case NEON_3R_VABD:
9ee6e8bb
PB		 4569 GEN_NEON_INTEGER_OP(abd);
4570 break;
62698be3 4571 case NEON_3R_VABA:
9ee6e8bb 4572 GEN_NEON_INTEGER_OP(abd);
7d1b0095 4573 tcg_temp_free_i32(tmp2);
dd8fbd78
FN		 4574 tmp2 = neon_load_reg(rd, pass);
4575 gen_neon_add(size, tmp, tmp2);
9ee6e8bb 4576 break;
62698be3 4577 case NEON_3R_VADD_VSUB:
9ee6e8bb 4578 if (!u) { /* VADD */
62698be3 4579 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4580 } else { /* VSUB */
4581 switch (size) {
dd8fbd78
FN		 4582 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4583 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4584 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
62698be3 4585 default: abort();
9ee6e8bb
PB		 4586 }
4587 }
4588 break;
62698be3 4589 case NEON_3R_VTST_VCEQ:
9ee6e8bb
PB		 4590 if (!u) { /* VTST */
4591 switch (size) {
dd8fbd78
FN		 4592 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4593 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4594 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
62698be3 4595 default: abort();
9ee6e8bb
PB		 4596 }
4597 } else { /* VCEQ */
4598 switch (size) {
dd8fbd78
FN		 4599 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4600 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4601 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
62698be3 4602 default: abort();
9ee6e8bb
PB		 4603 }
4604 }
4605 break;
62698be3 4606 case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
9ee6e8bb 4607 switch (size) {
dd8fbd78
FN		 4608 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4609 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4610 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
62698be3 4611 default: abort();
9ee6e8bb 4612 }
7d1b0095 4613 tcg_temp_free_i32(tmp2);
dd8fbd78 4614 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4615 if (u) { /* VMLS */
dd8fbd78 4616 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4617 } else { /* VMLA */
dd8fbd78 4618 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4619 }
4620 break;
62698be3 4621 case NEON_3R_VMUL:
9ee6e8bb 4622 if (u) { /* polynomial */
dd8fbd78 4623 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4624 } else { /* Integer */
4625 switch (size) {
dd8fbd78
FN		 4626 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4627 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4628 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
62698be3 4629 default: abort();
9ee6e8bb
PB		 4630 }
4631 }
4632 break;
62698be3 4633 case NEON_3R_VPMAX:
9ee6e8bb
PB		 4634 GEN_NEON_INTEGER_OP(pmax);
4635 break;
62698be3 4636 case NEON_3R_VPMIN:
9ee6e8bb
PB		 4637 GEN_NEON_INTEGER_OP(pmin);
4638 break;
62698be3 4639 case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
9ee6e8bb
PB		 4640 if (!u) { /* VQDMULH */
4641 switch (size) {
2a3f75b4
PM		 4642 case 1: gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2); break;
4643 case 2: gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2); break;
62698be3 4644 default: abort();
9ee6e8bb 4645 }
62698be3 4646 } else { /* VQRDMULH */
9ee6e8bb 4647 switch (size) {
2a3f75b4
PM		 4648 case 1: gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2); break;
4649 case 2: gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2); break;
62698be3 4650 default: abort();
9ee6e8bb
PB		 4651 }
4652 }
4653 break;
62698be3 4654 case NEON_3R_VPADD:
9ee6e8bb 4655 switch (size) {
dd8fbd78
FN		 4656 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4657 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4658 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
62698be3 4659 default: abort();
9ee6e8bb
PB		 4660 }
4661 break;
62698be3 4662 case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
9ee6e8bb
PB		 4663 switch ((u << 2) | size) {
4664 case 0: /* VADD */
dd8fbd78 4665 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4666 break;
4667 case 2: /* VSUB */
dd8fbd78 4668 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4669 break;
4670 case 4: /* VPADD */
dd8fbd78 4671 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4672 break;
4673 case 6: /* VABD */
dd8fbd78 4674 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4675 break;
4676 default:
62698be3 4677 abort();
9ee6e8bb
PB		 4678 }
4679 break;
62698be3 4680 case NEON_3R_FLOAT_MULTIPLY:
dd8fbd78 4681 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4682 if (!u) {
7d1b0095 4683 tcg_temp_free_i32(tmp2);
dd8fbd78 4684 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4685 if (size == 0) {
dd8fbd78 4686 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4687 } else {
dd8fbd78 4688 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4689 }
4690 }
4691 break;
62698be3 4692 case NEON_3R_FLOAT_CMP:
9ee6e8bb 4693 if (!u) {
dd8fbd78 4694 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4695 } else {
9ee6e8bb 4696 if (size == 0)
dd8fbd78 4697 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4698 else
dd8fbd78 4699 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4700 }
2c0262af 4701 break;
62698be3 4702 case NEON_3R_FLOAT_ACMP:
9ee6e8bb 4703 if (size == 0)
dd8fbd78 4704 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4705 else
dd8fbd78 4706 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4707 break;
62698be3 4708 case NEON_3R_FLOAT_MINMAX:
9ee6e8bb 4709 if (size == 0)
dd8fbd78 4710 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4711 else
dd8fbd78 4712 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb 4713 break;
62698be3 4714 case NEON_3R_VRECPS_VRSQRTS:
9ee6e8bb 4715 if (size == 0)
dd8fbd78 4716 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4717 else
dd8fbd78 4718 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4719 break;
9ee6e8bb
PB		 4720 default:
4721 abort();
2c0262af 4722 }
7d1b0095 4723 tcg_temp_free_i32(tmp2);
dd8fbd78 4724
9ee6e8bb
PB		 4725 /* Save the result. For elementwise operations we can put it
4726 straight into the destination register. For pairwise operations
4727 we have to be careful to avoid clobbering the source operands. */
4728 if (pairwise && rd == rm) {
dd8fbd78 4729 neon_store_scratch(pass, tmp);
9ee6e8bb 4730 } else {
dd8fbd78 4731 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4732 }
4733
4734 } /* for pass */
4735 if (pairwise && rd == rm) {
4736 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4737 tmp = neon_load_scratch(pass);
4738 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4739 }
4740 }
ad69471c 4741 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4742 } else if (insn & (1 << 4)) {
4743 if ((insn & 0x00380080) != 0) {
4744 /* Two registers and shift. */
4745 op = (insn >> 8) & 0xf;
4746 if (insn & (1 << 7)) {
cc13115b
PM		 4747 /* 64-bit shift. */
4748 if (op > 7) {
4749 return 1;
4750 }
9ee6e8bb
PB		 4751 size = 3;
4752 } else {
4753 size = 2;
4754 while ((insn & (1 << (size + 19))) == 0)
4755 size--;
4756 }
4757 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4758 /* To avoid excessive dumplication of ops we implement shift
4759 by immediate using the variable shift operations. */
4760 if (op < 8) {
4761 /* Shift by immediate:
4762 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
cc13115b
PM		 4763 if (q && ((rd | rm) & 1)) {
4764 return 1;
4765 }
4766 if (!u && (op == 4 || op == 6)) {
4767 return 1;
4768 }
9ee6e8bb
PB		 4769 /* Right shifts are encoded as N - shift, where N is the
4770 element size in bits. */
4771 if (op <= 4)
4772 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4773 if (size == 3) {
4774 count = q + 1;
4775 } else {
4776 count = q ? 4: 2;
4777 }
4778 switch (size) {
4779 case 0:
4780 imm = (uint8_t) shift;
4781 imm |= imm << 8;
4782 imm |= imm << 16;
4783 break;
4784 case 1:
4785 imm = (uint16_t) shift;
4786 imm |= imm << 16;
4787 break;
4788 case 2:
4789 case 3:
4790 imm = shift;
4791 break;
4792 default:
4793 abort();
4794 }
4795
4796 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4797 if (size == 3) {
4798 neon_load_reg64(cpu_V0, rm + pass);
4799 tcg_gen_movi_i64(cpu_V1, imm);
4800 switch (op) {
4801 case 0: /* VSHR */
4802 case 1: /* VSRA */
4803 if (u)
4804 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4805 else
ad69471c 4806 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4807 break;
ad69471c
PB		 4808 case 2: /* VRSHR */
4809 case 3: /* VRSRA */
4810 if (u)
4811 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4812 else
ad69471c 4813 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4814 break;
ad69471c 4815 case 4: /* VSRI */
ad69471c
PB		 4816 case 5: /* VSHL, VSLI */
4817 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4818 break;
0322b26e 4819 case 6: /* VQSHLU */
cc13115b 4820 gen_helper_neon_qshlu_s64(cpu_V0, cpu_V0, cpu_V1);
ad69471c 4821 break;
0322b26e
PM		 4822 case 7: /* VQSHL */
4823 if (u) {
2a3f75b4 4824 gen_helper_neon_qshl_u64(cpu_V0,
0322b26e
PM		 4825 cpu_V0, cpu_V1);
4826 } else {
2a3f75b4 4827 gen_helper_neon_qshl_s64(cpu_V0,
0322b26e
PM		 4828 cpu_V0, cpu_V1);
4829 }
9ee6e8bb 4830 break;
9ee6e8bb 4831 }
ad69471c
PB		 4832 if (op == 1 || op == 3) {
4833 /* Accumulate. */
5371cb81 4834 neon_load_reg64(cpu_V1, rd + pass);
ad69471c
PB		 4835 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4836 } else if (op == 4 || (op == 5 && u)) {
4837 /* Insert */
923e6509
CL		 4838 neon_load_reg64(cpu_V1, rd + pass);
4839 uint64_t mask;
4840 if (shift < -63 || shift > 63) {
4841 mask = 0;
4842 } else {
4843 if (op == 4) {
4844 mask = 0xffffffffffffffffull >> -shift;
4845 } else {
4846 mask = 0xffffffffffffffffull << shift;
4847 }
4848 }
4849 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4850 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
ad69471c
PB		 4851 }
4852 neon_store_reg64(cpu_V0, rd + pass);
4853 } else { /* size < 3 */
4854 /* Operands in T0 and T1. */
dd8fbd78 4855 tmp = neon_load_reg(rm, pass);
7d1b0095 4856 tmp2 = tcg_temp_new_i32();
dd8fbd78 4857 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4858 switch (op) {
4859 case 0: /* VSHR */
4860 case 1: /* VSRA */
4861 GEN_NEON_INTEGER_OP(shl);
4862 break;
4863 case 2: /* VRSHR */
4864 case 3: /* VRSRA */
4865 GEN_NEON_INTEGER_OP(rshl);
4866 break;
4867 case 4: /* VSRI */
ad69471c
PB		 4868 case 5: /* VSHL, VSLI */
4869 switch (size) {
dd8fbd78
FN		 4870 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4871 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4872 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
cc13115b 4873 default: abort();
ad69471c
PB		 4874 }
4875 break;
0322b26e 4876 case 6: /* VQSHLU */
ad69471c 4877 switch (size) {
0322b26e 4878 case 0:
2a3f75b4 4879 gen_helper_neon_qshlu_s8(tmp, tmp, tmp2);
0322b26e
PM		 4880 break;
4881 case 1:
2a3f75b4 4882 gen_helper_neon_qshlu_s16(tmp, tmp, tmp2);
0322b26e
PM		 4883 break;
4884 case 2:
2a3f75b4 4885 gen_helper_neon_qshlu_s32(tmp, tmp, tmp2);
0322b26e
PM		 4886 break;
4887 default:
cc13115b 4888 abort();
ad69471c
PB		 4889 }
4890 break;
0322b26e 4891 case 7: /* VQSHL */
2a3f75b4 4892 GEN_NEON_INTEGER_OP(qshl);
0322b26e 4893 break;
ad69471c 4894 }
7d1b0095 4895 tcg_temp_free_i32(tmp2);
ad69471c
PB		 4896
4897 if (op == 1 || op == 3) {
4898 /* Accumulate. */
dd8fbd78 4899 tmp2 = neon_load_reg(rd, pass);
5371cb81 4900 gen_neon_add(size, tmp, tmp2);
7d1b0095 4901 tcg_temp_free_i32(tmp2);
ad69471c
PB		 4902 } else if (op == 4 || (op == 5 && u)) {
4903 /* Insert */
4904 switch (size) {
4905 case 0:
4906 if (op == 4)
ca9a32e4 4907 mask = 0xff >> -shift;
ad69471c 4908 else
ca9a32e4
JR		 4909 mask = (uint8_t)(0xff << shift);
4910 mask |= mask << 8;
4911 mask |= mask << 16;
ad69471c
PB		 4912 break;
4913 case 1:
4914 if (op == 4)
ca9a32e4 4915 mask = 0xffff >> -shift;
ad69471c 4916 else
ca9a32e4
JR		 4917 mask = (uint16_t)(0xffff << shift);
4918 mask |= mask << 16;
ad69471c
PB		 4919 break;
4920 case 2:
ca9a32e4
JR		 4921 if (shift < -31 || shift > 31) {
4922 mask = 0;
4923 } else {
4924 if (op == 4)
4925 mask = 0xffffffffu >> -shift;
4926 else
4927 mask = 0xffffffffu << shift;
4928 }
ad69471c
PB		 4929 break;
4930 default:
4931 abort();
4932 }
dd8fbd78 4933 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4934 tcg_gen_andi_i32(tmp, tmp, mask);
4935 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78 4936 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 4937 tcg_temp_free_i32(tmp2);
ad69471c 4938 }
dd8fbd78 4939 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4940 }
4941 } /* for pass */
4942 } else if (op < 10) {
ad69471c 4943 /* Shift by immediate and narrow:
9ee6e8bb 4944 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
0b36f4cd 4945 int input_unsigned = (op == 8) ? !u : u;
cc13115b
PM		 4946 if (rm & 1) {
4947 return 1;
4948 }
9ee6e8bb
PB		 4949 shift = shift - (1 << (size + 3));
4950 size++;
92cdfaeb 4951 if (size == 3) {
a7812ae4 4952 tmp64 = tcg_const_i64(shift);
92cdfaeb
PM		 4953 neon_load_reg64(cpu_V0, rm);
4954 neon_load_reg64(cpu_V1, rm + 1);
4955 for (pass = 0; pass < 2; pass++) {
4956 TCGv_i64 in;
4957 if (pass == 0) {
4958 in = cpu_V0;
4959 } else {
4960 in = cpu_V1;
4961 }
ad69471c 4962 if (q) {
0b36f4cd 4963 if (input_unsigned) {
92cdfaeb 4964 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
0b36f4cd 4965 } else {
92cdfaeb 4966 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
0b36f4cd 4967 }
ad69471c 4968 } else {
0b36f4cd 4969 if (input_unsigned) {
92cdfaeb 4970 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
0b36f4cd 4971 } else {
92cdfaeb 4972 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
0b36f4cd 4973 }
ad69471c 4974 }
7d1b0095 4975 tmp = tcg_temp_new_i32();
92cdfaeb
PM		 4976 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
4977 neon_store_reg(rd, pass, tmp);
4978 } /* for pass */
4979 tcg_temp_free_i64(tmp64);
4980 } else {
4981 if (size == 1) {
4982 imm = (uint16_t)shift;
4983 imm |= imm << 16;
2c0262af 4984 } else {
92cdfaeb
PM		 4985 /* size == 2 */
4986 imm = (uint32_t)shift;
4987 }
4988 tmp2 = tcg_const_i32(imm);
4989 tmp4 = neon_load_reg(rm + 1, 0);
4990 tmp5 = neon_load_reg(rm + 1, 1);
4991 for (pass = 0; pass < 2; pass++) {
4992 if (pass == 0) {
4993 tmp = neon_load_reg(rm, 0);
4994 } else {
4995 tmp = tmp4;
4996 }
0b36f4cd
CL		 4997 gen_neon_shift_narrow(size, tmp, tmp2, q,
4998 input_unsigned);
92cdfaeb
PM		 4999 if (pass == 0) {
5000 tmp3 = neon_load_reg(rm, 1);
5001 } else {
5002 tmp3 = tmp5;
5003 }
0b36f4cd
CL		 5004 gen_neon_shift_narrow(size, tmp3, tmp2, q,
5005 input_unsigned);
36aa55dc 5006 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
7d1b0095
PM		 5007 tcg_temp_free_i32(tmp);
5008 tcg_temp_free_i32(tmp3);
5009 tmp = tcg_temp_new_i32();
92cdfaeb
PM		 5010 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5011 neon_store_reg(rd, pass, tmp);
5012 } /* for pass */
c6067f04 5013 tcg_temp_free_i32(tmp2);
b75263d6 5014 }
9ee6e8bb 5015 } else if (op == 10) {
cc13115b
PM		 5016 /* VSHLL, VMOVL */
5017 if (q || (rd & 1)) {
9ee6e8bb 5018 return 1;
cc13115b 5019 }
ad69471c
PB		 5020 tmp = neon_load_reg(rm, 0);
5021 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5022 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5023 if (pass == 1)
5024 tmp = tmp2;
5025
5026 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 5027
9ee6e8bb
PB		 5028 if (shift != 0) {
5029 /* The shift is less than the width of the source
ad69471c
PB		 5030 type, so we can just shift the whole register. */
5031 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
acdf01ef
CL		 5032 /* Widen the result of shift: we need to clear
5033 * the potential overflow bits resulting from
5034 * left bits of the narrow input appearing as
5035 * right bits of left the neighbour narrow
5036 * input. */
ad69471c
PB		 5037 if (size < 2 || !u) {
5038 uint64_t imm64;
5039 if (size == 0) {
5040 imm = (0xffu >> (8 - shift));
5041 imm |= imm << 16;
acdf01ef 5042 } else if (size == 1) {
ad69471c 5043 imm = 0xffff >> (16 - shift);
acdf01ef
CL		 5044 } else {
5045 /* size == 2 */
5046 imm = 0xffffffff >> (32 - shift);
5047 }
5048 if (size < 2) {
5049 imm64 = imm | (((uint64_t)imm) << 32);
5050 } else {
5051 imm64 = imm;
9ee6e8bb 5052 }
acdf01ef 5053 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
9ee6e8bb
PB		 5054 }
5055 }
ad69471c 5056 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5057 }
f73534a5 5058 } else if (op >= 14) {
9ee6e8bb 5059 /* VCVT fixed-point. */
cc13115b
PM		 5060 if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
5061 return 1;
5062 }
f73534a5
PM		 5063 /* We have already masked out the must-be-1 top bit of imm6,
5064 * hence this 32-shift where the ARM ARM has 64-imm6.
5065 */
5066 shift = 32 - shift;
9ee6e8bb 5067 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 5068 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
f73534a5 5069 if (!(op & 1)) {
9ee6e8bb 5070 if (u)
4373f3ce 5071 gen_vfp_ulto(0, shift);
9ee6e8bb 5072 else
4373f3ce 5073 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 5074 } else {
5075 if (u)
4373f3ce 5076 gen_vfp_toul(0, shift);
9ee6e8bb 5077 else
4373f3ce 5078 gen_vfp_tosl(0, shift);
2c0262af 5079 }
4373f3ce 5080 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 5081 }
5082 } else {
9ee6e8bb
PB		 5083 return 1;
5084 }
5085 } else { /* (insn & 0x00380080) == 0 */
5086 int invert;
7d80fee5
PM		 5087 if (q && (rd & 1)) {
5088 return 1;
5089 }
9ee6e8bb
PB		 5090
5091 op = (insn >> 8) & 0xf;
5092 /* One register and immediate. */
5093 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
5094 invert = (insn & (1 << 5)) != 0;
7d80fee5
PM		 5095 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5096 * We choose to not special-case this and will behave as if a
5097 * valid constant encoding of 0 had been given.
5098 */
9ee6e8bb
PB		 5099 switch (op) {
5100 case 0: case 1:
5101 /* no-op */
5102 break;
5103 case 2: case 3:
5104 imm <<= 8;
5105 break;
5106 case 4: case 5:
5107 imm <<= 16;
5108 break;
5109 case 6: case 7:
5110 imm <<= 24;
5111 break;
5112 case 8: case 9:
5113 imm |= imm << 16;
5114 break;
5115 case 10: case 11:
5116 imm = (imm << 8) | (imm << 24);
5117 break;
5118 case 12:
8e31209e 5119 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 5120 break;
5121 case 13:
5122 imm = (imm << 16) | 0xffff;
5123 break;
5124 case 14:
5125 imm |= (imm << 8) | (imm << 16) | (imm << 24);
5126 if (invert)
5127 imm = ~imm;
5128 break;
5129 case 15:
7d80fee5
PM		 5130 if (invert) {
5131 return 1;
5132 }
9ee6e8bb
PB		 5133 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
5134 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
5135 break;
5136 }
5137 if (invert)
5138 imm = ~imm;
5139
9ee6e8bb
PB		 5140 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5141 if (op & 1 && op < 12) {
ad69471c 5142 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5143 if (invert) {
5144 /* The immediate value has already been inverted, so
5145 BIC becomes AND. */
ad69471c 5146 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 5147 } else {
ad69471c 5148 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 5149 }
9ee6e8bb 5150 } else {
ad69471c 5151 /* VMOV, VMVN. */
7d1b0095 5152 tmp = tcg_temp_new_i32();
9ee6e8bb 5153 if (op == 14 && invert) {
a5a14945 5154 int n;
ad69471c
PB		 5155 uint32_t val;
5156 val = 0;
9ee6e8bb
PB		 5157 for (n = 0; n < 4; n++) {
5158 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 5159 val |= 0xff << (n * 8);
9ee6e8bb 5160 }
ad69471c
PB		 5161 tcg_gen_movi_i32(tmp, val);
5162 } else {
5163 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 5164 }
9ee6e8bb 5165 }
ad69471c 5166 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5167 }
5168 }
e4b3861d 5169 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 5170 if (size != 3) {
5171 op = (insn >> 8) & 0xf;
5172 if ((insn & (1 << 6)) == 0) {
5173 /* Three registers of different lengths. */
5174 int src1_wide;
5175 int src2_wide;
5176 int prewiden;
5177 /* prewiden, src1_wide, src2_wide */
5178 static const int neon_3reg_wide[16][3] = {
5179 {1, 0, 0}, /* VADDL */
5180 {1, 1, 0}, /* VADDW */
5181 {1, 0, 0}, /* VSUBL */
5182 {1, 1, 0}, /* VSUBW */
5183 {0, 1, 1}, /* VADDHN */
5184 {0, 0, 0}, /* VABAL */
5185 {0, 1, 1}, /* VSUBHN */
5186 {0, 0, 0}, /* VABDL */
5187 {0, 0, 0}, /* VMLAL */
5188 {0, 0, 0}, /* VQDMLAL */
5189 {0, 0, 0}, /* VMLSL */
5190 {0, 0, 0}, /* VQDMLSL */
5191 {0, 0, 0}, /* Integer VMULL */
5192 {0, 0, 0}, /* VQDMULL */
5193 {0, 0, 0} /* Polynomial VMULL */
5194 };
5195
5196 prewiden = neon_3reg_wide[op][0];
5197 src1_wide = neon_3reg_wide[op][1];
5198 src2_wide = neon_3reg_wide[op][2];
5199
ad69471c
PB		 5200 if (size == 0 && (op == 9 || op == 11 || op == 13))
5201 return 1;
5202
9ee6e8bb
PB		 5203 /* Avoid overlapping operands. Wide source operands are
5204 always aligned so will never overlap with wide
5205 destinations in problematic ways. */
8f8e3aa4 5206 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 5207 tmp = neon_load_reg(rm, 1);
5208 neon_store_scratch(2, tmp);
8f8e3aa4 5209 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 5210 tmp = neon_load_reg(rn, 1);
5211 neon_store_scratch(2, tmp);
9ee6e8bb 5212 }
a50f5b91 5213 TCGV_UNUSED(tmp3);
9ee6e8bb 5214 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5215 if (src1_wide) {
5216 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 5217 TCGV_UNUSED(tmp);
9ee6e8bb 5218 } else {
ad69471c 5219 if (pass == 1 && rd == rn) {
dd8fbd78 5220 tmp = neon_load_scratch(2);
9ee6e8bb 5221 } else {
ad69471c
PB		 5222 tmp = neon_load_reg(rn, pass);
5223 }
5224 if (prewiden) {
5225 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 5226 }
5227 }
ad69471c
PB		 5228 if (src2_wide) {
5229 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5230 TCGV_UNUSED(tmp2);
9ee6e8bb 5231 } else {
ad69471c 5232 if (pass == 1 && rd == rm) {
dd8fbd78 5233 tmp2 = neon_load_scratch(2);
9ee6e8bb 5234 } else {
ad69471c
PB		 5235 tmp2 = neon_load_reg(rm, pass);
5236 }
5237 if (prewiden) {
5238 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5239 }
9ee6e8bb
PB		 5240 }
5241 switch (op) {
5242 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5243 gen_neon_addl(size);
9ee6e8bb 5244 break;
79b0e534 5245 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5246 gen_neon_subl(size);
9ee6e8bb
PB		 5247 break;
5248 case 5: case 7: /* VABAL, VABDL */
5249 switch ((size << 1) | u) {
ad69471c
PB		 5250 case 0:
5251 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5252 break;
5253 case 1:
5254 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5255 break;
5256 case 2:
5257 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5258 break;
5259 case 3:
5260 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5261 break;
5262 case 4:
5263 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5264 break;
5265 case 5:
5266 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5267 break;
9ee6e8bb
PB		 5268 default: abort();
5269 }
7d1b0095
PM		 5270 tcg_temp_free_i32(tmp2);
5271 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5272 break;
5273 case 8: case 9: case 10: case 11: case 12: case 13:
5274 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5275 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb
PB		 5276 break;
5277 case 14: /* Polynomial VMULL */
e5ca24cb 5278 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
7d1b0095
PM		 5279 tcg_temp_free_i32(tmp2);
5280 tcg_temp_free_i32(tmp);
e5ca24cb 5281 break;
9ee6e8bb
PB		 5282 default: /* 15 is RESERVED. */
5283 return 1;
5284 }
ebcd88ce
PM		 5285 if (op == 13) {
5286 /* VQDMULL */
5287 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5288 neon_store_reg64(cpu_V0, rd + pass);
5289 } else if (op == 5 || (op >= 8 && op <= 11)) {
9ee6e8bb 5290 /* Accumulate. */
ebcd88ce 5291 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5292 switch (op) {
4dc064e6
PM		 5293 case 10: /* VMLSL */
5294 gen_neon_negl(cpu_V0, size);
5295 /* Fall through */
5296 case 5: case 8: /* VABAL, VMLAL */
ad69471c 5297 gen_neon_addl(size);
9ee6e8bb
PB		 5298 break;
5299 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c 5300 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5301 if (op == 11) {
5302 gen_neon_negl(cpu_V0, size);
5303 }
ad69471c
PB		 5304 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5305 break;
9ee6e8bb
PB		 5306 default:
5307 abort();
5308 }
ad69471c 5309 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5310 } else if (op == 4 || op == 6) {
5311 /* Narrowing operation. */
7d1b0095 5312 tmp = tcg_temp_new_i32();
79b0e534 5313 if (!u) {
9ee6e8bb 5314 switch (size) {
ad69471c
PB		 5315 case 0:
5316 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5317 break;
5318 case 1:
5319 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5320 break;
5321 case 2:
5322 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5323 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5324 break;
9ee6e8bb
PB		 5325 default: abort();
5326 }
5327 } else {
5328 switch (size) {
ad69471c
PB		 5329 case 0:
5330 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5331 break;
5332 case 1:
5333 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5334 break;
5335 case 2:
5336 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5337 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5338 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5339 break;
9ee6e8bb
PB		 5340 default: abort();
5341 }
5342 }
ad69471c
PB		 5343 if (pass == 0) {
5344 tmp3 = tmp;
5345 } else {
5346 neon_store_reg(rd, 0, tmp3);
5347 neon_store_reg(rd, 1, tmp);
5348 }
9ee6e8bb
PB		 5349 } else {
5350 /* Write back the result. */
ad69471c 5351 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5352 }
5353 }
5354 } else {
5355 /* Two registers and a scalar. */
5356 switch (op) {
5357 case 0: /* Integer VMLA scalar */
5358 case 1: /* Float VMLA scalar */
5359 case 4: /* Integer VMLS scalar */
5360 case 5: /* Floating point VMLS scalar */
5361 case 8: /* Integer VMUL scalar */
5362 case 9: /* Floating point VMUL scalar */
5363 case 12: /* VQDMULH scalar */
5364 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5365 tmp = neon_get_scalar(size, rm);
5366 neon_store_scratch(0, tmp);
9ee6e8bb 5367 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5368 tmp = neon_load_scratch(0);
5369 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5370 if (op == 12) {
5371 if (size == 1) {
2a3f75b4 5372 gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2);
9ee6e8bb 5373 } else {
2a3f75b4 5374 gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5375 }
5376 } else if (op == 13) {
5377 if (size == 1) {
2a3f75b4 5378 gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2);
9ee6e8bb 5379 } else {
2a3f75b4 5380 gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5381 }
5382 } else if (op & 1) {
dd8fbd78 5383 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5384 } else {
5385 switch (size) {
dd8fbd78
FN		 5386 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5387 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5388 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5389 default: return 1;
5390 }
5391 }
7d1b0095 5392 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 5393 if (op < 8) {
5394 /* Accumulate. */
dd8fbd78 5395 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5396 switch (op) {
5397 case 0:
dd8fbd78 5398 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5399 break;
5400 case 1:
dd8fbd78 5401 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5402 break;
5403 case 4:
dd8fbd78 5404 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5405 break;
5406 case 5:
dd8fbd78 5407 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5408 break;
5409 default:
5410 abort();
5411 }
7d1b0095 5412 tcg_temp_free_i32(tmp2);
9ee6e8bb 5413 }
dd8fbd78 5414 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5415 }
5416 break;
5417 case 2: /* VMLAL sclar */
5418 case 3: /* VQDMLAL scalar */
5419 case 6: /* VMLSL scalar */
5420 case 7: /* VQDMLSL scalar */
5421 case 10: /* VMULL scalar */
5422 case 11: /* VQDMULL scalar */
ad69471c
PB		 5423 if (size == 0 && (op == 3 || op == 7 || op == 11))
5424 return 1;
5425
dd8fbd78 5426 tmp2 = neon_get_scalar(size, rm);
c6067f04
CL		 5427 /* We need a copy of tmp2 because gen_neon_mull
5428 * deletes it during pass 0. */
7d1b0095 5429 tmp4 = tcg_temp_new_i32();
c6067f04 5430 tcg_gen_mov_i32(tmp4, tmp2);
dd8fbd78 5431 tmp3 = neon_load_reg(rn, 1);
ad69471c 5432
9ee6e8bb 5433 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5434 if (pass == 0) {
5435 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5436 } else {
dd8fbd78 5437 tmp = tmp3;
c6067f04 5438 tmp2 = tmp4;
9ee6e8bb 5439 }
ad69471c 5440 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
ad69471c
PB		 5441 if (op != 11) {
5442 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5443 }
9ee6e8bb 5444 switch (op) {
4dc064e6
PM		 5445 case 6:
5446 gen_neon_negl(cpu_V0, size);
5447 /* Fall through */
5448 case 2:
ad69471c 5449 gen_neon_addl(size);
9ee6e8bb
PB		 5450 break;
5451 case 3: case 7:
ad69471c 5452 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5453 if (op == 7) {
5454 gen_neon_negl(cpu_V0, size);
5455 }
ad69471c 5456 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5457 break;
5458 case 10:
5459 /* no-op */
5460 break;
5461 case 11:
ad69471c 5462 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5463 break;
5464 default:
5465 abort();
5466 }
ad69471c 5467 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5468 }
dd8fbd78 5469
dd8fbd78 5470
9ee6e8bb
PB		 5471 break;
5472 default: /* 14 and 15 are RESERVED */
5473 return 1;
5474 }
5475 }
5476 } else { /* size == 3 */
5477 if (!u) {
5478 /* Extract. */
9ee6e8bb 5479 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5480
5481 if (imm > 7 && !q)
5482 return 1;
5483
5484 if (imm == 0) {
5485 neon_load_reg64(cpu_V0, rn);
5486 if (q) {
5487 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5488 }
ad69471c
PB		 5489 } else if (imm == 8) {
5490 neon_load_reg64(cpu_V0, rn + 1);
5491 if (q) {
5492 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5493 }
ad69471c 5494 } else if (q) {
a7812ae4 5495 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5496 if (imm < 8) {
5497 neon_load_reg64(cpu_V0, rn);
a7812ae4 5498 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5499 } else {
5500 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5501 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5502 }
5503 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5504 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5505 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5506 if (imm < 8) {
5507 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5508 } else {
ad69471c
PB		 5509 neon_load_reg64(cpu_V1, rm + 1);
5510 imm -= 8;
9ee6e8bb 5511 }
ad69471c 5512 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5513 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5514 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5515 tcg_temp_free_i64(tmp64);
ad69471c 5516 } else {
a7812ae4 5517 /* BUGFIX */
ad69471c 5518 neon_load_reg64(cpu_V0, rn);
a7812ae4 5519 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5520 neon_load_reg64(cpu_V1, rm);
a7812ae4 5521 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5522 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5523 }
5524 neon_store_reg64(cpu_V0, rd);
5525 if (q) {
5526 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5527 }
5528 } else if ((insn & (1 << 11)) == 0) {
5529 /* Two register misc. */
5530 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5531 size = (insn >> 18) & 3;
5532 switch (op) {
5533 case 0: /* VREV64 */
5534 if (size == 3)
5535 return 1;
5536 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5537 tmp = neon_load_reg(rm, pass * 2);
5538 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5539 switch (size) {
dd8fbd78
FN		 5540 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5541 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5542 case 2: /* no-op */ break;
5543 default: abort();
5544 }
dd8fbd78 5545 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5546 if (size == 2) {
dd8fbd78 5547 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5548 } else {
9ee6e8bb 5549 switch (size) {
dd8fbd78
FN		 5550 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5551 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5552 default: abort();
5553 }
dd8fbd78 5554 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5555 }
5556 }
5557 break;
5558 case 4: case 5: /* VPADDL */
5559 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5560 if (size == 3)
5561 return 1;
ad69471c
PB		 5562 for (pass = 0; pass < q + 1; pass++) {
5563 tmp = neon_load_reg(rm, pass * 2);
5564 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5565 tmp = neon_load_reg(rm, pass * 2 + 1);
5566 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5567 switch (size) {
5568 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5569 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5570 case 2: tcg_gen_add_i64(CPU_V001); break;
5571 default: abort();
5572 }
9ee6e8bb
PB		 5573 if (op >= 12) {
5574 /* Accumulate. */
ad69471c
PB		 5575 neon_load_reg64(cpu_V1, rd + pass);
5576 gen_neon_addl(size);
9ee6e8bb 5577 }
ad69471c 5578 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5579 }
5580 break;
5581 case 33: /* VTRN */
5582 if (size == 2) {
a5a14945 5583 int n;
9ee6e8bb 5584 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5585 tmp = neon_load_reg(rm, n);
5586 tmp2 = neon_load_reg(rd, n + 1);
5587 neon_store_reg(rm, n, tmp2);
5588 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5589 }
5590 } else {
5591 goto elementwise;
5592 }
5593 break;
5594 case 34: /* VUZP */
02acedf9 5595 if (gen_neon_unzip(rd, rm, size, q)) {
9ee6e8bb 5596 return 1;
9ee6e8bb
PB		 5597 }
5598 break;
5599 case 35: /* VZIP */
d68a6f3a 5600 if (gen_neon_zip(rd, rm, size, q)) {
9ee6e8bb 5601 return 1;
9ee6e8bb
PB		 5602 }
5603 break;
5604 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5605 if (size == 3)
5606 return 1;
a50f5b91 5607 TCGV_UNUSED(tmp2);
9ee6e8bb 5608 for (pass = 0; pass < 2; pass++) {
ad69471c 5609 neon_load_reg64(cpu_V0, rm + pass);
7d1b0095 5610 tmp = tcg_temp_new_i32();
c33171c7 5611 gen_neon_narrow_op(op == 36, q, size, tmp, cpu_V0);
ad69471c
PB		 5612 if (pass == 0) {
5613 tmp2 = tmp;
5614 } else {
5615 neon_store_reg(rd, 0, tmp2);
5616 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5617 }
9ee6e8bb
PB		 5618 }
5619 break;
5620 case 38: /* VSHLL */
ad69471c 5621 if (q || size == 3)
9ee6e8bb 5622 return 1;
ad69471c
PB		 5623 tmp = neon_load_reg(rm, 0);
5624 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5625 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5626 if (pass == 1)
5627 tmp = tmp2;
5628 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5629 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5630 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5631 }
5632 break;
60011498
PB		 5633 case 44: /* VCVT.F16.F32 */
5634 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5635 return 1;
7d1b0095
PM		 5636 tmp = tcg_temp_new_i32();
5637 tmp2 = tcg_temp_new_i32();
60011498 5638 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
2d981da7 5639 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498 5640 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
2d981da7 5641 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5642 tcg_gen_shli_i32(tmp2, tmp2, 16);
5643 tcg_gen_or_i32(tmp2, tmp2, tmp);
5644 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
2d981da7 5645 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498
PB		 5646 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5647 neon_store_reg(rd, 0, tmp2);
7d1b0095 5648 tmp2 = tcg_temp_new_i32();
2d981da7 5649 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5650 tcg_gen_shli_i32(tmp2, tmp2, 16);
5651 tcg_gen_or_i32(tmp2, tmp2, tmp);
5652 neon_store_reg(rd, 1, tmp2);
7d1b0095 5653 tcg_temp_free_i32(tmp);
60011498
PB		 5654 break;
5655 case 46: /* VCVT.F32.F16 */
5656 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5657 return 1;
7d1b0095 5658 tmp3 = tcg_temp_new_i32();
60011498
PB		 5659 tmp = neon_load_reg(rm, 0);
5660 tmp2 = neon_load_reg(rm, 1);
5661 tcg_gen_ext16u_i32(tmp3, tmp);
2d981da7 5662 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5663 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5664 tcg_gen_shri_i32(tmp3, tmp, 16);
2d981da7 5665 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498 5666 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
7d1b0095 5667 tcg_temp_free_i32(tmp);
60011498 5668 tcg_gen_ext16u_i32(tmp3, tmp2);
2d981da7 5669 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5670 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5671 tcg_gen_shri_i32(tmp3, tmp2, 16);
2d981da7 5672 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498 5673 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
7d1b0095
PM		 5674 tcg_temp_free_i32(tmp2);
5675 tcg_temp_free_i32(tmp3);
60011498 5676 break;
9ee6e8bb
PB		 5677 default:
5678 elementwise:
5679 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5680 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5681 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5682 neon_reg_offset(rm, pass));
dd8fbd78 5683 TCGV_UNUSED(tmp);
9ee6e8bb 5684 } else {
dd8fbd78 5685 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5686 }
5687 switch (op) {
5688 case 1: /* VREV32 */
5689 switch (size) {
dd8fbd78
FN		 5690 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5691 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5692 default: return 1;
5693 }
5694 break;
5695 case 2: /* VREV16 */
5696 if (size != 0)
5697 return 1;
dd8fbd78 5698 gen_rev16(tmp);
9ee6e8bb 5699 break;
9ee6e8bb
PB		 5700 case 8: /* CLS */
5701 switch (size) {
dd8fbd78
FN		 5702 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5703 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5704 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5705 default: return 1;
5706 }
5707 break;
5708 case 9: /* CLZ */
5709 switch (size) {
dd8fbd78
FN		 5710 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5711 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5712 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5713 default: return 1;
5714 }
5715 break;
5716 case 10: /* CNT */
5717 if (size != 0)
5718 return 1;
dd8fbd78 5719 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5720 break;
5721 case 11: /* VNOT */
5722 if (size != 0)
5723 return 1;
dd8fbd78 5724 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5725 break;
5726 case 14: /* VQABS */
5727 switch (size) {
2a3f75b4
PM		 5728 case 0: gen_helper_neon_qabs_s8(tmp, tmp); break;
5729 case 1: gen_helper_neon_qabs_s16(tmp, tmp); break;
5730 case 2: gen_helper_neon_qabs_s32(tmp, tmp); break;
9ee6e8bb
PB		 5731 default: return 1;
5732 }
5733 break;
5734 case 15: /* VQNEG */
5735 switch (size) {
2a3f75b4
PM		 5736 case 0: gen_helper_neon_qneg_s8(tmp, tmp); break;
5737 case 1: gen_helper_neon_qneg_s16(tmp, tmp); break;
5738 case 2: gen_helper_neon_qneg_s32(tmp, tmp); break;
9ee6e8bb
PB		 5739 default: return 1;
5740 }
5741 break;
5742 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5743 tmp2 = tcg_const_i32(0);
9ee6e8bb 5744 switch(size) {
dd8fbd78
FN		 5745 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5746 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5747 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5748 default: return 1;
5749 }
dd8fbd78 5750 tcg_temp_free(tmp2);
9ee6e8bb 5751 if (op == 19)
dd8fbd78 5752 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5753 break;
5754 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5755 tmp2 = tcg_const_i32(0);
9ee6e8bb 5756 switch(size) {
dd8fbd78
FN		 5757 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5758 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5759 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5760 default: return 1;
5761 }
dd8fbd78 5762 tcg_temp_free(tmp2);
9ee6e8bb 5763 if (op == 20)
dd8fbd78 5764 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5765 break;
5766 case 18: /* VCEQ #0 */
dd8fbd78 5767 tmp2 = tcg_const_i32(0);
9ee6e8bb 5768 switch(size) {
dd8fbd78
FN		 5769 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5770 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5771 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5772 default: return 1;
5773 }
dd8fbd78 5774 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5775 break;
5776 case 22: /* VABS */
5777 switch(size) {
dd8fbd78
FN		 5778 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5779 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5780 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5781 default: return 1;
5782 }
5783 break;
5784 case 23: /* VNEG */
ad69471c
PB		 5785 if (size == 3)
5786 return 1;
dd8fbd78
FN		 5787 tmp2 = tcg_const_i32(0);
5788 gen_neon_rsb(size, tmp, tmp2);
5789 tcg_temp_free(tmp2);
9ee6e8bb 5790 break;
0e326109 5791 case 24: /* Float VCGT #0 */
dd8fbd78
FN		 5792 tmp2 = tcg_const_i32(0);
5793 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5794 tcg_temp_free(tmp2);
9ee6e8bb 5795 break;
0e326109 5796 case 25: /* Float VCGE #0 */
dd8fbd78
FN		 5797 tmp2 = tcg_const_i32(0);
5798 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5799 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5800 break;
5801 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5802 tmp2 = tcg_const_i32(0);
5803 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5804 tcg_temp_free(tmp2);
9ee6e8bb 5805 break;
0e326109
PM		 5806 case 27: /* Float VCLE #0 */
5807 tmp2 = tcg_const_i32(0);
5808 gen_helper_neon_cge_f32(tmp, tmp2, tmp);
5809 tcg_temp_free(tmp2);
5810 break;
5811 case 28: /* Float VCLT #0 */
5812 tmp2 = tcg_const_i32(0);
5813 gen_helper_neon_cgt_f32(tmp, tmp2, tmp);
5814 tcg_temp_free(tmp2);
5815 break;
9ee6e8bb 5816 case 30: /* Float VABS */
4373f3ce 5817 gen_vfp_abs(0);
9ee6e8bb
PB		 5818 break;
5819 case 31: /* Float VNEG */
4373f3ce 5820 gen_vfp_neg(0);
9ee6e8bb
PB		 5821 break;
5822 case 32: /* VSWP */
dd8fbd78
FN		 5823 tmp2 = neon_load_reg(rd, pass);
5824 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5825 break;
5826 case 33: /* VTRN */
dd8fbd78 5827 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5828 switch (size) {
dd8fbd78
FN		 5829 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5830 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5831 case 2: abort();
5832 default: return 1;
5833 }
dd8fbd78 5834 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5835 break;
5836 case 56: /* Integer VRECPE */
dd8fbd78 5837 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5838 break;
5839 case 57: /* Integer VRSQRTE */
dd8fbd78 5840 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5841 break;
5842 case 58: /* Float VRECPE */
4373f3ce 5843 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5844 break;
5845 case 59: /* Float VRSQRTE */
4373f3ce 5846 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5847 break;
5848 case 60: /* VCVT.F32.S32 */
d3587ef8 5849 gen_vfp_sito(0);
9ee6e8bb
PB		 5850 break;
5851 case 61: /* VCVT.F32.U32 */
d3587ef8 5852 gen_vfp_uito(0);
9ee6e8bb
PB		 5853 break;
5854 case 62: /* VCVT.S32.F32 */
d3587ef8 5855 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5856 break;
5857 case 63: /* VCVT.U32.F32 */
d3587ef8 5858 gen_vfp_touiz(0);
9ee6e8bb
PB		 5859 break;
5860 default:
5861 /* Reserved: 21, 29, 39-56 */
5862 return 1;
5863 }
5864 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5865 tcg_gen_st_f32(cpu_F0s, cpu_env,
5866 neon_reg_offset(rd, pass));
9ee6e8bb 5867 } else {
dd8fbd78 5868 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5869 }
5870 }
5871 break;
5872 }
5873 } else if ((insn & (1 << 10)) == 0) {
5874 /* VTBL, VTBX. */
a5a14945 5875 int n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5876 if (insn & (1 << 6)) {
8f8e3aa4 5877 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5878 } else {
7d1b0095 5879 tmp = tcg_temp_new_i32();
8f8e3aa4 5880 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5881 }
8f8e3aa4 5882 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5883 tmp4 = tcg_const_i32(rn);
5884 tmp5 = tcg_const_i32(n);
5885 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
7d1b0095 5886 tcg_temp_free_i32(tmp);
9ee6e8bb 5887 if (insn & (1 << 6)) {
8f8e3aa4 5888 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5889 } else {
7d1b0095 5890 tmp = tcg_temp_new_i32();
8f8e3aa4 5891 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5892 }
8f8e3aa4 5893 tmp3 = neon_load_reg(rm, 1);
b75263d6 5894 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5895 tcg_temp_free_i32(tmp5);
5896 tcg_temp_free_i32(tmp4);
8f8e3aa4 5897 neon_store_reg(rd, 0, tmp2);
3018f259 5898 neon_store_reg(rd, 1, tmp3);
7d1b0095 5899 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5900 } else if ((insn & 0x380) == 0) {
5901 /* VDUP */
5902 if (insn & (1 << 19)) {
dd8fbd78 5903 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5904 } else {
dd8fbd78 5905 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5906 }
5907 if (insn & (1 << 16)) {
dd8fbd78 5908 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5909 } else if (insn & (1 << 17)) {
5910 if ((insn >> 18) & 1)
dd8fbd78 5911 gen_neon_dup_high16(tmp);
9ee6e8bb 5912 else
dd8fbd78 5913 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5914 }
5915 for (pass = 0; pass < (q ? 4 : 2); pass++) {
7d1b0095 5916 tmp2 = tcg_temp_new_i32();
dd8fbd78
FN		 5917 tcg_gen_mov_i32(tmp2, tmp);
5918 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5919 }
7d1b0095 5920 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 5921 } else {
5922 return 1;
5923 }
5924 }
5925 }
5926 return 0;
5927}
5928
fe1479c3
PB		 5929static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5930{
5931 int crn = (insn >> 16) & 0xf;
5932 int crm = insn & 0xf;
5933 int op1 = (insn >> 21) & 7;
5934 int op2 = (insn >> 5) & 7;
5935 int rt = (insn >> 12) & 0xf;
5936 TCGv tmp;
5937
ca27c052
PM		 5938 /* Minimal set of debug registers, since we don't support debug */
5939 if (op1 == 0 && crn == 0 && op2 == 0) {
5940 switch (crm) {
5941 case 0:
5942 /* DBGDIDR: just RAZ. In particular this means the
5943 * "debug architecture version" bits will read as
5944 * a reserved value, which should cause Linux to
5945 * not try to use the debug hardware.
5946 */
5947 tmp = tcg_const_i32(0);
5948 store_reg(s, rt, tmp);
5949 return 0;
5950 case 1:
5951 case 2:
5952 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
5953 * don't implement memory mapped debug components
5954 */
5955 if (ENABLE_ARCH_7) {
5956 tmp = tcg_const_i32(0);
5957 store_reg(s, rt, tmp);
5958 return 0;
5959 }
5960 break;
5961 default:
5962 break;
5963 }
5964 }
5965
fe1479c3
PB		 5966 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5967 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5968 /* TEECR */
5969 if (IS_USER(s))
5970 return 1;
5971 tmp = load_cpu_field(teecr);
5972 store_reg(s, rt, tmp);
5973 return 0;
5974 }
5975 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5976 /* TEEHBR */
5977 if (IS_USER(s) && (env->teecr & 1))
5978 return 1;
5979 tmp = load_cpu_field(teehbr);
5980 store_reg(s, rt, tmp);
5981 return 0;
5982 }
5983 }
5984 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5985 op1, crn, crm, op2);
5986 return 1;
5987}
5988
5989static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5990{
5991 int crn = (insn >> 16) & 0xf;
5992 int crm = insn & 0xf;
5993 int op1 = (insn >> 21) & 7;
5994 int op2 = (insn >> 5) & 7;
5995 int rt = (insn >> 12) & 0xf;
5996 TCGv tmp;
5997
5998 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5999 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
6000 /* TEECR */
6001 if (IS_USER(s))
6002 return 1;
6003 tmp = load_reg(s, rt);
6004 gen_helper_set_teecr(cpu_env, tmp);
7d1b0095 6005 tcg_temp_free_i32(tmp);
fe1479c3
PB		 6006 return 0;
6007 }
6008 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
6009 /* TEEHBR */
6010 if (IS_USER(s) && (env->teecr & 1))
6011 return 1;
6012 tmp = load_reg(s, rt);
6013 store_cpu_field(tmp, teehbr);
6014 return 0;
6015 }
6016 }
6017 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
6018 op1, crn, crm, op2);
6019 return 1;
6020}
6021
9ee6e8bb
PB		 6022static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
6023{
6024 int cpnum;
6025
6026 cpnum = (insn >> 8) & 0xf;
6027 if (arm_feature(env, ARM_FEATURE_XSCALE)
6028 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
6029 return 1;
6030
6031 switch (cpnum) {
6032 case 0:
6033 case 1:
6034 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6035 return disas_iwmmxt_insn(env, s, insn);
6036 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
6037 return disas_dsp_insn(env, s, insn);
6038 }
6039 return 1;
6040 case 10:
6041 case 11:
6042 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 6043 case 14:
6044 /* Coprocessors 7-15 are architecturally reserved by ARM.
6045 Unfortunately Intel decided to ignore this. */
6046 if (arm_feature(env, ARM_FEATURE_XSCALE))
6047 goto board;
6048 if (insn & (1 << 20))
6049 return disas_cp14_read(env, s, insn);
6050 else
6051 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 6052 case 15:
6053 return disas_cp15_insn (env, s, insn);
6054 default:
fe1479c3 6055 board:
9ee6e8bb
PB		 6056 /* Unknown coprocessor. See if the board has hooked it. */
6057 return disas_cp_insn (env, s, insn);
6058 }
6059}
6060
5e3f878a
PB		 6061
6062/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 6063static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 6064{
6065 TCGv tmp;
7d1b0095 6066 tmp = tcg_temp_new_i32();
5e3f878a
PB		 6067 tcg_gen_trunc_i64_i32(tmp, val);
6068 store_reg(s, rlow, tmp);
7d1b0095 6069 tmp = tcg_temp_new_i32();
5e3f878a
PB		 6070 tcg_gen_shri_i64(val, val, 32);
6071 tcg_gen_trunc_i64_i32(tmp, val);
6072 store_reg(s, rhigh, tmp);
6073}
6074
6075/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 6076static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 6077{
a7812ae4 6078 TCGv_i64 tmp;
5e3f878a
PB		 6079 TCGv tmp2;
6080
36aa55dc 6081 /* Load value and extend to 64 bits. */
a7812ae4 6082 tmp = tcg_temp_new_i64();
5e3f878a
PB		 6083 tmp2 = load_reg(s, rlow);
6084 tcg_gen_extu_i32_i64(tmp, tmp2);
7d1b0095 6085 tcg_temp_free_i32(tmp2);
5e3f878a 6086 tcg_gen_add_i64(val, val, tmp);
b75263d6 6087 tcg_temp_free_i64(tmp);
5e3f878a
PB		 6088}
6089
6090/* load and add a 64-bit value from a register pair. */
a7812ae4 6091static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 6092{
a7812ae4 6093 TCGv_i64 tmp;
36aa55dc
PB		 6094 TCGv tmpl;
6095 TCGv tmph;
5e3f878a
PB		 6096
6097 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 6098 tmpl = load_reg(s, rlow);
6099 tmph = load_reg(s, rhigh);
a7812ae4 6100 tmp = tcg_temp_new_i64();
36aa55dc 6101 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
7d1b0095
PM		 6102 tcg_temp_free_i32(tmpl);
6103 tcg_temp_free_i32(tmph);
5e3f878a 6104 tcg_gen_add_i64(val, val, tmp);
b75263d6 6105 tcg_temp_free_i64(tmp);
5e3f878a
PB		 6106}
6107
6108/* Set N and Z flags from a 64-bit value. */
a7812ae4 6109static void gen_logicq_cc(TCGv_i64 val)
5e3f878a 6110{
7d1b0095 6111 TCGv tmp = tcg_temp_new_i32();
5e3f878a 6112 gen_helper_logicq_cc(tmp, val);
6fbe23d5 6113 gen_logic_CC(tmp);
7d1b0095 6114 tcg_temp_free_i32(tmp);
5e3f878a
PB		 6115}
6116
426f5abc
PB		 6117/* Load/Store exclusive instructions are implemented by remembering
6118 the value/address loaded, and seeing if these are the same
6119 when the store is performed. This should be is sufficient to implement
6120 the architecturally mandated semantics, and avoids having to monitor
6121 regular stores.
6122
6123 In system emulation mode only one CPU will be running at once, so
6124 this sequence is effectively atomic. In user emulation mode we
6125 throw an exception and handle the atomic operation elsewhere. */
6126static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
6127 TCGv addr, int size)
6128{
6129 TCGv tmp;
6130
6131 switch (size) {
6132 case 0:
6133 tmp = gen_ld8u(addr, IS_USER(s));
6134 break;
6135 case 1:
6136 tmp = gen_ld16u(addr, IS_USER(s));
6137 break;
6138 case 2:
6139 case 3:
6140 tmp = gen_ld32(addr, IS_USER(s));
6141 break;
6142 default:
6143 abort();
6144 }
6145 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
6146 store_reg(s, rt, tmp);
6147 if (size == 3) {
7d1b0095 6148 TCGv tmp2 = tcg_temp_new_i32();
2c9adbda
PM		 6149 tcg_gen_addi_i32(tmp2, addr, 4);
6150 tmp = gen_ld32(tmp2, IS_USER(s));
7d1b0095 6151 tcg_temp_free_i32(tmp2);
426f5abc
PB		 6152 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
6153 store_reg(s, rt2, tmp);
6154 }
6155 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6156}
6157
6158static void gen_clrex(DisasContext *s)
6159{
6160 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6161}
6162
6163#ifdef CONFIG_USER_ONLY
6164static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6165 TCGv addr, int size)
6166{
6167 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6168 tcg_gen_movi_i32(cpu_exclusive_info,
6169 size | (rd << 4) | (rt << 8) | (rt2 << 12));
bc4a0de0 6170 gen_exception_insn(s, 4, EXCP_STREX);
426f5abc
PB		 6171}
6172#else
6173static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6174 TCGv addr, int size)
6175{
6176 TCGv tmp;
6177 int done_label;
6178 int fail_label;
6179
6180 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6181 [addr] = {Rt};
6182 {Rd} = 0;
6183 } else {
6184 {Rd} = 1;
6185 } */
6186 fail_label = gen_new_label();
6187 done_label = gen_new_label();
6188 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6189 switch (size) {
6190 case 0:
6191 tmp = gen_ld8u(addr, IS_USER(s));
6192 break;
6193 case 1:
6194 tmp = gen_ld16u(addr, IS_USER(s));
6195 break;
6196 case 2:
6197 case 3:
6198 tmp = gen_ld32(addr, IS_USER(s));
6199 break;
6200 default:
6201 abort();
6202 }
6203 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
7d1b0095 6204 tcg_temp_free_i32(tmp);
426f5abc 6205 if (size == 3) {
7d1b0095 6206 TCGv tmp2 = tcg_temp_new_i32();
426f5abc 6207 tcg_gen_addi_i32(tmp2, addr, 4);
2c9adbda 6208 tmp = gen_ld32(tmp2, IS_USER(s));
7d1b0095 6209 tcg_temp_free_i32(tmp2);
426f5abc 6210 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
7d1b0095 6211 tcg_temp_free_i32(tmp);
426f5abc
PB		 6212 }
6213 tmp = load_reg(s, rt);
6214 switch (size) {
6215 case 0:
6216 gen_st8(tmp, addr, IS_USER(s));
6217 break;
6218 case 1:
6219 gen_st16(tmp, addr, IS_USER(s));
6220 break;
6221 case 2:
6222 case 3:
6223 gen_st32(tmp, addr, IS_USER(s));
6224 break;
6225 default:
6226 abort();
6227 }
6228 if (size == 3) {
6229 tcg_gen_addi_i32(addr, addr, 4);
6230 tmp = load_reg(s, rt2);
6231 gen_st32(tmp, addr, IS_USER(s));
6232 }
6233 tcg_gen_movi_i32(cpu_R[rd], 0);
6234 tcg_gen_br(done_label);
6235 gen_set_label(fail_label);
6236 tcg_gen_movi_i32(cpu_R[rd], 1);
6237 gen_set_label(done_label);
6238 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6239}
6240#endif
6241
9ee6e8bb
PB		 6242static void disas_arm_insn(CPUState * env, DisasContext *s)
6243{
6244 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6245 TCGv tmp;
3670669c 6246 TCGv tmp2;
6ddbc6e4 6247 TCGv tmp3;
b0109805 6248 TCGv addr;
a7812ae4 6249 TCGv_i64 tmp64;
9ee6e8bb
PB		 6250
6251 insn = ldl_code(s->pc);
6252 s->pc += 4;
6253
6254 /* M variants do not implement ARM mode. */
6255 if (IS_M(env))
6256 goto illegal_op;
6257 cond = insn >> 28;
6258 if (cond == 0xf){
be5e7a76
DES		 6259 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
6260 * choose to UNDEF. In ARMv5 and above the space is used
6261 * for miscellaneous unconditional instructions.
6262 */
6263 ARCH(5);
6264
9ee6e8bb
PB		 6265 /* Unconditional instructions. */
6266 if (((insn >> 25) & 7) == 1) {
6267 /* NEON Data processing. */
6268 if (!arm_feature(env, ARM_FEATURE_NEON))
6269 goto illegal_op;
6270
6271 if (disas_neon_data_insn(env, s, insn))
6272 goto illegal_op;
6273 return;
6274 }
6275 if ((insn & 0x0f100000) == 0x04000000) {
6276 /* NEON load/store. */
6277 if (!arm_feature(env, ARM_FEATURE_NEON))
6278 goto illegal_op;
6279
6280 if (disas_neon_ls_insn(env, s, insn))
6281 goto illegal_op;
6282 return;
6283 }
3d185e5d
PM		 6284 if (((insn & 0x0f30f000) == 0x0510f000) ||
6285 ((insn & 0x0f30f010) == 0x0710f000)) {
6286 if ((insn & (1 << 22)) == 0) {
6287 /* PLDW; v7MP */
6288 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6289 goto illegal_op;
6290 }
6291 }
6292 /* Otherwise PLD; v5TE+ */
be5e7a76 6293 ARCH(5TE);
3d185e5d
PM		 6294 return;
6295 }
6296 if (((insn & 0x0f70f000) == 0x0450f000) ||
6297 ((insn & 0x0f70f010) == 0x0650f000)) {
6298 ARCH(7);
6299 return; /* PLI; V7 */
6300 }
6301 if (((insn & 0x0f700000) == 0x04100000) ||
6302 ((insn & 0x0f700010) == 0x06100000)) {
6303 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6304 goto illegal_op;
6305 }
6306 return; /* v7MP: Unallocated memory hint: must NOP */
6307 }
6308
6309 if ((insn & 0x0ffffdff) == 0x01010000) {
9ee6e8bb
PB		 6310 ARCH(6);
6311 /* setend */
6312 if (insn & (1 << 9)) {
6313 /* BE8 mode not implemented. */
6314 goto illegal_op;
6315 }
6316 return;
6317 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6318 switch ((insn >> 4) & 0xf) {
6319 case 1: /* clrex */
6320 ARCH(6K);
426f5abc 6321 gen_clrex(s);
9ee6e8bb
PB		 6322 return;
6323 case 4: /* dsb */
6324 case 5: /* dmb */
6325 case 6: /* isb */
6326 ARCH(7);
6327 /* We don't emulate caches so these are a no-op. */
6328 return;
6329 default:
6330 goto illegal_op;
6331 }
6332 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6333 /* srs */
c67b6b71 6334 int32_t offset;
9ee6e8bb
PB		 6335 if (IS_USER(s))
6336 goto illegal_op;
6337 ARCH(6);
6338 op1 = (insn & 0x1f);
7d1b0095 6339 addr = tcg_temp_new_i32();
39ea3d4e
PM		 6340 tmp = tcg_const_i32(op1);
6341 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6342 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6343 i = (insn >> 23) & 3;
6344 switch (i) {
6345 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6346 case 1: offset = 0; break; /* IA */
6347 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6348 case 3: offset = 4; break; /* IB */
6349 default: abort();
6350 }
6351 if (offset)
b0109805
PB		 6352 tcg_gen_addi_i32(addr, addr, offset);
6353 tmp = load_reg(s, 14);
6354 gen_st32(tmp, addr, 0);
c67b6b71 6355 tmp = load_cpu_field(spsr);
b0109805
PB		 6356 tcg_gen_addi_i32(addr, addr, 4);
6357 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6358 if (insn & (1 << 21)) {
6359 /* Base writeback. */
6360 switch (i) {
6361 case 0: offset = -8; break;
c67b6b71
FN		 6362 case 1: offset = 4; break;
6363 case 2: offset = -4; break;
9ee6e8bb
PB		 6364 case 3: offset = 0; break;
6365 default: abort();
6366 }
6367 if (offset)
c67b6b71 6368 tcg_gen_addi_i32(addr, addr, offset);
39ea3d4e
PM		 6369 tmp = tcg_const_i32(op1);
6370 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6371 tcg_temp_free_i32(tmp);
7d1b0095 6372 tcg_temp_free_i32(addr);
b0109805 6373 } else {
7d1b0095 6374 tcg_temp_free_i32(addr);
9ee6e8bb 6375 }
a990f58f 6376 return;
ea825eee 6377 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6378 /* rfe */
c67b6b71 6379 int32_t offset;
9ee6e8bb
PB		 6380 if (IS_USER(s))
6381 goto illegal_op;
6382 ARCH(6);
6383 rn = (insn >> 16) & 0xf;
b0109805 6384 addr = load_reg(s, rn);
9ee6e8bb
PB		 6385 i = (insn >> 23) & 3;
6386 switch (i) {
b0109805 6387 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6388 case 1: offset = 0; break; /* IA */
6389 case 2: offset = -8; break; /* DB */
b0109805 6390 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6391 default: abort();
6392 }
6393 if (offset)
b0109805
PB		 6394 tcg_gen_addi_i32(addr, addr, offset);
6395 /* Load PC into tmp and CPSR into tmp2. */
6396 tmp = gen_ld32(addr, 0);
6397 tcg_gen_addi_i32(addr, addr, 4);
6398 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6399 if (insn & (1 << 21)) {
6400 /* Base writeback. */
6401 switch (i) {
b0109805 6402 case 0: offset = -8; break;
c67b6b71
FN		 6403 case 1: offset = 4; break;
6404 case 2: offset = -4; break;
b0109805 6405 case 3: offset = 0; break;
9ee6e8bb
PB		 6406 default: abort();
6407 }
6408 if (offset)
b0109805
PB		 6409 tcg_gen_addi_i32(addr, addr, offset);
6410 store_reg(s, rn, addr);
6411 } else {
7d1b0095 6412 tcg_temp_free_i32(addr);
9ee6e8bb 6413 }
b0109805 6414 gen_rfe(s, tmp, tmp2);
c67b6b71 6415 return;
9ee6e8bb
PB		 6416 } else if ((insn & 0x0e000000) == 0x0a000000) {
6417 /* branch link and change to thumb (blx <offset>) */
6418 int32_t offset;
6419
6420 val = (uint32_t)s->pc;
7d1b0095 6421 tmp = tcg_temp_new_i32();
d9ba4830
PB		 6422 tcg_gen_movi_i32(tmp, val);
6423 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6424 /* Sign-extend the 24-bit offset */
6425 offset = (((int32_t)insn) << 8) >> 8;
6426 /* offset * 4 + bit24 * 2 + (thumb bit) */
6427 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6428 /* pipeline offset */
6429 val += 4;
be5e7a76 6430 /* protected by ARCH(5); above, near the start of uncond block */
d9ba4830 6431 gen_bx_im(s, val);
9ee6e8bb
PB		 6432 return;
6433 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6434 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6435 /* iWMMXt register transfer. */
6436 if (env->cp15.c15_cpar & (1 << 1))
6437 if (!disas_iwmmxt_insn(env, s, insn))
6438 return;
6439 }
6440 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6441 /* Coprocessor double register transfer. */
be5e7a76 6442 ARCH(5TE);
9ee6e8bb
PB		 6443 } else if ((insn & 0x0f000010) == 0x0e000010) {
6444 /* Additional coprocessor register transfer. */
7997d92f 6445 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6446 uint32_t mask;
6447 uint32_t val;
6448 /* cps (privileged) */
6449 if (IS_USER(s))
6450 return;
6451 mask = val = 0;
6452 if (insn & (1 << 19)) {
6453 if (insn & (1 << 8))
6454 mask |= CPSR_A;
6455 if (insn & (1 << 7))
6456 mask |= CPSR_I;
6457 if (insn & (1 << 6))
6458 mask |= CPSR_F;
6459 if (insn & (1 << 18))
6460 val |= mask;
6461 }
7997d92f 6462 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6463 mask |= CPSR_M;
6464 val |= (insn & 0x1f);
6465 }
6466 if (mask) {
2fbac54b 6467 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6468 }
6469 return;
6470 }
6471 goto illegal_op;
6472 }
6473 if (cond != 0xe) {
6474 /* if not always execute, we generate a conditional jump to
6475 next instruction */
6476 s->condlabel = gen_new_label();
d9ba4830 6477 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6478 s->condjmp = 1;
6479 }
6480 if ((insn & 0x0f900000) == 0x03000000) {
6481 if ((insn & (1 << 21)) == 0) {
6482 ARCH(6T2);
6483 rd = (insn >> 12) & 0xf;
6484 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6485 if ((insn & (1 << 22)) == 0) {
6486 /* MOVW */
7d1b0095 6487 tmp = tcg_temp_new_i32();
5e3f878a 6488 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6489 } else {
6490 /* MOVT */
5e3f878a 6491 tmp = load_reg(s, rd);
86831435 6492 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6493 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6494 }
5e3f878a 6495 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6496 } else {
6497 if (((insn >> 12) & 0xf) != 0xf)
6498 goto illegal_op;
6499 if (((insn >> 16) & 0xf) == 0) {
6500 gen_nop_hint(s, insn & 0xff);
6501 } else {
6502 /* CPSR = immediate */
6503 val = insn & 0xff;
6504 shift = ((insn >> 8) & 0xf) * 2;
6505 if (shift)
6506 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6507 i = ((insn & (1 << 22)) != 0);
2fbac54b 6508 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6509 goto illegal_op;
6510 }
6511 }
6512 } else if ((insn & 0x0f900000) == 0x01000000
6513 && (insn & 0x00000090) != 0x00000090) {
6514 /* miscellaneous instructions */
6515 op1 = (insn >> 21) & 3;
6516 sh = (insn >> 4) & 0xf;
6517 rm = insn & 0xf;
6518 switch (sh) {
6519 case 0x0: /* move program status register */
6520 if (op1 & 1) {
6521 /* PSR = reg */
2fbac54b 6522 tmp = load_reg(s, rm);
9ee6e8bb 6523 i = ((op1 & 2) != 0);
2fbac54b 6524 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6525 goto illegal_op;
6526 } else {
6527 /* reg = PSR */
6528 rd = (insn >> 12) & 0xf;
6529 if (op1 & 2) {
6530 if (IS_USER(s))
6531 goto illegal_op;
d9ba4830 6532 tmp = load_cpu_field(spsr);
9ee6e8bb 6533 } else {
7d1b0095 6534 tmp = tcg_temp_new_i32();
d9ba4830 6535 gen_helper_cpsr_read(tmp);
9ee6e8bb 6536 }
d9ba4830 6537 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6538 }
6539 break;
6540 case 0x1:
6541 if (op1 == 1) {
6542 /* branch/exchange thumb (bx). */
be5e7a76 6543 ARCH(4T);
d9ba4830
PB		 6544 tmp = load_reg(s, rm);
6545 gen_bx(s, tmp);
9ee6e8bb
PB		 6546 } else if (op1 == 3) {
6547 /* clz */
be5e7a76 6548 ARCH(5);
9ee6e8bb 6549 rd = (insn >> 12) & 0xf;
1497c961
PB		 6550 tmp = load_reg(s, rm);
6551 gen_helper_clz(tmp, tmp);
6552 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6553 } else {
6554 goto illegal_op;
6555 }
6556 break;
6557 case 0x2:
6558 if (op1 == 1) {
6559 ARCH(5J); /* bxj */
6560 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6561 tmp = load_reg(s, rm);
6562 gen_bx(s, tmp);
9ee6e8bb
PB		 6563 } else {
6564 goto illegal_op;
6565 }
6566 break;
6567 case 0x3:
6568 if (op1 != 1)
6569 goto illegal_op;
6570
be5e7a76 6571 ARCH(5);
9ee6e8bb 6572 /* branch link/exchange thumb (blx) */
d9ba4830 6573 tmp = load_reg(s, rm);
7d1b0095 6574 tmp2 = tcg_temp_new_i32();
d9ba4830
PB		 6575 tcg_gen_movi_i32(tmp2, s->pc);
6576 store_reg(s, 14, tmp2);
6577 gen_bx(s, tmp);
9ee6e8bb
PB		 6578 break;
6579 case 0x5: /* saturating add/subtract */
be5e7a76 6580 ARCH(5TE);
9ee6e8bb
PB		 6581 rd = (insn >> 12) & 0xf;
6582 rn = (insn >> 16) & 0xf;
b40d0353 6583 tmp = load_reg(s, rm);
5e3f878a 6584 tmp2 = load_reg(s, rn);
9ee6e8bb 6585 if (op1 & 2)
5e3f878a 6586 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6587 if (op1 & 1)
5e3f878a 6588 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6589 else
5e3f878a 6590 gen_helper_add_saturate(tmp, tmp, tmp2);
7d1b0095 6591 tcg_temp_free_i32(tmp2);
5e3f878a 6592 store_reg(s, rd, tmp);
9ee6e8bb 6593 break;
49e14940
AL		 6594 case 7:
6595 /* SMC instruction (op1 == 3)
6596 and undefined instructions (op1 == 0 || op1 == 2)
6597 will trap */
6598 if (op1 != 1) {
6599 goto illegal_op;
6600 }
6601 /* bkpt */
be5e7a76 6602 ARCH(5);
bc4a0de0 6603 gen_exception_insn(s, 4, EXCP_BKPT);
9ee6e8bb
PB		 6604 break;
6605 case 0x8: /* signed multiply */
6606 case 0xa:
6607 case 0xc:
6608 case 0xe:
be5e7a76 6609 ARCH(5TE);
9ee6e8bb
PB		 6610 rs = (insn >> 8) & 0xf;
6611 rn = (insn >> 12) & 0xf;
6612 rd = (insn >> 16) & 0xf;
6613 if (op1 == 1) {
6614 /* (32 * 16) >> 16 */
5e3f878a
PB		 6615 tmp = load_reg(s, rm);
6616 tmp2 = load_reg(s, rs);
9ee6e8bb 6617 if (sh & 4)
5e3f878a 6618 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6619 else
5e3f878a 6620 gen_sxth(tmp2);
a7812ae4
PB		 6621 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6622 tcg_gen_shri_i64(tmp64, tmp64, 16);
7d1b0095 6623 tmp = tcg_temp_new_i32();
a7812ae4 6624 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6625 tcg_temp_free_i64(tmp64);
9ee6e8bb 6626 if ((sh & 2) == 0) {
5e3f878a
PB		 6627 tmp2 = load_reg(s, rn);
6628 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 6629 tcg_temp_free_i32(tmp2);
9ee6e8bb 6630 }
5e3f878a 6631 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6632 } else {
6633 /* 16 * 16 */
5e3f878a
PB		 6634 tmp = load_reg(s, rm);
6635 tmp2 = load_reg(s, rs);
6636 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
7d1b0095 6637 tcg_temp_free_i32(tmp2);
9ee6e8bb 6638 if (op1 == 2) {
a7812ae4
PB		 6639 tmp64 = tcg_temp_new_i64();
6640 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 6641 tcg_temp_free_i32(tmp);
a7812ae4
PB		 6642 gen_addq(s, tmp64, rn, rd);
6643 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6644 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6645 } else {
6646 if (op1 == 0) {
5e3f878a
PB		 6647 tmp2 = load_reg(s, rn);
6648 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 6649 tcg_temp_free_i32(tmp2);
9ee6e8bb 6650 }
5e3f878a 6651 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6652 }
6653 }
6654 break;
6655 default:
6656 goto illegal_op;
6657 }
6658 } else if (((insn & 0x0e000000) == 0 &&
6659 (insn & 0x00000090) != 0x90) ||
6660 ((insn & 0x0e000000) == (1 << 25))) {
6661 int set_cc, logic_cc, shiftop;
6662
6663 op1 = (insn >> 21) & 0xf;
6664 set_cc = (insn >> 20) & 1;
6665 logic_cc = table_logic_cc[op1] & set_cc;
6666
6667 /* data processing instruction */
6668 if (insn & (1 << 25)) {
6669 /* immediate operand */
6670 val = insn & 0xff;
6671 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6672 if (shift) {
9ee6e8bb 6673 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9 6674 }
7d1b0095 6675 tmp2 = tcg_temp_new_i32();
e9bb4aa9
JR		 6676 tcg_gen_movi_i32(tmp2, val);
6677 if (logic_cc && shift) {
6678 gen_set_CF_bit31(tmp2);
6679 }
9ee6e8bb
PB		 6680 } else {
6681 /* register */
6682 rm = (insn) & 0xf;
e9bb4aa9 6683 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6684 shiftop = (insn >> 5) & 3;
6685 if (!(insn & (1 << 4))) {
6686 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6687 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6688 } else {
6689 rs = (insn >> 8) & 0xf;
8984bd2e 6690 tmp = load_reg(s, rs);
e9bb4aa9 6691 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6692 }
6693 }
6694 if (op1 != 0x0f && op1 != 0x0d) {
6695 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6696 tmp = load_reg(s, rn);
6697 } else {
6698 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6699 }
6700 rd = (insn >> 12) & 0xf;
6701 switch(op1) {
6702 case 0x00:
e9bb4aa9
JR		 6703 tcg_gen_and_i32(tmp, tmp, tmp2);
6704 if (logic_cc) {
6705 gen_logic_CC(tmp);
6706 }
21aeb343 6707 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6708 break;
6709 case 0x01:
e9bb4aa9
JR		 6710 tcg_gen_xor_i32(tmp, tmp, tmp2);
6711 if (logic_cc) {
6712 gen_logic_CC(tmp);
6713 }
21aeb343 6714 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6715 break;
6716 case 0x02:
6717 if (set_cc && rd == 15) {
6718 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6719 if (IS_USER(s)) {
9ee6e8bb 6720 goto illegal_op;
e9bb4aa9
JR		 6721 }
6722 gen_helper_sub_cc(tmp, tmp, tmp2);
6723 gen_exception_return(s, tmp);
9ee6e8bb 6724 } else {
e9bb4aa9
JR		 6725 if (set_cc) {
6726 gen_helper_sub_cc(tmp, tmp, tmp2);
6727 } else {
6728 tcg_gen_sub_i32(tmp, tmp, tmp2);
6729 }
21aeb343 6730 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6731 }
6732 break;
6733 case 0x03:
e9bb4aa9
JR		 6734 if (set_cc) {
6735 gen_helper_sub_cc(tmp, tmp2, tmp);
6736 } else {
6737 tcg_gen_sub_i32(tmp, tmp2, tmp);
6738 }
21aeb343 6739 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6740 break;
6741 case 0x04:
e9bb4aa9
JR		 6742 if (set_cc) {
6743 gen_helper_add_cc(tmp, tmp, tmp2);
6744 } else {
6745 tcg_gen_add_i32(tmp, tmp, tmp2);
6746 }
21aeb343 6747 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6748 break;
6749 case 0x05:
e9bb4aa9
JR		 6750 if (set_cc) {
6751 gen_helper_adc_cc(tmp, tmp, tmp2);
6752 } else {
6753 gen_add_carry(tmp, tmp, tmp2);
6754 }
21aeb343 6755 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6756 break;
6757 case 0x06:
e9bb4aa9
JR		 6758 if (set_cc) {
6759 gen_helper_sbc_cc(tmp, tmp, tmp2);
6760 } else {
6761 gen_sub_carry(tmp, tmp, tmp2);
6762 }
21aeb343 6763 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6764 break;
6765 case 0x07:
e9bb4aa9
JR		 6766 if (set_cc) {
6767 gen_helper_sbc_cc(tmp, tmp2, tmp);
6768 } else {
6769 gen_sub_carry(tmp, tmp2, tmp);
6770 }
21aeb343 6771 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6772 break;
6773 case 0x08:
6774 if (set_cc) {
e9bb4aa9
JR		 6775 tcg_gen_and_i32(tmp, tmp, tmp2);
6776 gen_logic_CC(tmp);
9ee6e8bb 6777 }
7d1b0095 6778 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6779 break;
6780 case 0x09:
6781 if (set_cc) {
e9bb4aa9
JR		 6782 tcg_gen_xor_i32(tmp, tmp, tmp2);
6783 gen_logic_CC(tmp);
9ee6e8bb 6784 }
7d1b0095 6785 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6786 break;
6787 case 0x0a:
6788 if (set_cc) {
e9bb4aa9 6789 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6790 }
7d1b0095 6791 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6792 break;
6793 case 0x0b:
6794 if (set_cc) {
e9bb4aa9 6795 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6796 }
7d1b0095 6797 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6798 break;
6799 case 0x0c:
e9bb4aa9
JR		 6800 tcg_gen_or_i32(tmp, tmp, tmp2);
6801 if (logic_cc) {
6802 gen_logic_CC(tmp);
6803 }
21aeb343 6804 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6805 break;
6806 case 0x0d:
6807 if (logic_cc && rd == 15) {
6808 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6809 if (IS_USER(s)) {
9ee6e8bb 6810 goto illegal_op;
e9bb4aa9
JR		 6811 }
6812 gen_exception_return(s, tmp2);
9ee6e8bb 6813 } else {
e9bb4aa9
JR		 6814 if (logic_cc) {
6815 gen_logic_CC(tmp2);
6816 }
21aeb343 6817 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6818 }
6819 break;
6820 case 0x0e:
f669df27 6821 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6822 if (logic_cc) {
6823 gen_logic_CC(tmp);
6824 }
21aeb343 6825 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6826 break;
6827 default:
6828 case 0x0f:
e9bb4aa9
JR		 6829 tcg_gen_not_i32(tmp2, tmp2);
6830 if (logic_cc) {
6831 gen_logic_CC(tmp2);
6832 }
21aeb343 6833 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6834 break;
6835 }
e9bb4aa9 6836 if (op1 != 0x0f && op1 != 0x0d) {
7d1b0095 6837 tcg_temp_free_i32(tmp2);
e9bb4aa9 6838 }
9ee6e8bb
PB		 6839 } else {
6840 /* other instructions */
6841 op1 = (insn >> 24) & 0xf;
6842 switch(op1) {
6843 case 0x0:
6844 case 0x1:
6845 /* multiplies, extra load/stores */
6846 sh = (insn >> 5) & 3;
6847 if (sh == 0) {
6848 if (op1 == 0x0) {
6849 rd = (insn >> 16) & 0xf;
6850 rn = (insn >> 12) & 0xf;
6851 rs = (insn >> 8) & 0xf;
6852 rm = (insn) & 0xf;
6853 op1 = (insn >> 20) & 0xf;
6854 switch (op1) {
6855 case 0: case 1: case 2: case 3: case 6:
6856 /* 32 bit mul */
5e3f878a
PB		 6857 tmp = load_reg(s, rs);
6858 tmp2 = load_reg(s, rm);
6859 tcg_gen_mul_i32(tmp, tmp, tmp2);
7d1b0095 6860 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6861 if (insn & (1 << 22)) {
6862 /* Subtract (mls) */
6863 ARCH(6T2);
5e3f878a
PB		 6864 tmp2 = load_reg(s, rn);
6865 tcg_gen_sub_i32(tmp, tmp2, tmp);
7d1b0095 6866 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6867 } else if (insn & (1 << 21)) {
6868 /* Add */
5e3f878a
PB		 6869 tmp2 = load_reg(s, rn);
6870 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 6871 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 6872 }
6873 if (insn & (1 << 20))
5e3f878a
PB		 6874 gen_logic_CC(tmp);
6875 store_reg(s, rd, tmp);
9ee6e8bb 6876 break;
8aac08b1
AJ		 6877 case 4:
6878 /* 64 bit mul double accumulate (UMAAL) */
6879 ARCH(6);
6880 tmp = load_reg(s, rs);
6881 tmp2 = load_reg(s, rm);
6882 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6883 gen_addq_lo(s, tmp64, rn);
6884 gen_addq_lo(s, tmp64, rd);
6885 gen_storeq_reg(s, rn, rd, tmp64);
6886 tcg_temp_free_i64(tmp64);
6887 break;
6888 case 8: case 9: case 10: case 11:
6889 case 12: case 13: case 14: case 15:
6890 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
5e3f878a
PB		 6891 tmp = load_reg(s, rs);
6892 tmp2 = load_reg(s, rm);
8aac08b1 6893 if (insn & (1 << 22)) {
a7812ae4 6894 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8aac08b1 6895 } else {
a7812ae4 6896 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8aac08b1
AJ		 6897 }
6898 if (insn & (1 << 21)) { /* mult accumulate */
a7812ae4 6899 gen_addq(s, tmp64, rn, rd);
9ee6e8bb 6900 }
8aac08b1 6901 if (insn & (1 << 20)) {
a7812ae4 6902 gen_logicq_cc(tmp64);
8aac08b1 6903 }
a7812ae4 6904 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6905 tcg_temp_free_i64(tmp64);
9ee6e8bb 6906 break;
8aac08b1
AJ		 6907 default:
6908 goto illegal_op;
9ee6e8bb
PB		 6909 }
6910 } else {
6911 rn = (insn >> 16) & 0xf;
6912 rd = (insn >> 12) & 0xf;
6913 if (insn & (1 << 23)) {
6914 /* load/store exclusive */
86753403
PB		 6915 op1 = (insn >> 21) & 0x3;
6916 if (op1)
a47f43d2 6917 ARCH(6K);
86753403
PB		 6918 else
6919 ARCH(6);
3174f8e9 6920 addr = tcg_temp_local_new_i32();
98a46317 6921 load_reg_var(s, addr, rn);
9ee6e8bb 6922 if (insn & (1 << 20)) {
86753403
PB		 6923 switch (op1) {
6924 case 0: /* ldrex */
426f5abc 6925 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6926 break;
6927 case 1: /* ldrexd */
426f5abc 6928 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6929 break;
6930 case 2: /* ldrexb */
426f5abc 6931 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6932 break;
6933 case 3: /* ldrexh */
426f5abc 6934 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6935 break;
6936 default:
6937 abort();
6938 }
9ee6e8bb
PB		 6939 } else {
6940 rm = insn & 0xf;
86753403
PB		 6941 switch (op1) {
6942 case 0: /* strex */
426f5abc 6943 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6944 break;
6945 case 1: /* strexd */
502e64fe 6946 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6947 break;
6948 case 2: /* strexb */
426f5abc 6949 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6950 break;
6951 case 3: /* strexh */
426f5abc 6952 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6953 break;
6954 default:
6955 abort();
6956 }
9ee6e8bb 6957 }
3174f8e9 6958 tcg_temp_free(addr);
9ee6e8bb
PB		 6959 } else {
6960 /* SWP instruction */
6961 rm = (insn) & 0xf;
6962
8984bd2e
PB		 6963 /* ??? This is not really atomic. However we know
6964 we never have multiple CPUs running in parallel,
6965 so it is good enough. */
6966 addr = load_reg(s, rn);
6967 tmp = load_reg(s, rm);
9ee6e8bb 6968 if (insn & (1 << 22)) {
8984bd2e
PB		 6969 tmp2 = gen_ld8u(addr, IS_USER(s));
6970 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6971 } else {
8984bd2e
PB		 6972 tmp2 = gen_ld32(addr, IS_USER(s));
6973 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6974 }
7d1b0095 6975 tcg_temp_free_i32(addr);
8984bd2e 6976 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6977 }
6978 }
6979 } else {
6980 int address_offset;
6981 int load;
6982 /* Misc load/store */
6983 rn = (insn >> 16) & 0xf;
6984 rd = (insn >> 12) & 0xf;
b0109805 6985 addr = load_reg(s, rn);
9ee6e8bb 6986 if (insn & (1 << 24))
b0109805 6987 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6988 address_offset = 0;
6989 if (insn & (1 << 20)) {
6990 /* load */
6991 switch(sh) {
6992 case 1:
b0109805 6993 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6994 break;
6995 case 2:
b0109805 6996 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6997 break;
6998 default:
6999 case 3:
b0109805 7000 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 7001 break;
7002 }
7003 load = 1;
7004 } else if (sh & 2) {
be5e7a76 7005 ARCH(5TE);
9ee6e8bb
PB		 7006 /* doubleword */
7007 if (sh & 1) {
7008 /* store */
b0109805
PB		 7009 tmp = load_reg(s, rd);
7010 gen_st32(tmp, addr, IS_USER(s));
7011 tcg_gen_addi_i32(addr, addr, 4);
7012 tmp = load_reg(s, rd + 1);
7013 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7014 load = 0;
7015 } else {
7016 /* load */
b0109805
PB		 7017 tmp = gen_ld32(addr, IS_USER(s));
7018 store_reg(s, rd, tmp);
7019 tcg_gen_addi_i32(addr, addr, 4);
7020 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 7021 rd++;
7022 load = 1;
7023 }
7024 address_offset = -4;
7025 } else {
7026 /* store */
b0109805
PB		 7027 tmp = load_reg(s, rd);
7028 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7029 load = 0;
7030 }
7031 /* Perform base writeback before the loaded value to
7032 ensure correct behavior with overlapping index registers.
7033 ldrd with base writeback is is undefined if the
7034 destination and index registers overlap. */
7035 if (!(insn & (1 << 24))) {
b0109805
PB		 7036 gen_add_datah_offset(s, insn, address_offset, addr);
7037 store_reg(s, rn, addr);
9ee6e8bb
PB		 7038 } else if (insn & (1 << 21)) {
7039 if (address_offset)
b0109805
PB		 7040 tcg_gen_addi_i32(addr, addr, address_offset);
7041 store_reg(s, rn, addr);
7042 } else {
7d1b0095 7043 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7044 }
7045 if (load) {
7046 /* Complete the load. */
b0109805 7047 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7048 }
7049 }
7050 break;
7051 case 0x4:
7052 case 0x5:
7053 goto do_ldst;
7054 case 0x6:
7055 case 0x7:
7056 if (insn & (1 << 4)) {
7057 ARCH(6);
7058 /* Armv6 Media instructions. */
7059 rm = insn & 0xf;
7060 rn = (insn >> 16) & 0xf;
2c0262af 7061 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 7062 rs = (insn >> 8) & 0xf;
7063 switch ((insn >> 23) & 3) {
7064 case 0: /* Parallel add/subtract. */
7065 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 7066 tmp = load_reg(s, rn);
7067 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7068 sh = (insn >> 5) & 7;
7069 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
7070 goto illegal_op;
6ddbc6e4 7071 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
7d1b0095 7072 tcg_temp_free_i32(tmp2);
6ddbc6e4 7073 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7074 break;
7075 case 1:
7076 if ((insn & 0x00700020) == 0) {
6c95676b 7077 /* Halfword pack. */
3670669c
PB		 7078 tmp = load_reg(s, rn);
7079 tmp2 = load_reg(s, rm);
9ee6e8bb 7080 shift = (insn >> 7) & 0x1f;
3670669c
PB		 7081 if (insn & (1 << 6)) {
7082 /* pkhtb */
22478e79
AZ		 7083 if (shift == 0)
7084 shift = 31;
7085 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 7086 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 7087 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 7088 } else {
7089 /* pkhbt */
22478e79
AZ		 7090 if (shift)
7091 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 7092 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 7093 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7094 }
7095 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 7096 tcg_temp_free_i32(tmp2);
3670669c 7097 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7098 } else if ((insn & 0x00200020) == 0x00200000) {
7099 /* [us]sat */
6ddbc6e4 7100 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7101 shift = (insn >> 7) & 0x1f;
7102 if (insn & (1 << 6)) {
7103 if (shift == 0)
7104 shift = 31;
6ddbc6e4 7105 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 7106 } else {
6ddbc6e4 7107 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 7108 }
7109 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 7110 tmp2 = tcg_const_i32(sh);
7111 if (insn & (1 << 22))
7112 gen_helper_usat(tmp, tmp, tmp2);
7113 else
7114 gen_helper_ssat(tmp, tmp, tmp2);
7115 tcg_temp_free_i32(tmp2);
6ddbc6e4 7116 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7117 } else if ((insn & 0x00300fe0) == 0x00200f20) {
7118 /* [us]sat16 */
6ddbc6e4 7119 tmp = load_reg(s, rm);
9ee6e8bb 7120 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 7121 tmp2 = tcg_const_i32(sh);
7122 if (insn & (1 << 22))
7123 gen_helper_usat16(tmp, tmp, tmp2);
7124 else
7125 gen_helper_ssat16(tmp, tmp, tmp2);
7126 tcg_temp_free_i32(tmp2);
6ddbc6e4 7127 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7128 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
7129 /* Select bytes. */
6ddbc6e4
PB		 7130 tmp = load_reg(s, rn);
7131 tmp2 = load_reg(s, rm);
7d1b0095 7132 tmp3 = tcg_temp_new_i32();
6ddbc6e4
PB		 7133 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7134 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7d1b0095
PM		 7135 tcg_temp_free_i32(tmp3);
7136 tcg_temp_free_i32(tmp2);
6ddbc6e4 7137 store_reg(s, rd, tmp);
9ee6e8bb 7138 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 7139 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7140 shift = (insn >> 10) & 3;
7141 /* ??? In many cases it's not neccessary to do a
7142 rotate, a shift is sufficient. */
7143 if (shift != 0)
f669df27 7144 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7145 op1 = (insn >> 20) & 7;
7146 switch (op1) {
5e3f878a
PB		 7147 case 0: gen_sxtb16(tmp); break;
7148 case 2: gen_sxtb(tmp); break;
7149 case 3: gen_sxth(tmp); break;
7150 case 4: gen_uxtb16(tmp); break;
7151 case 6: gen_uxtb(tmp); break;
7152 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 7153 default: goto illegal_op;
7154 }
7155 if (rn != 15) {
5e3f878a 7156 tmp2 = load_reg(s, rn);
9ee6e8bb 7157 if ((op1 & 3) == 0) {
5e3f878a 7158 gen_add16(tmp, tmp2);
9ee6e8bb 7159 } else {
5e3f878a 7160 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7161 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7162 }
7163 }
6c95676b 7164 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7165 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
7166 /* rev */
b0109805 7167 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7168 if (insn & (1 << 22)) {
7169 if (insn & (1 << 7)) {
b0109805 7170 gen_revsh(tmp);
9ee6e8bb
PB		 7171 } else {
7172 ARCH(6T2);
b0109805 7173 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7174 }
7175 } else {
7176 if (insn & (1 << 7))
b0109805 7177 gen_rev16(tmp);
9ee6e8bb 7178 else
66896cb8 7179 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 7180 }
b0109805 7181 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7182 } else {
7183 goto illegal_op;
7184 }
7185 break;
7186 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 7187 tmp = load_reg(s, rm);
7188 tmp2 = load_reg(s, rs);
9ee6e8bb 7189 if (insn & (1 << 20)) {
838fa72d
AJ		 7190 /* Signed multiply most significant [accumulate].
7191 (SMMUL, SMMLA, SMMLS) */
a7812ae4 7192 tmp64 = gen_muls_i64_i32(tmp, tmp2);
838fa72d 7193
955a7dd5 7194 if (rd != 15) {
838fa72d 7195 tmp = load_reg(s, rd);
9ee6e8bb 7196 if (insn & (1 << 6)) {
838fa72d 7197 tmp64 = gen_subq_msw(tmp64, tmp);
9ee6e8bb 7198 } else {
838fa72d 7199 tmp64 = gen_addq_msw(tmp64, tmp);
9ee6e8bb
PB		 7200 }
7201 }
838fa72d
AJ		 7202 if (insn & (1 << 5)) {
7203 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7204 }
7205 tcg_gen_shri_i64(tmp64, tmp64, 32);
7d1b0095 7206 tmp = tcg_temp_new_i32();
838fa72d
AJ		 7207 tcg_gen_trunc_i64_i32(tmp, tmp64);
7208 tcg_temp_free_i64(tmp64);
955a7dd5 7209 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7210 } else {
7211 if (insn & (1 << 5))
5e3f878a
PB		 7212 gen_swap_half(tmp2);
7213 gen_smul_dual(tmp, tmp2);
5e3f878a 7214 if (insn & (1 << 6)) {
e1d177b9 7215 /* This subtraction cannot overflow. */
5e3f878a
PB		 7216 tcg_gen_sub_i32(tmp, tmp, tmp2);
7217 } else {
e1d177b9
PM		 7218 /* This addition cannot overflow 32 bits;
7219 * however it may overflow considered as a signed
7220 * operation, in which case we must set the Q flag.
7221 */
7222 gen_helper_add_setq(tmp, tmp, tmp2);
5e3f878a 7223 }
7d1b0095 7224 tcg_temp_free_i32(tmp2);
9ee6e8bb 7225 if (insn & (1 << 22)) {
5e3f878a 7226 /* smlald, smlsld */
a7812ae4
PB		 7227 tmp64 = tcg_temp_new_i64();
7228 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 7229 tcg_temp_free_i32(tmp);
a7812ae4
PB		 7230 gen_addq(s, tmp64, rd, rn);
7231 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 7232 tcg_temp_free_i64(tmp64);
9ee6e8bb 7233 } else {
5e3f878a 7234 /* smuad, smusd, smlad, smlsd */
22478e79 7235 if (rd != 15)
9ee6e8bb 7236 {
22478e79 7237 tmp2 = load_reg(s, rd);
5e3f878a 7238 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 7239 tcg_temp_free_i32(tmp2);
9ee6e8bb 7240 }
22478e79 7241 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7242 }
7243 }
7244 break;
7245 case 3:
7246 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7247 switch (op1) {
7248 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 7249 ARCH(6);
7250 tmp = load_reg(s, rm);
7251 tmp2 = load_reg(s, rs);
7252 gen_helper_usad8(tmp, tmp, tmp2);
7d1b0095 7253 tcg_temp_free_i32(tmp2);
ded9d295
AZ		 7254 if (rd != 15) {
7255 tmp2 = load_reg(s, rd);
6ddbc6e4 7256 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7257 tcg_temp_free_i32(tmp2);
9ee6e8bb 7258 }
ded9d295 7259 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7260 break;
7261 case 0x20: case 0x24: case 0x28: case 0x2c:
7262 /* Bitfield insert/clear. */
7263 ARCH(6T2);
7264 shift = (insn >> 7) & 0x1f;
7265 i = (insn >> 16) & 0x1f;
7266 i = i + 1 - shift;
7267 if (rm == 15) {
7d1b0095 7268 tmp = tcg_temp_new_i32();
5e3f878a 7269 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7270 } else {
5e3f878a 7271 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7272 }
7273 if (i != 32) {
5e3f878a 7274 tmp2 = load_reg(s, rd);
8f8e3aa4 7275 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7d1b0095 7276 tcg_temp_free_i32(tmp2);
9ee6e8bb 7277 }
5e3f878a 7278 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7279 break;
7280 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7281 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7282 ARCH(6T2);
5e3f878a 7283 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7284 shift = (insn >> 7) & 0x1f;
7285 i = ((insn >> 16) & 0x1f) + 1;
7286 if (shift + i > 32)
7287 goto illegal_op;
7288 if (i < 32) {
7289 if (op1 & 0x20) {
5e3f878a 7290 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7291 } else {
5e3f878a 7292 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7293 }
7294 }
5e3f878a 7295 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7296 break;
7297 default:
7298 goto illegal_op;
7299 }
7300 break;
7301 }
7302 break;
7303 }
7304 do_ldst:
7305 /* Check for undefined extension instructions
7306 * per the ARM Bible IE:
7307 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7308 */
7309 sh = (0xf << 20) | (0xf << 4);
7310 if (op1 == 0x7 && ((insn & sh) == sh))
7311 {
7312 goto illegal_op;
7313 }
7314 /* load/store byte/word */
7315 rn = (insn >> 16) & 0xf;
7316 rd = (insn >> 12) & 0xf;
b0109805 7317 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7318 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7319 if (insn & (1 << 24))
b0109805 7320 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7321 if (insn & (1 << 20)) {
7322 /* load */
9ee6e8bb 7323 if (insn & (1 << 22)) {
b0109805 7324 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7325 } else {
b0109805 7326 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7327 }
9ee6e8bb
PB		 7328 } else {
7329 /* store */
b0109805 7330 tmp = load_reg(s, rd);
9ee6e8bb 7331 if (insn & (1 << 22))
b0109805 7332 gen_st8(tmp, tmp2, i);
9ee6e8bb 7333 else
b0109805 7334 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7335 }
7336 if (!(insn & (1 << 24))) {
b0109805
PB		 7337 gen_add_data_offset(s, insn, tmp2);
7338 store_reg(s, rn, tmp2);
7339 } else if (insn & (1 << 21)) {
7340 store_reg(s, rn, tmp2);
7341 } else {
7d1b0095 7342 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7343 }
7344 if (insn & (1 << 20)) {
7345 /* Complete the load. */
be5e7a76 7346 store_reg_from_load(env, s, rd, tmp);
9ee6e8bb
PB		 7347 }
7348 break;
7349 case 0x08:
7350 case 0x09:
7351 {
7352 int j, n, user, loaded_base;
b0109805 7353 TCGv loaded_var;
9ee6e8bb
PB		 7354 /* load/store multiple words */
7355 /* XXX: store correct base if write back */
7356 user = 0;
7357 if (insn & (1 << 22)) {
7358 if (IS_USER(s))
7359 goto illegal_op; /* only usable in supervisor mode */
7360
7361 if ((insn & (1 << 15)) == 0)
7362 user = 1;
7363 }
7364 rn = (insn >> 16) & 0xf;
b0109805 7365 addr = load_reg(s, rn);
9ee6e8bb
PB		 7366
7367 /* compute total size */
7368 loaded_base = 0;
a50f5b91 7369 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7370 n = 0;
7371 for(i=0;i<16;i++) {
7372 if (insn & (1 << i))
7373 n++;
7374 }
7375 /* XXX: test invalid n == 0 case ? */
7376 if (insn & (1 << 23)) {
7377 if (insn & (1 << 24)) {
7378 /* pre increment */
b0109805 7379 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7380 } else {
7381 /* post increment */
7382 }
7383 } else {
7384 if (insn & (1 << 24)) {
7385 /* pre decrement */
b0109805 7386 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7387 } else {
7388 /* post decrement */
7389 if (n != 1)
b0109805 7390 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7391 }
7392 }
7393 j = 0;
7394 for(i=0;i<16;i++) {
7395 if (insn & (1 << i)) {
7396 if (insn & (1 << 20)) {
7397 /* load */
b0109805 7398 tmp = gen_ld32(addr, IS_USER(s));
be5e7a76 7399 if (user) {
b75263d6
JR		 7400 tmp2 = tcg_const_i32(i);
7401 gen_helper_set_user_reg(tmp2, tmp);
7402 tcg_temp_free_i32(tmp2);
7d1b0095 7403 tcg_temp_free_i32(tmp);
9ee6e8bb 7404 } else if (i == rn) {
b0109805 7405 loaded_var = tmp;
9ee6e8bb
PB		 7406 loaded_base = 1;
7407 } else {
be5e7a76 7408 store_reg_from_load(env, s, i, tmp);
9ee6e8bb
PB		 7409 }
7410 } else {
7411 /* store */
7412 if (i == 15) {
7413 /* special case: r15 = PC + 8 */
7414 val = (long)s->pc + 4;
7d1b0095 7415 tmp = tcg_temp_new_i32();
b0109805 7416 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7417 } else if (user) {
7d1b0095 7418 tmp = tcg_temp_new_i32();
b75263d6
JR		 7419 tmp2 = tcg_const_i32(i);
7420 gen_helper_get_user_reg(tmp, tmp2);
7421 tcg_temp_free_i32(tmp2);
9ee6e8bb 7422 } else {
b0109805 7423 tmp = load_reg(s, i);
9ee6e8bb 7424 }
b0109805 7425 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7426 }
7427 j++;
7428 /* no need to add after the last transfer */
7429 if (j != n)
b0109805 7430 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7431 }
7432 }
7433 if (insn & (1 << 21)) {
7434 /* write back */
7435 if (insn & (1 << 23)) {
7436 if (insn & (1 << 24)) {
7437 /* pre increment */
7438 } else {
7439 /* post increment */
b0109805 7440 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7441 }
7442 } else {
7443 if (insn & (1 << 24)) {
7444 /* pre decrement */
7445 if (n != 1)
b0109805 7446 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7447 } else {
7448 /* post decrement */
b0109805 7449 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7450 }
7451 }
b0109805
PB		 7452 store_reg(s, rn, addr);
7453 } else {
7d1b0095 7454 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7455 }
7456 if (loaded_base) {
b0109805 7457 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7458 }
7459 if ((insn & (1 << 22)) && !user) {
7460 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7461 tmp = load_cpu_field(spsr);
7462 gen_set_cpsr(tmp, 0xffffffff);
7d1b0095 7463 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7464 s->is_jmp = DISAS_UPDATE;
7465 }
7466 }
7467 break;
7468 case 0xa:
7469 case 0xb:
7470 {
7471 int32_t offset;
7472
7473 /* branch (and link) */
7474 val = (int32_t)s->pc;
7475 if (insn & (1 << 24)) {
7d1b0095 7476 tmp = tcg_temp_new_i32();
5e3f878a
PB		 7477 tcg_gen_movi_i32(tmp, val);
7478 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7479 }
7480 offset = (((int32_t)insn << 8) >> 8);
7481 val += (offset << 2) + 4;
7482 gen_jmp(s, val);
7483 }
7484 break;
7485 case 0xc:
7486 case 0xd:
7487 case 0xe:
7488 /* Coprocessor. */
7489 if (disas_coproc_insn(env, s, insn))
7490 goto illegal_op;
7491 break;
7492 case 0xf:
7493 /* swi */
5e3f878a 7494 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7495 s->is_jmp = DISAS_SWI;
7496 break;
7497 default:
7498 illegal_op:
bc4a0de0 7499 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 7500 break;
7501 }
7502 }
7503}
7504
7505/* Return true if this is a Thumb-2 logical op. */
7506static int
7507thumb2_logic_op(int op)
7508{
7509 return (op < 8);
7510}
7511
7512/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7513 then set condition code flags based on the result of the operation.
7514 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7515 to the high bit of T1.
7516 Returns zero if the opcode is valid. */
7517
7518static int
396e467c 7519gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7520{
7521 int logic_cc;
7522
7523 logic_cc = 0;
7524 switch (op) {
7525 case 0: /* and */
396e467c 7526 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7527 logic_cc = conds;
7528 break;
7529 case 1: /* bic */
f669df27 7530 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7531 logic_cc = conds;
7532 break;
7533 case 2: /* orr */
396e467c 7534 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7535 logic_cc = conds;
7536 break;
7537 case 3: /* orn */
29501f1b 7538 tcg_gen_orc_i32(t0, t0, t1);
9ee6e8bb
PB		 7539 logic_cc = conds;
7540 break;
7541 case 4: /* eor */
396e467c 7542 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7543 logic_cc = conds;
7544 break;
7545 case 8: /* add */
7546 if (conds)
396e467c 7547 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7548 else
396e467c 7549 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7550 break;
7551 case 10: /* adc */
7552 if (conds)
396e467c 7553 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7554 else
396e467c 7555 gen_adc(t0, t1);
9ee6e8bb
PB		 7556 break;
7557 case 11: /* sbc */
7558 if (conds)
396e467c 7559 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7560 else
396e467c 7561 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7562 break;
7563 case 13: /* sub */
7564 if (conds)
396e467c 7565 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7566 else
396e467c 7567 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7568 break;
7569 case 14: /* rsb */
7570 if (conds)
396e467c 7571 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7572 else
396e467c 7573 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7574 break;
7575 default: /* 5, 6, 7, 9, 12, 15. */
7576 return 1;
7577 }
7578 if (logic_cc) {
396e467c 7579 gen_logic_CC(t0);
9ee6e8bb 7580 if (shifter_out)
396e467c 7581 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7582 }
7583 return 0;
7584}
7585
7586/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7587 is not legal. */
7588static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7589{
b0109805 7590 uint32_t insn, imm, shift, offset;
9ee6e8bb 7591 uint32_t rd, rn, rm, rs;
b26eefb6 7592 TCGv tmp;
6ddbc6e4
PB		 7593 TCGv tmp2;
7594 TCGv tmp3;
b0109805 7595 TCGv addr;
a7812ae4 7596 TCGv_i64 tmp64;
9ee6e8bb
PB		 7597 int op;
7598 int shiftop;
7599 int conds;
7600 int logic_cc;
7601
7602 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7603 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7604 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7605 16-bit instructions to get correct prefetch abort behavior. */
7606 insn = insn_hw1;
7607 if ((insn & (1 << 12)) == 0) {
be5e7a76 7608 ARCH(5);
9ee6e8bb
PB		 7609 /* Second half of blx. */
7610 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7611 tmp = load_reg(s, 14);
7612 tcg_gen_addi_i32(tmp, tmp, offset);
7613 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7614
7d1b0095 7615 tmp2 = tcg_temp_new_i32();
b0109805 7616 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7617 store_reg(s, 14, tmp2);
7618 gen_bx(s, tmp);
9ee6e8bb
PB		 7619 return 0;
7620 }
7621 if (insn & (1 << 11)) {
7622 /* Second half of bl. */
7623 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7624 tmp = load_reg(s, 14);
6a0d8a1d 7625 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7626
7d1b0095 7627 tmp2 = tcg_temp_new_i32();
b0109805 7628 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7629 store_reg(s, 14, tmp2);
7630 gen_bx(s, tmp);
9ee6e8bb
PB		 7631 return 0;
7632 }
7633 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7634 /* Instruction spans a page boundary. Implement it as two
7635 16-bit instructions in case the second half causes an
7636 prefetch abort. */
7637 offset = ((int32_t)insn << 21) >> 9;
396e467c 7638 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7639 return 0;
7640 }
7641 /* Fall through to 32-bit decode. */
7642 }
7643
7644 insn = lduw_code(s->pc);
7645 s->pc += 2;
7646 insn |= (uint32_t)insn_hw1 << 16;
7647
7648 if ((insn & 0xf800e800) != 0xf000e800) {
7649 ARCH(6T2);
7650 }
7651
7652 rn = (insn >> 16) & 0xf;
7653 rs = (insn >> 12) & 0xf;
7654 rd = (insn >> 8) & 0xf;
7655 rm = insn & 0xf;
7656 switch ((insn >> 25) & 0xf) {
7657 case 0: case 1: case 2: case 3:
7658 /* 16-bit instructions. Should never happen. */
7659 abort();
7660 case 4:
7661 if (insn & (1 << 22)) {
7662 /* Other load/store, table branch. */
7663 if (insn & 0x01200000) {
7664 /* Load/store doubleword. */
7665 if (rn == 15) {
7d1b0095 7666 addr = tcg_temp_new_i32();
b0109805 7667 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7668 } else {
b0109805 7669 addr = load_reg(s, rn);
9ee6e8bb
PB		 7670 }
7671 offset = (insn & 0xff) * 4;
7672 if ((insn & (1 << 23)) == 0)
7673 offset = -offset;
7674 if (insn & (1 << 24)) {
b0109805 7675 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7676 offset = 0;
7677 }
7678 if (insn & (1 << 20)) {
7679 /* ldrd */
b0109805
PB		 7680 tmp = gen_ld32(addr, IS_USER(s));
7681 store_reg(s, rs, tmp);
7682 tcg_gen_addi_i32(addr, addr, 4);
7683 tmp = gen_ld32(addr, IS_USER(s));
7684 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7685 } else {
7686 /* strd */
b0109805
PB		 7687 tmp = load_reg(s, rs);
7688 gen_st32(tmp, addr, IS_USER(s));
7689 tcg_gen_addi_i32(addr, addr, 4);
7690 tmp = load_reg(s, rd);
7691 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7692 }
7693 if (insn & (1 << 21)) {
7694 /* Base writeback. */
7695 if (rn == 15)
7696 goto illegal_op;
b0109805
PB		 7697 tcg_gen_addi_i32(addr, addr, offset - 4);
7698 store_reg(s, rn, addr);
7699 } else {
7d1b0095 7700 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7701 }
7702 } else if ((insn & (1 << 23)) == 0) {
7703 /* Load/store exclusive word. */
3174f8e9 7704 addr = tcg_temp_local_new();
98a46317 7705 load_reg_var(s, addr, rn);
426f5abc 7706 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7707 if (insn & (1 << 20)) {
426f5abc 7708 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7709 } else {
426f5abc 7710 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7711 }
3174f8e9 7712 tcg_temp_free(addr);
9ee6e8bb
PB		 7713 } else if ((insn & (1 << 6)) == 0) {
7714 /* Table Branch. */
7715 if (rn == 15) {
7d1b0095 7716 addr = tcg_temp_new_i32();
b0109805 7717 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7718 } else {
b0109805 7719 addr = load_reg(s, rn);
9ee6e8bb 7720 }
b26eefb6 7721 tmp = load_reg(s, rm);
b0109805 7722 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7723 if (insn & (1 << 4)) {
7724 /* tbh */
b0109805 7725 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 7726 tcg_temp_free_i32(tmp);
b0109805 7727 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7728 } else { /* tbb */
7d1b0095 7729 tcg_temp_free_i32(tmp);
b0109805 7730 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7731 }
7d1b0095 7732 tcg_temp_free_i32(addr);
b0109805
PB		 7733 tcg_gen_shli_i32(tmp, tmp, 1);
7734 tcg_gen_addi_i32(tmp, tmp, s->pc);
7735 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7736 } else {
7737 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7738 ARCH(7);
9ee6e8bb 7739 op = (insn >> 4) & 0x3;
426f5abc
PB		 7740 if (op == 2) {
7741 goto illegal_op;
7742 }
3174f8e9 7743 addr = tcg_temp_local_new();
98a46317 7744 load_reg_var(s, addr, rn);
9ee6e8bb 7745 if (insn & (1 << 20)) {
426f5abc 7746 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7747 } else {
426f5abc 7748 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7749 }
3174f8e9 7750 tcg_temp_free(addr);
9ee6e8bb
PB		 7751 }
7752 } else {
7753 /* Load/store multiple, RFE, SRS. */
7754 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7755 /* Not available in user mode. */
b0109805 7756 if (IS_USER(s))
9ee6e8bb
PB		 7757 goto illegal_op;
7758 if (insn & (1 << 20)) {
7759 /* rfe */
b0109805
PB		 7760 addr = load_reg(s, rn);
7761 if ((insn & (1 << 24)) == 0)
7762 tcg_gen_addi_i32(addr, addr, -8);
7763 /* Load PC into tmp and CPSR into tmp2. */
7764 tmp = gen_ld32(addr, 0);
7765 tcg_gen_addi_i32(addr, addr, 4);
7766 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7767 if (insn & (1 << 21)) {
7768 /* Base writeback. */
b0109805
PB		 7769 if (insn & (1 << 24)) {
7770 tcg_gen_addi_i32(addr, addr, 4);
7771 } else {
7772 tcg_gen_addi_i32(addr, addr, -4);
7773 }
7774 store_reg(s, rn, addr);
7775 } else {
7d1b0095 7776 tcg_temp_free_i32(addr);
9ee6e8bb 7777 }
b0109805 7778 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7779 } else {
7780 /* srs */
7781 op = (insn & 0x1f);
7d1b0095 7782 addr = tcg_temp_new_i32();
39ea3d4e
PM		 7783 tmp = tcg_const_i32(op);
7784 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7785 tcg_temp_free_i32(tmp);
9ee6e8bb 7786 if ((insn & (1 << 24)) == 0) {
b0109805 7787 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7788 }
b0109805
PB		 7789 tmp = load_reg(s, 14);
7790 gen_st32(tmp, addr, 0);
7791 tcg_gen_addi_i32(addr, addr, 4);
7d1b0095 7792 tmp = tcg_temp_new_i32();
b0109805
PB		 7793 gen_helper_cpsr_read(tmp);
7794 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7795 if (insn & (1 << 21)) {
7796 if ((insn & (1 << 24)) == 0) {
b0109805 7797 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7798 } else {
b0109805 7799 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb 7800 }
39ea3d4e
PM		 7801 tmp = tcg_const_i32(op);
7802 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7803 tcg_temp_free_i32(tmp);
b0109805 7804 } else {
7d1b0095 7805 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7806 }
7807 }
7808 } else {
7809 int i;
7810 /* Load/store multiple. */
b0109805 7811 addr = load_reg(s, rn);
9ee6e8bb
PB		 7812 offset = 0;
7813 for (i = 0; i < 16; i++) {
7814 if (insn & (1 << i))
7815 offset += 4;
7816 }
7817 if (insn & (1 << 24)) {
b0109805 7818 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7819 }
7820
7821 for (i = 0; i < 16; i++) {
7822 if ((insn & (1 << i)) == 0)
7823 continue;
7824 if (insn & (1 << 20)) {
7825 /* Load. */
b0109805 7826 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7827 if (i == 15) {
b0109805 7828 gen_bx(s, tmp);
9ee6e8bb 7829 } else {
b0109805 7830 store_reg(s, i, tmp);
9ee6e8bb
PB		 7831 }
7832 } else {
7833 /* Store. */
b0109805
PB		 7834 tmp = load_reg(s, i);
7835 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7836 }
b0109805 7837 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7838 }
7839 if (insn & (1 << 21)) {
7840 /* Base register writeback. */
7841 if (insn & (1 << 24)) {
b0109805 7842 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7843 }
7844 /* Fault if writeback register is in register list. */
7845 if (insn & (1 << rn))
7846 goto illegal_op;
b0109805
PB		 7847 store_reg(s, rn, addr);
7848 } else {
7d1b0095 7849 tcg_temp_free_i32(addr);
9ee6e8bb
PB		 7850 }
7851 }
7852 }
7853 break;
2af9ab77
JB		 7854 case 5:
7855
9ee6e8bb 7856 op = (insn >> 21) & 0xf;
2af9ab77
JB		 7857 if (op == 6) {
7858 /* Halfword pack. */
7859 tmp = load_reg(s, rn);
7860 tmp2 = load_reg(s, rm);
7861 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7862 if (insn & (1 << 5)) {
7863 /* pkhtb */
7864 if (shift == 0)
7865 shift = 31;
7866 tcg_gen_sari_i32(tmp2, tmp2, shift);
7867 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7868 tcg_gen_ext16u_i32(tmp2, tmp2);
7869 } else {
7870 /* pkhbt */
7871 if (shift)
7872 tcg_gen_shli_i32(tmp2, tmp2, shift);
7873 tcg_gen_ext16u_i32(tmp, tmp);
7874 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7875 }
7876 tcg_gen_or_i32(tmp, tmp, tmp2);
7d1b0095 7877 tcg_temp_free_i32(tmp2);
3174f8e9
FN		 7878 store_reg(s, rd, tmp);
7879 } else {
2af9ab77
JB		 7880 /* Data processing register constant shift. */
7881 if (rn == 15) {
7d1b0095 7882 tmp = tcg_temp_new_i32();
2af9ab77
JB		 7883 tcg_gen_movi_i32(tmp, 0);
7884 } else {
7885 tmp = load_reg(s, rn);
7886 }
7887 tmp2 = load_reg(s, rm);
7888
7889 shiftop = (insn >> 4) & 3;
7890 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7891 conds = (insn & (1 << 20)) != 0;
7892 logic_cc = (conds && thumb2_logic_op(op));
7893 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7894 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7895 goto illegal_op;
7d1b0095 7896 tcg_temp_free_i32(tmp2);
2af9ab77
JB		 7897 if (rd != 15) {
7898 store_reg(s, rd, tmp);
7899 } else {
7d1b0095 7900 tcg_temp_free_i32(tmp);
2af9ab77 7901 }
3174f8e9 7902 }
9ee6e8bb
PB		 7903 break;
7904 case 13: /* Misc data processing. */
7905 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7906 if (op < 4 && (insn & 0xf000) != 0xf000)
7907 goto illegal_op;
7908 switch (op) {
7909 case 0: /* Register controlled shift. */
8984bd2e
PB		 7910 tmp = load_reg(s, rn);
7911 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7912 if ((insn & 0x70) != 0)
7913 goto illegal_op;
7914 op = (insn >> 21) & 3;
8984bd2e
PB		 7915 logic_cc = (insn & (1 << 20)) != 0;
7916 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7917 if (logic_cc)
7918 gen_logic_CC(tmp);
21aeb343 7919 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7920 break;
7921 case 1: /* Sign/zero extend. */
5e3f878a 7922 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7923 shift = (insn >> 4) & 3;
7924 /* ??? In many cases it's not neccessary to do a
7925 rotate, a shift is sufficient. */
7926 if (shift != 0)
f669df27 7927 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7928 op = (insn >> 20) & 7;
7929 switch (op) {
5e3f878a
PB		 7930 case 0: gen_sxth(tmp); break;
7931 case 1: gen_uxth(tmp); break;
7932 case 2: gen_sxtb16(tmp); break;
7933 case 3: gen_uxtb16(tmp); break;
7934 case 4: gen_sxtb(tmp); break;
7935 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7936 default: goto illegal_op;
7937 }
7938 if (rn != 15) {
5e3f878a 7939 tmp2 = load_reg(s, rn);
9ee6e8bb 7940 if ((op >> 1) == 1) {
5e3f878a 7941 gen_add16(tmp, tmp2);
9ee6e8bb 7942 } else {
5e3f878a 7943 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 7944 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7945 }
7946 }
5e3f878a 7947 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7948 break;
7949 case 2: /* SIMD add/subtract. */
7950 op = (insn >> 20) & 7;
7951 shift = (insn >> 4) & 7;
7952 if ((op & 3) == 3 || (shift & 3) == 3)
7953 goto illegal_op;
6ddbc6e4
PB		 7954 tmp = load_reg(s, rn);
7955 tmp2 = load_reg(s, rm);
7956 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7d1b0095 7957 tcg_temp_free_i32(tmp2);
6ddbc6e4 7958 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7959 break;
7960 case 3: /* Other data processing. */
7961 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7962 if (op < 4) {
7963 /* Saturating add/subtract. */
d9ba4830
PB		 7964 tmp = load_reg(s, rn);
7965 tmp2 = load_reg(s, rm);
9ee6e8bb 7966 if (op & 1)
4809c612
JB		 7967 gen_helper_double_saturate(tmp, tmp);
7968 if (op & 2)
d9ba4830 7969 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7970 else
d9ba4830 7971 gen_helper_add_saturate(tmp, tmp, tmp2);
7d1b0095 7972 tcg_temp_free_i32(tmp2);
9ee6e8bb 7973 } else {
d9ba4830 7974 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7975 switch (op) {
7976 case 0x0a: /* rbit */
d9ba4830 7977 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7978 break;
7979 case 0x08: /* rev */
66896cb8 7980 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7981 break;
7982 case 0x09: /* rev16 */
d9ba4830 7983 gen_rev16(tmp);
9ee6e8bb
PB		 7984 break;
7985 case 0x0b: /* revsh */
d9ba4830 7986 gen_revsh(tmp);
9ee6e8bb
PB		 7987 break;
7988 case 0x10: /* sel */
d9ba4830 7989 tmp2 = load_reg(s, rm);
7d1b0095 7990 tmp3 = tcg_temp_new_i32();
6ddbc6e4 7991 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7992 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7d1b0095
PM		 7993 tcg_temp_free_i32(tmp3);
7994 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 7995 break;
7996 case 0x18: /* clz */
d9ba4830 7997 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7998 break;
7999 default:
8000 goto illegal_op;
8001 }
8002 }
d9ba4830 8003 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8004 break;
8005 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
8006 op = (insn >> 4) & 0xf;
d9ba4830
PB		 8007 tmp = load_reg(s, rn);
8008 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 8009 switch ((insn >> 20) & 7) {
8010 case 0: /* 32 x 32 -> 32 */
d9ba4830 8011 tcg_gen_mul_i32(tmp, tmp, tmp2);
7d1b0095 8012 tcg_temp_free_i32(tmp2);
9ee6e8bb 8013 if (rs != 15) {
d9ba4830 8014 tmp2 = load_reg(s, rs);
9ee6e8bb 8015 if (op)
d9ba4830 8016 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 8017 else
d9ba4830 8018 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8019 tcg_temp_free_i32(tmp2);
9ee6e8bb 8020 }
9ee6e8bb
PB		 8021 break;
8022 case 1: /* 16 x 16 -> 32 */
d9ba4830 8023 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7d1b0095 8024 tcg_temp_free_i32(tmp2);
9ee6e8bb 8025 if (rs != 15) {
d9ba4830
PB		 8026 tmp2 = load_reg(s, rs);
8027 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 8028 tcg_temp_free_i32(tmp2);
9ee6e8bb 8029 }
9ee6e8bb
PB		 8030 break;
8031 case 2: /* Dual multiply add. */
8032 case 4: /* Dual multiply subtract. */
8033 if (op)
d9ba4830
PB		 8034 gen_swap_half(tmp2);
8035 gen_smul_dual(tmp, tmp2);
9ee6e8bb 8036 if (insn & (1 << 22)) {
e1d177b9 8037 /* This subtraction cannot overflow. */
d9ba4830 8038 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8039 } else {
e1d177b9
PM		 8040 /* This addition cannot overflow 32 bits;
8041 * however it may overflow considered as a signed
8042 * operation, in which case we must set the Q flag.
8043 */
8044 gen_helper_add_setq(tmp, tmp, tmp2);
9ee6e8bb 8045 }
7d1b0095 8046 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8047 if (rs != 15)
8048 {
d9ba4830
PB		 8049 tmp2 = load_reg(s, rs);
8050 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 8051 tcg_temp_free_i32(tmp2);
9ee6e8bb 8052 }
9ee6e8bb
PB		 8053 break;
8054 case 3: /* 32 * 16 -> 32msb */
8055 if (op)
d9ba4830 8056 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 8057 else
d9ba4830 8058 gen_sxth(tmp2);
a7812ae4
PB		 8059 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8060 tcg_gen_shri_i64(tmp64, tmp64, 16);
7d1b0095 8061 tmp = tcg_temp_new_i32();
a7812ae4 8062 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 8063 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 8064 if (rs != 15)
8065 {
d9ba4830
PB		 8066 tmp2 = load_reg(s, rs);
8067 gen_helper_add_setq(tmp, tmp, tmp2);
7d1b0095 8068 tcg_temp_free_i32(tmp2);
9ee6e8bb 8069 }
9ee6e8bb 8070 break;
838fa72d
AJ		 8071 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
8072 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 8073 if (rs != 15) {
838fa72d
AJ		 8074 tmp = load_reg(s, rs);
8075 if (insn & (1 << 20)) {
8076 tmp64 = gen_addq_msw(tmp64, tmp);
99c475ab 8077 } else {
838fa72d 8078 tmp64 = gen_subq_msw(tmp64, tmp);
99c475ab 8079 }
2c0262af 8080 }
838fa72d
AJ		 8081 if (insn & (1 << 4)) {
8082 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
8083 }
8084 tcg_gen_shri_i64(tmp64, tmp64, 32);
7d1b0095 8085 tmp = tcg_temp_new_i32();
838fa72d
AJ		 8086 tcg_gen_trunc_i64_i32(tmp, tmp64);
8087 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 8088 break;
8089 case 7: /* Unsigned sum of absolute differences. */
d9ba4830 8090 gen_helper_usad8(tmp, tmp, tmp2);
7d1b0095 8091 tcg_temp_free_i32(tmp2);
9ee6e8bb 8092 if (rs != 15) {
d9ba4830
PB		 8093 tmp2 = load_reg(s, rs);
8094 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8095 tcg_temp_free_i32(tmp2);
5fd46862 8096 }
9ee6e8bb 8097 break;
2c0262af 8098 }
d9ba4830 8099 store_reg(s, rd, tmp);
2c0262af 8100 break;
9ee6e8bb
PB		 8101 case 6: case 7: /* 64-bit multiply, Divide. */
8102 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 8103 tmp = load_reg(s, rn);
8104 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 8105 if ((op & 0x50) == 0x10) {
8106 /* sdiv, udiv */
8107 if (!arm_feature(env, ARM_FEATURE_DIV))
8108 goto illegal_op;
8109 if (op & 0x20)
5e3f878a 8110 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 8111 else
5e3f878a 8112 gen_helper_sdiv(tmp, tmp, tmp2);
7d1b0095 8113 tcg_temp_free_i32(tmp2);
5e3f878a 8114 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8115 } else if ((op & 0xe) == 0xc) {
8116 /* Dual multiply accumulate long. */
8117 if (op & 1)
5e3f878a
PB		 8118 gen_swap_half(tmp2);
8119 gen_smul_dual(tmp, tmp2);
9ee6e8bb 8120 if (op & 0x10) {
5e3f878a 8121 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 8122 } else {
5e3f878a 8123 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 8124 }
7d1b0095 8125 tcg_temp_free_i32(tmp2);
a7812ae4
PB		 8126 /* BUGFIX */
8127 tmp64 = tcg_temp_new_i64();
8128 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 8129 tcg_temp_free_i32(tmp);
a7812ae4
PB		 8130 gen_addq(s, tmp64, rs, rd);
8131 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 8132 tcg_temp_free_i64(tmp64);
2c0262af 8133 } else {
9ee6e8bb
PB		 8134 if (op & 0x20) {
8135 /* Unsigned 64-bit multiply */
a7812ae4 8136 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 8137 } else {
9ee6e8bb
PB		 8138 if (op & 8) {
8139 /* smlalxy */
5e3f878a 8140 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7d1b0095 8141 tcg_temp_free_i32(tmp2);
a7812ae4
PB		 8142 tmp64 = tcg_temp_new_i64();
8143 tcg_gen_ext_i32_i64(tmp64, tmp);
7d1b0095 8144 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8145 } else {
8146 /* Signed 64-bit multiply */
a7812ae4 8147 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 8148 }
b5ff1b31 8149 }
9ee6e8bb
PB		 8150 if (op & 4) {
8151 /* umaal */
a7812ae4
PB		 8152 gen_addq_lo(s, tmp64, rs);
8153 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 8154 } else if (op & 0x40) {
8155 /* 64-bit accumulate. */
a7812ae4 8156 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 8157 }
a7812ae4 8158 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 8159 tcg_temp_free_i64(tmp64);
5fd46862 8160 }
2c0262af 8161 break;
9ee6e8bb
PB		 8162 }
8163 break;
8164 case 6: case 7: case 14: case 15:
8165 /* Coprocessor. */
8166 if (((insn >> 24) & 3) == 3) {
8167 /* Translate into the equivalent ARM encoding. */
f06053e3 8168 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
9ee6e8bb
PB		 8169 if (disas_neon_data_insn(env, s, insn))
8170 goto illegal_op;
8171 } else {
8172 if (insn & (1 << 28))
8173 goto illegal_op;
8174 if (disas_coproc_insn (env, s, insn))
8175 goto illegal_op;
8176 }
8177 break;
8178 case 8: case 9: case 10: case 11:
8179 if (insn & (1 << 15)) {
8180 /* Branches, misc control. */
8181 if (insn & 0x5000) {
8182 /* Unconditional branch. */
8183 /* signextend(hw1[10:0]) -> offset[:12]. */
8184 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8185 /* hw1[10:0] -> offset[11:1]. */
8186 offset |= (insn & 0x7ff) << 1;
8187 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8188 offset[24:22] already have the same value because of the
8189 sign extension above. */
8190 offset ^= ((~insn) & (1 << 13)) << 10;
8191 offset ^= ((~insn) & (1 << 11)) << 11;
8192
9ee6e8bb
PB		 8193 if (insn & (1 << 14)) {
8194 /* Branch and link. */
3174f8e9 8195 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 8196 }
3b46e624 8197
b0109805 8198 offset += s->pc;
9ee6e8bb
PB		 8199 if (insn & (1 << 12)) {
8200 /* b/bl */
b0109805 8201 gen_jmp(s, offset);
9ee6e8bb
PB		 8202 } else {
8203 /* blx */
b0109805 8204 offset &= ~(uint32_t)2;
be5e7a76 8205 /* thumb2 bx, no need to check */
b0109805 8206 gen_bx_im(s, offset);
2c0262af 8207 }
9ee6e8bb
PB		 8208 } else if (((insn >> 23) & 7) == 7) {
8209 /* Misc control */
8210 if (insn & (1 << 13))
8211 goto illegal_op;
8212
8213 if (insn & (1 << 26)) {
8214 /* Secure monitor call (v6Z) */
8215 goto illegal_op; /* not implemented. */
2c0262af 8216 } else {
9ee6e8bb
PB		 8217 op = (insn >> 20) & 7;
8218 switch (op) {
8219 case 0: /* msr cpsr. */
8220 if (IS_M(env)) {
8984bd2e
PB		 8221 tmp = load_reg(s, rn);
8222 addr = tcg_const_i32(insn & 0xff);
8223 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8224 tcg_temp_free_i32(addr);
7d1b0095 8225 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8226 gen_lookup_tb(s);
8227 break;
8228 }
8229 /* fall through */
8230 case 1: /* msr spsr. */
8231 if (IS_M(env))
8232 goto illegal_op;
2fbac54b
FN		 8233 tmp = load_reg(s, rn);
8234 if (gen_set_psr(s,
9ee6e8bb 8235 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 8236 op == 1, tmp))
9ee6e8bb
PB		 8237 goto illegal_op;
8238 break;
8239 case 2: /* cps, nop-hint. */
8240 if (((insn >> 8) & 7) == 0) {
8241 gen_nop_hint(s, insn & 0xff);
8242 }
8243 /* Implemented as NOP in user mode. */
8244 if (IS_USER(s))
8245 break;
8246 offset = 0;
8247 imm = 0;
8248 if (insn & (1 << 10)) {
8249 if (insn & (1 << 7))
8250 offset |= CPSR_A;
8251 if (insn & (1 << 6))
8252 offset |= CPSR_I;
8253 if (insn & (1 << 5))
8254 offset |= CPSR_F;
8255 if (insn & (1 << 9))
8256 imm = CPSR_A | CPSR_I | CPSR_F;
8257 }
8258 if (insn & (1 << 8)) {
8259 offset |= 0x1f;
8260 imm |= (insn & 0x1f);
8261 }
8262 if (offset) {
2fbac54b 8263 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 8264 }
8265 break;
8266 case 3: /* Special control operations. */
426f5abc 8267 ARCH(7);
9ee6e8bb
PB		 8268 op = (insn >> 4) & 0xf;
8269 switch (op) {
8270 case 2: /* clrex */
426f5abc 8271 gen_clrex(s);
9ee6e8bb
PB		 8272 break;
8273 case 4: /* dsb */
8274 case 5: /* dmb */
8275 case 6: /* isb */
8276 /* These execute as NOPs. */
9ee6e8bb
PB		 8277 break;
8278 default:
8279 goto illegal_op;
8280 }
8281 break;
8282 case 4: /* bxj */
8283 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8284 tmp = load_reg(s, rn);
8285 gen_bx(s, tmp);
9ee6e8bb
PB		 8286 break;
8287 case 5: /* Exception return. */
b8b45b68
RV		 8288 if (IS_USER(s)) {
8289 goto illegal_op;
8290 }
8291 if (rn != 14 || rd != 15) {
8292 goto illegal_op;
8293 }
8294 tmp = load_reg(s, rn);
8295 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8296 gen_exception_return(s, tmp);
8297 break;
9ee6e8bb 8298 case 6: /* mrs cpsr. */
7d1b0095 8299 tmp = tcg_temp_new_i32();
9ee6e8bb 8300 if (IS_M(env)) {
8984bd2e
PB		 8301 addr = tcg_const_i32(insn & 0xff);
8302 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8303 tcg_temp_free_i32(addr);
9ee6e8bb 8304 } else {
8984bd2e 8305 gen_helper_cpsr_read(tmp);
9ee6e8bb 8306 }
8984bd2e 8307 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8308 break;
8309 case 7: /* mrs spsr. */
8310 /* Not accessible in user mode. */
8311 if (IS_USER(s) || IS_M(env))
8312 goto illegal_op;
d9ba4830
PB		 8313 tmp = load_cpu_field(spsr);
8314 store_reg(s, rd, tmp);
9ee6e8bb 8315 break;
2c0262af
FB		 8316 }
8317 }
9ee6e8bb
PB		 8318 } else {
8319 /* Conditional branch. */
8320 op = (insn >> 22) & 0xf;
8321 /* Generate a conditional jump to next instruction. */
8322 s->condlabel = gen_new_label();
d9ba4830 8323 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8324 s->condjmp = 1;
8325
8326 /* offset[11:1] = insn[10:0] */
8327 offset = (insn & 0x7ff) << 1;
8328 /* offset[17:12] = insn[21:16]. */
8329 offset |= (insn & 0x003f0000) >> 4;
8330 /* offset[31:20] = insn[26]. */
8331 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8332 /* offset[18] = insn[13]. */
8333 offset |= (insn & (1 << 13)) << 5;
8334 /* offset[19] = insn[11]. */
8335 offset |= (insn & (1 << 11)) << 8;
8336
8337 /* jump to the offset */
b0109805 8338 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8339 }
8340 } else {
8341 /* Data processing immediate. */
8342 if (insn & (1 << 25)) {
8343 if (insn & (1 << 24)) {
8344 if (insn & (1 << 20))
8345 goto illegal_op;
8346 /* Bitfield/Saturate. */
8347 op = (insn >> 21) & 7;
8348 imm = insn & 0x1f;
8349 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4 8350 if (rn == 15) {
7d1b0095 8351 tmp = tcg_temp_new_i32();
6ddbc6e4
PB		 8352 tcg_gen_movi_i32(tmp, 0);
8353 } else {
8354 tmp = load_reg(s, rn);
8355 }
9ee6e8bb
PB		 8356 switch (op) {
8357 case 2: /* Signed bitfield extract. */
8358 imm++;
8359 if (shift + imm > 32)
8360 goto illegal_op;
8361 if (imm < 32)
6ddbc6e4 8362 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8363 break;
8364 case 6: /* Unsigned bitfield extract. */
8365 imm++;
8366 if (shift + imm > 32)
8367 goto illegal_op;
8368 if (imm < 32)
6ddbc6e4 8369 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8370 break;
8371 case 3: /* Bitfield insert/clear. */
8372 if (imm < shift)
8373 goto illegal_op;
8374 imm = imm + 1 - shift;
8375 if (imm != 32) {
6ddbc6e4 8376 tmp2 = load_reg(s, rd);
8f8e3aa4 8377 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
7d1b0095 8378 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8379 }
8380 break;
8381 case 7:
8382 goto illegal_op;
8383 default: /* Saturate. */
9ee6e8bb
PB		 8384 if (shift) {
8385 if (op & 1)
6ddbc6e4 8386 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8387 else
6ddbc6e4 8388 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8389 }
6ddbc6e4 8390 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8391 if (op & 4) {
8392 /* Unsigned. */
9ee6e8bb 8393 if ((op & 1) && shift == 0)
6ddbc6e4 8394 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8395 else
6ddbc6e4 8396 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8397 } else {
9ee6e8bb 8398 /* Signed. */
9ee6e8bb 8399 if ((op & 1) && shift == 0)
6ddbc6e4 8400 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8401 else
6ddbc6e4 8402 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8403 }
b75263d6 8404 tcg_temp_free_i32(tmp2);
9ee6e8bb 8405 break;
2c0262af 8406 }
6ddbc6e4 8407 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8408 } else {
8409 imm = ((insn & 0x04000000) >> 15)
8410 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8411 if (insn & (1 << 22)) {
8412 /* 16-bit immediate. */
8413 imm |= (insn >> 4) & 0xf000;
8414 if (insn & (1 << 23)) {
8415 /* movt */
5e3f878a 8416 tmp = load_reg(s, rd);
86831435 8417 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8418 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8419 } else {
9ee6e8bb 8420 /* movw */
7d1b0095 8421 tmp = tcg_temp_new_i32();
5e3f878a 8422 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8423 }
8424 } else {
9ee6e8bb
PB		 8425 /* Add/sub 12-bit immediate. */
8426 if (rn == 15) {
b0109805 8427 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8428 if (insn & (1 << 23))
b0109805 8429 offset -= imm;
9ee6e8bb 8430 else
b0109805 8431 offset += imm;
7d1b0095 8432 tmp = tcg_temp_new_i32();
5e3f878a 8433 tcg_gen_movi_i32(tmp, offset);
2c0262af 8434 } else {
5e3f878a 8435 tmp = load_reg(s, rn);
9ee6e8bb 8436 if (insn & (1 << 23))
5e3f878a 8437 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8438 else
5e3f878a 8439 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8440 }
9ee6e8bb 8441 }
5e3f878a 8442 store_reg(s, rd, tmp);
191abaa2 8443 }
9ee6e8bb
PB		 8444 } else {
8445 int shifter_out = 0;
8446 /* modified 12-bit immediate. */
8447 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8448 imm = (insn & 0xff);
8449 switch (shift) {
8450 case 0: /* XY */
8451 /* Nothing to do. */
8452 break;
8453 case 1: /* 00XY00XY */
8454 imm |= imm << 16;
8455 break;
8456 case 2: /* XY00XY00 */
8457 imm |= imm << 16;
8458 imm <<= 8;
8459 break;
8460 case 3: /* XYXYXYXY */
8461 imm |= imm << 16;
8462 imm |= imm << 8;
8463 break;
8464 default: /* Rotated constant. */
8465 shift = (shift << 1) | (imm >> 7);
8466 imm |= 0x80;
8467 imm = imm << (32 - shift);
8468 shifter_out = 1;
8469 break;
b5ff1b31 8470 }
7d1b0095 8471 tmp2 = tcg_temp_new_i32();
3174f8e9 8472 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8473 rn = (insn >> 16) & 0xf;
3174f8e9 8474 if (rn == 15) {
7d1b0095 8475 tmp = tcg_temp_new_i32();
3174f8e9
FN		 8476 tcg_gen_movi_i32(tmp, 0);
8477 } else {
8478 tmp = load_reg(s, rn);
8479 }
9ee6e8bb
PB		 8480 op = (insn >> 21) & 0xf;
8481 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8482 shifter_out, tmp, tmp2))
9ee6e8bb 8483 goto illegal_op;
7d1b0095 8484 tcg_temp_free_i32(tmp2);
9ee6e8bb
PB		 8485 rd = (insn >> 8) & 0xf;
8486 if (rd != 15) {
3174f8e9
FN		 8487 store_reg(s, rd, tmp);
8488 } else {
7d1b0095 8489 tcg_temp_free_i32(tmp);
2c0262af 8490 }
2c0262af 8491 }
9ee6e8bb
PB		 8492 }
8493 break;
8494 case 12: /* Load/store single data item. */
8495 {
8496 int postinc = 0;
8497 int writeback = 0;
b0109805 8498 int user;
9ee6e8bb
PB		 8499 if ((insn & 0x01100000) == 0x01000000) {
8500 if (disas_neon_ls_insn(env, s, insn))
c1713132 8501 goto illegal_op;
9ee6e8bb
PB		 8502 break;
8503 }
a2fdc890
PM		 8504 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8505 if (rs == 15) {
8506 if (!(insn & (1 << 20))) {
8507 goto illegal_op;
8508 }
8509 if (op != 2) {
8510 /* Byte or halfword load space with dest == r15 : memory hints.
8511 * Catch them early so we don't emit pointless addressing code.
8512 * This space is a mix of:
8513 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8514 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8515 * cores)
8516 * unallocated hints, which must be treated as NOPs
8517 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8518 * which is easiest for the decoding logic
8519 * Some space which must UNDEF
8520 */
8521 int op1 = (insn >> 23) & 3;
8522 int op2 = (insn >> 6) & 0x3f;
8523 if (op & 2) {
8524 goto illegal_op;
8525 }
8526 if (rn == 15) {
8527 /* UNPREDICTABLE or unallocated hint */
8528 return 0;
8529 }
8530 if (op1 & 1) {
8531 return 0; /* PLD* or unallocated hint */
8532 }
8533 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8534 return 0; /* PLD* or unallocated hint */
8535 }
8536 /* UNDEF space, or an UNPREDICTABLE */
8537 return 1;
8538 }
8539 }
b0109805 8540 user = IS_USER(s);
9ee6e8bb 8541 if (rn == 15) {
7d1b0095 8542 addr = tcg_temp_new_i32();
9ee6e8bb
PB		 8543 /* PC relative. */
8544 /* s->pc has already been incremented by 4. */
8545 imm = s->pc & 0xfffffffc;
8546 if (insn & (1 << 23))
8547 imm += insn & 0xfff;
8548 else
8549 imm -= insn & 0xfff;
b0109805 8550 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8551 } else {
b0109805 8552 addr = load_reg(s, rn);
9ee6e8bb
PB		 8553 if (insn & (1 << 23)) {
8554 /* Positive offset. */
8555 imm = insn & 0xfff;
b0109805 8556 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb 8557 } else {
9ee6e8bb 8558 imm = insn & 0xff;
2a0308c5
PM		 8559 switch ((insn >> 8) & 0xf) {
8560 case 0x0: /* Shifted Register. */
9ee6e8bb 8561 shift = (insn >> 4) & 0xf;
2a0308c5
PM		 8562 if (shift > 3) {
8563 tcg_temp_free_i32(addr);
18c9b560 8564 goto illegal_op;
2a0308c5 8565 }
b26eefb6 8566 tmp = load_reg(s, rm);
9ee6e8bb 8567 if (shift)
b26eefb6 8568 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8569 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 8570 tcg_temp_free_i32(tmp);
9ee6e8bb 8571 break;
2a0308c5 8572 case 0xc: /* Negative offset. */
b0109805 8573 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb 8574 break;
2a0308c5 8575 case 0xe: /* User privilege. */
b0109805
PB		 8576 tcg_gen_addi_i32(addr, addr, imm);
8577 user = 1;
9ee6e8bb 8578 break;
2a0308c5 8579 case 0x9: /* Post-decrement. */
9ee6e8bb
PB		 8580 imm = -imm;
8581 /* Fall through. */
2a0308c5 8582 case 0xb: /* Post-increment. */
9ee6e8bb
PB		 8583 postinc = 1;
8584 writeback = 1;
8585 break;
2a0308c5 8586 case 0xd: /* Pre-decrement. */
9ee6e8bb
PB		 8587 imm = -imm;
8588 /* Fall through. */
2a0308c5 8589 case 0xf: /* Pre-increment. */
b0109805 8590 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8591 writeback = 1;
8592 break;
8593 default:
2a0308c5 8594 tcg_temp_free_i32(addr);
b7bcbe95 8595 goto illegal_op;
9ee6e8bb
PB		 8596 }
8597 }
8598 }
9ee6e8bb
PB		 8599 if (insn & (1 << 20)) {
8600 /* Load. */
a2fdc890
PM		 8601 switch (op) {
8602 case 0: tmp = gen_ld8u(addr, user); break;
8603 case 4: tmp = gen_ld8s(addr, user); break;
8604 case 1: tmp = gen_ld16u(addr, user); break;
8605 case 5: tmp = gen_ld16s(addr, user); break;
8606 case 2: tmp = gen_ld32(addr, user); break;
2a0308c5
PM		 8607 default:
8608 tcg_temp_free_i32(addr);
8609 goto illegal_op;
a2fdc890
PM		 8610 }
8611 if (rs == 15) {
8612 gen_bx(s, tmp);
9ee6e8bb 8613 } else {
a2fdc890 8614 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8615 }
8616 } else {
8617 /* Store. */
b0109805 8618 tmp = load_reg(s, rs);
9ee6e8bb 8619 switch (op) {
b0109805
PB		 8620 case 0: gen_st8(tmp, addr, user); break;
8621 case 1: gen_st16(tmp, addr, user); break;
8622 case 2: gen_st32(tmp, addr, user); break;
2a0308c5
PM		 8623 default:
8624 tcg_temp_free_i32(addr);
8625 goto illegal_op;
b7bcbe95 8626 }
2c0262af 8627 }
9ee6e8bb 8628 if (postinc)
b0109805
PB		 8629 tcg_gen_addi_i32(addr, addr, imm);
8630 if (writeback) {
8631 store_reg(s, rn, addr);
8632 } else {
7d1b0095 8633 tcg_temp_free_i32(addr);
b0109805 8634 }
9ee6e8bb
PB		 8635 }
8636 break;
8637 default:
8638 goto illegal_op;
2c0262af 8639 }
9ee6e8bb
PB		 8640 return 0;
8641illegal_op:
8642 return 1;
2c0262af
FB		 8643}
8644
9ee6e8bb 8645static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8646{
8647 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8648 int32_t offset;
8649 int i;
b26eefb6 8650 TCGv tmp;
d9ba4830 8651 TCGv tmp2;
b0109805 8652 TCGv addr;
99c475ab 8653
9ee6e8bb
PB		 8654 if (s->condexec_mask) {
8655 cond = s->condexec_cond;
bedd2912
JB		 8656 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8657 s->condlabel = gen_new_label();
8658 gen_test_cc(cond ^ 1, s->condlabel);
8659 s->condjmp = 1;
8660 }
9ee6e8bb
PB		 8661 }
8662
b5ff1b31 8663 insn = lduw_code(s->pc);
99c475ab 8664 s->pc += 2;
b5ff1b31 8665
99c475ab
FB		 8666 switch (insn >> 12) {
8667 case 0: case 1:
396e467c 8668
99c475ab
FB		 8669 rd = insn & 7;
8670 op = (insn >> 11) & 3;
8671 if (op == 3) {
8672 /* add/subtract */
8673 rn = (insn >> 3) & 7;
396e467c 8674 tmp = load_reg(s, rn);
99c475ab
FB		 8675 if (insn & (1 << 10)) {
8676 /* immediate */
7d1b0095 8677 tmp2 = tcg_temp_new_i32();
396e467c 8678 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8679 } else {
8680 /* reg */
8681 rm = (insn >> 6) & 7;
396e467c 8682 tmp2 = load_reg(s, rm);
99c475ab 8683 }
9ee6e8bb
PB		 8684 if (insn & (1 << 9)) {
8685 if (s->condexec_mask)
396e467c 8686 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8687 else
396e467c 8688 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8689 } else {
8690 if (s->condexec_mask)
396e467c 8691 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8692 else
396e467c 8693 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8694 }
7d1b0095 8695 tcg_temp_free_i32(tmp2);
396e467c 8696 store_reg(s, rd, tmp);
99c475ab
FB		 8697 } else {
8698 /* shift immediate */
8699 rm = (insn >> 3) & 7;
8700 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8701 tmp = load_reg(s, rm);
8702 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8703 if (!s->condexec_mask)
8704 gen_logic_CC(tmp);
8705 store_reg(s, rd, tmp);
99c475ab
FB		 8706 }
8707 break;
8708 case 2: case 3:
8709 /* arithmetic large immediate */
8710 op = (insn >> 11) & 3;
8711 rd = (insn >> 8) & 0x7;
396e467c 8712 if (op == 0) { /* mov */
7d1b0095 8713 tmp = tcg_temp_new_i32();
396e467c 8714 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8715 if (!s->condexec_mask)
396e467c
FN		 8716 gen_logic_CC(tmp);
8717 store_reg(s, rd, tmp);
8718 } else {
8719 tmp = load_reg(s, rd);
7d1b0095 8720 tmp2 = tcg_temp_new_i32();
396e467c
FN		 8721 tcg_gen_movi_i32(tmp2, insn & 0xff);
8722 switch (op) {
8723 case 1: /* cmp */
8724 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095
PM		 8725 tcg_temp_free_i32(tmp);
8726 tcg_temp_free_i32(tmp2);
396e467c
FN		 8727 break;
8728 case 2: /* add */
8729 if (s->condexec_mask)
8730 tcg_gen_add_i32(tmp, tmp, tmp2);
8731 else
8732 gen_helper_add_cc(tmp, tmp, tmp2);
7d1b0095 8733 tcg_temp_free_i32(tmp2);
396e467c
FN		 8734 store_reg(s, rd, tmp);
8735 break;
8736 case 3: /* sub */
8737 if (s->condexec_mask)
8738 tcg_gen_sub_i32(tmp, tmp, tmp2);
8739 else
8740 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095 8741 tcg_temp_free_i32(tmp2);
396e467c
FN		 8742 store_reg(s, rd, tmp);
8743 break;
8744 }
99c475ab 8745 }
99c475ab
FB		 8746 break;
8747 case 4:
8748 if (insn & (1 << 11)) {
8749 rd = (insn >> 8) & 7;
5899f386
FB		 8750 /* load pc-relative. Bit 1 of PC is ignored. */
8751 val = s->pc + 2 + ((insn & 0xff) * 4);
8752 val &= ~(uint32_t)2;
7d1b0095 8753 addr = tcg_temp_new_i32();
b0109805
PB		 8754 tcg_gen_movi_i32(addr, val);
8755 tmp = gen_ld32(addr, IS_USER(s));
7d1b0095 8756 tcg_temp_free_i32(addr);
b0109805 8757 store_reg(s, rd, tmp);
99c475ab
FB		 8758 break;
8759 }
8760 if (insn & (1 << 10)) {
8761 /* data processing extended or blx */
8762 rd = (insn & 7) | ((insn >> 4) & 8);
8763 rm = (insn >> 3) & 0xf;
8764 op = (insn >> 8) & 3;
8765 switch (op) {
8766 case 0: /* add */
396e467c
FN		 8767 tmp = load_reg(s, rd);
8768 tmp2 = load_reg(s, rm);
8769 tcg_gen_add_i32(tmp, tmp, tmp2);
7d1b0095 8770 tcg_temp_free_i32(tmp2);
396e467c 8771 store_reg(s, rd, tmp);
99c475ab
FB		 8772 break;
8773 case 1: /* cmp */
396e467c
FN		 8774 tmp = load_reg(s, rd);
8775 tmp2 = load_reg(s, rm);
8776 gen_helper_sub_cc(tmp, tmp, tmp2);
7d1b0095
PM		 8777 tcg_temp_free_i32(tmp2);
8778 tcg_temp_free_i32(tmp);
99c475ab
FB		 8779 break;
8780 case 2: /* mov/cpy */
396e467c
FN		 8781 tmp = load_reg(s, rm);
8782 store_reg(s, rd, tmp);
99c475ab
FB		 8783 break;
8784 case 3:/* branch [and link] exchange thumb register */
b0109805 8785 tmp = load_reg(s, rm);
99c475ab 8786 if (insn & (1 << 7)) {
be5e7a76 8787 ARCH(5);
99c475ab 8788 val = (uint32_t)s->pc | 1;
7d1b0095 8789 tmp2 = tcg_temp_new_i32();
b0109805
PB		 8790 tcg_gen_movi_i32(tmp2, val);
8791 store_reg(s, 14, tmp2);
99c475ab 8792 }
be5e7a76 8793 /* already thumb, no need to check */
d9ba4830 8794 gen_bx(s, tmp);
99c475ab
FB		 8795 break;
8796 }
8797 break;
8798 }
8799
8800 /* data processing register */
8801 rd = insn & 7;
8802 rm = (insn >> 3) & 7;
8803 op = (insn >> 6) & 0xf;
8804 if (op == 2 || op == 3 || op == 4 || op == 7) {
8805 /* the shift/rotate ops want the operands backwards */
8806 val = rm;
8807 rm = rd;
8808 rd = val;
8809 val = 1;
8810 } else {
8811 val = 0;
8812 }
8813
396e467c 8814 if (op == 9) { /* neg */
7d1b0095 8815 tmp = tcg_temp_new_i32();
396e467c
FN		 8816 tcg_gen_movi_i32(tmp, 0);
8817 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8818 tmp = load_reg(s, rd);
8819 } else {
8820 TCGV_UNUSED(tmp);
8821 }
99c475ab 8822
396e467c 8823 tmp2 = load_reg(s, rm);
5899f386 8824 switch (op) {
99c475ab 8825 case 0x0: /* and */
396e467c 8826 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8827 if (!s->condexec_mask)
396e467c 8828 gen_logic_CC(tmp);
99c475ab
FB		 8829 break;
8830 case 0x1: /* eor */
396e467c 8831 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8832 if (!s->condexec_mask)
396e467c 8833 gen_logic_CC(tmp);
99c475ab
FB		 8834 break;
8835 case 0x2: /* lsl */
9ee6e8bb 8836 if (s->condexec_mask) {
396e467c 8837 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8838 } else {
396e467c
FN		 8839 gen_helper_shl_cc(tmp2, tmp2, tmp);
8840 gen_logic_CC(tmp2);
9ee6e8bb 8841 }
99c475ab
FB		 8842 break;
8843 case 0x3: /* lsr */
9ee6e8bb 8844 if (s->condexec_mask) {
396e467c 8845 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8846 } else {
396e467c
FN		 8847 gen_helper_shr_cc(tmp2, tmp2, tmp);
8848 gen_logic_CC(tmp2);
9ee6e8bb 8849 }
99c475ab
FB		 8850 break;
8851 case 0x4: /* asr */
9ee6e8bb 8852 if (s->condexec_mask) {
396e467c 8853 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8854 } else {
396e467c
FN		 8855 gen_helper_sar_cc(tmp2, tmp2, tmp);
8856 gen_logic_CC(tmp2);
9ee6e8bb 8857 }
99c475ab
FB		 8858 break;
8859 case 0x5: /* adc */
9ee6e8bb 8860 if (s->condexec_mask)
396e467c 8861 gen_adc(tmp, tmp2);
9ee6e8bb 8862 else
396e467c 8863 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8864 break;
8865 case 0x6: /* sbc */
9ee6e8bb 8866 if (s->condexec_mask)
396e467c 8867 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8868 else
396e467c 8869 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8870 break;
8871 case 0x7: /* ror */
9ee6e8bb 8872 if (s->condexec_mask) {
f669df27
AJ		 8873 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8874 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8875 } else {
396e467c
FN		 8876 gen_helper_ror_cc(tmp2, tmp2, tmp);
8877 gen_logic_CC(tmp2);
9ee6e8bb 8878 }
99c475ab
FB		 8879 break;
8880 case 0x8: /* tst */
396e467c
FN		 8881 tcg_gen_and_i32(tmp, tmp, tmp2);
8882 gen_logic_CC(tmp);
99c475ab 8883 rd = 16;
5899f386 8884 break;
99c475ab 8885 case 0x9: /* neg */
9ee6e8bb 8886 if (s->condexec_mask)
396e467c 8887 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8888 else
396e467c 8889 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8890 break;
8891 case 0xa: /* cmp */
396e467c 8892 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8893 rd = 16;
8894 break;
8895 case 0xb: /* cmn */
396e467c 8896 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8897 rd = 16;
8898 break;
8899 case 0xc: /* orr */
396e467c 8900 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8901 if (!s->condexec_mask)
396e467c 8902 gen_logic_CC(tmp);
99c475ab
FB		 8903 break;
8904 case 0xd: /* mul */
7b2919a0 8905 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8906 if (!s->condexec_mask)
396e467c 8907 gen_logic_CC(tmp);
99c475ab
FB		 8908 break;
8909 case 0xe: /* bic */
f669df27 8910 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8911 if (!s->condexec_mask)
396e467c 8912 gen_logic_CC(tmp);
99c475ab
FB		 8913 break;
8914 case 0xf: /* mvn */
396e467c 8915 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8916 if (!s->condexec_mask)
396e467c 8917 gen_logic_CC(tmp2);
99c475ab 8918 val = 1;
5899f386 8919 rm = rd;
99c475ab
FB		 8920 break;
8921 }
8922 if (rd != 16) {
396e467c
FN		 8923 if (val) {
8924 store_reg(s, rm, tmp2);
8925 if (op != 0xf)
7d1b0095 8926 tcg_temp_free_i32(tmp);
396e467c
FN		 8927 } else {
8928 store_reg(s, rd, tmp);
7d1b0095 8929 tcg_temp_free_i32(tmp2);
396e467c
FN		 8930 }
8931 } else {
7d1b0095
PM		 8932 tcg_temp_free_i32(tmp);
8933 tcg_temp_free_i32(tmp2);
99c475ab
FB		 8934 }
8935 break;
8936
8937 case 5:
8938 /* load/store register offset. */
8939 rd = insn & 7;
8940 rn = (insn >> 3) & 7;
8941 rm = (insn >> 6) & 7;
8942 op = (insn >> 9) & 7;
b0109805 8943 addr = load_reg(s, rn);
b26eefb6 8944 tmp = load_reg(s, rm);
b0109805 8945 tcg_gen_add_i32(addr, addr, tmp);
7d1b0095 8946 tcg_temp_free_i32(tmp);
99c475ab
FB		 8947
8948 if (op < 3) /* store */
b0109805 8949 tmp = load_reg(s, rd);
99c475ab
FB		 8950
8951 switch (op) {
8952 case 0: /* str */
b0109805 8953 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8954 break;
8955 case 1: /* strh */
b0109805 8956 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8957 break;
8958 case 2: /* strb */
b0109805 8959 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8960 break;
8961 case 3: /* ldrsb */
b0109805 8962 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8963 break;
8964 case 4: /* ldr */
b0109805 8965 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8966 break;
8967 case 5: /* ldrh */
b0109805 8968 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8969 break;
8970 case 6: /* ldrb */
b0109805 8971 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8972 break;
8973 case 7: /* ldrsh */
b0109805 8974 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8975 break;
8976 }
8977 if (op >= 3) /* load */
b0109805 8978 store_reg(s, rd, tmp);
7d1b0095 8979 tcg_temp_free_i32(addr);
99c475ab
FB		 8980 break;
8981
8982 case 6:
8983 /* load/store word immediate offset */
8984 rd = insn & 7;
8985 rn = (insn >> 3) & 7;
b0109805 8986 addr = load_reg(s, rn);
99c475ab 8987 val = (insn >> 4) & 0x7c;
b0109805 8988 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8989
8990 if (insn & (1 << 11)) {
8991 /* load */
b0109805
PB		 8992 tmp = gen_ld32(addr, IS_USER(s));
8993 store_reg(s, rd, tmp);
99c475ab
FB		 8994 } else {
8995 /* store */
b0109805
PB		 8996 tmp = load_reg(s, rd);
8997 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8998 }
7d1b0095 8999 tcg_temp_free_i32(addr);
99c475ab
FB		 9000 break;
9001
9002 case 7:
9003 /* load/store byte immediate offset */
9004 rd = insn & 7;
9005 rn = (insn >> 3) & 7;
b0109805 9006 addr = load_reg(s, rn);
99c475ab 9007 val = (insn >> 6) & 0x1f;
b0109805 9008 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 9009
9010 if (insn & (1 << 11)) {
9011 /* load */
b0109805
PB		 9012 tmp = gen_ld8u(addr, IS_USER(s));
9013 store_reg(s, rd, tmp);
99c475ab
FB		 9014 } else {
9015 /* store */
b0109805
PB		 9016 tmp = load_reg(s, rd);
9017 gen_st8(tmp, addr, IS_USER(s));
99c475ab 9018 }
7d1b0095 9019 tcg_temp_free_i32(addr);
99c475ab
FB		 9020 break;
9021
9022 case 8:
9023 /* load/store halfword immediate offset */
9024 rd = insn & 7;
9025 rn = (insn >> 3) & 7;
b0109805 9026 addr = load_reg(s, rn);
99c475ab 9027 val = (insn >> 5) & 0x3e;
b0109805 9028 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 9029
9030 if (insn & (1 << 11)) {
9031 /* load */
b0109805
PB		 9032 tmp = gen_ld16u(addr, IS_USER(s));
9033 store_reg(s, rd, tmp);
99c475ab
FB		 9034 } else {
9035 /* store */
b0109805
PB		 9036 tmp = load_reg(s, rd);
9037 gen_st16(tmp, addr, IS_USER(s));
99c475ab 9038 }
7d1b0095 9039 tcg_temp_free_i32(addr);
99c475ab
FB		 9040 break;
9041
9042 case 9:
9043 /* load/store from stack */
9044 rd = (insn >> 8) & 7;
b0109805 9045 addr = load_reg(s, 13);
99c475ab 9046 val = (insn & 0xff) * 4;
b0109805 9047 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 9048
9049 if (insn & (1 << 11)) {
9050 /* load */
b0109805
PB		 9051 tmp = gen_ld32(addr, IS_USER(s));
9052 store_reg(s, rd, tmp);
99c475ab
FB		 9053 } else {
9054 /* store */
b0109805
PB		 9055 tmp = load_reg(s, rd);
9056 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9057 }
7d1b0095 9058 tcg_temp_free_i32(addr);
99c475ab
FB		 9059 break;
9060
9061 case 10:
9062 /* add to high reg */
9063 rd = (insn >> 8) & 7;
5899f386
FB		 9064 if (insn & (1 << 11)) {
9065 /* SP */
5e3f878a 9066 tmp = load_reg(s, 13);
5899f386
FB		 9067 } else {
9068 /* PC. bit 1 is ignored. */
7d1b0095 9069 tmp = tcg_temp_new_i32();
5e3f878a 9070 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 9071 }
99c475ab 9072 val = (insn & 0xff) * 4;
5e3f878a
PB		 9073 tcg_gen_addi_i32(tmp, tmp, val);
9074 store_reg(s, rd, tmp);
99c475ab
FB		 9075 break;
9076
9077 case 11:
9078 /* misc */
9079 op = (insn >> 8) & 0xf;
9080 switch (op) {
9081 case 0:
9082 /* adjust stack pointer */
b26eefb6 9083 tmp = load_reg(s, 13);
99c475ab
FB		 9084 val = (insn & 0x7f) * 4;
9085 if (insn & (1 << 7))
6a0d8a1d 9086 val = -(int32_t)val;
b26eefb6
PB		 9087 tcg_gen_addi_i32(tmp, tmp, val);
9088 store_reg(s, 13, tmp);
99c475ab
FB		 9089 break;
9090
9ee6e8bb
PB		 9091 case 2: /* sign/zero extend. */
9092 ARCH(6);
9093 rd = insn & 7;
9094 rm = (insn >> 3) & 7;
b0109805 9095 tmp = load_reg(s, rm);
9ee6e8bb 9096 switch ((insn >> 6) & 3) {
b0109805
PB		 9097 case 0: gen_sxth(tmp); break;
9098 case 1: gen_sxtb(tmp); break;
9099 case 2: gen_uxth(tmp); break;
9100 case 3: gen_uxtb(tmp); break;
9ee6e8bb 9101 }
b0109805 9102 store_reg(s, rd, tmp);
9ee6e8bb 9103 break;
99c475ab
FB		 9104 case 4: case 5: case 0xc: case 0xd:
9105 /* push/pop */
b0109805 9106 addr = load_reg(s, 13);
5899f386
FB		 9107 if (insn & (1 << 8))
9108 offset = 4;
99c475ab 9109 else
5899f386
FB		 9110 offset = 0;
9111 for (i = 0; i < 8; i++) {
9112 if (insn & (1 << i))
9113 offset += 4;
9114 }
9115 if ((insn & (1 << 11)) == 0) {
b0109805 9116 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 9117 }
99c475ab
FB		 9118 for (i = 0; i < 8; i++) {
9119 if (insn & (1 << i)) {
9120 if (insn & (1 << 11)) {
9121 /* pop */
b0109805
PB		 9122 tmp = gen_ld32(addr, IS_USER(s));
9123 store_reg(s, i, tmp);
99c475ab
FB		 9124 } else {
9125 /* push */
b0109805
PB		 9126 tmp = load_reg(s, i);
9127 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9128 }
5899f386 9129 /* advance to the next address. */
b0109805 9130 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9131 }
9132 }
a50f5b91 9133 TCGV_UNUSED(tmp);
99c475ab
FB		 9134 if (insn & (1 << 8)) {
9135 if (insn & (1 << 11)) {
9136 /* pop pc */
b0109805 9137 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 9138 /* don't set the pc until the rest of the instruction
9139 has completed */
9140 } else {
9141 /* push lr */
b0109805
PB		 9142 tmp = load_reg(s, 14);
9143 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9144 }
b0109805 9145 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 9146 }
5899f386 9147 if ((insn & (1 << 11)) == 0) {
b0109805 9148 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 9149 }
99c475ab 9150 /* write back the new stack pointer */
b0109805 9151 store_reg(s, 13, addr);
99c475ab 9152 /* set the new PC value */
be5e7a76
DES		 9153 if ((insn & 0x0900) == 0x0900) {
9154 store_reg_from_load(env, s, 15, tmp);
9155 }
99c475ab
FB		 9156 break;
9157
9ee6e8bb
PB		 9158 case 1: case 3: case 9: case 11: /* czb */
9159 rm = insn & 7;
d9ba4830 9160 tmp = load_reg(s, rm);
9ee6e8bb
PB		 9161 s->condlabel = gen_new_label();
9162 s->condjmp = 1;
9163 if (insn & (1 << 11))
cb63669a 9164 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 9165 else
cb63669a 9166 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
7d1b0095 9167 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 9168 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
9169 val = (uint32_t)s->pc + 2;
9170 val += offset;
9171 gen_jmp(s, val);
9172 break;
9173
9174 case 15: /* IT, nop-hint. */
9175 if ((insn & 0xf) == 0) {
9176 gen_nop_hint(s, (insn >> 4) & 0xf);
9177 break;
9178 }
9179 /* If Then. */
9180 s->condexec_cond = (insn >> 4) & 0xe;
9181 s->condexec_mask = insn & 0x1f;
9182 /* No actual code generated for this insn, just setup state. */
9183 break;
9184
06c949e6 9185 case 0xe: /* bkpt */
be5e7a76 9186 ARCH(5);
bc4a0de0 9187 gen_exception_insn(s, 2, EXCP_BKPT);
06c949e6
PB		 9188 break;
9189
9ee6e8bb
PB		 9190 case 0xa: /* rev */
9191 ARCH(6);
9192 rn = (insn >> 3) & 0x7;
9193 rd = insn & 0x7;
b0109805 9194 tmp = load_reg(s, rn);
9ee6e8bb 9195 switch ((insn >> 6) & 3) {
66896cb8 9196 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 9197 case 1: gen_rev16(tmp); break;
9198 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 9199 default: goto illegal_op;
9200 }
b0109805 9201 store_reg(s, rd, tmp);
9ee6e8bb
PB		 9202 break;
9203
9204 case 6: /* cps */
9205 ARCH(6);
9206 if (IS_USER(s))
9207 break;
9208 if (IS_M(env)) {
8984bd2e 9209 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 9210 /* PRIMASK */
8984bd2e
PB		 9211 if (insn & 1) {
9212 addr = tcg_const_i32(16);
9213 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9214 tcg_temp_free_i32(addr);
8984bd2e 9215 }
9ee6e8bb 9216 /* FAULTMASK */
8984bd2e
PB		 9217 if (insn & 2) {
9218 addr = tcg_const_i32(17);
9219 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9220 tcg_temp_free_i32(addr);
8984bd2e 9221 }
b75263d6 9222 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 9223 gen_lookup_tb(s);
9224 } else {
9225 if (insn & (1 << 4))
9226 shift = CPSR_A | CPSR_I | CPSR_F;
9227 else
9228 shift = 0;
fa26df03 9229 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 9230 }
9231 break;
9232
99c475ab
FB		 9233 default:
9234 goto undef;
9235 }
9236 break;
9237
9238 case 12:
9239 /* load/store multiple */
9240 rn = (insn >> 8) & 0x7;
b0109805 9241 addr = load_reg(s, rn);
99c475ab
FB		 9242 for (i = 0; i < 8; i++) {
9243 if (insn & (1 << i)) {
99c475ab
FB		 9244 if (insn & (1 << 11)) {
9245 /* load */
b0109805
PB		 9246 tmp = gen_ld32(addr, IS_USER(s));
9247 store_reg(s, i, tmp);
99c475ab
FB		 9248 } else {
9249 /* store */
b0109805
PB		 9250 tmp = load_reg(s, i);
9251 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9252 }
5899f386 9253 /* advance to the next address */
b0109805 9254 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9255 }
9256 }
5899f386 9257 /* Base register writeback. */
b0109805
PB		 9258 if ((insn & (1 << rn)) == 0) {
9259 store_reg(s, rn, addr);
9260 } else {
7d1b0095 9261 tcg_temp_free_i32(addr);
b0109805 9262 }
99c475ab
FB		 9263 break;
9264
9265 case 13:
9266 /* conditional branch or swi */
9267 cond = (insn >> 8) & 0xf;
9268 if (cond == 0xe)
9269 goto undef;
9270
9271 if (cond == 0xf) {
9272 /* swi */
422ebf69 9273 gen_set_pc_im(s->pc);
9ee6e8bb 9274 s->is_jmp = DISAS_SWI;
99c475ab
FB		 9275 break;
9276 }
9277 /* generate a conditional jump to next instruction */
e50e6a20 9278 s->condlabel = gen_new_label();
d9ba4830 9279 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 9280 s->condjmp = 1;
99c475ab
FB		 9281
9282 /* jump to the offset */
5899f386 9283 val = (uint32_t)s->pc + 2;
99c475ab 9284 offset = ((int32_t)insn << 24) >> 24;
5899f386 9285 val += offset << 1;
8aaca4c0 9286 gen_jmp(s, val);
99c475ab
FB		 9287 break;
9288
9289 case 14:
358bf29e 9290 if (insn & (1 << 11)) {
9ee6e8bb
PB		 9291 if (disas_thumb2_insn(env, s, insn))
9292 goto undef32;
358bf29e
PB		 9293 break;
9294 }
9ee6e8bb 9295 /* unconditional branch */
99c475ab
FB		 9296 val = (uint32_t)s->pc;
9297 offset = ((int32_t)insn << 21) >> 21;
9298 val += (offset << 1) + 2;
8aaca4c0 9299 gen_jmp(s, val);
99c475ab
FB		 9300 break;
9301
9302 case 15:
9ee6e8bb 9303 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 9304 goto undef32;
9ee6e8bb 9305 break;
99c475ab
FB		 9306 }
9307 return;
9ee6e8bb 9308undef32:
bc4a0de0 9309 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 9310 return;
9311illegal_op:
99c475ab 9312undef:
bc4a0de0 9313 gen_exception_insn(s, 2, EXCP_UDEF);
99c475ab
FB		 9314}
9315
2c0262af
FB		 9316/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9317 basic block 'tb'. If search_pc is TRUE, also generate PC
9318 information for each intermediate instruction. */
2cfc5f17
TS		 9319static inline void gen_intermediate_code_internal(CPUState *env,
9320 TranslationBlock *tb,
9321 int search_pc)
2c0262af
FB		 9322{
9323 DisasContext dc1, *dc = &dc1;
a1d1bb31 9324 CPUBreakpoint *bp;
2c0262af
FB		 9325 uint16_t *gen_opc_end;
9326 int j, lj;
0fa85d43 9327 target_ulong pc_start;
b5ff1b31 9328 uint32_t next_page_start;
2e70f6ef
PB		 9329 int num_insns;
9330 int max_insns;
3b46e624 9331
2c0262af 9332 /* generate intermediate code */
0fa85d43 9333 pc_start = tb->pc;
3b46e624 9334
2c0262af
FB		 9335 dc->tb = tb;
9336
2c0262af 9337 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9338
9339 dc->is_jmp = DISAS_NEXT;
9340 dc->pc = pc_start;
8aaca4c0 9341 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9342 dc->condjmp = 0;
7204ab88 9343 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
98eac7ca
PM		 9344 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9345 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
b5ff1b31 9346#if !defined(CONFIG_USER_ONLY)
61f74d6a 9347 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
b5ff1b31 9348#endif
5df8bac1 9349 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
69d1fc22
PM		 9350 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9351 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
a7812ae4
PB		 9352 cpu_F0s = tcg_temp_new_i32();
9353 cpu_F1s = tcg_temp_new_i32();
9354 cpu_F0d = tcg_temp_new_i64();
9355 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9356 cpu_V0 = cpu_F0d;
9357 cpu_V1 = cpu_F1d;
e677137d 9358 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9359 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9360 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9361 lj = -1;
2e70f6ef
PB		 9362 num_insns = 0;
9363 max_insns = tb->cflags & CF_COUNT_MASK;
9364 if (max_insns == 0)
9365 max_insns = CF_COUNT_MASK;
9366
9367 gen_icount_start();
e12ce78d 9368
3849902c
PM		 9369 tcg_clear_temp_count();
9370
e12ce78d
PM		 9371 /* A note on handling of the condexec (IT) bits:
9372 *
9373 * We want to avoid the overhead of having to write the updated condexec
9374 * bits back to the CPUState for every instruction in an IT block. So:
9375 * (1) if the condexec bits are not already zero then we write
9376 * zero back into the CPUState now. This avoids complications trying
9377 * to do it at the end of the block. (For example if we don't do this
9378 * it's hard to identify whether we can safely skip writing condexec
9379 * at the end of the TB, which we definitely want to do for the case
9380 * where a TB doesn't do anything with the IT state at all.)
9381 * (2) if we are going to leave the TB then we call gen_set_condexec()
9382 * which will write the correct value into CPUState if zero is wrong.
9383 * This is done both for leaving the TB at the end, and for leaving
9384 * it because of an exception we know will happen, which is done in
9385 * gen_exception_insn(). The latter is necessary because we need to
9386 * leave the TB with the PC/IT state just prior to execution of the
9387 * instruction which caused the exception.
9388 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9389 * then the CPUState will be wrong and we need to reset it.
9390 * This is handled in the same way as restoration of the
9391 * PC in these situations: we will be called again with search_pc=1
9392 * and generate a mapping of the condexec bits for each PC in
9393 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9394 * the condexec bits.
9395 *
9396 * Note that there are no instructions which can read the condexec
9397 * bits, and none which can write non-static values to them, so
9398 * we don't need to care about whether CPUState is correct in the
9399 * middle of a TB.
9400 */
9401
9ee6e8bb
PB		 9402 /* Reset the conditional execution bits immediately. This avoids
9403 complications trying to do it at the end of the block. */
98eac7ca 9404 if (dc->condexec_mask || dc->condexec_cond)
8f01245e 9405 {
7d1b0095 9406 TCGv tmp = tcg_temp_new_i32();
8f01245e 9407 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9408 store_cpu_field(tmp, condexec_bits);
8f01245e 9409 }
2c0262af 9410 do {
fbb4a2e3
PB		 9411#ifdef CONFIG_USER_ONLY
9412 /* Intercept jump to the magic kernel page. */
9413 if (dc->pc >= 0xffff0000) {
9414 /* We always get here via a jump, so know we are not in a
9415 conditional execution block. */
9416 gen_exception(EXCP_KERNEL_TRAP);
9417 dc->is_jmp = DISAS_UPDATE;
9418 break;
9419 }
9420#else
9ee6e8bb
PB		 9421 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9422 /* We always get here via a jump, so know we are not in a
9423 conditional execution block. */
d9ba4830 9424 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9425 dc->is_jmp = DISAS_UPDATE;
9426 break;
9ee6e8bb
PB		 9427 }
9428#endif
9429
72cf2d4f
BS		 9430 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9431 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9432 if (bp->pc == dc->pc) {
bc4a0de0 9433 gen_exception_insn(dc, 0, EXCP_DEBUG);
9ee6e8bb
PB		 9434 /* Advance PC so that clearing the breakpoint will
9435 invalidate this TB. */
9436 dc->pc += 2;
9437 goto done_generating;
1fddef4b
FB		 9438 break;
9439 }
9440 }
9441 }
2c0262af
FB		 9442 if (search_pc) {
9443 j = gen_opc_ptr - gen_opc_buf;
9444 if (lj < j) {
9445 lj++;
9446 while (lj < j)
9447 gen_opc_instr_start[lj++] = 0;
9448 }
0fa85d43 9449 gen_opc_pc[lj] = dc->pc;
e12ce78d 9450 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
2c0262af 9451 gen_opc_instr_start[lj] = 1;
2e70f6ef 9452 gen_opc_icount[lj] = num_insns;
2c0262af 9453 }
e50e6a20 9454
2e70f6ef
PB		 9455 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9456 gen_io_start();
9457
5642463a
PM		 9458 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9459 tcg_gen_debug_insn_start(dc->pc);
9460 }
9461
7204ab88 9462 if (dc->thumb) {
9ee6e8bb
PB		 9463 disas_thumb_insn(env, dc);
9464 if (dc->condexec_mask) {
9465 dc->condexec_cond = (dc->condexec_cond & 0xe)
9466 | ((dc->condexec_mask >> 4) & 1);
9467 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9468 if (dc->condexec_mask == 0) {
9469 dc->condexec_cond = 0;
9470 }
9471 }
9472 } else {
9473 disas_arm_insn(env, dc);
9474 }
e50e6a20
FB		 9475
9476 if (dc->condjmp && !dc->is_jmp) {
9477 gen_set_label(dc->condlabel);
9478 dc->condjmp = 0;
9479 }
3849902c
PM		 9480
9481 if (tcg_check_temp_count()) {
9482 fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
9483 }
9484
aaf2d97d 9485 /* Translation stops when a conditional branch is encountered.
e50e6a20 9486 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9487 * Also stop translation when a page boundary is reached. This
bf20dc07 9488 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9489 num_insns ++;
1fddef4b
FB		 9490 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9491 !env->singlestep_enabled &&
1b530a6d 9492 !singlestep &&
2e70f6ef
PB		 9493 dc->pc < next_page_start &&
9494 num_insns < max_insns);
9495
9496 if (tb->cflags & CF_LAST_IO) {
9497 if (dc->condjmp) {
9498 /* FIXME: This can theoretically happen with self-modifying
9499 code. */
9500 cpu_abort(env, "IO on conditional branch instruction");
9501 }
9502 gen_io_end();
9503 }
9ee6e8bb 9504
b5ff1b31 9505 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9506 instruction was a conditional branch or trap, and the PC has
9507 already been written. */
551bd27f 9508 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9509 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9510 if (dc->condjmp) {
9ee6e8bb
PB		 9511 gen_set_condexec(dc);
9512 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9513 gen_exception(EXCP_SWI);
9ee6e8bb 9514 } else {
d9ba4830 9515 gen_exception(EXCP_DEBUG);
9ee6e8bb 9516 }
e50e6a20
FB		 9517 gen_set_label(dc->condlabel);
9518 }
9519 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9520 gen_set_pc_im(dc->pc);
e50e6a20 9521 dc->condjmp = 0;
8aaca4c0 9522 }
9ee6e8bb
PB		 9523 gen_set_condexec(dc);
9524 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9525 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9526 } else {
9527 /* FIXME: Single stepping a WFI insn will not halt
9528 the CPU. */
d9ba4830 9529 gen_exception(EXCP_DEBUG);
9ee6e8bb 9530 }
8aaca4c0 9531 } else {
9ee6e8bb
PB		 9532 /* While branches must always occur at the end of an IT block,
9533 there are a few other things that can cause us to terminate
9534 the TB in the middel of an IT block:
9535 - Exception generating instructions (bkpt, swi, undefined).
9536 - Page boundaries.
9537 - Hardware watchpoints.
9538 Hardware breakpoints have already been handled and skip this code.
9539 */
9540 gen_set_condexec(dc);
8aaca4c0 9541 switch(dc->is_jmp) {
8aaca4c0 9542 case DISAS_NEXT:
6e256c93 9543 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9544 break;
9545 default:
9546 case DISAS_JUMP:
9547 case DISAS_UPDATE:
9548 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9549 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9550 break;
9551 case DISAS_TB_JUMP:
9552 /* nothing more to generate */
9553 break;
9ee6e8bb 9554 case DISAS_WFI:
d9ba4830 9555 gen_helper_wfi();
9ee6e8bb
PB		 9556 break;
9557 case DISAS_SWI:
d9ba4830 9558 gen_exception(EXCP_SWI);
9ee6e8bb 9559 break;
8aaca4c0 9560 }
e50e6a20
FB		 9561 if (dc->condjmp) {
9562 gen_set_label(dc->condlabel);
9ee6e8bb 9563 gen_set_condexec(dc);
6e256c93 9564 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9565 dc->condjmp = 0;
9566 }
2c0262af 9567 }
2e70f6ef 9568
9ee6e8bb 9569done_generating:
2e70f6ef 9570 gen_icount_end(tb, num_insns);
2c0262af
FB		 9571 *gen_opc_ptr = INDEX_op_end;
9572
9573#ifdef DEBUG_DISAS
8fec2b8c 9574 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9575 qemu_log("----------------\n");
9576 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7204ab88 9577 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
93fcfe39 9578 qemu_log("\n");
2c0262af
FB		 9579 }
9580#endif
b5ff1b31
FB		 9581 if (search_pc) {
9582 j = gen_opc_ptr - gen_opc_buf;
9583 lj++;
9584 while (lj <= j)
9585 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9586 } else {
2c0262af 9587 tb->size = dc->pc - pc_start;
2e70f6ef 9588 tb->icount = num_insns;
b5ff1b31 9589 }
2c0262af
FB		 9590}
9591
2cfc5f17 9592void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9593{
2cfc5f17 9594 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9595}
9596
2cfc5f17 9597void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9598{
2cfc5f17 9599 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9600}
9601
b5ff1b31
FB		 9602static const char *cpu_mode_names[16] = {
9603 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9604 "???", "???", "???", "und", "???", "???", "???", "sys"
9605};
9ee6e8bb 9606
9a78eead 9607void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9608 int flags)
2c0262af
FB		 9609{
9610 int i;
06e80fc9 9611#if 0
bc380d17 9612 union {
b7bcbe95
FB		 9613 uint32_t i;
9614 float s;
9615 } s0, s1;
9616 CPU_DoubleU d;
a94a6abf
PB		 9617 /* ??? This assumes float64 and double have the same layout.
9618 Oh well, it's only debug dumps. */
9619 union {
9620 float64 f64;
9621 double d;
9622 } d0;
06e80fc9 9623#endif
b5ff1b31 9624 uint32_t psr;
2c0262af
FB		 9625
9626 for(i=0;i<16;i++) {
7fe48483 9627 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9628 if ((i % 4) == 3)
7fe48483 9629 cpu_fprintf(f, "\n");
2c0262af 9630 else
7fe48483 9631 cpu_fprintf(f, " ");
2c0262af 9632 }
b5ff1b31 9633 psr = cpsr_read(env);
687fa640
TS		 9634 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9635 psr,
b5ff1b31
FB		 9636 psr & (1 << 31) ? 'N' : '-',
9637 psr & (1 << 30) ? 'Z' : '-',
9638 psr & (1 << 29) ? 'C' : '-',
9639 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9640 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9641 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9642
5e3f878a 9643#if 0
b7bcbe95 9644 for (i = 0; i < 16; i++) {
8e96005d
FB		 9645 d.d = env->vfp.regs[i];
9646 s0.i = d.l.lower;
9647 s1.i = d.l.upper;
a94a6abf
PB		 9648 d0.f64 = d.d;
9649 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9650 i * 2, (int)s0.i, s0.s,
a94a6abf 9651 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9652 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9653 d0.d);
b7bcbe95 9654 }
40f137e1 9655 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9656#endif
2c0262af 9657}
a6b025d3 9658
d2856f1a
AJ		 9659void gen_pc_load(CPUState *env, TranslationBlock *tb,
9660 unsigned long searched_pc, int pc_pos, void *puc)
9661{
9662 env->regs[15] = gen_opc_pc[pc_pos];
e12ce78d 9663 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
d2856f1a 9664}
Qemu copy for testing