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tcg/arm: implement andc op
[qemu.git] / target-arm / translate.c
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2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
9ee6e8bb
PB		 37#define ENABLE_ARCH_5J 0
38#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 42
86753403 43#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 44
2c0262af
FB		 45/* internal defines */
46typedef struct DisasContext {
0fa85d43 47 target_ulong pc;
2c0262af 48 int is_jmp;
e50e6a20
FB		 49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
9ee6e8bb
PB		 53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
2c0262af 56 struct TranslationBlock *tb;
8aaca4c0 57 int singlestep_enabled;
5899f386 58 int thumb;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
2c0262af
FB		 62} DisasContext;
63
b5ff1b31
FB		 64#if defined(CONFIG_USER_ONLY)
65#define IS_USER(s) 1
66#else
67#define IS_USER(s) (s->user)
68#endif
69
9ee6e8bb
PB		 70/* These instructions trap after executing, so defer them until after the
71 conditional executions state has been updated. */
72#define DISAS_WFI 4
73#define DISAS_SWI 5
2c0262af 74
a7812ae4 75static TCGv_ptr cpu_env;
ad69471c 76/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 77static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 78static TCGv_i32 cpu_R[16];
426f5abc
PB		 79static TCGv_i32 cpu_exclusive_addr;
80static TCGv_i32 cpu_exclusive_val;
81static TCGv_i32 cpu_exclusive_high;
82#ifdef CONFIG_USER_ONLY
83static TCGv_i32 cpu_exclusive_test;
84static TCGv_i32 cpu_exclusive_info;
85#endif
ad69471c 86
b26eefb6 87/* FIXME: These should be removed. */
a7812ae4
PB		 88static TCGv cpu_F0s, cpu_F1s;
89static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 90
2e70f6ef
PB		 91#include "gen-icount.h"
92
155c3eac
FN		 93static const char *regnames[] =
94 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
95 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
96
b26eefb6
PB		 97/* initialize TCG globals. */
98void arm_translate_init(void)
99{
155c3eac
FN		 100 int i;
101
a7812ae4
PB		 102 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
103
155c3eac
FN		 104 for (i = 0; i < 16; i++) {
105 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
106 offsetof(CPUState, regs[i]),
107 regnames[i]);
108 }
426f5abc
PB		 109 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUState, exclusive_addr), "exclusive_addr");
111 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
112 offsetof(CPUState, exclusive_val), "exclusive_val");
113 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUState, exclusive_high), "exclusive_high");
115#ifdef CONFIG_USER_ONLY
116 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_test), "exclusive_test");
118 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_info), "exclusive_info");
120#endif
155c3eac 121
a7812ae4
PB		 122#define GEN_HELPER 2
123#include "helpers.h"
b26eefb6
PB		 124}
125
b26eefb6 126static int num_temps;
b26eefb6
PB		 127
128/* Allocate a temporary variable. */
a7812ae4 129static TCGv_i32 new_tmp(void)
b26eefb6 130{
12edd4f2
FN		 131 num_temps++;
132 return tcg_temp_new_i32();
b26eefb6
PB		 133}
134
135/* Release a temporary variable. */
136static void dead_tmp(TCGv tmp)
137{
12edd4f2 138 tcg_temp_free(tmp);
b26eefb6 139 num_temps--;
b26eefb6
PB		 140}
141
d9ba4830
PB		 142static inline TCGv load_cpu_offset(int offset)
143{
144 TCGv tmp = new_tmp();
145 tcg_gen_ld_i32(tmp, cpu_env, offset);
146 return tmp;
147}
148
149#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
150
151static inline void store_cpu_offset(TCGv var, int offset)
152{
153 tcg_gen_st_i32(var, cpu_env, offset);
154 dead_tmp(var);
155}
156
157#define store_cpu_field(var, name) \
158 store_cpu_offset(var, offsetof(CPUState, name))
159
b26eefb6
PB		 160/* Set a variable to the value of a CPU register. */
161static void load_reg_var(DisasContext *s, TCGv var, int reg)
162{
163 if (reg == 15) {
164 uint32_t addr;
165 /* normaly, since we updated PC, we need only to add one insn */
166 if (s->thumb)
167 addr = (long)s->pc + 2;
168 else
169 addr = (long)s->pc + 4;
170 tcg_gen_movi_i32(var, addr);
171 } else {
155c3eac 172 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 173 }
174}
175
176/* Create a new temporary and set it to the value of a CPU register. */
177static inline TCGv load_reg(DisasContext *s, int reg)
178{
179 TCGv tmp = new_tmp();
180 load_reg_var(s, tmp, reg);
181 return tmp;
182}
183
184/* Set a CPU register. The source must be a temporary and will be
185 marked as dead. */
186static void store_reg(DisasContext *s, int reg, TCGv var)
187{
188 if (reg == 15) {
189 tcg_gen_andi_i32(var, var, ~1);
190 s->is_jmp = DISAS_JUMP;
191 }
155c3eac 192 tcg_gen_mov_i32(cpu_R[reg], var);
b26eefb6
PB		 193 dead_tmp(var);
194}
195
b26eefb6 196/* Value extensions. */
86831435
PB		 197#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
198#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 199#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
200#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
201
1497c961
PB		 202#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
203#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 204
b26eefb6 205
b75263d6
JR		 206static inline void gen_set_cpsr(TCGv var, uint32_t mask)
207{
208 TCGv tmp_mask = tcg_const_i32(mask);
209 gen_helper_cpsr_write(var, tmp_mask);
210 tcg_temp_free_i32(tmp_mask);
211}
d9ba4830
PB		 212/* Set NZCV flags from the high 4 bits of var. */
213#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
214
215static void gen_exception(int excp)
216{
217 TCGv tmp = new_tmp();
218 tcg_gen_movi_i32(tmp, excp);
219 gen_helper_exception(tmp);
220 dead_tmp(tmp);
221}
222
3670669c
PB		 223static void gen_smul_dual(TCGv a, TCGv b)
224{
225 TCGv tmp1 = new_tmp();
226 TCGv tmp2 = new_tmp();
22478e79
AZ		 227 tcg_gen_ext16s_i32(tmp1, a);
228 tcg_gen_ext16s_i32(tmp2, b);
3670669c
PB		 229 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
230 dead_tmp(tmp2);
231 tcg_gen_sari_i32(a, a, 16);
232 tcg_gen_sari_i32(b, b, 16);
233 tcg_gen_mul_i32(b, b, a);
234 tcg_gen_mov_i32(a, tmp1);
235 dead_tmp(tmp1);
236}
237
238/* Byteswap each halfword. */
239static void gen_rev16(TCGv var)
240{
241 TCGv tmp = new_tmp();
242 tcg_gen_shri_i32(tmp, var, 8);
243 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
244 tcg_gen_shli_i32(var, var, 8);
245 tcg_gen_andi_i32(var, var, 0xff00ff00);
246 tcg_gen_or_i32(var, var, tmp);
247 dead_tmp(tmp);
248}
249
250/* Byteswap low halfword and sign extend. */
251static void gen_revsh(TCGv var)
252{
253 TCGv tmp = new_tmp();
254 tcg_gen_shri_i32(tmp, var, 8);
255 tcg_gen_andi_i32(tmp, tmp, 0x00ff);
256 tcg_gen_shli_i32(var, var, 8);
257 tcg_gen_ext8s_i32(var, var);
258 tcg_gen_or_i32(var, var, tmp);
259 dead_tmp(tmp);
260}
261
262/* Unsigned bitfield extract. */
263static void gen_ubfx(TCGv var, int shift, uint32_t mask)
264{
265 if (shift)
266 tcg_gen_shri_i32(var, var, shift);
267 tcg_gen_andi_i32(var, var, mask);
268}
269
270/* Signed bitfield extract. */
271static void gen_sbfx(TCGv var, int shift, int width)
272{
273 uint32_t signbit;
274
275 if (shift)
276 tcg_gen_sari_i32(var, var, shift);
277 if (shift + width < 32) {
278 signbit = 1u << (width - 1);
279 tcg_gen_andi_i32(var, var, (1u << width) - 1);
280 tcg_gen_xori_i32(var, var, signbit);
281 tcg_gen_subi_i32(var, var, signbit);
282 }
283}
284
285/* Bitfield insertion. Insert val into base. Clobbers base and val. */
286static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
287{
3670669c 288 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 289 tcg_gen_shli_i32(val, val, shift);
290 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 291 tcg_gen_or_i32(dest, base, val);
292}
293
d9ba4830
PB		 294/* Round the top 32 bits of a 64-bit value. */
295static void gen_roundqd(TCGv a, TCGv b)
3670669c 296{
d9ba4830
PB		 297 tcg_gen_shri_i32(a, a, 31);
298 tcg_gen_add_i32(a, a, b);
3670669c
PB		 299}
300
8f01245e
PB		 301/* FIXME: Most targets have native widening multiplication.
302 It would be good to use that instead of a full wide multiply. */
5e3f878a 303/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 304static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 305{
a7812ae4
PB		 306 TCGv_i64 tmp1 = tcg_temp_new_i64();
307 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 308
309 tcg_gen_extu_i32_i64(tmp1, a);
310 dead_tmp(a);
311 tcg_gen_extu_i32_i64(tmp2, b);
312 dead_tmp(b);
313 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 314 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 315 return tmp1;
316}
317
a7812ae4 318static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 319{
a7812ae4
PB		 320 TCGv_i64 tmp1 = tcg_temp_new_i64();
321 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 322
323 tcg_gen_ext_i32_i64(tmp1, a);
324 dead_tmp(a);
325 tcg_gen_ext_i32_i64(tmp2, b);
326 dead_tmp(b);
327 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 328 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 329 return tmp1;
330}
331
8f01245e 332/* Signed 32x32->64 multiply. */
d9ba4830 333static void gen_imull(TCGv a, TCGv b)
8f01245e 334{
a7812ae4
PB		 335 TCGv_i64 tmp1 = tcg_temp_new_i64();
336 TCGv_i64 tmp2 = tcg_temp_new_i64();
8f01245e 337
d9ba4830
PB		 338 tcg_gen_ext_i32_i64(tmp1, a);
339 tcg_gen_ext_i32_i64(tmp2, b);
8f01245e 340 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 341 tcg_temp_free_i64(tmp2);
d9ba4830 342 tcg_gen_trunc_i64_i32(a, tmp1);
8f01245e 343 tcg_gen_shri_i64(tmp1, tmp1, 32);
d9ba4830 344 tcg_gen_trunc_i64_i32(b, tmp1);
b75263d6 345 tcg_temp_free_i64(tmp1);
d9ba4830 346}
d9ba4830 347
8f01245e
PB		 348/* Swap low and high halfwords. */
349static void gen_swap_half(TCGv var)
350{
351 TCGv tmp = new_tmp();
352 tcg_gen_shri_i32(tmp, var, 16);
353 tcg_gen_shli_i32(var, var, 16);
354 tcg_gen_or_i32(var, var, tmp);
3670669c 355 dead_tmp(tmp);
8f01245e
PB		 356}
357
b26eefb6
PB		 358/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
359 tmp = (t0 ^ t1) & 0x8000;
360 t0 &= ~0x8000;
361 t1 &= ~0x8000;
362 t0 = (t0 + t1) ^ tmp;
363 */
364
365static void gen_add16(TCGv t0, TCGv t1)
366{
367 TCGv tmp = new_tmp();
368 tcg_gen_xor_i32(tmp, t0, t1);
369 tcg_gen_andi_i32(tmp, tmp, 0x8000);
370 tcg_gen_andi_i32(t0, t0, ~0x8000);
371 tcg_gen_andi_i32(t1, t1, ~0x8000);
372 tcg_gen_add_i32(t0, t0, t1);
373 tcg_gen_xor_i32(t0, t0, tmp);
374 dead_tmp(tmp);
375 dead_tmp(t1);
376}
377
9a119ff6
PB		 378#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
379
b26eefb6
PB		 380/* Set CF to the top bit of var. */
381static void gen_set_CF_bit31(TCGv var)
382{
383 TCGv tmp = new_tmp();
384 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 385 gen_set_CF(tmp);
b26eefb6
PB		 386 dead_tmp(tmp);
387}
388
389/* Set N and Z flags from var. */
390static inline void gen_logic_CC(TCGv var)
391{
6fbe23d5
PB		 392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 394}
395
396/* T0 += T1 + CF. */
396e467c 397static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 398{
d9ba4830 399 TCGv tmp;
396e467c 400 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 401 tmp = load_cpu_field(CF);
396e467c 402 tcg_gen_add_i32(t0, t0, tmp);
b26eefb6
PB		 403 dead_tmp(tmp);
404}
405
e9bb4aa9
JR		 406/* dest = T0 + T1 + CF. */
407static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
408{
409 TCGv tmp;
410 tcg_gen_add_i32(dest, t0, t1);
411 tmp = load_cpu_field(CF);
412 tcg_gen_add_i32(dest, dest, tmp);
413 dead_tmp(tmp);
414}
415
3670669c
PB		 416/* dest = T0 - T1 + CF - 1. */
417static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
418{
d9ba4830 419 TCGv tmp;
3670669c 420 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 421 tmp = load_cpu_field(CF);
3670669c
PB		 422 tcg_gen_add_i32(dest, dest, tmp);
423 tcg_gen_subi_i32(dest, dest, 1);
424 dead_tmp(tmp);
425}
426
ad69471c
PB		 427/* FIXME: Implement this natively. */
428#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
429
9a119ff6 430static void shifter_out_im(TCGv var, int shift)
b26eefb6 431{
9a119ff6
PB		 432 TCGv tmp = new_tmp();
433 if (shift == 0) {
434 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 435 } else {
9a119ff6 436 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 437 if (shift != 31)
9a119ff6
PB		 438 tcg_gen_andi_i32(tmp, tmp, 1);
439 }
440 gen_set_CF(tmp);
441 dead_tmp(tmp);
442}
b26eefb6 443
9a119ff6
PB		 444/* Shift by immediate. Includes special handling for shift == 0. */
445static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
446{
447 switch (shiftop) {
448 case 0: /* LSL */
449 if (shift != 0) {
450 if (flags)
451 shifter_out_im(var, 32 - shift);
452 tcg_gen_shli_i32(var, var, shift);
453 }
454 break;
455 case 1: /* LSR */
456 if (shift == 0) {
457 if (flags) {
458 tcg_gen_shri_i32(var, var, 31);
459 gen_set_CF(var);
460 }
461 tcg_gen_movi_i32(var, 0);
462 } else {
463 if (flags)
464 shifter_out_im(var, shift - 1);
465 tcg_gen_shri_i32(var, var, shift);
466 }
467 break;
468 case 2: /* ASR */
469 if (shift == 0)
470 shift = 32;
471 if (flags)
472 shifter_out_im(var, shift - 1);
473 if (shift == 32)
474 shift = 31;
475 tcg_gen_sari_i32(var, var, shift);
476 break;
477 case 3: /* ROR/RRX */
478 if (shift != 0) {
479 if (flags)
480 shifter_out_im(var, shift - 1);
f669df27 481 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 482 } else {
d9ba4830 483 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 484 if (flags)
485 shifter_out_im(var, 0);
486 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 487 tcg_gen_shli_i32(tmp, tmp, 31);
488 tcg_gen_or_i32(var, var, tmp);
489 dead_tmp(tmp);
b26eefb6
PB		 490 }
491 }
492};
493
8984bd2e
PB		 494static inline void gen_arm_shift_reg(TCGv var, int shiftop,
495 TCGv shift, int flags)
496{
497 if (flags) {
498 switch (shiftop) {
499 case 0: gen_helper_shl_cc(var, var, shift); break;
500 case 1: gen_helper_shr_cc(var, var, shift); break;
501 case 2: gen_helper_sar_cc(var, var, shift); break;
502 case 3: gen_helper_ror_cc(var, var, shift); break;
503 }
504 } else {
505 switch (shiftop) {
506 case 0: gen_helper_shl(var, var, shift); break;
507 case 1: gen_helper_shr(var, var, shift); break;
508 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 509 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
510 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 511 }
512 }
513 dead_tmp(shift);
514}
515
6ddbc6e4
PB		 516#define PAS_OP(pfx) \
517 switch (op2) { \
518 case 0: gen_pas_helper(glue(pfx,add16)); break; \
519 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
520 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
521 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
522 case 4: gen_pas_helper(glue(pfx,add8)); break; \
523 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
524 }
d9ba4830 525static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 526{
a7812ae4 527 TCGv_ptr tmp;
6ddbc6e4
PB		 528
529 switch (op1) {
530#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
531 case 1:
a7812ae4 532 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(s)
b75263d6 535 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 536 break;
537 case 5:
a7812ae4 538 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(u)
b75263d6 541 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 542 break;
543#undef gen_pas_helper
544#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
545 case 2:
546 PAS_OP(q);
547 break;
548 case 3:
549 PAS_OP(sh);
550 break;
551 case 6:
552 PAS_OP(uq);
553 break;
554 case 7:
555 PAS_OP(uh);
556 break;
557#undef gen_pas_helper
558 }
559}
9ee6e8bb
PB		 560#undef PAS_OP
561
6ddbc6e4
PB		 562/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
563#define PAS_OP(pfx) \
564 switch (op2) { \
565 case 0: gen_pas_helper(glue(pfx,add8)); break; \
566 case 1: gen_pas_helper(glue(pfx,add16)); break; \
567 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
568 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
569 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
570 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
571 }
d9ba4830 572static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 573{
a7812ae4 574 TCGv_ptr tmp;
6ddbc6e4
PB		 575
576 switch (op1) {
577#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
578 case 0:
a7812ae4 579 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(s)
b75263d6 582 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 583 break;
584 case 4:
a7812ae4 585 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(u)
b75263d6 588 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 589 break;
590#undef gen_pas_helper
591#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
592 case 1:
593 PAS_OP(q);
594 break;
595 case 2:
596 PAS_OP(sh);
597 break;
598 case 5:
599 PAS_OP(uq);
600 break;
601 case 6:
602 PAS_OP(uh);
603 break;
604#undef gen_pas_helper
605 }
606}
9ee6e8bb
PB		 607#undef PAS_OP
608
d9ba4830
PB		 609static void gen_test_cc(int cc, int label)
610{
611 TCGv tmp;
612 TCGv tmp2;
d9ba4830
PB		 613 int inv;
614
d9ba4830
PB		 615 switch (cc) {
616 case 0: /* eq: Z */
6fbe23d5 617 tmp = load_cpu_field(ZF);
cb63669a 618 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 619 break;
620 case 1: /* ne: !Z */
6fbe23d5 621 tmp = load_cpu_field(ZF);
cb63669a 622 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 623 break;
624 case 2: /* cs: C */
625 tmp = load_cpu_field(CF);
cb63669a 626 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 627 break;
628 case 3: /* cc: !C */
629 tmp = load_cpu_field(CF);
cb63669a 630 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 631 break;
632 case 4: /* mi: N */
6fbe23d5 633 tmp = load_cpu_field(NF);
cb63669a 634 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 635 break;
636 case 5: /* pl: !N */
6fbe23d5 637 tmp = load_cpu_field(NF);
cb63669a 638 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 639 break;
640 case 6: /* vs: V */
641 tmp = load_cpu_field(VF);
cb63669a 642 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 643 break;
644 case 7: /* vc: !V */
645 tmp = load_cpu_field(VF);
cb63669a 646 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 647 break;
648 case 8: /* hi: C && !Z */
649 inv = gen_new_label();
650 tmp = load_cpu_field(CF);
cb63669a 651 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830 652 dead_tmp(tmp);
6fbe23d5 653 tmp = load_cpu_field(ZF);
cb63669a 654 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 655 gen_set_label(inv);
656 break;
657 case 9: /* ls: !C || Z */
658 tmp = load_cpu_field(CF);
cb63669a 659 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830 660 dead_tmp(tmp);
6fbe23d5 661 tmp = load_cpu_field(ZF);
cb63669a 662 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 663 break;
664 case 10: /* ge: N == V -> N ^ V == 0 */
665 tmp = load_cpu_field(VF);
6fbe23d5 666 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 667 tcg_gen_xor_i32(tmp, tmp, tmp2);
668 dead_tmp(tmp2);
cb63669a 669 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 670 break;
671 case 11: /* lt: N != V -> N ^ V != 0 */
672 tmp = load_cpu_field(VF);
6fbe23d5 673 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 674 tcg_gen_xor_i32(tmp, tmp, tmp2);
675 dead_tmp(tmp2);
cb63669a 676 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 677 break;
678 case 12: /* gt: !Z && N == V */
679 inv = gen_new_label();
6fbe23d5 680 tmp = load_cpu_field(ZF);
cb63669a 681 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830
PB		 682 dead_tmp(tmp);
683 tmp = load_cpu_field(VF);
6fbe23d5 684 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 685 tcg_gen_xor_i32(tmp, tmp, tmp2);
686 dead_tmp(tmp2);
cb63669a 687 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 688 gen_set_label(inv);
689 break;
690 case 13: /* le: Z || N != V */
6fbe23d5 691 tmp = load_cpu_field(ZF);
cb63669a 692 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 693 dead_tmp(tmp);
694 tmp = load_cpu_field(VF);
6fbe23d5 695 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 696 tcg_gen_xor_i32(tmp, tmp, tmp2);
697 dead_tmp(tmp2);
cb63669a 698 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 699 break;
700 default:
701 fprintf(stderr, "Bad condition code 0x%x\n", cc);
702 abort();
703 }
704 dead_tmp(tmp);
705}
2c0262af 706
b1d8e52e 707static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 708 1, /* and */
709 1, /* xor */
710 0, /* sub */
711 0, /* rsb */
712 0, /* add */
713 0, /* adc */
714 0, /* sbc */
715 0, /* rsc */
716 1, /* andl */
717 1, /* xorl */
718 0, /* cmp */
719 0, /* cmn */
720 1, /* orr */
721 1, /* mov */
722 1, /* bic */
723 1, /* mvn */
724};
3b46e624 725
d9ba4830
PB		 726/* Set PC and Thumb state from an immediate address. */
727static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 728{
b26eefb6 729 TCGv tmp;
99c475ab 730
b26eefb6 731 s->is_jmp = DISAS_UPDATE;
d9ba4830 732 if (s->thumb != (addr & 1)) {
155c3eac 733 tmp = new_tmp();
d9ba4830
PB		 734 tcg_gen_movi_i32(tmp, addr & 1);
735 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
155c3eac 736 dead_tmp(tmp);
d9ba4830 737 }
155c3eac 738 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 739}
740
741/* Set PC and Thumb state from var. var is marked as dead. */
742static inline void gen_bx(DisasContext *s, TCGv var)
743{
d9ba4830 744 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 745 tcg_gen_andi_i32(cpu_R[15], var, ~1);
746 tcg_gen_andi_i32(var, var, 1);
747 store_cpu_field(var, thumb);
d9ba4830
PB		 748}
749
21aeb343
JR		 750/* Variant of store_reg which uses branch&exchange logic when storing
751 to r15 in ARM architecture v7 and above. The source must be a temporary
752 and will be marked as dead. */
753static inline void store_reg_bx(CPUState *env, DisasContext *s,
754 int reg, TCGv var)
755{
756 if (reg == 15 && ENABLE_ARCH_7) {
757 gen_bx(s, var);
758 } else {
759 store_reg(s, reg, var);
760 }
761}
762
b0109805
PB		 763static inline TCGv gen_ld8s(TCGv addr, int index)
764{
765 TCGv tmp = new_tmp();
766 tcg_gen_qemu_ld8s(tmp, addr, index);
767 return tmp;
768}
769static inline TCGv gen_ld8u(TCGv addr, int index)
770{
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8u(tmp, addr, index);
773 return tmp;
774}
775static inline TCGv gen_ld16s(TCGv addr, int index)
776{
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld16s(tmp, addr, index);
779 return tmp;
780}
781static inline TCGv gen_ld16u(TCGv addr, int index)
782{
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16u(tmp, addr, index);
785 return tmp;
786}
787static inline TCGv gen_ld32(TCGv addr, int index)
788{
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld32u(tmp, addr, index);
791 return tmp;
792}
84496233
JR		 793static inline TCGv_i64 gen_ld64(TCGv addr, int index)
794{
795 TCGv_i64 tmp = tcg_temp_new_i64();
796 tcg_gen_qemu_ld64(tmp, addr, index);
797 return tmp;
798}
b0109805
PB		 799static inline void gen_st8(TCGv val, TCGv addr, int index)
800{
801 tcg_gen_qemu_st8(val, addr, index);
802 dead_tmp(val);
803}
804static inline void gen_st16(TCGv val, TCGv addr, int index)
805{
806 tcg_gen_qemu_st16(val, addr, index);
807 dead_tmp(val);
808}
809static inline void gen_st32(TCGv val, TCGv addr, int index)
810{
811 tcg_gen_qemu_st32(val, addr, index);
812 dead_tmp(val);
813}
84496233
JR		 814static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
815{
816 tcg_gen_qemu_st64(val, addr, index);
817 tcg_temp_free_i64(val);
818}
b5ff1b31 819
5e3f878a
PB		 820static inline void gen_set_pc_im(uint32_t val)
821{
155c3eac 822 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 823}
824
b5ff1b31
FB		 825/* Force a TB lookup after an instruction that changes the CPU state. */
826static inline void gen_lookup_tb(DisasContext *s)
827{
a6445c52 828 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 829 s->is_jmp = DISAS_UPDATE;
830}
831
b0109805
PB		 832static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
833 TCGv var)
2c0262af 834{
1e8d4eec 835 int val, rm, shift, shiftop;
b26eefb6 836 TCGv offset;
2c0262af
FB		 837
838 if (!(insn & (1 << 25))) {
839 /* immediate */
840 val = insn & 0xfff;
841 if (!(insn & (1 << 23)))
842 val = -val;
537730b9 843 if (val != 0)
b0109805 844 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 845 } else {
846 /* shift/register */
847 rm = (insn) & 0xf;
848 shift = (insn >> 7) & 0x1f;
1e8d4eec 849 shiftop = (insn >> 5) & 3;
b26eefb6 850 offset = load_reg(s, rm);
9a119ff6 851 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 852 if (!(insn & (1 << 23)))
b0109805 853 tcg_gen_sub_i32(var, var, offset);
2c0262af 854 else
b0109805 855 tcg_gen_add_i32(var, var, offset);
b26eefb6 856 dead_tmp(offset);
2c0262af
FB		 857 }
858}
859
191f9a93 860static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 861 int extra, TCGv var)
2c0262af
FB		 862{
863 int val, rm;
b26eefb6 864 TCGv offset;
3b46e624 865
2c0262af
FB		 866 if (insn & (1 << 22)) {
867 /* immediate */
868 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
869 if (!(insn & (1 << 23)))
870 val = -val;
18acad92 871 val += extra;
537730b9 872 if (val != 0)
b0109805 873 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 874 } else {
875 /* register */
191f9a93 876 if (extra)
b0109805 877 tcg_gen_addi_i32(var, var, extra);
2c0262af 878 rm = (insn) & 0xf;
b26eefb6 879 offset = load_reg(s, rm);
2c0262af 880 if (!(insn & (1 << 23)))
b0109805 881 tcg_gen_sub_i32(var, var, offset);
2c0262af 882 else
b0109805 883 tcg_gen_add_i32(var, var, offset);
b26eefb6 884 dead_tmp(offset);
2c0262af
FB		 885 }
886}
887
4373f3ce
PB		 888#define VFP_OP2(name) \
889static inline void gen_vfp_##name(int dp) \
890{ \
891 if (dp) \
892 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
893 else \
894 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 895}
896
4373f3ce
PB		 897VFP_OP2(add)
898VFP_OP2(sub)
899VFP_OP2(mul)
900VFP_OP2(div)
901
902#undef VFP_OP2
903
904static inline void gen_vfp_abs(int dp)
905{
906 if (dp)
907 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
908 else
909 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
910}
911
912static inline void gen_vfp_neg(int dp)
913{
914 if (dp)
915 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
918}
919
920static inline void gen_vfp_sqrt(int dp)
921{
922 if (dp)
923 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
924 else
925 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
926}
927
928static inline void gen_vfp_cmp(int dp)
929{
930 if (dp)
931 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
932 else
933 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
934}
935
936static inline void gen_vfp_cmpe(int dp)
937{
938 if (dp)
939 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
942}
943
944static inline void gen_vfp_F1_ld0(int dp)
945{
946 if (dp)
5b340b51 947 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 948 else
5b340b51 949 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 950}
951
952static inline void gen_vfp_uito(int dp)
953{
954 if (dp)
955 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
956 else
957 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
958}
959
960static inline void gen_vfp_sito(int dp)
961{
962 if (dp)
66230e0d 963 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 964 else
66230e0d 965 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 966}
967
968static inline void gen_vfp_toui(int dp)
969{
970 if (dp)
971 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
972 else
973 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
974}
975
976static inline void gen_vfp_touiz(int dp)
977{
978 if (dp)
979 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
982}
983
984static inline void gen_vfp_tosi(int dp)
985{
986 if (dp)
987 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
990}
991
992static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 993{
994 if (dp)
4373f3ce 995 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 996 else
4373f3ce
PB		 997 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
998}
999
1000#define VFP_GEN_FIX(name) \
1001static inline void gen_vfp_##name(int dp, int shift) \
1002{ \
b75263d6 1003 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1004 if (dp) \
b75263d6 1005 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1006 else \
b75263d6
JR		 1007 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1008 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1009}
4373f3ce
PB		 1010VFP_GEN_FIX(tosh)
1011VFP_GEN_FIX(tosl)
1012VFP_GEN_FIX(touh)
1013VFP_GEN_FIX(toul)
1014VFP_GEN_FIX(shto)
1015VFP_GEN_FIX(slto)
1016VFP_GEN_FIX(uhto)
1017VFP_GEN_FIX(ulto)
1018#undef VFP_GEN_FIX
9ee6e8bb 1019
312eea9f 1020static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1021{
1022 if (dp)
312eea9f 1023 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1024 else
312eea9f 1025 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1026}
1027
312eea9f 1028static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1029{
1030 if (dp)
312eea9f 1031 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1032 else
312eea9f 1033 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1034}
1035
8e96005d
FB		 1036static inline long
1037vfp_reg_offset (int dp, int reg)
1038{
1039 if (dp)
1040 return offsetof(CPUARMState, vfp.regs[reg]);
1041 else if (reg & 1) {
1042 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1043 + offsetof(CPU_DoubleU, l.upper);
1044 } else {
1045 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1046 + offsetof(CPU_DoubleU, l.lower);
1047 }
1048}
9ee6e8bb
PB		 1049
1050/* Return the offset of a 32-bit piece of a NEON register.
1051 zero is the least significant end of the register. */
1052static inline long
1053neon_reg_offset (int reg, int n)
1054{
1055 int sreg;
1056 sreg = reg * 2 + n;
1057 return vfp_reg_offset(0, sreg);
1058}
1059
8f8e3aa4
PB		 1060static TCGv neon_load_reg(int reg, int pass)
1061{
1062 TCGv tmp = new_tmp();
1063 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1064 return tmp;
1065}
1066
1067static void neon_store_reg(int reg, int pass, TCGv var)
1068{
1069 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1070 dead_tmp(var);
1071}
1072
a7812ae4 1073static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1074{
1075 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1076}
1077
a7812ae4 1078static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1079{
1080 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1081}
1082
4373f3ce
PB		 1083#define tcg_gen_ld_f32 tcg_gen_ld_i32
1084#define tcg_gen_ld_f64 tcg_gen_ld_i64
1085#define tcg_gen_st_f32 tcg_gen_st_i32
1086#define tcg_gen_st_f64 tcg_gen_st_i64
1087
b7bcbe95
FB		 1088static inline void gen_mov_F0_vreg(int dp, int reg)
1089{
1090 if (dp)
4373f3ce 1091 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1092 else
4373f3ce 1093 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1094}
1095
1096static inline void gen_mov_F1_vreg(int dp, int reg)
1097{
1098 if (dp)
4373f3ce 1099 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1100 else
4373f3ce 1101 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1102}
1103
1104static inline void gen_mov_vreg_F0(int dp, int reg)
1105{
1106 if (dp)
4373f3ce 1107 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1108 else
4373f3ce 1109 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1110}
1111
18c9b560
AZ		 1112#define ARM_CP_RW_BIT (1 << 20)
1113
a7812ae4 1114static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1115{
1116 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1117}
1118
a7812ae4 1119static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1120{
1121 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1122}
1123
da6b5335 1124static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1125{
da6b5335
FN		 1126 TCGv var = new_tmp();
1127 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1128 return var;
e677137d
PB		 1129}
1130
da6b5335 1131static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1132{
da6b5335 1133 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
e677137d
PB		 1134}
1135
1136static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1137{
1138 iwmmxt_store_reg(cpu_M0, rn);
1139}
1140
1141static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1142{
1143 iwmmxt_load_reg(cpu_M0, rn);
1144}
1145
1146static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1147{
1148 iwmmxt_load_reg(cpu_V1, rn);
1149 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1150}
1151
1152static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1153{
1154 iwmmxt_load_reg(cpu_V1, rn);
1155 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1156}
1157
1158static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1159{
1160 iwmmxt_load_reg(cpu_V1, rn);
1161 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1162}
1163
1164#define IWMMXT_OP(name) \
1165static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1166{ \
1167 iwmmxt_load_reg(cpu_V1, rn); \
1168 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1169}
1170
1171#define IWMMXT_OP_ENV(name) \
1172static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173{ \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1176}
1177
1178#define IWMMXT_OP_ENV_SIZE(name) \
1179IWMMXT_OP_ENV(name##b) \
1180IWMMXT_OP_ENV(name##w) \
1181IWMMXT_OP_ENV(name##l)
1182
1183#define IWMMXT_OP_ENV1(name) \
1184static inline void gen_op_iwmmxt_##name##_M0(void) \
1185{ \
1186 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1187}
1188
1189IWMMXT_OP(maddsq)
1190IWMMXT_OP(madduq)
1191IWMMXT_OP(sadb)
1192IWMMXT_OP(sadw)
1193IWMMXT_OP(mulslw)
1194IWMMXT_OP(mulshw)
1195IWMMXT_OP(mululw)
1196IWMMXT_OP(muluhw)
1197IWMMXT_OP(macsw)
1198IWMMXT_OP(macuw)
1199
1200IWMMXT_OP_ENV_SIZE(unpackl)
1201IWMMXT_OP_ENV_SIZE(unpackh)
1202
1203IWMMXT_OP_ENV1(unpacklub)
1204IWMMXT_OP_ENV1(unpackluw)
1205IWMMXT_OP_ENV1(unpacklul)
1206IWMMXT_OP_ENV1(unpackhub)
1207IWMMXT_OP_ENV1(unpackhuw)
1208IWMMXT_OP_ENV1(unpackhul)
1209IWMMXT_OP_ENV1(unpacklsb)
1210IWMMXT_OP_ENV1(unpacklsw)
1211IWMMXT_OP_ENV1(unpacklsl)
1212IWMMXT_OP_ENV1(unpackhsb)
1213IWMMXT_OP_ENV1(unpackhsw)
1214IWMMXT_OP_ENV1(unpackhsl)
1215
1216IWMMXT_OP_ENV_SIZE(cmpeq)
1217IWMMXT_OP_ENV_SIZE(cmpgtu)
1218IWMMXT_OP_ENV_SIZE(cmpgts)
1219
1220IWMMXT_OP_ENV_SIZE(mins)
1221IWMMXT_OP_ENV_SIZE(minu)
1222IWMMXT_OP_ENV_SIZE(maxs)
1223IWMMXT_OP_ENV_SIZE(maxu)
1224
1225IWMMXT_OP_ENV_SIZE(subn)
1226IWMMXT_OP_ENV_SIZE(addn)
1227IWMMXT_OP_ENV_SIZE(subu)
1228IWMMXT_OP_ENV_SIZE(addu)
1229IWMMXT_OP_ENV_SIZE(subs)
1230IWMMXT_OP_ENV_SIZE(adds)
1231
1232IWMMXT_OP_ENV(avgb0)
1233IWMMXT_OP_ENV(avgb1)
1234IWMMXT_OP_ENV(avgw0)
1235IWMMXT_OP_ENV(avgw1)
1236
1237IWMMXT_OP(msadb)
1238
1239IWMMXT_OP_ENV(packuw)
1240IWMMXT_OP_ENV(packul)
1241IWMMXT_OP_ENV(packuq)
1242IWMMXT_OP_ENV(packsw)
1243IWMMXT_OP_ENV(packsl)
1244IWMMXT_OP_ENV(packsq)
1245
e677137d
PB		 1246static void gen_op_iwmmxt_set_mup(void)
1247{
1248 TCGv tmp;
1249 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1250 tcg_gen_ori_i32(tmp, tmp, 2);
1251 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1252}
1253
1254static void gen_op_iwmmxt_set_cup(void)
1255{
1256 TCGv tmp;
1257 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1258 tcg_gen_ori_i32(tmp, tmp, 1);
1259 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1260}
1261
1262static void gen_op_iwmmxt_setpsr_nz(void)
1263{
1264 TCGv tmp = new_tmp();
1265 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1267}
1268
1269static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1270{
1271 iwmmxt_load_reg(cpu_V1, rn);
86831435 1272 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1273 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1274}
1275
da6b5335 1276static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1277{
1278 int rd;
1279 uint32_t offset;
da6b5335 1280 TCGv tmp;
18c9b560
AZ		 1281
1282 rd = (insn >> 16) & 0xf;
da6b5335 1283 tmp = load_reg(s, rd);
18c9b560
AZ		 1284
1285 offset = (insn & 0xff) << ((insn >> 7) & 2);
1286 if (insn & (1 << 24)) {
1287 /* Pre indexed */
1288 if (insn & (1 << 23))
da6b5335 1289 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1290 else
da6b5335
FN		 1291 tcg_gen_addi_i32(tmp, tmp, -offset);
1292 tcg_gen_mov_i32(dest, tmp);
18c9b560 1293 if (insn & (1 << 21))
da6b5335
FN		 1294 store_reg(s, rd, tmp);
1295 else
1296 dead_tmp(tmp);
18c9b560
AZ		 1297 } else if (insn & (1 << 21)) {
1298 /* Post indexed */
da6b5335 1299 tcg_gen_mov_i32(dest, tmp);
18c9b560 1300 if (insn & (1 << 23))
da6b5335 1301 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1302 else
da6b5335
FN		 1303 tcg_gen_addi_i32(tmp, tmp, -offset);
1304 store_reg(s, rd, tmp);
18c9b560
AZ		 1305 } else if (!(insn & (1 << 23)))
1306 return 1;
1307 return 0;
1308}
1309
da6b5335 1310static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1311{
1312 int rd = (insn >> 0) & 0xf;
da6b5335 1313 TCGv tmp;
18c9b560 1314
da6b5335
FN		 1315 if (insn & (1 << 8)) {
1316 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1317 return 1;
da6b5335
FN		 1318 } else {
1319 tmp = iwmmxt_load_creg(rd);
1320 }
1321 } else {
1322 tmp = new_tmp();
1323 iwmmxt_load_reg(cpu_V0, rd);
1324 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1325 }
1326 tcg_gen_andi_i32(tmp, tmp, mask);
1327 tcg_gen_mov_i32(dest, tmp);
1328 dead_tmp(tmp);
18c9b560
AZ		 1329 return 0;
1330}
1331
1332/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1333 (ie. an undefined instruction). */
1334static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1335{
1336 int rd, wrd;
1337 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1338 TCGv addr;
1339 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1340
1341 if ((insn & 0x0e000e00) == 0x0c000000) {
1342 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1343 wrd = insn & 0xf;
1344 rdlo = (insn >> 12) & 0xf;
1345 rdhi = (insn >> 16) & 0xf;
1346 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1347 iwmmxt_load_reg(cpu_V0, wrd);
1348 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1349 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1350 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1351 } else { /* TMCRR */
da6b5335
FN		 1352 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1353 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1354 gen_op_iwmmxt_set_mup();
1355 }
1356 return 0;
1357 }
1358
1359 wrd = (insn >> 12) & 0xf;
da6b5335
FN		 1360 addr = new_tmp();
1361 if (gen_iwmmxt_address(s, insn, addr)) {
1362 dead_tmp(addr);
18c9b560 1363 return 1;
da6b5335 1364 }
18c9b560
AZ		 1365 if (insn & ARM_CP_RW_BIT) {
1366 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
da6b5335
FN		 1367 tmp = new_tmp();
1368 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1369 iwmmxt_store_creg(wrd, tmp);
18c9b560 1370 } else {
e677137d
PB		 1371 i = 1;
1372 if (insn & (1 << 8)) {
1373 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1374 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1375 i = 0;
1376 } else { /* WLDRW wRd */
da6b5335 1377 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1378 }
1379 } else {
1380 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1381 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1382 } else { /* WLDRB */
da6b5335 1383 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1384 }
1385 }
1386 if (i) {
1387 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1388 dead_tmp(tmp);
1389 }
18c9b560
AZ		 1390 gen_op_iwmmxt_movq_wRn_M0(wrd);
1391 }
1392 } else {
1393 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1394 tmp = iwmmxt_load_creg(wrd);
1395 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1396 } else {
1397 gen_op_iwmmxt_movq_M0_wRn(wrd);
e677137d
PB		 1398 tmp = new_tmp();
1399 if (insn & (1 << 8)) {
1400 if (insn & (1 << 22)) { /* WSTRD */
1401 dead_tmp(tmp);
da6b5335 1402 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1403 } else { /* WSTRW wRd */
1404 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1405 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1406 }
1407 } else {
1408 if (insn & (1 << 22)) { /* WSTRH */
1409 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1410 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1411 } else { /* WSTRB */
1412 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1413 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1414 }
1415 }
18c9b560
AZ		 1416 }
1417 }
1418 return 0;
1419 }
1420
1421 if ((insn & 0x0f000000) != 0x0e000000)
1422 return 1;
1423
1424 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1425 case 0x000: /* WOR */
1426 wrd = (insn >> 12) & 0xf;
1427 rd0 = (insn >> 0) & 0xf;
1428 rd1 = (insn >> 16) & 0xf;
1429 gen_op_iwmmxt_movq_M0_wRn(rd0);
1430 gen_op_iwmmxt_orq_M0_wRn(rd1);
1431 gen_op_iwmmxt_setpsr_nz();
1432 gen_op_iwmmxt_movq_wRn_M0(wrd);
1433 gen_op_iwmmxt_set_mup();
1434 gen_op_iwmmxt_set_cup();
1435 break;
1436 case 0x011: /* TMCR */
1437 if (insn & 0xf)
1438 return 1;
1439 rd = (insn >> 12) & 0xf;
1440 wrd = (insn >> 16) & 0xf;
1441 switch (wrd) {
1442 case ARM_IWMMXT_wCID:
1443 case ARM_IWMMXT_wCASF:
1444 break;
1445 case ARM_IWMMXT_wCon:
1446 gen_op_iwmmxt_set_cup();
1447 /* Fall through. */
1448 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1449 tmp = iwmmxt_load_creg(wrd);
1450 tmp2 = load_reg(s, rd);
f669df27 1451 tcg_gen_andc_i32(tmp, tmp, tmp2);
da6b5335
FN		 1452 dead_tmp(tmp2);
1453 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1454 break;
1455 case ARM_IWMMXT_wCGR0:
1456 case ARM_IWMMXT_wCGR1:
1457 case ARM_IWMMXT_wCGR2:
1458 case ARM_IWMMXT_wCGR3:
1459 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1460 tmp = load_reg(s, rd);
1461 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1462 break;
1463 default:
1464 return 1;
1465 }
1466 break;
1467 case 0x100: /* WXOR */
1468 wrd = (insn >> 12) & 0xf;
1469 rd0 = (insn >> 0) & 0xf;
1470 rd1 = (insn >> 16) & 0xf;
1471 gen_op_iwmmxt_movq_M0_wRn(rd0);
1472 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1473 gen_op_iwmmxt_setpsr_nz();
1474 gen_op_iwmmxt_movq_wRn_M0(wrd);
1475 gen_op_iwmmxt_set_mup();
1476 gen_op_iwmmxt_set_cup();
1477 break;
1478 case 0x111: /* TMRC */
1479 if (insn & 0xf)
1480 return 1;
1481 rd = (insn >> 12) & 0xf;
1482 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1483 tmp = iwmmxt_load_creg(wrd);
1484 store_reg(s, rd, tmp);
18c9b560
AZ		 1485 break;
1486 case 0x300: /* WANDN */
1487 wrd = (insn >> 12) & 0xf;
1488 rd0 = (insn >> 0) & 0xf;
1489 rd1 = (insn >> 16) & 0xf;
1490 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1491 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1492 gen_op_iwmmxt_andq_M0_wRn(rd1);
1493 gen_op_iwmmxt_setpsr_nz();
1494 gen_op_iwmmxt_movq_wRn_M0(wrd);
1495 gen_op_iwmmxt_set_mup();
1496 gen_op_iwmmxt_set_cup();
1497 break;
1498 case 0x200: /* WAND */
1499 wrd = (insn >> 12) & 0xf;
1500 rd0 = (insn >> 0) & 0xf;
1501 rd1 = (insn >> 16) & 0xf;
1502 gen_op_iwmmxt_movq_M0_wRn(rd0);
1503 gen_op_iwmmxt_andq_M0_wRn(rd1);
1504 gen_op_iwmmxt_setpsr_nz();
1505 gen_op_iwmmxt_movq_wRn_M0(wrd);
1506 gen_op_iwmmxt_set_mup();
1507 gen_op_iwmmxt_set_cup();
1508 break;
1509 case 0x810: case 0xa10: /* WMADD */
1510 wrd = (insn >> 12) & 0xf;
1511 rd0 = (insn >> 0) & 0xf;
1512 rd1 = (insn >> 16) & 0xf;
1513 gen_op_iwmmxt_movq_M0_wRn(rd0);
1514 if (insn & (1 << 21))
1515 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1516 else
1517 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1518 gen_op_iwmmxt_movq_wRn_M0(wrd);
1519 gen_op_iwmmxt_set_mup();
1520 break;
1521 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1522 wrd = (insn >> 12) & 0xf;
1523 rd0 = (insn >> 16) & 0xf;
1524 rd1 = (insn >> 0) & 0xf;
1525 gen_op_iwmmxt_movq_M0_wRn(rd0);
1526 switch ((insn >> 22) & 3) {
1527 case 0:
1528 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1529 break;
1530 case 1:
1531 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1532 break;
1533 case 2:
1534 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1535 break;
1536 case 3:
1537 return 1;
1538 }
1539 gen_op_iwmmxt_movq_wRn_M0(wrd);
1540 gen_op_iwmmxt_set_mup();
1541 gen_op_iwmmxt_set_cup();
1542 break;
1543 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1544 wrd = (insn >> 12) & 0xf;
1545 rd0 = (insn >> 16) & 0xf;
1546 rd1 = (insn >> 0) & 0xf;
1547 gen_op_iwmmxt_movq_M0_wRn(rd0);
1548 switch ((insn >> 22) & 3) {
1549 case 0:
1550 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1551 break;
1552 case 1:
1553 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1554 break;
1555 case 2:
1556 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1557 break;
1558 case 3:
1559 return 1;
1560 }
1561 gen_op_iwmmxt_movq_wRn_M0(wrd);
1562 gen_op_iwmmxt_set_mup();
1563 gen_op_iwmmxt_set_cup();
1564 break;
1565 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1566 wrd = (insn >> 12) & 0xf;
1567 rd0 = (insn >> 16) & 0xf;
1568 rd1 = (insn >> 0) & 0xf;
1569 gen_op_iwmmxt_movq_M0_wRn(rd0);
1570 if (insn & (1 << 22))
1571 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1572 else
1573 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1574 if (!(insn & (1 << 20)))
1575 gen_op_iwmmxt_addl_M0_wRn(wrd);
1576 gen_op_iwmmxt_movq_wRn_M0(wrd);
1577 gen_op_iwmmxt_set_mup();
1578 break;
1579 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1580 wrd = (insn >> 12) & 0xf;
1581 rd0 = (insn >> 16) & 0xf;
1582 rd1 = (insn >> 0) & 0xf;
1583 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1584 if (insn & (1 << 21)) {
1585 if (insn & (1 << 20))
1586 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1587 else
1588 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1589 } else {
1590 if (insn & (1 << 20))
1591 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1592 else
1593 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1594 }
18c9b560
AZ		 1595 gen_op_iwmmxt_movq_wRn_M0(wrd);
1596 gen_op_iwmmxt_set_mup();
1597 break;
1598 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1599 wrd = (insn >> 12) & 0xf;
1600 rd0 = (insn >> 16) & 0xf;
1601 rd1 = (insn >> 0) & 0xf;
1602 gen_op_iwmmxt_movq_M0_wRn(rd0);
1603 if (insn & (1 << 21))
1604 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1605 else
1606 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1607 if (!(insn & (1 << 20))) {
e677137d
PB		 1608 iwmmxt_load_reg(cpu_V1, wrd);
1609 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1610 }
1611 gen_op_iwmmxt_movq_wRn_M0(wrd);
1612 gen_op_iwmmxt_set_mup();
1613 break;
1614 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1615 wrd = (insn >> 12) & 0xf;
1616 rd0 = (insn >> 16) & 0xf;
1617 rd1 = (insn >> 0) & 0xf;
1618 gen_op_iwmmxt_movq_M0_wRn(rd0);
1619 switch ((insn >> 22) & 3) {
1620 case 0:
1621 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1622 break;
1623 case 1:
1624 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1625 break;
1626 case 2:
1627 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1628 break;
1629 case 3:
1630 return 1;
1631 }
1632 gen_op_iwmmxt_movq_wRn_M0(wrd);
1633 gen_op_iwmmxt_set_mup();
1634 gen_op_iwmmxt_set_cup();
1635 break;
1636 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1637 wrd = (insn >> 12) & 0xf;
1638 rd0 = (insn >> 16) & 0xf;
1639 rd1 = (insn >> 0) & 0xf;
1640 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1641 if (insn & (1 << 22)) {
1642 if (insn & (1 << 20))
1643 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1644 else
1645 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1646 } else {
1647 if (insn & (1 << 20))
1648 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1649 else
1650 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1651 }
18c9b560
AZ		 1652 gen_op_iwmmxt_movq_wRn_M0(wrd);
1653 gen_op_iwmmxt_set_mup();
1654 gen_op_iwmmxt_set_cup();
1655 break;
1656 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1657 wrd = (insn >> 12) & 0xf;
1658 rd0 = (insn >> 16) & 0xf;
1659 rd1 = (insn >> 0) & 0xf;
1660 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1661 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1662 tcg_gen_andi_i32(tmp, tmp, 7);
1663 iwmmxt_load_reg(cpu_V1, rd1);
1664 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1665 dead_tmp(tmp);
18c9b560
AZ		 1666 gen_op_iwmmxt_movq_wRn_M0(wrd);
1667 gen_op_iwmmxt_set_mup();
1668 break;
1669 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1670 if (((insn >> 6) & 3) == 3)
1671 return 1;
18c9b560
AZ		 1672 rd = (insn >> 12) & 0xf;
1673 wrd = (insn >> 16) & 0xf;
da6b5335 1674 tmp = load_reg(s, rd);
18c9b560
AZ		 1675 gen_op_iwmmxt_movq_M0_wRn(wrd);
1676 switch ((insn >> 6) & 3) {
1677 case 0:
da6b5335
FN		 1678 tmp2 = tcg_const_i32(0xff);
1679 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1680 break;
1681 case 1:
da6b5335
FN		 1682 tmp2 = tcg_const_i32(0xffff);
1683 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1684 break;
1685 case 2:
da6b5335
FN		 1686 tmp2 = tcg_const_i32(0xffffffff);
1687 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1688 break;
da6b5335
FN		 1689 default:
1690 TCGV_UNUSED(tmp2);
1691 TCGV_UNUSED(tmp3);
18c9b560 1692 }
da6b5335
FN		 1693 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1694 tcg_temp_free(tmp3);
1695 tcg_temp_free(tmp2);
1696 dead_tmp(tmp);
18c9b560
AZ		 1697 gen_op_iwmmxt_movq_wRn_M0(wrd);
1698 gen_op_iwmmxt_set_mup();
1699 break;
1700 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1701 rd = (insn >> 12) & 0xf;
1702 wrd = (insn >> 16) & 0xf;
da6b5335 1703 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1704 return 1;
1705 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335 1706 tmp = new_tmp();
18c9b560
AZ		 1707 switch ((insn >> 22) & 3) {
1708 case 0:
da6b5335
FN		 1709 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1710 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1711 if (insn & 8) {
1712 tcg_gen_ext8s_i32(tmp, tmp);
1713 } else {
1714 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1715 }
1716 break;
1717 case 1:
da6b5335
FN		 1718 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1719 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1720 if (insn & 8) {
1721 tcg_gen_ext16s_i32(tmp, tmp);
1722 } else {
1723 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1724 }
1725 break;
1726 case 2:
da6b5335
FN		 1727 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1728 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1729 break;
18c9b560 1730 }
da6b5335 1731 store_reg(s, rd, tmp);
18c9b560
AZ		 1732 break;
1733 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1734 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1735 return 1;
da6b5335 1736 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1737 switch ((insn >> 22) & 3) {
1738 case 0:
da6b5335 1739 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1740 break;
1741 case 1:
da6b5335 1742 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1743 break;
1744 case 2:
da6b5335 1745 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1746 break;
18c9b560 1747 }
da6b5335
FN		 1748 tcg_gen_shli_i32(tmp, tmp, 28);
1749 gen_set_nzcv(tmp);
1750 dead_tmp(tmp);
18c9b560
AZ		 1751 break;
1752 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1753 if (((insn >> 6) & 3) == 3)
1754 return 1;
18c9b560
AZ		 1755 rd = (insn >> 12) & 0xf;
1756 wrd = (insn >> 16) & 0xf;
da6b5335 1757 tmp = load_reg(s, rd);
18c9b560
AZ		 1758 switch ((insn >> 6) & 3) {
1759 case 0:
da6b5335 1760 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1761 break;
1762 case 1:
da6b5335 1763 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1764 break;
1765 case 2:
da6b5335 1766 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1767 break;
18c9b560 1768 }
da6b5335 1769 dead_tmp(tmp);
18c9b560
AZ		 1770 gen_op_iwmmxt_movq_wRn_M0(wrd);
1771 gen_op_iwmmxt_set_mup();
1772 break;
1773 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1774 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1775 return 1;
da6b5335
FN		 1776 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1777 tmp2 = new_tmp();
1778 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1779 switch ((insn >> 22) & 3) {
1780 case 0:
1781 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1782 tcg_gen_shli_i32(tmp2, tmp2, 4);
1783 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1784 }
1785 break;
1786 case 1:
1787 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1788 tcg_gen_shli_i32(tmp2, tmp2, 8);
1789 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1790 }
1791 break;
1792 case 2:
da6b5335
FN		 1793 tcg_gen_shli_i32(tmp2, tmp2, 16);
1794 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1795 break;
18c9b560 1796 }
da6b5335
FN		 1797 gen_set_nzcv(tmp);
1798 dead_tmp(tmp2);
1799 dead_tmp(tmp);
18c9b560
AZ		 1800 break;
1801 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1802 wrd = (insn >> 12) & 0xf;
1803 rd0 = (insn >> 16) & 0xf;
1804 gen_op_iwmmxt_movq_M0_wRn(rd0);
1805 switch ((insn >> 22) & 3) {
1806 case 0:
e677137d 1807 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1808 break;
1809 case 1:
e677137d 1810 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1811 break;
1812 case 2:
e677137d 1813 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1814 break;
1815 case 3:
1816 return 1;
1817 }
1818 gen_op_iwmmxt_movq_wRn_M0(wrd);
1819 gen_op_iwmmxt_set_mup();
1820 break;
1821 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1822 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1823 return 1;
da6b5335
FN		 1824 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1825 tmp2 = new_tmp();
1826 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1827 switch ((insn >> 22) & 3) {
1828 case 0:
1829 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1830 tcg_gen_shli_i32(tmp2, tmp2, 4);
1831 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1832 }
1833 break;
1834 case 1:
1835 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1836 tcg_gen_shli_i32(tmp2, tmp2, 8);
1837 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1838 }
1839 break;
1840 case 2:
da6b5335
FN		 1841 tcg_gen_shli_i32(tmp2, tmp2, 16);
1842 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1843 break;
18c9b560 1844 }
da6b5335
FN		 1845 gen_set_nzcv(tmp);
1846 dead_tmp(tmp2);
1847 dead_tmp(tmp);
18c9b560
AZ		 1848 break;
1849 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1850 rd = (insn >> 12) & 0xf;
1851 rd0 = (insn >> 16) & 0xf;
da6b5335 1852 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1853 return 1;
1854 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 1855 tmp = new_tmp();
18c9b560
AZ		 1856 switch ((insn >> 22) & 3) {
1857 case 0:
da6b5335 1858 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1859 break;
1860 case 1:
da6b5335 1861 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1862 break;
1863 case 2:
da6b5335 1864 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1865 break;
18c9b560 1866 }
da6b5335 1867 store_reg(s, rd, tmp);
18c9b560
AZ		 1868 break;
1869 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1870 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1871 wrd = (insn >> 12) & 0xf;
1872 rd0 = (insn >> 16) & 0xf;
1873 rd1 = (insn >> 0) & 0xf;
1874 gen_op_iwmmxt_movq_M0_wRn(rd0);
1875 switch ((insn >> 22) & 3) {
1876 case 0:
1877 if (insn & (1 << 21))
1878 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1879 else
1880 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1881 break;
1882 case 1:
1883 if (insn & (1 << 21))
1884 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1885 else
1886 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1887 break;
1888 case 2:
1889 if (insn & (1 << 21))
1890 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1891 else
1892 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1893 break;
1894 case 3:
1895 return 1;
1896 }
1897 gen_op_iwmmxt_movq_wRn_M0(wrd);
1898 gen_op_iwmmxt_set_mup();
1899 gen_op_iwmmxt_set_cup();
1900 break;
1901 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1902 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1903 wrd = (insn >> 12) & 0xf;
1904 rd0 = (insn >> 16) & 0xf;
1905 gen_op_iwmmxt_movq_M0_wRn(rd0);
1906 switch ((insn >> 22) & 3) {
1907 case 0:
1908 if (insn & (1 << 21))
1909 gen_op_iwmmxt_unpacklsb_M0();
1910 else
1911 gen_op_iwmmxt_unpacklub_M0();
1912 break;
1913 case 1:
1914 if (insn & (1 << 21))
1915 gen_op_iwmmxt_unpacklsw_M0();
1916 else
1917 gen_op_iwmmxt_unpackluw_M0();
1918 break;
1919 case 2:
1920 if (insn & (1 << 21))
1921 gen_op_iwmmxt_unpacklsl_M0();
1922 else
1923 gen_op_iwmmxt_unpacklul_M0();
1924 break;
1925 case 3:
1926 return 1;
1927 }
1928 gen_op_iwmmxt_movq_wRn_M0(wrd);
1929 gen_op_iwmmxt_set_mup();
1930 gen_op_iwmmxt_set_cup();
1931 break;
1932 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1933 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1934 wrd = (insn >> 12) & 0xf;
1935 rd0 = (insn >> 16) & 0xf;
1936 gen_op_iwmmxt_movq_M0_wRn(rd0);
1937 switch ((insn >> 22) & 3) {
1938 case 0:
1939 if (insn & (1 << 21))
1940 gen_op_iwmmxt_unpackhsb_M0();
1941 else
1942 gen_op_iwmmxt_unpackhub_M0();
1943 break;
1944 case 1:
1945 if (insn & (1 << 21))
1946 gen_op_iwmmxt_unpackhsw_M0();
1947 else
1948 gen_op_iwmmxt_unpackhuw_M0();
1949 break;
1950 case 2:
1951 if (insn & (1 << 21))
1952 gen_op_iwmmxt_unpackhsl_M0();
1953 else
1954 gen_op_iwmmxt_unpackhul_M0();
1955 break;
1956 case 3:
1957 return 1;
1958 }
1959 gen_op_iwmmxt_movq_wRn_M0(wrd);
1960 gen_op_iwmmxt_set_mup();
1961 gen_op_iwmmxt_set_cup();
1962 break;
1963 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1964 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1965 if (((insn >> 22) & 3) == 0)
1966 return 1;
18c9b560
AZ		 1967 wrd = (insn >> 12) & 0xf;
1968 rd0 = (insn >> 16) & 0xf;
1969 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1970 tmp = new_tmp();
1971 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1972 dead_tmp(tmp);
18c9b560 1973 return 1;
da6b5335 1974 }
18c9b560 1975 switch ((insn >> 22) & 3) {
18c9b560 1976 case 1:
da6b5335 1977 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1978 break;
1979 case 2:
da6b5335 1980 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1981 break;
1982 case 3:
da6b5335 1983 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1984 break;
1985 }
da6b5335 1986 dead_tmp(tmp);
18c9b560
AZ		 1987 gen_op_iwmmxt_movq_wRn_M0(wrd);
1988 gen_op_iwmmxt_set_mup();
1989 gen_op_iwmmxt_set_cup();
1990 break;
1991 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1992 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 1993 if (((insn >> 22) & 3) == 0)
1994 return 1;
18c9b560
AZ		 1995 wrd = (insn >> 12) & 0xf;
1996 rd0 = (insn >> 16) & 0xf;
1997 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1998 tmp = new_tmp();
1999 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2000 dead_tmp(tmp);
18c9b560 2001 return 1;
da6b5335 2002 }
18c9b560 2003 switch ((insn >> 22) & 3) {
18c9b560 2004 case 1:
da6b5335 2005 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2006 break;
2007 case 2:
da6b5335 2008 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2009 break;
2010 case 3:
da6b5335 2011 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2012 break;
2013 }
da6b5335 2014 dead_tmp(tmp);
18c9b560
AZ		 2015 gen_op_iwmmxt_movq_wRn_M0(wrd);
2016 gen_op_iwmmxt_set_mup();
2017 gen_op_iwmmxt_set_cup();
2018 break;
2019 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2020 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2021 if (((insn >> 22) & 3) == 0)
2022 return 1;
18c9b560
AZ		 2023 wrd = (insn >> 12) & 0xf;
2024 rd0 = (insn >> 16) & 0xf;
2025 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2026 tmp = new_tmp();
2027 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2028 dead_tmp(tmp);
18c9b560 2029 return 1;
da6b5335 2030 }
18c9b560 2031 switch ((insn >> 22) & 3) {
18c9b560 2032 case 1:
da6b5335 2033 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2034 break;
2035 case 2:
da6b5335 2036 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2037 break;
2038 case 3:
da6b5335 2039 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2040 break;
2041 }
da6b5335 2042 dead_tmp(tmp);
18c9b560
AZ		 2043 gen_op_iwmmxt_movq_wRn_M0(wrd);
2044 gen_op_iwmmxt_set_mup();
2045 gen_op_iwmmxt_set_cup();
2046 break;
2047 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2048 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2049 if (((insn >> 22) & 3) == 0)
2050 return 1;
18c9b560
AZ		 2051 wrd = (insn >> 12) & 0xf;
2052 rd0 = (insn >> 16) & 0xf;
2053 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2054 tmp = new_tmp();
18c9b560 2055 switch ((insn >> 22) & 3) {
18c9b560 2056 case 1:
da6b5335
FN		 2057 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2058 dead_tmp(tmp);
18c9b560 2059 return 1;
da6b5335
FN		 2060 }
2061 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2062 break;
2063 case 2:
da6b5335
FN		 2064 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2065 dead_tmp(tmp);
18c9b560 2066 return 1;
da6b5335
FN		 2067 }
2068 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2069 break;
2070 case 3:
da6b5335
FN		 2071 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2072 dead_tmp(tmp);
18c9b560 2073 return 1;
da6b5335
FN		 2074 }
2075 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2076 break;
2077 }
da6b5335 2078 dead_tmp(tmp);
18c9b560
AZ		 2079 gen_op_iwmmxt_movq_wRn_M0(wrd);
2080 gen_op_iwmmxt_set_mup();
2081 gen_op_iwmmxt_set_cup();
2082 break;
2083 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2084 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2085 wrd = (insn >> 12) & 0xf;
2086 rd0 = (insn >> 16) & 0xf;
2087 rd1 = (insn >> 0) & 0xf;
2088 gen_op_iwmmxt_movq_M0_wRn(rd0);
2089 switch ((insn >> 22) & 3) {
2090 case 0:
2091 if (insn & (1 << 21))
2092 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2093 else
2094 gen_op_iwmmxt_minub_M0_wRn(rd1);
2095 break;
2096 case 1:
2097 if (insn & (1 << 21))
2098 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2099 else
2100 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2101 break;
2102 case 2:
2103 if (insn & (1 << 21))
2104 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2105 else
2106 gen_op_iwmmxt_minul_M0_wRn(rd1);
2107 break;
2108 case 3:
2109 return 1;
2110 }
2111 gen_op_iwmmxt_movq_wRn_M0(wrd);
2112 gen_op_iwmmxt_set_mup();
2113 break;
2114 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2115 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2116 wrd = (insn >> 12) & 0xf;
2117 rd0 = (insn >> 16) & 0xf;
2118 rd1 = (insn >> 0) & 0xf;
2119 gen_op_iwmmxt_movq_M0_wRn(rd0);
2120 switch ((insn >> 22) & 3) {
2121 case 0:
2122 if (insn & (1 << 21))
2123 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2124 else
2125 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2126 break;
2127 case 1:
2128 if (insn & (1 << 21))
2129 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2130 else
2131 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2132 break;
2133 case 2:
2134 if (insn & (1 << 21))
2135 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2136 else
2137 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2138 break;
2139 case 3:
2140 return 1;
2141 }
2142 gen_op_iwmmxt_movq_wRn_M0(wrd);
2143 gen_op_iwmmxt_set_mup();
2144 break;
2145 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2146 case 0x402: case 0x502: case 0x602: case 0x702:
2147 wrd = (insn >> 12) & 0xf;
2148 rd0 = (insn >> 16) & 0xf;
2149 rd1 = (insn >> 0) & 0xf;
2150 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2151 tmp = tcg_const_i32((insn >> 20) & 3);
2152 iwmmxt_load_reg(cpu_V1, rd1);
2153 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2154 tcg_temp_free(tmp);
18c9b560
AZ		 2155 gen_op_iwmmxt_movq_wRn_M0(wrd);
2156 gen_op_iwmmxt_set_mup();
2157 break;
2158 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2159 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2160 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2161 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2162 wrd = (insn >> 12) & 0xf;
2163 rd0 = (insn >> 16) & 0xf;
2164 rd1 = (insn >> 0) & 0xf;
2165 gen_op_iwmmxt_movq_M0_wRn(rd0);
2166 switch ((insn >> 20) & 0xf) {
2167 case 0x0:
2168 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2169 break;
2170 case 0x1:
2171 gen_op_iwmmxt_subub_M0_wRn(rd1);
2172 break;
2173 case 0x3:
2174 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2175 break;
2176 case 0x4:
2177 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2178 break;
2179 case 0x5:
2180 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2181 break;
2182 case 0x7:
2183 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2184 break;
2185 case 0x8:
2186 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2187 break;
2188 case 0x9:
2189 gen_op_iwmmxt_subul_M0_wRn(rd1);
2190 break;
2191 case 0xb:
2192 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2193 break;
2194 default:
2195 return 1;
2196 }
2197 gen_op_iwmmxt_movq_wRn_M0(wrd);
2198 gen_op_iwmmxt_set_mup();
2199 gen_op_iwmmxt_set_cup();
2200 break;
2201 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2202 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2203 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2204 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2205 wrd = (insn >> 12) & 0xf;
2206 rd0 = (insn >> 16) & 0xf;
2207 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2208 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2209 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2210 tcg_temp_free(tmp);
18c9b560
AZ		 2211 gen_op_iwmmxt_movq_wRn_M0(wrd);
2212 gen_op_iwmmxt_set_mup();
2213 gen_op_iwmmxt_set_cup();
2214 break;
2215 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2216 case 0x418: case 0x518: case 0x618: case 0x718:
2217 case 0x818: case 0x918: case 0xa18: case 0xb18:
2218 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2219 wrd = (insn >> 12) & 0xf;
2220 rd0 = (insn >> 16) & 0xf;
2221 rd1 = (insn >> 0) & 0xf;
2222 gen_op_iwmmxt_movq_M0_wRn(rd0);
2223 switch ((insn >> 20) & 0xf) {
2224 case 0x0:
2225 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2226 break;
2227 case 0x1:
2228 gen_op_iwmmxt_addub_M0_wRn(rd1);
2229 break;
2230 case 0x3:
2231 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2232 break;
2233 case 0x4:
2234 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2235 break;
2236 case 0x5:
2237 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2238 break;
2239 case 0x7:
2240 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2241 break;
2242 case 0x8:
2243 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2244 break;
2245 case 0x9:
2246 gen_op_iwmmxt_addul_M0_wRn(rd1);
2247 break;
2248 case 0xb:
2249 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2250 break;
2251 default:
2252 return 1;
2253 }
2254 gen_op_iwmmxt_movq_wRn_M0(wrd);
2255 gen_op_iwmmxt_set_mup();
2256 gen_op_iwmmxt_set_cup();
2257 break;
2258 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2259 case 0x408: case 0x508: case 0x608: case 0x708:
2260 case 0x808: case 0x908: case 0xa08: case 0xb08:
2261 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2262 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2263 return 1;
18c9b560
AZ		 2264 wrd = (insn >> 12) & 0xf;
2265 rd0 = (insn >> 16) & 0xf;
2266 rd1 = (insn >> 0) & 0xf;
2267 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2268 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2269 case 1:
2270 if (insn & (1 << 21))
2271 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2272 else
2273 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2274 break;
2275 case 2:
2276 if (insn & (1 << 21))
2277 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2278 else
2279 gen_op_iwmmxt_packul_M0_wRn(rd1);
2280 break;
2281 case 3:
2282 if (insn & (1 << 21))
2283 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2284 else
2285 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2286 break;
2287 }
2288 gen_op_iwmmxt_movq_wRn_M0(wrd);
2289 gen_op_iwmmxt_set_mup();
2290 gen_op_iwmmxt_set_cup();
2291 break;
2292 case 0x201: case 0x203: case 0x205: case 0x207:
2293 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2294 case 0x211: case 0x213: case 0x215: case 0x217:
2295 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2296 wrd = (insn >> 5) & 0xf;
2297 rd0 = (insn >> 12) & 0xf;
2298 rd1 = (insn >> 0) & 0xf;
2299 if (rd0 == 0xf || rd1 == 0xf)
2300 return 1;
2301 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2302 tmp = load_reg(s, rd0);
2303 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2304 switch ((insn >> 16) & 0xf) {
2305 case 0x0: /* TMIA */
da6b5335 2306 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2307 break;
2308 case 0x8: /* TMIAPH */
da6b5335 2309 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2310 break;
2311 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2312 if (insn & (1 << 16))
da6b5335 2313 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2314 if (insn & (1 << 17))
da6b5335
FN		 2315 tcg_gen_shri_i32(tmp2, tmp2, 16);
2316 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2317 break;
2318 default:
da6b5335
FN		 2319 dead_tmp(tmp2);
2320 dead_tmp(tmp);
18c9b560
AZ		 2321 return 1;
2322 }
da6b5335
FN		 2323 dead_tmp(tmp2);
2324 dead_tmp(tmp);
18c9b560
AZ		 2325 gen_op_iwmmxt_movq_wRn_M0(wrd);
2326 gen_op_iwmmxt_set_mup();
2327 break;
2328 default:
2329 return 1;
2330 }
2331
2332 return 0;
2333}
2334
2335/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2336 (ie. an undefined instruction). */
2337static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2338{
2339 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2340 TCGv tmp, tmp2;
18c9b560
AZ		 2341
2342 if ((insn & 0x0ff00f10) == 0x0e200010) {
2343 /* Multiply with Internal Accumulate Format */
2344 rd0 = (insn >> 12) & 0xf;
2345 rd1 = insn & 0xf;
2346 acc = (insn >> 5) & 7;
2347
2348 if (acc != 0)
2349 return 1;
2350
3a554c0f
FN		 2351 tmp = load_reg(s, rd0);
2352 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2353 switch ((insn >> 16) & 0xf) {
2354 case 0x0: /* MIA */
3a554c0f 2355 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2356 break;
2357 case 0x8: /* MIAPH */
3a554c0f 2358 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2359 break;
2360 case 0xc: /* MIABB */
2361 case 0xd: /* MIABT */
2362 case 0xe: /* MIATB */
2363 case 0xf: /* MIATT */
18c9b560 2364 if (insn & (1 << 16))
3a554c0f 2365 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2366 if (insn & (1 << 17))
3a554c0f
FN		 2367 tcg_gen_shri_i32(tmp2, tmp2, 16);
2368 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2369 break;
2370 default:
2371 return 1;
2372 }
3a554c0f
FN		 2373 dead_tmp(tmp2);
2374 dead_tmp(tmp);
18c9b560
AZ		 2375
2376 gen_op_iwmmxt_movq_wRn_M0(acc);
2377 return 0;
2378 }
2379
2380 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2381 /* Internal Accumulator Access Format */
2382 rdhi = (insn >> 16) & 0xf;
2383 rdlo = (insn >> 12) & 0xf;
2384 acc = insn & 7;
2385
2386 if (acc != 0)
2387 return 1;
2388
2389 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2390 iwmmxt_load_reg(cpu_V0, acc);
2391 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2392 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2393 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2394 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2395 } else { /* MAR */
3a554c0f
FN		 2396 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2397 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2398 }
2399 return 0;
2400 }
2401
2402 return 1;
2403}
2404
c1713132
AZ		 2405/* Disassemble system coprocessor instruction. Return nonzero if
2406 instruction is not defined. */
2407static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2408{
b75263d6 2409 TCGv tmp, tmp2;
c1713132
AZ		 2410 uint32_t rd = (insn >> 12) & 0xf;
2411 uint32_t cp = (insn >> 8) & 0xf;
2412 if (IS_USER(s)) {
2413 return 1;
2414 }
2415
18c9b560 2416 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2417 if (!env->cp[cp].cp_read)
2418 return 1;
8984bd2e
PB		 2419 gen_set_pc_im(s->pc);
2420 tmp = new_tmp();
b75263d6
JR		 2421 tmp2 = tcg_const_i32(insn);
2422 gen_helper_get_cp(tmp, cpu_env, tmp2);
2423 tcg_temp_free(tmp2);
8984bd2e 2424 store_reg(s, rd, tmp);
c1713132
AZ		 2425 } else {
2426 if (!env->cp[cp].cp_write)
2427 return 1;
8984bd2e
PB		 2428 gen_set_pc_im(s->pc);
2429 tmp = load_reg(s, rd);
b75263d6
JR		 2430 tmp2 = tcg_const_i32(insn);
2431 gen_helper_set_cp(cpu_env, tmp2, tmp);
2432 tcg_temp_free(tmp2);
a60de947 2433 dead_tmp(tmp);
c1713132
AZ		 2434 }
2435 return 0;
2436}
2437
9ee6e8bb
PB		 2438static int cp15_user_ok(uint32_t insn)
2439{
2440 int cpn = (insn >> 16) & 0xf;
2441 int cpm = insn & 0xf;
2442 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2443
2444 if (cpn == 13 && cpm == 0) {
2445 /* TLS register. */
2446 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2447 return 1;
2448 }
2449 if (cpn == 7) {
2450 /* ISB, DSB, DMB. */
2451 if ((cpm == 5 && op == 4)
2452 || (cpm == 10 && (op == 4 || op == 5)))
2453 return 1;
2454 }
2455 return 0;
2456}
2457
3f26c122
RV		 2458static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2459{
2460 TCGv tmp;
2461 int cpn = (insn >> 16) & 0xf;
2462 int cpm = insn & 0xf;
2463 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2464
2465 if (!arm_feature(env, ARM_FEATURE_V6K))
2466 return 0;
2467
2468 if (!(cpn == 13 && cpm == 0))
2469 return 0;
2470
2471 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2472 switch (op) {
2473 case 2:
c5883be2 2474 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2475 break;
2476 case 3:
c5883be2 2477 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2478 break;
2479 case 4:
c5883be2 2480 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2481 break;
2482 default:
3f26c122
RV		 2483 return 0;
2484 }
2485 store_reg(s, rd, tmp);
2486
2487 } else {
2488 tmp = load_reg(s, rd);
2489 switch (op) {
2490 case 2:
c5883be2 2491 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2492 break;
2493 case 3:
c5883be2 2494 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2495 break;
2496 case 4:
c5883be2 2497 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2498 break;
2499 default:
c5883be2 2500 dead_tmp(tmp);
3f26c122
RV		 2501 return 0;
2502 }
3f26c122
RV		 2503 }
2504 return 1;
2505}
2506
b5ff1b31
FB		 2507/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2508 instruction is not defined. */
a90b7318 2509static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2510{
2511 uint32_t rd;
b75263d6 2512 TCGv tmp, tmp2;
b5ff1b31 2513
9ee6e8bb
PB		 2514 /* M profile cores use memory mapped registers instead of cp15. */
2515 if (arm_feature(env, ARM_FEATURE_M))
2516 return 1;
2517
2518 if ((insn & (1 << 25)) == 0) {
2519 if (insn & (1 << 20)) {
2520 /* mrrc */
2521 return 1;
2522 }
2523 /* mcrr. Used for block cache operations, so implement as no-op. */
2524 return 0;
2525 }
2526 if ((insn & (1 << 4)) == 0) {
2527 /* cdp */
2528 return 1;
2529 }
2530 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2531 return 1;
2532 }
9332f9da
FB		 2533 if ((insn & 0x0fff0fff) == 0x0e070f90
2534 || (insn & 0x0fff0fff) == 0x0e070f58) {
2535 /* Wait for interrupt. */
8984bd2e 2536 gen_set_pc_im(s->pc);
9ee6e8bb 2537 s->is_jmp = DISAS_WFI;
9332f9da
FB		 2538 return 0;
2539 }
b5ff1b31 2540 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2541
2542 if (cp15_tls_load_store(env, s, insn, rd))
2543 return 0;
2544
b75263d6 2545 tmp2 = tcg_const_i32(insn);
18c9b560 2546 if (insn & ARM_CP_RW_BIT) {
8984bd2e 2547 tmp = new_tmp();
b75263d6 2548 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2549 /* If the destination register is r15 then sets condition codes. */
2550 if (rd != 15)
8984bd2e
PB		 2551 store_reg(s, rd, tmp);
2552 else
2553 dead_tmp(tmp);
b5ff1b31 2554 } else {
8984bd2e 2555 tmp = load_reg(s, rd);
b75263d6 2556 gen_helper_set_cp15(cpu_env, tmp2, tmp);
8984bd2e 2557 dead_tmp(tmp);
a90b7318
AZ		 2558 /* Normally we would always end the TB here, but Linux
2559 * arch/arm/mach-pxa/sleep.S expects two instructions following
2560 * an MMU enable to execute from cache. Imitate this behaviour. */
2561 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2562 (insn & 0x0fff0fff) != 0x0e010f10)
2563 gen_lookup_tb(s);
b5ff1b31 2564 }
b75263d6 2565 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2566 return 0;
2567}
2568
9ee6e8bb
PB		 2569#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2570#define VFP_SREG(insn, bigbit, smallbit) \
2571 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2572#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2573 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2574 reg = (((insn) >> (bigbit)) & 0x0f) \
2575 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2576 } else { \
2577 if (insn & (1 << (smallbit))) \
2578 return 1; \
2579 reg = ((insn) >> (bigbit)) & 0x0f; \
2580 }} while (0)
2581
2582#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2583#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2584#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2585#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2586#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2587#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2588
4373f3ce
PB		 2589/* Move between integer and VFP cores. */
2590static TCGv gen_vfp_mrs(void)
2591{
2592 TCGv tmp = new_tmp();
2593 tcg_gen_mov_i32(tmp, cpu_F0s);
2594 return tmp;
2595}
2596
2597static void gen_vfp_msr(TCGv tmp)
2598{
2599 tcg_gen_mov_i32(cpu_F0s, tmp);
2600 dead_tmp(tmp);
2601}
2602
9ee6e8bb
PB		 2603static inline int
2604vfp_enabled(CPUState * env)
2605{
2606 return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0);
2607}
2608
ad69471c
PB		 2609static void gen_neon_dup_u8(TCGv var, int shift)
2610{
2611 TCGv tmp = new_tmp();
2612 if (shift)
2613 tcg_gen_shri_i32(var, var, shift);
86831435 2614 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2615 tcg_gen_shli_i32(tmp, var, 8);
2616 tcg_gen_or_i32(var, var, tmp);
2617 tcg_gen_shli_i32(tmp, var, 16);
2618 tcg_gen_or_i32(var, var, tmp);
2619 dead_tmp(tmp);
2620}
2621
2622static void gen_neon_dup_low16(TCGv var)
2623{
2624 TCGv tmp = new_tmp();
86831435 2625 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2626 tcg_gen_shli_i32(tmp, var, 16);
2627 tcg_gen_or_i32(var, var, tmp);
2628 dead_tmp(tmp);
2629}
2630
2631static void gen_neon_dup_high16(TCGv var)
2632{
2633 TCGv tmp = new_tmp();
2634 tcg_gen_andi_i32(var, var, 0xffff0000);
2635 tcg_gen_shri_i32(tmp, var, 16);
2636 tcg_gen_or_i32(var, var, tmp);
2637 dead_tmp(tmp);
2638}
2639
b7bcbe95
FB		 2640/* Disassemble a VFP instruction. Returns nonzero if an error occured
2641 (ie. an undefined instruction). */
2642static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2643{
2644 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2645 int dp, veclen;
312eea9f 2646 TCGv addr;
4373f3ce 2647 TCGv tmp;
ad69471c 2648 TCGv tmp2;
b7bcbe95 2649
40f137e1
PB		 2650 if (!arm_feature(env, ARM_FEATURE_VFP))
2651 return 1;
2652
9ee6e8bb
PB		 2653 if (!vfp_enabled(env)) {
2654 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2655 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2656 return 1;
2657 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2658 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2659 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2660 return 1;
2661 }
b7bcbe95
FB		 2662 dp = ((insn & 0xf00) == 0xb00);
2663 switch ((insn >> 24) & 0xf) {
2664 case 0xe:
2665 if (insn & (1 << 4)) {
2666 /* single register transfer */
b7bcbe95
FB		 2667 rd = (insn >> 12) & 0xf;
2668 if (dp) {
9ee6e8bb
PB		 2669 int size;
2670 int pass;
2671
2672 VFP_DREG_N(rn, insn);
2673 if (insn & 0xf)
b7bcbe95 2674 return 1;
9ee6e8bb
PB		 2675 if (insn & 0x00c00060
2676 && !arm_feature(env, ARM_FEATURE_NEON))
2677 return 1;
2678
2679 pass = (insn >> 21) & 1;
2680 if (insn & (1 << 22)) {
2681 size = 0;
2682 offset = ((insn >> 5) & 3) * 8;
2683 } else if (insn & (1 << 5)) {
2684 size = 1;
2685 offset = (insn & (1 << 6)) ? 16 : 0;
2686 } else {
2687 size = 2;
2688 offset = 0;
2689 }
18c9b560 2690 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2691 /* vfp->arm */
ad69471c 2692 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2693 switch (size) {
2694 case 0:
9ee6e8bb 2695 if (offset)
ad69471c 2696 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2697 if (insn & (1 << 23))
ad69471c 2698 gen_uxtb(tmp);
9ee6e8bb 2699 else
ad69471c 2700 gen_sxtb(tmp);
9ee6e8bb
PB		 2701 break;
2702 case 1:
9ee6e8bb
PB		 2703 if (insn & (1 << 23)) {
2704 if (offset) {
ad69471c 2705 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2706 } else {
ad69471c 2707 gen_uxth(tmp);
9ee6e8bb
PB		 2708 }
2709 } else {
2710 if (offset) {
ad69471c 2711 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2712 } else {
ad69471c 2713 gen_sxth(tmp);
9ee6e8bb
PB		 2714 }
2715 }
2716 break;
2717 case 2:
9ee6e8bb
PB		 2718 break;
2719 }
ad69471c 2720 store_reg(s, rd, tmp);
b7bcbe95
FB		 2721 } else {
2722 /* arm->vfp */
ad69471c 2723 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2724 if (insn & (1 << 23)) {
2725 /* VDUP */
2726 if (size == 0) {
ad69471c 2727 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2728 } else if (size == 1) {
ad69471c 2729 gen_neon_dup_low16(tmp);
9ee6e8bb 2730 }
cbbccffc
PB		 2731 for (n = 0; n <= pass * 2; n++) {
2732 tmp2 = new_tmp();
2733 tcg_gen_mov_i32(tmp2, tmp);
2734 neon_store_reg(rn, n, tmp2);
2735 }
2736 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2737 } else {
2738 /* VMOV */
2739 switch (size) {
2740 case 0:
ad69471c
PB		 2741 tmp2 = neon_load_reg(rn, pass);
2742 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2743 dead_tmp(tmp2);
9ee6e8bb
PB		 2744 break;
2745 case 1:
ad69471c
PB		 2746 tmp2 = neon_load_reg(rn, pass);
2747 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2748 dead_tmp(tmp2);
9ee6e8bb
PB		 2749 break;
2750 case 2:
9ee6e8bb
PB		 2751 break;
2752 }
ad69471c 2753 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2754 }
b7bcbe95 2755 }
9ee6e8bb
PB		 2756 } else { /* !dp */
2757 if ((insn & 0x6f) != 0x00)
2758 return 1;
2759 rn = VFP_SREG_N(insn);
18c9b560 2760 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2761 /* vfp->arm */
2762 if (insn & (1 << 21)) {
2763 /* system register */
40f137e1 2764 rn >>= 1;
9ee6e8bb 2765
b7bcbe95 2766 switch (rn) {
40f137e1 2767 case ARM_VFP_FPSID:
4373f3ce 2768 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2769 VFP3 restricts all id registers to privileged
2770 accesses. */
2771 if (IS_USER(s)
2772 && arm_feature(env, ARM_FEATURE_VFP3))
2773 return 1;
4373f3ce 2774 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2775 break;
40f137e1 2776 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2777 if (IS_USER(s))
2778 return 1;
4373f3ce 2779 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2780 break;
40f137e1
PB		 2781 case ARM_VFP_FPINST:
2782 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2783 /* Not present in VFP3. */
2784 if (IS_USER(s)
2785 || arm_feature(env, ARM_FEATURE_VFP3))
2786 return 1;
4373f3ce 2787 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2788 break;
40f137e1 2789 case ARM_VFP_FPSCR:
601d70b9 2790 if (rd == 15) {
4373f3ce
PB		 2791 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2792 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2793 } else {
2794 tmp = new_tmp();
2795 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2796 }
b7bcbe95 2797 break;
9ee6e8bb
PB		 2798 case ARM_VFP_MVFR0:
2799 case ARM_VFP_MVFR1:
2800 if (IS_USER(s)
2801 || !arm_feature(env, ARM_FEATURE_VFP3))
2802 return 1;
4373f3ce 2803 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2804 break;
b7bcbe95
FB		 2805 default:
2806 return 1;
2807 }
2808 } else {
2809 gen_mov_F0_vreg(0, rn);
4373f3ce 2810 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2811 }
2812 if (rd == 15) {
b5ff1b31 2813 /* Set the 4 flag bits in the CPSR. */
4373f3ce
PB		 2814 gen_set_nzcv(tmp);
2815 dead_tmp(tmp);
2816 } else {
2817 store_reg(s, rd, tmp);
2818 }
b7bcbe95
FB		 2819 } else {
2820 /* arm->vfp */
4373f3ce 2821 tmp = load_reg(s, rd);
b7bcbe95 2822 if (insn & (1 << 21)) {
40f137e1 2823 rn >>= 1;
b7bcbe95
FB		 2824 /* system register */
2825 switch (rn) {
40f137e1 2826 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2827 case ARM_VFP_MVFR0:
2828 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2829 /* Writes are ignored. */
2830 break;
40f137e1 2831 case ARM_VFP_FPSCR:
4373f3ce
PB		 2832 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2833 dead_tmp(tmp);
b5ff1b31 2834 gen_lookup_tb(s);
b7bcbe95 2835 break;
40f137e1 2836 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2837 if (IS_USER(s))
2838 return 1;
71b3c3de
JR		 2839 /* TODO: VFP subarchitecture support.
2840 * For now, keep the EN bit only */
2841 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2842 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2843 gen_lookup_tb(s);
2844 break;
2845 case ARM_VFP_FPINST:
2846 case ARM_VFP_FPINST2:
4373f3ce 2847 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2848 break;
b7bcbe95
FB		 2849 default:
2850 return 1;
2851 }
2852 } else {
4373f3ce 2853 gen_vfp_msr(tmp);
b7bcbe95
FB		 2854 gen_mov_vreg_F0(0, rn);
2855 }
2856 }
2857 }
2858 } else {
2859 /* data processing */
2860 /* The opcode is in bits 23, 21, 20 and 6. */
2861 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2862 if (dp) {
2863 if (op == 15) {
2864 /* rn is opcode */
2865 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2866 } else {
2867 /* rn is register number */
9ee6e8bb 2868 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2869 }
2870
2871 if (op == 15 && (rn == 15 || rn > 17)) {
2872 /* Integer or single precision destination. */
9ee6e8bb 2873 rd = VFP_SREG_D(insn);
b7bcbe95 2874 } else {
9ee6e8bb 2875 VFP_DREG_D(rd, insn);
b7bcbe95
FB		 2876 }
2877
2878 if (op == 15 && (rn == 16 || rn == 17)) {
2879 /* Integer source. */
2880 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
2881 } else {
9ee6e8bb 2882 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2883 }
2884 } else {
9ee6e8bb 2885 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2886 if (op == 15 && rn == 15) {
2887 /* Double precision destination. */
9ee6e8bb
PB		 2888 VFP_DREG_D(rd, insn);
2889 } else {
2890 rd = VFP_SREG_D(insn);
2891 }
2892 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2893 }
2894
2895 veclen = env->vfp.vec_len;
2896 if (op == 15 && rn > 3)
2897 veclen = 0;
2898
2899 /* Shut up compiler warnings. */
2900 delta_m = 0;
2901 delta_d = 0;
2902 bank_mask = 0;
3b46e624 2903
b7bcbe95
FB		 2904 if (veclen > 0) {
2905 if (dp)
2906 bank_mask = 0xc;
2907 else
2908 bank_mask = 0x18;
2909
2910 /* Figure out what type of vector operation this is. */
2911 if ((rd & bank_mask) == 0) {
2912 /* scalar */
2913 veclen = 0;
2914 } else {
2915 if (dp)
2916 delta_d = (env->vfp.vec_stride >> 1) + 1;
2917 else
2918 delta_d = env->vfp.vec_stride + 1;
2919
2920 if ((rm & bank_mask) == 0) {
2921 /* mixed scalar/vector */
2922 delta_m = 0;
2923 } else {
2924 /* vector */
2925 delta_m = delta_d;
2926 }
2927 }
2928 }
2929
2930 /* Load the initial operands. */
2931 if (op == 15) {
2932 switch (rn) {
2933 case 16:
2934 case 17:
2935 /* Integer source */
2936 gen_mov_F0_vreg(0, rm);
2937 break;
2938 case 8:
2939 case 9:
2940 /* Compare */
2941 gen_mov_F0_vreg(dp, rd);
2942 gen_mov_F1_vreg(dp, rm);
2943 break;
2944 case 10:
2945 case 11:
2946 /* Compare with zero */
2947 gen_mov_F0_vreg(dp, rd);
2948 gen_vfp_F1_ld0(dp);
2949 break;
9ee6e8bb
PB		 2950 case 20:
2951 case 21:
2952 case 22:
2953 case 23:
644ad806
PB		 2954 case 28:
2955 case 29:
2956 case 30:
2957 case 31:
9ee6e8bb
PB		 2958 /* Source and destination the same. */
2959 gen_mov_F0_vreg(dp, rd);
2960 break;
b7bcbe95
FB		 2961 default:
2962 /* One source operand. */
2963 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 2964 break;
b7bcbe95
FB		 2965 }
2966 } else {
2967 /* Two source operands. */
2968 gen_mov_F0_vreg(dp, rn);
2969 gen_mov_F1_vreg(dp, rm);
2970 }
2971
2972 for (;;) {
2973 /* Perform the calculation. */
2974 switch (op) {
2975 case 0: /* mac: fd + (fn * fm) */
2976 gen_vfp_mul(dp);
2977 gen_mov_F1_vreg(dp, rd);
2978 gen_vfp_add(dp);
2979 break;
2980 case 1: /* nmac: fd - (fn * fm) */
2981 gen_vfp_mul(dp);
2982 gen_vfp_neg(dp);
2983 gen_mov_F1_vreg(dp, rd);
2984 gen_vfp_add(dp);
2985 break;
2986 case 2: /* msc: -fd + (fn * fm) */
2987 gen_vfp_mul(dp);
2988 gen_mov_F1_vreg(dp, rd);
2989 gen_vfp_sub(dp);
2990 break;
2991 case 3: /* nmsc: -fd - (fn * fm) */
2992 gen_vfp_mul(dp);
b7bcbe95 2993 gen_vfp_neg(dp);
c9fb531a
PB		 2994 gen_mov_F1_vreg(dp, rd);
2995 gen_vfp_sub(dp);
b7bcbe95
FB		 2996 break;
2997 case 4: /* mul: fn * fm */
2998 gen_vfp_mul(dp);
2999 break;
3000 case 5: /* nmul: -(fn * fm) */
3001 gen_vfp_mul(dp);
3002 gen_vfp_neg(dp);
3003 break;
3004 case 6: /* add: fn + fm */
3005 gen_vfp_add(dp);
3006 break;
3007 case 7: /* sub: fn - fm */
3008 gen_vfp_sub(dp);
3009 break;
3010 case 8: /* div: fn / fm */
3011 gen_vfp_div(dp);
3012 break;
9ee6e8bb
PB		 3013 case 14: /* fconst */
3014 if (!arm_feature(env, ARM_FEATURE_VFP3))
3015 return 1;
3016
3017 n = (insn << 12) & 0x80000000;
3018 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3019 if (dp) {
3020 if (i & 0x40)
3021 i |= 0x3f80;
3022 else
3023 i |= 0x4000;
3024 n |= i << 16;
4373f3ce 3025 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3026 } else {
3027 if (i & 0x40)
3028 i |= 0x780;
3029 else
3030 i |= 0x800;
3031 n |= i << 19;
5b340b51 3032 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3033 }
9ee6e8bb 3034 break;
b7bcbe95
FB		 3035 case 15: /* extension space */
3036 switch (rn) {
3037 case 0: /* cpy */
3038 /* no-op */
3039 break;
3040 case 1: /* abs */
3041 gen_vfp_abs(dp);
3042 break;
3043 case 2: /* neg */
3044 gen_vfp_neg(dp);
3045 break;
3046 case 3: /* sqrt */
3047 gen_vfp_sqrt(dp);
3048 break;
60011498
PB		 3049 case 4: /* vcvtb.f32.f16 */
3050 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3051 return 1;
3052 tmp = gen_vfp_mrs();
3053 tcg_gen_ext16u_i32(tmp, tmp);
3054 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3055 dead_tmp(tmp);
3056 break;
3057 case 5: /* vcvtt.f32.f16 */
3058 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3059 return 1;
3060 tmp = gen_vfp_mrs();
3061 tcg_gen_shri_i32(tmp, tmp, 16);
3062 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3063 dead_tmp(tmp);
3064 break;
3065 case 6: /* vcvtb.f16.f32 */
3066 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3067 return 1;
3068 tmp = new_tmp();
3069 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3070 gen_mov_F0_vreg(0, rd);
3071 tmp2 = gen_vfp_mrs();
3072 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3073 tcg_gen_or_i32(tmp, tmp, tmp2);
3074 dead_tmp(tmp2);
3075 gen_vfp_msr(tmp);
3076 break;
3077 case 7: /* vcvtt.f16.f32 */
3078 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3079 return 1;
3080 tmp = new_tmp();
3081 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3082 tcg_gen_shli_i32(tmp, tmp, 16);
3083 gen_mov_F0_vreg(0, rd);
3084 tmp2 = gen_vfp_mrs();
3085 tcg_gen_ext16u_i32(tmp2, tmp2);
3086 tcg_gen_or_i32(tmp, tmp, tmp2);
3087 dead_tmp(tmp2);
3088 gen_vfp_msr(tmp);
3089 break;
b7bcbe95
FB		 3090 case 8: /* cmp */
3091 gen_vfp_cmp(dp);
3092 break;
3093 case 9: /* cmpe */
3094 gen_vfp_cmpe(dp);
3095 break;
3096 case 10: /* cmpz */
3097 gen_vfp_cmp(dp);
3098 break;
3099 case 11: /* cmpez */
3100 gen_vfp_F1_ld0(dp);
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 15: /* single<->double conversion */
3104 if (dp)
4373f3ce 3105 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3106 else
4373f3ce 3107 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3108 break;
3109 case 16: /* fuito */
3110 gen_vfp_uito(dp);
3111 break;
3112 case 17: /* fsito */
3113 gen_vfp_sito(dp);
3114 break;
9ee6e8bb
PB		 3115 case 20: /* fshto */
3116 if (!arm_feature(env, ARM_FEATURE_VFP3))
3117 return 1;
644ad806 3118 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3119 break;
3120 case 21: /* fslto */
3121 if (!arm_feature(env, ARM_FEATURE_VFP3))
3122 return 1;
644ad806 3123 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3124 break;
3125 case 22: /* fuhto */
3126 if (!arm_feature(env, ARM_FEATURE_VFP3))
3127 return 1;
644ad806 3128 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3129 break;
3130 case 23: /* fulto */
3131 if (!arm_feature(env, ARM_FEATURE_VFP3))
3132 return 1;
644ad806 3133 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3134 break;
b7bcbe95
FB		 3135 case 24: /* ftoui */
3136 gen_vfp_toui(dp);
3137 break;
3138 case 25: /* ftouiz */
3139 gen_vfp_touiz(dp);
3140 break;
3141 case 26: /* ftosi */
3142 gen_vfp_tosi(dp);
3143 break;
3144 case 27: /* ftosiz */
3145 gen_vfp_tosiz(dp);
3146 break;
9ee6e8bb
PB		 3147 case 28: /* ftosh */
3148 if (!arm_feature(env, ARM_FEATURE_VFP3))
3149 return 1;
644ad806 3150 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3151 break;
3152 case 29: /* ftosl */
3153 if (!arm_feature(env, ARM_FEATURE_VFP3))
3154 return 1;
644ad806 3155 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3156 break;
3157 case 30: /* ftouh */
3158 if (!arm_feature(env, ARM_FEATURE_VFP3))
3159 return 1;
644ad806 3160 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3161 break;
3162 case 31: /* ftoul */
3163 if (!arm_feature(env, ARM_FEATURE_VFP3))
3164 return 1;
644ad806 3165 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3166 break;
b7bcbe95
FB		 3167 default: /* undefined */
3168 printf ("rn:%d\n", rn);
3169 return 1;
3170 }
3171 break;
3172 default: /* undefined */
3173 printf ("op:%d\n", op);
3174 return 1;
3175 }
3176
3177 /* Write back the result. */
3178 if (op == 15 && (rn >= 8 && rn <= 11))
3179 ; /* Comparison, do nothing. */
3180 else if (op == 15 && rn > 17)
3181 /* Integer result. */
3182 gen_mov_vreg_F0(0, rd);
3183 else if (op == 15 && rn == 15)
3184 /* conversion */
3185 gen_mov_vreg_F0(!dp, rd);
3186 else
3187 gen_mov_vreg_F0(dp, rd);
3188
3189 /* break out of the loop if we have finished */
3190 if (veclen == 0)
3191 break;
3192
3193 if (op == 15 && delta_m == 0) {
3194 /* single source one-many */
3195 while (veclen--) {
3196 rd = ((rd + delta_d) & (bank_mask - 1))
3197 | (rd & bank_mask);
3198 gen_mov_vreg_F0(dp, rd);
3199 }
3200 break;
3201 }
3202 /* Setup the next operands. */
3203 veclen--;
3204 rd = ((rd + delta_d) & (bank_mask - 1))
3205 | (rd & bank_mask);
3206
3207 if (op == 15) {
3208 /* One source operand. */
3209 rm = ((rm + delta_m) & (bank_mask - 1))
3210 | (rm & bank_mask);
3211 gen_mov_F0_vreg(dp, rm);
3212 } else {
3213 /* Two source operands. */
3214 rn = ((rn + delta_d) & (bank_mask - 1))
3215 | (rn & bank_mask);
3216 gen_mov_F0_vreg(dp, rn);
3217 if (delta_m) {
3218 rm = ((rm + delta_m) & (bank_mask - 1))
3219 | (rm & bank_mask);
3220 gen_mov_F1_vreg(dp, rm);
3221 }
3222 }
3223 }
3224 }
3225 break;
3226 case 0xc:
3227 case 0xd:
9ee6e8bb 3228 if (dp && (insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3229 /* two-register transfer */
3230 rn = (insn >> 16) & 0xf;
3231 rd = (insn >> 12) & 0xf;
3232 if (dp) {
9ee6e8bb
PB		 3233 VFP_DREG_M(rm, insn);
3234 } else {
3235 rm = VFP_SREG_M(insn);
3236 }
b7bcbe95 3237
18c9b560 3238 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3239 /* vfp->arm */
3240 if (dp) {
4373f3ce
PB		 3241 gen_mov_F0_vreg(0, rm * 2);
3242 tmp = gen_vfp_mrs();
3243 store_reg(s, rd, tmp);
3244 gen_mov_F0_vreg(0, rm * 2 + 1);
3245 tmp = gen_vfp_mrs();
3246 store_reg(s, rn, tmp);
b7bcbe95
FB		 3247 } else {
3248 gen_mov_F0_vreg(0, rm);
4373f3ce
PB		 3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rn, tmp);
b7bcbe95 3251 gen_mov_F0_vreg(0, rm + 1);
4373f3ce
PB		 3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rd, tmp);
b7bcbe95
FB		 3254 }
3255 } else {
3256 /* arm->vfp */
3257 if (dp) {
4373f3ce
PB		 3258 tmp = load_reg(s, rd);
3259 gen_vfp_msr(tmp);
3260 gen_mov_vreg_F0(0, rm * 2);
3261 tmp = load_reg(s, rn);
3262 gen_vfp_msr(tmp);
3263 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3264 } else {
4373f3ce
PB		 3265 tmp = load_reg(s, rn);
3266 gen_vfp_msr(tmp);
b7bcbe95 3267 gen_mov_vreg_F0(0, rm);
4373f3ce
PB		 3268 tmp = load_reg(s, rd);
3269 gen_vfp_msr(tmp);
b7bcbe95
FB		 3270 gen_mov_vreg_F0(0, rm + 1);
3271 }
3272 }
3273 } else {
3274 /* Load/store */
3275 rn = (insn >> 16) & 0xf;
3276 if (dp)
9ee6e8bb 3277 VFP_DREG_D(rd, insn);
b7bcbe95 3278 else
9ee6e8bb
PB		 3279 rd = VFP_SREG_D(insn);
3280 if (s->thumb && rn == 15) {
312eea9f
FN		 3281 addr = new_tmp();
3282 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3283 } else {
312eea9f 3284 addr = load_reg(s, rn);
9ee6e8bb 3285 }
b7bcbe95
FB		 3286 if ((insn & 0x01200000) == 0x01000000) {
3287 /* Single load/store */
3288 offset = (insn & 0xff) << 2;
3289 if ((insn & (1 << 23)) == 0)
3290 offset = -offset;
312eea9f 3291 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3292 if (insn & (1 << 20)) {
312eea9f 3293 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3294 gen_mov_vreg_F0(dp, rd);
3295 } else {
3296 gen_mov_F0_vreg(dp, rd);
312eea9f 3297 gen_vfp_st(s, dp, addr);
b7bcbe95 3298 }
312eea9f 3299 dead_tmp(addr);
b7bcbe95
FB		 3300 } else {
3301 /* load/store multiple */
3302 if (dp)
3303 n = (insn >> 1) & 0x7f;
3304 else
3305 n = insn & 0xff;
3306
3307 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3308 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3309
3310 if (dp)
3311 offset = 8;
3312 else
3313 offset = 4;
3314 for (i = 0; i < n; i++) {
18c9b560 3315 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3316 /* load */
312eea9f 3317 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3318 gen_mov_vreg_F0(dp, rd + i);
3319 } else {
3320 /* store */
3321 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3322 gen_vfp_st(s, dp, addr);
b7bcbe95 3323 }
312eea9f 3324 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3325 }
3326 if (insn & (1 << 21)) {
3327 /* writeback */
3328 if (insn & (1 << 24))
3329 offset = -offset * n;
3330 else if (dp && (insn & 1))
3331 offset = 4;
3332 else
3333 offset = 0;
3334
3335 if (offset != 0)
312eea9f
FN		 3336 tcg_gen_addi_i32(addr, addr, offset);
3337 store_reg(s, rn, addr);
3338 } else {
3339 dead_tmp(addr);
b7bcbe95
FB		 3340 }
3341 }
3342 }
3343 break;
3344 default:
3345 /* Should never happen. */
3346 return 1;
3347 }
3348 return 0;
3349}
3350
6e256c93 3351static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3352{
6e256c93
FB		 3353 TranslationBlock *tb;
3354
3355 tb = s->tb;
3356 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3357 tcg_gen_goto_tb(n);
8984bd2e 3358 gen_set_pc_im(dest);
57fec1fe 3359 tcg_gen_exit_tb((long)tb + n);
6e256c93 3360 } else {
8984bd2e 3361 gen_set_pc_im(dest);
57fec1fe 3362 tcg_gen_exit_tb(0);
6e256c93 3363 }
c53be334
FB		 3364}
3365
8aaca4c0
FB		 3366static inline void gen_jmp (DisasContext *s, uint32_t dest)
3367{
551bd27f 3368 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3369 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3370 if (s->thumb)
d9ba4830
PB		 3371 dest |= 1;
3372 gen_bx_im(s, dest);
8aaca4c0 3373 } else {
6e256c93 3374 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3375 s->is_jmp = DISAS_TB_JUMP;
3376 }
3377}
3378
d9ba4830 3379static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3380{
ee097184 3381 if (x)
d9ba4830 3382 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3383 else
d9ba4830 3384 gen_sxth(t0);
ee097184 3385 if (y)
d9ba4830 3386 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3387 else
d9ba4830
PB		 3388 gen_sxth(t1);
3389 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3390}
3391
3392/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3393static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3394 uint32_t mask;
3395
3396 mask = 0;
3397 if (flags & (1 << 0))
3398 mask |= 0xff;
3399 if (flags & (1 << 1))
3400 mask |= 0xff00;
3401 if (flags & (1 << 2))
3402 mask |= 0xff0000;
3403 if (flags & (1 << 3))
3404 mask |= 0xff000000;
9ee6e8bb 3405
2ae23e75 3406 /* Mask out undefined bits. */
9ee6e8bb
PB		 3407 mask &= ~CPSR_RESERVED;
3408 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3409 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3410 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3411 mask &= ~CPSR_IT;
9ee6e8bb 3412 /* Mask out execution state bits. */
2ae23e75 3413 if (!spsr)
e160c51c 3414 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3415 /* Mask out privileged bits. */
3416 if (IS_USER(s))
9ee6e8bb 3417 mask &= CPSR_USER;
b5ff1b31
FB		 3418 return mask;
3419}
3420
2fbac54b
FN		 3421/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3422static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3423{
d9ba4830 3424 TCGv tmp;
b5ff1b31
FB		 3425 if (spsr) {
3426 /* ??? This is also undefined in system mode. */
3427 if (IS_USER(s))
3428 return 1;
d9ba4830
PB		 3429
3430 tmp = load_cpu_field(spsr);
3431 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3432 tcg_gen_andi_i32(t0, t0, mask);
3433 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3434 store_cpu_field(tmp, spsr);
b5ff1b31 3435 } else {
2fbac54b 3436 gen_set_cpsr(t0, mask);
b5ff1b31 3437 }
2fbac54b 3438 dead_tmp(t0);
b5ff1b31
FB		 3439 gen_lookup_tb(s);
3440 return 0;
3441}
3442
2fbac54b
FN		 3443/* Returns nonzero if access to the PSR is not permitted. */
3444static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3445{
3446 TCGv tmp;
3447 tmp = new_tmp();
3448 tcg_gen_movi_i32(tmp, val);
3449 return gen_set_psr(s, mask, spsr, tmp);
3450}
3451
e9bb4aa9
JR		 3452/* Generate an old-style exception return. Marks pc as dead. */
3453static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3454{
d9ba4830 3455 TCGv tmp;
e9bb4aa9 3456 store_reg(s, 15, pc);
d9ba4830
PB		 3457 tmp = load_cpu_field(spsr);
3458 gen_set_cpsr(tmp, 0xffffffff);
3459 dead_tmp(tmp);
b5ff1b31
FB		 3460 s->is_jmp = DISAS_UPDATE;
3461}
3462
b0109805
PB		 3463/* Generate a v6 exception return. Marks both values as dead. */
3464static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3465{
b0109805
PB		 3466 gen_set_cpsr(cpsr, 0xffffffff);
3467 dead_tmp(cpsr);
3468 store_reg(s, 15, pc);
9ee6e8bb
PB		 3469 s->is_jmp = DISAS_UPDATE;
3470}
3b46e624 3471
9ee6e8bb
PB		 3472static inline void
3473gen_set_condexec (DisasContext *s)
3474{
3475 if (s->condexec_mask) {
8f01245e
PB		 3476 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3477 TCGv tmp = new_tmp();
3478 tcg_gen_movi_i32(tmp, val);
d9ba4830 3479 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3480 }
3481}
3b46e624 3482
9ee6e8bb
PB		 3483static void gen_nop_hint(DisasContext *s, int val)
3484{
3485 switch (val) {
3486 case 3: /* wfi */
8984bd2e 3487 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3488 s->is_jmp = DISAS_WFI;
3489 break;
3490 case 2: /* wfe */
3491 case 4: /* sev */
3492 /* TODO: Implement SEV and WFE. May help SMP performance. */
3493 default: /* nop */
3494 break;
3495 }
3496}
99c475ab 3497
ad69471c 3498#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3499
dd8fbd78 3500static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3501{
3502 switch (size) {
dd8fbd78
FN		 3503 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3504 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3505 case 2: tcg_gen_add_i32(t0, t0, t1); break;
9ee6e8bb
PB		 3506 default: return 1;
3507 }
3508 return 0;
3509}
3510
dd8fbd78 3511static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3512{
3513 switch (size) {
dd8fbd78
FN		 3514 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3515 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3516 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3517 default: return;
3518 }
3519}
3520
3521/* 32-bit pairwise ops end up the same as the elementwise versions. */
3522#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3523#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3524#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3525#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3526
3527/* FIXME: This is wrong. They set the wrong overflow bit. */
3528#define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c)
3529#define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c)
3530#define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c)
3531#define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c)
3532
3533#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3534 switch ((size << 1) | u) { \
3535 case 0: \
dd8fbd78 3536 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3537 break; \
3538 case 1: \
dd8fbd78 3539 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3540 break; \
3541 case 2: \
dd8fbd78 3542 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3543 break; \
3544 case 3: \
dd8fbd78 3545 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3546 break; \
3547 case 4: \
dd8fbd78 3548 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3549 break; \
3550 case 5: \
dd8fbd78 3551 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3552 break; \
3553 default: return 1; \
3554 }} while (0)
9ee6e8bb
PB		 3555
3556#define GEN_NEON_INTEGER_OP(name) do { \
3557 switch ((size << 1) | u) { \
ad69471c 3558 case 0: \
dd8fbd78 3559 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3560 break; \
3561 case 1: \
dd8fbd78 3562 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3563 break; \
3564 case 2: \
dd8fbd78 3565 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3566 break; \
3567 case 3: \
dd8fbd78 3568 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3569 break; \
3570 case 4: \
dd8fbd78 3571 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3572 break; \
3573 case 5: \
dd8fbd78 3574 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3575 break; \
9ee6e8bb
PB		 3576 default: return 1; \
3577 }} while (0)
3578
dd8fbd78 3579static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3580{
dd8fbd78
FN		 3581 TCGv tmp = new_tmp();
3582 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3583 return tmp;
9ee6e8bb
PB		 3584}
3585
dd8fbd78 3586static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3587{
dd8fbd78
FN		 3588 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3589 dead_tmp(var);
9ee6e8bb
PB		 3590}
3591
dd8fbd78 3592static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3593{
dd8fbd78 3594 TCGv tmp;
9ee6e8bb 3595 if (size == 1) {
dd8fbd78 3596 tmp = neon_load_reg(reg >> 1, reg & 1);
9ee6e8bb 3597 } else {
dd8fbd78
FN		 3598 tmp = neon_load_reg(reg >> 2, (reg >> 1) & 1);
3599 if (reg & 1) {
3600 gen_neon_dup_low16(tmp);
3601 } else {
3602 gen_neon_dup_high16(tmp);
3603 }
9ee6e8bb 3604 }
dd8fbd78 3605 return tmp;
9ee6e8bb
PB		 3606}
3607
19457615
FN		 3608static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3609{
3610 TCGv rd, rm, tmp;
3611
3612 rd = new_tmp();
3613 rm = new_tmp();
3614 tmp = new_tmp();
3615
3616 tcg_gen_andi_i32(rd, t0, 0xff);
3617 tcg_gen_shri_i32(tmp, t0, 8);
3618 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3619 tcg_gen_or_i32(rd, rd, tmp);
3620 tcg_gen_shli_i32(tmp, t1, 16);
3621 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3622 tcg_gen_or_i32(rd, rd, tmp);
3623 tcg_gen_shli_i32(tmp, t1, 8);
3624 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3625 tcg_gen_or_i32(rd, rd, tmp);
3626
3627 tcg_gen_shri_i32(rm, t0, 8);
3628 tcg_gen_andi_i32(rm, rm, 0xff);
3629 tcg_gen_shri_i32(tmp, t0, 16);
3630 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3631 tcg_gen_or_i32(rm, rm, tmp);
3632 tcg_gen_shli_i32(tmp, t1, 8);
3633 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3634 tcg_gen_or_i32(rm, rm, tmp);
3635 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3636 tcg_gen_or_i32(t1, rm, tmp);
3637 tcg_gen_mov_i32(t0, rd);
3638
3639 dead_tmp(tmp);
3640 dead_tmp(rm);
3641 dead_tmp(rd);
3642}
3643
3644static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3645{
3646 TCGv rd, rm, tmp;
3647
3648 rd = new_tmp();
3649 rm = new_tmp();
3650 tmp = new_tmp();
3651
3652 tcg_gen_andi_i32(rd, t0, 0xff);
3653 tcg_gen_shli_i32(tmp, t1, 8);
3654 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3655 tcg_gen_or_i32(rd, rd, tmp);
3656 tcg_gen_shli_i32(tmp, t0, 16);
3657 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3658 tcg_gen_or_i32(rd, rd, tmp);
3659 tcg_gen_shli_i32(tmp, t1, 24);
3660 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3661 tcg_gen_or_i32(rd, rd, tmp);
3662
3663 tcg_gen_andi_i32(rm, t1, 0xff000000);
3664 tcg_gen_shri_i32(tmp, t0, 8);
3665 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3666 tcg_gen_or_i32(rm, rm, tmp);
3667 tcg_gen_shri_i32(tmp, t1, 8);
3668 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3669 tcg_gen_or_i32(rm, rm, tmp);
3670 tcg_gen_shri_i32(tmp, t0, 16);
3671 tcg_gen_andi_i32(tmp, tmp, 0xff);
3672 tcg_gen_or_i32(t1, rm, tmp);
3673 tcg_gen_mov_i32(t0, rd);
3674
3675 dead_tmp(tmp);
3676 dead_tmp(rm);
3677 dead_tmp(rd);
3678}
3679
3680static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3681{
3682 TCGv tmp, tmp2;
3683
3684 tmp = new_tmp();
3685 tmp2 = new_tmp();
3686
3687 tcg_gen_andi_i32(tmp, t0, 0xffff);
3688 tcg_gen_shli_i32(tmp2, t1, 16);
3689 tcg_gen_or_i32(tmp, tmp, tmp2);
3690 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3691 tcg_gen_shri_i32(tmp2, t0, 16);
3692 tcg_gen_or_i32(t1, t1, tmp2);
3693 tcg_gen_mov_i32(t0, tmp);
3694
3695 dead_tmp(tmp2);
3696 dead_tmp(tmp);
3697}
3698
9ee6e8bb
PB		 3699static void gen_neon_unzip(int reg, int q, int tmp, int size)
3700{
3701 int n;
dd8fbd78 3702 TCGv t0, t1;
9ee6e8bb
PB		 3703
3704 for (n = 0; n < q + 1; n += 2) {
dd8fbd78
FN		 3705 t0 = neon_load_reg(reg, n);
3706 t1 = neon_load_reg(reg, n + 1);
9ee6e8bb 3707 switch (size) {
dd8fbd78
FN		 3708 case 0: gen_neon_unzip_u8(t0, t1); break;
3709 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
9ee6e8bb
PB		 3710 case 2: /* no-op */; break;
3711 default: abort();
3712 }
dd8fbd78
FN		 3713 neon_store_scratch(tmp + n, t0);
3714 neon_store_scratch(tmp + n + 1, t1);
9ee6e8bb
PB		 3715 }
3716}
3717
19457615
FN		 3718static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3719{
3720 TCGv rd, tmp;
3721
3722 rd = new_tmp();
3723 tmp = new_tmp();
3724
3725 tcg_gen_shli_i32(rd, t0, 8);
3726 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3727 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3728 tcg_gen_or_i32(rd, rd, tmp);
3729
3730 tcg_gen_shri_i32(t1, t1, 8);
3731 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3732 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3733 tcg_gen_or_i32(t1, t1, tmp);
3734 tcg_gen_mov_i32(t0, rd);
3735
3736 dead_tmp(tmp);
3737 dead_tmp(rd);
3738}
3739
3740static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3741{
3742 TCGv rd, tmp;
3743
3744 rd = new_tmp();
3745 tmp = new_tmp();
3746
3747 tcg_gen_shli_i32(rd, t0, 16);
3748 tcg_gen_andi_i32(tmp, t1, 0xffff);
3749 tcg_gen_or_i32(rd, rd, tmp);
3750 tcg_gen_shri_i32(t1, t1, 16);
3751 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3752 tcg_gen_or_i32(t1, t1, tmp);
3753 tcg_gen_mov_i32(t0, rd);
3754
3755 dead_tmp(tmp);
3756 dead_tmp(rd);
3757}
3758
3759
9ee6e8bb
PB		 3760static struct {
3761 int nregs;
3762 int interleave;
3763 int spacing;
3764} neon_ls_element_type[11] = {
3765 {4, 4, 1},
3766 {4, 4, 2},
3767 {4, 1, 1},
3768 {4, 2, 1},
3769 {3, 3, 1},
3770 {3, 3, 2},
3771 {3, 1, 1},
3772 {1, 1, 1},
3773 {2, 2, 1},
3774 {2, 2, 2},
3775 {2, 1, 1}
3776};
3777
3778/* Translate a NEON load/store element instruction. Return nonzero if the
3779 instruction is invalid. */
3780static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3781{
3782 int rd, rn, rm;
3783 int op;
3784 int nregs;
3785 int interleave;
84496233 3786 int spacing;
9ee6e8bb
PB		 3787 int stride;
3788 int size;
3789 int reg;
3790 int pass;
3791 int load;
3792 int shift;
9ee6e8bb 3793 int n;
1b2b1e54 3794 TCGv addr;
b0109805 3795 TCGv tmp;
8f8e3aa4 3796 TCGv tmp2;
84496233 3797 TCGv_i64 tmp64;
9ee6e8bb
PB		 3798
3799 if (!vfp_enabled(env))
3800 return 1;
3801 VFP_DREG_D(rd, insn);
3802 rn = (insn >> 16) & 0xf;
3803 rm = insn & 0xf;
3804 load = (insn & (1 << 21)) != 0;
1b2b1e54 3805 addr = new_tmp();
9ee6e8bb
PB		 3806 if ((insn & (1 << 23)) == 0) {
3807 /* Load store all elements. */
3808 op = (insn >> 8) & 0xf;
3809 size = (insn >> 6) & 3;
84496233 3810 if (op > 10)
9ee6e8bb
PB		 3811 return 1;
3812 nregs = neon_ls_element_type[op].nregs;
3813 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3814 spacing = neon_ls_element_type[op].spacing;
3815 if (size == 3 && (interleave | spacing) != 1)
3816 return 1;
dcc65026 3817 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3818 stride = (1 << size) * interleave;
3819 for (reg = 0; reg < nregs; reg++) {
3820 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3821 load_reg_var(s, addr, rn);
3822 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3823 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3824 load_reg_var(s, addr, rn);
3825 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3826 }
84496233
JR		 3827 if (size == 3) {
3828 if (load) {
3829 tmp64 = gen_ld64(addr, IS_USER(s));
3830 neon_store_reg64(tmp64, rd);
3831 tcg_temp_free_i64(tmp64);
3832 } else {
3833 tmp64 = tcg_temp_new_i64();
3834 neon_load_reg64(tmp64, rd);
3835 gen_st64(tmp64, addr, IS_USER(s));
3836 }
3837 tcg_gen_addi_i32(addr, addr, stride);
3838 } else {
3839 for (pass = 0; pass < 2; pass++) {
3840 if (size == 2) {
3841 if (load) {
3842 tmp = gen_ld32(addr, IS_USER(s));
3843 neon_store_reg(rd, pass, tmp);
3844 } else {
3845 tmp = neon_load_reg(rd, pass);
3846 gen_st32(tmp, addr, IS_USER(s));
3847 }
1b2b1e54 3848 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3849 } else if (size == 1) {
3850 if (load) {
3851 tmp = gen_ld16u(addr, IS_USER(s));
3852 tcg_gen_addi_i32(addr, addr, stride);
3853 tmp2 = gen_ld16u(addr, IS_USER(s));
3854 tcg_gen_addi_i32(addr, addr, stride);
3855 gen_bfi(tmp, tmp, tmp2, 16, 0xffff);
3856 dead_tmp(tmp2);
3857 neon_store_reg(rd, pass, tmp);
3858 } else {
3859 tmp = neon_load_reg(rd, pass);
3860 tmp2 = new_tmp();
3861 tcg_gen_shri_i32(tmp2, tmp, 16);
3862 gen_st16(tmp, addr, IS_USER(s));
3863 tcg_gen_addi_i32(addr, addr, stride);
3864 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3865 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3866 }
84496233
JR		 3867 } else /* size == 0 */ {
3868 if (load) {
3869 TCGV_UNUSED(tmp2);
3870 for (n = 0; n < 4; n++) {
3871 tmp = gen_ld8u(addr, IS_USER(s));
3872 tcg_gen_addi_i32(addr, addr, stride);
3873 if (n == 0) {
3874 tmp2 = tmp;
3875 } else {
3876 gen_bfi(tmp2, tmp2, tmp, n * 8, 0xff);
3877 dead_tmp(tmp);
3878 }
9ee6e8bb 3879 }
84496233
JR		 3880 neon_store_reg(rd, pass, tmp2);
3881 } else {
3882 tmp2 = neon_load_reg(rd, pass);
3883 for (n = 0; n < 4; n++) {
3884 tmp = new_tmp();
3885 if (n == 0) {
3886 tcg_gen_mov_i32(tmp, tmp2);
3887 } else {
3888 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3889 }
3890 gen_st8(tmp, addr, IS_USER(s));
3891 tcg_gen_addi_i32(addr, addr, stride);
3892 }
3893 dead_tmp(tmp2);
9ee6e8bb
PB		 3894 }
3895 }
3896 }
3897 }
84496233 3898 rd += spacing;
9ee6e8bb
PB		 3899 }
3900 stride = nregs * 8;
3901 } else {
3902 size = (insn >> 10) & 3;
3903 if (size == 3) {
3904 /* Load single element to all lanes. */
3905 if (!load)
3906 return 1;
3907 size = (insn >> 6) & 3;
3908 nregs = ((insn >> 8) & 3) + 1;
3909 stride = (insn & (1 << 5)) ? 2 : 1;
dcc65026 3910 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3911 for (reg = 0; reg < nregs; reg++) {
3912 switch (size) {
3913 case 0:
1b2b1e54 3914 tmp = gen_ld8u(addr, IS_USER(s));
ad69471c 3915 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3916 break;
3917 case 1:
1b2b1e54 3918 tmp = gen_ld16u(addr, IS_USER(s));
ad69471c 3919 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3920 break;
3921 case 2:
1b2b1e54 3922 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 3923 break;
3924 case 3:
3925 return 1;
a50f5b91
PB		 3926 default: /* Avoid compiler warnings. */
3927 abort();
99c475ab 3928 }
1b2b1e54 3929 tcg_gen_addi_i32(addr, addr, 1 << size);
ad69471c
PB		 3930 tmp2 = new_tmp();
3931 tcg_gen_mov_i32(tmp2, tmp);
3932 neon_store_reg(rd, 0, tmp2);
3018f259 3933 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 3934 rd += stride;
3935 }
3936 stride = (1 << size) * nregs;
3937 } else {
3938 /* Single element. */
3939 pass = (insn >> 7) & 1;
3940 switch (size) {
3941 case 0:
3942 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3943 stride = 1;
3944 break;
3945 case 1:
3946 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3947 stride = (insn & (1 << 5)) ? 2 : 1;
3948 break;
3949 case 2:
3950 shift = 0;
9ee6e8bb
PB		 3951 stride = (insn & (1 << 6)) ? 2 : 1;
3952 break;
3953 default:
3954 abort();
3955 }
3956 nregs = ((insn >> 8) & 3) + 1;
dcc65026 3957 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3958 for (reg = 0; reg < nregs; reg++) {
3959 if (load) {
9ee6e8bb
PB		 3960 switch (size) {
3961 case 0:
1b2b1e54 3962 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 3963 break;
3964 case 1:
1b2b1e54 3965 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 3966 break;
3967 case 2:
1b2b1e54 3968 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 3969 break;
a50f5b91
PB		 3970 default: /* Avoid compiler warnings. */
3971 abort();
9ee6e8bb
PB		 3972 }
3973 if (size != 2) {
8f8e3aa4
PB		 3974 tmp2 = neon_load_reg(rd, pass);
3975 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3976 dead_tmp(tmp2);
9ee6e8bb 3977 }
8f8e3aa4 3978 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3979 } else { /* Store */
8f8e3aa4
PB		 3980 tmp = neon_load_reg(rd, pass);
3981 if (shift)
3982 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3983 switch (size) {
3984 case 0:
1b2b1e54 3985 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3986 break;
3987 case 1:
1b2b1e54 3988 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3989 break;
3990 case 2:
1b2b1e54 3991 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 3992 break;
99c475ab 3993 }
99c475ab 3994 }
9ee6e8bb 3995 rd += stride;
1b2b1e54 3996 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 3997 }
9ee6e8bb 3998 stride = nregs * (1 << size);
99c475ab 3999 }
9ee6e8bb 4000 }
1b2b1e54 4001 dead_tmp(addr);
9ee6e8bb 4002 if (rm != 15) {
b26eefb6
PB		 4003 TCGv base;
4004
4005 base = load_reg(s, rn);
9ee6e8bb 4006 if (rm == 13) {
b26eefb6 4007 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4008 } else {
b26eefb6
PB		 4009 TCGv index;
4010 index = load_reg(s, rm);
4011 tcg_gen_add_i32(base, base, index);
4012 dead_tmp(index);
9ee6e8bb 4013 }
b26eefb6 4014 store_reg(s, rn, base);
9ee6e8bb
PB		 4015 }
4016 return 0;
4017}
3b46e624 4018
8f8e3aa4
PB		 4019/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4020static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4021{
4022 tcg_gen_and_i32(t, t, c);
f669df27 4023 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4024 tcg_gen_or_i32(dest, t, f);
4025}
4026
a7812ae4 4027static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4028{
4029 switch (size) {
4030 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4031 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4032 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4033 default: abort();
4034 }
4035}
4036
a7812ae4 4037static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4038{
4039 switch (size) {
4040 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4041 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4042 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4043 default: abort();
4044 }
4045}
4046
a7812ae4 4047static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4048{
4049 switch (size) {
4050 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4051 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4052 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4053 default: abort();
4054 }
4055}
4056
4057static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4058 int q, int u)
4059{
4060 if (q) {
4061 if (u) {
4062 switch (size) {
4063 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4064 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4065 default: abort();
4066 }
4067 } else {
4068 switch (size) {
4069 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4070 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4071 default: abort();
4072 }
4073 }
4074 } else {
4075 if (u) {
4076 switch (size) {
4077 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4078 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4079 default: abort();
4080 }
4081 } else {
4082 switch (size) {
4083 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4084 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4085 default: abort();
4086 }
4087 }
4088 }
4089}
4090
a7812ae4 4091static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4092{
4093 if (u) {
4094 switch (size) {
4095 case 0: gen_helper_neon_widen_u8(dest, src); break;
4096 case 1: gen_helper_neon_widen_u16(dest, src); break;
4097 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4098 default: abort();
4099 }
4100 } else {
4101 switch (size) {
4102 case 0: gen_helper_neon_widen_s8(dest, src); break;
4103 case 1: gen_helper_neon_widen_s16(dest, src); break;
4104 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4105 default: abort();
4106 }
4107 }
4108 dead_tmp(src);
4109}
4110
4111static inline void gen_neon_addl(int size)
4112{
4113 switch (size) {
4114 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4115 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4116 case 2: tcg_gen_add_i64(CPU_V001); break;
4117 default: abort();
4118 }
4119}
4120
4121static inline void gen_neon_subl(int size)
4122{
4123 switch (size) {
4124 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4125 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4126 case 2: tcg_gen_sub_i64(CPU_V001); break;
4127 default: abort();
4128 }
4129}
4130
a7812ae4 4131static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4132{
4133 switch (size) {
4134 case 0: gen_helper_neon_negl_u16(var, var); break;
4135 case 1: gen_helper_neon_negl_u32(var, var); break;
4136 case 2: gen_helper_neon_negl_u64(var, var); break;
4137 default: abort();
4138 }
4139}
4140
a7812ae4 4141static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4142{
4143 switch (size) {
4144 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4145 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4146 default: abort();
4147 }
4148}
4149
a7812ae4 4150static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4151{
a7812ae4 4152 TCGv_i64 tmp;
ad69471c
PB		 4153
4154 switch ((size << 1) | u) {
4155 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4156 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4157 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4158 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4159 case 4:
4160 tmp = gen_muls_i64_i32(a, b);
4161 tcg_gen_mov_i64(dest, tmp);
4162 break;
4163 case 5:
4164 tmp = gen_mulu_i64_i32(a, b);
4165 tcg_gen_mov_i64(dest, tmp);
4166 break;
4167 default: abort();
4168 }
ad69471c
PB		 4169}
4170
9ee6e8bb
PB		 4171/* Translate a NEON data processing instruction. Return nonzero if the
4172 instruction is invalid.
ad69471c
PB		 4173 We process data in a mixture of 32-bit and 64-bit chunks.
4174 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4175
9ee6e8bb
PB		 4176static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4177{
4178 int op;
4179 int q;
4180 int rd, rn, rm;
4181 int size;
4182 int shift;
4183 int pass;
4184 int count;
4185 int pairwise;
4186 int u;
4187 int n;
ca9a32e4 4188 uint32_t imm, mask;
b75263d6 4189 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4190 TCGv_i64 tmp64;
9ee6e8bb
PB		 4191
4192 if (!vfp_enabled(env))
4193 return 1;
4194 q = (insn & (1 << 6)) != 0;
4195 u = (insn >> 24) & 1;
4196 VFP_DREG_D(rd, insn);
4197 VFP_DREG_N(rn, insn);
4198 VFP_DREG_M(rm, insn);
4199 size = (insn >> 20) & 3;
4200 if ((insn & (1 << 23)) == 0) {
4201 /* Three register same length. */
4202 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4203 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4204 || op == 10 || op == 11 || op == 16)) {
4205 /* 64-bit element instructions. */
9ee6e8bb 4206 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4207 neon_load_reg64(cpu_V0, rn + pass);
4208 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4209 switch (op) {
4210 case 1: /* VQADD */
4211 if (u) {
ad69471c 4212 gen_helper_neon_add_saturate_u64(CPU_V001);
2c0262af 4213 } else {
ad69471c 4214 gen_helper_neon_add_saturate_s64(CPU_V001);
2c0262af 4215 }
9ee6e8bb
PB		 4216 break;
4217 case 5: /* VQSUB */
4218 if (u) {
ad69471c
PB		 4219 gen_helper_neon_sub_saturate_u64(CPU_V001);
4220 } else {
4221 gen_helper_neon_sub_saturate_s64(CPU_V001);
4222 }
4223 break;
4224 case 8: /* VSHL */
4225 if (u) {
4226 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4227 } else {
4228 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4229 }
4230 break;
4231 case 9: /* VQSHL */
4232 if (u) {
4233 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4234 cpu_V0, cpu_V0);
4235 } else {
4236 gen_helper_neon_qshl_s64(cpu_V1, cpu_env,
4237 cpu_V1, cpu_V0);
4238 }
4239 break;
4240 case 10: /* VRSHL */
4241 if (u) {
4242 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4243 } else {
ad69471c
PB		 4244 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4245 }
4246 break;
4247 case 11: /* VQRSHL */
4248 if (u) {
4249 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4250 cpu_V1, cpu_V0);
4251 } else {
4252 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4253 cpu_V1, cpu_V0);
1e8d4eec 4254 }
9ee6e8bb
PB		 4255 break;
4256 case 16:
4257 if (u) {
ad69471c 4258 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4259 } else {
ad69471c 4260 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4261 }
4262 break;
4263 default:
4264 abort();
2c0262af 4265 }
ad69471c 4266 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4267 }
9ee6e8bb 4268 return 0;
2c0262af 4269 }
9ee6e8bb
PB		 4270 switch (op) {
4271 case 8: /* VSHL */
4272 case 9: /* VQSHL */
4273 case 10: /* VRSHL */
ad69471c 4274 case 11: /* VQRSHL */
9ee6e8bb 4275 {
ad69471c
PB		 4276 int rtmp;
4277 /* Shift instruction operands are reversed. */
4278 rtmp = rn;
9ee6e8bb 4279 rn = rm;
ad69471c 4280 rm = rtmp;
9ee6e8bb
PB		 4281 pairwise = 0;
4282 }
2c0262af 4283 break;
9ee6e8bb
PB		 4284 case 20: /* VPMAX */
4285 case 21: /* VPMIN */
4286 case 23: /* VPADD */
4287 pairwise = 1;
2c0262af 4288 break;
9ee6e8bb
PB		 4289 case 26: /* VPADD (float) */
4290 pairwise = (u && size < 2);
2c0262af 4291 break;
9ee6e8bb
PB		 4292 case 30: /* VPMIN/VPMAX (float) */
4293 pairwise = u;
2c0262af 4294 break;
9ee6e8bb
PB		 4295 default:
4296 pairwise = 0;
2c0262af 4297 break;
9ee6e8bb 4298 }
dd8fbd78 4299
9ee6e8bb
PB		 4300 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4301
4302 if (pairwise) {
4303 /* Pairwise. */
4304 if (q)
4305 n = (pass & 1) * 2;
2c0262af 4306 else
9ee6e8bb
PB		 4307 n = 0;
4308 if (pass < q + 1) {
dd8fbd78
FN		 4309 tmp = neon_load_reg(rn, n);
4310 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4311 } else {
dd8fbd78
FN		 4312 tmp = neon_load_reg(rm, n);
4313 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4314 }
4315 } else {
4316 /* Elementwise. */
dd8fbd78
FN		 4317 tmp = neon_load_reg(rn, pass);
4318 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4319 }
4320 switch (op) {
4321 case 0: /* VHADD */
4322 GEN_NEON_INTEGER_OP(hadd);
4323 break;
4324 case 1: /* VQADD */
ad69471c 4325 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4326 break;
9ee6e8bb
PB		 4327 case 2: /* VRHADD */
4328 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4329 break;
9ee6e8bb
PB		 4330 case 3: /* Logic ops. */
4331 switch ((u << 2) | size) {
4332 case 0: /* VAND */
dd8fbd78 4333 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4334 break;
4335 case 1: /* BIC */
f669df27 4336 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4337 break;
4338 case 2: /* VORR */
dd8fbd78 4339 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4340 break;
4341 case 3: /* VORN */
f669df27 4342 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4343 break;
4344 case 4: /* VEOR */
dd8fbd78 4345 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4346 break;
4347 case 5: /* VBSL */
dd8fbd78
FN		 4348 tmp3 = neon_load_reg(rd, pass);
4349 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4350 dead_tmp(tmp3);
9ee6e8bb
PB		 4351 break;
4352 case 6: /* VBIT */
dd8fbd78
FN		 4353 tmp3 = neon_load_reg(rd, pass);
4354 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4355 dead_tmp(tmp3);
9ee6e8bb
PB		 4356 break;
4357 case 7: /* VBIF */
dd8fbd78
FN		 4358 tmp3 = neon_load_reg(rd, pass);
4359 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4360 dead_tmp(tmp3);
9ee6e8bb 4361 break;
2c0262af
FB		 4362 }
4363 break;
9ee6e8bb
PB		 4364 case 4: /* VHSUB */
4365 GEN_NEON_INTEGER_OP(hsub);
4366 break;
4367 case 5: /* VQSUB */
ad69471c 4368 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4369 break;
9ee6e8bb
PB		 4370 case 6: /* VCGT */
4371 GEN_NEON_INTEGER_OP(cgt);
4372 break;
4373 case 7: /* VCGE */
4374 GEN_NEON_INTEGER_OP(cge);
4375 break;
4376 case 8: /* VSHL */
ad69471c 4377 GEN_NEON_INTEGER_OP(shl);
2c0262af 4378 break;
9ee6e8bb 4379 case 9: /* VQSHL */
ad69471c 4380 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4381 break;
9ee6e8bb 4382 case 10: /* VRSHL */
ad69471c 4383 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4384 break;
9ee6e8bb 4385 case 11: /* VQRSHL */
ad69471c 4386 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4387 break;
4388 case 12: /* VMAX */
4389 GEN_NEON_INTEGER_OP(max);
4390 break;
4391 case 13: /* VMIN */
4392 GEN_NEON_INTEGER_OP(min);
4393 break;
4394 case 14: /* VABD */
4395 GEN_NEON_INTEGER_OP(abd);
4396 break;
4397 case 15: /* VABA */
4398 GEN_NEON_INTEGER_OP(abd);
dd8fbd78
FN		 4399 dead_tmp(tmp2);
4400 tmp2 = neon_load_reg(rd, pass);
4401 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4402 break;
4403 case 16:
4404 if (!u) { /* VADD */
dd8fbd78 4405 if (gen_neon_add(size, tmp, tmp2))
9ee6e8bb
PB		 4406 return 1;
4407 } else { /* VSUB */
4408 switch (size) {
dd8fbd78
FN		 4409 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4410 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4411 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4412 default: return 1;
4413 }
4414 }
4415 break;
4416 case 17:
4417 if (!u) { /* VTST */
4418 switch (size) {
dd8fbd78
FN		 4419 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4420 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4421 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4422 default: return 1;
4423 }
4424 } else { /* VCEQ */
4425 switch (size) {
dd8fbd78
FN		 4426 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4427 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4428 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4429 default: return 1;
4430 }
4431 }
4432 break;
4433 case 18: /* Multiply. */
4434 switch (size) {
dd8fbd78
FN		 4435 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4436 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4437 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4438 default: return 1;
4439 }
dd8fbd78
FN		 4440 dead_tmp(tmp2);
4441 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4442 if (u) { /* VMLS */
dd8fbd78 4443 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4444 } else { /* VMLA */
dd8fbd78 4445 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4446 }
4447 break;
4448 case 19: /* VMUL */
4449 if (u) { /* polynomial */
dd8fbd78 4450 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4451 } else { /* Integer */
4452 switch (size) {
dd8fbd78
FN		 4453 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4454 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4455 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4456 default: return 1;
4457 }
4458 }
4459 break;
4460 case 20: /* VPMAX */
4461 GEN_NEON_INTEGER_OP(pmax);
4462 break;
4463 case 21: /* VPMIN */
4464 GEN_NEON_INTEGER_OP(pmin);
4465 break;
4466 case 22: /* Hultiply high. */
4467 if (!u) { /* VQDMULH */
4468 switch (size) {
dd8fbd78
FN		 4469 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4470 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4471 default: return 1;
4472 }
4473 } else { /* VQRDHMUL */
4474 switch (size) {
dd8fbd78
FN		 4475 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4476 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4477 default: return 1;
4478 }
4479 }
4480 break;
4481 case 23: /* VPADD */
4482 if (u)
4483 return 1;
4484 switch (size) {
dd8fbd78
FN		 4485 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4486 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4487 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4488 default: return 1;
4489 }
4490 break;
4491 case 26: /* Floating point arithnetic. */
4492 switch ((u << 2) | size) {
4493 case 0: /* VADD */
dd8fbd78 4494 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4495 break;
4496 case 2: /* VSUB */
dd8fbd78 4497 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4498 break;
4499 case 4: /* VPADD */
dd8fbd78 4500 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4501 break;
4502 case 6: /* VABD */
dd8fbd78 4503 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4504 break;
4505 default:
4506 return 1;
4507 }
4508 break;
4509 case 27: /* Float multiply. */
dd8fbd78 4510 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4511 if (!u) {
dd8fbd78
FN		 4512 dead_tmp(tmp2);
4513 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4514 if (size == 0) {
dd8fbd78 4515 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4516 } else {
dd8fbd78 4517 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4518 }
4519 }
4520 break;
4521 case 28: /* Float compare. */
4522 if (!u) {
dd8fbd78 4523 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4524 } else {
9ee6e8bb 4525 if (size == 0)
dd8fbd78 4526 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4527 else
dd8fbd78 4528 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4529 }
2c0262af 4530 break;
9ee6e8bb
PB		 4531 case 29: /* Float compare absolute. */
4532 if (!u)
4533 return 1;
4534 if (size == 0)
dd8fbd78 4535 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4536 else
dd8fbd78 4537 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4538 break;
9ee6e8bb
PB		 4539 case 30: /* Float min/max. */
4540 if (size == 0)
dd8fbd78 4541 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4542 else
dd8fbd78 4543 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4544 break;
4545 case 31:
4546 if (size == 0)
dd8fbd78 4547 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4548 else
dd8fbd78 4549 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4550 break;
9ee6e8bb
PB		 4551 default:
4552 abort();
2c0262af 4553 }
dd8fbd78
FN		 4554 dead_tmp(tmp2);
4555
9ee6e8bb
PB		 4556 /* Save the result. For elementwise operations we can put it
4557 straight into the destination register. For pairwise operations
4558 we have to be careful to avoid clobbering the source operands. */
4559 if (pairwise && rd == rm) {
dd8fbd78 4560 neon_store_scratch(pass, tmp);
9ee6e8bb 4561 } else {
dd8fbd78 4562 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4563 }
4564
4565 } /* for pass */
4566 if (pairwise && rd == rm) {
4567 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4568 tmp = neon_load_scratch(pass);
4569 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4570 }
4571 }
ad69471c 4572 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4573 } else if (insn & (1 << 4)) {
4574 if ((insn & 0x00380080) != 0) {
4575 /* Two registers and shift. */
4576 op = (insn >> 8) & 0xf;
4577 if (insn & (1 << 7)) {
4578 /* 64-bit shift. */
4579 size = 3;
4580 } else {
4581 size = 2;
4582 while ((insn & (1 << (size + 19))) == 0)
4583 size--;
4584 }
4585 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4586 /* To avoid excessive dumplication of ops we implement shift
4587 by immediate using the variable shift operations. */
4588 if (op < 8) {
4589 /* Shift by immediate:
4590 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4591 /* Right shifts are encoded as N - shift, where N is the
4592 element size in bits. */
4593 if (op <= 4)
4594 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4595 if (size == 3) {
4596 count = q + 1;
4597 } else {
4598 count = q ? 4: 2;
4599 }
4600 switch (size) {
4601 case 0:
4602 imm = (uint8_t) shift;
4603 imm |= imm << 8;
4604 imm |= imm << 16;
4605 break;
4606 case 1:
4607 imm = (uint16_t) shift;
4608 imm |= imm << 16;
4609 break;
4610 case 2:
4611 case 3:
4612 imm = shift;
4613 break;
4614 default:
4615 abort();
4616 }
4617
4618 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4619 if (size == 3) {
4620 neon_load_reg64(cpu_V0, rm + pass);
4621 tcg_gen_movi_i64(cpu_V1, imm);
4622 switch (op) {
4623 case 0: /* VSHR */
4624 case 1: /* VSRA */
4625 if (u)
4626 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4627 else
ad69471c 4628 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4629 break;
ad69471c
PB		 4630 case 2: /* VRSHR */
4631 case 3: /* VRSRA */
4632 if (u)
4633 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4634 else
ad69471c 4635 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4636 break;
ad69471c
PB		 4637 case 4: /* VSRI */
4638 if (!u)
4639 return 1;
4640 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4641 break;
4642 case 5: /* VSHL, VSLI */
4643 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4644 break;
4645 case 6: /* VQSHL */
4646 if (u)
4647 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4648 else
ad69471c
PB		 4649 gen_helper_neon_qshl_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
4650 break;
4651 case 7: /* VQSHLU */
4652 gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1);
9ee6e8bb 4653 break;
9ee6e8bb 4654 }
ad69471c
PB		 4655 if (op == 1 || op == 3) {
4656 /* Accumulate. */
4657 neon_load_reg64(cpu_V0, rd + pass);
4658 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4659 } else if (op == 4 || (op == 5 && u)) {
4660 /* Insert */
4661 cpu_abort(env, "VS[LR]I.64 not implemented");
4662 }
4663 neon_store_reg64(cpu_V0, rd + pass);
4664 } else { /* size < 3 */
4665 /* Operands in T0 and T1. */
dd8fbd78
FN		 4666 tmp = neon_load_reg(rm, pass);
4667 tmp2 = new_tmp();
4668 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4669 switch (op) {
4670 case 0: /* VSHR */
4671 case 1: /* VSRA */
4672 GEN_NEON_INTEGER_OP(shl);
4673 break;
4674 case 2: /* VRSHR */
4675 case 3: /* VRSRA */
4676 GEN_NEON_INTEGER_OP(rshl);
4677 break;
4678 case 4: /* VSRI */
4679 if (!u)
4680 return 1;
4681 GEN_NEON_INTEGER_OP(shl);
4682 break;
4683 case 5: /* VSHL, VSLI */
4684 switch (size) {
dd8fbd78
FN		 4685 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4686 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4687 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4688 default: return 1;
4689 }
4690 break;
4691 case 6: /* VQSHL */
4692 GEN_NEON_INTEGER_OP_ENV(qshl);
4693 break;
4694 case 7: /* VQSHLU */
4695 switch (size) {
dd8fbd78
FN		 4696 case 0: gen_helper_neon_qshl_u8(tmp, cpu_env, tmp, tmp2); break;
4697 case 1: gen_helper_neon_qshl_u16(tmp, cpu_env, tmp, tmp2); break;
4698 case 2: gen_helper_neon_qshl_u32(tmp, cpu_env, tmp, tmp2); break;
ad69471c
PB		 4699 default: return 1;
4700 }
4701 break;
4702 }
dd8fbd78 4703 dead_tmp(tmp2);
ad69471c
PB		 4704
4705 if (op == 1 || op == 3) {
4706 /* Accumulate. */
dd8fbd78
FN		 4707 tmp2 = neon_load_reg(rd, pass);
4708 gen_neon_add(size, tmp2, tmp);
4709 dead_tmp(tmp2);
ad69471c
PB		 4710 } else if (op == 4 || (op == 5 && u)) {
4711 /* Insert */
4712 switch (size) {
4713 case 0:
4714 if (op == 4)
ca9a32e4 4715 mask = 0xff >> -shift;
ad69471c 4716 else
ca9a32e4
JR		 4717 mask = (uint8_t)(0xff << shift);
4718 mask |= mask << 8;
4719 mask |= mask << 16;
ad69471c
PB		 4720 break;
4721 case 1:
4722 if (op == 4)
ca9a32e4 4723 mask = 0xffff >> -shift;
ad69471c 4724 else
ca9a32e4
JR		 4725 mask = (uint16_t)(0xffff << shift);
4726 mask |= mask << 16;
ad69471c
PB		 4727 break;
4728 case 2:
ca9a32e4
JR		 4729 if (shift < -31 || shift > 31) {
4730 mask = 0;
4731 } else {
4732 if (op == 4)
4733 mask = 0xffffffffu >> -shift;
4734 else
4735 mask = 0xffffffffu << shift;
4736 }
ad69471c
PB		 4737 break;
4738 default:
4739 abort();
4740 }
dd8fbd78 4741 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4742 tcg_gen_andi_i32(tmp, tmp, mask);
4743 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78
FN		 4744 tcg_gen_or_i32(tmp, tmp, tmp2);
4745 dead_tmp(tmp2);
ad69471c 4746 }
dd8fbd78 4747 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4748 }
4749 } /* for pass */
4750 } else if (op < 10) {
ad69471c 4751 /* Shift by immediate and narrow:
9ee6e8bb
PB		 4752 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4753 shift = shift - (1 << (size + 3));
4754 size++;
9ee6e8bb
PB		 4755 switch (size) {
4756 case 1:
ad69471c 4757 imm = (uint16_t)shift;
9ee6e8bb 4758 imm |= imm << 16;
ad69471c 4759 tmp2 = tcg_const_i32(imm);
a7812ae4 4760 TCGV_UNUSED_I64(tmp64);
9ee6e8bb
PB		 4761 break;
4762 case 2:
ad69471c
PB		 4763 imm = (uint32_t)shift;
4764 tmp2 = tcg_const_i32(imm);
a7812ae4 4765 TCGV_UNUSED_I64(tmp64);
4cc633c3 4766 break;
9ee6e8bb 4767 case 3:
a7812ae4
PB		 4768 tmp64 = tcg_const_i64(shift);
4769 TCGV_UNUSED(tmp2);
9ee6e8bb
PB		 4770 break;
4771 default:
4772 abort();
4773 }
4774
ad69471c
PB		 4775 for (pass = 0; pass < 2; pass++) {
4776 if (size == 3) {
4777 neon_load_reg64(cpu_V0, rm + pass);
4778 if (q) {
4779 if (u)
a7812ae4 4780 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4781 else
a7812ae4 4782 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c
PB		 4783 } else {
4784 if (u)
a7812ae4 4785 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4786 else
a7812ae4 4787 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c 4788 }
2c0262af 4789 } else {
ad69471c
PB		 4790 tmp = neon_load_reg(rm + pass, 0);
4791 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
36aa55dc
PB		 4792 tmp3 = neon_load_reg(rm + pass, 1);
4793 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4794 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
ad69471c 4795 dead_tmp(tmp);
36aa55dc 4796 dead_tmp(tmp3);
9ee6e8bb 4797 }
ad69471c
PB		 4798 tmp = new_tmp();
4799 if (op == 8 && !u) {
4800 gen_neon_narrow(size - 1, tmp, cpu_V0);
9ee6e8bb 4801 } else {
ad69471c
PB		 4802 if (op == 8)
4803 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
9ee6e8bb 4804 else
ad69471c
PB		 4805 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4806 }
2301db49 4807 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4808 } /* for pass */
b75263d6
JR		 4809 if (size == 3) {
4810 tcg_temp_free_i64(tmp64);
2301db49
JR		 4811 } else {
4812 dead_tmp(tmp2);
b75263d6 4813 }
9ee6e8bb
PB		 4814 } else if (op == 10) {
4815 /* VSHLL */
ad69471c 4816 if (q || size == 3)
9ee6e8bb 4817 return 1;
ad69471c
PB		 4818 tmp = neon_load_reg(rm, 0);
4819 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4820 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4821 if (pass == 1)
4822 tmp = tmp2;
4823
4824 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4825
9ee6e8bb
PB		 4826 if (shift != 0) {
4827 /* The shift is less than the width of the source
ad69471c
PB		 4828 type, so we can just shift the whole register. */
4829 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4830 if (size < 2 || !u) {
4831 uint64_t imm64;
4832 if (size == 0) {
4833 imm = (0xffu >> (8 - shift));
4834 imm |= imm << 16;
4835 } else {
4836 imm = 0xffff >> (16 - shift);
9ee6e8bb 4837 }
ad69471c
PB		 4838 imm64 = imm | (((uint64_t)imm) << 32);
4839 tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64);
9ee6e8bb
PB		 4840 }
4841 }
ad69471c 4842 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 4843 }
4844 } else if (op == 15 || op == 16) {
4845 /* VCVT fixed-point. */
4846 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4847 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
9ee6e8bb
PB		 4848 if (op & 1) {
4849 if (u)
4373f3ce 4850 gen_vfp_ulto(0, shift);
9ee6e8bb 4851 else
4373f3ce 4852 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4853 } else {
4854 if (u)
4373f3ce 4855 gen_vfp_toul(0, shift);
9ee6e8bb 4856 else
4373f3ce 4857 gen_vfp_tosl(0, shift);
2c0262af 4858 }
4373f3ce 4859 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4860 }
4861 } else {
9ee6e8bb
PB		 4862 return 1;
4863 }
4864 } else { /* (insn & 0x00380080) == 0 */
4865 int invert;
4866
4867 op = (insn >> 8) & 0xf;
4868 /* One register and immediate. */
4869 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4870 invert = (insn & (1 << 5)) != 0;
4871 switch (op) {
4872 case 0: case 1:
4873 /* no-op */
4874 break;
4875 case 2: case 3:
4876 imm <<= 8;
4877 break;
4878 case 4: case 5:
4879 imm <<= 16;
4880 break;
4881 case 6: case 7:
4882 imm <<= 24;
4883 break;
4884 case 8: case 9:
4885 imm |= imm << 16;
4886 break;
4887 case 10: case 11:
4888 imm = (imm << 8) | (imm << 24);
4889 break;
4890 case 12:
4891 imm = (imm < 8) | 0xff;
4892 break;
4893 case 13:
4894 imm = (imm << 16) | 0xffff;
4895 break;
4896 case 14:
4897 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4898 if (invert)
4899 imm = ~imm;
4900 break;
4901 case 15:
4902 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4903 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4904 break;
4905 }
4906 if (invert)
4907 imm = ~imm;
4908
9ee6e8bb
PB		 4909 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4910 if (op & 1 && op < 12) {
ad69471c 4911 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4912 if (invert) {
4913 /* The immediate value has already been inverted, so
4914 BIC becomes AND. */
ad69471c 4915 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 4916 } else {
ad69471c 4917 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 4918 }
9ee6e8bb 4919 } else {
ad69471c
PB		 4920 /* VMOV, VMVN. */
4921 tmp = new_tmp();
9ee6e8bb 4922 if (op == 14 && invert) {
ad69471c
PB		 4923 uint32_t val;
4924 val = 0;
9ee6e8bb
PB		 4925 for (n = 0; n < 4; n++) {
4926 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 4927 val |= 0xff << (n * 8);
9ee6e8bb 4928 }
ad69471c
PB		 4929 tcg_gen_movi_i32(tmp, val);
4930 } else {
4931 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 4932 }
9ee6e8bb 4933 }
ad69471c 4934 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4935 }
4936 }
e4b3861d 4937 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 4938 if (size != 3) {
4939 op = (insn >> 8) & 0xf;
4940 if ((insn & (1 << 6)) == 0) {
4941 /* Three registers of different lengths. */
4942 int src1_wide;
4943 int src2_wide;
4944 int prewiden;
4945 /* prewiden, src1_wide, src2_wide */
4946 static const int neon_3reg_wide[16][3] = {
4947 {1, 0, 0}, /* VADDL */
4948 {1, 1, 0}, /* VADDW */
4949 {1, 0, 0}, /* VSUBL */
4950 {1, 1, 0}, /* VSUBW */
4951 {0, 1, 1}, /* VADDHN */
4952 {0, 0, 0}, /* VABAL */
4953 {0, 1, 1}, /* VSUBHN */
4954 {0, 0, 0}, /* VABDL */
4955 {0, 0, 0}, /* VMLAL */
4956 {0, 0, 0}, /* VQDMLAL */
4957 {0, 0, 0}, /* VMLSL */
4958 {0, 0, 0}, /* VQDMLSL */
4959 {0, 0, 0}, /* Integer VMULL */
4960 {0, 0, 0}, /* VQDMULL */
4961 {0, 0, 0} /* Polynomial VMULL */
4962 };
4963
4964 prewiden = neon_3reg_wide[op][0];
4965 src1_wide = neon_3reg_wide[op][1];
4966 src2_wide = neon_3reg_wide[op][2];
4967
ad69471c
PB		 4968 if (size == 0 && (op == 9 || op == 11 || op == 13))
4969 return 1;
4970
9ee6e8bb
PB		 4971 /* Avoid overlapping operands. Wide source operands are
4972 always aligned so will never overlap with wide
4973 destinations in problematic ways. */
8f8e3aa4 4974 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 4975 tmp = neon_load_reg(rm, 1);
4976 neon_store_scratch(2, tmp);
8f8e3aa4 4977 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 4978 tmp = neon_load_reg(rn, 1);
4979 neon_store_scratch(2, tmp);
9ee6e8bb 4980 }
a50f5b91 4981 TCGV_UNUSED(tmp3);
9ee6e8bb 4982 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4983 if (src1_wide) {
4984 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 4985 TCGV_UNUSED(tmp);
9ee6e8bb 4986 } else {
ad69471c 4987 if (pass == 1 && rd == rn) {
dd8fbd78 4988 tmp = neon_load_scratch(2);
9ee6e8bb 4989 } else {
ad69471c
PB		 4990 tmp = neon_load_reg(rn, pass);
4991 }
4992 if (prewiden) {
4993 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 4994 }
4995 }
ad69471c
PB		 4996 if (src2_wide) {
4997 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 4998 TCGV_UNUSED(tmp2);
9ee6e8bb 4999 } else {
ad69471c 5000 if (pass == 1 && rd == rm) {
dd8fbd78 5001 tmp2 = neon_load_scratch(2);
9ee6e8bb 5002 } else {
ad69471c
PB		 5003 tmp2 = neon_load_reg(rm, pass);
5004 }
5005 if (prewiden) {
5006 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5007 }
9ee6e8bb
PB		 5008 }
5009 switch (op) {
5010 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5011 gen_neon_addl(size);
9ee6e8bb 5012 break;
79b0e534 5013 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5014 gen_neon_subl(size);
9ee6e8bb
PB		 5015 break;
5016 case 5: case 7: /* VABAL, VABDL */
5017 switch ((size << 1) | u) {
ad69471c
PB		 5018 case 0:
5019 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5020 break;
5021 case 1:
5022 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5023 break;
5024 case 2:
5025 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5026 break;
5027 case 3:
5028 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5029 break;
5030 case 4:
5031 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5032 break;
5033 case 5:
5034 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5035 break;
9ee6e8bb
PB		 5036 default: abort();
5037 }
ad69471c
PB		 5038 dead_tmp(tmp2);
5039 dead_tmp(tmp);
9ee6e8bb
PB		 5040 break;
5041 case 8: case 9: case 10: case 11: case 12: case 13:
5042 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5043 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
dd8fbd78
FN		 5044 dead_tmp(tmp2);
5045 dead_tmp(tmp);
9ee6e8bb
PB		 5046 break;
5047 case 14: /* Polynomial VMULL */
5048 cpu_abort(env, "Polynomial VMULL not implemented");
5049
5050 default: /* 15 is RESERVED. */
5051 return 1;
5052 }
5053 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5054 /* Accumulate. */
5055 if (op == 10 || op == 11) {
ad69471c 5056 gen_neon_negl(cpu_V0, size);
9ee6e8bb
PB		 5057 }
5058
9ee6e8bb 5059 if (op != 13) {
ad69471c 5060 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb
PB		 5061 }
5062
5063 switch (op) {
5064 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
ad69471c 5065 gen_neon_addl(size);
9ee6e8bb
PB		 5066 break;
5067 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c
PB		 5068 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5069 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5070 break;
9ee6e8bb
PB		 5071 /* Fall through. */
5072 case 13: /* VQDMULL */
ad69471c 5073 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5074 break;
5075 default:
5076 abort();
5077 }
ad69471c 5078 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5079 } else if (op == 4 || op == 6) {
5080 /* Narrowing operation. */
ad69471c 5081 tmp = new_tmp();
79b0e534 5082 if (!u) {
9ee6e8bb 5083 switch (size) {
ad69471c
PB		 5084 case 0:
5085 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5086 break;
5087 case 1:
5088 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5089 break;
5090 case 2:
5091 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5092 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5093 break;
9ee6e8bb
PB		 5094 default: abort();
5095 }
5096 } else {
5097 switch (size) {
ad69471c
PB		 5098 case 0:
5099 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5100 break;
5101 case 1:
5102 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5103 break;
5104 case 2:
5105 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5106 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5107 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5108 break;
9ee6e8bb
PB		 5109 default: abort();
5110 }
5111 }
ad69471c
PB		 5112 if (pass == 0) {
5113 tmp3 = tmp;
5114 } else {
5115 neon_store_reg(rd, 0, tmp3);
5116 neon_store_reg(rd, 1, tmp);
5117 }
9ee6e8bb
PB		 5118 } else {
5119 /* Write back the result. */
ad69471c 5120 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5121 }
5122 }
5123 } else {
5124 /* Two registers and a scalar. */
5125 switch (op) {
5126 case 0: /* Integer VMLA scalar */
5127 case 1: /* Float VMLA scalar */
5128 case 4: /* Integer VMLS scalar */
5129 case 5: /* Floating point VMLS scalar */
5130 case 8: /* Integer VMUL scalar */
5131 case 9: /* Floating point VMUL scalar */
5132 case 12: /* VQDMULH scalar */
5133 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5134 tmp = neon_get_scalar(size, rm);
5135 neon_store_scratch(0, tmp);
9ee6e8bb 5136 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5137 tmp = neon_load_scratch(0);
5138 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5139 if (op == 12) {
5140 if (size == 1) {
dd8fbd78 5141 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5142 } else {
dd8fbd78 5143 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5144 }
5145 } else if (op == 13) {
5146 if (size == 1) {
dd8fbd78 5147 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5148 } else {
dd8fbd78 5149 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5150 }
5151 } else if (op & 1) {
dd8fbd78 5152 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5153 } else {
5154 switch (size) {
dd8fbd78
FN		 5155 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5156 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5157 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5158 default: return 1;
5159 }
5160 }
dd8fbd78 5161 dead_tmp(tmp2);
9ee6e8bb
PB		 5162 if (op < 8) {
5163 /* Accumulate. */
dd8fbd78 5164 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5165 switch (op) {
5166 case 0:
dd8fbd78 5167 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5168 break;
5169 case 1:
dd8fbd78 5170 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5171 break;
5172 case 4:
dd8fbd78 5173 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5174 break;
5175 case 5:
dd8fbd78 5176 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5177 break;
5178 default:
5179 abort();
5180 }
dd8fbd78 5181 dead_tmp(tmp2);
9ee6e8bb 5182 }
dd8fbd78 5183 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5184 }
5185 break;
5186 case 2: /* VMLAL sclar */
5187 case 3: /* VQDMLAL scalar */
5188 case 6: /* VMLSL scalar */
5189 case 7: /* VQDMLSL scalar */
5190 case 10: /* VMULL scalar */
5191 case 11: /* VQDMULL scalar */
ad69471c
PB		 5192 if (size == 0 && (op == 3 || op == 7 || op == 11))
5193 return 1;
5194
dd8fbd78
FN		 5195 tmp2 = neon_get_scalar(size, rm);
5196 tmp3 = neon_load_reg(rn, 1);
ad69471c 5197
9ee6e8bb 5198 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5199 if (pass == 0) {
5200 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5201 } else {
dd8fbd78 5202 tmp = tmp3;
9ee6e8bb 5203 }
ad69471c 5204 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
dd8fbd78 5205 dead_tmp(tmp);
9ee6e8bb 5206 if (op == 6 || op == 7) {
ad69471c
PB		 5207 gen_neon_negl(cpu_V0, size);
5208 }
5209 if (op != 11) {
5210 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5211 }
9ee6e8bb
PB		 5212 switch (op) {
5213 case 2: case 6:
ad69471c 5214 gen_neon_addl(size);
9ee6e8bb
PB		 5215 break;
5216 case 3: case 7:
ad69471c
PB		 5217 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5218 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5219 break;
5220 case 10:
5221 /* no-op */
5222 break;
5223 case 11:
ad69471c 5224 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5225 break;
5226 default:
5227 abort();
5228 }
ad69471c 5229 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5230 }
dd8fbd78
FN		 5231
5232 dead_tmp(tmp2);
5233
9ee6e8bb
PB		 5234 break;
5235 default: /* 14 and 15 are RESERVED */
5236 return 1;
5237 }
5238 }
5239 } else { /* size == 3 */
5240 if (!u) {
5241 /* Extract. */
9ee6e8bb 5242 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5243 count = q + 1;
5244
5245 if (imm > 7 && !q)
5246 return 1;
5247
5248 if (imm == 0) {
5249 neon_load_reg64(cpu_V0, rn);
5250 if (q) {
5251 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5252 }
ad69471c
PB		 5253 } else if (imm == 8) {
5254 neon_load_reg64(cpu_V0, rn + 1);
5255 if (q) {
5256 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5257 }
ad69471c 5258 } else if (q) {
a7812ae4 5259 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5260 if (imm < 8) {
5261 neon_load_reg64(cpu_V0, rn);
a7812ae4 5262 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5263 } else {
5264 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5265 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5266 }
5267 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5268 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5269 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5270 if (imm < 8) {
5271 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5272 } else {
ad69471c
PB		 5273 neon_load_reg64(cpu_V1, rm + 1);
5274 imm -= 8;
9ee6e8bb 5275 }
ad69471c 5276 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5277 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5278 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5279 tcg_temp_free_i64(tmp64);
ad69471c 5280 } else {
a7812ae4 5281 /* BUGFIX */
ad69471c 5282 neon_load_reg64(cpu_V0, rn);
a7812ae4 5283 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5284 neon_load_reg64(cpu_V1, rm);
a7812ae4 5285 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5286 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5287 }
5288 neon_store_reg64(cpu_V0, rd);
5289 if (q) {
5290 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5291 }
5292 } else if ((insn & (1 << 11)) == 0) {
5293 /* Two register misc. */
5294 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5295 size = (insn >> 18) & 3;
5296 switch (op) {
5297 case 0: /* VREV64 */
5298 if (size == 3)
5299 return 1;
5300 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5301 tmp = neon_load_reg(rm, pass * 2);
5302 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5303 switch (size) {
dd8fbd78
FN		 5304 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5305 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5306 case 2: /* no-op */ break;
5307 default: abort();
5308 }
dd8fbd78 5309 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5310 if (size == 2) {
dd8fbd78 5311 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5312 } else {
9ee6e8bb 5313 switch (size) {
dd8fbd78
FN		 5314 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5315 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5316 default: abort();
5317 }
dd8fbd78 5318 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5319 }
5320 }
5321 break;
5322 case 4: case 5: /* VPADDL */
5323 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5324 if (size == 3)
5325 return 1;
ad69471c
PB		 5326 for (pass = 0; pass < q + 1; pass++) {
5327 tmp = neon_load_reg(rm, pass * 2);
5328 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5329 tmp = neon_load_reg(rm, pass * 2 + 1);
5330 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5331 switch (size) {
5332 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5333 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5334 case 2: tcg_gen_add_i64(CPU_V001); break;
5335 default: abort();
5336 }
9ee6e8bb
PB		 5337 if (op >= 12) {
5338 /* Accumulate. */
ad69471c
PB		 5339 neon_load_reg64(cpu_V1, rd + pass);
5340 gen_neon_addl(size);
9ee6e8bb 5341 }
ad69471c 5342 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5343 }
5344 break;
5345 case 33: /* VTRN */
5346 if (size == 2) {
5347 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5348 tmp = neon_load_reg(rm, n);
5349 tmp2 = neon_load_reg(rd, n + 1);
5350 neon_store_reg(rm, n, tmp2);
5351 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5352 }
5353 } else {
5354 goto elementwise;
5355 }
5356 break;
5357 case 34: /* VUZP */
5358 /* Reg Before After
5359 Rd A3 A2 A1 A0 B2 B0 A2 A0
5360 Rm B3 B2 B1 B0 B3 B1 A3 A1
5361 */
5362 if (size == 3)
5363 return 1;
5364 gen_neon_unzip(rd, q, 0, size);
5365 gen_neon_unzip(rm, q, 4, size);
5366 if (q) {
5367 static int unzip_order_q[8] =
5368 {0, 2, 4, 6, 1, 3, 5, 7};
5369 for (n = 0; n < 8; n++) {
5370 int reg = (n < 4) ? rd : rm;
dd8fbd78
FN		 5371 tmp = neon_load_scratch(unzip_order_q[n]);
5372 neon_store_reg(reg, n % 4, tmp);
9ee6e8bb
PB		 5373 }
5374 } else {
5375 static int unzip_order[4] =
5376 {0, 4, 1, 5};
5377 for (n = 0; n < 4; n++) {
5378 int reg = (n < 2) ? rd : rm;
dd8fbd78
FN		 5379 tmp = neon_load_scratch(unzip_order[n]);
5380 neon_store_reg(reg, n % 2, tmp);
9ee6e8bb
PB		 5381 }
5382 }
5383 break;
5384 case 35: /* VZIP */
5385 /* Reg Before After
5386 Rd A3 A2 A1 A0 B1 A1 B0 A0
5387 Rm B3 B2 B1 B0 B3 A3 B2 A2
5388 */
5389 if (size == 3)
5390 return 1;
5391 count = (q ? 4 : 2);
5392 for (n = 0; n < count; n++) {
dd8fbd78
FN		 5393 tmp = neon_load_reg(rd, n);
5394 tmp2 = neon_load_reg(rd, n);
9ee6e8bb 5395 switch (size) {
dd8fbd78
FN		 5396 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5397 case 1: gen_neon_zip_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5398 case 2: /* no-op */; break;
5399 default: abort();
5400 }
dd8fbd78
FN		 5401 neon_store_scratch(n * 2, tmp);
5402 neon_store_scratch(n * 2 + 1, tmp2);
9ee6e8bb
PB		 5403 }
5404 for (n = 0; n < count * 2; n++) {
5405 int reg = (n < count) ? rd : rm;
dd8fbd78
FN		 5406 tmp = neon_load_scratch(n);
5407 neon_store_reg(reg, n % count, tmp);
9ee6e8bb
PB		 5408 }
5409 break;
5410 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5411 if (size == 3)
5412 return 1;
a50f5b91 5413 TCGV_UNUSED(tmp2);
9ee6e8bb 5414 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5415 neon_load_reg64(cpu_V0, rm + pass);
5416 tmp = new_tmp();
9ee6e8bb 5417 if (op == 36 && q == 0) {
ad69471c 5418 gen_neon_narrow(size, tmp, cpu_V0);
9ee6e8bb 5419 } else if (q) {
ad69471c 5420 gen_neon_narrow_satu(size, tmp, cpu_V0);
9ee6e8bb 5421 } else {
ad69471c
PB		 5422 gen_neon_narrow_sats(size, tmp, cpu_V0);
5423 }
5424 if (pass == 0) {
5425 tmp2 = tmp;
5426 } else {
5427 neon_store_reg(rd, 0, tmp2);
5428 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5429 }
9ee6e8bb
PB		 5430 }
5431 break;
5432 case 38: /* VSHLL */
ad69471c 5433 if (q || size == 3)
9ee6e8bb 5434 return 1;
ad69471c
PB		 5435 tmp = neon_load_reg(rm, 0);
5436 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5437 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5438 if (pass == 1)
5439 tmp = tmp2;
5440 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5441 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5442 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5443 }
5444 break;
60011498
PB		 5445 case 44: /* VCVT.F16.F32 */
5446 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5447 return 1;
5448 tmp = new_tmp();
5449 tmp2 = new_tmp();
5450 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5451 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5452 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5453 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5454 tcg_gen_shli_i32(tmp2, tmp2, 16);
5455 tcg_gen_or_i32(tmp2, tmp2, tmp);
5456 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5457 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5458 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5459 neon_store_reg(rd, 0, tmp2);
5460 tmp2 = new_tmp();
5461 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5462 tcg_gen_shli_i32(tmp2, tmp2, 16);
5463 tcg_gen_or_i32(tmp2, tmp2, tmp);
5464 neon_store_reg(rd, 1, tmp2);
5465 dead_tmp(tmp);
5466 break;
5467 case 46: /* VCVT.F32.F16 */
5468 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5469 return 1;
5470 tmp3 = new_tmp();
5471 tmp = neon_load_reg(rm, 0);
5472 tmp2 = neon_load_reg(rm, 1);
5473 tcg_gen_ext16u_i32(tmp3, tmp);
5474 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5475 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5476 tcg_gen_shri_i32(tmp3, tmp, 16);
5477 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5478 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5479 dead_tmp(tmp);
5480 tcg_gen_ext16u_i32(tmp3, tmp2);
5481 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5482 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5483 tcg_gen_shri_i32(tmp3, tmp2, 16);
5484 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5485 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5486 dead_tmp(tmp2);
5487 dead_tmp(tmp3);
5488 break;
9ee6e8bb
PB		 5489 default:
5490 elementwise:
5491 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5492 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5493 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5494 neon_reg_offset(rm, pass));
dd8fbd78 5495 TCGV_UNUSED(tmp);
9ee6e8bb 5496 } else {
dd8fbd78 5497 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5498 }
5499 switch (op) {
5500 case 1: /* VREV32 */
5501 switch (size) {
dd8fbd78
FN		 5502 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5503 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5504 default: return 1;
5505 }
5506 break;
5507 case 2: /* VREV16 */
5508 if (size != 0)
5509 return 1;
dd8fbd78 5510 gen_rev16(tmp);
9ee6e8bb 5511 break;
9ee6e8bb
PB		 5512 case 8: /* CLS */
5513 switch (size) {
dd8fbd78
FN		 5514 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5515 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5516 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5517 default: return 1;
5518 }
5519 break;
5520 case 9: /* CLZ */
5521 switch (size) {
dd8fbd78
FN		 5522 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5523 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5524 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5525 default: return 1;
5526 }
5527 break;
5528 case 10: /* CNT */
5529 if (size != 0)
5530 return 1;
dd8fbd78 5531 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5532 break;
5533 case 11: /* VNOT */
5534 if (size != 0)
5535 return 1;
dd8fbd78 5536 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5537 break;
5538 case 14: /* VQABS */
5539 switch (size) {
dd8fbd78
FN		 5540 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5541 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5542 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5543 default: return 1;
5544 }
5545 break;
5546 case 15: /* VQNEG */
5547 switch (size) {
dd8fbd78
FN		 5548 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5549 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5550 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5551 default: return 1;
5552 }
5553 break;
5554 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5555 tmp2 = tcg_const_i32(0);
9ee6e8bb 5556 switch(size) {
dd8fbd78
FN		 5557 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5558 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5559 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5560 default: return 1;
5561 }
dd8fbd78 5562 tcg_temp_free(tmp2);
9ee6e8bb 5563 if (op == 19)
dd8fbd78 5564 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5565 break;
5566 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5567 tmp2 = tcg_const_i32(0);
9ee6e8bb 5568 switch(size) {
dd8fbd78
FN		 5569 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5570 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5571 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5572 default: return 1;
5573 }
dd8fbd78 5574 tcg_temp_free(tmp2);
9ee6e8bb 5575 if (op == 20)
dd8fbd78 5576 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5577 break;
5578 case 18: /* VCEQ #0 */
dd8fbd78 5579 tmp2 = tcg_const_i32(0);
9ee6e8bb 5580 switch(size) {
dd8fbd78
FN		 5581 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5582 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5583 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5584 default: return 1;
5585 }
dd8fbd78 5586 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5587 break;
5588 case 22: /* VABS */
5589 switch(size) {
dd8fbd78
FN		 5590 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5591 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5592 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5593 default: return 1;
5594 }
5595 break;
5596 case 23: /* VNEG */
ad69471c
PB		 5597 if (size == 3)
5598 return 1;
dd8fbd78
FN		 5599 tmp2 = tcg_const_i32(0);
5600 gen_neon_rsb(size, tmp, tmp2);
5601 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5602 break;
5603 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
dd8fbd78
FN		 5604 tmp2 = tcg_const_i32(0);
5605 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5606 tcg_temp_free(tmp2);
9ee6e8bb 5607 if (op == 27)
dd8fbd78 5608 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5609 break;
5610 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
dd8fbd78
FN		 5611 tmp2 = tcg_const_i32(0);
5612 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5613 tcg_temp_free(tmp2);
9ee6e8bb 5614 if (op == 28)
dd8fbd78 5615 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5616 break;
5617 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5618 tmp2 = tcg_const_i32(0);
5619 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5620 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5621 break;
5622 case 30: /* Float VABS */
4373f3ce 5623 gen_vfp_abs(0);
9ee6e8bb
PB		 5624 break;
5625 case 31: /* Float VNEG */
4373f3ce 5626 gen_vfp_neg(0);
9ee6e8bb
PB		 5627 break;
5628 case 32: /* VSWP */
dd8fbd78
FN		 5629 tmp2 = neon_load_reg(rd, pass);
5630 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5631 break;
5632 case 33: /* VTRN */
dd8fbd78 5633 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5634 switch (size) {
dd8fbd78
FN		 5635 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5636 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5637 case 2: abort();
5638 default: return 1;
5639 }
dd8fbd78 5640 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5641 break;
5642 case 56: /* Integer VRECPE */
dd8fbd78 5643 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5644 break;
5645 case 57: /* Integer VRSQRTE */
dd8fbd78 5646 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5647 break;
5648 case 58: /* Float VRECPE */
4373f3ce 5649 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5650 break;
5651 case 59: /* Float VRSQRTE */
4373f3ce 5652 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5653 break;
5654 case 60: /* VCVT.F32.S32 */
4373f3ce 5655 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5656 break;
5657 case 61: /* VCVT.F32.U32 */
4373f3ce 5658 gen_vfp_touiz(0);
9ee6e8bb
PB		 5659 break;
5660 case 62: /* VCVT.S32.F32 */
4373f3ce 5661 gen_vfp_sito(0);
9ee6e8bb
PB		 5662 break;
5663 case 63: /* VCVT.U32.F32 */
4373f3ce 5664 gen_vfp_uito(0);
9ee6e8bb
PB		 5665 break;
5666 default:
5667 /* Reserved: 21, 29, 39-56 */
5668 return 1;
5669 }
5670 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5671 tcg_gen_st_f32(cpu_F0s, cpu_env,
5672 neon_reg_offset(rd, pass));
9ee6e8bb 5673 } else {
dd8fbd78 5674 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5675 }
5676 }
5677 break;
5678 }
5679 } else if ((insn & (1 << 10)) == 0) {
5680 /* VTBL, VTBX. */
3018f259 5681 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5682 if (insn & (1 << 6)) {
8f8e3aa4 5683 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5684 } else {
8f8e3aa4
PB		 5685 tmp = new_tmp();
5686 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5687 }
8f8e3aa4 5688 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5689 tmp4 = tcg_const_i32(rn);
5690 tmp5 = tcg_const_i32(n);
5691 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
3018f259 5692 dead_tmp(tmp);
9ee6e8bb 5693 if (insn & (1 << 6)) {
8f8e3aa4 5694 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5695 } else {
8f8e3aa4
PB		 5696 tmp = new_tmp();
5697 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5698 }
8f8e3aa4 5699 tmp3 = neon_load_reg(rm, 1);
b75263d6 5700 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5701 tcg_temp_free_i32(tmp5);
5702 tcg_temp_free_i32(tmp4);
8f8e3aa4 5703 neon_store_reg(rd, 0, tmp2);
3018f259
PB		 5704 neon_store_reg(rd, 1, tmp3);
5705 dead_tmp(tmp);
9ee6e8bb
PB		 5706 } else if ((insn & 0x380) == 0) {
5707 /* VDUP */
5708 if (insn & (1 << 19)) {
dd8fbd78 5709 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5710 } else {
dd8fbd78 5711 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5712 }
5713 if (insn & (1 << 16)) {
dd8fbd78 5714 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5715 } else if (insn & (1 << 17)) {
5716 if ((insn >> 18) & 1)
dd8fbd78 5717 gen_neon_dup_high16(tmp);
9ee6e8bb 5718 else
dd8fbd78 5719 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5720 }
5721 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 5722 tmp2 = new_tmp();
5723 tcg_gen_mov_i32(tmp2, tmp);
5724 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5725 }
dd8fbd78 5726 dead_tmp(tmp);
9ee6e8bb
PB		 5727 } else {
5728 return 1;
5729 }
5730 }
5731 }
5732 return 0;
5733}
5734
fe1479c3
PB		 5735static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5736{
5737 int crn = (insn >> 16) & 0xf;
5738 int crm = insn & 0xf;
5739 int op1 = (insn >> 21) & 7;
5740 int op2 = (insn >> 5) & 7;
5741 int rt = (insn >> 12) & 0xf;
5742 TCGv tmp;
5743
5744 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5745 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5746 /* TEECR */
5747 if (IS_USER(s))
5748 return 1;
5749 tmp = load_cpu_field(teecr);
5750 store_reg(s, rt, tmp);
5751 return 0;
5752 }
5753 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5754 /* TEEHBR */
5755 if (IS_USER(s) && (env->teecr & 1))
5756 return 1;
5757 tmp = load_cpu_field(teehbr);
5758 store_reg(s, rt, tmp);
5759 return 0;
5760 }
5761 }
5762 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5763 op1, crn, crm, op2);
5764 return 1;
5765}
5766
5767static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5768{
5769 int crn = (insn >> 16) & 0xf;
5770 int crm = insn & 0xf;
5771 int op1 = (insn >> 21) & 7;
5772 int op2 = (insn >> 5) & 7;
5773 int rt = (insn >> 12) & 0xf;
5774 TCGv tmp;
5775
5776 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5777 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5778 /* TEECR */
5779 if (IS_USER(s))
5780 return 1;
5781 tmp = load_reg(s, rt);
5782 gen_helper_set_teecr(cpu_env, tmp);
5783 dead_tmp(tmp);
5784 return 0;
5785 }
5786 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5787 /* TEEHBR */
5788 if (IS_USER(s) && (env->teecr & 1))
5789 return 1;
5790 tmp = load_reg(s, rt);
5791 store_cpu_field(tmp, teehbr);
5792 return 0;
5793 }
5794 }
5795 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5796 op1, crn, crm, op2);
5797 return 1;
5798}
5799
9ee6e8bb
PB		 5800static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5801{
5802 int cpnum;
5803
5804 cpnum = (insn >> 8) & 0xf;
5805 if (arm_feature(env, ARM_FEATURE_XSCALE)
5806 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5807 return 1;
5808
5809 switch (cpnum) {
5810 case 0:
5811 case 1:
5812 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5813 return disas_iwmmxt_insn(env, s, insn);
5814 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5815 return disas_dsp_insn(env, s, insn);
5816 }
5817 return 1;
5818 case 10:
5819 case 11:
5820 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 5821 case 14:
5822 /* Coprocessors 7-15 are architecturally reserved by ARM.
5823 Unfortunately Intel decided to ignore this. */
5824 if (arm_feature(env, ARM_FEATURE_XSCALE))
5825 goto board;
5826 if (insn & (1 << 20))
5827 return disas_cp14_read(env, s, insn);
5828 else
5829 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 5830 case 15:
5831 return disas_cp15_insn (env, s, insn);
5832 default:
fe1479c3 5833 board:
9ee6e8bb
PB		 5834 /* Unknown coprocessor. See if the board has hooked it. */
5835 return disas_cp_insn (env, s, insn);
5836 }
5837}
5838
5e3f878a
PB		 5839
5840/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 5841static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 5842{
5843 TCGv tmp;
5844 tmp = new_tmp();
5845 tcg_gen_trunc_i64_i32(tmp, val);
5846 store_reg(s, rlow, tmp);
5847 tmp = new_tmp();
5848 tcg_gen_shri_i64(val, val, 32);
5849 tcg_gen_trunc_i64_i32(tmp, val);
5850 store_reg(s, rhigh, tmp);
5851}
5852
5853/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 5854static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 5855{
a7812ae4 5856 TCGv_i64 tmp;
5e3f878a
PB		 5857 TCGv tmp2;
5858
36aa55dc 5859 /* Load value and extend to 64 bits. */
a7812ae4 5860 tmp = tcg_temp_new_i64();
5e3f878a
PB		 5861 tmp2 = load_reg(s, rlow);
5862 tcg_gen_extu_i32_i64(tmp, tmp2);
5863 dead_tmp(tmp2);
5864 tcg_gen_add_i64(val, val, tmp);
b75263d6 5865 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5866}
5867
5868/* load and add a 64-bit value from a register pair. */
a7812ae4 5869static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 5870{
a7812ae4 5871 TCGv_i64 tmp;
36aa55dc
PB		 5872 TCGv tmpl;
5873 TCGv tmph;
5e3f878a
PB		 5874
5875 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 5876 tmpl = load_reg(s, rlow);
5877 tmph = load_reg(s, rhigh);
a7812ae4 5878 tmp = tcg_temp_new_i64();
36aa55dc
PB		 5879 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5880 dead_tmp(tmpl);
5881 dead_tmp(tmph);
5e3f878a 5882 tcg_gen_add_i64(val, val, tmp);
b75263d6 5883 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5884}
5885
5886/* Set N and Z flags from a 64-bit value. */
a7812ae4 5887static void gen_logicq_cc(TCGv_i64 val)
5e3f878a
PB		 5888{
5889 TCGv tmp = new_tmp();
5890 gen_helper_logicq_cc(tmp, val);
6fbe23d5
PB		 5891 gen_logic_CC(tmp);
5892 dead_tmp(tmp);
5e3f878a
PB		 5893}
5894
426f5abc
PB		 5895/* Load/Store exclusive instructions are implemented by remembering
5896 the value/address loaded, and seeing if these are the same
5897 when the store is performed. This should be is sufficient to implement
5898 the architecturally mandated semantics, and avoids having to monitor
5899 regular stores.
5900
5901 In system emulation mode only one CPU will be running at once, so
5902 this sequence is effectively atomic. In user emulation mode we
5903 throw an exception and handle the atomic operation elsewhere. */
5904static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5905 TCGv addr, int size)
5906{
5907 TCGv tmp;
5908
5909 switch (size) {
5910 case 0:
5911 tmp = gen_ld8u(addr, IS_USER(s));
5912 break;
5913 case 1:
5914 tmp = gen_ld16u(addr, IS_USER(s));
5915 break;
5916 case 2:
5917 case 3:
5918 tmp = gen_ld32(addr, IS_USER(s));
5919 break;
5920 default:
5921 abort();
5922 }
5923 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5924 store_reg(s, rt, tmp);
5925 if (size == 3) {
5926 tcg_gen_addi_i32(addr, addr, 4);
5927 tmp = gen_ld32(addr, IS_USER(s));
5928 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5929 store_reg(s, rt2, tmp);
5930 }
5931 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5932}
5933
5934static void gen_clrex(DisasContext *s)
5935{
5936 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5937}
5938
5939#ifdef CONFIG_USER_ONLY
5940static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5941 TCGv addr, int size)
5942{
5943 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5944 tcg_gen_movi_i32(cpu_exclusive_info,
5945 size | (rd << 4) | (rt << 8) | (rt2 << 12));
5946 gen_set_condexec(s);
5947 gen_set_pc_im(s->pc - 4);
5948 gen_exception(EXCP_STREX);
5949 s->is_jmp = DISAS_JUMP;
5950}
5951#else
5952static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5953 TCGv addr, int size)
5954{
5955 TCGv tmp;
5956 int done_label;
5957 int fail_label;
5958
5959 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
5960 [addr] = {Rt};
5961 {Rd} = 0;
5962 } else {
5963 {Rd} = 1;
5964 } */
5965 fail_label = gen_new_label();
5966 done_label = gen_new_label();
5967 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
5968 switch (size) {
5969 case 0:
5970 tmp = gen_ld8u(addr, IS_USER(s));
5971 break;
5972 case 1:
5973 tmp = gen_ld16u(addr, IS_USER(s));
5974 break;
5975 case 2:
5976 case 3:
5977 tmp = gen_ld32(addr, IS_USER(s));
5978 break;
5979 default:
5980 abort();
5981 }
5982 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
5983 dead_tmp(tmp);
5984 if (size == 3) {
5985 TCGv tmp2 = new_tmp();
5986 tcg_gen_addi_i32(tmp2, addr, 4);
5987 tmp = gen_ld32(addr, IS_USER(s));
5988 dead_tmp(tmp2);
5989 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
5990 dead_tmp(tmp);
5991 }
5992 tmp = load_reg(s, rt);
5993 switch (size) {
5994 case 0:
5995 gen_st8(tmp, addr, IS_USER(s));
5996 break;
5997 case 1:
5998 gen_st16(tmp, addr, IS_USER(s));
5999 break;
6000 case 2:
6001 case 3:
6002 gen_st32(tmp, addr, IS_USER(s));
6003 break;
6004 default:
6005 abort();
6006 }
6007 if (size == 3) {
6008 tcg_gen_addi_i32(addr, addr, 4);
6009 tmp = load_reg(s, rt2);
6010 gen_st32(tmp, addr, IS_USER(s));
6011 }
6012 tcg_gen_movi_i32(cpu_R[rd], 0);
6013 tcg_gen_br(done_label);
6014 gen_set_label(fail_label);
6015 tcg_gen_movi_i32(cpu_R[rd], 1);
6016 gen_set_label(done_label);
6017 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6018}
6019#endif
6020
9ee6e8bb
PB		 6021static void disas_arm_insn(CPUState * env, DisasContext *s)
6022{
6023 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6024 TCGv tmp;
3670669c 6025 TCGv tmp2;
6ddbc6e4 6026 TCGv tmp3;
b0109805 6027 TCGv addr;
a7812ae4 6028 TCGv_i64 tmp64;
9ee6e8bb
PB		 6029
6030 insn = ldl_code(s->pc);
6031 s->pc += 4;
6032
6033 /* M variants do not implement ARM mode. */
6034 if (IS_M(env))
6035 goto illegal_op;
6036 cond = insn >> 28;
6037 if (cond == 0xf){
6038 /* Unconditional instructions. */
6039 if (((insn >> 25) & 7) == 1) {
6040 /* NEON Data processing. */
6041 if (!arm_feature(env, ARM_FEATURE_NEON))
6042 goto illegal_op;
6043
6044 if (disas_neon_data_insn(env, s, insn))
6045 goto illegal_op;
6046 return;
6047 }
6048 if ((insn & 0x0f100000) == 0x04000000) {
6049 /* NEON load/store. */
6050 if (!arm_feature(env, ARM_FEATURE_NEON))
6051 goto illegal_op;
6052
6053 if (disas_neon_ls_insn(env, s, insn))
6054 goto illegal_op;
6055 return;
6056 }
6057 if ((insn & 0x0d70f000) == 0x0550f000)
6058 return; /* PLD */
6059 else if ((insn & 0x0ffffdff) == 0x01010000) {
6060 ARCH(6);
6061 /* setend */
6062 if (insn & (1 << 9)) {
6063 /* BE8 mode not implemented. */
6064 goto illegal_op;
6065 }
6066 return;
6067 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6068 switch ((insn >> 4) & 0xf) {
6069 case 1: /* clrex */
6070 ARCH(6K);
426f5abc 6071 gen_clrex(s);
9ee6e8bb
PB		 6072 return;
6073 case 4: /* dsb */
6074 case 5: /* dmb */
6075 case 6: /* isb */
6076 ARCH(7);
6077 /* We don't emulate caches so these are a no-op. */
6078 return;
6079 default:
6080 goto illegal_op;
6081 }
6082 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6083 /* srs */
c67b6b71 6084 int32_t offset;
9ee6e8bb
PB		 6085 if (IS_USER(s))
6086 goto illegal_op;
6087 ARCH(6);
6088 op1 = (insn & 0x1f);
6089 if (op1 == (env->uncached_cpsr & CPSR_M)) {
b0109805 6090 addr = load_reg(s, 13);
9ee6e8bb 6091 } else {
b0109805 6092 addr = new_tmp();
b75263d6
JR		 6093 tmp = tcg_const_i32(op1);
6094 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6095 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6096 }
6097 i = (insn >> 23) & 3;
6098 switch (i) {
6099 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6100 case 1: offset = 0; break; /* IA */
6101 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6102 case 3: offset = 4; break; /* IB */
6103 default: abort();
6104 }
6105 if (offset)
b0109805
PB		 6106 tcg_gen_addi_i32(addr, addr, offset);
6107 tmp = load_reg(s, 14);
6108 gen_st32(tmp, addr, 0);
c67b6b71 6109 tmp = load_cpu_field(spsr);
b0109805
PB		 6110 tcg_gen_addi_i32(addr, addr, 4);
6111 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6112 if (insn & (1 << 21)) {
6113 /* Base writeback. */
6114 switch (i) {
6115 case 0: offset = -8; break;
c67b6b71
FN		 6116 case 1: offset = 4; break;
6117 case 2: offset = -4; break;
9ee6e8bb
PB		 6118 case 3: offset = 0; break;
6119 default: abort();
6120 }
6121 if (offset)
c67b6b71 6122 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb 6123 if (op1 == (env->uncached_cpsr & CPSR_M)) {
c67b6b71 6124 store_reg(s, 13, addr);
9ee6e8bb 6125 } else {
b75263d6
JR		 6126 tmp = tcg_const_i32(op1);
6127 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6128 tcg_temp_free_i32(tmp);
c67b6b71 6129 dead_tmp(addr);
9ee6e8bb 6130 }
b0109805
PB		 6131 } else {
6132 dead_tmp(addr);
9ee6e8bb 6133 }
a990f58f 6134 return;
9ee6e8bb
PB		 6135 } else if ((insn & 0x0e5fffe0) == 0x081d0a00) {
6136 /* rfe */
c67b6b71 6137 int32_t offset;
9ee6e8bb
PB		 6138 if (IS_USER(s))
6139 goto illegal_op;
6140 ARCH(6);
6141 rn = (insn >> 16) & 0xf;
b0109805 6142 addr = load_reg(s, rn);
9ee6e8bb
PB		 6143 i = (insn >> 23) & 3;
6144 switch (i) {
b0109805 6145 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6146 case 1: offset = 0; break; /* IA */
6147 case 2: offset = -8; break; /* DB */
b0109805 6148 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6149 default: abort();
6150 }
6151 if (offset)
b0109805
PB		 6152 tcg_gen_addi_i32(addr, addr, offset);
6153 /* Load PC into tmp and CPSR into tmp2. */
6154 tmp = gen_ld32(addr, 0);
6155 tcg_gen_addi_i32(addr, addr, 4);
6156 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6157 if (insn & (1 << 21)) {
6158 /* Base writeback. */
6159 switch (i) {
b0109805 6160 case 0: offset = -8; break;
c67b6b71
FN		 6161 case 1: offset = 4; break;
6162 case 2: offset = -4; break;
b0109805 6163 case 3: offset = 0; break;
9ee6e8bb
PB		 6164 default: abort();
6165 }
6166 if (offset)
b0109805
PB		 6167 tcg_gen_addi_i32(addr, addr, offset);
6168 store_reg(s, rn, addr);
6169 } else {
6170 dead_tmp(addr);
9ee6e8bb 6171 }
b0109805 6172 gen_rfe(s, tmp, tmp2);
c67b6b71 6173 return;
9ee6e8bb
PB		 6174 } else if ((insn & 0x0e000000) == 0x0a000000) {
6175 /* branch link and change to thumb (blx <offset>) */
6176 int32_t offset;
6177
6178 val = (uint32_t)s->pc;
d9ba4830
PB		 6179 tmp = new_tmp();
6180 tcg_gen_movi_i32(tmp, val);
6181 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6182 /* Sign-extend the 24-bit offset */
6183 offset = (((int32_t)insn) << 8) >> 8;
6184 /* offset * 4 + bit24 * 2 + (thumb bit) */
6185 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6186 /* pipeline offset */
6187 val += 4;
d9ba4830 6188 gen_bx_im(s, val);
9ee6e8bb
PB		 6189 return;
6190 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6191 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6192 /* iWMMXt register transfer. */
6193 if (env->cp15.c15_cpar & (1 << 1))
6194 if (!disas_iwmmxt_insn(env, s, insn))
6195 return;
6196 }
6197 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6198 /* Coprocessor double register transfer. */
6199 } else if ((insn & 0x0f000010) == 0x0e000010) {
6200 /* Additional coprocessor register transfer. */
7997d92f 6201 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6202 uint32_t mask;
6203 uint32_t val;
6204 /* cps (privileged) */
6205 if (IS_USER(s))
6206 return;
6207 mask = val = 0;
6208 if (insn & (1 << 19)) {
6209 if (insn & (1 << 8))
6210 mask |= CPSR_A;
6211 if (insn & (1 << 7))
6212 mask |= CPSR_I;
6213 if (insn & (1 << 6))
6214 mask |= CPSR_F;
6215 if (insn & (1 << 18))
6216 val |= mask;
6217 }
7997d92f 6218 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6219 mask |= CPSR_M;
6220 val |= (insn & 0x1f);
6221 }
6222 if (mask) {
2fbac54b 6223 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6224 }
6225 return;
6226 }
6227 goto illegal_op;
6228 }
6229 if (cond != 0xe) {
6230 /* if not always execute, we generate a conditional jump to
6231 next instruction */
6232 s->condlabel = gen_new_label();
d9ba4830 6233 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6234 s->condjmp = 1;
6235 }
6236 if ((insn & 0x0f900000) == 0x03000000) {
6237 if ((insn & (1 << 21)) == 0) {
6238 ARCH(6T2);
6239 rd = (insn >> 12) & 0xf;
6240 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6241 if ((insn & (1 << 22)) == 0) {
6242 /* MOVW */
5e3f878a
PB		 6243 tmp = new_tmp();
6244 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6245 } else {
6246 /* MOVT */
5e3f878a 6247 tmp = load_reg(s, rd);
86831435 6248 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6249 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6250 }
5e3f878a 6251 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6252 } else {
6253 if (((insn >> 12) & 0xf) != 0xf)
6254 goto illegal_op;
6255 if (((insn >> 16) & 0xf) == 0) {
6256 gen_nop_hint(s, insn & 0xff);
6257 } else {
6258 /* CPSR = immediate */
6259 val = insn & 0xff;
6260 shift = ((insn >> 8) & 0xf) * 2;
6261 if (shift)
6262 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6263 i = ((insn & (1 << 22)) != 0);
2fbac54b 6264 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6265 goto illegal_op;
6266 }
6267 }
6268 } else if ((insn & 0x0f900000) == 0x01000000
6269 && (insn & 0x00000090) != 0x00000090) {
6270 /* miscellaneous instructions */
6271 op1 = (insn >> 21) & 3;
6272 sh = (insn >> 4) & 0xf;
6273 rm = insn & 0xf;
6274 switch (sh) {
6275 case 0x0: /* move program status register */
6276 if (op1 & 1) {
6277 /* PSR = reg */
2fbac54b 6278 tmp = load_reg(s, rm);
9ee6e8bb 6279 i = ((op1 & 2) != 0);
2fbac54b 6280 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6281 goto illegal_op;
6282 } else {
6283 /* reg = PSR */
6284 rd = (insn >> 12) & 0xf;
6285 if (op1 & 2) {
6286 if (IS_USER(s))
6287 goto illegal_op;
d9ba4830 6288 tmp = load_cpu_field(spsr);
9ee6e8bb 6289 } else {
d9ba4830
PB		 6290 tmp = new_tmp();
6291 gen_helper_cpsr_read(tmp);
9ee6e8bb 6292 }
d9ba4830 6293 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6294 }
6295 break;
6296 case 0x1:
6297 if (op1 == 1) {
6298 /* branch/exchange thumb (bx). */
d9ba4830
PB		 6299 tmp = load_reg(s, rm);
6300 gen_bx(s, tmp);
9ee6e8bb
PB		 6301 } else if (op1 == 3) {
6302 /* clz */
6303 rd = (insn >> 12) & 0xf;
1497c961
PB		 6304 tmp = load_reg(s, rm);
6305 gen_helper_clz(tmp, tmp);
6306 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6307 } else {
6308 goto illegal_op;
6309 }
6310 break;
6311 case 0x2:
6312 if (op1 == 1) {
6313 ARCH(5J); /* bxj */
6314 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6315 tmp = load_reg(s, rm);
6316 gen_bx(s, tmp);
9ee6e8bb
PB		 6317 } else {
6318 goto illegal_op;
6319 }
6320 break;
6321 case 0x3:
6322 if (op1 != 1)
6323 goto illegal_op;
6324
6325 /* branch link/exchange thumb (blx) */
d9ba4830
PB		 6326 tmp = load_reg(s, rm);
6327 tmp2 = new_tmp();
6328 tcg_gen_movi_i32(tmp2, s->pc);
6329 store_reg(s, 14, tmp2);
6330 gen_bx(s, tmp);
9ee6e8bb
PB		 6331 break;
6332 case 0x5: /* saturating add/subtract */
6333 rd = (insn >> 12) & 0xf;
6334 rn = (insn >> 16) & 0xf;
b40d0353 6335 tmp = load_reg(s, rm);
5e3f878a 6336 tmp2 = load_reg(s, rn);
9ee6e8bb 6337 if (op1 & 2)
5e3f878a 6338 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6339 if (op1 & 1)
5e3f878a 6340 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6341 else
5e3f878a
PB		 6342 gen_helper_add_saturate(tmp, tmp, tmp2);
6343 dead_tmp(tmp2);
6344 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6345 break;
6346 case 7: /* bkpt */
6347 gen_set_condexec(s);
5e3f878a 6348 gen_set_pc_im(s->pc - 4);
d9ba4830 6349 gen_exception(EXCP_BKPT);
9ee6e8bb
PB		 6350 s->is_jmp = DISAS_JUMP;
6351 break;
6352 case 0x8: /* signed multiply */
6353 case 0xa:
6354 case 0xc:
6355 case 0xe:
6356 rs = (insn >> 8) & 0xf;
6357 rn = (insn >> 12) & 0xf;
6358 rd = (insn >> 16) & 0xf;
6359 if (op1 == 1) {
6360 /* (32 * 16) >> 16 */
5e3f878a
PB		 6361 tmp = load_reg(s, rm);
6362 tmp2 = load_reg(s, rs);
9ee6e8bb 6363 if (sh & 4)
5e3f878a 6364 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6365 else
5e3f878a 6366 gen_sxth(tmp2);
a7812ae4
PB		 6367 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6368 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 6369 tmp = new_tmp();
a7812ae4 6370 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6371 tcg_temp_free_i64(tmp64);
9ee6e8bb 6372 if ((sh & 2) == 0) {
5e3f878a
PB		 6373 tmp2 = load_reg(s, rn);
6374 gen_helper_add_setq(tmp, tmp, tmp2);
6375 dead_tmp(tmp2);
9ee6e8bb 6376 }
5e3f878a 6377 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6378 } else {
6379 /* 16 * 16 */
5e3f878a
PB		 6380 tmp = load_reg(s, rm);
6381 tmp2 = load_reg(s, rs);
6382 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6383 dead_tmp(tmp2);
9ee6e8bb 6384 if (op1 == 2) {
a7812ae4
PB		 6385 tmp64 = tcg_temp_new_i64();
6386 tcg_gen_ext_i32_i64(tmp64, tmp);
22478e79 6387 dead_tmp(tmp);
a7812ae4
PB		 6388 gen_addq(s, tmp64, rn, rd);
6389 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6390 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6391 } else {
6392 if (op1 == 0) {
5e3f878a
PB		 6393 tmp2 = load_reg(s, rn);
6394 gen_helper_add_setq(tmp, tmp, tmp2);
6395 dead_tmp(tmp2);
9ee6e8bb 6396 }
5e3f878a 6397 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6398 }
6399 }
6400 break;
6401 default:
6402 goto illegal_op;
6403 }
6404 } else if (((insn & 0x0e000000) == 0 &&
6405 (insn & 0x00000090) != 0x90) ||
6406 ((insn & 0x0e000000) == (1 << 25))) {
6407 int set_cc, logic_cc, shiftop;
6408
6409 op1 = (insn >> 21) & 0xf;
6410 set_cc = (insn >> 20) & 1;
6411 logic_cc = table_logic_cc[op1] & set_cc;
6412
6413 /* data processing instruction */
6414 if (insn & (1 << 25)) {
6415 /* immediate operand */
6416 val = insn & 0xff;
6417 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6418 if (shift) {
9ee6e8bb 6419 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9
JR		 6420 }
6421 tmp2 = new_tmp();
6422 tcg_gen_movi_i32(tmp2, val);
6423 if (logic_cc && shift) {
6424 gen_set_CF_bit31(tmp2);
6425 }
9ee6e8bb
PB		 6426 } else {
6427 /* register */
6428 rm = (insn) & 0xf;
e9bb4aa9 6429 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6430 shiftop = (insn >> 5) & 3;
6431 if (!(insn & (1 << 4))) {
6432 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6433 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6434 } else {
6435 rs = (insn >> 8) & 0xf;
8984bd2e 6436 tmp = load_reg(s, rs);
e9bb4aa9 6437 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6438 }
6439 }
6440 if (op1 != 0x0f && op1 != 0x0d) {
6441 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6442 tmp = load_reg(s, rn);
6443 } else {
6444 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6445 }
6446 rd = (insn >> 12) & 0xf;
6447 switch(op1) {
6448 case 0x00:
e9bb4aa9
JR		 6449 tcg_gen_and_i32(tmp, tmp, tmp2);
6450 if (logic_cc) {
6451 gen_logic_CC(tmp);
6452 }
21aeb343 6453 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6454 break;
6455 case 0x01:
e9bb4aa9
JR		 6456 tcg_gen_xor_i32(tmp, tmp, tmp2);
6457 if (logic_cc) {
6458 gen_logic_CC(tmp);
6459 }
21aeb343 6460 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6461 break;
6462 case 0x02:
6463 if (set_cc && rd == 15) {
6464 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6465 if (IS_USER(s)) {
9ee6e8bb 6466 goto illegal_op;
e9bb4aa9
JR		 6467 }
6468 gen_helper_sub_cc(tmp, tmp, tmp2);
6469 gen_exception_return(s, tmp);
9ee6e8bb 6470 } else {
e9bb4aa9
JR		 6471 if (set_cc) {
6472 gen_helper_sub_cc(tmp, tmp, tmp2);
6473 } else {
6474 tcg_gen_sub_i32(tmp, tmp, tmp2);
6475 }
21aeb343 6476 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6477 }
6478 break;
6479 case 0x03:
e9bb4aa9
JR		 6480 if (set_cc) {
6481 gen_helper_sub_cc(tmp, tmp2, tmp);
6482 } else {
6483 tcg_gen_sub_i32(tmp, tmp2, tmp);
6484 }
21aeb343 6485 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6486 break;
6487 case 0x04:
e9bb4aa9
JR		 6488 if (set_cc) {
6489 gen_helper_add_cc(tmp, tmp, tmp2);
6490 } else {
6491 tcg_gen_add_i32(tmp, tmp, tmp2);
6492 }
21aeb343 6493 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6494 break;
6495 case 0x05:
e9bb4aa9
JR		 6496 if (set_cc) {
6497 gen_helper_adc_cc(tmp, tmp, tmp2);
6498 } else {
6499 gen_add_carry(tmp, tmp, tmp2);
6500 }
21aeb343 6501 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6502 break;
6503 case 0x06:
e9bb4aa9
JR		 6504 if (set_cc) {
6505 gen_helper_sbc_cc(tmp, tmp, tmp2);
6506 } else {
6507 gen_sub_carry(tmp, tmp, tmp2);
6508 }
21aeb343 6509 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6510 break;
6511 case 0x07:
e9bb4aa9
JR		 6512 if (set_cc) {
6513 gen_helper_sbc_cc(tmp, tmp2, tmp);
6514 } else {
6515 gen_sub_carry(tmp, tmp2, tmp);
6516 }
21aeb343 6517 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6518 break;
6519 case 0x08:
6520 if (set_cc) {
e9bb4aa9
JR		 6521 tcg_gen_and_i32(tmp, tmp, tmp2);
6522 gen_logic_CC(tmp);
9ee6e8bb 6523 }
e9bb4aa9 6524 dead_tmp(tmp);
9ee6e8bb
PB		 6525 break;
6526 case 0x09:
6527 if (set_cc) {
e9bb4aa9
JR		 6528 tcg_gen_xor_i32(tmp, tmp, tmp2);
6529 gen_logic_CC(tmp);
9ee6e8bb 6530 }
e9bb4aa9 6531 dead_tmp(tmp);
9ee6e8bb
PB		 6532 break;
6533 case 0x0a:
6534 if (set_cc) {
e9bb4aa9 6535 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6536 }
e9bb4aa9 6537 dead_tmp(tmp);
9ee6e8bb
PB		 6538 break;
6539 case 0x0b:
6540 if (set_cc) {
e9bb4aa9 6541 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6542 }
e9bb4aa9 6543 dead_tmp(tmp);
9ee6e8bb
PB		 6544 break;
6545 case 0x0c:
e9bb4aa9
JR		 6546 tcg_gen_or_i32(tmp, tmp, tmp2);
6547 if (logic_cc) {
6548 gen_logic_CC(tmp);
6549 }
21aeb343 6550 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6551 break;
6552 case 0x0d:
6553 if (logic_cc && rd == 15) {
6554 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6555 if (IS_USER(s)) {
9ee6e8bb 6556 goto illegal_op;
e9bb4aa9
JR		 6557 }
6558 gen_exception_return(s, tmp2);
9ee6e8bb 6559 } else {
e9bb4aa9
JR		 6560 if (logic_cc) {
6561 gen_logic_CC(tmp2);
6562 }
21aeb343 6563 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6564 }
6565 break;
6566 case 0x0e:
f669df27 6567 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6568 if (logic_cc) {
6569 gen_logic_CC(tmp);
6570 }
21aeb343 6571 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6572 break;
6573 default:
6574 case 0x0f:
e9bb4aa9
JR		 6575 tcg_gen_not_i32(tmp2, tmp2);
6576 if (logic_cc) {
6577 gen_logic_CC(tmp2);
6578 }
21aeb343 6579 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6580 break;
6581 }
e9bb4aa9
JR		 6582 if (op1 != 0x0f && op1 != 0x0d) {
6583 dead_tmp(tmp2);
6584 }
9ee6e8bb
PB		 6585 } else {
6586 /* other instructions */
6587 op1 = (insn >> 24) & 0xf;
6588 switch(op1) {
6589 case 0x0:
6590 case 0x1:
6591 /* multiplies, extra load/stores */
6592 sh = (insn >> 5) & 3;
6593 if (sh == 0) {
6594 if (op1 == 0x0) {
6595 rd = (insn >> 16) & 0xf;
6596 rn = (insn >> 12) & 0xf;
6597 rs = (insn >> 8) & 0xf;
6598 rm = (insn) & 0xf;
6599 op1 = (insn >> 20) & 0xf;
6600 switch (op1) {
6601 case 0: case 1: case 2: case 3: case 6:
6602 /* 32 bit mul */
5e3f878a
PB		 6603 tmp = load_reg(s, rs);
6604 tmp2 = load_reg(s, rm);
6605 tcg_gen_mul_i32(tmp, tmp, tmp2);
6606 dead_tmp(tmp2);
9ee6e8bb
PB		 6607 if (insn & (1 << 22)) {
6608 /* Subtract (mls) */
6609 ARCH(6T2);
5e3f878a
PB		 6610 tmp2 = load_reg(s, rn);
6611 tcg_gen_sub_i32(tmp, tmp2, tmp);
6612 dead_tmp(tmp2);
9ee6e8bb
PB		 6613 } else if (insn & (1 << 21)) {
6614 /* Add */
5e3f878a
PB		 6615 tmp2 = load_reg(s, rn);
6616 tcg_gen_add_i32(tmp, tmp, tmp2);
6617 dead_tmp(tmp2);
9ee6e8bb
PB		 6618 }
6619 if (insn & (1 << 20))
5e3f878a
PB		 6620 gen_logic_CC(tmp);
6621 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6622 break;
6623 default:
6624 /* 64 bit mul */
5e3f878a
PB		 6625 tmp = load_reg(s, rs);
6626 tmp2 = load_reg(s, rm);
9ee6e8bb 6627 if (insn & (1 << 22))
a7812ae4 6628 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6629 else
a7812ae4 6630 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
9ee6e8bb 6631 if (insn & (1 << 21)) /* mult accumulate */
a7812ae4 6632 gen_addq(s, tmp64, rn, rd);
9ee6e8bb
PB		 6633 if (!(insn & (1 << 23))) { /* double accumulate */
6634 ARCH(6);
a7812ae4
PB		 6635 gen_addq_lo(s, tmp64, rn);
6636 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 6637 }
6638 if (insn & (1 << 20))
a7812ae4
PB		 6639 gen_logicq_cc(tmp64);
6640 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6641 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6642 break;
6643 }
6644 } else {
6645 rn = (insn >> 16) & 0xf;
6646 rd = (insn >> 12) & 0xf;
6647 if (insn & (1 << 23)) {
6648 /* load/store exclusive */
86753403
PB		 6649 op1 = (insn >> 21) & 0x3;
6650 if (op1)
a47f43d2 6651 ARCH(6K);
86753403
PB		 6652 else
6653 ARCH(6);
3174f8e9 6654 addr = tcg_temp_local_new_i32();
98a46317 6655 load_reg_var(s, addr, rn);
9ee6e8bb 6656 if (insn & (1 << 20)) {
86753403
PB		 6657 switch (op1) {
6658 case 0: /* ldrex */
426f5abc 6659 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6660 break;
6661 case 1: /* ldrexd */
426f5abc 6662 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6663 break;
6664 case 2: /* ldrexb */
426f5abc 6665 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6666 break;
6667 case 3: /* ldrexh */
426f5abc 6668 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6669 break;
6670 default:
6671 abort();
6672 }
9ee6e8bb
PB		 6673 } else {
6674 rm = insn & 0xf;
86753403
PB		 6675 switch (op1) {
6676 case 0: /* strex */
426f5abc 6677 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6678 break;
6679 case 1: /* strexd */
502e64fe 6680 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6681 break;
6682 case 2: /* strexb */
426f5abc 6683 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6684 break;
6685 case 3: /* strexh */
426f5abc 6686 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6687 break;
6688 default:
6689 abort();
6690 }
9ee6e8bb 6691 }
3174f8e9 6692 tcg_temp_free(addr);
9ee6e8bb
PB		 6693 } else {
6694 /* SWP instruction */
6695 rm = (insn) & 0xf;
6696
8984bd2e
PB		 6697 /* ??? This is not really atomic. However we know
6698 we never have multiple CPUs running in parallel,
6699 so it is good enough. */
6700 addr = load_reg(s, rn);
6701 tmp = load_reg(s, rm);
9ee6e8bb 6702 if (insn & (1 << 22)) {
8984bd2e
PB		 6703 tmp2 = gen_ld8u(addr, IS_USER(s));
6704 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6705 } else {
8984bd2e
PB		 6706 tmp2 = gen_ld32(addr, IS_USER(s));
6707 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6708 }
8984bd2e
PB		 6709 dead_tmp(addr);
6710 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6711 }
6712 }
6713 } else {
6714 int address_offset;
6715 int load;
6716 /* Misc load/store */
6717 rn = (insn >> 16) & 0xf;
6718 rd = (insn >> 12) & 0xf;
b0109805 6719 addr = load_reg(s, rn);
9ee6e8bb 6720 if (insn & (1 << 24))
b0109805 6721 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6722 address_offset = 0;
6723 if (insn & (1 << 20)) {
6724 /* load */
6725 switch(sh) {
6726 case 1:
b0109805 6727 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6728 break;
6729 case 2:
b0109805 6730 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6731 break;
6732 default:
6733 case 3:
b0109805 6734 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6735 break;
6736 }
6737 load = 1;
6738 } else if (sh & 2) {
6739 /* doubleword */
6740 if (sh & 1) {
6741 /* store */
b0109805
PB		 6742 tmp = load_reg(s, rd);
6743 gen_st32(tmp, addr, IS_USER(s));
6744 tcg_gen_addi_i32(addr, addr, 4);
6745 tmp = load_reg(s, rd + 1);
6746 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6747 load = 0;
6748 } else {
6749 /* load */
b0109805
PB		 6750 tmp = gen_ld32(addr, IS_USER(s));
6751 store_reg(s, rd, tmp);
6752 tcg_gen_addi_i32(addr, addr, 4);
6753 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6754 rd++;
6755 load = 1;
6756 }
6757 address_offset = -4;
6758 } else {
6759 /* store */
b0109805
PB		 6760 tmp = load_reg(s, rd);
6761 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6762 load = 0;
6763 }
6764 /* Perform base writeback before the loaded value to
6765 ensure correct behavior with overlapping index registers.
6766 ldrd with base writeback is is undefined if the
6767 destination and index registers overlap. */
6768 if (!(insn & (1 << 24))) {
b0109805
PB		 6769 gen_add_datah_offset(s, insn, address_offset, addr);
6770 store_reg(s, rn, addr);
9ee6e8bb
PB		 6771 } else if (insn & (1 << 21)) {
6772 if (address_offset)
b0109805
PB		 6773 tcg_gen_addi_i32(addr, addr, address_offset);
6774 store_reg(s, rn, addr);
6775 } else {
6776 dead_tmp(addr);
9ee6e8bb
PB		 6777 }
6778 if (load) {
6779 /* Complete the load. */
b0109805 6780 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6781 }
6782 }
6783 break;
6784 case 0x4:
6785 case 0x5:
6786 goto do_ldst;
6787 case 0x6:
6788 case 0x7:
6789 if (insn & (1 << 4)) {
6790 ARCH(6);
6791 /* Armv6 Media instructions. */
6792 rm = insn & 0xf;
6793 rn = (insn >> 16) & 0xf;
2c0262af 6794 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6795 rs = (insn >> 8) & 0xf;
6796 switch ((insn >> 23) & 3) {
6797 case 0: /* Parallel add/subtract. */
6798 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6799 tmp = load_reg(s, rn);
6800 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6801 sh = (insn >> 5) & 7;
6802 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6803 goto illegal_op;
6ddbc6e4
PB		 6804 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6805 dead_tmp(tmp2);
6806 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6807 break;
6808 case 1:
6809 if ((insn & 0x00700020) == 0) {
6c95676b 6810 /* Halfword pack. */
3670669c
PB		 6811 tmp = load_reg(s, rn);
6812 tmp2 = load_reg(s, rm);
9ee6e8bb 6813 shift = (insn >> 7) & 0x1f;
3670669c
PB		 6814 if (insn & (1 << 6)) {
6815 /* pkhtb */
22478e79
AZ		 6816 if (shift == 0)
6817 shift = 31;
6818 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 6819 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 6820 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 6821 } else {
6822 /* pkhbt */
22478e79
AZ		 6823 if (shift)
6824 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 6825 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 6826 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6827 }
6828 tcg_gen_or_i32(tmp, tmp, tmp2);
22478e79 6829 dead_tmp(tmp2);
3670669c 6830 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6831 } else if ((insn & 0x00200020) == 0x00200000) {
6832 /* [us]sat */
6ddbc6e4 6833 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6834 shift = (insn >> 7) & 0x1f;
6835 if (insn & (1 << 6)) {
6836 if (shift == 0)
6837 shift = 31;
6ddbc6e4 6838 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6839 } else {
6ddbc6e4 6840 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6841 }
6842 sh = (insn >> 16) & 0x1f;
6843 if (sh != 0) {
b75263d6 6844 tmp2 = tcg_const_i32(sh);
9ee6e8bb 6845 if (insn & (1 << 22))
b75263d6 6846 gen_helper_usat(tmp, tmp, tmp2);
9ee6e8bb 6847 else
b75263d6
JR		 6848 gen_helper_ssat(tmp, tmp, tmp2);
6849 tcg_temp_free_i32(tmp2);
9ee6e8bb 6850 }
6ddbc6e4 6851 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6852 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6853 /* [us]sat16 */
6ddbc6e4 6854 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6855 sh = (insn >> 16) & 0x1f;
6856 if (sh != 0) {
b75263d6 6857 tmp2 = tcg_const_i32(sh);
9ee6e8bb 6858 if (insn & (1 << 22))
b75263d6 6859 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 6860 else
b75263d6
JR		 6861 gen_helper_ssat16(tmp, tmp, tmp2);
6862 tcg_temp_free_i32(tmp2);
9ee6e8bb 6863 }
6ddbc6e4 6864 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6865 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6866 /* Select bytes. */
6ddbc6e4
PB		 6867 tmp = load_reg(s, rn);
6868 tmp2 = load_reg(s, rm);
6869 tmp3 = new_tmp();
6870 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6871 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6872 dead_tmp(tmp3);
6873 dead_tmp(tmp2);
6874 store_reg(s, rd, tmp);
9ee6e8bb 6875 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6876 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6877 shift = (insn >> 10) & 3;
6878 /* ??? In many cases it's not neccessary to do a
6879 rotate, a shift is sufficient. */
6880 if (shift != 0)
f669df27 6881 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6882 op1 = (insn >> 20) & 7;
6883 switch (op1) {
5e3f878a
PB		 6884 case 0: gen_sxtb16(tmp); break;
6885 case 2: gen_sxtb(tmp); break;
6886 case 3: gen_sxth(tmp); break;
6887 case 4: gen_uxtb16(tmp); break;
6888 case 6: gen_uxtb(tmp); break;
6889 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 6890 default: goto illegal_op;
6891 }
6892 if (rn != 15) {
5e3f878a 6893 tmp2 = load_reg(s, rn);
9ee6e8bb 6894 if ((op1 & 3) == 0) {
5e3f878a 6895 gen_add16(tmp, tmp2);
9ee6e8bb 6896 } else {
5e3f878a
PB		 6897 tcg_gen_add_i32(tmp, tmp, tmp2);
6898 dead_tmp(tmp2);
9ee6e8bb
PB		 6899 }
6900 }
6c95676b 6901 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6902 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6903 /* rev */
b0109805 6904 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6905 if (insn & (1 << 22)) {
6906 if (insn & (1 << 7)) {
b0109805 6907 gen_revsh(tmp);
9ee6e8bb
PB		 6908 } else {
6909 ARCH(6T2);
b0109805 6910 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 6911 }
6912 } else {
6913 if (insn & (1 << 7))
b0109805 6914 gen_rev16(tmp);
9ee6e8bb 6915 else
66896cb8 6916 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 6917 }
b0109805 6918 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6919 } else {
6920 goto illegal_op;
6921 }
6922 break;
6923 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 6924 tmp = load_reg(s, rm);
6925 tmp2 = load_reg(s, rs);
9ee6e8bb
PB		 6926 if (insn & (1 << 20)) {
6927 /* Signed multiply most significant [accumulate]. */
a7812ae4 6928 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 6929 if (insn & (1 << 5))
a7812ae4
PB		 6930 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
6931 tcg_gen_shri_i64(tmp64, tmp64, 32);
5e3f878a 6932 tmp = new_tmp();
a7812ae4 6933 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6934 tcg_temp_free_i64(tmp64);
955a7dd5
AZ		 6935 if (rd != 15) {
6936 tmp2 = load_reg(s, rd);
9ee6e8bb 6937 if (insn & (1 << 6)) {
5e3f878a 6938 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 6939 } else {
5e3f878a 6940 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 6941 }
5e3f878a 6942 dead_tmp(tmp2);
9ee6e8bb 6943 }
955a7dd5 6944 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6945 } else {
6946 if (insn & (1 << 5))
5e3f878a
PB		 6947 gen_swap_half(tmp2);
6948 gen_smul_dual(tmp, tmp2);
6949 /* This addition cannot overflow. */
6950 if (insn & (1 << 6)) {
6951 tcg_gen_sub_i32(tmp, tmp, tmp2);
6952 } else {
6953 tcg_gen_add_i32(tmp, tmp, tmp2);
6954 }
6955 dead_tmp(tmp2);
9ee6e8bb 6956 if (insn & (1 << 22)) {
5e3f878a 6957 /* smlald, smlsld */
a7812ae4
PB		 6958 tmp64 = tcg_temp_new_i64();
6959 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 6960 dead_tmp(tmp);
a7812ae4
PB		 6961 gen_addq(s, tmp64, rd, rn);
6962 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 6963 tcg_temp_free_i64(tmp64);
9ee6e8bb 6964 } else {
5e3f878a 6965 /* smuad, smusd, smlad, smlsd */
22478e79 6966 if (rd != 15)
9ee6e8bb 6967 {
22478e79 6968 tmp2 = load_reg(s, rd);
5e3f878a
PB		 6969 gen_helper_add_setq(tmp, tmp, tmp2);
6970 dead_tmp(tmp2);
9ee6e8bb 6971 }
22478e79 6972 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6973 }
6974 }
6975 break;
6976 case 3:
6977 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6978 switch (op1) {
6979 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 6980 ARCH(6);
6981 tmp = load_reg(s, rm);
6982 tmp2 = load_reg(s, rs);
6983 gen_helper_usad8(tmp, tmp, tmp2);
6984 dead_tmp(tmp2);
ded9d295
AZ		 6985 if (rd != 15) {
6986 tmp2 = load_reg(s, rd);
6ddbc6e4
PB		 6987 tcg_gen_add_i32(tmp, tmp, tmp2);
6988 dead_tmp(tmp2);
9ee6e8bb 6989 }
ded9d295 6990 store_reg(s, rn, tmp);
9ee6e8bb
PB		 6991 break;
6992 case 0x20: case 0x24: case 0x28: case 0x2c:
6993 /* Bitfield insert/clear. */
6994 ARCH(6T2);
6995 shift = (insn >> 7) & 0x1f;
6996 i = (insn >> 16) & 0x1f;
6997 i = i + 1 - shift;
6998 if (rm == 15) {
5e3f878a
PB		 6999 tmp = new_tmp();
7000 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7001 } else {
5e3f878a 7002 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7003 }
7004 if (i != 32) {
5e3f878a 7005 tmp2 = load_reg(s, rd);
8f8e3aa4 7006 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
5e3f878a 7007 dead_tmp(tmp2);
9ee6e8bb 7008 }
5e3f878a 7009 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7010 break;
7011 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7012 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7013 ARCH(6T2);
5e3f878a 7014 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7015 shift = (insn >> 7) & 0x1f;
7016 i = ((insn >> 16) & 0x1f) + 1;
7017 if (shift + i > 32)
7018 goto illegal_op;
7019 if (i < 32) {
7020 if (op1 & 0x20) {
5e3f878a 7021 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7022 } else {
5e3f878a 7023 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7024 }
7025 }
5e3f878a 7026 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7027 break;
7028 default:
7029 goto illegal_op;
7030 }
7031 break;
7032 }
7033 break;
7034 }
7035 do_ldst:
7036 /* Check for undefined extension instructions
7037 * per the ARM Bible IE:
7038 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7039 */
7040 sh = (0xf << 20) | (0xf << 4);
7041 if (op1 == 0x7 && ((insn & sh) == sh))
7042 {
7043 goto illegal_op;
7044 }
7045 /* load/store byte/word */
7046 rn = (insn >> 16) & 0xf;
7047 rd = (insn >> 12) & 0xf;
b0109805 7048 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7049 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7050 if (insn & (1 << 24))
b0109805 7051 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7052 if (insn & (1 << 20)) {
7053 /* load */
9ee6e8bb 7054 if (insn & (1 << 22)) {
b0109805 7055 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7056 } else {
b0109805 7057 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7058 }
9ee6e8bb
PB		 7059 } else {
7060 /* store */
b0109805 7061 tmp = load_reg(s, rd);
9ee6e8bb 7062 if (insn & (1 << 22))
b0109805 7063 gen_st8(tmp, tmp2, i);
9ee6e8bb 7064 else
b0109805 7065 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7066 }
7067 if (!(insn & (1 << 24))) {
b0109805
PB		 7068 gen_add_data_offset(s, insn, tmp2);
7069 store_reg(s, rn, tmp2);
7070 } else if (insn & (1 << 21)) {
7071 store_reg(s, rn, tmp2);
7072 } else {
7073 dead_tmp(tmp2);
9ee6e8bb
PB		 7074 }
7075 if (insn & (1 << 20)) {
7076 /* Complete the load. */
7077 if (rd == 15)
b0109805 7078 gen_bx(s, tmp);
9ee6e8bb 7079 else
b0109805 7080 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7081 }
7082 break;
7083 case 0x08:
7084 case 0x09:
7085 {
7086 int j, n, user, loaded_base;
b0109805 7087 TCGv loaded_var;
9ee6e8bb
PB		 7088 /* load/store multiple words */
7089 /* XXX: store correct base if write back */
7090 user = 0;
7091 if (insn & (1 << 22)) {
7092 if (IS_USER(s))
7093 goto illegal_op; /* only usable in supervisor mode */
7094
7095 if ((insn & (1 << 15)) == 0)
7096 user = 1;
7097 }
7098 rn = (insn >> 16) & 0xf;
b0109805 7099 addr = load_reg(s, rn);
9ee6e8bb
PB		 7100
7101 /* compute total size */
7102 loaded_base = 0;
a50f5b91 7103 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7104 n = 0;
7105 for(i=0;i<16;i++) {
7106 if (insn & (1 << i))
7107 n++;
7108 }
7109 /* XXX: test invalid n == 0 case ? */
7110 if (insn & (1 << 23)) {
7111 if (insn & (1 << 24)) {
7112 /* pre increment */
b0109805 7113 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7114 } else {
7115 /* post increment */
7116 }
7117 } else {
7118 if (insn & (1 << 24)) {
7119 /* pre decrement */
b0109805 7120 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7121 } else {
7122 /* post decrement */
7123 if (n != 1)
b0109805 7124 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7125 }
7126 }
7127 j = 0;
7128 for(i=0;i<16;i++) {
7129 if (insn & (1 << i)) {
7130 if (insn & (1 << 20)) {
7131 /* load */
b0109805 7132 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7133 if (i == 15) {
b0109805 7134 gen_bx(s, tmp);
9ee6e8bb 7135 } else if (user) {
b75263d6
JR		 7136 tmp2 = tcg_const_i32(i);
7137 gen_helper_set_user_reg(tmp2, tmp);
7138 tcg_temp_free_i32(tmp2);
b0109805 7139 dead_tmp(tmp);
9ee6e8bb 7140 } else if (i == rn) {
b0109805 7141 loaded_var = tmp;
9ee6e8bb
PB		 7142 loaded_base = 1;
7143 } else {
b0109805 7144 store_reg(s, i, tmp);
9ee6e8bb
PB		 7145 }
7146 } else {
7147 /* store */
7148 if (i == 15) {
7149 /* special case: r15 = PC + 8 */
7150 val = (long)s->pc + 4;
b0109805
PB		 7151 tmp = new_tmp();
7152 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7153 } else if (user) {
b0109805 7154 tmp = new_tmp();
b75263d6
JR		 7155 tmp2 = tcg_const_i32(i);
7156 gen_helper_get_user_reg(tmp, tmp2);
7157 tcg_temp_free_i32(tmp2);
9ee6e8bb 7158 } else {
b0109805 7159 tmp = load_reg(s, i);
9ee6e8bb 7160 }
b0109805 7161 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7162 }
7163 j++;
7164 /* no need to add after the last transfer */
7165 if (j != n)
b0109805 7166 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7167 }
7168 }
7169 if (insn & (1 << 21)) {
7170 /* write back */
7171 if (insn & (1 << 23)) {
7172 if (insn & (1 << 24)) {
7173 /* pre increment */
7174 } else {
7175 /* post increment */
b0109805 7176 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7177 }
7178 } else {
7179 if (insn & (1 << 24)) {
7180 /* pre decrement */
7181 if (n != 1)
b0109805 7182 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7183 } else {
7184 /* post decrement */
b0109805 7185 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7186 }
7187 }
b0109805
PB		 7188 store_reg(s, rn, addr);
7189 } else {
7190 dead_tmp(addr);
9ee6e8bb
PB		 7191 }
7192 if (loaded_base) {
b0109805 7193 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7194 }
7195 if ((insn & (1 << 22)) && !user) {
7196 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7197 tmp = load_cpu_field(spsr);
7198 gen_set_cpsr(tmp, 0xffffffff);
7199 dead_tmp(tmp);
9ee6e8bb
PB		 7200 s->is_jmp = DISAS_UPDATE;
7201 }
7202 }
7203 break;
7204 case 0xa:
7205 case 0xb:
7206 {
7207 int32_t offset;
7208
7209 /* branch (and link) */
7210 val = (int32_t)s->pc;
7211 if (insn & (1 << 24)) {
5e3f878a
PB		 7212 tmp = new_tmp();
7213 tcg_gen_movi_i32(tmp, val);
7214 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7215 }
7216 offset = (((int32_t)insn << 8) >> 8);
7217 val += (offset << 2) + 4;
7218 gen_jmp(s, val);
7219 }
7220 break;
7221 case 0xc:
7222 case 0xd:
7223 case 0xe:
7224 /* Coprocessor. */
7225 if (disas_coproc_insn(env, s, insn))
7226 goto illegal_op;
7227 break;
7228 case 0xf:
7229 /* swi */
5e3f878a 7230 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7231 s->is_jmp = DISAS_SWI;
7232 break;
7233 default:
7234 illegal_op:
7235 gen_set_condexec(s);
5e3f878a 7236 gen_set_pc_im(s->pc - 4);
d9ba4830 7237 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 7238 s->is_jmp = DISAS_JUMP;
7239 break;
7240 }
7241 }
7242}
7243
7244/* Return true if this is a Thumb-2 logical op. */
7245static int
7246thumb2_logic_op(int op)
7247{
7248 return (op < 8);
7249}
7250
7251/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7252 then set condition code flags based on the result of the operation.
7253 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7254 to the high bit of T1.
7255 Returns zero if the opcode is valid. */
7256
7257static int
396e467c 7258gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7259{
7260 int logic_cc;
7261
7262 logic_cc = 0;
7263 switch (op) {
7264 case 0: /* and */
396e467c 7265 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7266 logic_cc = conds;
7267 break;
7268 case 1: /* bic */
f669df27 7269 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7270 logic_cc = conds;
7271 break;
7272 case 2: /* orr */
396e467c 7273 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7274 logic_cc = conds;
7275 break;
7276 case 3: /* orn */
396e467c
FN		 7277 tcg_gen_not_i32(t1, t1);
7278 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7279 logic_cc = conds;
7280 break;
7281 case 4: /* eor */
396e467c 7282 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7283 logic_cc = conds;
7284 break;
7285 case 8: /* add */
7286 if (conds)
396e467c 7287 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7288 else
396e467c 7289 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7290 break;
7291 case 10: /* adc */
7292 if (conds)
396e467c 7293 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7294 else
396e467c 7295 gen_adc(t0, t1);
9ee6e8bb
PB		 7296 break;
7297 case 11: /* sbc */
7298 if (conds)
396e467c 7299 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7300 else
396e467c 7301 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7302 break;
7303 case 13: /* sub */
7304 if (conds)
396e467c 7305 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7306 else
396e467c 7307 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7308 break;
7309 case 14: /* rsb */
7310 if (conds)
396e467c 7311 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7312 else
396e467c 7313 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7314 break;
7315 default: /* 5, 6, 7, 9, 12, 15. */
7316 return 1;
7317 }
7318 if (logic_cc) {
396e467c 7319 gen_logic_CC(t0);
9ee6e8bb 7320 if (shifter_out)
396e467c 7321 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7322 }
7323 return 0;
7324}
7325
7326/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7327 is not legal. */
7328static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7329{
b0109805 7330 uint32_t insn, imm, shift, offset;
9ee6e8bb 7331 uint32_t rd, rn, rm, rs;
b26eefb6 7332 TCGv tmp;
6ddbc6e4
PB		 7333 TCGv tmp2;
7334 TCGv tmp3;
b0109805 7335 TCGv addr;
a7812ae4 7336 TCGv_i64 tmp64;
9ee6e8bb
PB		 7337 int op;
7338 int shiftop;
7339 int conds;
7340 int logic_cc;
7341
7342 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7343 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7344 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7345 16-bit instructions to get correct prefetch abort behavior. */
7346 insn = insn_hw1;
7347 if ((insn & (1 << 12)) == 0) {
7348 /* Second half of blx. */
7349 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7350 tmp = load_reg(s, 14);
7351 tcg_gen_addi_i32(tmp, tmp, offset);
7352 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7353
d9ba4830 7354 tmp2 = new_tmp();
b0109805 7355 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7356 store_reg(s, 14, tmp2);
7357 gen_bx(s, tmp);
9ee6e8bb
PB		 7358 return 0;
7359 }
7360 if (insn & (1 << 11)) {
7361 /* Second half of bl. */
7362 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7363 tmp = load_reg(s, 14);
6a0d8a1d 7364 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7365
d9ba4830 7366 tmp2 = new_tmp();
b0109805 7367 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7368 store_reg(s, 14, tmp2);
7369 gen_bx(s, tmp);
9ee6e8bb
PB		 7370 return 0;
7371 }
7372 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7373 /* Instruction spans a page boundary. Implement it as two
7374 16-bit instructions in case the second half causes an
7375 prefetch abort. */
7376 offset = ((int32_t)insn << 21) >> 9;
396e467c 7377 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7378 return 0;
7379 }
7380 /* Fall through to 32-bit decode. */
7381 }
7382
7383 insn = lduw_code(s->pc);
7384 s->pc += 2;
7385 insn |= (uint32_t)insn_hw1 << 16;
7386
7387 if ((insn & 0xf800e800) != 0xf000e800) {
7388 ARCH(6T2);
7389 }
7390
7391 rn = (insn >> 16) & 0xf;
7392 rs = (insn >> 12) & 0xf;
7393 rd = (insn >> 8) & 0xf;
7394 rm = insn & 0xf;
7395 switch ((insn >> 25) & 0xf) {
7396 case 0: case 1: case 2: case 3:
7397 /* 16-bit instructions. Should never happen. */
7398 abort();
7399 case 4:
7400 if (insn & (1 << 22)) {
7401 /* Other load/store, table branch. */
7402 if (insn & 0x01200000) {
7403 /* Load/store doubleword. */
7404 if (rn == 15) {
b0109805
PB		 7405 addr = new_tmp();
7406 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7407 } else {
b0109805 7408 addr = load_reg(s, rn);
9ee6e8bb
PB		 7409 }
7410 offset = (insn & 0xff) * 4;
7411 if ((insn & (1 << 23)) == 0)
7412 offset = -offset;
7413 if (insn & (1 << 24)) {
b0109805 7414 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7415 offset = 0;
7416 }
7417 if (insn & (1 << 20)) {
7418 /* ldrd */
b0109805
PB		 7419 tmp = gen_ld32(addr, IS_USER(s));
7420 store_reg(s, rs, tmp);
7421 tcg_gen_addi_i32(addr, addr, 4);
7422 tmp = gen_ld32(addr, IS_USER(s));
7423 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7424 } else {
7425 /* strd */
b0109805
PB		 7426 tmp = load_reg(s, rs);
7427 gen_st32(tmp, addr, IS_USER(s));
7428 tcg_gen_addi_i32(addr, addr, 4);
7429 tmp = load_reg(s, rd);
7430 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7431 }
7432 if (insn & (1 << 21)) {
7433 /* Base writeback. */
7434 if (rn == 15)
7435 goto illegal_op;
b0109805
PB		 7436 tcg_gen_addi_i32(addr, addr, offset - 4);
7437 store_reg(s, rn, addr);
7438 } else {
7439 dead_tmp(addr);
9ee6e8bb
PB		 7440 }
7441 } else if ((insn & (1 << 23)) == 0) {
7442 /* Load/store exclusive word. */
3174f8e9 7443 addr = tcg_temp_local_new();
98a46317 7444 load_reg_var(s, addr, rn);
426f5abc 7445 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7446 if (insn & (1 << 20)) {
426f5abc 7447 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7448 } else {
426f5abc 7449 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7450 }
3174f8e9 7451 tcg_temp_free(addr);
9ee6e8bb
PB		 7452 } else if ((insn & (1 << 6)) == 0) {
7453 /* Table Branch. */
7454 if (rn == 15) {
b0109805
PB		 7455 addr = new_tmp();
7456 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7457 } else {
b0109805 7458 addr = load_reg(s, rn);
9ee6e8bb 7459 }
b26eefb6 7460 tmp = load_reg(s, rm);
b0109805 7461 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7462 if (insn & (1 << 4)) {
7463 /* tbh */
b0109805 7464 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7465 dead_tmp(tmp);
b0109805 7466 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7467 } else { /* tbb */
b26eefb6 7468 dead_tmp(tmp);
b0109805 7469 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7470 }
b0109805
PB		 7471 dead_tmp(addr);
7472 tcg_gen_shli_i32(tmp, tmp, 1);
7473 tcg_gen_addi_i32(tmp, tmp, s->pc);
7474 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7475 } else {
7476 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7477 ARCH(7);
9ee6e8bb 7478 op = (insn >> 4) & 0x3;
426f5abc
PB		 7479 if (op == 2) {
7480 goto illegal_op;
7481 }
3174f8e9 7482 addr = tcg_temp_local_new();
98a46317 7483 load_reg_var(s, addr, rn);
9ee6e8bb 7484 if (insn & (1 << 20)) {
426f5abc 7485 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7486 } else {
426f5abc 7487 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7488 }
3174f8e9 7489 tcg_temp_free(addr);
9ee6e8bb
PB		 7490 }
7491 } else {
7492 /* Load/store multiple, RFE, SRS. */
7493 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7494 /* Not available in user mode. */
b0109805 7495 if (IS_USER(s))
9ee6e8bb
PB		 7496 goto illegal_op;
7497 if (insn & (1 << 20)) {
7498 /* rfe */
b0109805
PB		 7499 addr = load_reg(s, rn);
7500 if ((insn & (1 << 24)) == 0)
7501 tcg_gen_addi_i32(addr, addr, -8);
7502 /* Load PC into tmp and CPSR into tmp2. */
7503 tmp = gen_ld32(addr, 0);
7504 tcg_gen_addi_i32(addr, addr, 4);
7505 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7506 if (insn & (1 << 21)) {
7507 /* Base writeback. */
b0109805
PB		 7508 if (insn & (1 << 24)) {
7509 tcg_gen_addi_i32(addr, addr, 4);
7510 } else {
7511 tcg_gen_addi_i32(addr, addr, -4);
7512 }
7513 store_reg(s, rn, addr);
7514 } else {
7515 dead_tmp(addr);
9ee6e8bb 7516 }
b0109805 7517 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7518 } else {
7519 /* srs */
7520 op = (insn & 0x1f);
7521 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7522 addr = load_reg(s, 13);
9ee6e8bb 7523 } else {
b0109805 7524 addr = new_tmp();
b75263d6
JR		 7525 tmp = tcg_const_i32(op);
7526 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7527 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 7528 }
7529 if ((insn & (1 << 24)) == 0) {
b0109805 7530 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7531 }
b0109805
PB		 7532 tmp = load_reg(s, 14);
7533 gen_st32(tmp, addr, 0);
7534 tcg_gen_addi_i32(addr, addr, 4);
7535 tmp = new_tmp();
7536 gen_helper_cpsr_read(tmp);
7537 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7538 if (insn & (1 << 21)) {
7539 if ((insn & (1 << 24)) == 0) {
b0109805 7540 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7541 } else {
b0109805 7542 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7543 }
7544 if (op == (env->uncached_cpsr & CPSR_M)) {
b0109805 7545 store_reg(s, 13, addr);
9ee6e8bb 7546 } else {
b75263d6
JR		 7547 tmp = tcg_const_i32(op);
7548 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7549 tcg_temp_free_i32(tmp);
9ee6e8bb 7550 }
b0109805
PB		 7551 } else {
7552 dead_tmp(addr);
9ee6e8bb
PB		 7553 }
7554 }
7555 } else {
7556 int i;
7557 /* Load/store multiple. */
b0109805 7558 addr = load_reg(s, rn);
9ee6e8bb
PB		 7559 offset = 0;
7560 for (i = 0; i < 16; i++) {
7561 if (insn & (1 << i))
7562 offset += 4;
7563 }
7564 if (insn & (1 << 24)) {
b0109805 7565 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7566 }
7567
7568 for (i = 0; i < 16; i++) {
7569 if ((insn & (1 << i)) == 0)
7570 continue;
7571 if (insn & (1 << 20)) {
7572 /* Load. */
b0109805 7573 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7574 if (i == 15) {
b0109805 7575 gen_bx(s, tmp);
9ee6e8bb 7576 } else {
b0109805 7577 store_reg(s, i, tmp);
9ee6e8bb
PB		 7578 }
7579 } else {
7580 /* Store. */
b0109805
PB		 7581 tmp = load_reg(s, i);
7582 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7583 }
b0109805 7584 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7585 }
7586 if (insn & (1 << 21)) {
7587 /* Base register writeback. */
7588 if (insn & (1 << 24)) {
b0109805 7589 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7590 }
7591 /* Fault if writeback register is in register list. */
7592 if (insn & (1 << rn))
7593 goto illegal_op;
b0109805
PB		 7594 store_reg(s, rn, addr);
7595 } else {
7596 dead_tmp(addr);
9ee6e8bb
PB		 7597 }
7598 }
7599 }
7600 break;
7601 case 5: /* Data processing register constant shift. */
3174f8e9
FN		 7602 if (rn == 15) {
7603 tmp = new_tmp();
7604 tcg_gen_movi_i32(tmp, 0);
7605 } else {
7606 tmp = load_reg(s, rn);
7607 }
7608 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7609 op = (insn >> 21) & 0xf;
7610 shiftop = (insn >> 4) & 3;
7611 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7612 conds = (insn & (1 << 20)) != 0;
7613 logic_cc = (conds && thumb2_logic_op(op));
3174f8e9
FN		 7614 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7615 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
9ee6e8bb 7616 goto illegal_op;
3174f8e9
FN		 7617 dead_tmp(tmp2);
7618 if (rd != 15) {
7619 store_reg(s, rd, tmp);
7620 } else {
7621 dead_tmp(tmp);
7622 }
9ee6e8bb
PB		 7623 break;
7624 case 13: /* Misc data processing. */
7625 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7626 if (op < 4 && (insn & 0xf000) != 0xf000)
7627 goto illegal_op;
7628 switch (op) {
7629 case 0: /* Register controlled shift. */
8984bd2e
PB		 7630 tmp = load_reg(s, rn);
7631 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7632 if ((insn & 0x70) != 0)
7633 goto illegal_op;
7634 op = (insn >> 21) & 3;
8984bd2e
PB		 7635 logic_cc = (insn & (1 << 20)) != 0;
7636 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7637 if (logic_cc)
7638 gen_logic_CC(tmp);
21aeb343 7639 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7640 break;
7641 case 1: /* Sign/zero extend. */
5e3f878a 7642 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7643 shift = (insn >> 4) & 3;
7644 /* ??? In many cases it's not neccessary to do a
7645 rotate, a shift is sufficient. */
7646 if (shift != 0)
f669df27 7647 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7648 op = (insn >> 20) & 7;
7649 switch (op) {
5e3f878a
PB		 7650 case 0: gen_sxth(tmp); break;
7651 case 1: gen_uxth(tmp); break;
7652 case 2: gen_sxtb16(tmp); break;
7653 case 3: gen_uxtb16(tmp); break;
7654 case 4: gen_sxtb(tmp); break;
7655 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7656 default: goto illegal_op;
7657 }
7658 if (rn != 15) {
5e3f878a 7659 tmp2 = load_reg(s, rn);
9ee6e8bb 7660 if ((op >> 1) == 1) {
5e3f878a 7661 gen_add16(tmp, tmp2);
9ee6e8bb 7662 } else {
5e3f878a
PB		 7663 tcg_gen_add_i32(tmp, tmp, tmp2);
7664 dead_tmp(tmp2);
9ee6e8bb
PB		 7665 }
7666 }
5e3f878a 7667 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7668 break;
7669 case 2: /* SIMD add/subtract. */
7670 op = (insn >> 20) & 7;
7671 shift = (insn >> 4) & 7;
7672 if ((op & 3) == 3 || (shift & 3) == 3)
7673 goto illegal_op;
6ddbc6e4
PB		 7674 tmp = load_reg(s, rn);
7675 tmp2 = load_reg(s, rm);
7676 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7677 dead_tmp(tmp2);
7678 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7679 break;
7680 case 3: /* Other data processing. */
7681 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7682 if (op < 4) {
7683 /* Saturating add/subtract. */
d9ba4830
PB		 7684 tmp = load_reg(s, rn);
7685 tmp2 = load_reg(s, rm);
9ee6e8bb 7686 if (op & 2)
d9ba4830 7687 gen_helper_double_saturate(tmp, tmp);
9ee6e8bb 7688 if (op & 1)
d9ba4830 7689 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7690 else
d9ba4830
PB		 7691 gen_helper_add_saturate(tmp, tmp, tmp2);
7692 dead_tmp(tmp2);
9ee6e8bb 7693 } else {
d9ba4830 7694 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7695 switch (op) {
7696 case 0x0a: /* rbit */
d9ba4830 7697 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7698 break;
7699 case 0x08: /* rev */
66896cb8 7700 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7701 break;
7702 case 0x09: /* rev16 */
d9ba4830 7703 gen_rev16(tmp);
9ee6e8bb
PB		 7704 break;
7705 case 0x0b: /* revsh */
d9ba4830 7706 gen_revsh(tmp);
9ee6e8bb
PB		 7707 break;
7708 case 0x10: /* sel */
d9ba4830 7709 tmp2 = load_reg(s, rm);
6ddbc6e4
PB		 7710 tmp3 = new_tmp();
7711 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7712 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6ddbc6e4 7713 dead_tmp(tmp3);
d9ba4830 7714 dead_tmp(tmp2);
9ee6e8bb
PB		 7715 break;
7716 case 0x18: /* clz */
d9ba4830 7717 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7718 break;
7719 default:
7720 goto illegal_op;
7721 }
7722 }
d9ba4830 7723 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7724 break;
7725 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7726 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7727 tmp = load_reg(s, rn);
7728 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7729 switch ((insn >> 20) & 7) {
7730 case 0: /* 32 x 32 -> 32 */
d9ba4830
PB		 7731 tcg_gen_mul_i32(tmp, tmp, tmp2);
7732 dead_tmp(tmp2);
9ee6e8bb 7733 if (rs != 15) {
d9ba4830 7734 tmp2 = load_reg(s, rs);
9ee6e8bb 7735 if (op)
d9ba4830 7736 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7737 else
d9ba4830
PB		 7738 tcg_gen_add_i32(tmp, tmp, tmp2);
7739 dead_tmp(tmp2);
9ee6e8bb 7740 }
9ee6e8bb
PB		 7741 break;
7742 case 1: /* 16 x 16 -> 32 */
d9ba4830
PB		 7743 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7744 dead_tmp(tmp2);
9ee6e8bb 7745 if (rs != 15) {
d9ba4830
PB		 7746 tmp2 = load_reg(s, rs);
7747 gen_helper_add_setq(tmp, tmp, tmp2);
7748 dead_tmp(tmp2);
9ee6e8bb 7749 }
9ee6e8bb
PB		 7750 break;
7751 case 2: /* Dual multiply add. */
7752 case 4: /* Dual multiply subtract. */
7753 if (op)
d9ba4830
PB		 7754 gen_swap_half(tmp2);
7755 gen_smul_dual(tmp, tmp2);
9ee6e8bb
PB		 7756 /* This addition cannot overflow. */
7757 if (insn & (1 << 22)) {
d9ba4830 7758 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7759 } else {
d9ba4830 7760 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 7761 }
d9ba4830 7762 dead_tmp(tmp2);
9ee6e8bb
PB		 7763 if (rs != 15)
7764 {
d9ba4830
PB		 7765 tmp2 = load_reg(s, rs);
7766 gen_helper_add_setq(tmp, tmp, tmp2);
7767 dead_tmp(tmp2);
9ee6e8bb 7768 }
9ee6e8bb
PB		 7769 break;
7770 case 3: /* 32 * 16 -> 32msb */
7771 if (op)
d9ba4830 7772 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7773 else
d9ba4830 7774 gen_sxth(tmp2);
a7812ae4
PB		 7775 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7776 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 7777 tmp = new_tmp();
a7812ae4 7778 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 7779 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7780 if (rs != 15)
7781 {
d9ba4830
PB		 7782 tmp2 = load_reg(s, rs);
7783 gen_helper_add_setq(tmp, tmp, tmp2);
7784 dead_tmp(tmp2);
9ee6e8bb 7785 }
9ee6e8bb
PB		 7786 break;
7787 case 5: case 6: /* 32 * 32 -> 32msb */
d9ba4830
PB		 7788 gen_imull(tmp, tmp2);
7789 if (insn & (1 << 5)) {
7790 gen_roundqd(tmp, tmp2);
7791 dead_tmp(tmp2);
7792 } else {
7793 dead_tmp(tmp);
7794 tmp = tmp2;
7795 }
9ee6e8bb 7796 if (rs != 15) {
d9ba4830 7797 tmp2 = load_reg(s, rs);
9ee6e8bb 7798 if (insn & (1 << 21)) {
d9ba4830 7799 tcg_gen_add_i32(tmp, tmp, tmp2);
99c475ab 7800 } else {
d9ba4830 7801 tcg_gen_sub_i32(tmp, tmp2, tmp);
99c475ab 7802 }
d9ba4830 7803 dead_tmp(tmp2);
2c0262af 7804 }
9ee6e8bb
PB		 7805 break;
7806 case 7: /* Unsigned sum of absolute differences. */
d9ba4830
PB		 7807 gen_helper_usad8(tmp, tmp, tmp2);
7808 dead_tmp(tmp2);
9ee6e8bb 7809 if (rs != 15) {
d9ba4830
PB		 7810 tmp2 = load_reg(s, rs);
7811 tcg_gen_add_i32(tmp, tmp, tmp2);
7812 dead_tmp(tmp2);
5fd46862 7813 }
9ee6e8bb 7814 break;
2c0262af 7815 }
d9ba4830 7816 store_reg(s, rd, tmp);
2c0262af 7817 break;
9ee6e8bb
PB		 7818 case 6: case 7: /* 64-bit multiply, Divide. */
7819 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7820 tmp = load_reg(s, rn);
7821 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7822 if ((op & 0x50) == 0x10) {
7823 /* sdiv, udiv */
7824 if (!arm_feature(env, ARM_FEATURE_DIV))
7825 goto illegal_op;
7826 if (op & 0x20)
5e3f878a 7827 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7828 else
5e3f878a
PB		 7829 gen_helper_sdiv(tmp, tmp, tmp2);
7830 dead_tmp(tmp2);
7831 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7832 } else if ((op & 0xe) == 0xc) {
7833 /* Dual multiply accumulate long. */
7834 if (op & 1)
5e3f878a
PB		 7835 gen_swap_half(tmp2);
7836 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7837 if (op & 0x10) {
5e3f878a 7838 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7839 } else {
5e3f878a 7840 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7841 }
5e3f878a 7842 dead_tmp(tmp2);
a7812ae4
PB		 7843 /* BUGFIX */
7844 tmp64 = tcg_temp_new_i64();
7845 tcg_gen_ext_i32_i64(tmp64, tmp);
7846 dead_tmp(tmp);
7847 gen_addq(s, tmp64, rs, rd);
7848 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7849 tcg_temp_free_i64(tmp64);
2c0262af 7850 } else {
9ee6e8bb
PB		 7851 if (op & 0x20) {
7852 /* Unsigned 64-bit multiply */
a7812ae4 7853 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7854 } else {
9ee6e8bb
PB		 7855 if (op & 8) {
7856 /* smlalxy */
5e3f878a
PB		 7857 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7858 dead_tmp(tmp2);
a7812ae4
PB		 7859 tmp64 = tcg_temp_new_i64();
7860 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7861 dead_tmp(tmp);
9ee6e8bb
PB		 7862 } else {
7863 /* Signed 64-bit multiply */
a7812ae4 7864 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7865 }
b5ff1b31 7866 }
9ee6e8bb
PB		 7867 if (op & 4) {
7868 /* umaal */
a7812ae4
PB		 7869 gen_addq_lo(s, tmp64, rs);
7870 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 7871 } else if (op & 0x40) {
7872 /* 64-bit accumulate. */
a7812ae4 7873 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 7874 }
a7812ae4 7875 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7876 tcg_temp_free_i64(tmp64);
5fd46862 7877 }
2c0262af 7878 break;
9ee6e8bb
PB		 7879 }
7880 break;
7881 case 6: case 7: case 14: case 15:
7882 /* Coprocessor. */
7883 if (((insn >> 24) & 3) == 3) {
7884 /* Translate into the equivalent ARM encoding. */
7885 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7886 if (disas_neon_data_insn(env, s, insn))
7887 goto illegal_op;
7888 } else {
7889 if (insn & (1 << 28))
7890 goto illegal_op;
7891 if (disas_coproc_insn (env, s, insn))
7892 goto illegal_op;
7893 }
7894 break;
7895 case 8: case 9: case 10: case 11:
7896 if (insn & (1 << 15)) {
7897 /* Branches, misc control. */
7898 if (insn & 0x5000) {
7899 /* Unconditional branch. */
7900 /* signextend(hw1[10:0]) -> offset[:12]. */
7901 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7902 /* hw1[10:0] -> offset[11:1]. */
7903 offset |= (insn & 0x7ff) << 1;
7904 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7905 offset[24:22] already have the same value because of the
7906 sign extension above. */
7907 offset ^= ((~insn) & (1 << 13)) << 10;
7908 offset ^= ((~insn) & (1 << 11)) << 11;
7909
9ee6e8bb
PB		 7910 if (insn & (1 << 14)) {
7911 /* Branch and link. */
3174f8e9 7912 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 7913 }
3b46e624 7914
b0109805 7915 offset += s->pc;
9ee6e8bb
PB		 7916 if (insn & (1 << 12)) {
7917 /* b/bl */
b0109805 7918 gen_jmp(s, offset);
9ee6e8bb
PB		 7919 } else {
7920 /* blx */
b0109805
PB		 7921 offset &= ~(uint32_t)2;
7922 gen_bx_im(s, offset);
2c0262af 7923 }
9ee6e8bb
PB		 7924 } else if (((insn >> 23) & 7) == 7) {
7925 /* Misc control */
7926 if (insn & (1 << 13))
7927 goto illegal_op;
7928
7929 if (insn & (1 << 26)) {
7930 /* Secure monitor call (v6Z) */
7931 goto illegal_op; /* not implemented. */
2c0262af 7932 } else {
9ee6e8bb
PB		 7933 op = (insn >> 20) & 7;
7934 switch (op) {
7935 case 0: /* msr cpsr. */
7936 if (IS_M(env)) {
8984bd2e
PB		 7937 tmp = load_reg(s, rn);
7938 addr = tcg_const_i32(insn & 0xff);
7939 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6
JR		 7940 tcg_temp_free_i32(addr);
7941 dead_tmp(tmp);
9ee6e8bb
PB		 7942 gen_lookup_tb(s);
7943 break;
7944 }
7945 /* fall through */
7946 case 1: /* msr spsr. */
7947 if (IS_M(env))
7948 goto illegal_op;
2fbac54b
FN		 7949 tmp = load_reg(s, rn);
7950 if (gen_set_psr(s,
9ee6e8bb 7951 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 7952 op == 1, tmp))
9ee6e8bb
PB		 7953 goto illegal_op;
7954 break;
7955 case 2: /* cps, nop-hint. */
7956 if (((insn >> 8) & 7) == 0) {
7957 gen_nop_hint(s, insn & 0xff);
7958 }
7959 /* Implemented as NOP in user mode. */
7960 if (IS_USER(s))
7961 break;
7962 offset = 0;
7963 imm = 0;
7964 if (insn & (1 << 10)) {
7965 if (insn & (1 << 7))
7966 offset |= CPSR_A;
7967 if (insn & (1 << 6))
7968 offset |= CPSR_I;
7969 if (insn & (1 << 5))
7970 offset |= CPSR_F;
7971 if (insn & (1 << 9))
7972 imm = CPSR_A | CPSR_I | CPSR_F;
7973 }
7974 if (insn & (1 << 8)) {
7975 offset |= 0x1f;
7976 imm |= (insn & 0x1f);
7977 }
7978 if (offset) {
2fbac54b 7979 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 7980 }
7981 break;
7982 case 3: /* Special control operations. */
426f5abc 7983 ARCH(7);
9ee6e8bb
PB		 7984 op = (insn >> 4) & 0xf;
7985 switch (op) {
7986 case 2: /* clrex */
426f5abc 7987 gen_clrex(s);
9ee6e8bb
PB		 7988 break;
7989 case 4: /* dsb */
7990 case 5: /* dmb */
7991 case 6: /* isb */
7992 /* These execute as NOPs. */
9ee6e8bb
PB		 7993 break;
7994 default:
7995 goto illegal_op;
7996 }
7997 break;
7998 case 4: /* bxj */
7999 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8000 tmp = load_reg(s, rn);
8001 gen_bx(s, tmp);
9ee6e8bb
PB		 8002 break;
8003 case 5: /* Exception return. */
b8b45b68
RV		 8004 if (IS_USER(s)) {
8005 goto illegal_op;
8006 }
8007 if (rn != 14 || rd != 15) {
8008 goto illegal_op;
8009 }
8010 tmp = load_reg(s, rn);
8011 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8012 gen_exception_return(s, tmp);
8013 break;
9ee6e8bb 8014 case 6: /* mrs cpsr. */
8984bd2e 8015 tmp = new_tmp();
9ee6e8bb 8016 if (IS_M(env)) {
8984bd2e
PB		 8017 addr = tcg_const_i32(insn & 0xff);
8018 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8019 tcg_temp_free_i32(addr);
9ee6e8bb 8020 } else {
8984bd2e 8021 gen_helper_cpsr_read(tmp);
9ee6e8bb 8022 }
8984bd2e 8023 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8024 break;
8025 case 7: /* mrs spsr. */
8026 /* Not accessible in user mode. */
8027 if (IS_USER(s) || IS_M(env))
8028 goto illegal_op;
d9ba4830
PB		 8029 tmp = load_cpu_field(spsr);
8030 store_reg(s, rd, tmp);
9ee6e8bb 8031 break;
2c0262af
FB		 8032 }
8033 }
9ee6e8bb
PB		 8034 } else {
8035 /* Conditional branch. */
8036 op = (insn >> 22) & 0xf;
8037 /* Generate a conditional jump to next instruction. */
8038 s->condlabel = gen_new_label();
d9ba4830 8039 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8040 s->condjmp = 1;
8041
8042 /* offset[11:1] = insn[10:0] */
8043 offset = (insn & 0x7ff) << 1;
8044 /* offset[17:12] = insn[21:16]. */
8045 offset |= (insn & 0x003f0000) >> 4;
8046 /* offset[31:20] = insn[26]. */
8047 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8048 /* offset[18] = insn[13]. */
8049 offset |= (insn & (1 << 13)) << 5;
8050 /* offset[19] = insn[11]. */
8051 offset |= (insn & (1 << 11)) << 8;
8052
8053 /* jump to the offset */
b0109805 8054 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8055 }
8056 } else {
8057 /* Data processing immediate. */
8058 if (insn & (1 << 25)) {
8059 if (insn & (1 << 24)) {
8060 if (insn & (1 << 20))
8061 goto illegal_op;
8062 /* Bitfield/Saturate. */
8063 op = (insn >> 21) & 7;
8064 imm = insn & 0x1f;
8065 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4
PB		 8066 if (rn == 15) {
8067 tmp = new_tmp();
8068 tcg_gen_movi_i32(tmp, 0);
8069 } else {
8070 tmp = load_reg(s, rn);
8071 }
9ee6e8bb
PB		 8072 switch (op) {
8073 case 2: /* Signed bitfield extract. */
8074 imm++;
8075 if (shift + imm > 32)
8076 goto illegal_op;
8077 if (imm < 32)
6ddbc6e4 8078 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8079 break;
8080 case 6: /* Unsigned bitfield extract. */
8081 imm++;
8082 if (shift + imm > 32)
8083 goto illegal_op;
8084 if (imm < 32)
6ddbc6e4 8085 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8086 break;
8087 case 3: /* Bitfield insert/clear. */
8088 if (imm < shift)
8089 goto illegal_op;
8090 imm = imm + 1 - shift;
8091 if (imm != 32) {
6ddbc6e4 8092 tmp2 = load_reg(s, rd);
8f8e3aa4 8093 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
6ddbc6e4 8094 dead_tmp(tmp2);
9ee6e8bb
PB		 8095 }
8096 break;
8097 case 7:
8098 goto illegal_op;
8099 default: /* Saturate. */
9ee6e8bb
PB		 8100 if (shift) {
8101 if (op & 1)
6ddbc6e4 8102 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8103 else
6ddbc6e4 8104 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8105 }
6ddbc6e4 8106 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8107 if (op & 4) {
8108 /* Unsigned. */
9ee6e8bb 8109 if ((op & 1) && shift == 0)
6ddbc6e4 8110 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8111 else
6ddbc6e4 8112 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8113 } else {
9ee6e8bb 8114 /* Signed. */
9ee6e8bb 8115 if ((op & 1) && shift == 0)
6ddbc6e4 8116 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8117 else
6ddbc6e4 8118 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8119 }
b75263d6 8120 tcg_temp_free_i32(tmp2);
9ee6e8bb 8121 break;
2c0262af 8122 }
6ddbc6e4 8123 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8124 } else {
8125 imm = ((insn & 0x04000000) >> 15)
8126 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8127 if (insn & (1 << 22)) {
8128 /* 16-bit immediate. */
8129 imm |= (insn >> 4) & 0xf000;
8130 if (insn & (1 << 23)) {
8131 /* movt */
5e3f878a 8132 tmp = load_reg(s, rd);
86831435 8133 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8134 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8135 } else {
9ee6e8bb 8136 /* movw */
5e3f878a
PB		 8137 tmp = new_tmp();
8138 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8139 }
8140 } else {
9ee6e8bb
PB		 8141 /* Add/sub 12-bit immediate. */
8142 if (rn == 15) {
b0109805 8143 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8144 if (insn & (1 << 23))
b0109805 8145 offset -= imm;
9ee6e8bb 8146 else
b0109805 8147 offset += imm;
5e3f878a
PB		 8148 tmp = new_tmp();
8149 tcg_gen_movi_i32(tmp, offset);
2c0262af 8150 } else {
5e3f878a 8151 tmp = load_reg(s, rn);
9ee6e8bb 8152 if (insn & (1 << 23))
5e3f878a 8153 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8154 else
5e3f878a 8155 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8156 }
9ee6e8bb 8157 }
5e3f878a 8158 store_reg(s, rd, tmp);
191abaa2 8159 }
9ee6e8bb
PB		 8160 } else {
8161 int shifter_out = 0;
8162 /* modified 12-bit immediate. */
8163 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8164 imm = (insn & 0xff);
8165 switch (shift) {
8166 case 0: /* XY */
8167 /* Nothing to do. */
8168 break;
8169 case 1: /* 00XY00XY */
8170 imm |= imm << 16;
8171 break;
8172 case 2: /* XY00XY00 */
8173 imm |= imm << 16;
8174 imm <<= 8;
8175 break;
8176 case 3: /* XYXYXYXY */
8177 imm |= imm << 16;
8178 imm |= imm << 8;
8179 break;
8180 default: /* Rotated constant. */
8181 shift = (shift << 1) | (imm >> 7);
8182 imm |= 0x80;
8183 imm = imm << (32 - shift);
8184 shifter_out = 1;
8185 break;
b5ff1b31 8186 }
3174f8e9
FN		 8187 tmp2 = new_tmp();
8188 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8189 rn = (insn >> 16) & 0xf;
3174f8e9
FN		 8190 if (rn == 15) {
8191 tmp = new_tmp();
8192 tcg_gen_movi_i32(tmp, 0);
8193 } else {
8194 tmp = load_reg(s, rn);
8195 }
9ee6e8bb
PB		 8196 op = (insn >> 21) & 0xf;
8197 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8198 shifter_out, tmp, tmp2))
9ee6e8bb 8199 goto illegal_op;
3174f8e9 8200 dead_tmp(tmp2);
9ee6e8bb
PB		 8201 rd = (insn >> 8) & 0xf;
8202 if (rd != 15) {
3174f8e9
FN		 8203 store_reg(s, rd, tmp);
8204 } else {
8205 dead_tmp(tmp);
2c0262af 8206 }
2c0262af 8207 }
9ee6e8bb
PB		 8208 }
8209 break;
8210 case 12: /* Load/store single data item. */
8211 {
8212 int postinc = 0;
8213 int writeback = 0;
b0109805 8214 int user;
9ee6e8bb
PB		 8215 if ((insn & 0x01100000) == 0x01000000) {
8216 if (disas_neon_ls_insn(env, s, insn))
c1713132 8217 goto illegal_op;
9ee6e8bb
PB		 8218 break;
8219 }
b0109805 8220 user = IS_USER(s);
9ee6e8bb 8221 if (rn == 15) {
b0109805 8222 addr = new_tmp();
9ee6e8bb
PB		 8223 /* PC relative. */
8224 /* s->pc has already been incremented by 4. */
8225 imm = s->pc & 0xfffffffc;
8226 if (insn & (1 << 23))
8227 imm += insn & 0xfff;
8228 else
8229 imm -= insn & 0xfff;
b0109805 8230 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8231 } else {
b0109805 8232 addr = load_reg(s, rn);
9ee6e8bb
PB		 8233 if (insn & (1 << 23)) {
8234 /* Positive offset. */
8235 imm = insn & 0xfff;
b0109805 8236 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8237 } else {
8238 op = (insn >> 8) & 7;
8239 imm = insn & 0xff;
8240 switch (op) {
8241 case 0: case 8: /* Shifted Register. */
8242 shift = (insn >> 4) & 0xf;
8243 if (shift > 3)
18c9b560 8244 goto illegal_op;
b26eefb6 8245 tmp = load_reg(s, rm);
9ee6e8bb 8246 if (shift)
b26eefb6 8247 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8248 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8249 dead_tmp(tmp);
9ee6e8bb
PB		 8250 break;
8251 case 4: /* Negative offset. */
b0109805 8252 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb
PB		 8253 break;
8254 case 6: /* User privilege. */
b0109805
PB		 8255 tcg_gen_addi_i32(addr, addr, imm);
8256 user = 1;
9ee6e8bb
PB		 8257 break;
8258 case 1: /* Post-decrement. */
8259 imm = -imm;
8260 /* Fall through. */
8261 case 3: /* Post-increment. */
9ee6e8bb
PB		 8262 postinc = 1;
8263 writeback = 1;
8264 break;
8265 case 5: /* Pre-decrement. */
8266 imm = -imm;
8267 /* Fall through. */
8268 case 7: /* Pre-increment. */
b0109805 8269 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8270 writeback = 1;
8271 break;
8272 default:
b7bcbe95 8273 goto illegal_op;
9ee6e8bb
PB		 8274 }
8275 }
8276 }
8277 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8278 if (insn & (1 << 20)) {
8279 /* Load. */
8280 if (rs == 15 && op != 2) {
8281 if (op & 2)
b5ff1b31 8282 goto illegal_op;
9ee6e8bb
PB		 8283 /* Memory hint. Implemented as NOP. */
8284 } else {
8285 switch (op) {
b0109805
PB		 8286 case 0: tmp = gen_ld8u(addr, user); break;
8287 case 4: tmp = gen_ld8s(addr, user); break;
8288 case 1: tmp = gen_ld16u(addr, user); break;
8289 case 5: tmp = gen_ld16s(addr, user); break;
8290 case 2: tmp = gen_ld32(addr, user); break;
9ee6e8bb
PB		 8291 default: goto illegal_op;
8292 }
8293 if (rs == 15) {
b0109805 8294 gen_bx(s, tmp);
9ee6e8bb 8295 } else {
b0109805 8296 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8297 }
8298 }
8299 } else {
8300 /* Store. */
8301 if (rs == 15)
b7bcbe95 8302 goto illegal_op;
b0109805 8303 tmp = load_reg(s, rs);
9ee6e8bb 8304 switch (op) {
b0109805
PB		 8305 case 0: gen_st8(tmp, addr, user); break;
8306 case 1: gen_st16(tmp, addr, user); break;
8307 case 2: gen_st32(tmp, addr, user); break;
9ee6e8bb 8308 default: goto illegal_op;
b7bcbe95 8309 }
2c0262af 8310 }
9ee6e8bb 8311 if (postinc)
b0109805
PB		 8312 tcg_gen_addi_i32(addr, addr, imm);
8313 if (writeback) {
8314 store_reg(s, rn, addr);
8315 } else {
8316 dead_tmp(addr);
8317 }
9ee6e8bb
PB		 8318 }
8319 break;
8320 default:
8321 goto illegal_op;
2c0262af 8322 }
9ee6e8bb
PB		 8323 return 0;
8324illegal_op:
8325 return 1;
2c0262af
FB		 8326}
8327
9ee6e8bb 8328static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8329{
8330 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8331 int32_t offset;
8332 int i;
b26eefb6 8333 TCGv tmp;
d9ba4830 8334 TCGv tmp2;
b0109805 8335 TCGv addr;
99c475ab 8336
9ee6e8bb
PB		 8337 if (s->condexec_mask) {
8338 cond = s->condexec_cond;
8339 s->condlabel = gen_new_label();
d9ba4830 8340 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 8341 s->condjmp = 1;
8342 }
8343
b5ff1b31 8344 insn = lduw_code(s->pc);
99c475ab 8345 s->pc += 2;
b5ff1b31 8346
99c475ab
FB		 8347 switch (insn >> 12) {
8348 case 0: case 1:
396e467c 8349
99c475ab
FB		 8350 rd = insn & 7;
8351 op = (insn >> 11) & 3;
8352 if (op == 3) {
8353 /* add/subtract */
8354 rn = (insn >> 3) & 7;
396e467c 8355 tmp = load_reg(s, rn);
99c475ab
FB		 8356 if (insn & (1 << 10)) {
8357 /* immediate */
396e467c
FN		 8358 tmp2 = new_tmp();
8359 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8360 } else {
8361 /* reg */
8362 rm = (insn >> 6) & 7;
396e467c 8363 tmp2 = load_reg(s, rm);
99c475ab 8364 }
9ee6e8bb
PB		 8365 if (insn & (1 << 9)) {
8366 if (s->condexec_mask)
396e467c 8367 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8368 else
396e467c 8369 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8370 } else {
8371 if (s->condexec_mask)
396e467c 8372 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8373 else
396e467c 8374 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8375 }
396e467c
FN		 8376 dead_tmp(tmp2);
8377 store_reg(s, rd, tmp);
99c475ab
FB		 8378 } else {
8379 /* shift immediate */
8380 rm = (insn >> 3) & 7;
8381 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8382 tmp = load_reg(s, rm);
8383 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8384 if (!s->condexec_mask)
8385 gen_logic_CC(tmp);
8386 store_reg(s, rd, tmp);
99c475ab
FB		 8387 }
8388 break;
8389 case 2: case 3:
8390 /* arithmetic large immediate */
8391 op = (insn >> 11) & 3;
8392 rd = (insn >> 8) & 0x7;
396e467c
FN		 8393 if (op == 0) { /* mov */
8394 tmp = new_tmp();
8395 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8396 if (!s->condexec_mask)
396e467c
FN		 8397 gen_logic_CC(tmp);
8398 store_reg(s, rd, tmp);
8399 } else {
8400 tmp = load_reg(s, rd);
8401 tmp2 = new_tmp();
8402 tcg_gen_movi_i32(tmp2, insn & 0xff);
8403 switch (op) {
8404 case 1: /* cmp */
8405 gen_helper_sub_cc(tmp, tmp, tmp2);
8406 dead_tmp(tmp);
8407 dead_tmp(tmp2);
8408 break;
8409 case 2: /* add */
8410 if (s->condexec_mask)
8411 tcg_gen_add_i32(tmp, tmp, tmp2);
8412 else
8413 gen_helper_add_cc(tmp, tmp, tmp2);
8414 dead_tmp(tmp2);
8415 store_reg(s, rd, tmp);
8416 break;
8417 case 3: /* sub */
8418 if (s->condexec_mask)
8419 tcg_gen_sub_i32(tmp, tmp, tmp2);
8420 else
8421 gen_helper_sub_cc(tmp, tmp, tmp2);
8422 dead_tmp(tmp2);
8423 store_reg(s, rd, tmp);
8424 break;
8425 }
99c475ab 8426 }
99c475ab
FB		 8427 break;
8428 case 4:
8429 if (insn & (1 << 11)) {
8430 rd = (insn >> 8) & 7;
5899f386
FB		 8431 /* load pc-relative. Bit 1 of PC is ignored. */
8432 val = s->pc + 2 + ((insn & 0xff) * 4);
8433 val &= ~(uint32_t)2;
b0109805
PB		 8434 addr = new_tmp();
8435 tcg_gen_movi_i32(addr, val);
8436 tmp = gen_ld32(addr, IS_USER(s));
8437 dead_tmp(addr);
8438 store_reg(s, rd, tmp);
99c475ab
FB		 8439 break;
8440 }
8441 if (insn & (1 << 10)) {
8442 /* data processing extended or blx */
8443 rd = (insn & 7) | ((insn >> 4) & 8);
8444 rm = (insn >> 3) & 0xf;
8445 op = (insn >> 8) & 3;
8446 switch (op) {
8447 case 0: /* add */
396e467c
FN		 8448 tmp = load_reg(s, rd);
8449 tmp2 = load_reg(s, rm);
8450 tcg_gen_add_i32(tmp, tmp, tmp2);
8451 dead_tmp(tmp2);
8452 store_reg(s, rd, tmp);
99c475ab
FB		 8453 break;
8454 case 1: /* cmp */
396e467c
FN		 8455 tmp = load_reg(s, rd);
8456 tmp2 = load_reg(s, rm);
8457 gen_helper_sub_cc(tmp, tmp, tmp2);
8458 dead_tmp(tmp2);
8459 dead_tmp(tmp);
99c475ab
FB		 8460 break;
8461 case 2: /* mov/cpy */
396e467c
FN		 8462 tmp = load_reg(s, rm);
8463 store_reg(s, rd, tmp);
99c475ab
FB		 8464 break;
8465 case 3:/* branch [and link] exchange thumb register */
b0109805 8466 tmp = load_reg(s, rm);
99c475ab
FB		 8467 if (insn & (1 << 7)) {
8468 val = (uint32_t)s->pc | 1;
b0109805
PB		 8469 tmp2 = new_tmp();
8470 tcg_gen_movi_i32(tmp2, val);
8471 store_reg(s, 14, tmp2);
99c475ab 8472 }
d9ba4830 8473 gen_bx(s, tmp);
99c475ab
FB		 8474 break;
8475 }
8476 break;
8477 }
8478
8479 /* data processing register */
8480 rd = insn & 7;
8481 rm = (insn >> 3) & 7;
8482 op = (insn >> 6) & 0xf;
8483 if (op == 2 || op == 3 || op == 4 || op == 7) {
8484 /* the shift/rotate ops want the operands backwards */
8485 val = rm;
8486 rm = rd;
8487 rd = val;
8488 val = 1;
8489 } else {
8490 val = 0;
8491 }
8492
396e467c
FN		 8493 if (op == 9) { /* neg */
8494 tmp = new_tmp();
8495 tcg_gen_movi_i32(tmp, 0);
8496 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8497 tmp = load_reg(s, rd);
8498 } else {
8499 TCGV_UNUSED(tmp);
8500 }
99c475ab 8501
396e467c 8502 tmp2 = load_reg(s, rm);
5899f386 8503 switch (op) {
99c475ab 8504 case 0x0: /* and */
396e467c 8505 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8506 if (!s->condexec_mask)
396e467c 8507 gen_logic_CC(tmp);
99c475ab
FB		 8508 break;
8509 case 0x1: /* eor */
396e467c 8510 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8511 if (!s->condexec_mask)
396e467c 8512 gen_logic_CC(tmp);
99c475ab
FB		 8513 break;
8514 case 0x2: /* lsl */
9ee6e8bb 8515 if (s->condexec_mask) {
396e467c 8516 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8517 } else {
396e467c
FN		 8518 gen_helper_shl_cc(tmp2, tmp2, tmp);
8519 gen_logic_CC(tmp2);
9ee6e8bb 8520 }
99c475ab
FB		 8521 break;
8522 case 0x3: /* lsr */
9ee6e8bb 8523 if (s->condexec_mask) {
396e467c 8524 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8525 } else {
396e467c
FN		 8526 gen_helper_shr_cc(tmp2, tmp2, tmp);
8527 gen_logic_CC(tmp2);
9ee6e8bb 8528 }
99c475ab
FB		 8529 break;
8530 case 0x4: /* asr */
9ee6e8bb 8531 if (s->condexec_mask) {
396e467c 8532 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8533 } else {
396e467c
FN		 8534 gen_helper_sar_cc(tmp2, tmp2, tmp);
8535 gen_logic_CC(tmp2);
9ee6e8bb 8536 }
99c475ab
FB		 8537 break;
8538 case 0x5: /* adc */
9ee6e8bb 8539 if (s->condexec_mask)
396e467c 8540 gen_adc(tmp, tmp2);
9ee6e8bb 8541 else
396e467c 8542 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8543 break;
8544 case 0x6: /* sbc */
9ee6e8bb 8545 if (s->condexec_mask)
396e467c 8546 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8547 else
396e467c 8548 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8549 break;
8550 case 0x7: /* ror */
9ee6e8bb 8551 if (s->condexec_mask) {
f669df27
AJ		 8552 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8553 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8554 } else {
396e467c
FN		 8555 gen_helper_ror_cc(tmp2, tmp2, tmp);
8556 gen_logic_CC(tmp2);
9ee6e8bb 8557 }
99c475ab
FB		 8558 break;
8559 case 0x8: /* tst */
396e467c
FN		 8560 tcg_gen_and_i32(tmp, tmp, tmp2);
8561 gen_logic_CC(tmp);
99c475ab 8562 rd = 16;
5899f386 8563 break;
99c475ab 8564 case 0x9: /* neg */
9ee6e8bb 8565 if (s->condexec_mask)
396e467c 8566 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8567 else
396e467c 8568 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8569 break;
8570 case 0xa: /* cmp */
396e467c 8571 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8572 rd = 16;
8573 break;
8574 case 0xb: /* cmn */
396e467c 8575 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8576 rd = 16;
8577 break;
8578 case 0xc: /* orr */
396e467c 8579 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8580 if (!s->condexec_mask)
396e467c 8581 gen_logic_CC(tmp);
99c475ab
FB		 8582 break;
8583 case 0xd: /* mul */
7b2919a0 8584 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8585 if (!s->condexec_mask)
396e467c 8586 gen_logic_CC(tmp);
99c475ab
FB		 8587 break;
8588 case 0xe: /* bic */
f669df27 8589 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8590 if (!s->condexec_mask)
396e467c 8591 gen_logic_CC(tmp);
99c475ab
FB		 8592 break;
8593 case 0xf: /* mvn */
396e467c 8594 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8595 if (!s->condexec_mask)
396e467c 8596 gen_logic_CC(tmp2);
99c475ab 8597 val = 1;
5899f386 8598 rm = rd;
99c475ab
FB		 8599 break;
8600 }
8601 if (rd != 16) {
396e467c
FN		 8602 if (val) {
8603 store_reg(s, rm, tmp2);
8604 if (op != 0xf)
8605 dead_tmp(tmp);
8606 } else {
8607 store_reg(s, rd, tmp);
8608 dead_tmp(tmp2);
8609 }
8610 } else {
8611 dead_tmp(tmp);
8612 dead_tmp(tmp2);
99c475ab
FB		 8613 }
8614 break;
8615
8616 case 5:
8617 /* load/store register offset. */
8618 rd = insn & 7;
8619 rn = (insn >> 3) & 7;
8620 rm = (insn >> 6) & 7;
8621 op = (insn >> 9) & 7;
b0109805 8622 addr = load_reg(s, rn);
b26eefb6 8623 tmp = load_reg(s, rm);
b0109805 8624 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8625 dead_tmp(tmp);
99c475ab
FB		 8626
8627 if (op < 3) /* store */
b0109805 8628 tmp = load_reg(s, rd);
99c475ab
FB		 8629
8630 switch (op) {
8631 case 0: /* str */
b0109805 8632 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8633 break;
8634 case 1: /* strh */
b0109805 8635 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8636 break;
8637 case 2: /* strb */
b0109805 8638 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8639 break;
8640 case 3: /* ldrsb */
b0109805 8641 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8642 break;
8643 case 4: /* ldr */
b0109805 8644 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8645 break;
8646 case 5: /* ldrh */
b0109805 8647 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8648 break;
8649 case 6: /* ldrb */
b0109805 8650 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8651 break;
8652 case 7: /* ldrsh */
b0109805 8653 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8654 break;
8655 }
8656 if (op >= 3) /* load */
b0109805
PB		 8657 store_reg(s, rd, tmp);
8658 dead_tmp(addr);
99c475ab
FB		 8659 break;
8660
8661 case 6:
8662 /* load/store word immediate offset */
8663 rd = insn & 7;
8664 rn = (insn >> 3) & 7;
b0109805 8665 addr = load_reg(s, rn);
99c475ab 8666 val = (insn >> 4) & 0x7c;
b0109805 8667 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8668
8669 if (insn & (1 << 11)) {
8670 /* load */
b0109805
PB		 8671 tmp = gen_ld32(addr, IS_USER(s));
8672 store_reg(s, rd, tmp);
99c475ab
FB		 8673 } else {
8674 /* store */
b0109805
PB		 8675 tmp = load_reg(s, rd);
8676 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8677 }
b0109805 8678 dead_tmp(addr);
99c475ab
FB		 8679 break;
8680
8681 case 7:
8682 /* load/store byte immediate offset */
8683 rd = insn & 7;
8684 rn = (insn >> 3) & 7;
b0109805 8685 addr = load_reg(s, rn);
99c475ab 8686 val = (insn >> 6) & 0x1f;
b0109805 8687 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8688
8689 if (insn & (1 << 11)) {
8690 /* load */
b0109805
PB		 8691 tmp = gen_ld8u(addr, IS_USER(s));
8692 store_reg(s, rd, tmp);
99c475ab
FB		 8693 } else {
8694 /* store */
b0109805
PB		 8695 tmp = load_reg(s, rd);
8696 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8697 }
b0109805 8698 dead_tmp(addr);
99c475ab
FB		 8699 break;
8700
8701 case 8:
8702 /* load/store halfword immediate offset */
8703 rd = insn & 7;
8704 rn = (insn >> 3) & 7;
b0109805 8705 addr = load_reg(s, rn);
99c475ab 8706 val = (insn >> 5) & 0x3e;
b0109805 8707 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8708
8709 if (insn & (1 << 11)) {
8710 /* load */
b0109805
PB		 8711 tmp = gen_ld16u(addr, IS_USER(s));
8712 store_reg(s, rd, tmp);
99c475ab
FB		 8713 } else {
8714 /* store */
b0109805
PB		 8715 tmp = load_reg(s, rd);
8716 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8717 }
b0109805 8718 dead_tmp(addr);
99c475ab
FB		 8719 break;
8720
8721 case 9:
8722 /* load/store from stack */
8723 rd = (insn >> 8) & 7;
b0109805 8724 addr = load_reg(s, 13);
99c475ab 8725 val = (insn & 0xff) * 4;
b0109805 8726 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8727
8728 if (insn & (1 << 11)) {
8729 /* load */
b0109805
PB		 8730 tmp = gen_ld32(addr, IS_USER(s));
8731 store_reg(s, rd, tmp);
99c475ab
FB		 8732 } else {
8733 /* store */
b0109805
PB		 8734 tmp = load_reg(s, rd);
8735 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8736 }
b0109805 8737 dead_tmp(addr);
99c475ab
FB		 8738 break;
8739
8740 case 10:
8741 /* add to high reg */
8742 rd = (insn >> 8) & 7;
5899f386
FB		 8743 if (insn & (1 << 11)) {
8744 /* SP */
5e3f878a 8745 tmp = load_reg(s, 13);
5899f386
FB		 8746 } else {
8747 /* PC. bit 1 is ignored. */
5e3f878a
PB		 8748 tmp = new_tmp();
8749 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8750 }
99c475ab 8751 val = (insn & 0xff) * 4;
5e3f878a
PB		 8752 tcg_gen_addi_i32(tmp, tmp, val);
8753 store_reg(s, rd, tmp);
99c475ab
FB		 8754 break;
8755
8756 case 11:
8757 /* misc */
8758 op = (insn >> 8) & 0xf;
8759 switch (op) {
8760 case 0:
8761 /* adjust stack pointer */
b26eefb6 8762 tmp = load_reg(s, 13);
99c475ab
FB		 8763 val = (insn & 0x7f) * 4;
8764 if (insn & (1 << 7))
6a0d8a1d 8765 val = -(int32_t)val;
b26eefb6
PB		 8766 tcg_gen_addi_i32(tmp, tmp, val);
8767 store_reg(s, 13, tmp);
99c475ab
FB		 8768 break;
8769
9ee6e8bb
PB		 8770 case 2: /* sign/zero extend. */
8771 ARCH(6);
8772 rd = insn & 7;
8773 rm = (insn >> 3) & 7;
b0109805 8774 tmp = load_reg(s, rm);
9ee6e8bb 8775 switch ((insn >> 6) & 3) {
b0109805
PB		 8776 case 0: gen_sxth(tmp); break;
8777 case 1: gen_sxtb(tmp); break;
8778 case 2: gen_uxth(tmp); break;
8779 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8780 }
b0109805 8781 store_reg(s, rd, tmp);
9ee6e8bb 8782 break;
99c475ab
FB		 8783 case 4: case 5: case 0xc: case 0xd:
8784 /* push/pop */
b0109805 8785 addr = load_reg(s, 13);
5899f386
FB		 8786 if (insn & (1 << 8))
8787 offset = 4;
99c475ab 8788 else
5899f386
FB		 8789 offset = 0;
8790 for (i = 0; i < 8; i++) {
8791 if (insn & (1 << i))
8792 offset += 4;
8793 }
8794 if ((insn & (1 << 11)) == 0) {
b0109805 8795 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8796 }
99c475ab
FB		 8797 for (i = 0; i < 8; i++) {
8798 if (insn & (1 << i)) {
8799 if (insn & (1 << 11)) {
8800 /* pop */
b0109805
PB		 8801 tmp = gen_ld32(addr, IS_USER(s));
8802 store_reg(s, i, tmp);
99c475ab
FB		 8803 } else {
8804 /* push */
b0109805
PB		 8805 tmp = load_reg(s, i);
8806 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8807 }
5899f386 8808 /* advance to the next address. */
b0109805 8809 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8810 }
8811 }
a50f5b91 8812 TCGV_UNUSED(tmp);
99c475ab
FB		 8813 if (insn & (1 << 8)) {
8814 if (insn & (1 << 11)) {
8815 /* pop pc */
b0109805 8816 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8817 /* don't set the pc until the rest of the instruction
8818 has completed */
8819 } else {
8820 /* push lr */
b0109805
PB		 8821 tmp = load_reg(s, 14);
8822 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8823 }
b0109805 8824 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8825 }
5899f386 8826 if ((insn & (1 << 11)) == 0) {
b0109805 8827 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8828 }
99c475ab 8829 /* write back the new stack pointer */
b0109805 8830 store_reg(s, 13, addr);
99c475ab
FB		 8831 /* set the new PC value */
8832 if ((insn & 0x0900) == 0x0900)
b0109805 8833 gen_bx(s, tmp);
99c475ab
FB		 8834 break;
8835
9ee6e8bb
PB		 8836 case 1: case 3: case 9: case 11: /* czb */
8837 rm = insn & 7;
d9ba4830 8838 tmp = load_reg(s, rm);
9ee6e8bb
PB		 8839 s->condlabel = gen_new_label();
8840 s->condjmp = 1;
8841 if (insn & (1 << 11))
cb63669a 8842 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 8843 else
cb63669a 8844 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
d9ba4830 8845 dead_tmp(tmp);
9ee6e8bb
PB		 8846 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8847 val = (uint32_t)s->pc + 2;
8848 val += offset;
8849 gen_jmp(s, val);
8850 break;
8851
8852 case 15: /* IT, nop-hint. */
8853 if ((insn & 0xf) == 0) {
8854 gen_nop_hint(s, (insn >> 4) & 0xf);
8855 break;
8856 }
8857 /* If Then. */
8858 s->condexec_cond = (insn >> 4) & 0xe;
8859 s->condexec_mask = insn & 0x1f;
8860 /* No actual code generated for this insn, just setup state. */
8861 break;
8862
06c949e6 8863 case 0xe: /* bkpt */
9ee6e8bb 8864 gen_set_condexec(s);
5e3f878a 8865 gen_set_pc_im(s->pc - 2);
d9ba4830 8866 gen_exception(EXCP_BKPT);
06c949e6
PB		 8867 s->is_jmp = DISAS_JUMP;
8868 break;
8869
9ee6e8bb
PB		 8870 case 0xa: /* rev */
8871 ARCH(6);
8872 rn = (insn >> 3) & 0x7;
8873 rd = insn & 0x7;
b0109805 8874 tmp = load_reg(s, rn);
9ee6e8bb 8875 switch ((insn >> 6) & 3) {
66896cb8 8876 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 8877 case 1: gen_rev16(tmp); break;
8878 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 8879 default: goto illegal_op;
8880 }
b0109805 8881 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8882 break;
8883
8884 case 6: /* cps */
8885 ARCH(6);
8886 if (IS_USER(s))
8887 break;
8888 if (IS_M(env)) {
8984bd2e 8889 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 8890 /* PRIMASK */
8984bd2e
PB		 8891 if (insn & 1) {
8892 addr = tcg_const_i32(16);
8893 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8894 tcg_temp_free_i32(addr);
8984bd2e 8895 }
9ee6e8bb 8896 /* FAULTMASK */
8984bd2e
PB		 8897 if (insn & 2) {
8898 addr = tcg_const_i32(17);
8899 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 8900 tcg_temp_free_i32(addr);
8984bd2e 8901 }
b75263d6 8902 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 8903 gen_lookup_tb(s);
8904 } else {
8905 if (insn & (1 << 4))
8906 shift = CPSR_A | CPSR_I | CPSR_F;
8907 else
8908 shift = 0;
fa26df03 8909 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 8910 }
8911 break;
8912
99c475ab
FB		 8913 default:
8914 goto undef;
8915 }
8916 break;
8917
8918 case 12:
8919 /* load/store multiple */
8920 rn = (insn >> 8) & 0x7;
b0109805 8921 addr = load_reg(s, rn);
99c475ab
FB		 8922 for (i = 0; i < 8; i++) {
8923 if (insn & (1 << i)) {
99c475ab
FB		 8924 if (insn & (1 << 11)) {
8925 /* load */
b0109805
PB		 8926 tmp = gen_ld32(addr, IS_USER(s));
8927 store_reg(s, i, tmp);
99c475ab
FB		 8928 } else {
8929 /* store */
b0109805
PB		 8930 tmp = load_reg(s, i);
8931 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8932 }
5899f386 8933 /* advance to the next address */
b0109805 8934 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8935 }
8936 }
5899f386 8937 /* Base register writeback. */
b0109805
PB		 8938 if ((insn & (1 << rn)) == 0) {
8939 store_reg(s, rn, addr);
8940 } else {
8941 dead_tmp(addr);
8942 }
99c475ab
FB		 8943 break;
8944
8945 case 13:
8946 /* conditional branch or swi */
8947 cond = (insn >> 8) & 0xf;
8948 if (cond == 0xe)
8949 goto undef;
8950
8951 if (cond == 0xf) {
8952 /* swi */
9ee6e8bb 8953 gen_set_condexec(s);
422ebf69 8954 gen_set_pc_im(s->pc);
9ee6e8bb 8955 s->is_jmp = DISAS_SWI;
99c475ab
FB		 8956 break;
8957 }
8958 /* generate a conditional jump to next instruction */
e50e6a20 8959 s->condlabel = gen_new_label();
d9ba4830 8960 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 8961 s->condjmp = 1;
99c475ab
FB		 8962
8963 /* jump to the offset */
5899f386 8964 val = (uint32_t)s->pc + 2;
99c475ab 8965 offset = ((int32_t)insn << 24) >> 24;
5899f386 8966 val += offset << 1;
8aaca4c0 8967 gen_jmp(s, val);
99c475ab
FB		 8968 break;
8969
8970 case 14:
358bf29e 8971 if (insn & (1 << 11)) {
9ee6e8bb
PB		 8972 if (disas_thumb2_insn(env, s, insn))
8973 goto undef32;
358bf29e
PB		 8974 break;
8975 }
9ee6e8bb 8976 /* unconditional branch */
99c475ab
FB		 8977 val = (uint32_t)s->pc;
8978 offset = ((int32_t)insn << 21) >> 21;
8979 val += (offset << 1) + 2;
8aaca4c0 8980 gen_jmp(s, val);
99c475ab
FB		 8981 break;
8982
8983 case 15:
9ee6e8bb 8984 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 8985 goto undef32;
9ee6e8bb 8986 break;
99c475ab
FB		 8987 }
8988 return;
9ee6e8bb
PB		 8989undef32:
8990 gen_set_condexec(s);
5e3f878a 8991 gen_set_pc_im(s->pc - 4);
d9ba4830 8992 gen_exception(EXCP_UDEF);
9ee6e8bb
PB		 8993 s->is_jmp = DISAS_JUMP;
8994 return;
8995illegal_op:
99c475ab 8996undef:
9ee6e8bb 8997 gen_set_condexec(s);
5e3f878a 8998 gen_set_pc_im(s->pc - 2);
d9ba4830 8999 gen_exception(EXCP_UDEF);
99c475ab
FB		 9000 s->is_jmp = DISAS_JUMP;
9001}
9002
2c0262af
FB		 9003/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9004 basic block 'tb'. If search_pc is TRUE, also generate PC
9005 information for each intermediate instruction. */
2cfc5f17
TS		 9006static inline void gen_intermediate_code_internal(CPUState *env,
9007 TranslationBlock *tb,
9008 int search_pc)
2c0262af
FB		 9009{
9010 DisasContext dc1, *dc = &dc1;
a1d1bb31 9011 CPUBreakpoint *bp;
2c0262af
FB		 9012 uint16_t *gen_opc_end;
9013 int j, lj;
0fa85d43 9014 target_ulong pc_start;
b5ff1b31 9015 uint32_t next_page_start;
2e70f6ef
PB		 9016 int num_insns;
9017 int max_insns;
3b46e624 9018
2c0262af 9019 /* generate intermediate code */
b26eefb6 9020 num_temps = 0;
b26eefb6 9021
0fa85d43 9022 pc_start = tb->pc;
3b46e624 9023
2c0262af
FB		 9024 dc->tb = tb;
9025
2c0262af 9026 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9027
9028 dc->is_jmp = DISAS_NEXT;
9029 dc->pc = pc_start;
8aaca4c0 9030 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9031 dc->condjmp = 0;
5899f386 9032 dc->thumb = env->thumb;
9ee6e8bb
PB		 9033 dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
9034 dc->condexec_cond = env->condexec_bits >> 4;
b5ff1b31 9035#if !defined(CONFIG_USER_ONLY)
9ee6e8bb
PB		 9036 if (IS_M(env)) {
9037 dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
9038 } else {
9039 dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
9040 }
b5ff1b31 9041#endif
a7812ae4
PB		 9042 cpu_F0s = tcg_temp_new_i32();
9043 cpu_F1s = tcg_temp_new_i32();
9044 cpu_F0d = tcg_temp_new_i64();
9045 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9046 cpu_V0 = cpu_F0d;
9047 cpu_V1 = cpu_F1d;
e677137d 9048 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9049 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9050 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9051 lj = -1;
2e70f6ef
PB		 9052 num_insns = 0;
9053 max_insns = tb->cflags & CF_COUNT_MASK;
9054 if (max_insns == 0)
9055 max_insns = CF_COUNT_MASK;
9056
9057 gen_icount_start();
9ee6e8bb
PB		 9058 /* Reset the conditional execution bits immediately. This avoids
9059 complications trying to do it at the end of the block. */
9060 if (env->condexec_bits)
8f01245e
PB		 9061 {
9062 TCGv tmp = new_tmp();
9063 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9064 store_cpu_field(tmp, condexec_bits);
8f01245e 9065 }
2c0262af 9066 do {
fbb4a2e3
PB		 9067#ifdef CONFIG_USER_ONLY
9068 /* Intercept jump to the magic kernel page. */
9069 if (dc->pc >= 0xffff0000) {
9070 /* We always get here via a jump, so know we are not in a
9071 conditional execution block. */
9072 gen_exception(EXCP_KERNEL_TRAP);
9073 dc->is_jmp = DISAS_UPDATE;
9074 break;
9075 }
9076#else
9ee6e8bb
PB		 9077 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9078 /* We always get here via a jump, so know we are not in a
9079 conditional execution block. */
d9ba4830 9080 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9081 dc->is_jmp = DISAS_UPDATE;
9082 break;
9ee6e8bb
PB		 9083 }
9084#endif
9085
72cf2d4f
BS		 9086 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9087 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9088 if (bp->pc == dc->pc) {
9ee6e8bb 9089 gen_set_condexec(dc);
5e3f878a 9090 gen_set_pc_im(dc->pc);
d9ba4830 9091 gen_exception(EXCP_DEBUG);
1fddef4b 9092 dc->is_jmp = DISAS_JUMP;
9ee6e8bb
PB		 9093 /* Advance PC so that clearing the breakpoint will
9094 invalidate this TB. */
9095 dc->pc += 2;
9096 goto done_generating;
1fddef4b
FB		 9097 break;
9098 }
9099 }
9100 }
2c0262af
FB		 9101 if (search_pc) {
9102 j = gen_opc_ptr - gen_opc_buf;
9103 if (lj < j) {
9104 lj++;
9105 while (lj < j)
9106 gen_opc_instr_start[lj++] = 0;
9107 }
0fa85d43 9108 gen_opc_pc[lj] = dc->pc;
2c0262af 9109 gen_opc_instr_start[lj] = 1;
2e70f6ef 9110 gen_opc_icount[lj] = num_insns;
2c0262af 9111 }
e50e6a20 9112
2e70f6ef
PB		 9113 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9114 gen_io_start();
9115
9ee6e8bb
PB		 9116 if (env->thumb) {
9117 disas_thumb_insn(env, dc);
9118 if (dc->condexec_mask) {
9119 dc->condexec_cond = (dc->condexec_cond & 0xe)
9120 | ((dc->condexec_mask >> 4) & 1);
9121 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9122 if (dc->condexec_mask == 0) {
9123 dc->condexec_cond = 0;
9124 }
9125 }
9126 } else {
9127 disas_arm_insn(env, dc);
9128 }
b26eefb6
PB		 9129 if (num_temps) {
9130 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9131 num_temps = 0;
9132 }
e50e6a20
FB		 9133
9134 if (dc->condjmp && !dc->is_jmp) {
9135 gen_set_label(dc->condlabel);
9136 dc->condjmp = 0;
9137 }
aaf2d97d 9138 /* Translation stops when a conditional branch is encountered.
e50e6a20 9139 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9140 * Also stop translation when a page boundary is reached. This
bf20dc07 9141 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9142 num_insns ++;
1fddef4b
FB		 9143 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9144 !env->singlestep_enabled &&
1b530a6d 9145 !singlestep &&
2e70f6ef
PB		 9146 dc->pc < next_page_start &&
9147 num_insns < max_insns);
9148
9149 if (tb->cflags & CF_LAST_IO) {
9150 if (dc->condjmp) {
9151 /* FIXME: This can theoretically happen with self-modifying
9152 code. */
9153 cpu_abort(env, "IO on conditional branch instruction");
9154 }
9155 gen_io_end();
9156 }
9ee6e8bb 9157
b5ff1b31 9158 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9159 instruction was a conditional branch or trap, and the PC has
9160 already been written. */
551bd27f 9161 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9162 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9163 if (dc->condjmp) {
9ee6e8bb
PB		 9164 gen_set_condexec(dc);
9165 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9166 gen_exception(EXCP_SWI);
9ee6e8bb 9167 } else {
d9ba4830 9168 gen_exception(EXCP_DEBUG);
9ee6e8bb 9169 }
e50e6a20
FB		 9170 gen_set_label(dc->condlabel);
9171 }
9172 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9173 gen_set_pc_im(dc->pc);
e50e6a20 9174 dc->condjmp = 0;
8aaca4c0 9175 }
9ee6e8bb
PB		 9176 gen_set_condexec(dc);
9177 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9178 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9179 } else {
9180 /* FIXME: Single stepping a WFI insn will not halt
9181 the CPU. */
d9ba4830 9182 gen_exception(EXCP_DEBUG);
9ee6e8bb 9183 }
8aaca4c0 9184 } else {
9ee6e8bb
PB		 9185 /* While branches must always occur at the end of an IT block,
9186 there are a few other things that can cause us to terminate
9187 the TB in the middel of an IT block:
9188 - Exception generating instructions (bkpt, swi, undefined).
9189 - Page boundaries.
9190 - Hardware watchpoints.
9191 Hardware breakpoints have already been handled and skip this code.
9192 */
9193 gen_set_condexec(dc);
8aaca4c0 9194 switch(dc->is_jmp) {
8aaca4c0 9195 case DISAS_NEXT:
6e256c93 9196 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9197 break;
9198 default:
9199 case DISAS_JUMP:
9200 case DISAS_UPDATE:
9201 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9202 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9203 break;
9204 case DISAS_TB_JUMP:
9205 /* nothing more to generate */
9206 break;
9ee6e8bb 9207 case DISAS_WFI:
d9ba4830 9208 gen_helper_wfi();
9ee6e8bb
PB		 9209 break;
9210 case DISAS_SWI:
d9ba4830 9211 gen_exception(EXCP_SWI);
9ee6e8bb 9212 break;
8aaca4c0 9213 }
e50e6a20
FB		 9214 if (dc->condjmp) {
9215 gen_set_label(dc->condlabel);
9ee6e8bb 9216 gen_set_condexec(dc);
6e256c93 9217 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9218 dc->condjmp = 0;
9219 }
2c0262af 9220 }
2e70f6ef 9221
9ee6e8bb 9222done_generating:
2e70f6ef 9223 gen_icount_end(tb, num_insns);
2c0262af
FB		 9224 *gen_opc_ptr = INDEX_op_end;
9225
9226#ifdef DEBUG_DISAS
8fec2b8c 9227 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9228 qemu_log("----------------\n");
9229 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9230 log_target_disas(pc_start, dc->pc - pc_start, env->thumb);
9231 qemu_log("\n");
2c0262af
FB		 9232 }
9233#endif
b5ff1b31
FB		 9234 if (search_pc) {
9235 j = gen_opc_ptr - gen_opc_buf;
9236 lj++;
9237 while (lj <= j)
9238 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9239 } else {
2c0262af 9240 tb->size = dc->pc - pc_start;
2e70f6ef 9241 tb->icount = num_insns;
b5ff1b31 9242 }
2c0262af
FB		 9243}
9244
2cfc5f17 9245void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9246{
2cfc5f17 9247 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9248}
9249
2cfc5f17 9250void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9251{
2cfc5f17 9252 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9253}
9254
b5ff1b31
FB		 9255static const char *cpu_mode_names[16] = {
9256 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9257 "???", "???", "???", "und", "???", "???", "???", "sys"
9258};
9ee6e8bb 9259
5fafdf24 9260void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 9261 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
9262 int flags)
2c0262af
FB		 9263{
9264 int i;
06e80fc9 9265#if 0
bc380d17 9266 union {
b7bcbe95
FB		 9267 uint32_t i;
9268 float s;
9269 } s0, s1;
9270 CPU_DoubleU d;
a94a6abf
PB		 9271 /* ??? This assumes float64 and double have the same layout.
9272 Oh well, it's only debug dumps. */
9273 union {
9274 float64 f64;
9275 double d;
9276 } d0;
06e80fc9 9277#endif
b5ff1b31 9278 uint32_t psr;
2c0262af
FB		 9279
9280 for(i=0;i<16;i++) {
7fe48483 9281 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9282 if ((i % 4) == 3)
7fe48483 9283 cpu_fprintf(f, "\n");
2c0262af 9284 else
7fe48483 9285 cpu_fprintf(f, " ");
2c0262af 9286 }
b5ff1b31 9287 psr = cpsr_read(env);
687fa640
TS		 9288 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9289 psr,
b5ff1b31
FB		 9290 psr & (1 << 31) ? 'N' : '-',
9291 psr & (1 << 30) ? 'Z' : '-',
9292 psr & (1 << 29) ? 'C' : '-',
9293 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9294 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9295 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9296
5e3f878a 9297#if 0
b7bcbe95 9298 for (i = 0; i < 16; i++) {
8e96005d
FB		 9299 d.d = env->vfp.regs[i];
9300 s0.i = d.l.lower;
9301 s1.i = d.l.upper;
a94a6abf
PB		 9302 d0.f64 = d.d;
9303 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9304 i * 2, (int)s0.i, s0.s,
a94a6abf 9305 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9306 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9307 d0.d);
b7bcbe95 9308 }
40f137e1 9309 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9310#endif
2c0262af 9311}
a6b025d3 9312
d2856f1a
AJ		 9313void gen_pc_load(CPUState *env, TranslationBlock *tb,
9314 unsigned long searched_pc, int pc_pos, void *puc)
9315{
9316 env->regs[15] = gen_opc_pc[pc_pos];
9317}
Qemu copy for testing