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target-arm: Correct conversion of Thumb Neon dp encodings into ARM
[qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
5fafdf24 3 *
2c0262af 4 * Copyright (c) 2003 Fabrice Bellard
9ee6e8bb 5 * Copyright (c) 2005-2007 CodeSourcery
18c9b560 6 * Copyright (c) 2007 OpenedHand, Ltd.
2c0262af
FB		 7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
8167ee88 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af
FB		 20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
57fec1fe 30#include "tcg-op.h"
79383c9c 31#include "qemu-log.h"
1497c961 32
a7812ae4 33#include "helpers.h"
1497c961 34#define GEN_HELPER 1
b26eefb6 35#include "helpers.h"
2c0262af 36
9ee6e8bb
PB		 37#define ENABLE_ARCH_5J 0
38#define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39#define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40#define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41#define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
b5ff1b31 42
86753403 43#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
b5ff1b31 44
2c0262af
FB		 45/* internal defines */
46typedef struct DisasContext {
0fa85d43 47 target_ulong pc;
2c0262af 48 int is_jmp;
e50e6a20
FB		 49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
9ee6e8bb
PB		 53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
2c0262af 56 struct TranslationBlock *tb;
8aaca4c0 57 int singlestep_enabled;
5899f386 58 int thumb;
b5ff1b31
FB		 59#if !defined(CONFIG_USER_ONLY)
60 int user;
61#endif
5df8bac1 62 int vfp_enabled;
69d1fc22
PM		 63 int vec_len;
64 int vec_stride;
2c0262af
FB		 65} DisasContext;
66
e12ce78d
PM		 67static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
b5ff1b31
FB		 69#if defined(CONFIG_USER_ONLY)
70#define IS_USER(s) 1
71#else
72#define IS_USER(s) (s->user)
73#endif
74
9ee6e8bb
PB		 75/* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77#define DISAS_WFI 4
78#define DISAS_SWI 5
2c0262af 79
a7812ae4 80static TCGv_ptr cpu_env;
ad69471c 81/* We reuse the same 64-bit temporaries for efficiency. */
a7812ae4 82static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
155c3eac 83static TCGv_i32 cpu_R[16];
426f5abc
PB		 84static TCGv_i32 cpu_exclusive_addr;
85static TCGv_i32 cpu_exclusive_val;
86static TCGv_i32 cpu_exclusive_high;
87#ifdef CONFIG_USER_ONLY
88static TCGv_i32 cpu_exclusive_test;
89static TCGv_i32 cpu_exclusive_info;
90#endif
ad69471c 91
b26eefb6 92/* FIXME: These should be removed. */
a7812ae4
PB		 93static TCGv cpu_F0s, cpu_F1s;
94static TCGv_i64 cpu_F0d, cpu_F1d;
b26eefb6 95
2e70f6ef
PB		 96#include "gen-icount.h"
97
155c3eac
FN		 98static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
b26eefb6
PB		 102/* initialize TCG globals. */
103void arm_translate_init(void)
104{
155c3eac
FN		 105 int i;
106
a7812ae4
PB		 107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
155c3eac
FN		 109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
426f5abc
PB		 114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120#ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125#endif
155c3eac 126
a7812ae4
PB		 127#define GEN_HELPER 2
128#include "helpers.h"
b26eefb6
PB		 129}
130
b26eefb6 131static int num_temps;
b26eefb6
PB		 132
133/* Allocate a temporary variable. */
a7812ae4 134static TCGv_i32 new_tmp(void)
b26eefb6 135{
12edd4f2
FN		 136 num_temps++;
137 return tcg_temp_new_i32();
b26eefb6
PB		 138}
139
140/* Release a temporary variable. */
141static void dead_tmp(TCGv tmp)
142{
12edd4f2 143 tcg_temp_free(tmp);
b26eefb6 144 num_temps--;
b26eefb6
PB		 145}
146
d9ba4830
PB		 147static inline TCGv load_cpu_offset(int offset)
148{
149 TCGv tmp = new_tmp();
150 tcg_gen_ld_i32(tmp, cpu_env, offset);
151 return tmp;
152}
153
154#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
155
156static inline void store_cpu_offset(TCGv var, int offset)
157{
158 tcg_gen_st_i32(var, cpu_env, offset);
159 dead_tmp(var);
160}
161
162#define store_cpu_field(var, name) \
163 store_cpu_offset(var, offsetof(CPUState, name))
164
b26eefb6
PB		 165/* Set a variable to the value of a CPU register. */
166static void load_reg_var(DisasContext *s, TCGv var, int reg)
167{
168 if (reg == 15) {
169 uint32_t addr;
170 /* normaly, since we updated PC, we need only to add one insn */
171 if (s->thumb)
172 addr = (long)s->pc + 2;
173 else
174 addr = (long)s->pc + 4;
175 tcg_gen_movi_i32(var, addr);
176 } else {
155c3eac 177 tcg_gen_mov_i32(var, cpu_R[reg]);
b26eefb6
PB		 178 }
179}
180
181/* Create a new temporary and set it to the value of a CPU register. */
182static inline TCGv load_reg(DisasContext *s, int reg)
183{
184 TCGv tmp = new_tmp();
185 load_reg_var(s, tmp, reg);
186 return tmp;
187}
188
189/* Set a CPU register. The source must be a temporary and will be
190 marked as dead. */
191static void store_reg(DisasContext *s, int reg, TCGv var)
192{
193 if (reg == 15) {
194 tcg_gen_andi_i32(var, var, ~1);
195 s->is_jmp = DISAS_JUMP;
196 }
155c3eac 197 tcg_gen_mov_i32(cpu_R[reg], var);
b26eefb6
PB		 198 dead_tmp(var);
199}
200
b26eefb6 201/* Value extensions. */
86831435
PB		 202#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
203#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
b26eefb6
PB		 204#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
205#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
206
1497c961
PB		 207#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
208#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
8f01245e 209
b26eefb6 210
b75263d6
JR		 211static inline void gen_set_cpsr(TCGv var, uint32_t mask)
212{
213 TCGv tmp_mask = tcg_const_i32(mask);
214 gen_helper_cpsr_write(var, tmp_mask);
215 tcg_temp_free_i32(tmp_mask);
216}
d9ba4830
PB		 217/* Set NZCV flags from the high 4 bits of var. */
218#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
219
220static void gen_exception(int excp)
221{
222 TCGv tmp = new_tmp();
223 tcg_gen_movi_i32(tmp, excp);
224 gen_helper_exception(tmp);
225 dead_tmp(tmp);
226}
227
3670669c
PB		 228static void gen_smul_dual(TCGv a, TCGv b)
229{
230 TCGv tmp1 = new_tmp();
231 TCGv tmp2 = new_tmp();
22478e79
AZ		 232 tcg_gen_ext16s_i32(tmp1, a);
233 tcg_gen_ext16s_i32(tmp2, b);
3670669c
PB		 234 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
235 dead_tmp(tmp2);
236 tcg_gen_sari_i32(a, a, 16);
237 tcg_gen_sari_i32(b, b, 16);
238 tcg_gen_mul_i32(b, b, a);
239 tcg_gen_mov_i32(a, tmp1);
240 dead_tmp(tmp1);
241}
242
243/* Byteswap each halfword. */
244static void gen_rev16(TCGv var)
245{
246 TCGv tmp = new_tmp();
247 tcg_gen_shri_i32(tmp, var, 8);
248 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
249 tcg_gen_shli_i32(var, var, 8);
250 tcg_gen_andi_i32(var, var, 0xff00ff00);
251 tcg_gen_or_i32(var, var, tmp);
252 dead_tmp(tmp);
253}
254
255/* Byteswap low halfword and sign extend. */
256static void gen_revsh(TCGv var)
257{
1a855029
AJ		 258 tcg_gen_ext16u_i32(var, var);
259 tcg_gen_bswap16_i32(var, var);
260 tcg_gen_ext16s_i32(var, var);
3670669c
PB		 261}
262
263/* Unsigned bitfield extract. */
264static void gen_ubfx(TCGv var, int shift, uint32_t mask)
265{
266 if (shift)
267 tcg_gen_shri_i32(var, var, shift);
268 tcg_gen_andi_i32(var, var, mask);
269}
270
271/* Signed bitfield extract. */
272static void gen_sbfx(TCGv var, int shift, int width)
273{
274 uint32_t signbit;
275
276 if (shift)
277 tcg_gen_sari_i32(var, var, shift);
278 if (shift + width < 32) {
279 signbit = 1u << (width - 1);
280 tcg_gen_andi_i32(var, var, (1u << width) - 1);
281 tcg_gen_xori_i32(var, var, signbit);
282 tcg_gen_subi_i32(var, var, signbit);
283 }
284}
285
286/* Bitfield insertion. Insert val into base. Clobbers base and val. */
287static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
288{
3670669c 289 tcg_gen_andi_i32(val, val, mask);
8f8e3aa4
PB		 290 tcg_gen_shli_i32(val, val, shift);
291 tcg_gen_andi_i32(base, base, ~(mask << shift));
3670669c
PB		 292 tcg_gen_or_i32(dest, base, val);
293}
294
838fa72d
AJ		 295/* Return (b << 32) + a. Mark inputs as dead */
296static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
3670669c 297{
838fa72d
AJ		 298 TCGv_i64 tmp64 = tcg_temp_new_i64();
299
300 tcg_gen_extu_i32_i64(tmp64, b);
301 dead_tmp(b);
302 tcg_gen_shli_i64(tmp64, tmp64, 32);
303 tcg_gen_add_i64(a, tmp64, a);
304
305 tcg_temp_free_i64(tmp64);
306 return a;
307}
308
309/* Return (b << 32) - a. Mark inputs as dead. */
310static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
311{
312 TCGv_i64 tmp64 = tcg_temp_new_i64();
313
314 tcg_gen_extu_i32_i64(tmp64, b);
315 dead_tmp(b);
316 tcg_gen_shli_i64(tmp64, tmp64, 32);
317 tcg_gen_sub_i64(a, tmp64, a);
318
319 tcg_temp_free_i64(tmp64);
320 return a;
3670669c
PB		 321}
322
8f01245e
PB		 323/* FIXME: Most targets have native widening multiplication.
324 It would be good to use that instead of a full wide multiply. */
5e3f878a 325/* 32x32->64 multiply. Marks inputs as dead. */
a7812ae4 326static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
5e3f878a 327{
a7812ae4
PB		 328 TCGv_i64 tmp1 = tcg_temp_new_i64();
329 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 330
331 tcg_gen_extu_i32_i64(tmp1, a);
332 dead_tmp(a);
333 tcg_gen_extu_i32_i64(tmp2, b);
334 dead_tmp(b);
335 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 336 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 337 return tmp1;
338}
339
a7812ae4 340static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
5e3f878a 341{
a7812ae4
PB		 342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
5e3f878a
PB		 344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
b75263d6 350 tcg_temp_free_i64(tmp2);
5e3f878a
PB		 351 return tmp1;
352}
353
8f01245e
PB		 354/* Swap low and high halfwords. */
355static void gen_swap_half(TCGv var)
356{
357 TCGv tmp = new_tmp();
358 tcg_gen_shri_i32(tmp, var, 16);
359 tcg_gen_shli_i32(var, var, 16);
360 tcg_gen_or_i32(var, var, tmp);
3670669c 361 dead_tmp(tmp);
8f01245e
PB		 362}
363
b26eefb6
PB		 364/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
365 tmp = (t0 ^ t1) & 0x8000;
366 t0 &= ~0x8000;
367 t1 &= ~0x8000;
368 t0 = (t0 + t1) ^ tmp;
369 */
370
371static void gen_add16(TCGv t0, TCGv t1)
372{
373 TCGv tmp = new_tmp();
374 tcg_gen_xor_i32(tmp, t0, t1);
375 tcg_gen_andi_i32(tmp, tmp, 0x8000);
376 tcg_gen_andi_i32(t0, t0, ~0x8000);
377 tcg_gen_andi_i32(t1, t1, ~0x8000);
378 tcg_gen_add_i32(t0, t0, t1);
379 tcg_gen_xor_i32(t0, t0, tmp);
380 dead_tmp(tmp);
381 dead_tmp(t1);
382}
383
9a119ff6
PB		 384#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
385
b26eefb6
PB		 386/* Set CF to the top bit of var. */
387static void gen_set_CF_bit31(TCGv var)
388{
389 TCGv tmp = new_tmp();
390 tcg_gen_shri_i32(tmp, var, 31);
4cc633c3 391 gen_set_CF(tmp);
b26eefb6
PB		 392 dead_tmp(tmp);
393}
394
395/* Set N and Z flags from var. */
396static inline void gen_logic_CC(TCGv var)
397{
6fbe23d5
PB		 398 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
399 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
b26eefb6
PB		 400}
401
402/* T0 += T1 + CF. */
396e467c 403static void gen_adc(TCGv t0, TCGv t1)
b26eefb6 404{
d9ba4830 405 TCGv tmp;
396e467c 406 tcg_gen_add_i32(t0, t0, t1);
d9ba4830 407 tmp = load_cpu_field(CF);
396e467c 408 tcg_gen_add_i32(t0, t0, tmp);
b26eefb6
PB		 409 dead_tmp(tmp);
410}
411
e9bb4aa9
JR		 412/* dest = T0 + T1 + CF. */
413static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
414{
415 TCGv tmp;
416 tcg_gen_add_i32(dest, t0, t1);
417 tmp = load_cpu_field(CF);
418 tcg_gen_add_i32(dest, dest, tmp);
419 dead_tmp(tmp);
420}
421
3670669c
PB		 422/* dest = T0 - T1 + CF - 1. */
423static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
424{
d9ba4830 425 TCGv tmp;
3670669c 426 tcg_gen_sub_i32(dest, t0, t1);
d9ba4830 427 tmp = load_cpu_field(CF);
3670669c
PB		 428 tcg_gen_add_i32(dest, dest, tmp);
429 tcg_gen_subi_i32(dest, dest, 1);
430 dead_tmp(tmp);
431}
432
ad69471c
PB		 433/* FIXME: Implement this natively. */
434#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
435
9a119ff6 436static void shifter_out_im(TCGv var, int shift)
b26eefb6 437{
9a119ff6
PB		 438 TCGv tmp = new_tmp();
439 if (shift == 0) {
440 tcg_gen_andi_i32(tmp, var, 1);
b26eefb6 441 } else {
9a119ff6 442 tcg_gen_shri_i32(tmp, var, shift);
4cc633c3 443 if (shift != 31)
9a119ff6
PB		 444 tcg_gen_andi_i32(tmp, tmp, 1);
445 }
446 gen_set_CF(tmp);
447 dead_tmp(tmp);
448}
b26eefb6 449
9a119ff6
PB		 450/* Shift by immediate. Includes special handling for shift == 0. */
451static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
452{
453 switch (shiftop) {
454 case 0: /* LSL */
455 if (shift != 0) {
456 if (flags)
457 shifter_out_im(var, 32 - shift);
458 tcg_gen_shli_i32(var, var, shift);
459 }
460 break;
461 case 1: /* LSR */
462 if (shift == 0) {
463 if (flags) {
464 tcg_gen_shri_i32(var, var, 31);
465 gen_set_CF(var);
466 }
467 tcg_gen_movi_i32(var, 0);
468 } else {
469 if (flags)
470 shifter_out_im(var, shift - 1);
471 tcg_gen_shri_i32(var, var, shift);
472 }
473 break;
474 case 2: /* ASR */
475 if (shift == 0)
476 shift = 32;
477 if (flags)
478 shifter_out_im(var, shift - 1);
479 if (shift == 32)
480 shift = 31;
481 tcg_gen_sari_i32(var, var, shift);
482 break;
483 case 3: /* ROR/RRX */
484 if (shift != 0) {
485 if (flags)
486 shifter_out_im(var, shift - 1);
f669df27 487 tcg_gen_rotri_i32(var, var, shift); break;
9a119ff6 488 } else {
d9ba4830 489 TCGv tmp = load_cpu_field(CF);
9a119ff6
PB		 490 if (flags)
491 shifter_out_im(var, 0);
492 tcg_gen_shri_i32(var, var, 1);
b26eefb6
PB		 493 tcg_gen_shli_i32(tmp, tmp, 31);
494 tcg_gen_or_i32(var, var, tmp);
495 dead_tmp(tmp);
b26eefb6
PB		 496 }
497 }
498};
499
8984bd2e
PB		 500static inline void gen_arm_shift_reg(TCGv var, int shiftop,
501 TCGv shift, int flags)
502{
503 if (flags) {
504 switch (shiftop) {
505 case 0: gen_helper_shl_cc(var, var, shift); break;
506 case 1: gen_helper_shr_cc(var, var, shift); break;
507 case 2: gen_helper_sar_cc(var, var, shift); break;
508 case 3: gen_helper_ror_cc(var, var, shift); break;
509 }
510 } else {
511 switch (shiftop) {
512 case 0: gen_helper_shl(var, var, shift); break;
513 case 1: gen_helper_shr(var, var, shift); break;
514 case 2: gen_helper_sar(var, var, shift); break;
f669df27
AJ		 515 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
516 tcg_gen_rotr_i32(var, var, shift); break;
8984bd2e
PB		 517 }
518 }
519 dead_tmp(shift);
520}
521
6ddbc6e4
PB		 522#define PAS_OP(pfx) \
523 switch (op2) { \
524 case 0: gen_pas_helper(glue(pfx,add16)); break; \
525 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
526 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
527 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
528 case 4: gen_pas_helper(glue(pfx,add8)); break; \
529 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 }
d9ba4830 531static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 532{
a7812ae4 533 TCGv_ptr tmp;
6ddbc6e4
PB		 534
535 switch (op1) {
536#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 case 1:
a7812ae4 538 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(s)
b75263d6 541 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 542 break;
543 case 5:
a7812ae4 544 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 545 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
546 PAS_OP(u)
b75263d6 547 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 548 break;
549#undef gen_pas_helper
550#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 case 2:
552 PAS_OP(q);
553 break;
554 case 3:
555 PAS_OP(sh);
556 break;
557 case 6:
558 PAS_OP(uq);
559 break;
560 case 7:
561 PAS_OP(uh);
562 break;
563#undef gen_pas_helper
564 }
565}
9ee6e8bb
PB		 566#undef PAS_OP
567
6ddbc6e4
PB		 568/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
569#define PAS_OP(pfx) \
ed89a2f1 570 switch (op1) { \
6ddbc6e4
PB		 571 case 0: gen_pas_helper(glue(pfx,add8)); break; \
572 case 1: gen_pas_helper(glue(pfx,add16)); break; \
573 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
574 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
575 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
576 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 }
d9ba4830 578static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
6ddbc6e4 579{
a7812ae4 580 TCGv_ptr tmp;
6ddbc6e4 581
ed89a2f1 582 switch (op2) {
6ddbc6e4
PB		 583#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 case 0:
a7812ae4 585 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(s)
b75263d6 588 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 589 break;
590 case 4:
a7812ae4 591 tmp = tcg_temp_new_ptr();
6ddbc6e4
PB		 592 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
593 PAS_OP(u)
b75263d6 594 tcg_temp_free_ptr(tmp);
6ddbc6e4
PB		 595 break;
596#undef gen_pas_helper
597#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 1:
599 PAS_OP(q);
600 break;
601 case 2:
602 PAS_OP(sh);
603 break;
604 case 5:
605 PAS_OP(uq);
606 break;
607 case 6:
608 PAS_OP(uh);
609 break;
610#undef gen_pas_helper
611 }
612}
9ee6e8bb
PB		 613#undef PAS_OP
614
d9ba4830
PB		 615static void gen_test_cc(int cc, int label)
616{
617 TCGv tmp;
618 TCGv tmp2;
d9ba4830
PB		 619 int inv;
620
d9ba4830
PB		 621 switch (cc) {
622 case 0: /* eq: Z */
6fbe23d5 623 tmp = load_cpu_field(ZF);
cb63669a 624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 625 break;
626 case 1: /* ne: !Z */
6fbe23d5 627 tmp = load_cpu_field(ZF);
cb63669a 628 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 629 break;
630 case 2: /* cs: C */
631 tmp = load_cpu_field(CF);
cb63669a 632 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 633 break;
634 case 3: /* cc: !C */
635 tmp = load_cpu_field(CF);
cb63669a 636 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 637 break;
638 case 4: /* mi: N */
6fbe23d5 639 tmp = load_cpu_field(NF);
cb63669a 640 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 641 break;
642 case 5: /* pl: !N */
6fbe23d5 643 tmp = load_cpu_field(NF);
cb63669a 644 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 645 break;
646 case 6: /* vs: V */
647 tmp = load_cpu_field(VF);
cb63669a 648 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 649 break;
650 case 7: /* vc: !V */
651 tmp = load_cpu_field(VF);
cb63669a 652 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 653 break;
654 case 8: /* hi: C && !Z */
655 inv = gen_new_label();
656 tmp = load_cpu_field(CF);
cb63669a 657 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830 658 dead_tmp(tmp);
6fbe23d5 659 tmp = load_cpu_field(ZF);
cb63669a 660 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
d9ba4830
PB		 661 gen_set_label(inv);
662 break;
663 case 9: /* ls: !C || Z */
664 tmp = load_cpu_field(CF);
cb63669a 665 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830 666 dead_tmp(tmp);
6fbe23d5 667 tmp = load_cpu_field(ZF);
cb63669a 668 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 669 break;
670 case 10: /* ge: N == V -> N ^ V == 0 */
671 tmp = load_cpu_field(VF);
6fbe23d5 672 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 673 tcg_gen_xor_i32(tmp, tmp, tmp2);
674 dead_tmp(tmp2);
cb63669a 675 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 676 break;
677 case 11: /* lt: N != V -> N ^ V != 0 */
678 tmp = load_cpu_field(VF);
6fbe23d5 679 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 680 tcg_gen_xor_i32(tmp, tmp, tmp2);
681 dead_tmp(tmp2);
cb63669a 682 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 683 break;
684 case 12: /* gt: !Z && N == V */
685 inv = gen_new_label();
6fbe23d5 686 tmp = load_cpu_field(ZF);
cb63669a 687 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
d9ba4830
PB		 688 dead_tmp(tmp);
689 tmp = load_cpu_field(VF);
6fbe23d5 690 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 691 tcg_gen_xor_i32(tmp, tmp, tmp2);
692 dead_tmp(tmp2);
cb63669a 693 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
d9ba4830
PB		 694 gen_set_label(inv);
695 break;
696 case 13: /* le: Z || N != V */
6fbe23d5 697 tmp = load_cpu_field(ZF);
cb63669a 698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
d9ba4830
PB		 699 dead_tmp(tmp);
700 tmp = load_cpu_field(VF);
6fbe23d5 701 tmp2 = load_cpu_field(NF);
d9ba4830
PB		 702 tcg_gen_xor_i32(tmp, tmp, tmp2);
703 dead_tmp(tmp2);
cb63669a 704 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
d9ba4830
PB		 705 break;
706 default:
707 fprintf(stderr, "Bad condition code 0x%x\n", cc);
708 abort();
709 }
710 dead_tmp(tmp);
711}
2c0262af 712
b1d8e52e 713static const uint8_t table_logic_cc[16] = {
2c0262af
FB		 714 1, /* and */
715 1, /* xor */
716 0, /* sub */
717 0, /* rsb */
718 0, /* add */
719 0, /* adc */
720 0, /* sbc */
721 0, /* rsc */
722 1, /* andl */
723 1, /* xorl */
724 0, /* cmp */
725 0, /* cmn */
726 1, /* orr */
727 1, /* mov */
728 1, /* bic */
729 1, /* mvn */
730};
3b46e624 731
d9ba4830
PB		 732/* Set PC and Thumb state from an immediate address. */
733static inline void gen_bx_im(DisasContext *s, uint32_t addr)
99c475ab 734{
b26eefb6 735 TCGv tmp;
99c475ab 736
b26eefb6 737 s->is_jmp = DISAS_UPDATE;
d9ba4830 738 if (s->thumb != (addr & 1)) {
155c3eac 739 tmp = new_tmp();
d9ba4830
PB		 740 tcg_gen_movi_i32(tmp, addr & 1);
741 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
155c3eac 742 dead_tmp(tmp);
d9ba4830 743 }
155c3eac 744 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
d9ba4830
PB		 745}
746
747/* Set PC and Thumb state from var. var is marked as dead. */
748static inline void gen_bx(DisasContext *s, TCGv var)
749{
d9ba4830 750 s->is_jmp = DISAS_UPDATE;
155c3eac
FN		 751 tcg_gen_andi_i32(cpu_R[15], var, ~1);
752 tcg_gen_andi_i32(var, var, 1);
753 store_cpu_field(var, thumb);
d9ba4830
PB		 754}
755
21aeb343
JR		 756/* Variant of store_reg which uses branch&exchange logic when storing
757 to r15 in ARM architecture v7 and above. The source must be a temporary
758 and will be marked as dead. */
759static inline void store_reg_bx(CPUState *env, DisasContext *s,
760 int reg, TCGv var)
761{
762 if (reg == 15 && ENABLE_ARCH_7) {
763 gen_bx(s, var);
764 } else {
765 store_reg(s, reg, var);
766 }
767}
768
b0109805
PB		 769static inline TCGv gen_ld8s(TCGv addr, int index)
770{
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8s(tmp, addr, index);
773 return tmp;
774}
775static inline TCGv gen_ld8u(TCGv addr, int index)
776{
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld8u(tmp, addr, index);
779 return tmp;
780}
781static inline TCGv gen_ld16s(TCGv addr, int index)
782{
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16s(tmp, addr, index);
785 return tmp;
786}
787static inline TCGv gen_ld16u(TCGv addr, int index)
788{
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld16u(tmp, addr, index);
791 return tmp;
792}
793static inline TCGv gen_ld32(TCGv addr, int index)
794{
795 TCGv tmp = new_tmp();
796 tcg_gen_qemu_ld32u(tmp, addr, index);
797 return tmp;
798}
84496233
JR		 799static inline TCGv_i64 gen_ld64(TCGv addr, int index)
800{
801 TCGv_i64 tmp = tcg_temp_new_i64();
802 tcg_gen_qemu_ld64(tmp, addr, index);
803 return tmp;
804}
b0109805
PB		 805static inline void gen_st8(TCGv val, TCGv addr, int index)
806{
807 tcg_gen_qemu_st8(val, addr, index);
808 dead_tmp(val);
809}
810static inline void gen_st16(TCGv val, TCGv addr, int index)
811{
812 tcg_gen_qemu_st16(val, addr, index);
813 dead_tmp(val);
814}
815static inline void gen_st32(TCGv val, TCGv addr, int index)
816{
817 tcg_gen_qemu_st32(val, addr, index);
818 dead_tmp(val);
819}
84496233
JR		 820static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
821{
822 tcg_gen_qemu_st64(val, addr, index);
823 tcg_temp_free_i64(val);
824}
b5ff1b31 825
5e3f878a
PB		 826static inline void gen_set_pc_im(uint32_t val)
827{
155c3eac 828 tcg_gen_movi_i32(cpu_R[15], val);
5e3f878a
PB		 829}
830
b5ff1b31
FB		 831/* Force a TB lookup after an instruction that changes the CPU state. */
832static inline void gen_lookup_tb(DisasContext *s)
833{
a6445c52 834 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
b5ff1b31
FB		 835 s->is_jmp = DISAS_UPDATE;
836}
837
b0109805
PB		 838static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
839 TCGv var)
2c0262af 840{
1e8d4eec 841 int val, rm, shift, shiftop;
b26eefb6 842 TCGv offset;
2c0262af
FB		 843
844 if (!(insn & (1 << 25))) {
845 /* immediate */
846 val = insn & 0xfff;
847 if (!(insn & (1 << 23)))
848 val = -val;
537730b9 849 if (val != 0)
b0109805 850 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 851 } else {
852 /* shift/register */
853 rm = (insn) & 0xf;
854 shift = (insn >> 7) & 0x1f;
1e8d4eec 855 shiftop = (insn >> 5) & 3;
b26eefb6 856 offset = load_reg(s, rm);
9a119ff6 857 gen_arm_shift_im(offset, shiftop, shift, 0);
2c0262af 858 if (!(insn & (1 << 23)))
b0109805 859 tcg_gen_sub_i32(var, var, offset);
2c0262af 860 else
b0109805 861 tcg_gen_add_i32(var, var, offset);
b26eefb6 862 dead_tmp(offset);
2c0262af
FB		 863 }
864}
865
191f9a93 866static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
b0109805 867 int extra, TCGv var)
2c0262af
FB		 868{
869 int val, rm;
b26eefb6 870 TCGv offset;
3b46e624 871
2c0262af
FB		 872 if (insn & (1 << 22)) {
873 /* immediate */
874 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
875 if (!(insn & (1 << 23)))
876 val = -val;
18acad92 877 val += extra;
537730b9 878 if (val != 0)
b0109805 879 tcg_gen_addi_i32(var, var, val);
2c0262af
FB		 880 } else {
881 /* register */
191f9a93 882 if (extra)
b0109805 883 tcg_gen_addi_i32(var, var, extra);
2c0262af 884 rm = (insn) & 0xf;
b26eefb6 885 offset = load_reg(s, rm);
2c0262af 886 if (!(insn & (1 << 23)))
b0109805 887 tcg_gen_sub_i32(var, var, offset);
2c0262af 888 else
b0109805 889 tcg_gen_add_i32(var, var, offset);
b26eefb6 890 dead_tmp(offset);
2c0262af
FB		 891 }
892}
893
4373f3ce
PB		 894#define VFP_OP2(name) \
895static inline void gen_vfp_##name(int dp) \
896{ \
897 if (dp) \
898 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 else \
900 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
b7bcbe95
FB		 901}
902
4373f3ce
PB		 903VFP_OP2(add)
904VFP_OP2(sub)
905VFP_OP2(mul)
906VFP_OP2(div)
907
908#undef VFP_OP2
909
910static inline void gen_vfp_abs(int dp)
911{
912 if (dp)
913 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
914 else
915 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
916}
917
918static inline void gen_vfp_neg(int dp)
919{
920 if (dp)
921 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
922 else
923 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
924}
925
926static inline void gen_vfp_sqrt(int dp)
927{
928 if (dp)
929 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
930 else
931 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
932}
933
934static inline void gen_vfp_cmp(int dp)
935{
936 if (dp)
937 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
938 else
939 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
940}
941
942static inline void gen_vfp_cmpe(int dp)
943{
944 if (dp)
945 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
946 else
947 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
948}
949
950static inline void gen_vfp_F1_ld0(int dp)
951{
952 if (dp)
5b340b51 953 tcg_gen_movi_i64(cpu_F1d, 0);
4373f3ce 954 else
5b340b51 955 tcg_gen_movi_i32(cpu_F1s, 0);
4373f3ce
PB		 956}
957
958static inline void gen_vfp_uito(int dp)
959{
960 if (dp)
961 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
962 else
963 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
964}
965
966static inline void gen_vfp_sito(int dp)
967{
968 if (dp)
66230e0d 969 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
4373f3ce 970 else
66230e0d 971 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
4373f3ce
PB		 972}
973
974static inline void gen_vfp_toui(int dp)
975{
976 if (dp)
977 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
980}
981
982static inline void gen_vfp_touiz(int dp)
983{
984 if (dp)
985 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
986 else
987 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
988}
989
990static inline void gen_vfp_tosi(int dp)
991{
992 if (dp)
993 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
994 else
995 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
996}
997
998static inline void gen_vfp_tosiz(int dp)
9ee6e8bb
PB		 999{
1000 if (dp)
4373f3ce 1001 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
9ee6e8bb 1002 else
4373f3ce
PB		 1003 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1004}
1005
1006#define VFP_GEN_FIX(name) \
1007static inline void gen_vfp_##name(int dp, int shift) \
1008{ \
b75263d6 1009 TCGv tmp_shift = tcg_const_i32(shift); \
4373f3ce 1010 if (dp) \
b75263d6 1011 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
4373f3ce 1012 else \
b75263d6
JR		 1013 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1014 tcg_temp_free_i32(tmp_shift); \
9ee6e8bb 1015}
4373f3ce
PB		 1016VFP_GEN_FIX(tosh)
1017VFP_GEN_FIX(tosl)
1018VFP_GEN_FIX(touh)
1019VFP_GEN_FIX(toul)
1020VFP_GEN_FIX(shto)
1021VFP_GEN_FIX(slto)
1022VFP_GEN_FIX(uhto)
1023VFP_GEN_FIX(ulto)
1024#undef VFP_GEN_FIX
9ee6e8bb 1025
312eea9f 1026static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1027{
1028 if (dp)
312eea9f 1029 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1030 else
312eea9f 1031 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1032}
1033
312eea9f 1034static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
b5ff1b31
FB		 1035{
1036 if (dp)
312eea9f 1037 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
b5ff1b31 1038 else
312eea9f 1039 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
b5ff1b31
FB		 1040}
1041
8e96005d
FB		 1042static inline long
1043vfp_reg_offset (int dp, int reg)
1044{
1045 if (dp)
1046 return offsetof(CPUARMState, vfp.regs[reg]);
1047 else if (reg & 1) {
1048 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1049 + offsetof(CPU_DoubleU, l.upper);
1050 } else {
1051 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1052 + offsetof(CPU_DoubleU, l.lower);
1053 }
1054}
9ee6e8bb
PB		 1055
1056/* Return the offset of a 32-bit piece of a NEON register.
1057 zero is the least significant end of the register. */
1058static inline long
1059neon_reg_offset (int reg, int n)
1060{
1061 int sreg;
1062 sreg = reg * 2 + n;
1063 return vfp_reg_offset(0, sreg);
1064}
1065
8f8e3aa4
PB		 1066static TCGv neon_load_reg(int reg, int pass)
1067{
1068 TCGv tmp = new_tmp();
1069 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1070 return tmp;
1071}
1072
1073static void neon_store_reg(int reg, int pass, TCGv var)
1074{
1075 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1076 dead_tmp(var);
1077}
1078
a7812ae4 1079static inline void neon_load_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1080{
1081 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1082}
1083
a7812ae4 1084static inline void neon_store_reg64(TCGv_i64 var, int reg)
ad69471c
PB		 1085{
1086 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1087}
1088
4373f3ce
PB		 1089#define tcg_gen_ld_f32 tcg_gen_ld_i32
1090#define tcg_gen_ld_f64 tcg_gen_ld_i64
1091#define tcg_gen_st_f32 tcg_gen_st_i32
1092#define tcg_gen_st_f64 tcg_gen_st_i64
1093
b7bcbe95
FB		 1094static inline void gen_mov_F0_vreg(int dp, int reg)
1095{
1096 if (dp)
4373f3ce 1097 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1098 else
4373f3ce 1099 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1100}
1101
1102static inline void gen_mov_F1_vreg(int dp, int reg)
1103{
1104 if (dp)
4373f3ce 1105 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1106 else
4373f3ce 1107 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1108}
1109
1110static inline void gen_mov_vreg_F0(int dp, int reg)
1111{
1112 if (dp)
4373f3ce 1113 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95 1114 else
4373f3ce 1115 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
b7bcbe95
FB		 1116}
1117
18c9b560
AZ		 1118#define ARM_CP_RW_BIT (1 << 20)
1119
a7812ae4 1120static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
e677137d
PB		 1121{
1122 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1123}
1124
a7812ae4 1125static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
e677137d
PB		 1126{
1127 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1128}
1129
da6b5335 1130static inline TCGv iwmmxt_load_creg(int reg)
e677137d 1131{
da6b5335
FN		 1132 TCGv var = new_tmp();
1133 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1134 return var;
e677137d
PB		 1135}
1136
da6b5335 1137static inline void iwmmxt_store_creg(int reg, TCGv var)
e677137d 1138{
da6b5335 1139 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
d9968827 1140 dead_tmp(var);
e677137d
PB		 1141}
1142
1143static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1144{
1145 iwmmxt_store_reg(cpu_M0, rn);
1146}
1147
1148static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1149{
1150 iwmmxt_load_reg(cpu_M0, rn);
1151}
1152
1153static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1154{
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1157}
1158
1159static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1160{
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1163}
1164
1165static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1166{
1167 iwmmxt_load_reg(cpu_V1, rn);
1168 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1169}
1170
1171#define IWMMXT_OP(name) \
1172static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173{ \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176}
1177
1178#define IWMMXT_OP_ENV(name) \
1179static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1180{ \
1181 iwmmxt_load_reg(cpu_V1, rn); \
1182 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183}
1184
1185#define IWMMXT_OP_ENV_SIZE(name) \
1186IWMMXT_OP_ENV(name##b) \
1187IWMMXT_OP_ENV(name##w) \
1188IWMMXT_OP_ENV(name##l)
1189
1190#define IWMMXT_OP_ENV1(name) \
1191static inline void gen_op_iwmmxt_##name##_M0(void) \
1192{ \
1193 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1194}
1195
1196IWMMXT_OP(maddsq)
1197IWMMXT_OP(madduq)
1198IWMMXT_OP(sadb)
1199IWMMXT_OP(sadw)
1200IWMMXT_OP(mulslw)
1201IWMMXT_OP(mulshw)
1202IWMMXT_OP(mululw)
1203IWMMXT_OP(muluhw)
1204IWMMXT_OP(macsw)
1205IWMMXT_OP(macuw)
1206
1207IWMMXT_OP_ENV_SIZE(unpackl)
1208IWMMXT_OP_ENV_SIZE(unpackh)
1209
1210IWMMXT_OP_ENV1(unpacklub)
1211IWMMXT_OP_ENV1(unpackluw)
1212IWMMXT_OP_ENV1(unpacklul)
1213IWMMXT_OP_ENV1(unpackhub)
1214IWMMXT_OP_ENV1(unpackhuw)
1215IWMMXT_OP_ENV1(unpackhul)
1216IWMMXT_OP_ENV1(unpacklsb)
1217IWMMXT_OP_ENV1(unpacklsw)
1218IWMMXT_OP_ENV1(unpacklsl)
1219IWMMXT_OP_ENV1(unpackhsb)
1220IWMMXT_OP_ENV1(unpackhsw)
1221IWMMXT_OP_ENV1(unpackhsl)
1222
1223IWMMXT_OP_ENV_SIZE(cmpeq)
1224IWMMXT_OP_ENV_SIZE(cmpgtu)
1225IWMMXT_OP_ENV_SIZE(cmpgts)
1226
1227IWMMXT_OP_ENV_SIZE(mins)
1228IWMMXT_OP_ENV_SIZE(minu)
1229IWMMXT_OP_ENV_SIZE(maxs)
1230IWMMXT_OP_ENV_SIZE(maxu)
1231
1232IWMMXT_OP_ENV_SIZE(subn)
1233IWMMXT_OP_ENV_SIZE(addn)
1234IWMMXT_OP_ENV_SIZE(subu)
1235IWMMXT_OP_ENV_SIZE(addu)
1236IWMMXT_OP_ENV_SIZE(subs)
1237IWMMXT_OP_ENV_SIZE(adds)
1238
1239IWMMXT_OP_ENV(avgb0)
1240IWMMXT_OP_ENV(avgb1)
1241IWMMXT_OP_ENV(avgw0)
1242IWMMXT_OP_ENV(avgw1)
1243
1244IWMMXT_OP(msadb)
1245
1246IWMMXT_OP_ENV(packuw)
1247IWMMXT_OP_ENV(packul)
1248IWMMXT_OP_ENV(packuq)
1249IWMMXT_OP_ENV(packsw)
1250IWMMXT_OP_ENV(packsl)
1251IWMMXT_OP_ENV(packsq)
1252
e677137d
PB		 1253static void gen_op_iwmmxt_set_mup(void)
1254{
1255 TCGv tmp;
1256 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1257 tcg_gen_ori_i32(tmp, tmp, 2);
1258 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259}
1260
1261static void gen_op_iwmmxt_set_cup(void)
1262{
1263 TCGv tmp;
1264 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1265 tcg_gen_ori_i32(tmp, tmp, 1);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1267}
1268
1269static void gen_op_iwmmxt_setpsr_nz(void)
1270{
1271 TCGv tmp = new_tmp();
1272 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1273 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1274}
1275
1276static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1277{
1278 iwmmxt_load_reg(cpu_V1, rn);
86831435 1279 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
e677137d
PB		 1280 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1281}
1282
da6b5335 1283static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
18c9b560
AZ		 1284{
1285 int rd;
1286 uint32_t offset;
da6b5335 1287 TCGv tmp;
18c9b560
AZ		 1288
1289 rd = (insn >> 16) & 0xf;
da6b5335 1290 tmp = load_reg(s, rd);
18c9b560
AZ		 1291
1292 offset = (insn & 0xff) << ((insn >> 7) & 2);
1293 if (insn & (1 << 24)) {
1294 /* Pre indexed */
1295 if (insn & (1 << 23))
da6b5335 1296 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1297 else
da6b5335
FN		 1298 tcg_gen_addi_i32(tmp, tmp, -offset);
1299 tcg_gen_mov_i32(dest, tmp);
18c9b560 1300 if (insn & (1 << 21))
da6b5335
FN		 1301 store_reg(s, rd, tmp);
1302 else
1303 dead_tmp(tmp);
18c9b560
AZ		 1304 } else if (insn & (1 << 21)) {
1305 /* Post indexed */
da6b5335 1306 tcg_gen_mov_i32(dest, tmp);
18c9b560 1307 if (insn & (1 << 23))
da6b5335 1308 tcg_gen_addi_i32(tmp, tmp, offset);
18c9b560 1309 else
da6b5335
FN		 1310 tcg_gen_addi_i32(tmp, tmp, -offset);
1311 store_reg(s, rd, tmp);
18c9b560
AZ		 1312 } else if (!(insn & (1 << 23)))
1313 return 1;
1314 return 0;
1315}
1316
da6b5335 1317static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
18c9b560
AZ		 1318{
1319 int rd = (insn >> 0) & 0xf;
da6b5335 1320 TCGv tmp;
18c9b560 1321
da6b5335
FN		 1322 if (insn & (1 << 8)) {
1323 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
18c9b560 1324 return 1;
da6b5335
FN		 1325 } else {
1326 tmp = iwmmxt_load_creg(rd);
1327 }
1328 } else {
1329 tmp = new_tmp();
1330 iwmmxt_load_reg(cpu_V0, rd);
1331 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1332 }
1333 tcg_gen_andi_i32(tmp, tmp, mask);
1334 tcg_gen_mov_i32(dest, tmp);
1335 dead_tmp(tmp);
18c9b560
AZ		 1336 return 0;
1337}
1338
1339/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1340 (ie. an undefined instruction). */
1341static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1342{
1343 int rd, wrd;
1344 int rdhi, rdlo, rd0, rd1, i;
da6b5335
FN		 1345 TCGv addr;
1346 TCGv tmp, tmp2, tmp3;
18c9b560
AZ		 1347
1348 if ((insn & 0x0e000e00) == 0x0c000000) {
1349 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1350 wrd = insn & 0xf;
1351 rdlo = (insn >> 12) & 0xf;
1352 rdhi = (insn >> 16) & 0xf;
1353 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
da6b5335
FN		 1354 iwmmxt_load_reg(cpu_V0, wrd);
1355 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1356 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1357 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
18c9b560 1358 } else { /* TMCRR */
da6b5335
FN		 1359 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1360 iwmmxt_store_reg(cpu_V0, wrd);
18c9b560
AZ		 1361 gen_op_iwmmxt_set_mup();
1362 }
1363 return 0;
1364 }
1365
1366 wrd = (insn >> 12) & 0xf;
da6b5335
FN		 1367 addr = new_tmp();
1368 if (gen_iwmmxt_address(s, insn, addr)) {
1369 dead_tmp(addr);
18c9b560 1370 return 1;
da6b5335 1371 }
18c9b560
AZ		 1372 if (insn & ARM_CP_RW_BIT) {
1373 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
da6b5335
FN		 1374 tmp = new_tmp();
1375 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1376 iwmmxt_store_creg(wrd, tmp);
18c9b560 1377 } else {
e677137d
PB		 1378 i = 1;
1379 if (insn & (1 << 8)) {
1380 if (insn & (1 << 22)) { /* WLDRD */
da6b5335 1381 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1382 i = 0;
1383 } else { /* WLDRW wRd */
da6b5335 1384 tmp = gen_ld32(addr, IS_USER(s));
e677137d
PB		 1385 }
1386 } else {
1387 if (insn & (1 << 22)) { /* WLDRH */
da6b5335 1388 tmp = gen_ld16u(addr, IS_USER(s));
e677137d 1389 } else { /* WLDRB */
da6b5335 1390 tmp = gen_ld8u(addr, IS_USER(s));
e677137d
PB		 1391 }
1392 }
1393 if (i) {
1394 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1395 dead_tmp(tmp);
1396 }
18c9b560
AZ		 1397 gen_op_iwmmxt_movq_wRn_M0(wrd);
1398 }
1399 } else {
1400 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
da6b5335
FN		 1401 tmp = iwmmxt_load_creg(wrd);
1402 gen_st32(tmp, addr, IS_USER(s));
18c9b560
AZ		 1403 } else {
1404 gen_op_iwmmxt_movq_M0_wRn(wrd);
e677137d
PB		 1405 tmp = new_tmp();
1406 if (insn & (1 << 8)) {
1407 if (insn & (1 << 22)) { /* WSTRD */
1408 dead_tmp(tmp);
da6b5335 1409 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
e677137d
PB		 1410 } else { /* WSTRW wRd */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1412 gen_st32(tmp, addr, IS_USER(s));
e677137d
PB		 1413 }
1414 } else {
1415 if (insn & (1 << 22)) { /* WSTRH */
1416 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1417 gen_st16(tmp, addr, IS_USER(s));
e677137d
PB		 1418 } else { /* WSTRB */
1419 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
da6b5335 1420 gen_st8(tmp, addr, IS_USER(s));
e677137d
PB		 1421 }
1422 }
18c9b560
AZ		 1423 }
1424 }
d9968827 1425 dead_tmp(addr);
18c9b560
AZ		 1426 return 0;
1427 }
1428
1429 if ((insn & 0x0f000000) != 0x0e000000)
1430 return 1;
1431
1432 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1433 case 0x000: /* WOR */
1434 wrd = (insn >> 12) & 0xf;
1435 rd0 = (insn >> 0) & 0xf;
1436 rd1 = (insn >> 16) & 0xf;
1437 gen_op_iwmmxt_movq_M0_wRn(rd0);
1438 gen_op_iwmmxt_orq_M0_wRn(rd1);
1439 gen_op_iwmmxt_setpsr_nz();
1440 gen_op_iwmmxt_movq_wRn_M0(wrd);
1441 gen_op_iwmmxt_set_mup();
1442 gen_op_iwmmxt_set_cup();
1443 break;
1444 case 0x011: /* TMCR */
1445 if (insn & 0xf)
1446 return 1;
1447 rd = (insn >> 12) & 0xf;
1448 wrd = (insn >> 16) & 0xf;
1449 switch (wrd) {
1450 case ARM_IWMMXT_wCID:
1451 case ARM_IWMMXT_wCASF:
1452 break;
1453 case ARM_IWMMXT_wCon:
1454 gen_op_iwmmxt_set_cup();
1455 /* Fall through. */
1456 case ARM_IWMMXT_wCSSF:
da6b5335
FN		 1457 tmp = iwmmxt_load_creg(wrd);
1458 tmp2 = load_reg(s, rd);
f669df27 1459 tcg_gen_andc_i32(tmp, tmp, tmp2);
da6b5335
FN		 1460 dead_tmp(tmp2);
1461 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1462 break;
1463 case ARM_IWMMXT_wCGR0:
1464 case ARM_IWMMXT_wCGR1:
1465 case ARM_IWMMXT_wCGR2:
1466 case ARM_IWMMXT_wCGR3:
1467 gen_op_iwmmxt_set_cup();
da6b5335
FN		 1468 tmp = load_reg(s, rd);
1469 iwmmxt_store_creg(wrd, tmp);
18c9b560
AZ		 1470 break;
1471 default:
1472 return 1;
1473 }
1474 break;
1475 case 0x100: /* WXOR */
1476 wrd = (insn >> 12) & 0xf;
1477 rd0 = (insn >> 0) & 0xf;
1478 rd1 = (insn >> 16) & 0xf;
1479 gen_op_iwmmxt_movq_M0_wRn(rd0);
1480 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1481 gen_op_iwmmxt_setpsr_nz();
1482 gen_op_iwmmxt_movq_wRn_M0(wrd);
1483 gen_op_iwmmxt_set_mup();
1484 gen_op_iwmmxt_set_cup();
1485 break;
1486 case 0x111: /* TMRC */
1487 if (insn & 0xf)
1488 return 1;
1489 rd = (insn >> 12) & 0xf;
1490 wrd = (insn >> 16) & 0xf;
da6b5335
FN		 1491 tmp = iwmmxt_load_creg(wrd);
1492 store_reg(s, rd, tmp);
18c9b560
AZ		 1493 break;
1494 case 0x300: /* WANDN */
1495 wrd = (insn >> 12) & 0xf;
1496 rd0 = (insn >> 0) & 0xf;
1497 rd1 = (insn >> 16) & 0xf;
1498 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d 1499 tcg_gen_neg_i64(cpu_M0, cpu_M0);
18c9b560
AZ		 1500 gen_op_iwmmxt_andq_M0_wRn(rd1);
1501 gen_op_iwmmxt_setpsr_nz();
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 gen_op_iwmmxt_set_mup();
1504 gen_op_iwmmxt_set_cup();
1505 break;
1506 case 0x200: /* WAND */
1507 wrd = (insn >> 12) & 0xf;
1508 rd0 = (insn >> 0) & 0xf;
1509 rd1 = (insn >> 16) & 0xf;
1510 gen_op_iwmmxt_movq_M0_wRn(rd0);
1511 gen_op_iwmmxt_andq_M0_wRn(rd1);
1512 gen_op_iwmmxt_setpsr_nz();
1513 gen_op_iwmmxt_movq_wRn_M0(wrd);
1514 gen_op_iwmmxt_set_mup();
1515 gen_op_iwmmxt_set_cup();
1516 break;
1517 case 0x810: case 0xa10: /* WMADD */
1518 wrd = (insn >> 12) & 0xf;
1519 rd0 = (insn >> 0) & 0xf;
1520 rd1 = (insn >> 16) & 0xf;
1521 gen_op_iwmmxt_movq_M0_wRn(rd0);
1522 if (insn & (1 << 21))
1523 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1524 else
1525 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1526 gen_op_iwmmxt_movq_wRn_M0(wrd);
1527 gen_op_iwmmxt_set_mup();
1528 break;
1529 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1530 wrd = (insn >> 12) & 0xf;
1531 rd0 = (insn >> 16) & 0xf;
1532 rd1 = (insn >> 0) & 0xf;
1533 gen_op_iwmmxt_movq_M0_wRn(rd0);
1534 switch ((insn >> 22) & 3) {
1535 case 0:
1536 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1537 break;
1538 case 1:
1539 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1540 break;
1541 case 2:
1542 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1543 break;
1544 case 3:
1545 return 1;
1546 }
1547 gen_op_iwmmxt_movq_wRn_M0(wrd);
1548 gen_op_iwmmxt_set_mup();
1549 gen_op_iwmmxt_set_cup();
1550 break;
1551 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1552 wrd = (insn >> 12) & 0xf;
1553 rd0 = (insn >> 16) & 0xf;
1554 rd1 = (insn >> 0) & 0xf;
1555 gen_op_iwmmxt_movq_M0_wRn(rd0);
1556 switch ((insn >> 22) & 3) {
1557 case 0:
1558 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1559 break;
1560 case 1:
1561 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1562 break;
1563 case 2:
1564 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1565 break;
1566 case 3:
1567 return 1;
1568 }
1569 gen_op_iwmmxt_movq_wRn_M0(wrd);
1570 gen_op_iwmmxt_set_mup();
1571 gen_op_iwmmxt_set_cup();
1572 break;
1573 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 16) & 0xf;
1576 rd1 = (insn >> 0) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 if (insn & (1 << 22))
1579 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1580 else
1581 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1582 if (!(insn & (1 << 20)))
1583 gen_op_iwmmxt_addl_M0_wRn(wrd);
1584 gen_op_iwmmxt_movq_wRn_M0(wrd);
1585 gen_op_iwmmxt_set_mup();
1586 break;
1587 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1588 wrd = (insn >> 12) & 0xf;
1589 rd0 = (insn >> 16) & 0xf;
1590 rd1 = (insn >> 0) & 0xf;
1591 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1592 if (insn & (1 << 21)) {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1597 } else {
1598 if (insn & (1 << 20))
1599 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1600 else
1601 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1602 }
18c9b560
AZ		 1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 if (insn & (1 << 21))
1612 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1613 else
1614 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1615 if (!(insn & (1 << 20))) {
e677137d
PB		 1616 iwmmxt_load_reg(cpu_V1, wrd);
1617 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
18c9b560
AZ		 1618 }
1619 gen_op_iwmmxt_movq_wRn_M0(wrd);
1620 gen_op_iwmmxt_set_mup();
1621 break;
1622 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 16) & 0xf;
1625 rd1 = (insn >> 0) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 switch ((insn >> 22) & 3) {
1628 case 0:
1629 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1630 break;
1631 case 1:
1632 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1633 break;
1634 case 2:
1635 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1636 break;
1637 case 3:
1638 return 1;
1639 }
1640 gen_op_iwmmxt_movq_wRn_M0(wrd);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1643 break;
1644 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1645 wrd = (insn >> 12) & 0xf;
1646 rd0 = (insn >> 16) & 0xf;
1647 rd1 = (insn >> 0) & 0xf;
1648 gen_op_iwmmxt_movq_M0_wRn(rd0);
e677137d
PB		 1649 if (insn & (1 << 22)) {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1654 } else {
1655 if (insn & (1 << 20))
1656 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1657 else
1658 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1659 }
18c9b560
AZ		 1660 gen_op_iwmmxt_movq_wRn_M0(wrd);
1661 gen_op_iwmmxt_set_mup();
1662 gen_op_iwmmxt_set_cup();
1663 break;
1664 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1665 wrd = (insn >> 12) & 0xf;
1666 rd0 = (insn >> 16) & 0xf;
1667 rd1 = (insn >> 0) & 0xf;
1668 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1669 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1670 tcg_gen_andi_i32(tmp, tmp, 7);
1671 iwmmxt_load_reg(cpu_V1, rd1);
1672 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1673 dead_tmp(tmp);
18c9b560
AZ		 1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 break;
1677 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
da6b5335
FN		 1678 if (((insn >> 6) & 3) == 3)
1679 return 1;
18c9b560
AZ		 1680 rd = (insn >> 12) & 0xf;
1681 wrd = (insn >> 16) & 0xf;
da6b5335 1682 tmp = load_reg(s, rd);
18c9b560
AZ		 1683 gen_op_iwmmxt_movq_M0_wRn(wrd);
1684 switch ((insn >> 6) & 3) {
1685 case 0:
da6b5335
FN		 1686 tmp2 = tcg_const_i32(0xff);
1687 tmp3 = tcg_const_i32((insn & 7) << 3);
18c9b560
AZ		 1688 break;
1689 case 1:
da6b5335
FN		 1690 tmp2 = tcg_const_i32(0xffff);
1691 tmp3 = tcg_const_i32((insn & 3) << 4);
18c9b560
AZ		 1692 break;
1693 case 2:
da6b5335
FN		 1694 tmp2 = tcg_const_i32(0xffffffff);
1695 tmp3 = tcg_const_i32((insn & 1) << 5);
18c9b560 1696 break;
da6b5335
FN		 1697 default:
1698 TCGV_UNUSED(tmp2);
1699 TCGV_UNUSED(tmp3);
18c9b560 1700 }
da6b5335
FN		 1701 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1702 tcg_temp_free(tmp3);
1703 tcg_temp_free(tmp2);
1704 dead_tmp(tmp);
18c9b560
AZ		 1705 gen_op_iwmmxt_movq_wRn_M0(wrd);
1706 gen_op_iwmmxt_set_mup();
1707 break;
1708 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1709 rd = (insn >> 12) & 0xf;
1710 wrd = (insn >> 16) & 0xf;
da6b5335 1711 if (rd == 15 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1712 return 1;
1713 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335 1714 tmp = new_tmp();
18c9b560
AZ		 1715 switch ((insn >> 22) & 3) {
1716 case 0:
da6b5335
FN		 1717 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1718 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1719 if (insn & 8) {
1720 tcg_gen_ext8s_i32(tmp, tmp);
1721 } else {
1722 tcg_gen_andi_i32(tmp, tmp, 0xff);
18c9b560
AZ		 1723 }
1724 break;
1725 case 1:
da6b5335
FN		 1726 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1727 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1728 if (insn & 8) {
1729 tcg_gen_ext16s_i32(tmp, tmp);
1730 } else {
1731 tcg_gen_andi_i32(tmp, tmp, 0xffff);
18c9b560
AZ		 1732 }
1733 break;
1734 case 2:
da6b5335
FN		 1735 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1736 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
18c9b560 1737 break;
18c9b560 1738 }
da6b5335 1739 store_reg(s, rd, tmp);
18c9b560
AZ		 1740 break;
1741 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
da6b5335 1742 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1743 return 1;
da6b5335 1744 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
18c9b560
AZ		 1745 switch ((insn >> 22) & 3) {
1746 case 0:
da6b5335 1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
18c9b560
AZ		 1748 break;
1749 case 1:
da6b5335 1750 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
18c9b560
AZ		 1751 break;
1752 case 2:
da6b5335 1753 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
18c9b560 1754 break;
18c9b560 1755 }
da6b5335
FN		 1756 tcg_gen_shli_i32(tmp, tmp, 28);
1757 gen_set_nzcv(tmp);
1758 dead_tmp(tmp);
18c9b560
AZ		 1759 break;
1760 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
da6b5335
FN		 1761 if (((insn >> 6) & 3) == 3)
1762 return 1;
18c9b560
AZ		 1763 rd = (insn >> 12) & 0xf;
1764 wrd = (insn >> 16) & 0xf;
da6b5335 1765 tmp = load_reg(s, rd);
18c9b560
AZ		 1766 switch ((insn >> 6) & 3) {
1767 case 0:
da6b5335 1768 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
18c9b560
AZ		 1769 break;
1770 case 1:
da6b5335 1771 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
18c9b560
AZ		 1772 break;
1773 case 2:
da6b5335 1774 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
18c9b560 1775 break;
18c9b560 1776 }
da6b5335 1777 dead_tmp(tmp);
18c9b560
AZ		 1778 gen_op_iwmmxt_movq_wRn_M0(wrd);
1779 gen_op_iwmmxt_set_mup();
1780 break;
1781 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
da6b5335 1782 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1783 return 1;
da6b5335
FN		 1784 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1785 tmp2 = new_tmp();
1786 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1787 switch ((insn >> 22) & 3) {
1788 case 0:
1789 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1790 tcg_gen_shli_i32(tmp2, tmp2, 4);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1792 }
1793 break;
1794 case 1:
1795 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1796 tcg_gen_shli_i32(tmp2, tmp2, 8);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1798 }
1799 break;
1800 case 2:
da6b5335
FN		 1801 tcg_gen_shli_i32(tmp2, tmp2, 16);
1802 tcg_gen_and_i32(tmp, tmp, tmp2);
18c9b560 1803 break;
18c9b560 1804 }
da6b5335
FN		 1805 gen_set_nzcv(tmp);
1806 dead_tmp(tmp2);
1807 dead_tmp(tmp);
18c9b560
AZ		 1808 break;
1809 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 16) & 0xf;
1812 gen_op_iwmmxt_movq_M0_wRn(rd0);
1813 switch ((insn >> 22) & 3) {
1814 case 0:
e677137d 1815 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
18c9b560
AZ		 1816 break;
1817 case 1:
e677137d 1818 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
18c9b560
AZ		 1819 break;
1820 case 2:
e677137d 1821 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
18c9b560
AZ		 1822 break;
1823 case 3:
1824 return 1;
1825 }
1826 gen_op_iwmmxt_movq_wRn_M0(wrd);
1827 gen_op_iwmmxt_set_mup();
1828 break;
1829 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
da6b5335 1830 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
18c9b560 1831 return 1;
da6b5335
FN		 1832 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1833 tmp2 = new_tmp();
1834 tcg_gen_mov_i32(tmp2, tmp);
18c9b560
AZ		 1835 switch ((insn >> 22) & 3) {
1836 case 0:
1837 for (i = 0; i < 7; i ++) {
da6b5335
FN		 1838 tcg_gen_shli_i32(tmp2, tmp2, 4);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1840 }
1841 break;
1842 case 1:
1843 for (i = 0; i < 3; i ++) {
da6b5335
FN		 1844 tcg_gen_shli_i32(tmp2, tmp2, 8);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560
AZ		 1846 }
1847 break;
1848 case 2:
da6b5335
FN		 1849 tcg_gen_shli_i32(tmp2, tmp2, 16);
1850 tcg_gen_or_i32(tmp, tmp, tmp2);
18c9b560 1851 break;
18c9b560 1852 }
da6b5335
FN		 1853 gen_set_nzcv(tmp);
1854 dead_tmp(tmp2);
1855 dead_tmp(tmp);
18c9b560
AZ		 1856 break;
1857 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1858 rd = (insn >> 12) & 0xf;
1859 rd0 = (insn >> 16) & 0xf;
da6b5335 1860 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
18c9b560
AZ		 1861 return 1;
1862 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 1863 tmp = new_tmp();
18c9b560
AZ		 1864 switch ((insn >> 22) & 3) {
1865 case 0:
da6b5335 1866 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
18c9b560
AZ		 1867 break;
1868 case 1:
da6b5335 1869 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
18c9b560
AZ		 1870 break;
1871 case 2:
da6b5335 1872 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
18c9b560 1873 break;
18c9b560 1874 }
da6b5335 1875 store_reg(s, rd, tmp);
18c9b560
AZ		 1876 break;
1877 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1878 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1879 wrd = (insn >> 12) & 0xf;
1880 rd0 = (insn >> 16) & 0xf;
1881 rd1 = (insn >> 0) & 0xf;
1882 gen_op_iwmmxt_movq_M0_wRn(rd0);
1883 switch ((insn >> 22) & 3) {
1884 case 0:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1889 break;
1890 case 1:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1895 break;
1896 case 2:
1897 if (insn & (1 << 21))
1898 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1899 else
1900 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 gen_op_iwmmxt_set_cup();
1908 break;
1909 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1910 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1911 wrd = (insn >> 12) & 0xf;
1912 rd0 = (insn >> 16) & 0xf;
1913 gen_op_iwmmxt_movq_M0_wRn(rd0);
1914 switch ((insn >> 22) & 3) {
1915 case 0:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsb_M0();
1918 else
1919 gen_op_iwmmxt_unpacklub_M0();
1920 break;
1921 case 1:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsw_M0();
1924 else
1925 gen_op_iwmmxt_unpackluw_M0();
1926 break;
1927 case 2:
1928 if (insn & (1 << 21))
1929 gen_op_iwmmxt_unpacklsl_M0();
1930 else
1931 gen_op_iwmmxt_unpacklul_M0();
1932 break;
1933 case 3:
1934 return 1;
1935 }
1936 gen_op_iwmmxt_movq_wRn_M0(wrd);
1937 gen_op_iwmmxt_set_mup();
1938 gen_op_iwmmxt_set_cup();
1939 break;
1940 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1941 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1942 wrd = (insn >> 12) & 0xf;
1943 rd0 = (insn >> 16) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 switch ((insn >> 22) & 3) {
1946 case 0:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsb_M0();
1949 else
1950 gen_op_iwmmxt_unpackhub_M0();
1951 break;
1952 case 1:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsw_M0();
1955 else
1956 gen_op_iwmmxt_unpackhuw_M0();
1957 break;
1958 case 2:
1959 if (insn & (1 << 21))
1960 gen_op_iwmmxt_unpackhsl_M0();
1961 else
1962 gen_op_iwmmxt_unpackhul_M0();
1963 break;
1964 case 3:
1965 return 1;
1966 }
1967 gen_op_iwmmxt_movq_wRn_M0(wrd);
1968 gen_op_iwmmxt_set_mup();
1969 gen_op_iwmmxt_set_cup();
1970 break;
1971 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1972 case 0x214: case 0x614: case 0xa14: case 0xe14:
da6b5335
FN		 1973 if (((insn >> 22) & 3) == 0)
1974 return 1;
18c9b560
AZ		 1975 wrd = (insn >> 12) & 0xf;
1976 rd0 = (insn >> 16) & 0xf;
1977 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 1978 tmp = new_tmp();
1979 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1980 dead_tmp(tmp);
18c9b560 1981 return 1;
da6b5335 1982 }
18c9b560 1983 switch ((insn >> 22) & 3) {
18c9b560 1984 case 1:
da6b5335 1985 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1986 break;
1987 case 2:
da6b5335 1988 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1989 break;
1990 case 3:
da6b5335 1991 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 1992 break;
1993 }
da6b5335 1994 dead_tmp(tmp);
18c9b560
AZ		 1995 gen_op_iwmmxt_movq_wRn_M0(wrd);
1996 gen_op_iwmmxt_set_mup();
1997 gen_op_iwmmxt_set_cup();
1998 break;
1999 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2000 case 0x014: case 0x414: case 0x814: case 0xc14:
da6b5335
FN		 2001 if (((insn >> 22) & 3) == 0)
2002 return 1;
18c9b560
AZ		 2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2006 tmp = new_tmp();
2007 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2008 dead_tmp(tmp);
18c9b560 2009 return 1;
da6b5335 2010 }
18c9b560 2011 switch ((insn >> 22) & 3) {
18c9b560 2012 case 1:
da6b5335 2013 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2014 break;
2015 case 2:
da6b5335 2016 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2017 break;
2018 case 3:
da6b5335 2019 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2020 break;
2021 }
da6b5335 2022 dead_tmp(tmp);
18c9b560
AZ		 2023 gen_op_iwmmxt_movq_wRn_M0(wrd);
2024 gen_op_iwmmxt_set_mup();
2025 gen_op_iwmmxt_set_cup();
2026 break;
2027 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2028 case 0x114: case 0x514: case 0x914: case 0xd14:
da6b5335
FN		 2029 if (((insn >> 22) & 3) == 0)
2030 return 1;
18c9b560
AZ		 2031 wrd = (insn >> 12) & 0xf;
2032 rd0 = (insn >> 16) & 0xf;
2033 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2034 tmp = new_tmp();
2035 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2036 dead_tmp(tmp);
18c9b560 2037 return 1;
da6b5335 2038 }
18c9b560 2039 switch ((insn >> 22) & 3) {
18c9b560 2040 case 1:
da6b5335 2041 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2042 break;
2043 case 2:
da6b5335 2044 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2045 break;
2046 case 3:
da6b5335 2047 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2048 break;
2049 }
da6b5335 2050 dead_tmp(tmp);
18c9b560
AZ		 2051 gen_op_iwmmxt_movq_wRn_M0(wrd);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2054 break;
2055 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2056 case 0x314: case 0x714: case 0xb14: case 0xf14:
da6b5335
FN		 2057 if (((insn >> 22) & 3) == 0)
2058 return 1;
18c9b560
AZ		 2059 wrd = (insn >> 12) & 0xf;
2060 rd0 = (insn >> 16) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335 2062 tmp = new_tmp();
18c9b560 2063 switch ((insn >> 22) & 3) {
18c9b560 2064 case 1:
da6b5335
FN		 2065 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2066 dead_tmp(tmp);
18c9b560 2067 return 1;
da6b5335
FN		 2068 }
2069 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2070 break;
2071 case 2:
da6b5335
FN		 2072 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2073 dead_tmp(tmp);
18c9b560 2074 return 1;
da6b5335
FN		 2075 }
2076 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2077 break;
2078 case 3:
da6b5335
FN		 2079 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2080 dead_tmp(tmp);
18c9b560 2081 return 1;
da6b5335
FN		 2082 }
2083 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
18c9b560
AZ		 2084 break;
2085 }
da6b5335 2086 dead_tmp(tmp);
18c9b560
AZ		 2087 gen_op_iwmmxt_movq_wRn_M0(wrd);
2088 gen_op_iwmmxt_set_mup();
2089 gen_op_iwmmxt_set_cup();
2090 break;
2091 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2092 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2093 wrd = (insn >> 12) & 0xf;
2094 rd0 = (insn >> 16) & 0xf;
2095 rd1 = (insn >> 0) & 0xf;
2096 gen_op_iwmmxt_movq_M0_wRn(rd0);
2097 switch ((insn >> 22) & 3) {
2098 case 0:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minub_M0_wRn(rd1);
2103 break;
2104 case 1:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2109 break;
2110 case 2:
2111 if (insn & (1 << 21))
2112 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2113 else
2114 gen_op_iwmmxt_minul_M0_wRn(rd1);
2115 break;
2116 case 3:
2117 return 1;
2118 }
2119 gen_op_iwmmxt_movq_wRn_M0(wrd);
2120 gen_op_iwmmxt_set_mup();
2121 break;
2122 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2123 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2124 wrd = (insn >> 12) & 0xf;
2125 rd0 = (insn >> 16) & 0xf;
2126 rd1 = (insn >> 0) & 0xf;
2127 gen_op_iwmmxt_movq_M0_wRn(rd0);
2128 switch ((insn >> 22) & 3) {
2129 case 0:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2134 break;
2135 case 1:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2140 break;
2141 case 2:
2142 if (insn & (1 << 21))
2143 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2144 else
2145 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2146 break;
2147 case 3:
2148 return 1;
2149 }
2150 gen_op_iwmmxt_movq_wRn_M0(wrd);
2151 gen_op_iwmmxt_set_mup();
2152 break;
2153 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2154 case 0x402: case 0x502: case 0x602: case 0x702:
2155 wrd = (insn >> 12) & 0xf;
2156 rd0 = (insn >> 16) & 0xf;
2157 rd1 = (insn >> 0) & 0xf;
2158 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2159 tmp = tcg_const_i32((insn >> 20) & 3);
2160 iwmmxt_load_reg(cpu_V1, rd1);
2161 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2162 tcg_temp_free(tmp);
18c9b560
AZ		 2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 break;
2166 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2167 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2168 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2169 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2170 wrd = (insn >> 12) & 0xf;
2171 rd0 = (insn >> 16) & 0xf;
2172 rd1 = (insn >> 0) & 0xf;
2173 gen_op_iwmmxt_movq_M0_wRn(rd0);
2174 switch ((insn >> 20) & 0xf) {
2175 case 0x0:
2176 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2177 break;
2178 case 0x1:
2179 gen_op_iwmmxt_subub_M0_wRn(rd1);
2180 break;
2181 case 0x3:
2182 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2183 break;
2184 case 0x4:
2185 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2186 break;
2187 case 0x5:
2188 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2189 break;
2190 case 0x7:
2191 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2192 break;
2193 case 0x8:
2194 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2195 break;
2196 case 0x9:
2197 gen_op_iwmmxt_subul_M0_wRn(rd1);
2198 break;
2199 case 0xb:
2200 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2201 break;
2202 default:
2203 return 1;
2204 }
2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
2206 gen_op_iwmmxt_set_mup();
2207 gen_op_iwmmxt_set_cup();
2208 break;
2209 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2210 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2211 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2212 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 gen_op_iwmmxt_movq_M0_wRn(rd0);
da6b5335
FN		 2216 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2217 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2218 tcg_temp_free(tmp);
18c9b560
AZ		 2219 gen_op_iwmmxt_movq_wRn_M0(wrd);
2220 gen_op_iwmmxt_set_mup();
2221 gen_op_iwmmxt_set_cup();
2222 break;
2223 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2224 case 0x418: case 0x518: case 0x618: case 0x718:
2225 case 0x818: case 0x918: case 0xa18: case 0xb18:
2226 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2227 wrd = (insn >> 12) & 0xf;
2228 rd0 = (insn >> 16) & 0xf;
2229 rd1 = (insn >> 0) & 0xf;
2230 gen_op_iwmmxt_movq_M0_wRn(rd0);
2231 switch ((insn >> 20) & 0xf) {
2232 case 0x0:
2233 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2234 break;
2235 case 0x1:
2236 gen_op_iwmmxt_addub_M0_wRn(rd1);
2237 break;
2238 case 0x3:
2239 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2240 break;
2241 case 0x4:
2242 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2243 break;
2244 case 0x5:
2245 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2246 break;
2247 case 0x7:
2248 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2249 break;
2250 case 0x8:
2251 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2252 break;
2253 case 0x9:
2254 gen_op_iwmmxt_addul_M0_wRn(rd1);
2255 break;
2256 case 0xb:
2257 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2258 break;
2259 default:
2260 return 1;
2261 }
2262 gen_op_iwmmxt_movq_wRn_M0(wrd);
2263 gen_op_iwmmxt_set_mup();
2264 gen_op_iwmmxt_set_cup();
2265 break;
2266 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2267 case 0x408: case 0x508: case 0x608: case 0x708:
2268 case 0x808: case 0x908: case 0xa08: case 0xb08:
2269 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
da6b5335
FN		 2270 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2271 return 1;
18c9b560
AZ		 2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
18c9b560 2276 switch ((insn >> 22) & 3) {
18c9b560
AZ		 2277 case 1:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2282 break;
2283 case 2:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packul_M0_wRn(rd1);
2288 break;
2289 case 3:
2290 if (insn & (1 << 21))
2291 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2292 else
2293 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2294 break;
2295 }
2296 gen_op_iwmmxt_movq_wRn_M0(wrd);
2297 gen_op_iwmmxt_set_mup();
2298 gen_op_iwmmxt_set_cup();
2299 break;
2300 case 0x201: case 0x203: case 0x205: case 0x207:
2301 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2302 case 0x211: case 0x213: case 0x215: case 0x217:
2303 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2304 wrd = (insn >> 5) & 0xf;
2305 rd0 = (insn >> 12) & 0xf;
2306 rd1 = (insn >> 0) & 0xf;
2307 if (rd0 == 0xf || rd1 == 0xf)
2308 return 1;
2309 gen_op_iwmmxt_movq_M0_wRn(wrd);
da6b5335
FN		 2310 tmp = load_reg(s, rd0);
2311 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2312 switch ((insn >> 16) & 0xf) {
2313 case 0x0: /* TMIA */
da6b5335 2314 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2315 break;
2316 case 0x8: /* TMIAPH */
da6b5335 2317 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2318 break;
2319 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
18c9b560 2320 if (insn & (1 << 16))
da6b5335 2321 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2322 if (insn & (1 << 17))
da6b5335
FN		 2323 tcg_gen_shri_i32(tmp2, tmp2, 16);
2324 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2325 break;
2326 default:
da6b5335
FN		 2327 dead_tmp(tmp2);
2328 dead_tmp(tmp);
18c9b560
AZ		 2329 return 1;
2330 }
da6b5335
FN		 2331 dead_tmp(tmp2);
2332 dead_tmp(tmp);
18c9b560
AZ		 2333 gen_op_iwmmxt_movq_wRn_M0(wrd);
2334 gen_op_iwmmxt_set_mup();
2335 break;
2336 default:
2337 return 1;
2338 }
2339
2340 return 0;
2341}
2342
2343/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2344 (ie. an undefined instruction). */
2345static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2346{
2347 int acc, rd0, rd1, rdhi, rdlo;
3a554c0f 2348 TCGv tmp, tmp2;
18c9b560
AZ		 2349
2350 if ((insn & 0x0ff00f10) == 0x0e200010) {
2351 /* Multiply with Internal Accumulate Format */
2352 rd0 = (insn >> 12) & 0xf;
2353 rd1 = insn & 0xf;
2354 acc = (insn >> 5) & 7;
2355
2356 if (acc != 0)
2357 return 1;
2358
3a554c0f
FN		 2359 tmp = load_reg(s, rd0);
2360 tmp2 = load_reg(s, rd1);
18c9b560
AZ		 2361 switch ((insn >> 16) & 0xf) {
2362 case 0x0: /* MIA */
3a554c0f 2363 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2364 break;
2365 case 0x8: /* MIAPH */
3a554c0f 2366 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2367 break;
2368 case 0xc: /* MIABB */
2369 case 0xd: /* MIABT */
2370 case 0xe: /* MIATB */
2371 case 0xf: /* MIATT */
18c9b560 2372 if (insn & (1 << 16))
3a554c0f 2373 tcg_gen_shri_i32(tmp, tmp, 16);
18c9b560 2374 if (insn & (1 << 17))
3a554c0f
FN		 2375 tcg_gen_shri_i32(tmp2, tmp2, 16);
2376 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
18c9b560
AZ		 2377 break;
2378 default:
2379 return 1;
2380 }
3a554c0f
FN		 2381 dead_tmp(tmp2);
2382 dead_tmp(tmp);
18c9b560
AZ		 2383
2384 gen_op_iwmmxt_movq_wRn_M0(acc);
2385 return 0;
2386 }
2387
2388 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2389 /* Internal Accumulator Access Format */
2390 rdhi = (insn >> 16) & 0xf;
2391 rdlo = (insn >> 12) & 0xf;
2392 acc = insn & 7;
2393
2394 if (acc != 0)
2395 return 1;
2396
2397 if (insn & ARM_CP_RW_BIT) { /* MRA */
3a554c0f
FN		 2398 iwmmxt_load_reg(cpu_V0, acc);
2399 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2400 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2401 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2402 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
18c9b560 2403 } else { /* MAR */
3a554c0f
FN		 2404 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2405 iwmmxt_store_reg(cpu_V0, acc);
18c9b560
AZ		 2406 }
2407 return 0;
2408 }
2409
2410 return 1;
2411}
2412
c1713132
AZ		 2413/* Disassemble system coprocessor instruction. Return nonzero if
2414 instruction is not defined. */
2415static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2416{
b75263d6 2417 TCGv tmp, tmp2;
c1713132
AZ		 2418 uint32_t rd = (insn >> 12) & 0xf;
2419 uint32_t cp = (insn >> 8) & 0xf;
2420 if (IS_USER(s)) {
2421 return 1;
2422 }
2423
18c9b560 2424 if (insn & ARM_CP_RW_BIT) {
c1713132
AZ		 2425 if (!env->cp[cp].cp_read)
2426 return 1;
8984bd2e
PB		 2427 gen_set_pc_im(s->pc);
2428 tmp = new_tmp();
b75263d6
JR		 2429 tmp2 = tcg_const_i32(insn);
2430 gen_helper_get_cp(tmp, cpu_env, tmp2);
2431 tcg_temp_free(tmp2);
8984bd2e 2432 store_reg(s, rd, tmp);
c1713132
AZ		 2433 } else {
2434 if (!env->cp[cp].cp_write)
2435 return 1;
8984bd2e
PB		 2436 gen_set_pc_im(s->pc);
2437 tmp = load_reg(s, rd);
b75263d6
JR		 2438 tmp2 = tcg_const_i32(insn);
2439 gen_helper_set_cp(cpu_env, tmp2, tmp);
2440 tcg_temp_free(tmp2);
a60de947 2441 dead_tmp(tmp);
c1713132
AZ		 2442 }
2443 return 0;
2444}
2445
9ee6e8bb
PB		 2446static int cp15_user_ok(uint32_t insn)
2447{
2448 int cpn = (insn >> 16) & 0xf;
2449 int cpm = insn & 0xf;
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2451
2452 if (cpn == 13 && cpm == 0) {
2453 /* TLS register. */
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2455 return 1;
2456 }
2457 if (cpn == 7) {
2458 /* ISB, DSB, DMB. */
2459 if ((cpm == 5 && op == 4)
2460 || (cpm == 10 && (op == 4 || op == 5)))
2461 return 1;
2462 }
2463 return 0;
2464}
2465
3f26c122
RV		 2466static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2467{
2468 TCGv tmp;
2469 int cpn = (insn >> 16) & 0xf;
2470 int cpm = insn & 0xf;
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2472
2473 if (!arm_feature(env, ARM_FEATURE_V6K))
2474 return 0;
2475
2476 if (!(cpn == 13 && cpm == 0))
2477 return 0;
2478
2479 if (insn & ARM_CP_RW_BIT) {
3f26c122
RV		 2480 switch (op) {
2481 case 2:
c5883be2 2482 tmp = load_cpu_field(cp15.c13_tls1);
3f26c122
RV		 2483 break;
2484 case 3:
c5883be2 2485 tmp = load_cpu_field(cp15.c13_tls2);
3f26c122
RV		 2486 break;
2487 case 4:
c5883be2 2488 tmp = load_cpu_field(cp15.c13_tls3);
3f26c122
RV		 2489 break;
2490 default:
3f26c122
RV		 2491 return 0;
2492 }
2493 store_reg(s, rd, tmp);
2494
2495 } else {
2496 tmp = load_reg(s, rd);
2497 switch (op) {
2498 case 2:
c5883be2 2499 store_cpu_field(tmp, cp15.c13_tls1);
3f26c122
RV		 2500 break;
2501 case 3:
c5883be2 2502 store_cpu_field(tmp, cp15.c13_tls2);
3f26c122
RV		 2503 break;
2504 case 4:
c5883be2 2505 store_cpu_field(tmp, cp15.c13_tls3);
3f26c122
RV		 2506 break;
2507 default:
c5883be2 2508 dead_tmp(tmp);
3f26c122
RV		 2509 return 0;
2510 }
3f26c122
RV		 2511 }
2512 return 1;
2513}
2514
b5ff1b31
FB		 2515/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2516 instruction is not defined. */
a90b7318 2517static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
b5ff1b31
FB		 2518{
2519 uint32_t rd;
b75263d6 2520 TCGv tmp, tmp2;
b5ff1b31 2521
9ee6e8bb
PB		 2522 /* M profile cores use memory mapped registers instead of cp15. */
2523 if (arm_feature(env, ARM_FEATURE_M))
2524 return 1;
2525
2526 if ((insn & (1 << 25)) == 0) {
2527 if (insn & (1 << 20)) {
2528 /* mrrc */
2529 return 1;
2530 }
2531 /* mcrr. Used for block cache operations, so implement as no-op. */
2532 return 0;
2533 }
2534 if ((insn & (1 << 4)) == 0) {
2535 /* cdp */
2536 return 1;
2537 }
2538 if (IS_USER(s) && !cp15_user_ok(insn)) {
b5ff1b31
FB		 2539 return 1;
2540 }
9332f9da
FB		 2541 if ((insn & 0x0fff0fff) == 0x0e070f90
2542 || (insn & 0x0fff0fff) == 0x0e070f58) {
2543 /* Wait for interrupt. */
8984bd2e 2544 gen_set_pc_im(s->pc);
9ee6e8bb 2545 s->is_jmp = DISAS_WFI;
9332f9da
FB		 2546 return 0;
2547 }
b5ff1b31 2548 rd = (insn >> 12) & 0xf;
3f26c122
RV		 2549
2550 if (cp15_tls_load_store(env, s, insn, rd))
2551 return 0;
2552
b75263d6 2553 tmp2 = tcg_const_i32(insn);
18c9b560 2554 if (insn & ARM_CP_RW_BIT) {
8984bd2e 2555 tmp = new_tmp();
b75263d6 2556 gen_helper_get_cp15(tmp, cpu_env, tmp2);
b5ff1b31
FB		 2557 /* If the destination register is r15 then sets condition codes. */
2558 if (rd != 15)
8984bd2e
PB		 2559 store_reg(s, rd, tmp);
2560 else
2561 dead_tmp(tmp);
b5ff1b31 2562 } else {
8984bd2e 2563 tmp = load_reg(s, rd);
b75263d6 2564 gen_helper_set_cp15(cpu_env, tmp2, tmp);
8984bd2e 2565 dead_tmp(tmp);
a90b7318
AZ		 2566 /* Normally we would always end the TB here, but Linux
2567 * arch/arm/mach-pxa/sleep.S expects two instructions following
2568 * an MMU enable to execute from cache. Imitate this behaviour. */
2569 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2570 (insn & 0x0fff0fff) != 0x0e010f10)
2571 gen_lookup_tb(s);
b5ff1b31 2572 }
b75263d6 2573 tcg_temp_free_i32(tmp2);
b5ff1b31
FB		 2574 return 0;
2575}
2576
9ee6e8bb
PB		 2577#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2578#define VFP_SREG(insn, bigbit, smallbit) \
2579 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2580#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2581 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2582 reg = (((insn) >> (bigbit)) & 0x0f) \
2583 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2584 } else { \
2585 if (insn & (1 << (smallbit))) \
2586 return 1; \
2587 reg = ((insn) >> (bigbit)) & 0x0f; \
2588 }} while (0)
2589
2590#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2591#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2592#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2593#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2594#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2595#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2596
4373f3ce
PB		 2597/* Move between integer and VFP cores. */
2598static TCGv gen_vfp_mrs(void)
2599{
2600 TCGv tmp = new_tmp();
2601 tcg_gen_mov_i32(tmp, cpu_F0s);
2602 return tmp;
2603}
2604
2605static void gen_vfp_msr(TCGv tmp)
2606{
2607 tcg_gen_mov_i32(cpu_F0s, tmp);
2608 dead_tmp(tmp);
2609}
2610
ad69471c
PB		 2611static void gen_neon_dup_u8(TCGv var, int shift)
2612{
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
86831435 2616 tcg_gen_ext8u_i32(var, var);
ad69471c
PB		 2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622}
2623
2624static void gen_neon_dup_low16(TCGv var)
2625{
2626 TCGv tmp = new_tmp();
86831435 2627 tcg_gen_ext16u_i32(var, var);
ad69471c
PB		 2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631}
2632
2633static void gen_neon_dup_high16(TCGv var)
2634{
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640}
2641
b7bcbe95
FB		 2642/* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645{
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
312eea9f 2648 TCGv addr;
4373f3ce 2649 TCGv tmp;
ad69471c 2650 TCGv tmp2;
b7bcbe95 2651
40f137e1
PB		 2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
5df8bac1 2655 if (!s->vfp_enabled) {
9ee6e8bb 2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
40f137e1
PB		 2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
9ee6e8bb
PB		 2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
40f137e1
PB		 2662 return 1;
2663 }
b7bcbe95
FB		 2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
b7bcbe95
FB		 2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
9ee6e8bb
PB		 2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
b7bcbe95 2676 return 1;
9ee6e8bb
PB		 2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
18c9b560 2692 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 2693 /* vfp->arm */
ad69471c 2694 tmp = neon_load_reg(rn, pass);
9ee6e8bb
PB		 2695 switch (size) {
2696 case 0:
9ee6e8bb 2697 if (offset)
ad69471c 2698 tcg_gen_shri_i32(tmp, tmp, offset);
9ee6e8bb 2699 if (insn & (1 << 23))
ad69471c 2700 gen_uxtb(tmp);
9ee6e8bb 2701 else
ad69471c 2702 gen_sxtb(tmp);
9ee6e8bb
PB		 2703 break;
2704 case 1:
9ee6e8bb
PB		 2705 if (insn & (1 << 23)) {
2706 if (offset) {
ad69471c 2707 tcg_gen_shri_i32(tmp, tmp, 16);
9ee6e8bb 2708 } else {
ad69471c 2709 gen_uxth(tmp);
9ee6e8bb
PB		 2710 }
2711 } else {
2712 if (offset) {
ad69471c 2713 tcg_gen_sari_i32(tmp, tmp, 16);
9ee6e8bb 2714 } else {
ad69471c 2715 gen_sxth(tmp);
9ee6e8bb
PB		 2716 }
2717 }
2718 break;
2719 case 2:
9ee6e8bb
PB		 2720 break;
2721 }
ad69471c 2722 store_reg(s, rd, tmp);
b7bcbe95
FB		 2723 } else {
2724 /* arm->vfp */
ad69471c 2725 tmp = load_reg(s, rd);
9ee6e8bb
PB		 2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
ad69471c 2729 gen_neon_dup_u8(tmp, 0);
9ee6e8bb 2730 } else if (size == 1) {
ad69471c 2731 gen_neon_dup_low16(tmp);
9ee6e8bb 2732 }
cbbccffc
PB		 2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
9ee6e8bb
PB		 2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
ad69471c
PB		 2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
9ee6e8bb
PB		 2746 break;
2747 case 1:
ad69471c
PB		 2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
9ee6e8bb
PB		 2751 break;
2752 case 2:
9ee6e8bb
PB		 2753 break;
2754 }
ad69471c 2755 neon_store_reg(rn, pass, tmp);
9ee6e8bb 2756 }
b7bcbe95 2757 }
9ee6e8bb
PB		 2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
18c9b560 2762 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
40f137e1 2766 rn >>= 1;
9ee6e8bb 2767
b7bcbe95 2768 switch (rn) {
40f137e1 2769 case ARM_VFP_FPSID:
4373f3ce 2770 /* VFP2 allows access to FSID from userspace.
9ee6e8bb
PB		 2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
4373f3ce 2776 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2777 break;
40f137e1 2778 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2779 if (IS_USER(s))
2780 return 1;
4373f3ce 2781 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2782 break;
40f137e1
PB		 2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
9ee6e8bb
PB		 2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
4373f3ce 2789 tmp = load_cpu_field(vfp.xregs[rn]);
b7bcbe95 2790 break;
40f137e1 2791 case ARM_VFP_FPSCR:
601d70b9 2792 if (rd == 15) {
4373f3ce
PB		 2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
b7bcbe95 2799 break;
9ee6e8bb
PB		 2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
4373f3ce 2805 tmp = load_cpu_field(vfp.xregs[rn]);
9ee6e8bb 2806 break;
b7bcbe95
FB		 2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
4373f3ce 2812 tmp = gen_vfp_mrs();
b7bcbe95
FB		 2813 }
2814 if (rd == 15) {
b5ff1b31 2815 /* Set the 4 flag bits in the CPSR. */
4373f3ce
PB		 2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
b7bcbe95
FB		 2821 } else {
2822 /* arm->vfp */
4373f3ce 2823 tmp = load_reg(s, rd);
b7bcbe95 2824 if (insn & (1 << 21)) {
40f137e1 2825 rn >>= 1;
b7bcbe95
FB		 2826 /* system register */
2827 switch (rn) {
40f137e1 2828 case ARM_VFP_FPSID:
9ee6e8bb
PB		 2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
b7bcbe95
FB		 2831 /* Writes are ignored. */
2832 break;
40f137e1 2833 case ARM_VFP_FPSCR:
4373f3ce
PB		 2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
b5ff1b31 2836 gen_lookup_tb(s);
b7bcbe95 2837 break;
40f137e1 2838 case ARM_VFP_FPEXC:
9ee6e8bb
PB		 2839 if (IS_USER(s))
2840 return 1;
71b3c3de
JR		 2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
4373f3ce 2844 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1
PB		 2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
4373f3ce 2849 store_cpu_field(tmp, vfp.xregs[rn]);
40f137e1 2850 break;
b7bcbe95
FB		 2851 default:
2852 return 1;
2853 }
2854 } else {
4373f3ce 2855 gen_vfp_msr(tmp);
b7bcbe95
FB		 2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
9ee6e8bb 2870 VFP_DREG_N(rn, insn);
b7bcbe95
FB		 2871 }
2872
04595bf6 2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
b7bcbe95 2874 /* Integer or single precision destination. */
9ee6e8bb 2875 rd = VFP_SREG_D(insn);
b7bcbe95 2876 } else {
9ee6e8bb 2877 VFP_DREG_D(rd, insn);
b7bcbe95 2878 }
04595bf6
PM		 2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
b7bcbe95 2885 } else {
9ee6e8bb 2886 VFP_DREG_M(rm, insn);
b7bcbe95
FB		 2887 }
2888 } else {
9ee6e8bb 2889 rn = VFP_SREG_N(insn);
b7bcbe95
FB		 2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
9ee6e8bb
PB		 2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
04595bf6
PM		 2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
9ee6e8bb 2899 rm = VFP_SREG_M(insn);
b7bcbe95
FB		 2900 }
2901
69d1fc22 2902 veclen = s->vec_len;
b7bcbe95
FB		 2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
3b46e624 2910
b7bcbe95
FB		 2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
69d1fc22 2923 delta_d = (s->vec_stride >> 1) + 1;
b7bcbe95 2924 else
69d1fc22 2925 delta_d = s->vec_stride + 1;
b7bcbe95
FB		 2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
9ee6e8bb
PB		 2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
644ad806
PB		 2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
9ee6e8bb
PB		 2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
b7bcbe95
FB		 2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
9ee6e8bb 2971 break;
b7bcbe95
FB		 2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
b7bcbe95 3000 gen_vfp_neg(dp);
c9fb531a
PB		 3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
b7bcbe95
FB		 3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
9ee6e8bb
PB		 3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
4373f3ce 3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
9ee6e8bb
PB		 3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
5b340b51 3039 tcg_gen_movi_i32(cpu_F0s, n);
9ee6e8bb 3040 }
9ee6e8bb 3041 break;
b7bcbe95
FB		 3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
60011498
PB		 3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
b7bcbe95
FB		 3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
4373f3ce 3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
b7bcbe95 3113 else
4373f3ce 3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
b7bcbe95
FB		 3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
9ee6e8bb
PB		 3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
644ad806 3125 gen_vfp_shto(dp, 16 - rm);
9ee6e8bb
PB		 3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
644ad806 3130 gen_vfp_slto(dp, 32 - rm);
9ee6e8bb
PB		 3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
644ad806 3135 gen_vfp_uhto(dp, 16 - rm);
9ee6e8bb
PB		 3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
644ad806 3140 gen_vfp_ulto(dp, 32 - rm);
9ee6e8bb 3141 break;
b7bcbe95
FB		 3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
9ee6e8bb
PB		 3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
644ad806 3157 gen_vfp_tosh(dp, 16 - rm);
9ee6e8bb
PB		 3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
644ad806 3162 gen_vfp_tosl(dp, 32 - rm);
9ee6e8bb
PB		 3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
644ad806 3167 gen_vfp_touh(dp, 16 - rm);
9ee6e8bb
PB		 3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
644ad806 3172 gen_vfp_toul(dp, 32 - rm);
9ee6e8bb 3173 break;
b7bcbe95
FB		 3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
04595bf6
PM		 3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
b7bcbe95
FB		 3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
9ee6e8bb 3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
b7bcbe95
FB		 3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
9ee6e8bb
PB		 3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
b7bcbe95 3244
18c9b560 3245 if (insn & ARM_CP_RW_BIT) {
b7bcbe95
FB		 3246 /* vfp->arm */
3247 if (dp) {
4373f3ce
PB		 3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
b7bcbe95
FB		 3254 } else {
3255 gen_mov_F0_vreg(0, rm);
4373f3ce
PB		 3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
b7bcbe95 3258 gen_mov_F0_vreg(0, rm + 1);
4373f3ce
PB		 3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
b7bcbe95
FB		 3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
4373f3ce
PB		 3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
b7bcbe95 3271 } else {
4373f3ce
PB		 3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
b7bcbe95 3274 gen_mov_vreg_F0(0, rm);
4373f3ce
PB		 3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
b7bcbe95
FB		 3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
9ee6e8bb 3284 VFP_DREG_D(rd, insn);
b7bcbe95 3285 else
9ee6e8bb
PB		 3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
312eea9f
FN		 3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
9ee6e8bb 3290 } else {
312eea9f 3291 addr = load_reg(s, rn);
9ee6e8bb 3292 }
b7bcbe95
FB		 3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
312eea9f 3298 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95 3299 if (insn & (1 << 20)) {
312eea9f 3300 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
312eea9f 3304 gen_vfp_st(s, dp, addr);
b7bcbe95 3305 }
312eea9f 3306 dead_tmp(addr);
b7bcbe95
FB		 3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
312eea9f 3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
b7bcbe95
FB		 3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
18c9b560 3322 if (insn & ARM_CP_RW_BIT) {
b7bcbe95 3323 /* load */
312eea9f 3324 gen_vfp_ld(s, dp, addr);
b7bcbe95
FB		 3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
312eea9f 3329 gen_vfp_st(s, dp, addr);
b7bcbe95 3330 }
312eea9f 3331 tcg_gen_addi_i32(addr, addr, offset);
b7bcbe95
FB		 3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
312eea9f
FN		 3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
b7bcbe95
FB		 3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356}
3357
6e256c93 3358static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 3359{
6e256c93
FB		 3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
57fec1fe 3364 tcg_gen_goto_tb(n);
8984bd2e 3365 gen_set_pc_im(dest);
57fec1fe 3366 tcg_gen_exit_tb((long)tb + n);
6e256c93 3367 } else {
8984bd2e 3368 gen_set_pc_im(dest);
57fec1fe 3369 tcg_gen_exit_tb(0);
6e256c93 3370 }
c53be334
FB		 3371}
3372
8aaca4c0
FB		 3373static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374{
551bd27f 3375 if (unlikely(s->singlestep_enabled)) {
8aaca4c0 3376 /* An indirect jump so that we still trigger the debug exception. */
5899f386 3377 if (s->thumb)
d9ba4830
PB		 3378 dest |= 1;
3379 gen_bx_im(s, dest);
8aaca4c0 3380 } else {
6e256c93 3381 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384}
3385
d9ba4830 3386static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
b5ff1b31 3387{
ee097184 3388 if (x)
d9ba4830 3389 tcg_gen_sari_i32(t0, t0, 16);
b5ff1b31 3390 else
d9ba4830 3391 gen_sxth(t0);
ee097184 3392 if (y)
d9ba4830 3393 tcg_gen_sari_i32(t1, t1, 16);
b5ff1b31 3394 else
d9ba4830
PB		 3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
b5ff1b31
FB		 3397}
3398
3399/* Return the mask of PSR bits set by a MSR instruction. */
9ee6e8bb 3400static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
b5ff1b31
FB		 3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
9ee6e8bb 3412
2ae23e75 3413 /* Mask out undefined bits. */
9ee6e8bb
PB		 3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
e160c51c 3416 mask &= ~(CPSR_E | CPSR_GE);
9ee6e8bb 3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
e160c51c 3418 mask &= ~CPSR_IT;
9ee6e8bb 3419 /* Mask out execution state bits. */
2ae23e75 3420 if (!spsr)
e160c51c 3421 mask &= ~CPSR_EXEC;
b5ff1b31
FB		 3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
9ee6e8bb 3424 mask &= CPSR_USER;
b5ff1b31
FB		 3425 return mask;
3426}
3427
2fbac54b
FN		 3428/* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
b5ff1b31 3430{
d9ba4830 3431 TCGv tmp;
b5ff1b31
FB		 3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
d9ba4830
PB		 3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
2fbac54b
FN		 3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
d9ba4830 3441 store_cpu_field(tmp, spsr);
b5ff1b31 3442 } else {
2fbac54b 3443 gen_set_cpsr(t0, mask);
b5ff1b31 3444 }
2fbac54b 3445 dead_tmp(t0);
b5ff1b31
FB		 3446 gen_lookup_tb(s);
3447 return 0;
3448}
3449
2fbac54b
FN		 3450/* Returns nonzero if access to the PSR is not permitted. */
3451static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452{
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457}
3458
e9bb4aa9
JR		 3459/* Generate an old-style exception return. Marks pc as dead. */
3460static void gen_exception_return(DisasContext *s, TCGv pc)
b5ff1b31 3461{
d9ba4830 3462 TCGv tmp;
e9bb4aa9 3463 store_reg(s, 15, pc);
d9ba4830
PB		 3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
b5ff1b31
FB		 3467 s->is_jmp = DISAS_UPDATE;
3468}
3469
b0109805
PB		 3470/* Generate a v6 exception return. Marks both values as dead. */
3471static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
2c0262af 3472{
b0109805
PB		 3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
9ee6e8bb
PB		 3476 s->is_jmp = DISAS_UPDATE;
3477}
3b46e624 3478
9ee6e8bb
PB		 3479static inline void
3480gen_set_condexec (DisasContext *s)
3481{
3482 if (s->condexec_mask) {
8f01245e
PB		 3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
d9ba4830 3486 store_cpu_field(tmp, condexec_bits);
9ee6e8bb
PB		 3487 }
3488}
3b46e624 3489
bc4a0de0
PM		 3490static void gen_exception_insn(DisasContext *s, int offset, int excp)
3491{
3492 gen_set_condexec(s);
3493 gen_set_pc_im(s->pc - offset);
3494 gen_exception(excp);
3495 s->is_jmp = DISAS_JUMP;
3496}
3497
9ee6e8bb
PB		 3498static void gen_nop_hint(DisasContext *s, int val)
3499{
3500 switch (val) {
3501 case 3: /* wfi */
8984bd2e 3502 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 3503 s->is_jmp = DISAS_WFI;
3504 break;
3505 case 2: /* wfe */
3506 case 4: /* sev */
3507 /* TODO: Implement SEV and WFE. May help SMP performance. */
3508 default: /* nop */
3509 break;
3510 }
3511}
99c475ab 3512
ad69471c 3513#define CPU_V001 cpu_V0, cpu_V0, cpu_V1
9ee6e8bb 3514
dd8fbd78 3515static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
9ee6e8bb
PB		 3516{
3517 switch (size) {
dd8fbd78
FN		 3518 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3519 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3520 case 2: tcg_gen_add_i32(t0, t0, t1); break;
9ee6e8bb
PB		 3521 default: return 1;
3522 }
3523 return 0;
3524}
3525
dd8fbd78 3526static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
ad69471c
PB		 3527{
3528 switch (size) {
dd8fbd78
FN		 3529 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3530 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3531 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
ad69471c
PB		 3532 default: return;
3533 }
3534}
3535
3536/* 32-bit pairwise ops end up the same as the elementwise versions. */
3537#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3538#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3539#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3540#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3541
ad69471c
PB		 3542#define GEN_NEON_INTEGER_OP_ENV(name) do { \
3543 switch ((size << 1) | u) { \
3544 case 0: \
dd8fbd78 3545 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3546 break; \
3547 case 1: \
dd8fbd78 3548 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3549 break; \
3550 case 2: \
dd8fbd78 3551 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3552 break; \
3553 case 3: \
dd8fbd78 3554 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3555 break; \
3556 case 4: \
dd8fbd78 3557 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3558 break; \
3559 case 5: \
dd8fbd78 3560 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
ad69471c
PB		 3561 break; \
3562 default: return 1; \
3563 }} while (0)
9ee6e8bb
PB		 3564
3565#define GEN_NEON_INTEGER_OP(name) do { \
3566 switch ((size << 1) | u) { \
ad69471c 3567 case 0: \
dd8fbd78 3568 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
ad69471c
PB		 3569 break; \
3570 case 1: \
dd8fbd78 3571 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
ad69471c
PB		 3572 break; \
3573 case 2: \
dd8fbd78 3574 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
ad69471c
PB		 3575 break; \
3576 case 3: \
dd8fbd78 3577 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
ad69471c
PB		 3578 break; \
3579 case 4: \
dd8fbd78 3580 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
ad69471c
PB		 3581 break; \
3582 case 5: \
dd8fbd78 3583 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
ad69471c 3584 break; \
9ee6e8bb
PB		 3585 default: return 1; \
3586 }} while (0)
3587
dd8fbd78 3588static TCGv neon_load_scratch(int scratch)
9ee6e8bb 3589{
dd8fbd78
FN		 3590 TCGv tmp = new_tmp();
3591 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3592 return tmp;
9ee6e8bb
PB		 3593}
3594
dd8fbd78 3595static void neon_store_scratch(int scratch, TCGv var)
9ee6e8bb 3596{
dd8fbd78
FN		 3597 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3598 dead_tmp(var);
9ee6e8bb
PB		 3599}
3600
dd8fbd78 3601static inline TCGv neon_get_scalar(int size, int reg)
9ee6e8bb 3602{
dd8fbd78 3603 TCGv tmp;
9ee6e8bb 3604 if (size == 1) {
0fad6efc
PM		 3605 tmp = neon_load_reg(reg & 7, reg >> 4);
3606 if (reg & 8) {
dd8fbd78 3607 gen_neon_dup_high16(tmp);
0fad6efc
PM		 3608 } else {
3609 gen_neon_dup_low16(tmp);
dd8fbd78 3610 }
0fad6efc
PM		 3611 } else {
3612 tmp = neon_load_reg(reg & 15, reg >> 4);
9ee6e8bb 3613 }
dd8fbd78 3614 return tmp;
9ee6e8bb
PB		 3615}
3616
19457615
FN		 3617static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3618{
3619 TCGv rd, rm, tmp;
3620
3621 rd = new_tmp();
3622 rm = new_tmp();
3623 tmp = new_tmp();
3624
3625 tcg_gen_andi_i32(rd, t0, 0xff);
3626 tcg_gen_shri_i32(tmp, t0, 8);
3627 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3628 tcg_gen_or_i32(rd, rd, tmp);
3629 tcg_gen_shli_i32(tmp, t1, 16);
3630 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3631 tcg_gen_or_i32(rd, rd, tmp);
3632 tcg_gen_shli_i32(tmp, t1, 8);
3633 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3634 tcg_gen_or_i32(rd, rd, tmp);
3635
3636 tcg_gen_shri_i32(rm, t0, 8);
3637 tcg_gen_andi_i32(rm, rm, 0xff);
3638 tcg_gen_shri_i32(tmp, t0, 16);
3639 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3640 tcg_gen_or_i32(rm, rm, tmp);
3641 tcg_gen_shli_i32(tmp, t1, 8);
3642 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3643 tcg_gen_or_i32(rm, rm, tmp);
3644 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3645 tcg_gen_or_i32(t1, rm, tmp);
3646 tcg_gen_mov_i32(t0, rd);
3647
3648 dead_tmp(tmp);
3649 dead_tmp(rm);
3650 dead_tmp(rd);
3651}
3652
3653static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3654{
3655 TCGv rd, rm, tmp;
3656
3657 rd = new_tmp();
3658 rm = new_tmp();
3659 tmp = new_tmp();
3660
3661 tcg_gen_andi_i32(rd, t0, 0xff);
3662 tcg_gen_shli_i32(tmp, t1, 8);
3663 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3664 tcg_gen_or_i32(rd, rd, tmp);
3665 tcg_gen_shli_i32(tmp, t0, 16);
3666 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3667 tcg_gen_or_i32(rd, rd, tmp);
3668 tcg_gen_shli_i32(tmp, t1, 24);
3669 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3670 tcg_gen_or_i32(rd, rd, tmp);
3671
3672 tcg_gen_andi_i32(rm, t1, 0xff000000);
3673 tcg_gen_shri_i32(tmp, t0, 8);
3674 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3675 tcg_gen_or_i32(rm, rm, tmp);
3676 tcg_gen_shri_i32(tmp, t1, 8);
3677 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3678 tcg_gen_or_i32(rm, rm, tmp);
3679 tcg_gen_shri_i32(tmp, t0, 16);
3680 tcg_gen_andi_i32(tmp, tmp, 0xff);
3681 tcg_gen_or_i32(t1, rm, tmp);
3682 tcg_gen_mov_i32(t0, rd);
3683
3684 dead_tmp(tmp);
3685 dead_tmp(rm);
3686 dead_tmp(rd);
3687}
3688
3689static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3690{
3691 TCGv tmp, tmp2;
3692
3693 tmp = new_tmp();
3694 tmp2 = new_tmp();
3695
3696 tcg_gen_andi_i32(tmp, t0, 0xffff);
3697 tcg_gen_shli_i32(tmp2, t1, 16);
3698 tcg_gen_or_i32(tmp, tmp, tmp2);
3699 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3700 tcg_gen_shri_i32(tmp2, t0, 16);
3701 tcg_gen_or_i32(t1, t1, tmp2);
3702 tcg_gen_mov_i32(t0, tmp);
3703
3704 dead_tmp(tmp2);
3705 dead_tmp(tmp);
3706}
3707
9ee6e8bb
PB		 3708static void gen_neon_unzip(int reg, int q, int tmp, int size)
3709{
3710 int n;
dd8fbd78 3711 TCGv t0, t1;
9ee6e8bb
PB		 3712
3713 for (n = 0; n < q + 1; n += 2) {
dd8fbd78
FN		 3714 t0 = neon_load_reg(reg, n);
3715 t1 = neon_load_reg(reg, n + 1);
9ee6e8bb 3716 switch (size) {
dd8fbd78
FN		 3717 case 0: gen_neon_unzip_u8(t0, t1); break;
3718 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
9ee6e8bb
PB		 3719 case 2: /* no-op */; break;
3720 default: abort();
3721 }
dd8fbd78
FN		 3722 neon_store_scratch(tmp + n, t0);
3723 neon_store_scratch(tmp + n + 1, t1);
9ee6e8bb
PB		 3724 }
3725}
3726
19457615
FN		 3727static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3728{
3729 TCGv rd, tmp;
3730
3731 rd = new_tmp();
3732 tmp = new_tmp();
3733
3734 tcg_gen_shli_i32(rd, t0, 8);
3735 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3736 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3737 tcg_gen_or_i32(rd, rd, tmp);
3738
3739 tcg_gen_shri_i32(t1, t1, 8);
3740 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3741 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3742 tcg_gen_or_i32(t1, t1, tmp);
3743 tcg_gen_mov_i32(t0, rd);
3744
3745 dead_tmp(tmp);
3746 dead_tmp(rd);
3747}
3748
3749static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3750{
3751 TCGv rd, tmp;
3752
3753 rd = new_tmp();
3754 tmp = new_tmp();
3755
3756 tcg_gen_shli_i32(rd, t0, 16);
3757 tcg_gen_andi_i32(tmp, t1, 0xffff);
3758 tcg_gen_or_i32(rd, rd, tmp);
3759 tcg_gen_shri_i32(t1, t1, 16);
3760 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3761 tcg_gen_or_i32(t1, t1, tmp);
3762 tcg_gen_mov_i32(t0, rd);
3763
3764 dead_tmp(tmp);
3765 dead_tmp(rd);
3766}
3767
3768
9ee6e8bb
PB		 3769static struct {
3770 int nregs;
3771 int interleave;
3772 int spacing;
3773} neon_ls_element_type[11] = {
3774 {4, 4, 1},
3775 {4, 4, 2},
3776 {4, 1, 1},
3777 {4, 2, 1},
3778 {3, 3, 1},
3779 {3, 3, 2},
3780 {3, 1, 1},
3781 {1, 1, 1},
3782 {2, 2, 1},
3783 {2, 2, 2},
3784 {2, 1, 1}
3785};
3786
3787/* Translate a NEON load/store element instruction. Return nonzero if the
3788 instruction is invalid. */
3789static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3790{
3791 int rd, rn, rm;
3792 int op;
3793 int nregs;
3794 int interleave;
84496233 3795 int spacing;
9ee6e8bb
PB		 3796 int stride;
3797 int size;
3798 int reg;
3799 int pass;
3800 int load;
3801 int shift;
9ee6e8bb 3802 int n;
1b2b1e54 3803 TCGv addr;
b0109805 3804 TCGv tmp;
8f8e3aa4 3805 TCGv tmp2;
84496233 3806 TCGv_i64 tmp64;
9ee6e8bb 3807
5df8bac1 3808 if (!s->vfp_enabled)
9ee6e8bb
PB		 3809 return 1;
3810 VFP_DREG_D(rd, insn);
3811 rn = (insn >> 16) & 0xf;
3812 rm = insn & 0xf;
3813 load = (insn & (1 << 21)) != 0;
1b2b1e54 3814 addr = new_tmp();
9ee6e8bb
PB		 3815 if ((insn & (1 << 23)) == 0) {
3816 /* Load store all elements. */
3817 op = (insn >> 8) & 0xf;
3818 size = (insn >> 6) & 3;
84496233 3819 if (op > 10)
9ee6e8bb
PB		 3820 return 1;
3821 nregs = neon_ls_element_type[op].nregs;
3822 interleave = neon_ls_element_type[op].interleave;
84496233
JR		 3823 spacing = neon_ls_element_type[op].spacing;
3824 if (size == 3 && (interleave | spacing) != 1)
3825 return 1;
dcc65026 3826 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3827 stride = (1 << size) * interleave;
3828 for (reg = 0; reg < nregs; reg++) {
3829 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
dcc65026
AJ		 3830 load_reg_var(s, addr, rn);
3831 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
9ee6e8bb 3832 } else if (interleave == 2 && nregs == 4 && reg == 2) {
dcc65026
AJ		 3833 load_reg_var(s, addr, rn);
3834 tcg_gen_addi_i32(addr, addr, 1 << size);
9ee6e8bb 3835 }
84496233
JR		 3836 if (size == 3) {
3837 if (load) {
3838 tmp64 = gen_ld64(addr, IS_USER(s));
3839 neon_store_reg64(tmp64, rd);
3840 tcg_temp_free_i64(tmp64);
3841 } else {
3842 tmp64 = tcg_temp_new_i64();
3843 neon_load_reg64(tmp64, rd);
3844 gen_st64(tmp64, addr, IS_USER(s));
3845 }
3846 tcg_gen_addi_i32(addr, addr, stride);
3847 } else {
3848 for (pass = 0; pass < 2; pass++) {
3849 if (size == 2) {
3850 if (load) {
3851 tmp = gen_ld32(addr, IS_USER(s));
3852 neon_store_reg(rd, pass, tmp);
3853 } else {
3854 tmp = neon_load_reg(rd, pass);
3855 gen_st32(tmp, addr, IS_USER(s));
3856 }
1b2b1e54 3857 tcg_gen_addi_i32(addr, addr, stride);
84496233
JR		 3858 } else if (size == 1) {
3859 if (load) {
3860 tmp = gen_ld16u(addr, IS_USER(s));
3861 tcg_gen_addi_i32(addr, addr, stride);
3862 tmp2 = gen_ld16u(addr, IS_USER(s));
3863 tcg_gen_addi_i32(addr, addr, stride);
41ba8341
PB		 3864 tcg_gen_shli_i32(tmp2, tmp2, 16);
3865 tcg_gen_or_i32(tmp, tmp, tmp2);
84496233
JR		 3866 dead_tmp(tmp2);
3867 neon_store_reg(rd, pass, tmp);
3868 } else {
3869 tmp = neon_load_reg(rd, pass);
3870 tmp2 = new_tmp();
3871 tcg_gen_shri_i32(tmp2, tmp, 16);
3872 gen_st16(tmp, addr, IS_USER(s));
3873 tcg_gen_addi_i32(addr, addr, stride);
3874 gen_st16(tmp2, addr, IS_USER(s));
1b2b1e54 3875 tcg_gen_addi_i32(addr, addr, stride);
9ee6e8bb 3876 }
84496233
JR		 3877 } else /* size == 0 */ {
3878 if (load) {
3879 TCGV_UNUSED(tmp2);
3880 for (n = 0; n < 4; n++) {
3881 tmp = gen_ld8u(addr, IS_USER(s));
3882 tcg_gen_addi_i32(addr, addr, stride);
3883 if (n == 0) {
3884 tmp2 = tmp;
3885 } else {
41ba8341
PB		 3886 tcg_gen_shli_i32(tmp, tmp, n * 8);
3887 tcg_gen_or_i32(tmp2, tmp2, tmp);
84496233
JR		 3888 dead_tmp(tmp);
3889 }
9ee6e8bb 3890 }
84496233
JR		 3891 neon_store_reg(rd, pass, tmp2);
3892 } else {
3893 tmp2 = neon_load_reg(rd, pass);
3894 for (n = 0; n < 4; n++) {
3895 tmp = new_tmp();
3896 if (n == 0) {
3897 tcg_gen_mov_i32(tmp, tmp2);
3898 } else {
3899 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3900 }
3901 gen_st8(tmp, addr, IS_USER(s));
3902 tcg_gen_addi_i32(addr, addr, stride);
3903 }
3904 dead_tmp(tmp2);
9ee6e8bb
PB		 3905 }
3906 }
3907 }
3908 }
84496233 3909 rd += spacing;
9ee6e8bb
PB		 3910 }
3911 stride = nregs * 8;
3912 } else {
3913 size = (insn >> 10) & 3;
3914 if (size == 3) {
3915 /* Load single element to all lanes. */
3916 if (!load)
3917 return 1;
3918 size = (insn >> 6) & 3;
3919 nregs = ((insn >> 8) & 3) + 1;
3920 stride = (insn & (1 << 5)) ? 2 : 1;
dcc65026 3921 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3922 for (reg = 0; reg < nregs; reg++) {
3923 switch (size) {
3924 case 0:
1b2b1e54 3925 tmp = gen_ld8u(addr, IS_USER(s));
ad69471c 3926 gen_neon_dup_u8(tmp, 0);
9ee6e8bb
PB		 3927 break;
3928 case 1:
1b2b1e54 3929 tmp = gen_ld16u(addr, IS_USER(s));
ad69471c 3930 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 3931 break;
3932 case 2:
1b2b1e54 3933 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 3934 break;
3935 case 3:
3936 return 1;
a50f5b91
PB		 3937 default: /* Avoid compiler warnings. */
3938 abort();
99c475ab 3939 }
1b2b1e54 3940 tcg_gen_addi_i32(addr, addr, 1 << size);
ad69471c
PB		 3941 tmp2 = new_tmp();
3942 tcg_gen_mov_i32(tmp2, tmp);
3943 neon_store_reg(rd, 0, tmp2);
3018f259 3944 neon_store_reg(rd, 1, tmp);
9ee6e8bb
PB		 3945 rd += stride;
3946 }
3947 stride = (1 << size) * nregs;
3948 } else {
3949 /* Single element. */
3950 pass = (insn >> 7) & 1;
3951 switch (size) {
3952 case 0:
3953 shift = ((insn >> 5) & 3) * 8;
9ee6e8bb
PB		 3954 stride = 1;
3955 break;
3956 case 1:
3957 shift = ((insn >> 6) & 1) * 16;
9ee6e8bb
PB		 3958 stride = (insn & (1 << 5)) ? 2 : 1;
3959 break;
3960 case 2:
3961 shift = 0;
9ee6e8bb
PB		 3962 stride = (insn & (1 << 6)) ? 2 : 1;
3963 break;
3964 default:
3965 abort();
3966 }
3967 nregs = ((insn >> 8) & 3) + 1;
dcc65026 3968 load_reg_var(s, addr, rn);
9ee6e8bb
PB		 3969 for (reg = 0; reg < nregs; reg++) {
3970 if (load) {
9ee6e8bb
PB		 3971 switch (size) {
3972 case 0:
1b2b1e54 3973 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb
PB		 3974 break;
3975 case 1:
1b2b1e54 3976 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 3977 break;
3978 case 2:
1b2b1e54 3979 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 3980 break;
a50f5b91
PB		 3981 default: /* Avoid compiler warnings. */
3982 abort();
9ee6e8bb
PB		 3983 }
3984 if (size != 2) {
8f8e3aa4
PB		 3985 tmp2 = neon_load_reg(rd, pass);
3986 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3987 dead_tmp(tmp2);
9ee6e8bb 3988 }
8f8e3aa4 3989 neon_store_reg(rd, pass, tmp);
9ee6e8bb 3990 } else { /* Store */
8f8e3aa4
PB		 3991 tmp = neon_load_reg(rd, pass);
3992 if (shift)
3993 tcg_gen_shri_i32(tmp, tmp, shift);
9ee6e8bb
PB		 3994 switch (size) {
3995 case 0:
1b2b1e54 3996 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 3997 break;
3998 case 1:
1b2b1e54 3999 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 4000 break;
4001 case 2:
1b2b1e54 4002 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 4003 break;
99c475ab 4004 }
99c475ab 4005 }
9ee6e8bb 4006 rd += stride;
1b2b1e54 4007 tcg_gen_addi_i32(addr, addr, 1 << size);
99c475ab 4008 }
9ee6e8bb 4009 stride = nregs * (1 << size);
99c475ab 4010 }
9ee6e8bb 4011 }
1b2b1e54 4012 dead_tmp(addr);
9ee6e8bb 4013 if (rm != 15) {
b26eefb6
PB		 4014 TCGv base;
4015
4016 base = load_reg(s, rn);
9ee6e8bb 4017 if (rm == 13) {
b26eefb6 4018 tcg_gen_addi_i32(base, base, stride);
9ee6e8bb 4019 } else {
b26eefb6
PB		 4020 TCGv index;
4021 index = load_reg(s, rm);
4022 tcg_gen_add_i32(base, base, index);
4023 dead_tmp(index);
9ee6e8bb 4024 }
b26eefb6 4025 store_reg(s, rn, base);
9ee6e8bb
PB		 4026 }
4027 return 0;
4028}
3b46e624 4029
8f8e3aa4
PB		 4030/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4031static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4032{
4033 tcg_gen_and_i32(t, t, c);
f669df27 4034 tcg_gen_andc_i32(f, f, c);
8f8e3aa4
PB		 4035 tcg_gen_or_i32(dest, t, f);
4036}
4037
a7812ae4 4038static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4039{
4040 switch (size) {
4041 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4042 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4043 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4044 default: abort();
4045 }
4046}
4047
a7812ae4 4048static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4049{
4050 switch (size) {
4051 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4052 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4053 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4054 default: abort();
4055 }
4056}
4057
a7812ae4 4058static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
ad69471c
PB		 4059{
4060 switch (size) {
4061 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4062 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4063 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4064 default: abort();
4065 }
4066}
4067
af1bbf30
JR		 4068static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4069{
4070 switch (size) {
4071 case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
4072 case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
4073 case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
4074 default: abort();
4075 }
4076}
4077
ad69471c
PB		 4078static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4079 int q, int u)
4080{
4081 if (q) {
4082 if (u) {
4083 switch (size) {
4084 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4085 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4086 default: abort();
4087 }
4088 } else {
4089 switch (size) {
4090 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4091 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4092 default: abort();
4093 }
4094 }
4095 } else {
4096 if (u) {
4097 switch (size) {
4098 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4099 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4100 default: abort();
4101 }
4102 } else {
4103 switch (size) {
4104 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4105 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4106 default: abort();
4107 }
4108 }
4109 }
4110}
4111
a7812ae4 4112static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
ad69471c
PB		 4113{
4114 if (u) {
4115 switch (size) {
4116 case 0: gen_helper_neon_widen_u8(dest, src); break;
4117 case 1: gen_helper_neon_widen_u16(dest, src); break;
4118 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4119 default: abort();
4120 }
4121 } else {
4122 switch (size) {
4123 case 0: gen_helper_neon_widen_s8(dest, src); break;
4124 case 1: gen_helper_neon_widen_s16(dest, src); break;
4125 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4126 default: abort();
4127 }
4128 }
4129 dead_tmp(src);
4130}
4131
4132static inline void gen_neon_addl(int size)
4133{
4134 switch (size) {
4135 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4136 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4137 case 2: tcg_gen_add_i64(CPU_V001); break;
4138 default: abort();
4139 }
4140}
4141
4142static inline void gen_neon_subl(int size)
4143{
4144 switch (size) {
4145 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4146 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4147 case 2: tcg_gen_sub_i64(CPU_V001); break;
4148 default: abort();
4149 }
4150}
4151
a7812ae4 4152static inline void gen_neon_negl(TCGv_i64 var, int size)
ad69471c
PB		 4153{
4154 switch (size) {
4155 case 0: gen_helper_neon_negl_u16(var, var); break;
4156 case 1: gen_helper_neon_negl_u32(var, var); break;
4157 case 2: gen_helper_neon_negl_u64(var, var); break;
4158 default: abort();
4159 }
4160}
4161
a7812ae4 4162static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
ad69471c
PB		 4163{
4164 switch (size) {
4165 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4166 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4167 default: abort();
4168 }
4169}
4170
a7812ae4 4171static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
ad69471c 4172{
a7812ae4 4173 TCGv_i64 tmp;
ad69471c
PB		 4174
4175 switch ((size << 1) | u) {
4176 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4177 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4178 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4179 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4180 case 4:
4181 tmp = gen_muls_i64_i32(a, b);
4182 tcg_gen_mov_i64(dest, tmp);
4183 break;
4184 case 5:
4185 tmp = gen_mulu_i64_i32(a, b);
4186 tcg_gen_mov_i64(dest, tmp);
4187 break;
4188 default: abort();
4189 }
c6067f04
CL		 4190
4191 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4192 Don't forget to clean them now. */
4193 if (size < 2) {
4194 dead_tmp(a);
4195 dead_tmp(b);
4196 }
ad69471c
PB		 4197}
4198
9ee6e8bb
PB		 4199/* Translate a NEON data processing instruction. Return nonzero if the
4200 instruction is invalid.
ad69471c
PB		 4201 We process data in a mixture of 32-bit and 64-bit chunks.
4202 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
2c0262af 4203
9ee6e8bb
PB		 4204static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4205{
4206 int op;
4207 int q;
4208 int rd, rn, rm;
4209 int size;
4210 int shift;
4211 int pass;
4212 int count;
4213 int pairwise;
4214 int u;
4215 int n;
ca9a32e4 4216 uint32_t imm, mask;
b75263d6 4217 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
a7812ae4 4218 TCGv_i64 tmp64;
9ee6e8bb 4219
5df8bac1 4220 if (!s->vfp_enabled)
9ee6e8bb
PB		 4221 return 1;
4222 q = (insn & (1 << 6)) != 0;
4223 u = (insn >> 24) & 1;
4224 VFP_DREG_D(rd, insn);
4225 VFP_DREG_N(rn, insn);
4226 VFP_DREG_M(rm, insn);
4227 size = (insn >> 20) & 3;
4228 if ((insn & (1 << 23)) == 0) {
4229 /* Three register same length. */
4230 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
ad69471c
PB		 4231 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4232 || op == 10 || op == 11 || op == 16)) {
4233 /* 64-bit element instructions. */
9ee6e8bb 4234 for (pass = 0; pass < (q ? 2 : 1); pass++) {
ad69471c
PB		 4235 neon_load_reg64(cpu_V0, rn + pass);
4236 neon_load_reg64(cpu_V1, rm + pass);
9ee6e8bb
PB		 4237 switch (op) {
4238 case 1: /* VQADD */
4239 if (u) {
72902672
CL		 4240 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4241 cpu_V0, cpu_V1);
2c0262af 4242 } else {
72902672
CL		 4243 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4244 cpu_V0, cpu_V1);
2c0262af 4245 }
9ee6e8bb
PB		 4246 break;
4247 case 5: /* VQSUB */
4248 if (u) {
72902672
CL		 4249 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4250 cpu_V0, cpu_V1);
ad69471c 4251 } else {
72902672
CL		 4252 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4253 cpu_V0, cpu_V1);
ad69471c
PB		 4254 }
4255 break;
4256 case 8: /* VSHL */
4257 if (u) {
4258 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4259 } else {
4260 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4261 }
4262 break;
4263 case 9: /* VQSHL */
4264 if (u) {
4265 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
def126ce 4266 cpu_V1, cpu_V0);
ad69471c 4267 } else {
def126ce 4268 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
ad69471c
PB		 4269 cpu_V1, cpu_V0);
4270 }
4271 break;
4272 case 10: /* VRSHL */
4273 if (u) {
4274 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
1e8d4eec 4275 } else {
ad69471c
PB		 4276 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4277 }
4278 break;
4279 case 11: /* VQRSHL */
4280 if (u) {
4281 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4282 cpu_V1, cpu_V0);
4283 } else {
4284 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4285 cpu_V1, cpu_V0);
1e8d4eec 4286 }
9ee6e8bb
PB		 4287 break;
4288 case 16:
4289 if (u) {
ad69471c 4290 tcg_gen_sub_i64(CPU_V001);
9ee6e8bb 4291 } else {
ad69471c 4292 tcg_gen_add_i64(CPU_V001);
9ee6e8bb
PB		 4293 }
4294 break;
4295 default:
4296 abort();
2c0262af 4297 }
ad69471c 4298 neon_store_reg64(cpu_V0, rd + pass);
2c0262af 4299 }
9ee6e8bb 4300 return 0;
2c0262af 4301 }
9ee6e8bb
PB		 4302 switch (op) {
4303 case 8: /* VSHL */
4304 case 9: /* VQSHL */
4305 case 10: /* VRSHL */
ad69471c 4306 case 11: /* VQRSHL */
9ee6e8bb 4307 {
ad69471c
PB		 4308 int rtmp;
4309 /* Shift instruction operands are reversed. */
4310 rtmp = rn;
9ee6e8bb 4311 rn = rm;
ad69471c 4312 rm = rtmp;
9ee6e8bb
PB		 4313 pairwise = 0;
4314 }
2c0262af 4315 break;
9ee6e8bb
PB		 4316 case 20: /* VPMAX */
4317 case 21: /* VPMIN */
4318 case 23: /* VPADD */
4319 pairwise = 1;
2c0262af 4320 break;
9ee6e8bb
PB		 4321 case 26: /* VPADD (float) */
4322 pairwise = (u && size < 2);
2c0262af 4323 break;
9ee6e8bb
PB		 4324 case 30: /* VPMIN/VPMAX (float) */
4325 pairwise = u;
2c0262af 4326 break;
9ee6e8bb
PB		 4327 default:
4328 pairwise = 0;
2c0262af 4329 break;
9ee6e8bb 4330 }
dd8fbd78 4331
9ee6e8bb
PB		 4332 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4333
4334 if (pairwise) {
4335 /* Pairwise. */
4336 if (q)
4337 n = (pass & 1) * 2;
2c0262af 4338 else
9ee6e8bb
PB		 4339 n = 0;
4340 if (pass < q + 1) {
dd8fbd78
FN		 4341 tmp = neon_load_reg(rn, n);
4342 tmp2 = neon_load_reg(rn, n + 1);
9ee6e8bb 4343 } else {
dd8fbd78
FN		 4344 tmp = neon_load_reg(rm, n);
4345 tmp2 = neon_load_reg(rm, n + 1);
9ee6e8bb
PB		 4346 }
4347 } else {
4348 /* Elementwise. */
dd8fbd78
FN		 4349 tmp = neon_load_reg(rn, pass);
4350 tmp2 = neon_load_reg(rm, pass);
9ee6e8bb
PB		 4351 }
4352 switch (op) {
4353 case 0: /* VHADD */
4354 GEN_NEON_INTEGER_OP(hadd);
4355 break;
4356 case 1: /* VQADD */
ad69471c 4357 GEN_NEON_INTEGER_OP_ENV(qadd);
2c0262af 4358 break;
9ee6e8bb
PB		 4359 case 2: /* VRHADD */
4360 GEN_NEON_INTEGER_OP(rhadd);
2c0262af 4361 break;
9ee6e8bb
PB		 4362 case 3: /* Logic ops. */
4363 switch ((u << 2) | size) {
4364 case 0: /* VAND */
dd8fbd78 4365 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4366 break;
4367 case 1: /* BIC */
f669df27 4368 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4369 break;
4370 case 2: /* VORR */
dd8fbd78 4371 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4372 break;
4373 case 3: /* VORN */
f669df27 4374 tcg_gen_orc_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4375 break;
4376 case 4: /* VEOR */
dd8fbd78 4377 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4378 break;
4379 case 5: /* VBSL */
dd8fbd78
FN		 4380 tmp3 = neon_load_reg(rd, pass);
4381 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4382 dead_tmp(tmp3);
9ee6e8bb
PB		 4383 break;
4384 case 6: /* VBIT */
dd8fbd78
FN		 4385 tmp3 = neon_load_reg(rd, pass);
4386 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4387 dead_tmp(tmp3);
9ee6e8bb
PB		 4388 break;
4389 case 7: /* VBIF */
dd8fbd78
FN		 4390 tmp3 = neon_load_reg(rd, pass);
4391 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4392 dead_tmp(tmp3);
9ee6e8bb 4393 break;
2c0262af
FB		 4394 }
4395 break;
9ee6e8bb
PB		 4396 case 4: /* VHSUB */
4397 GEN_NEON_INTEGER_OP(hsub);
4398 break;
4399 case 5: /* VQSUB */
ad69471c 4400 GEN_NEON_INTEGER_OP_ENV(qsub);
2c0262af 4401 break;
9ee6e8bb
PB		 4402 case 6: /* VCGT */
4403 GEN_NEON_INTEGER_OP(cgt);
4404 break;
4405 case 7: /* VCGE */
4406 GEN_NEON_INTEGER_OP(cge);
4407 break;
4408 case 8: /* VSHL */
ad69471c 4409 GEN_NEON_INTEGER_OP(shl);
2c0262af 4410 break;
9ee6e8bb 4411 case 9: /* VQSHL */
ad69471c 4412 GEN_NEON_INTEGER_OP_ENV(qshl);
2c0262af 4413 break;
9ee6e8bb 4414 case 10: /* VRSHL */
ad69471c 4415 GEN_NEON_INTEGER_OP(rshl);
2c0262af 4416 break;
9ee6e8bb 4417 case 11: /* VQRSHL */
ad69471c 4418 GEN_NEON_INTEGER_OP_ENV(qrshl);
9ee6e8bb
PB		 4419 break;
4420 case 12: /* VMAX */
4421 GEN_NEON_INTEGER_OP(max);
4422 break;
4423 case 13: /* VMIN */
4424 GEN_NEON_INTEGER_OP(min);
4425 break;
4426 case 14: /* VABD */
4427 GEN_NEON_INTEGER_OP(abd);
4428 break;
4429 case 15: /* VABA */
4430 GEN_NEON_INTEGER_OP(abd);
dd8fbd78
FN		 4431 dead_tmp(tmp2);
4432 tmp2 = neon_load_reg(rd, pass);
4433 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4434 break;
4435 case 16:
4436 if (!u) { /* VADD */
dd8fbd78 4437 if (gen_neon_add(size, tmp, tmp2))
9ee6e8bb
PB		 4438 return 1;
4439 } else { /* VSUB */
4440 switch (size) {
dd8fbd78
FN		 4441 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4442 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4443 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4444 default: return 1;
4445 }
4446 }
4447 break;
4448 case 17:
4449 if (!u) { /* VTST */
4450 switch (size) {
dd8fbd78
FN		 4451 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4452 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4453 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4454 default: return 1;
4455 }
4456 } else { /* VCEQ */
4457 switch (size) {
dd8fbd78
FN		 4458 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4459 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4460 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4461 default: return 1;
4462 }
4463 }
4464 break;
4465 case 18: /* Multiply. */
4466 switch (size) {
dd8fbd78
FN		 4467 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4468 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4469 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4470 default: return 1;
4471 }
dd8fbd78
FN		 4472 dead_tmp(tmp2);
4473 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4474 if (u) { /* VMLS */
dd8fbd78 4475 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb 4476 } else { /* VMLA */
dd8fbd78 4477 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 4478 }
4479 break;
4480 case 19: /* VMUL */
4481 if (u) { /* polynomial */
dd8fbd78 4482 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
9ee6e8bb
PB		 4483 } else { /* Integer */
4484 switch (size) {
dd8fbd78
FN		 4485 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4486 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4487 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4488 default: return 1;
4489 }
4490 }
4491 break;
4492 case 20: /* VPMAX */
4493 GEN_NEON_INTEGER_OP(pmax);
4494 break;
4495 case 21: /* VPMIN */
4496 GEN_NEON_INTEGER_OP(pmin);
4497 break;
4498 case 22: /* Hultiply high. */
4499 if (!u) { /* VQDMULH */
4500 switch (size) {
dd8fbd78
FN		 4501 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4502 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4503 default: return 1;
4504 }
4505 } else { /* VQRDHMUL */
4506 switch (size) {
dd8fbd78
FN		 4507 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4508 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
9ee6e8bb
PB		 4509 default: return 1;
4510 }
4511 }
4512 break;
4513 case 23: /* VPADD */
4514 if (u)
4515 return 1;
4516 switch (size) {
dd8fbd78
FN		 4517 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4518 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4519 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 4520 default: return 1;
4521 }
4522 break;
4523 case 26: /* Floating point arithnetic. */
4524 switch ((u << 2) | size) {
4525 case 0: /* VADD */
dd8fbd78 4526 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4527 break;
4528 case 2: /* VSUB */
dd8fbd78 4529 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4530 break;
4531 case 4: /* VPADD */
dd8fbd78 4532 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4533 break;
4534 case 6: /* VABD */
dd8fbd78 4535 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4536 break;
4537 default:
4538 return 1;
4539 }
4540 break;
4541 case 27: /* Float multiply. */
dd8fbd78 4542 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb 4543 if (!u) {
dd8fbd78
FN		 4544 dead_tmp(tmp2);
4545 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 4546 if (size == 0) {
dd8fbd78 4547 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb 4548 } else {
dd8fbd78 4549 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 4550 }
4551 }
4552 break;
4553 case 28: /* Float compare. */
4554 if (!u) {
dd8fbd78 4555 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
b5ff1b31 4556 } else {
9ee6e8bb 4557 if (size == 0)
dd8fbd78 4558 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
9ee6e8bb 4559 else
dd8fbd78 4560 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
b5ff1b31 4561 }
2c0262af 4562 break;
9ee6e8bb
PB		 4563 case 29: /* Float compare absolute. */
4564 if (!u)
4565 return 1;
4566 if (size == 0)
dd8fbd78 4567 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
9ee6e8bb 4568 else
dd8fbd78 4569 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
2c0262af 4570 break;
9ee6e8bb
PB		 4571 case 30: /* Float min/max. */
4572 if (size == 0)
dd8fbd78 4573 gen_helper_neon_max_f32(tmp, tmp, tmp2);
9ee6e8bb 4574 else
dd8fbd78 4575 gen_helper_neon_min_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 4576 break;
4577 case 31:
4578 if (size == 0)
dd8fbd78 4579 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
9ee6e8bb 4580 else
dd8fbd78 4581 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
2c0262af 4582 break;
9ee6e8bb
PB		 4583 default:
4584 abort();
2c0262af 4585 }
dd8fbd78
FN		 4586 dead_tmp(tmp2);
4587
9ee6e8bb
PB		 4588 /* Save the result. For elementwise operations we can put it
4589 straight into the destination register. For pairwise operations
4590 we have to be careful to avoid clobbering the source operands. */
4591 if (pairwise && rd == rm) {
dd8fbd78 4592 neon_store_scratch(pass, tmp);
9ee6e8bb 4593 } else {
dd8fbd78 4594 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4595 }
4596
4597 } /* for pass */
4598 if (pairwise && rd == rm) {
4599 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 4600 tmp = neon_load_scratch(pass);
4601 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4602 }
4603 }
ad69471c 4604 /* End of 3 register same size operations. */
9ee6e8bb
PB		 4605 } else if (insn & (1 << 4)) {
4606 if ((insn & 0x00380080) != 0) {
4607 /* Two registers and shift. */
4608 op = (insn >> 8) & 0xf;
4609 if (insn & (1 << 7)) {
4610 /* 64-bit shift. */
4611 size = 3;
4612 } else {
4613 size = 2;
4614 while ((insn & (1 << (size + 19))) == 0)
4615 size--;
4616 }
4617 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4618 /* To avoid excessive dumplication of ops we implement shift
4619 by immediate using the variable shift operations. */
4620 if (op < 8) {
4621 /* Shift by immediate:
4622 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4623 /* Right shifts are encoded as N - shift, where N is the
4624 element size in bits. */
4625 if (op <= 4)
4626 shift = shift - (1 << (size + 3));
9ee6e8bb
PB		 4627 if (size == 3) {
4628 count = q + 1;
4629 } else {
4630 count = q ? 4: 2;
4631 }
4632 switch (size) {
4633 case 0:
4634 imm = (uint8_t) shift;
4635 imm |= imm << 8;
4636 imm |= imm << 16;
4637 break;
4638 case 1:
4639 imm = (uint16_t) shift;
4640 imm |= imm << 16;
4641 break;
4642 case 2:
4643 case 3:
4644 imm = shift;
4645 break;
4646 default:
4647 abort();
4648 }
4649
4650 for (pass = 0; pass < count; pass++) {
ad69471c
PB		 4651 if (size == 3) {
4652 neon_load_reg64(cpu_V0, rm + pass);
4653 tcg_gen_movi_i64(cpu_V1, imm);
4654 switch (op) {
4655 case 0: /* VSHR */
4656 case 1: /* VSRA */
4657 if (u)
4658 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4659 else
ad69471c 4660 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4661 break;
ad69471c
PB		 4662 case 2: /* VRSHR */
4663 case 3: /* VRSRA */
4664 if (u)
4665 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4666 else
ad69471c 4667 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
9ee6e8bb 4668 break;
ad69471c
PB		 4669 case 4: /* VSRI */
4670 if (!u)
4671 return 1;
4672 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4673 break;
4674 case 5: /* VSHL, VSLI */
4675 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4676 break;
0322b26e
PM		 4677 case 6: /* VQSHLU */
4678 if (u) {
4679 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4680 cpu_V0, cpu_V1);
4681 } else {
4682 return 1;
4683 }
ad69471c 4684 break;
0322b26e
PM		 4685 case 7: /* VQSHL */
4686 if (u) {
4687 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4688 cpu_V0, cpu_V1);
4689 } else {
4690 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4691 cpu_V0, cpu_V1);
4692 }
9ee6e8bb 4693 break;
9ee6e8bb 4694 }
ad69471c
PB		 4695 if (op == 1 || op == 3) {
4696 /* Accumulate. */
5371cb81 4697 neon_load_reg64(cpu_V1, rd + pass);
ad69471c
PB		 4698 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4699 } else if (op == 4 || (op == 5 && u)) {
4700 /* Insert */
923e6509
CL		 4701 neon_load_reg64(cpu_V1, rd + pass);
4702 uint64_t mask;
4703 if (shift < -63 || shift > 63) {
4704 mask = 0;
4705 } else {
4706 if (op == 4) {
4707 mask = 0xffffffffffffffffull >> -shift;
4708 } else {
4709 mask = 0xffffffffffffffffull << shift;
4710 }
4711 }
4712 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4713 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
ad69471c
PB		 4714 }
4715 neon_store_reg64(cpu_V0, rd + pass);
4716 } else { /* size < 3 */
4717 /* Operands in T0 and T1. */
dd8fbd78
FN		 4718 tmp = neon_load_reg(rm, pass);
4719 tmp2 = new_tmp();
4720 tcg_gen_movi_i32(tmp2, imm);
ad69471c
PB		 4721 switch (op) {
4722 case 0: /* VSHR */
4723 case 1: /* VSRA */
4724 GEN_NEON_INTEGER_OP(shl);
4725 break;
4726 case 2: /* VRSHR */
4727 case 3: /* VRSRA */
4728 GEN_NEON_INTEGER_OP(rshl);
4729 break;
4730 case 4: /* VSRI */
4731 if (!u)
4732 return 1;
4733 GEN_NEON_INTEGER_OP(shl);
4734 break;
4735 case 5: /* VSHL, VSLI */
4736 switch (size) {
dd8fbd78
FN		 4737 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4738 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4739 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
ad69471c
PB		 4740 default: return 1;
4741 }
4742 break;
0322b26e
PM		 4743 case 6: /* VQSHLU */
4744 if (!u) {
4745 return 1;
4746 }
ad69471c 4747 switch (size) {
0322b26e
PM		 4748 case 0:
4749 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4750 tmp, tmp2);
4751 break;
4752 case 1:
4753 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4754 tmp, tmp2);
4755 break;
4756 case 2:
4757 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4758 tmp, tmp2);
4759 break;
4760 default:
4761 return 1;
ad69471c
PB		 4762 }
4763 break;
0322b26e
PM		 4764 case 7: /* VQSHL */
4765 GEN_NEON_INTEGER_OP_ENV(qshl);
4766 break;
ad69471c 4767 }
dd8fbd78 4768 dead_tmp(tmp2);
ad69471c
PB		 4769
4770 if (op == 1 || op == 3) {
4771 /* Accumulate. */
dd8fbd78 4772 tmp2 = neon_load_reg(rd, pass);
5371cb81 4773 gen_neon_add(size, tmp, tmp2);
dd8fbd78 4774 dead_tmp(tmp2);
ad69471c
PB		 4775 } else if (op == 4 || (op == 5 && u)) {
4776 /* Insert */
4777 switch (size) {
4778 case 0:
4779 if (op == 4)
ca9a32e4 4780 mask = 0xff >> -shift;
ad69471c 4781 else
ca9a32e4
JR		 4782 mask = (uint8_t)(0xff << shift);
4783 mask |= mask << 8;
4784 mask |= mask << 16;
ad69471c
PB		 4785 break;
4786 case 1:
4787 if (op == 4)
ca9a32e4 4788 mask = 0xffff >> -shift;
ad69471c 4789 else
ca9a32e4
JR		 4790 mask = (uint16_t)(0xffff << shift);
4791 mask |= mask << 16;
ad69471c
PB		 4792 break;
4793 case 2:
ca9a32e4
JR		 4794 if (shift < -31 || shift > 31) {
4795 mask = 0;
4796 } else {
4797 if (op == 4)
4798 mask = 0xffffffffu >> -shift;
4799 else
4800 mask = 0xffffffffu << shift;
4801 }
ad69471c
PB		 4802 break;
4803 default:
4804 abort();
4805 }
dd8fbd78 4806 tmp2 = neon_load_reg(rd, pass);
ca9a32e4
JR		 4807 tcg_gen_andi_i32(tmp, tmp, mask);
4808 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
dd8fbd78
FN		 4809 tcg_gen_or_i32(tmp, tmp, tmp2);
4810 dead_tmp(tmp2);
ad69471c 4811 }
dd8fbd78 4812 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 4813 }
4814 } /* for pass */
4815 } else if (op < 10) {
ad69471c 4816 /* Shift by immediate and narrow:
9ee6e8bb
PB		 4817 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4818 shift = shift - (1 << (size + 3));
4819 size++;
9ee6e8bb
PB		 4820 switch (size) {
4821 case 1:
ad69471c 4822 imm = (uint16_t)shift;
9ee6e8bb 4823 imm |= imm << 16;
ad69471c 4824 tmp2 = tcg_const_i32(imm);
a7812ae4 4825 TCGV_UNUSED_I64(tmp64);
9ee6e8bb
PB		 4826 break;
4827 case 2:
ad69471c
PB		 4828 imm = (uint32_t)shift;
4829 tmp2 = tcg_const_i32(imm);
a7812ae4 4830 TCGV_UNUSED_I64(tmp64);
4cc633c3 4831 break;
9ee6e8bb 4832 case 3:
a7812ae4
PB		 4833 tmp64 = tcg_const_i64(shift);
4834 TCGV_UNUSED(tmp2);
9ee6e8bb
PB		 4835 break;
4836 default:
4837 abort();
4838 }
4839
ad69471c
PB		 4840 for (pass = 0; pass < 2; pass++) {
4841 if (size == 3) {
4842 neon_load_reg64(cpu_V0, rm + pass);
4843 if (q) {
4844 if (u)
a7812ae4 4845 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4846 else
a7812ae4 4847 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c
PB		 4848 } else {
4849 if (u)
a7812ae4 4850 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
ad69471c 4851 else
a7812ae4 4852 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
ad69471c 4853 }
2c0262af 4854 } else {
ad69471c
PB		 4855 tmp = neon_load_reg(rm + pass, 0);
4856 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
36aa55dc
PB		 4857 tmp3 = neon_load_reg(rm + pass, 1);
4858 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4859 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
ad69471c 4860 dead_tmp(tmp);
36aa55dc 4861 dead_tmp(tmp3);
9ee6e8bb 4862 }
ad69471c
PB		 4863 tmp = new_tmp();
4864 if (op == 8 && !u) {
4865 gen_neon_narrow(size - 1, tmp, cpu_V0);
9ee6e8bb 4866 } else {
ad69471c
PB		 4867 if (op == 8)
4868 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
9ee6e8bb 4869 else
ad69471c
PB		 4870 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4871 }
2301db49 4872 neon_store_reg(rd, pass, tmp);
9ee6e8bb 4873 } /* for pass */
b75263d6
JR		 4874 if (size == 3) {
4875 tcg_temp_free_i64(tmp64);
2301db49 4876 } else {
c6067f04 4877 tcg_temp_free_i32(tmp2);
b75263d6 4878 }
9ee6e8bb
PB		 4879 } else if (op == 10) {
4880 /* VSHLL */
ad69471c 4881 if (q || size == 3)
9ee6e8bb 4882 return 1;
ad69471c
PB		 4883 tmp = neon_load_reg(rm, 0);
4884 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 4885 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 4886 if (pass == 1)
4887 tmp = tmp2;
4888
4889 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb 4890
9ee6e8bb
PB		 4891 if (shift != 0) {
4892 /* The shift is less than the width of the source
ad69471c
PB		 4893 type, so we can just shift the whole register. */
4894 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
acdf01ef
CL		 4895 /* Widen the result of shift: we need to clear
4896 * the potential overflow bits resulting from
4897 * left bits of the narrow input appearing as
4898 * right bits of left the neighbour narrow
4899 * input. */
ad69471c
PB		 4900 if (size < 2 || !u) {
4901 uint64_t imm64;
4902 if (size == 0) {
4903 imm = (0xffu >> (8 - shift));
4904 imm |= imm << 16;
acdf01ef 4905 } else if (size == 1) {
ad69471c 4906 imm = 0xffff >> (16 - shift);
acdf01ef
CL		 4907 } else {
4908 /* size == 2 */
4909 imm = 0xffffffff >> (32 - shift);
4910 }
4911 if (size < 2) {
4912 imm64 = imm | (((uint64_t)imm) << 32);
4913 } else {
4914 imm64 = imm;
9ee6e8bb 4915 }
acdf01ef 4916 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
9ee6e8bb
PB		 4917 }
4918 }
ad69471c 4919 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 4920 }
f73534a5 4921 } else if (op >= 14) {
9ee6e8bb 4922 /* VCVT fixed-point. */
f73534a5
PM		 4923 /* We have already masked out the must-be-1 top bit of imm6,
4924 * hence this 32-shift where the ARM ARM has 64-imm6.
4925 */
4926 shift = 32 - shift;
9ee6e8bb 4927 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4373f3ce 4928 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
f73534a5 4929 if (!(op & 1)) {
9ee6e8bb 4930 if (u)
4373f3ce 4931 gen_vfp_ulto(0, shift);
9ee6e8bb 4932 else
4373f3ce 4933 gen_vfp_slto(0, shift);
9ee6e8bb
PB		 4934 } else {
4935 if (u)
4373f3ce 4936 gen_vfp_toul(0, shift);
9ee6e8bb 4937 else
4373f3ce 4938 gen_vfp_tosl(0, shift);
2c0262af 4939 }
4373f3ce 4940 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
2c0262af
FB		 4941 }
4942 } else {
9ee6e8bb
PB		 4943 return 1;
4944 }
4945 } else { /* (insn & 0x00380080) == 0 */
4946 int invert;
4947
4948 op = (insn >> 8) & 0xf;
4949 /* One register and immediate. */
4950 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4951 invert = (insn & (1 << 5)) != 0;
4952 switch (op) {
4953 case 0: case 1:
4954 /* no-op */
4955 break;
4956 case 2: case 3:
4957 imm <<= 8;
4958 break;
4959 case 4: case 5:
4960 imm <<= 16;
4961 break;
4962 case 6: case 7:
4963 imm <<= 24;
4964 break;
4965 case 8: case 9:
4966 imm |= imm << 16;
4967 break;
4968 case 10: case 11:
4969 imm = (imm << 8) | (imm << 24);
4970 break;
4971 case 12:
8e31209e 4972 imm = (imm << 8) | 0xff;
9ee6e8bb
PB		 4973 break;
4974 case 13:
4975 imm = (imm << 16) | 0xffff;
4976 break;
4977 case 14:
4978 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4979 if (invert)
4980 imm = ~imm;
4981 break;
4982 case 15:
4983 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4984 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4985 break;
4986 }
4987 if (invert)
4988 imm = ~imm;
4989
9ee6e8bb
PB		 4990 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4991 if (op & 1 && op < 12) {
ad69471c 4992 tmp = neon_load_reg(rd, pass);
9ee6e8bb
PB		 4993 if (invert) {
4994 /* The immediate value has already been inverted, so
4995 BIC becomes AND. */
ad69471c 4996 tcg_gen_andi_i32(tmp, tmp, imm);
9ee6e8bb 4997 } else {
ad69471c 4998 tcg_gen_ori_i32(tmp, tmp, imm);
9ee6e8bb 4999 }
9ee6e8bb 5000 } else {
ad69471c
PB		 5001 /* VMOV, VMVN. */
5002 tmp = new_tmp();
9ee6e8bb 5003 if (op == 14 && invert) {
ad69471c
PB		 5004 uint32_t val;
5005 val = 0;
9ee6e8bb
PB		 5006 for (n = 0; n < 4; n++) {
5007 if (imm & (1 << (n + (pass & 1) * 4)))
ad69471c 5008 val |= 0xff << (n * 8);
9ee6e8bb 5009 }
ad69471c
PB		 5010 tcg_gen_movi_i32(tmp, val);
5011 } else {
5012 tcg_gen_movi_i32(tmp, imm);
9ee6e8bb 5013 }
9ee6e8bb 5014 }
ad69471c 5015 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5016 }
5017 }
e4b3861d 5018 } else { /* (insn & 0x00800010 == 0x00800000) */
9ee6e8bb
PB		 5019 if (size != 3) {
5020 op = (insn >> 8) & 0xf;
5021 if ((insn & (1 << 6)) == 0) {
5022 /* Three registers of different lengths. */
5023 int src1_wide;
5024 int src2_wide;
5025 int prewiden;
5026 /* prewiden, src1_wide, src2_wide */
5027 static const int neon_3reg_wide[16][3] = {
5028 {1, 0, 0}, /* VADDL */
5029 {1, 1, 0}, /* VADDW */
5030 {1, 0, 0}, /* VSUBL */
5031 {1, 1, 0}, /* VSUBW */
5032 {0, 1, 1}, /* VADDHN */
5033 {0, 0, 0}, /* VABAL */
5034 {0, 1, 1}, /* VSUBHN */
5035 {0, 0, 0}, /* VABDL */
5036 {0, 0, 0}, /* VMLAL */
5037 {0, 0, 0}, /* VQDMLAL */
5038 {0, 0, 0}, /* VMLSL */
5039 {0, 0, 0}, /* VQDMLSL */
5040 {0, 0, 0}, /* Integer VMULL */
5041 {0, 0, 0}, /* VQDMULL */
5042 {0, 0, 0} /* Polynomial VMULL */
5043 };
5044
5045 prewiden = neon_3reg_wide[op][0];
5046 src1_wide = neon_3reg_wide[op][1];
5047 src2_wide = neon_3reg_wide[op][2];
5048
ad69471c
PB		 5049 if (size == 0 && (op == 9 || op == 11 || op == 13))
5050 return 1;
5051
9ee6e8bb
PB		 5052 /* Avoid overlapping operands. Wide source operands are
5053 always aligned so will never overlap with wide
5054 destinations in problematic ways. */
8f8e3aa4 5055 if (rd == rm && !src2_wide) {
dd8fbd78
FN		 5056 tmp = neon_load_reg(rm, 1);
5057 neon_store_scratch(2, tmp);
8f8e3aa4 5058 } else if (rd == rn && !src1_wide) {
dd8fbd78
FN		 5059 tmp = neon_load_reg(rn, 1);
5060 neon_store_scratch(2, tmp);
9ee6e8bb 5061 }
a50f5b91 5062 TCGV_UNUSED(tmp3);
9ee6e8bb 5063 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5064 if (src1_wide) {
5065 neon_load_reg64(cpu_V0, rn + pass);
a50f5b91 5066 TCGV_UNUSED(tmp);
9ee6e8bb 5067 } else {
ad69471c 5068 if (pass == 1 && rd == rn) {
dd8fbd78 5069 tmp = neon_load_scratch(2);
9ee6e8bb 5070 } else {
ad69471c
PB		 5071 tmp = neon_load_reg(rn, pass);
5072 }
5073 if (prewiden) {
5074 gen_neon_widen(cpu_V0, tmp, size, u);
9ee6e8bb
PB		 5075 }
5076 }
ad69471c
PB		 5077 if (src2_wide) {
5078 neon_load_reg64(cpu_V1, rm + pass);
a50f5b91 5079 TCGV_UNUSED(tmp2);
9ee6e8bb 5080 } else {
ad69471c 5081 if (pass == 1 && rd == rm) {
dd8fbd78 5082 tmp2 = neon_load_scratch(2);
9ee6e8bb 5083 } else {
ad69471c
PB		 5084 tmp2 = neon_load_reg(rm, pass);
5085 }
5086 if (prewiden) {
5087 gen_neon_widen(cpu_V1, tmp2, size, u);
9ee6e8bb 5088 }
9ee6e8bb
PB		 5089 }
5090 switch (op) {
5091 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
ad69471c 5092 gen_neon_addl(size);
9ee6e8bb 5093 break;
79b0e534 5094 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
ad69471c 5095 gen_neon_subl(size);
9ee6e8bb
PB		 5096 break;
5097 case 5: case 7: /* VABAL, VABDL */
5098 switch ((size << 1) | u) {
ad69471c
PB		 5099 case 0:
5100 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5101 break;
5102 case 1:
5103 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5104 break;
5105 case 2:
5106 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5107 break;
5108 case 3:
5109 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5110 break;
5111 case 4:
5112 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5113 break;
5114 case 5:
5115 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5116 break;
9ee6e8bb
PB		 5117 default: abort();
5118 }
ad69471c
PB		 5119 dead_tmp(tmp2);
5120 dead_tmp(tmp);
9ee6e8bb
PB		 5121 break;
5122 case 8: case 9: case 10: case 11: case 12: case 13:
5123 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
ad69471c 5124 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
9ee6e8bb
PB		 5125 break;
5126 case 14: /* Polynomial VMULL */
e5ca24cb
PM		 5127 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
5128 dead_tmp(tmp2);
5129 dead_tmp(tmp);
5130 break;
9ee6e8bb
PB		 5131 default: /* 15 is RESERVED. */
5132 return 1;
5133 }
ebcd88ce
PM		 5134 if (op == 13) {
5135 /* VQDMULL */
5136 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5137 neon_store_reg64(cpu_V0, rd + pass);
5138 } else if (op == 5 || (op >= 8 && op <= 11)) {
9ee6e8bb 5139 /* Accumulate. */
ebcd88ce 5140 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5141 switch (op) {
4dc064e6
PM		 5142 case 10: /* VMLSL */
5143 gen_neon_negl(cpu_V0, size);
5144 /* Fall through */
5145 case 5: case 8: /* VABAL, VMLAL */
ad69471c 5146 gen_neon_addl(size);
9ee6e8bb
PB		 5147 break;
5148 case 9: case 11: /* VQDMLAL, VQDMLSL */
ad69471c 5149 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5150 if (op == 11) {
5151 gen_neon_negl(cpu_V0, size);
5152 }
ad69471c
PB		 5153 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5154 break;
9ee6e8bb
PB		 5155 default:
5156 abort();
5157 }
ad69471c 5158 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5159 } else if (op == 4 || op == 6) {
5160 /* Narrowing operation. */
ad69471c 5161 tmp = new_tmp();
79b0e534 5162 if (!u) {
9ee6e8bb 5163 switch (size) {
ad69471c
PB		 5164 case 0:
5165 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5166 break;
5167 case 1:
5168 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5169 break;
5170 case 2:
5171 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5172 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5173 break;
9ee6e8bb
PB		 5174 default: abort();
5175 }
5176 } else {
5177 switch (size) {
ad69471c
PB		 5178 case 0:
5179 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5180 break;
5181 case 1:
5182 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5183 break;
5184 case 2:
5185 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5186 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5187 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5188 break;
9ee6e8bb
PB		 5189 default: abort();
5190 }
5191 }
ad69471c
PB		 5192 if (pass == 0) {
5193 tmp3 = tmp;
5194 } else {
5195 neon_store_reg(rd, 0, tmp3);
5196 neon_store_reg(rd, 1, tmp);
5197 }
9ee6e8bb
PB		 5198 } else {
5199 /* Write back the result. */
ad69471c 5200 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5201 }
5202 }
5203 } else {
5204 /* Two registers and a scalar. */
5205 switch (op) {
5206 case 0: /* Integer VMLA scalar */
5207 case 1: /* Float VMLA scalar */
5208 case 4: /* Integer VMLS scalar */
5209 case 5: /* Floating point VMLS scalar */
5210 case 8: /* Integer VMUL scalar */
5211 case 9: /* Floating point VMUL scalar */
5212 case 12: /* VQDMULH scalar */
5213 case 13: /* VQRDMULH scalar */
dd8fbd78
FN		 5214 tmp = neon_get_scalar(size, rm);
5215 neon_store_scratch(0, tmp);
9ee6e8bb 5216 for (pass = 0; pass < (u ? 4 : 2); pass++) {
dd8fbd78
FN		 5217 tmp = neon_load_scratch(0);
5218 tmp2 = neon_load_reg(rn, pass);
9ee6e8bb
PB		 5219 if (op == 12) {
5220 if (size == 1) {
dd8fbd78 5221 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5222 } else {
dd8fbd78 5223 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5224 }
5225 } else if (op == 13) {
5226 if (size == 1) {
dd8fbd78 5227 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
9ee6e8bb 5228 } else {
dd8fbd78 5229 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
9ee6e8bb
PB		 5230 }
5231 } else if (op & 1) {
dd8fbd78 5232 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5233 } else {
5234 switch (size) {
dd8fbd78
FN		 5235 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5236 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5237 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5238 default: return 1;
5239 }
5240 }
dd8fbd78 5241 dead_tmp(tmp2);
9ee6e8bb
PB		 5242 if (op < 8) {
5243 /* Accumulate. */
dd8fbd78 5244 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb
PB		 5245 switch (op) {
5246 case 0:
dd8fbd78 5247 gen_neon_add(size, tmp, tmp2);
9ee6e8bb
PB		 5248 break;
5249 case 1:
dd8fbd78 5250 gen_helper_neon_add_f32(tmp, tmp, tmp2);
9ee6e8bb
PB		 5251 break;
5252 case 4:
dd8fbd78 5253 gen_neon_rsb(size, tmp, tmp2);
9ee6e8bb
PB		 5254 break;
5255 case 5:
dd8fbd78 5256 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
9ee6e8bb
PB		 5257 break;
5258 default:
5259 abort();
5260 }
dd8fbd78 5261 dead_tmp(tmp2);
9ee6e8bb 5262 }
dd8fbd78 5263 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5264 }
5265 break;
5266 case 2: /* VMLAL sclar */
5267 case 3: /* VQDMLAL scalar */
5268 case 6: /* VMLSL scalar */
5269 case 7: /* VQDMLSL scalar */
5270 case 10: /* VMULL scalar */
5271 case 11: /* VQDMULL scalar */
ad69471c
PB		 5272 if (size == 0 && (op == 3 || op == 7 || op == 11))
5273 return 1;
5274
dd8fbd78 5275 tmp2 = neon_get_scalar(size, rm);
c6067f04
CL		 5276 /* We need a copy of tmp2 because gen_neon_mull
5277 * deletes it during pass 0. */
5278 tmp4 = new_tmp();
5279 tcg_gen_mov_i32(tmp4, tmp2);
dd8fbd78 5280 tmp3 = neon_load_reg(rn, 1);
ad69471c 5281
9ee6e8bb 5282 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5283 if (pass == 0) {
5284 tmp = neon_load_reg(rn, 0);
9ee6e8bb 5285 } else {
dd8fbd78 5286 tmp = tmp3;
c6067f04 5287 tmp2 = tmp4;
9ee6e8bb 5288 }
ad69471c 5289 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
ad69471c
PB		 5290 if (op != 11) {
5291 neon_load_reg64(cpu_V1, rd + pass);
9ee6e8bb 5292 }
9ee6e8bb 5293 switch (op) {
4dc064e6
PM		 5294 case 6:
5295 gen_neon_negl(cpu_V0, size);
5296 /* Fall through */
5297 case 2:
ad69471c 5298 gen_neon_addl(size);
9ee6e8bb
PB		 5299 break;
5300 case 3: case 7:
ad69471c 5301 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
4dc064e6
PM		 5302 if (op == 7) {
5303 gen_neon_negl(cpu_V0, size);
5304 }
ad69471c 5305 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
9ee6e8bb
PB		 5306 break;
5307 case 10:
5308 /* no-op */
5309 break;
5310 case 11:
ad69471c 5311 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
9ee6e8bb
PB		 5312 break;
5313 default:
5314 abort();
5315 }
ad69471c 5316 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb 5317 }
dd8fbd78 5318
dd8fbd78 5319
9ee6e8bb
PB		 5320 break;
5321 default: /* 14 and 15 are RESERVED */
5322 return 1;
5323 }
5324 }
5325 } else { /* size == 3 */
5326 if (!u) {
5327 /* Extract. */
9ee6e8bb 5328 imm = (insn >> 8) & 0xf;
ad69471c
PB		 5329
5330 if (imm > 7 && !q)
5331 return 1;
5332
5333 if (imm == 0) {
5334 neon_load_reg64(cpu_V0, rn);
5335 if (q) {
5336 neon_load_reg64(cpu_V1, rn + 1);
9ee6e8bb 5337 }
ad69471c
PB		 5338 } else if (imm == 8) {
5339 neon_load_reg64(cpu_V0, rn + 1);
5340 if (q) {
5341 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5342 }
ad69471c 5343 } else if (q) {
a7812ae4 5344 tmp64 = tcg_temp_new_i64();
ad69471c
PB		 5345 if (imm < 8) {
5346 neon_load_reg64(cpu_V0, rn);
a7812ae4 5347 neon_load_reg64(tmp64, rn + 1);
ad69471c
PB		 5348 } else {
5349 neon_load_reg64(cpu_V0, rn + 1);
a7812ae4 5350 neon_load_reg64(tmp64, rm);
ad69471c
PB		 5351 }
5352 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
a7812ae4 5353 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
ad69471c
PB		 5354 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5355 if (imm < 8) {
5356 neon_load_reg64(cpu_V1, rm);
9ee6e8bb 5357 } else {
ad69471c
PB		 5358 neon_load_reg64(cpu_V1, rm + 1);
5359 imm -= 8;
9ee6e8bb 5360 }
ad69471c 5361 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
a7812ae4
PB		 5362 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5363 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
b75263d6 5364 tcg_temp_free_i64(tmp64);
ad69471c 5365 } else {
a7812ae4 5366 /* BUGFIX */
ad69471c 5367 neon_load_reg64(cpu_V0, rn);
a7812ae4 5368 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
ad69471c 5369 neon_load_reg64(cpu_V1, rm);
a7812ae4 5370 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
ad69471c
PB		 5371 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5372 }
5373 neon_store_reg64(cpu_V0, rd);
5374 if (q) {
5375 neon_store_reg64(cpu_V1, rd + 1);
9ee6e8bb
PB		 5376 }
5377 } else if ((insn & (1 << 11)) == 0) {
5378 /* Two register misc. */
5379 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5380 size = (insn >> 18) & 3;
5381 switch (op) {
5382 case 0: /* VREV64 */
5383 if (size == 3)
5384 return 1;
5385 for (pass = 0; pass < (q ? 2 : 1); pass++) {
dd8fbd78
FN		 5386 tmp = neon_load_reg(rm, pass * 2);
5387 tmp2 = neon_load_reg(rm, pass * 2 + 1);
9ee6e8bb 5388 switch (size) {
dd8fbd78
FN		 5389 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5390 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5391 case 2: /* no-op */ break;
5392 default: abort();
5393 }
dd8fbd78 5394 neon_store_reg(rd, pass * 2 + 1, tmp);
9ee6e8bb 5395 if (size == 2) {
dd8fbd78 5396 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb 5397 } else {
9ee6e8bb 5398 switch (size) {
dd8fbd78
FN		 5399 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5400 case 1: gen_swap_half(tmp2); break;
9ee6e8bb
PB		 5401 default: abort();
5402 }
dd8fbd78 5403 neon_store_reg(rd, pass * 2, tmp2);
9ee6e8bb
PB		 5404 }
5405 }
5406 break;
5407 case 4: case 5: /* VPADDL */
5408 case 12: case 13: /* VPADAL */
9ee6e8bb
PB		 5409 if (size == 3)
5410 return 1;
ad69471c
PB		 5411 for (pass = 0; pass < q + 1; pass++) {
5412 tmp = neon_load_reg(rm, pass * 2);
5413 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5414 tmp = neon_load_reg(rm, pass * 2 + 1);
5415 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5416 switch (size) {
5417 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5418 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5419 case 2: tcg_gen_add_i64(CPU_V001); break;
5420 default: abort();
5421 }
9ee6e8bb
PB		 5422 if (op >= 12) {
5423 /* Accumulate. */
ad69471c
PB		 5424 neon_load_reg64(cpu_V1, rd + pass);
5425 gen_neon_addl(size);
9ee6e8bb 5426 }
ad69471c 5427 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5428 }
5429 break;
5430 case 33: /* VTRN */
5431 if (size == 2) {
5432 for (n = 0; n < (q ? 4 : 2); n += 2) {
dd8fbd78
FN		 5433 tmp = neon_load_reg(rm, n);
5434 tmp2 = neon_load_reg(rd, n + 1);
5435 neon_store_reg(rm, n, tmp2);
5436 neon_store_reg(rd, n + 1, tmp);
9ee6e8bb
PB		 5437 }
5438 } else {
5439 goto elementwise;
5440 }
5441 break;
5442 case 34: /* VUZP */
5443 /* Reg Before After
5444 Rd A3 A2 A1 A0 B2 B0 A2 A0
5445 Rm B3 B2 B1 B0 B3 B1 A3 A1
5446 */
5447 if (size == 3)
5448 return 1;
5449 gen_neon_unzip(rd, q, 0, size);
5450 gen_neon_unzip(rm, q, 4, size);
5451 if (q) {
5452 static int unzip_order_q[8] =
5453 {0, 2, 4, 6, 1, 3, 5, 7};
5454 for (n = 0; n < 8; n++) {
5455 int reg = (n < 4) ? rd : rm;
dd8fbd78
FN		 5456 tmp = neon_load_scratch(unzip_order_q[n]);
5457 neon_store_reg(reg, n % 4, tmp);
9ee6e8bb
PB		 5458 }
5459 } else {
5460 static int unzip_order[4] =
5461 {0, 4, 1, 5};
5462 for (n = 0; n < 4; n++) {
5463 int reg = (n < 2) ? rd : rm;
dd8fbd78
FN		 5464 tmp = neon_load_scratch(unzip_order[n]);
5465 neon_store_reg(reg, n % 2, tmp);
9ee6e8bb
PB		 5466 }
5467 }
5468 break;
5469 case 35: /* VZIP */
5470 /* Reg Before After
5471 Rd A3 A2 A1 A0 B1 A1 B0 A0
5472 Rm B3 B2 B1 B0 B3 A3 B2 A2
5473 */
5474 if (size == 3)
5475 return 1;
5476 count = (q ? 4 : 2);
5477 for (n = 0; n < count; n++) {
dd8fbd78
FN		 5478 tmp = neon_load_reg(rd, n);
5479 tmp2 = neon_load_reg(rd, n);
9ee6e8bb 5480 switch (size) {
dd8fbd78
FN		 5481 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5482 case 1: gen_neon_zip_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5483 case 2: /* no-op */; break;
5484 default: abort();
5485 }
dd8fbd78
FN		 5486 neon_store_scratch(n * 2, tmp);
5487 neon_store_scratch(n * 2 + 1, tmp2);
9ee6e8bb
PB		 5488 }
5489 for (n = 0; n < count * 2; n++) {
5490 int reg = (n < count) ? rd : rm;
dd8fbd78
FN		 5491 tmp = neon_load_scratch(n);
5492 neon_store_reg(reg, n % count, tmp);
9ee6e8bb
PB		 5493 }
5494 break;
5495 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
ad69471c
PB		 5496 if (size == 3)
5497 return 1;
a50f5b91 5498 TCGV_UNUSED(tmp2);
9ee6e8bb 5499 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5500 neon_load_reg64(cpu_V0, rm + pass);
5501 tmp = new_tmp();
af1bbf30
JR		 5502 if (op == 36) {
5503 if (q) { /* VQMOVUN */
5504 gen_neon_unarrow_sats(size, tmp, cpu_V0);
5505 } else { /* VMOVN */
5506 gen_neon_narrow(size, tmp, cpu_V0);
5507 }
5508 } else { /* VQMOVN */
5509 if (q) {
5510 gen_neon_narrow_satu(size, tmp, cpu_V0);
5511 } else {
5512 gen_neon_narrow_sats(size, tmp, cpu_V0);
5513 }
ad69471c
PB		 5514 }
5515 if (pass == 0) {
5516 tmp2 = tmp;
5517 } else {
5518 neon_store_reg(rd, 0, tmp2);
5519 neon_store_reg(rd, 1, tmp);
9ee6e8bb 5520 }
9ee6e8bb
PB		 5521 }
5522 break;
5523 case 38: /* VSHLL */
ad69471c 5524 if (q || size == 3)
9ee6e8bb 5525 return 1;
ad69471c
PB		 5526 tmp = neon_load_reg(rm, 0);
5527 tmp2 = neon_load_reg(rm, 1);
9ee6e8bb 5528 for (pass = 0; pass < 2; pass++) {
ad69471c
PB		 5529 if (pass == 1)
5530 tmp = tmp2;
5531 gen_neon_widen(cpu_V0, tmp, size, 1);
30d11a2a 5532 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
ad69471c 5533 neon_store_reg64(cpu_V0, rd + pass);
9ee6e8bb
PB		 5534 }
5535 break;
60011498
PB		 5536 case 44: /* VCVT.F16.F32 */
5537 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5538 return 1;
5539 tmp = new_tmp();
5540 tmp2 = new_tmp();
5541 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
2d981da7 5542 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498 5543 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
2d981da7 5544 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5545 tcg_gen_shli_i32(tmp2, tmp2, 16);
5546 tcg_gen_or_i32(tmp2, tmp2, tmp);
5547 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
2d981da7 5548 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
60011498
PB		 5549 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5550 neon_store_reg(rd, 0, tmp2);
5551 tmp2 = new_tmp();
2d981da7 5552 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
60011498
PB		 5553 tcg_gen_shli_i32(tmp2, tmp2, 16);
5554 tcg_gen_or_i32(tmp2, tmp2, tmp);
5555 neon_store_reg(rd, 1, tmp2);
5556 dead_tmp(tmp);
5557 break;
5558 case 46: /* VCVT.F32.F16 */
5559 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5560 return 1;
5561 tmp3 = new_tmp();
5562 tmp = neon_load_reg(rm, 0);
5563 tmp2 = neon_load_reg(rm, 1);
5564 tcg_gen_ext16u_i32(tmp3, tmp);
2d981da7 5565 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5566 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5567 tcg_gen_shri_i32(tmp3, tmp, 16);
2d981da7 5568 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5569 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5570 dead_tmp(tmp);
5571 tcg_gen_ext16u_i32(tmp3, tmp2);
2d981da7 5572 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5573 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5574 tcg_gen_shri_i32(tmp3, tmp2, 16);
2d981da7 5575 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
60011498
PB		 5576 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5577 dead_tmp(tmp2);
5578 dead_tmp(tmp3);
5579 break;
9ee6e8bb
PB		 5580 default:
5581 elementwise:
5582 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5583 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5584 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5585 neon_reg_offset(rm, pass));
dd8fbd78 5586 TCGV_UNUSED(tmp);
9ee6e8bb 5587 } else {
dd8fbd78 5588 tmp = neon_load_reg(rm, pass);
9ee6e8bb
PB		 5589 }
5590 switch (op) {
5591 case 1: /* VREV32 */
5592 switch (size) {
dd8fbd78
FN		 5593 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5594 case 1: gen_swap_half(tmp); break;
9ee6e8bb
PB		 5595 default: return 1;
5596 }
5597 break;
5598 case 2: /* VREV16 */
5599 if (size != 0)
5600 return 1;
dd8fbd78 5601 gen_rev16(tmp);
9ee6e8bb 5602 break;
9ee6e8bb
PB		 5603 case 8: /* CLS */
5604 switch (size) {
dd8fbd78
FN		 5605 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5606 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5607 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
9ee6e8bb
PB		 5608 default: return 1;
5609 }
5610 break;
5611 case 9: /* CLZ */
5612 switch (size) {
dd8fbd78
FN		 5613 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5614 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5615 case 2: gen_helper_clz(tmp, tmp); break;
9ee6e8bb
PB		 5616 default: return 1;
5617 }
5618 break;
5619 case 10: /* CNT */
5620 if (size != 0)
5621 return 1;
dd8fbd78 5622 gen_helper_neon_cnt_u8(tmp, tmp);
9ee6e8bb
PB		 5623 break;
5624 case 11: /* VNOT */
5625 if (size != 0)
5626 return 1;
dd8fbd78 5627 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5628 break;
5629 case 14: /* VQABS */
5630 switch (size) {
dd8fbd78
FN		 5631 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5632 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5633 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5634 default: return 1;
5635 }
5636 break;
5637 case 15: /* VQNEG */
5638 switch (size) {
dd8fbd78
FN		 5639 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5640 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5641 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
9ee6e8bb
PB		 5642 default: return 1;
5643 }
5644 break;
5645 case 16: case 19: /* VCGT #0, VCLE #0 */
dd8fbd78 5646 tmp2 = tcg_const_i32(0);
9ee6e8bb 5647 switch(size) {
dd8fbd78
FN		 5648 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5649 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5650 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5651 default: return 1;
5652 }
dd8fbd78 5653 tcg_temp_free(tmp2);
9ee6e8bb 5654 if (op == 19)
dd8fbd78 5655 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5656 break;
5657 case 17: case 20: /* VCGE #0, VCLT #0 */
dd8fbd78 5658 tmp2 = tcg_const_i32(0);
9ee6e8bb 5659 switch(size) {
dd8fbd78
FN		 5660 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5661 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5662 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5663 default: return 1;
5664 }
dd8fbd78 5665 tcg_temp_free(tmp2);
9ee6e8bb 5666 if (op == 20)
dd8fbd78 5667 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5668 break;
5669 case 18: /* VCEQ #0 */
dd8fbd78 5670 tmp2 = tcg_const_i32(0);
9ee6e8bb 5671 switch(size) {
dd8fbd78
FN		 5672 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5673 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5674 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
9ee6e8bb
PB		 5675 default: return 1;
5676 }
dd8fbd78 5677 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5678 break;
5679 case 22: /* VABS */
5680 switch(size) {
dd8fbd78
FN		 5681 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5682 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5683 case 2: tcg_gen_abs_i32(tmp, tmp); break;
9ee6e8bb
PB		 5684 default: return 1;
5685 }
5686 break;
5687 case 23: /* VNEG */
ad69471c
PB		 5688 if (size == 3)
5689 return 1;
dd8fbd78
FN		 5690 tmp2 = tcg_const_i32(0);
5691 gen_neon_rsb(size, tmp, tmp2);
5692 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5693 break;
5694 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
dd8fbd78
FN		 5695 tmp2 = tcg_const_i32(0);
5696 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5697 tcg_temp_free(tmp2);
9ee6e8bb 5698 if (op == 27)
dd8fbd78 5699 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5700 break;
5701 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
dd8fbd78
FN		 5702 tmp2 = tcg_const_i32(0);
5703 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5704 tcg_temp_free(tmp2);
9ee6e8bb 5705 if (op == 28)
dd8fbd78 5706 tcg_gen_not_i32(tmp, tmp);
9ee6e8bb
PB		 5707 break;
5708 case 26: /* Float VCEQ #0 */
dd8fbd78
FN		 5709 tmp2 = tcg_const_i32(0);
5710 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5711 tcg_temp_free(tmp2);
9ee6e8bb
PB		 5712 break;
5713 case 30: /* Float VABS */
4373f3ce 5714 gen_vfp_abs(0);
9ee6e8bb
PB		 5715 break;
5716 case 31: /* Float VNEG */
4373f3ce 5717 gen_vfp_neg(0);
9ee6e8bb
PB		 5718 break;
5719 case 32: /* VSWP */
dd8fbd78
FN		 5720 tmp2 = neon_load_reg(rd, pass);
5721 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5722 break;
5723 case 33: /* VTRN */
dd8fbd78 5724 tmp2 = neon_load_reg(rd, pass);
9ee6e8bb 5725 switch (size) {
dd8fbd78
FN		 5726 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5727 case 1: gen_neon_trn_u16(tmp, tmp2); break;
9ee6e8bb
PB		 5728 case 2: abort();
5729 default: return 1;
5730 }
dd8fbd78 5731 neon_store_reg(rm, pass, tmp2);
9ee6e8bb
PB		 5732 break;
5733 case 56: /* Integer VRECPE */
dd8fbd78 5734 gen_helper_recpe_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5735 break;
5736 case 57: /* Integer VRSQRTE */
dd8fbd78 5737 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
9ee6e8bb
PB		 5738 break;
5739 case 58: /* Float VRECPE */
4373f3ce 5740 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5741 break;
5742 case 59: /* Float VRSQRTE */
4373f3ce 5743 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
9ee6e8bb
PB		 5744 break;
5745 case 60: /* VCVT.F32.S32 */
d3587ef8 5746 gen_vfp_sito(0);
9ee6e8bb
PB		 5747 break;
5748 case 61: /* VCVT.F32.U32 */
d3587ef8 5749 gen_vfp_uito(0);
9ee6e8bb
PB		 5750 break;
5751 case 62: /* VCVT.S32.F32 */
d3587ef8 5752 gen_vfp_tosiz(0);
9ee6e8bb
PB		 5753 break;
5754 case 63: /* VCVT.U32.F32 */
d3587ef8 5755 gen_vfp_touiz(0);
9ee6e8bb
PB		 5756 break;
5757 default:
5758 /* Reserved: 21, 29, 39-56 */
5759 return 1;
5760 }
5761 if (op == 30 || op == 31 || op >= 58) {
4373f3ce
PB		 5762 tcg_gen_st_f32(cpu_F0s, cpu_env,
5763 neon_reg_offset(rd, pass));
9ee6e8bb 5764 } else {
dd8fbd78 5765 neon_store_reg(rd, pass, tmp);
9ee6e8bb
PB		 5766 }
5767 }
5768 break;
5769 }
5770 } else if ((insn & (1 << 10)) == 0) {
5771 /* VTBL, VTBX. */
3018f259 5772 n = ((insn >> 5) & 0x18) + 8;
9ee6e8bb 5773 if (insn & (1 << 6)) {
8f8e3aa4 5774 tmp = neon_load_reg(rd, 0);
9ee6e8bb 5775 } else {
8f8e3aa4
PB		 5776 tmp = new_tmp();
5777 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5778 }
8f8e3aa4 5779 tmp2 = neon_load_reg(rm, 0);
b75263d6
JR		 5780 tmp4 = tcg_const_i32(rn);
5781 tmp5 = tcg_const_i32(n);
5782 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
3018f259 5783 dead_tmp(tmp);
9ee6e8bb 5784 if (insn & (1 << 6)) {
8f8e3aa4 5785 tmp = neon_load_reg(rd, 1);
9ee6e8bb 5786 } else {
8f8e3aa4
PB		 5787 tmp = new_tmp();
5788 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 5789 }
8f8e3aa4 5790 tmp3 = neon_load_reg(rm, 1);
b75263d6 5791 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
25aeb69b
JR		 5792 tcg_temp_free_i32(tmp5);
5793 tcg_temp_free_i32(tmp4);
8f8e3aa4 5794 neon_store_reg(rd, 0, tmp2);
3018f259
PB		 5795 neon_store_reg(rd, 1, tmp3);
5796 dead_tmp(tmp);
9ee6e8bb
PB		 5797 } else if ((insn & 0x380) == 0) {
5798 /* VDUP */
5799 if (insn & (1 << 19)) {
dd8fbd78 5800 tmp = neon_load_reg(rm, 1);
9ee6e8bb 5801 } else {
dd8fbd78 5802 tmp = neon_load_reg(rm, 0);
9ee6e8bb
PB		 5803 }
5804 if (insn & (1 << 16)) {
dd8fbd78 5805 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
9ee6e8bb
PB		 5806 } else if (insn & (1 << 17)) {
5807 if ((insn >> 18) & 1)
dd8fbd78 5808 gen_neon_dup_high16(tmp);
9ee6e8bb 5809 else
dd8fbd78 5810 gen_neon_dup_low16(tmp);
9ee6e8bb
PB		 5811 }
5812 for (pass = 0; pass < (q ? 4 : 2); pass++) {
dd8fbd78
FN		 5813 tmp2 = new_tmp();
5814 tcg_gen_mov_i32(tmp2, tmp);
5815 neon_store_reg(rd, pass, tmp2);
9ee6e8bb 5816 }
dd8fbd78 5817 dead_tmp(tmp);
9ee6e8bb
PB		 5818 } else {
5819 return 1;
5820 }
5821 }
5822 }
5823 return 0;
5824}
5825
fe1479c3
PB		 5826static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5827{
5828 int crn = (insn >> 16) & 0xf;
5829 int crm = insn & 0xf;
5830 int op1 = (insn >> 21) & 7;
5831 int op2 = (insn >> 5) & 7;
5832 int rt = (insn >> 12) & 0xf;
5833 TCGv tmp;
5834
5835 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5836 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5837 /* TEECR */
5838 if (IS_USER(s))
5839 return 1;
5840 tmp = load_cpu_field(teecr);
5841 store_reg(s, rt, tmp);
5842 return 0;
5843 }
5844 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5845 /* TEEHBR */
5846 if (IS_USER(s) && (env->teecr & 1))
5847 return 1;
5848 tmp = load_cpu_field(teehbr);
5849 store_reg(s, rt, tmp);
5850 return 0;
5851 }
5852 }
5853 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5854 op1, crn, crm, op2);
5855 return 1;
5856}
5857
5858static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5859{
5860 int crn = (insn >> 16) & 0xf;
5861 int crm = insn & 0xf;
5862 int op1 = (insn >> 21) & 7;
5863 int op2 = (insn >> 5) & 7;
5864 int rt = (insn >> 12) & 0xf;
5865 TCGv tmp;
5866
5867 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5868 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5869 /* TEECR */
5870 if (IS_USER(s))
5871 return 1;
5872 tmp = load_reg(s, rt);
5873 gen_helper_set_teecr(cpu_env, tmp);
5874 dead_tmp(tmp);
5875 return 0;
5876 }
5877 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5878 /* TEEHBR */
5879 if (IS_USER(s) && (env->teecr & 1))
5880 return 1;
5881 tmp = load_reg(s, rt);
5882 store_cpu_field(tmp, teehbr);
5883 return 0;
5884 }
5885 }
5886 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5887 op1, crn, crm, op2);
5888 return 1;
5889}
5890
9ee6e8bb
PB		 5891static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5892{
5893 int cpnum;
5894
5895 cpnum = (insn >> 8) & 0xf;
5896 if (arm_feature(env, ARM_FEATURE_XSCALE)
5897 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5898 return 1;
5899
5900 switch (cpnum) {
5901 case 0:
5902 case 1:
5903 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5904 return disas_iwmmxt_insn(env, s, insn);
5905 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5906 return disas_dsp_insn(env, s, insn);
5907 }
5908 return 1;
5909 case 10:
5910 case 11:
5911 return disas_vfp_insn (env, s, insn);
fe1479c3
PB		 5912 case 14:
5913 /* Coprocessors 7-15 are architecturally reserved by ARM.
5914 Unfortunately Intel decided to ignore this. */
5915 if (arm_feature(env, ARM_FEATURE_XSCALE))
5916 goto board;
5917 if (insn & (1 << 20))
5918 return disas_cp14_read(env, s, insn);
5919 else
5920 return disas_cp14_write(env, s, insn);
9ee6e8bb
PB		 5921 case 15:
5922 return disas_cp15_insn (env, s, insn);
5923 default:
fe1479c3 5924 board:
9ee6e8bb
PB		 5925 /* Unknown coprocessor. See if the board has hooked it. */
5926 return disas_cp_insn (env, s, insn);
5927 }
5928}
5929
5e3f878a
PB		 5930
5931/* Store a 64-bit value to a register pair. Clobbers val. */
a7812ae4 5932static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5e3f878a
PB		 5933{
5934 TCGv tmp;
5935 tmp = new_tmp();
5936 tcg_gen_trunc_i64_i32(tmp, val);
5937 store_reg(s, rlow, tmp);
5938 tmp = new_tmp();
5939 tcg_gen_shri_i64(val, val, 32);
5940 tcg_gen_trunc_i64_i32(tmp, val);
5941 store_reg(s, rhigh, tmp);
5942}
5943
5944/* load a 32-bit value from a register and perform a 64-bit accumulate. */
a7812ae4 5945static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5e3f878a 5946{
a7812ae4 5947 TCGv_i64 tmp;
5e3f878a
PB		 5948 TCGv tmp2;
5949
36aa55dc 5950 /* Load value and extend to 64 bits. */
a7812ae4 5951 tmp = tcg_temp_new_i64();
5e3f878a
PB		 5952 tmp2 = load_reg(s, rlow);
5953 tcg_gen_extu_i32_i64(tmp, tmp2);
5954 dead_tmp(tmp2);
5955 tcg_gen_add_i64(val, val, tmp);
b75263d6 5956 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5957}
5958
5959/* load and add a 64-bit value from a register pair. */
a7812ae4 5960static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5e3f878a 5961{
a7812ae4 5962 TCGv_i64 tmp;
36aa55dc
PB		 5963 TCGv tmpl;
5964 TCGv tmph;
5e3f878a
PB		 5965
5966 /* Load 64-bit value rd:rn. */
36aa55dc
PB		 5967 tmpl = load_reg(s, rlow);
5968 tmph = load_reg(s, rhigh);
a7812ae4 5969 tmp = tcg_temp_new_i64();
36aa55dc
PB		 5970 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5971 dead_tmp(tmpl);
5972 dead_tmp(tmph);
5e3f878a 5973 tcg_gen_add_i64(val, val, tmp);
b75263d6 5974 tcg_temp_free_i64(tmp);
5e3f878a
PB		 5975}
5976
5977/* Set N and Z flags from a 64-bit value. */
a7812ae4 5978static void gen_logicq_cc(TCGv_i64 val)
5e3f878a
PB		 5979{
5980 TCGv tmp = new_tmp();
5981 gen_helper_logicq_cc(tmp, val);
6fbe23d5
PB		 5982 gen_logic_CC(tmp);
5983 dead_tmp(tmp);
5e3f878a
PB		 5984}
5985
426f5abc
PB		 5986/* Load/Store exclusive instructions are implemented by remembering
5987 the value/address loaded, and seeing if these are the same
5988 when the store is performed. This should be is sufficient to implement
5989 the architecturally mandated semantics, and avoids having to monitor
5990 regular stores.
5991
5992 In system emulation mode only one CPU will be running at once, so
5993 this sequence is effectively atomic. In user emulation mode we
5994 throw an exception and handle the atomic operation elsewhere. */
5995static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5996 TCGv addr, int size)
5997{
5998 TCGv tmp;
5999
6000 switch (size) {
6001 case 0:
6002 tmp = gen_ld8u(addr, IS_USER(s));
6003 break;
6004 case 1:
6005 tmp = gen_ld16u(addr, IS_USER(s));
6006 break;
6007 case 2:
6008 case 3:
6009 tmp = gen_ld32(addr, IS_USER(s));
6010 break;
6011 default:
6012 abort();
6013 }
6014 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
6015 store_reg(s, rt, tmp);
6016 if (size == 3) {
2c9adbda
PM		 6017 TCGv tmp2 = new_tmp();
6018 tcg_gen_addi_i32(tmp2, addr, 4);
6019 tmp = gen_ld32(tmp2, IS_USER(s));
6020 dead_tmp(tmp2);
426f5abc
PB		 6021 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
6022 store_reg(s, rt2, tmp);
6023 }
6024 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6025}
6026
6027static void gen_clrex(DisasContext *s)
6028{
6029 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6030}
6031
6032#ifdef CONFIG_USER_ONLY
6033static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6034 TCGv addr, int size)
6035{
6036 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6037 tcg_gen_movi_i32(cpu_exclusive_info,
6038 size | (rd << 4) | (rt << 8) | (rt2 << 12));
bc4a0de0 6039 gen_exception_insn(s, 4, EXCP_STREX);
426f5abc
PB		 6040}
6041#else
6042static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6043 TCGv addr, int size)
6044{
6045 TCGv tmp;
6046 int done_label;
6047 int fail_label;
6048
6049 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6050 [addr] = {Rt};
6051 {Rd} = 0;
6052 } else {
6053 {Rd} = 1;
6054 } */
6055 fail_label = gen_new_label();
6056 done_label = gen_new_label();
6057 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6058 switch (size) {
6059 case 0:
6060 tmp = gen_ld8u(addr, IS_USER(s));
6061 break;
6062 case 1:
6063 tmp = gen_ld16u(addr, IS_USER(s));
6064 break;
6065 case 2:
6066 case 3:
6067 tmp = gen_ld32(addr, IS_USER(s));
6068 break;
6069 default:
6070 abort();
6071 }
6072 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6073 dead_tmp(tmp);
6074 if (size == 3) {
6075 TCGv tmp2 = new_tmp();
6076 tcg_gen_addi_i32(tmp2, addr, 4);
2c9adbda 6077 tmp = gen_ld32(tmp2, IS_USER(s));
426f5abc
PB		 6078 dead_tmp(tmp2);
6079 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6080 dead_tmp(tmp);
6081 }
6082 tmp = load_reg(s, rt);
6083 switch (size) {
6084 case 0:
6085 gen_st8(tmp, addr, IS_USER(s));
6086 break;
6087 case 1:
6088 gen_st16(tmp, addr, IS_USER(s));
6089 break;
6090 case 2:
6091 case 3:
6092 gen_st32(tmp, addr, IS_USER(s));
6093 break;
6094 default:
6095 abort();
6096 }
6097 if (size == 3) {
6098 tcg_gen_addi_i32(addr, addr, 4);
6099 tmp = load_reg(s, rt2);
6100 gen_st32(tmp, addr, IS_USER(s));
6101 }
6102 tcg_gen_movi_i32(cpu_R[rd], 0);
6103 tcg_gen_br(done_label);
6104 gen_set_label(fail_label);
6105 tcg_gen_movi_i32(cpu_R[rd], 1);
6106 gen_set_label(done_label);
6107 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6108}
6109#endif
6110
9ee6e8bb
PB		 6111static void disas_arm_insn(CPUState * env, DisasContext *s)
6112{
6113 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
b26eefb6 6114 TCGv tmp;
3670669c 6115 TCGv tmp2;
6ddbc6e4 6116 TCGv tmp3;
b0109805 6117 TCGv addr;
a7812ae4 6118 TCGv_i64 tmp64;
9ee6e8bb
PB		 6119
6120 insn = ldl_code(s->pc);
6121 s->pc += 4;
6122
6123 /* M variants do not implement ARM mode. */
6124 if (IS_M(env))
6125 goto illegal_op;
6126 cond = insn >> 28;
6127 if (cond == 0xf){
6128 /* Unconditional instructions. */
6129 if (((insn >> 25) & 7) == 1) {
6130 /* NEON Data processing. */
6131 if (!arm_feature(env, ARM_FEATURE_NEON))
6132 goto illegal_op;
6133
6134 if (disas_neon_data_insn(env, s, insn))
6135 goto illegal_op;
6136 return;
6137 }
6138 if ((insn & 0x0f100000) == 0x04000000) {
6139 /* NEON load/store. */
6140 if (!arm_feature(env, ARM_FEATURE_NEON))
6141 goto illegal_op;
6142
6143 if (disas_neon_ls_insn(env, s, insn))
6144 goto illegal_op;
6145 return;
6146 }
3d185e5d
PM		 6147 if (((insn & 0x0f30f000) == 0x0510f000) ||
6148 ((insn & 0x0f30f010) == 0x0710f000)) {
6149 if ((insn & (1 << 22)) == 0) {
6150 /* PLDW; v7MP */
6151 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6152 goto illegal_op;
6153 }
6154 }
6155 /* Otherwise PLD; v5TE+ */
6156 return;
6157 }
6158 if (((insn & 0x0f70f000) == 0x0450f000) ||
6159 ((insn & 0x0f70f010) == 0x0650f000)) {
6160 ARCH(7);
6161 return; /* PLI; V7 */
6162 }
6163 if (((insn & 0x0f700000) == 0x04100000) ||
6164 ((insn & 0x0f700010) == 0x06100000)) {
6165 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6166 goto illegal_op;
6167 }
6168 return; /* v7MP: Unallocated memory hint: must NOP */
6169 }
6170
6171 if ((insn & 0x0ffffdff) == 0x01010000) {
9ee6e8bb
PB		 6172 ARCH(6);
6173 /* setend */
6174 if (insn & (1 << 9)) {
6175 /* BE8 mode not implemented. */
6176 goto illegal_op;
6177 }
6178 return;
6179 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6180 switch ((insn >> 4) & 0xf) {
6181 case 1: /* clrex */
6182 ARCH(6K);
426f5abc 6183 gen_clrex(s);
9ee6e8bb
PB		 6184 return;
6185 case 4: /* dsb */
6186 case 5: /* dmb */
6187 case 6: /* isb */
6188 ARCH(7);
6189 /* We don't emulate caches so these are a no-op. */
6190 return;
6191 default:
6192 goto illegal_op;
6193 }
6194 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6195 /* srs */
c67b6b71 6196 int32_t offset;
9ee6e8bb
PB		 6197 if (IS_USER(s))
6198 goto illegal_op;
6199 ARCH(6);
6200 op1 = (insn & 0x1f);
39ea3d4e
PM		 6201 addr = new_tmp();
6202 tmp = tcg_const_i32(op1);
6203 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6204 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 6205 i = (insn >> 23) & 3;
6206 switch (i) {
6207 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6208 case 1: offset = 0; break; /* IA */
6209 case 2: offset = -8; break; /* DB */
9ee6e8bb
PB		 6210 case 3: offset = 4; break; /* IB */
6211 default: abort();
6212 }
6213 if (offset)
b0109805
PB		 6214 tcg_gen_addi_i32(addr, addr, offset);
6215 tmp = load_reg(s, 14);
6216 gen_st32(tmp, addr, 0);
c67b6b71 6217 tmp = load_cpu_field(spsr);
b0109805
PB		 6218 tcg_gen_addi_i32(addr, addr, 4);
6219 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 6220 if (insn & (1 << 21)) {
6221 /* Base writeback. */
6222 switch (i) {
6223 case 0: offset = -8; break;
c67b6b71
FN		 6224 case 1: offset = 4; break;
6225 case 2: offset = -4; break;
9ee6e8bb
PB		 6226 case 3: offset = 0; break;
6227 default: abort();
6228 }
6229 if (offset)
c67b6b71 6230 tcg_gen_addi_i32(addr, addr, offset);
39ea3d4e
PM		 6231 tmp = tcg_const_i32(op1);
6232 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6233 tcg_temp_free_i32(tmp);
6234 dead_tmp(addr);
b0109805
PB		 6235 } else {
6236 dead_tmp(addr);
9ee6e8bb 6237 }
a990f58f 6238 return;
ea825eee 6239 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
9ee6e8bb 6240 /* rfe */
c67b6b71 6241 int32_t offset;
9ee6e8bb
PB		 6242 if (IS_USER(s))
6243 goto illegal_op;
6244 ARCH(6);
6245 rn = (insn >> 16) & 0xf;
b0109805 6246 addr = load_reg(s, rn);
9ee6e8bb
PB		 6247 i = (insn >> 23) & 3;
6248 switch (i) {
b0109805 6249 case 0: offset = -4; break; /* DA */
c67b6b71
FN		 6250 case 1: offset = 0; break; /* IA */
6251 case 2: offset = -8; break; /* DB */
b0109805 6252 case 3: offset = 4; break; /* IB */
9ee6e8bb
PB		 6253 default: abort();
6254 }
6255 if (offset)
b0109805
PB		 6256 tcg_gen_addi_i32(addr, addr, offset);
6257 /* Load PC into tmp and CPSR into tmp2. */
6258 tmp = gen_ld32(addr, 0);
6259 tcg_gen_addi_i32(addr, addr, 4);
6260 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 6261 if (insn & (1 << 21)) {
6262 /* Base writeback. */
6263 switch (i) {
b0109805 6264 case 0: offset = -8; break;
c67b6b71
FN		 6265 case 1: offset = 4; break;
6266 case 2: offset = -4; break;
b0109805 6267 case 3: offset = 0; break;
9ee6e8bb
PB		 6268 default: abort();
6269 }
6270 if (offset)
b0109805
PB		 6271 tcg_gen_addi_i32(addr, addr, offset);
6272 store_reg(s, rn, addr);
6273 } else {
6274 dead_tmp(addr);
9ee6e8bb 6275 }
b0109805 6276 gen_rfe(s, tmp, tmp2);
c67b6b71 6277 return;
9ee6e8bb
PB		 6278 } else if ((insn & 0x0e000000) == 0x0a000000) {
6279 /* branch link and change to thumb (blx <offset>) */
6280 int32_t offset;
6281
6282 val = (uint32_t)s->pc;
d9ba4830
PB		 6283 tmp = new_tmp();
6284 tcg_gen_movi_i32(tmp, val);
6285 store_reg(s, 14, tmp);
9ee6e8bb
PB		 6286 /* Sign-extend the 24-bit offset */
6287 offset = (((int32_t)insn) << 8) >> 8;
6288 /* offset * 4 + bit24 * 2 + (thumb bit) */
6289 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6290 /* pipeline offset */
6291 val += 4;
d9ba4830 6292 gen_bx_im(s, val);
9ee6e8bb
PB		 6293 return;
6294 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6295 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6296 /* iWMMXt register transfer. */
6297 if (env->cp15.c15_cpar & (1 << 1))
6298 if (!disas_iwmmxt_insn(env, s, insn))
6299 return;
6300 }
6301 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6302 /* Coprocessor double register transfer. */
6303 } else if ((insn & 0x0f000010) == 0x0e000010) {
6304 /* Additional coprocessor register transfer. */
7997d92f 6305 } else if ((insn & 0x0ff10020) == 0x01000000) {
9ee6e8bb
PB		 6306 uint32_t mask;
6307 uint32_t val;
6308 /* cps (privileged) */
6309 if (IS_USER(s))
6310 return;
6311 mask = val = 0;
6312 if (insn & (1 << 19)) {
6313 if (insn & (1 << 8))
6314 mask |= CPSR_A;
6315 if (insn & (1 << 7))
6316 mask |= CPSR_I;
6317 if (insn & (1 << 6))
6318 mask |= CPSR_F;
6319 if (insn & (1 << 18))
6320 val |= mask;
6321 }
7997d92f 6322 if (insn & (1 << 17)) {
9ee6e8bb
PB		 6323 mask |= CPSR_M;
6324 val |= (insn & 0x1f);
6325 }
6326 if (mask) {
2fbac54b 6327 gen_set_psr_im(s, mask, 0, val);
9ee6e8bb
PB		 6328 }
6329 return;
6330 }
6331 goto illegal_op;
6332 }
6333 if (cond != 0xe) {
6334 /* if not always execute, we generate a conditional jump to
6335 next instruction */
6336 s->condlabel = gen_new_label();
d9ba4830 6337 gen_test_cc(cond ^ 1, s->condlabel);
9ee6e8bb
PB		 6338 s->condjmp = 1;
6339 }
6340 if ((insn & 0x0f900000) == 0x03000000) {
6341 if ((insn & (1 << 21)) == 0) {
6342 ARCH(6T2);
6343 rd = (insn >> 12) & 0xf;
6344 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6345 if ((insn & (1 << 22)) == 0) {
6346 /* MOVW */
5e3f878a
PB		 6347 tmp = new_tmp();
6348 tcg_gen_movi_i32(tmp, val);
9ee6e8bb
PB		 6349 } else {
6350 /* MOVT */
5e3f878a 6351 tmp = load_reg(s, rd);
86831435 6352 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 6353 tcg_gen_ori_i32(tmp, tmp, val << 16);
9ee6e8bb 6354 }
5e3f878a 6355 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6356 } else {
6357 if (((insn >> 12) & 0xf) != 0xf)
6358 goto illegal_op;
6359 if (((insn >> 16) & 0xf) == 0) {
6360 gen_nop_hint(s, insn & 0xff);
6361 } else {
6362 /* CPSR = immediate */
6363 val = insn & 0xff;
6364 shift = ((insn >> 8) & 0xf) * 2;
6365 if (shift)
6366 val = (val >> shift) | (val << (32 - shift));
9ee6e8bb 6367 i = ((insn & (1 << 22)) != 0);
2fbac54b 6368 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
9ee6e8bb
PB		 6369 goto illegal_op;
6370 }
6371 }
6372 } else if ((insn & 0x0f900000) == 0x01000000
6373 && (insn & 0x00000090) != 0x00000090) {
6374 /* miscellaneous instructions */
6375 op1 = (insn >> 21) & 3;
6376 sh = (insn >> 4) & 0xf;
6377 rm = insn & 0xf;
6378 switch (sh) {
6379 case 0x0: /* move program status register */
6380 if (op1 & 1) {
6381 /* PSR = reg */
2fbac54b 6382 tmp = load_reg(s, rm);
9ee6e8bb 6383 i = ((op1 & 2) != 0);
2fbac54b 6384 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
9ee6e8bb
PB		 6385 goto illegal_op;
6386 } else {
6387 /* reg = PSR */
6388 rd = (insn >> 12) & 0xf;
6389 if (op1 & 2) {
6390 if (IS_USER(s))
6391 goto illegal_op;
d9ba4830 6392 tmp = load_cpu_field(spsr);
9ee6e8bb 6393 } else {
d9ba4830
PB		 6394 tmp = new_tmp();
6395 gen_helper_cpsr_read(tmp);
9ee6e8bb 6396 }
d9ba4830 6397 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6398 }
6399 break;
6400 case 0x1:
6401 if (op1 == 1) {
6402 /* branch/exchange thumb (bx). */
d9ba4830
PB		 6403 tmp = load_reg(s, rm);
6404 gen_bx(s, tmp);
9ee6e8bb
PB		 6405 } else if (op1 == 3) {
6406 /* clz */
6407 rd = (insn >> 12) & 0xf;
1497c961
PB		 6408 tmp = load_reg(s, rm);
6409 gen_helper_clz(tmp, tmp);
6410 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6411 } else {
6412 goto illegal_op;
6413 }
6414 break;
6415 case 0x2:
6416 if (op1 == 1) {
6417 ARCH(5J); /* bxj */
6418 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 6419 tmp = load_reg(s, rm);
6420 gen_bx(s, tmp);
9ee6e8bb
PB		 6421 } else {
6422 goto illegal_op;
6423 }
6424 break;
6425 case 0x3:
6426 if (op1 != 1)
6427 goto illegal_op;
6428
6429 /* branch link/exchange thumb (blx) */
d9ba4830
PB		 6430 tmp = load_reg(s, rm);
6431 tmp2 = new_tmp();
6432 tcg_gen_movi_i32(tmp2, s->pc);
6433 store_reg(s, 14, tmp2);
6434 gen_bx(s, tmp);
9ee6e8bb
PB		 6435 break;
6436 case 0x5: /* saturating add/subtract */
6437 rd = (insn >> 12) & 0xf;
6438 rn = (insn >> 16) & 0xf;
b40d0353 6439 tmp = load_reg(s, rm);
5e3f878a 6440 tmp2 = load_reg(s, rn);
9ee6e8bb 6441 if (op1 & 2)
5e3f878a 6442 gen_helper_double_saturate(tmp2, tmp2);
9ee6e8bb 6443 if (op1 & 1)
5e3f878a 6444 gen_helper_sub_saturate(tmp, tmp, tmp2);
9ee6e8bb 6445 else
5e3f878a
PB		 6446 gen_helper_add_saturate(tmp, tmp, tmp2);
6447 dead_tmp(tmp2);
6448 store_reg(s, rd, tmp);
9ee6e8bb 6449 break;
49e14940
AL		 6450 case 7:
6451 /* SMC instruction (op1 == 3)
6452 and undefined instructions (op1 == 0 || op1 == 2)
6453 will trap */
6454 if (op1 != 1) {
6455 goto illegal_op;
6456 }
6457 /* bkpt */
bc4a0de0 6458 gen_exception_insn(s, 4, EXCP_BKPT);
9ee6e8bb
PB		 6459 break;
6460 case 0x8: /* signed multiply */
6461 case 0xa:
6462 case 0xc:
6463 case 0xe:
6464 rs = (insn >> 8) & 0xf;
6465 rn = (insn >> 12) & 0xf;
6466 rd = (insn >> 16) & 0xf;
6467 if (op1 == 1) {
6468 /* (32 * 16) >> 16 */
5e3f878a
PB		 6469 tmp = load_reg(s, rm);
6470 tmp2 = load_reg(s, rs);
9ee6e8bb 6471 if (sh & 4)
5e3f878a 6472 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 6473 else
5e3f878a 6474 gen_sxth(tmp2);
a7812ae4
PB		 6475 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6476 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 6477 tmp = new_tmp();
a7812ae4 6478 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 6479 tcg_temp_free_i64(tmp64);
9ee6e8bb 6480 if ((sh & 2) == 0) {
5e3f878a
PB		 6481 tmp2 = load_reg(s, rn);
6482 gen_helper_add_setq(tmp, tmp, tmp2);
6483 dead_tmp(tmp2);
9ee6e8bb 6484 }
5e3f878a 6485 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6486 } else {
6487 /* 16 * 16 */
5e3f878a
PB		 6488 tmp = load_reg(s, rm);
6489 tmp2 = load_reg(s, rs);
6490 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6491 dead_tmp(tmp2);
9ee6e8bb 6492 if (op1 == 2) {
a7812ae4
PB		 6493 tmp64 = tcg_temp_new_i64();
6494 tcg_gen_ext_i32_i64(tmp64, tmp);
22478e79 6495 dead_tmp(tmp);
a7812ae4
PB		 6496 gen_addq(s, tmp64, rn, rd);
6497 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6498 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 6499 } else {
6500 if (op1 == 0) {
5e3f878a
PB		 6501 tmp2 = load_reg(s, rn);
6502 gen_helper_add_setq(tmp, tmp, tmp2);
6503 dead_tmp(tmp2);
9ee6e8bb 6504 }
5e3f878a 6505 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6506 }
6507 }
6508 break;
6509 default:
6510 goto illegal_op;
6511 }
6512 } else if (((insn & 0x0e000000) == 0 &&
6513 (insn & 0x00000090) != 0x90) ||
6514 ((insn & 0x0e000000) == (1 << 25))) {
6515 int set_cc, logic_cc, shiftop;
6516
6517 op1 = (insn >> 21) & 0xf;
6518 set_cc = (insn >> 20) & 1;
6519 logic_cc = table_logic_cc[op1] & set_cc;
6520
6521 /* data processing instruction */
6522 if (insn & (1 << 25)) {
6523 /* immediate operand */
6524 val = insn & 0xff;
6525 shift = ((insn >> 8) & 0xf) * 2;
e9bb4aa9 6526 if (shift) {
9ee6e8bb 6527 val = (val >> shift) | (val << (32 - shift));
e9bb4aa9
JR		 6528 }
6529 tmp2 = new_tmp();
6530 tcg_gen_movi_i32(tmp2, val);
6531 if (logic_cc && shift) {
6532 gen_set_CF_bit31(tmp2);
6533 }
9ee6e8bb
PB		 6534 } else {
6535 /* register */
6536 rm = (insn) & 0xf;
e9bb4aa9 6537 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6538 shiftop = (insn >> 5) & 3;
6539 if (!(insn & (1 << 4))) {
6540 shift = (insn >> 7) & 0x1f;
e9bb4aa9 6541 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9ee6e8bb
PB		 6542 } else {
6543 rs = (insn >> 8) & 0xf;
8984bd2e 6544 tmp = load_reg(s, rs);
e9bb4aa9 6545 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
9ee6e8bb
PB		 6546 }
6547 }
6548 if (op1 != 0x0f && op1 != 0x0d) {
6549 rn = (insn >> 16) & 0xf;
e9bb4aa9
JR		 6550 tmp = load_reg(s, rn);
6551 } else {
6552 TCGV_UNUSED(tmp);
9ee6e8bb
PB		 6553 }
6554 rd = (insn >> 12) & 0xf;
6555 switch(op1) {
6556 case 0x00:
e9bb4aa9
JR		 6557 tcg_gen_and_i32(tmp, tmp, tmp2);
6558 if (logic_cc) {
6559 gen_logic_CC(tmp);
6560 }
21aeb343 6561 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6562 break;
6563 case 0x01:
e9bb4aa9
JR		 6564 tcg_gen_xor_i32(tmp, tmp, tmp2);
6565 if (logic_cc) {
6566 gen_logic_CC(tmp);
6567 }
21aeb343 6568 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6569 break;
6570 case 0x02:
6571 if (set_cc && rd == 15) {
6572 /* SUBS r15, ... is used for exception return. */
e9bb4aa9 6573 if (IS_USER(s)) {
9ee6e8bb 6574 goto illegal_op;
e9bb4aa9
JR		 6575 }
6576 gen_helper_sub_cc(tmp, tmp, tmp2);
6577 gen_exception_return(s, tmp);
9ee6e8bb 6578 } else {
e9bb4aa9
JR		 6579 if (set_cc) {
6580 gen_helper_sub_cc(tmp, tmp, tmp2);
6581 } else {
6582 tcg_gen_sub_i32(tmp, tmp, tmp2);
6583 }
21aeb343 6584 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6585 }
6586 break;
6587 case 0x03:
e9bb4aa9
JR		 6588 if (set_cc) {
6589 gen_helper_sub_cc(tmp, tmp2, tmp);
6590 } else {
6591 tcg_gen_sub_i32(tmp, tmp2, tmp);
6592 }
21aeb343 6593 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6594 break;
6595 case 0x04:
e9bb4aa9
JR		 6596 if (set_cc) {
6597 gen_helper_add_cc(tmp, tmp, tmp2);
6598 } else {
6599 tcg_gen_add_i32(tmp, tmp, tmp2);
6600 }
21aeb343 6601 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6602 break;
6603 case 0x05:
e9bb4aa9
JR		 6604 if (set_cc) {
6605 gen_helper_adc_cc(tmp, tmp, tmp2);
6606 } else {
6607 gen_add_carry(tmp, tmp, tmp2);
6608 }
21aeb343 6609 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6610 break;
6611 case 0x06:
e9bb4aa9
JR		 6612 if (set_cc) {
6613 gen_helper_sbc_cc(tmp, tmp, tmp2);
6614 } else {
6615 gen_sub_carry(tmp, tmp, tmp2);
6616 }
21aeb343 6617 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6618 break;
6619 case 0x07:
e9bb4aa9
JR		 6620 if (set_cc) {
6621 gen_helper_sbc_cc(tmp, tmp2, tmp);
6622 } else {
6623 gen_sub_carry(tmp, tmp2, tmp);
6624 }
21aeb343 6625 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6626 break;
6627 case 0x08:
6628 if (set_cc) {
e9bb4aa9
JR		 6629 tcg_gen_and_i32(tmp, tmp, tmp2);
6630 gen_logic_CC(tmp);
9ee6e8bb 6631 }
e9bb4aa9 6632 dead_tmp(tmp);
9ee6e8bb
PB		 6633 break;
6634 case 0x09:
6635 if (set_cc) {
e9bb4aa9
JR		 6636 tcg_gen_xor_i32(tmp, tmp, tmp2);
6637 gen_logic_CC(tmp);
9ee6e8bb 6638 }
e9bb4aa9 6639 dead_tmp(tmp);
9ee6e8bb
PB		 6640 break;
6641 case 0x0a:
6642 if (set_cc) {
e9bb4aa9 6643 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb 6644 }
e9bb4aa9 6645 dead_tmp(tmp);
9ee6e8bb
PB		 6646 break;
6647 case 0x0b:
6648 if (set_cc) {
e9bb4aa9 6649 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 6650 }
e9bb4aa9 6651 dead_tmp(tmp);
9ee6e8bb
PB		 6652 break;
6653 case 0x0c:
e9bb4aa9
JR		 6654 tcg_gen_or_i32(tmp, tmp, tmp2);
6655 if (logic_cc) {
6656 gen_logic_CC(tmp);
6657 }
21aeb343 6658 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6659 break;
6660 case 0x0d:
6661 if (logic_cc && rd == 15) {
6662 /* MOVS r15, ... is used for exception return. */
e9bb4aa9 6663 if (IS_USER(s)) {
9ee6e8bb 6664 goto illegal_op;
e9bb4aa9
JR		 6665 }
6666 gen_exception_return(s, tmp2);
9ee6e8bb 6667 } else {
e9bb4aa9
JR		 6668 if (logic_cc) {
6669 gen_logic_CC(tmp2);
6670 }
21aeb343 6671 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6672 }
6673 break;
6674 case 0x0e:
f669df27 6675 tcg_gen_andc_i32(tmp, tmp, tmp2);
e9bb4aa9
JR		 6676 if (logic_cc) {
6677 gen_logic_CC(tmp);
6678 }
21aeb343 6679 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 6680 break;
6681 default:
6682 case 0x0f:
e9bb4aa9
JR		 6683 tcg_gen_not_i32(tmp2, tmp2);
6684 if (logic_cc) {
6685 gen_logic_CC(tmp2);
6686 }
21aeb343 6687 store_reg_bx(env, s, rd, tmp2);
9ee6e8bb
PB		 6688 break;
6689 }
e9bb4aa9
JR		 6690 if (op1 != 0x0f && op1 != 0x0d) {
6691 dead_tmp(tmp2);
6692 }
9ee6e8bb
PB		 6693 } else {
6694 /* other instructions */
6695 op1 = (insn >> 24) & 0xf;
6696 switch(op1) {
6697 case 0x0:
6698 case 0x1:
6699 /* multiplies, extra load/stores */
6700 sh = (insn >> 5) & 3;
6701 if (sh == 0) {
6702 if (op1 == 0x0) {
6703 rd = (insn >> 16) & 0xf;
6704 rn = (insn >> 12) & 0xf;
6705 rs = (insn >> 8) & 0xf;
6706 rm = (insn) & 0xf;
6707 op1 = (insn >> 20) & 0xf;
6708 switch (op1) {
6709 case 0: case 1: case 2: case 3: case 6:
6710 /* 32 bit mul */
5e3f878a
PB		 6711 tmp = load_reg(s, rs);
6712 tmp2 = load_reg(s, rm);
6713 tcg_gen_mul_i32(tmp, tmp, tmp2);
6714 dead_tmp(tmp2);
9ee6e8bb
PB		 6715 if (insn & (1 << 22)) {
6716 /* Subtract (mls) */
6717 ARCH(6T2);
5e3f878a
PB		 6718 tmp2 = load_reg(s, rn);
6719 tcg_gen_sub_i32(tmp, tmp2, tmp);
6720 dead_tmp(tmp2);
9ee6e8bb
PB		 6721 } else if (insn & (1 << 21)) {
6722 /* Add */
5e3f878a
PB		 6723 tmp2 = load_reg(s, rn);
6724 tcg_gen_add_i32(tmp, tmp, tmp2);
6725 dead_tmp(tmp2);
9ee6e8bb
PB		 6726 }
6727 if (insn & (1 << 20))
5e3f878a
PB		 6728 gen_logic_CC(tmp);
6729 store_reg(s, rd, tmp);
9ee6e8bb 6730 break;
8aac08b1
AJ		 6731 case 4:
6732 /* 64 bit mul double accumulate (UMAAL) */
6733 ARCH(6);
6734 tmp = load_reg(s, rs);
6735 tmp2 = load_reg(s, rm);
6736 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6737 gen_addq_lo(s, tmp64, rn);
6738 gen_addq_lo(s, tmp64, rd);
6739 gen_storeq_reg(s, rn, rd, tmp64);
6740 tcg_temp_free_i64(tmp64);
6741 break;
6742 case 8: case 9: case 10: case 11:
6743 case 12: case 13: case 14: case 15:
6744 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
5e3f878a
PB		 6745 tmp = load_reg(s, rs);
6746 tmp2 = load_reg(s, rm);
8aac08b1 6747 if (insn & (1 << 22)) {
a7812ae4 6748 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8aac08b1 6749 } else {
a7812ae4 6750 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8aac08b1
AJ		 6751 }
6752 if (insn & (1 << 21)) { /* mult accumulate */
a7812ae4 6753 gen_addq(s, tmp64, rn, rd);
9ee6e8bb 6754 }
8aac08b1 6755 if (insn & (1 << 20)) {
a7812ae4 6756 gen_logicq_cc(tmp64);
8aac08b1 6757 }
a7812ae4 6758 gen_storeq_reg(s, rn, rd, tmp64);
b75263d6 6759 tcg_temp_free_i64(tmp64);
9ee6e8bb 6760 break;
8aac08b1
AJ		 6761 default:
6762 goto illegal_op;
9ee6e8bb
PB		 6763 }
6764 } else {
6765 rn = (insn >> 16) & 0xf;
6766 rd = (insn >> 12) & 0xf;
6767 if (insn & (1 << 23)) {
6768 /* load/store exclusive */
86753403
PB		 6769 op1 = (insn >> 21) & 0x3;
6770 if (op1)
a47f43d2 6771 ARCH(6K);
86753403
PB		 6772 else
6773 ARCH(6);
3174f8e9 6774 addr = tcg_temp_local_new_i32();
98a46317 6775 load_reg_var(s, addr, rn);
9ee6e8bb 6776 if (insn & (1 << 20)) {
86753403
PB		 6777 switch (op1) {
6778 case 0: /* ldrex */
426f5abc 6779 gen_load_exclusive(s, rd, 15, addr, 2);
86753403
PB		 6780 break;
6781 case 1: /* ldrexd */
426f5abc 6782 gen_load_exclusive(s, rd, rd + 1, addr, 3);
86753403
PB		 6783 break;
6784 case 2: /* ldrexb */
426f5abc 6785 gen_load_exclusive(s, rd, 15, addr, 0);
86753403
PB		 6786 break;
6787 case 3: /* ldrexh */
426f5abc 6788 gen_load_exclusive(s, rd, 15, addr, 1);
86753403
PB		 6789 break;
6790 default:
6791 abort();
6792 }
9ee6e8bb
PB		 6793 } else {
6794 rm = insn & 0xf;
86753403
PB		 6795 switch (op1) {
6796 case 0: /* strex */
426f5abc 6797 gen_store_exclusive(s, rd, rm, 15, addr, 2);
86753403
PB		 6798 break;
6799 case 1: /* strexd */
502e64fe 6800 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
86753403
PB		 6801 break;
6802 case 2: /* strexb */
426f5abc 6803 gen_store_exclusive(s, rd, rm, 15, addr, 0);
86753403
PB		 6804 break;
6805 case 3: /* strexh */
426f5abc 6806 gen_store_exclusive(s, rd, rm, 15, addr, 1);
86753403
PB		 6807 break;
6808 default:
6809 abort();
6810 }
9ee6e8bb 6811 }
3174f8e9 6812 tcg_temp_free(addr);
9ee6e8bb
PB		 6813 } else {
6814 /* SWP instruction */
6815 rm = (insn) & 0xf;
6816
8984bd2e
PB		 6817 /* ??? This is not really atomic. However we know
6818 we never have multiple CPUs running in parallel,
6819 so it is good enough. */
6820 addr = load_reg(s, rn);
6821 tmp = load_reg(s, rm);
9ee6e8bb 6822 if (insn & (1 << 22)) {
8984bd2e
PB		 6823 tmp2 = gen_ld8u(addr, IS_USER(s));
6824 gen_st8(tmp, addr, IS_USER(s));
9ee6e8bb 6825 } else {
8984bd2e
PB		 6826 tmp2 = gen_ld32(addr, IS_USER(s));
6827 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 6828 }
8984bd2e
PB		 6829 dead_tmp(addr);
6830 store_reg(s, rd, tmp2);
9ee6e8bb
PB		 6831 }
6832 }
6833 } else {
6834 int address_offset;
6835 int load;
6836 /* Misc load/store */
6837 rn = (insn >> 16) & 0xf;
6838 rd = (insn >> 12) & 0xf;
b0109805 6839 addr = load_reg(s, rn);
9ee6e8bb 6840 if (insn & (1 << 24))
b0109805 6841 gen_add_datah_offset(s, insn, 0, addr);
9ee6e8bb
PB		 6842 address_offset = 0;
6843 if (insn & (1 << 20)) {
6844 /* load */
6845 switch(sh) {
6846 case 1:
b0109805 6847 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb
PB		 6848 break;
6849 case 2:
b0109805 6850 tmp = gen_ld8s(addr, IS_USER(s));
9ee6e8bb
PB		 6851 break;
6852 default:
6853 case 3:
b0109805 6854 tmp = gen_ld16s(addr, IS_USER(s));
9ee6e8bb
PB		 6855 break;
6856 }
6857 load = 1;
6858 } else if (sh & 2) {
6859 /* doubleword */
6860 if (sh & 1) {
6861 /* store */
b0109805
PB		 6862 tmp = load_reg(s, rd);
6863 gen_st32(tmp, addr, IS_USER(s));
6864 tcg_gen_addi_i32(addr, addr, 4);
6865 tmp = load_reg(s, rd + 1);
6866 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6867 load = 0;
6868 } else {
6869 /* load */
b0109805
PB		 6870 tmp = gen_ld32(addr, IS_USER(s));
6871 store_reg(s, rd, tmp);
6872 tcg_gen_addi_i32(addr, addr, 4);
6873 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb
PB		 6874 rd++;
6875 load = 1;
6876 }
6877 address_offset = -4;
6878 } else {
6879 /* store */
b0109805
PB		 6880 tmp = load_reg(s, rd);
6881 gen_st16(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 6882 load = 0;
6883 }
6884 /* Perform base writeback before the loaded value to
6885 ensure correct behavior with overlapping index registers.
6886 ldrd with base writeback is is undefined if the
6887 destination and index registers overlap. */
6888 if (!(insn & (1 << 24))) {
b0109805
PB		 6889 gen_add_datah_offset(s, insn, address_offset, addr);
6890 store_reg(s, rn, addr);
9ee6e8bb
PB		 6891 } else if (insn & (1 << 21)) {
6892 if (address_offset)
b0109805
PB		 6893 tcg_gen_addi_i32(addr, addr, address_offset);
6894 store_reg(s, rn, addr);
6895 } else {
6896 dead_tmp(addr);
9ee6e8bb
PB		 6897 }
6898 if (load) {
6899 /* Complete the load. */
b0109805 6900 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6901 }
6902 }
6903 break;
6904 case 0x4:
6905 case 0x5:
6906 goto do_ldst;
6907 case 0x6:
6908 case 0x7:
6909 if (insn & (1 << 4)) {
6910 ARCH(6);
6911 /* Armv6 Media instructions. */
6912 rm = insn & 0xf;
6913 rn = (insn >> 16) & 0xf;
2c0262af 6914 rd = (insn >> 12) & 0xf;
9ee6e8bb
PB		 6915 rs = (insn >> 8) & 0xf;
6916 switch ((insn >> 23) & 3) {
6917 case 0: /* Parallel add/subtract. */
6918 op1 = (insn >> 20) & 7;
6ddbc6e4
PB		 6919 tmp = load_reg(s, rn);
6920 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 6921 sh = (insn >> 5) & 7;
6922 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6923 goto illegal_op;
6ddbc6e4
PB		 6924 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6925 dead_tmp(tmp2);
6926 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6927 break;
6928 case 1:
6929 if ((insn & 0x00700020) == 0) {
6c95676b 6930 /* Halfword pack. */
3670669c
PB		 6931 tmp = load_reg(s, rn);
6932 tmp2 = load_reg(s, rm);
9ee6e8bb 6933 shift = (insn >> 7) & 0x1f;
3670669c
PB		 6934 if (insn & (1 << 6)) {
6935 /* pkhtb */
22478e79
AZ		 6936 if (shift == 0)
6937 shift = 31;
6938 tcg_gen_sari_i32(tmp2, tmp2, shift);
3670669c 6939 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
86831435 6940 tcg_gen_ext16u_i32(tmp2, tmp2);
3670669c
PB		 6941 } else {
6942 /* pkhbt */
22478e79
AZ		 6943 if (shift)
6944 tcg_gen_shli_i32(tmp2, tmp2, shift);
86831435 6945 tcg_gen_ext16u_i32(tmp, tmp);
3670669c
PB		 6946 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6947 }
6948 tcg_gen_or_i32(tmp, tmp, tmp2);
22478e79 6949 dead_tmp(tmp2);
3670669c 6950 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6951 } else if ((insn & 0x00200020) == 0x00200000) {
6952 /* [us]sat */
6ddbc6e4 6953 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6954 shift = (insn >> 7) & 0x1f;
6955 if (insn & (1 << 6)) {
6956 if (shift == 0)
6957 shift = 31;
6ddbc6e4 6958 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 6959 } else {
6ddbc6e4 6960 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb
PB		 6961 }
6962 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 6963 tmp2 = tcg_const_i32(sh);
6964 if (insn & (1 << 22))
6965 gen_helper_usat(tmp, tmp, tmp2);
6966 else
6967 gen_helper_ssat(tmp, tmp, tmp2);
6968 tcg_temp_free_i32(tmp2);
6ddbc6e4 6969 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6970 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6971 /* [us]sat16 */
6ddbc6e4 6972 tmp = load_reg(s, rm);
9ee6e8bb 6973 sh = (insn >> 16) & 0x1f;
40d3c433
CL		 6974 tmp2 = tcg_const_i32(sh);
6975 if (insn & (1 << 22))
6976 gen_helper_usat16(tmp, tmp, tmp2);
6977 else
6978 gen_helper_ssat16(tmp, tmp, tmp2);
6979 tcg_temp_free_i32(tmp2);
6ddbc6e4 6980 store_reg(s, rd, tmp);
9ee6e8bb
PB		 6981 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6982 /* Select bytes. */
6ddbc6e4
PB		 6983 tmp = load_reg(s, rn);
6984 tmp2 = load_reg(s, rm);
6985 tmp3 = new_tmp();
6986 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6987 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6988 dead_tmp(tmp3);
6989 dead_tmp(tmp2);
6990 store_reg(s, rd, tmp);
9ee6e8bb 6991 } else if ((insn & 0x000003e0) == 0x00000060) {
5e3f878a 6992 tmp = load_reg(s, rm);
9ee6e8bb
PB		 6993 shift = (insn >> 10) & 3;
6994 /* ??? In many cases it's not neccessary to do a
6995 rotate, a shift is sufficient. */
6996 if (shift != 0)
f669df27 6997 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 6998 op1 = (insn >> 20) & 7;
6999 switch (op1) {
5e3f878a
PB		 7000 case 0: gen_sxtb16(tmp); break;
7001 case 2: gen_sxtb(tmp); break;
7002 case 3: gen_sxth(tmp); break;
7003 case 4: gen_uxtb16(tmp); break;
7004 case 6: gen_uxtb(tmp); break;
7005 case 7: gen_uxth(tmp); break;
9ee6e8bb
PB		 7006 default: goto illegal_op;
7007 }
7008 if (rn != 15) {
5e3f878a 7009 tmp2 = load_reg(s, rn);
9ee6e8bb 7010 if ((op1 & 3) == 0) {
5e3f878a 7011 gen_add16(tmp, tmp2);
9ee6e8bb 7012 } else {
5e3f878a
PB		 7013 tcg_gen_add_i32(tmp, tmp, tmp2);
7014 dead_tmp(tmp2);
9ee6e8bb
PB		 7015 }
7016 }
6c95676b 7017 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7018 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
7019 /* rev */
b0109805 7020 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7021 if (insn & (1 << 22)) {
7022 if (insn & (1 << 7)) {
b0109805 7023 gen_revsh(tmp);
9ee6e8bb
PB		 7024 } else {
7025 ARCH(6T2);
b0109805 7026 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7027 }
7028 } else {
7029 if (insn & (1 << 7))
b0109805 7030 gen_rev16(tmp);
9ee6e8bb 7031 else
66896cb8 7032 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb 7033 }
b0109805 7034 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7035 } else {
7036 goto illegal_op;
7037 }
7038 break;
7039 case 2: /* Multiplies (Type 3). */
5e3f878a
PB		 7040 tmp = load_reg(s, rm);
7041 tmp2 = load_reg(s, rs);
9ee6e8bb 7042 if (insn & (1 << 20)) {
838fa72d
AJ		 7043 /* Signed multiply most significant [accumulate].
7044 (SMMUL, SMMLA, SMMLS) */
a7812ae4 7045 tmp64 = gen_muls_i64_i32(tmp, tmp2);
838fa72d 7046
955a7dd5 7047 if (rd != 15) {
838fa72d 7048 tmp = load_reg(s, rd);
9ee6e8bb 7049 if (insn & (1 << 6)) {
838fa72d 7050 tmp64 = gen_subq_msw(tmp64, tmp);
9ee6e8bb 7051 } else {
838fa72d 7052 tmp64 = gen_addq_msw(tmp64, tmp);
9ee6e8bb
PB		 7053 }
7054 }
838fa72d
AJ		 7055 if (insn & (1 << 5)) {
7056 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7057 }
7058 tcg_gen_shri_i64(tmp64, tmp64, 32);
7059 tmp = new_tmp();
7060 tcg_gen_trunc_i64_i32(tmp, tmp64);
7061 tcg_temp_free_i64(tmp64);
955a7dd5 7062 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7063 } else {
7064 if (insn & (1 << 5))
5e3f878a
PB		 7065 gen_swap_half(tmp2);
7066 gen_smul_dual(tmp, tmp2);
7067 /* This addition cannot overflow. */
7068 if (insn & (1 << 6)) {
7069 tcg_gen_sub_i32(tmp, tmp, tmp2);
7070 } else {
7071 tcg_gen_add_i32(tmp, tmp, tmp2);
7072 }
7073 dead_tmp(tmp2);
9ee6e8bb 7074 if (insn & (1 << 22)) {
5e3f878a 7075 /* smlald, smlsld */
a7812ae4
PB		 7076 tmp64 = tcg_temp_new_i64();
7077 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7078 dead_tmp(tmp);
a7812ae4
PB		 7079 gen_addq(s, tmp64, rd, rn);
7080 gen_storeq_reg(s, rd, rn, tmp64);
b75263d6 7081 tcg_temp_free_i64(tmp64);
9ee6e8bb 7082 } else {
5e3f878a 7083 /* smuad, smusd, smlad, smlsd */
22478e79 7084 if (rd != 15)
9ee6e8bb 7085 {
22478e79 7086 tmp2 = load_reg(s, rd);
5e3f878a
PB		 7087 gen_helper_add_setq(tmp, tmp, tmp2);
7088 dead_tmp(tmp2);
9ee6e8bb 7089 }
22478e79 7090 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7091 }
7092 }
7093 break;
7094 case 3:
7095 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7096 switch (op1) {
7097 case 0: /* Unsigned sum of absolute differences. */
6ddbc6e4
PB		 7098 ARCH(6);
7099 tmp = load_reg(s, rm);
7100 tmp2 = load_reg(s, rs);
7101 gen_helper_usad8(tmp, tmp, tmp2);
7102 dead_tmp(tmp2);
ded9d295
AZ		 7103 if (rd != 15) {
7104 tmp2 = load_reg(s, rd);
6ddbc6e4
PB		 7105 tcg_gen_add_i32(tmp, tmp, tmp2);
7106 dead_tmp(tmp2);
9ee6e8bb 7107 }
ded9d295 7108 store_reg(s, rn, tmp);
9ee6e8bb
PB		 7109 break;
7110 case 0x20: case 0x24: case 0x28: case 0x2c:
7111 /* Bitfield insert/clear. */
7112 ARCH(6T2);
7113 shift = (insn >> 7) & 0x1f;
7114 i = (insn >> 16) & 0x1f;
7115 i = i + 1 - shift;
7116 if (rm == 15) {
5e3f878a
PB		 7117 tmp = new_tmp();
7118 tcg_gen_movi_i32(tmp, 0);
9ee6e8bb 7119 } else {
5e3f878a 7120 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7121 }
7122 if (i != 32) {
5e3f878a 7123 tmp2 = load_reg(s, rd);
8f8e3aa4 7124 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
5e3f878a 7125 dead_tmp(tmp2);
9ee6e8bb 7126 }
5e3f878a 7127 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7128 break;
7129 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7130 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
4cc633c3 7131 ARCH(6T2);
5e3f878a 7132 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7133 shift = (insn >> 7) & 0x1f;
7134 i = ((insn >> 16) & 0x1f) + 1;
7135 if (shift + i > 32)
7136 goto illegal_op;
7137 if (i < 32) {
7138 if (op1 & 0x20) {
5e3f878a 7139 gen_ubfx(tmp, shift, (1u << i) - 1);
9ee6e8bb 7140 } else {
5e3f878a 7141 gen_sbfx(tmp, shift, i);
9ee6e8bb
PB		 7142 }
7143 }
5e3f878a 7144 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7145 break;
7146 default:
7147 goto illegal_op;
7148 }
7149 break;
7150 }
7151 break;
7152 }
7153 do_ldst:
7154 /* Check for undefined extension instructions
7155 * per the ARM Bible IE:
7156 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7157 */
7158 sh = (0xf << 20) | (0xf << 4);
7159 if (op1 == 0x7 && ((insn & sh) == sh))
7160 {
7161 goto illegal_op;
7162 }
7163 /* load/store byte/word */
7164 rn = (insn >> 16) & 0xf;
7165 rd = (insn >> 12) & 0xf;
b0109805 7166 tmp2 = load_reg(s, rn);
9ee6e8bb
PB		 7167 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7168 if (insn & (1 << 24))
b0109805 7169 gen_add_data_offset(s, insn, tmp2);
9ee6e8bb
PB		 7170 if (insn & (1 << 20)) {
7171 /* load */
9ee6e8bb 7172 if (insn & (1 << 22)) {
b0109805 7173 tmp = gen_ld8u(tmp2, i);
9ee6e8bb 7174 } else {
b0109805 7175 tmp = gen_ld32(tmp2, i);
9ee6e8bb 7176 }
9ee6e8bb
PB		 7177 } else {
7178 /* store */
b0109805 7179 tmp = load_reg(s, rd);
9ee6e8bb 7180 if (insn & (1 << 22))
b0109805 7181 gen_st8(tmp, tmp2, i);
9ee6e8bb 7182 else
b0109805 7183 gen_st32(tmp, tmp2, i);
9ee6e8bb
PB		 7184 }
7185 if (!(insn & (1 << 24))) {
b0109805
PB		 7186 gen_add_data_offset(s, insn, tmp2);
7187 store_reg(s, rn, tmp2);
7188 } else if (insn & (1 << 21)) {
7189 store_reg(s, rn, tmp2);
7190 } else {
7191 dead_tmp(tmp2);
9ee6e8bb
PB		 7192 }
7193 if (insn & (1 << 20)) {
7194 /* Complete the load. */
7195 if (rd == 15)
b0109805 7196 gen_bx(s, tmp);
9ee6e8bb 7197 else
b0109805 7198 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7199 }
7200 break;
7201 case 0x08:
7202 case 0x09:
7203 {
7204 int j, n, user, loaded_base;
b0109805 7205 TCGv loaded_var;
9ee6e8bb
PB		 7206 /* load/store multiple words */
7207 /* XXX: store correct base if write back */
7208 user = 0;
7209 if (insn & (1 << 22)) {
7210 if (IS_USER(s))
7211 goto illegal_op; /* only usable in supervisor mode */
7212
7213 if ((insn & (1 << 15)) == 0)
7214 user = 1;
7215 }
7216 rn = (insn >> 16) & 0xf;
b0109805 7217 addr = load_reg(s, rn);
9ee6e8bb
PB		 7218
7219 /* compute total size */
7220 loaded_base = 0;
a50f5b91 7221 TCGV_UNUSED(loaded_var);
9ee6e8bb
PB		 7222 n = 0;
7223 for(i=0;i<16;i++) {
7224 if (insn & (1 << i))
7225 n++;
7226 }
7227 /* XXX: test invalid n == 0 case ? */
7228 if (insn & (1 << 23)) {
7229 if (insn & (1 << 24)) {
7230 /* pre increment */
b0109805 7231 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7232 } else {
7233 /* post increment */
7234 }
7235 } else {
7236 if (insn & (1 << 24)) {
7237 /* pre decrement */
b0109805 7238 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7239 } else {
7240 /* post decrement */
7241 if (n != 1)
b0109805 7242 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7243 }
7244 }
7245 j = 0;
7246 for(i=0;i<16;i++) {
7247 if (insn & (1 << i)) {
7248 if (insn & (1 << 20)) {
7249 /* load */
b0109805 7250 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7251 if (i == 15) {
b0109805 7252 gen_bx(s, tmp);
9ee6e8bb 7253 } else if (user) {
b75263d6
JR		 7254 tmp2 = tcg_const_i32(i);
7255 gen_helper_set_user_reg(tmp2, tmp);
7256 tcg_temp_free_i32(tmp2);
b0109805 7257 dead_tmp(tmp);
9ee6e8bb 7258 } else if (i == rn) {
b0109805 7259 loaded_var = tmp;
9ee6e8bb
PB		 7260 loaded_base = 1;
7261 } else {
b0109805 7262 store_reg(s, i, tmp);
9ee6e8bb
PB		 7263 }
7264 } else {
7265 /* store */
7266 if (i == 15) {
7267 /* special case: r15 = PC + 8 */
7268 val = (long)s->pc + 4;
b0109805
PB		 7269 tmp = new_tmp();
7270 tcg_gen_movi_i32(tmp, val);
9ee6e8bb 7271 } else if (user) {
b0109805 7272 tmp = new_tmp();
b75263d6
JR		 7273 tmp2 = tcg_const_i32(i);
7274 gen_helper_get_user_reg(tmp, tmp2);
7275 tcg_temp_free_i32(tmp2);
9ee6e8bb 7276 } else {
b0109805 7277 tmp = load_reg(s, i);
9ee6e8bb 7278 }
b0109805 7279 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7280 }
7281 j++;
7282 /* no need to add after the last transfer */
7283 if (j != n)
b0109805 7284 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7285 }
7286 }
7287 if (insn & (1 << 21)) {
7288 /* write back */
7289 if (insn & (1 << 23)) {
7290 if (insn & (1 << 24)) {
7291 /* pre increment */
7292 } else {
7293 /* post increment */
b0109805 7294 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7295 }
7296 } else {
7297 if (insn & (1 << 24)) {
7298 /* pre decrement */
7299 if (n != 1)
b0109805 7300 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
9ee6e8bb
PB		 7301 } else {
7302 /* post decrement */
b0109805 7303 tcg_gen_addi_i32(addr, addr, -(n * 4));
9ee6e8bb
PB		 7304 }
7305 }
b0109805
PB		 7306 store_reg(s, rn, addr);
7307 } else {
7308 dead_tmp(addr);
9ee6e8bb
PB		 7309 }
7310 if (loaded_base) {
b0109805 7311 store_reg(s, rn, loaded_var);
9ee6e8bb
PB		 7312 }
7313 if ((insn & (1 << 22)) && !user) {
7314 /* Restore CPSR from SPSR. */
d9ba4830
PB		 7315 tmp = load_cpu_field(spsr);
7316 gen_set_cpsr(tmp, 0xffffffff);
7317 dead_tmp(tmp);
9ee6e8bb
PB		 7318 s->is_jmp = DISAS_UPDATE;
7319 }
7320 }
7321 break;
7322 case 0xa:
7323 case 0xb:
7324 {
7325 int32_t offset;
7326
7327 /* branch (and link) */
7328 val = (int32_t)s->pc;
7329 if (insn & (1 << 24)) {
5e3f878a
PB		 7330 tmp = new_tmp();
7331 tcg_gen_movi_i32(tmp, val);
7332 store_reg(s, 14, tmp);
9ee6e8bb
PB		 7333 }
7334 offset = (((int32_t)insn << 8) >> 8);
7335 val += (offset << 2) + 4;
7336 gen_jmp(s, val);
7337 }
7338 break;
7339 case 0xc:
7340 case 0xd:
7341 case 0xe:
7342 /* Coprocessor. */
7343 if (disas_coproc_insn(env, s, insn))
7344 goto illegal_op;
7345 break;
7346 case 0xf:
7347 /* swi */
5e3f878a 7348 gen_set_pc_im(s->pc);
9ee6e8bb
PB		 7349 s->is_jmp = DISAS_SWI;
7350 break;
7351 default:
7352 illegal_op:
bc4a0de0 7353 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 7354 break;
7355 }
7356 }
7357}
7358
7359/* Return true if this is a Thumb-2 logical op. */
7360static int
7361thumb2_logic_op(int op)
7362{
7363 return (op < 8);
7364}
7365
7366/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7367 then set condition code flags based on the result of the operation.
7368 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7369 to the high bit of T1.
7370 Returns zero if the opcode is valid. */
7371
7372static int
396e467c 7373gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
9ee6e8bb
PB		 7374{
7375 int logic_cc;
7376
7377 logic_cc = 0;
7378 switch (op) {
7379 case 0: /* and */
396e467c 7380 tcg_gen_and_i32(t0, t0, t1);
9ee6e8bb
PB		 7381 logic_cc = conds;
7382 break;
7383 case 1: /* bic */
f669df27 7384 tcg_gen_andc_i32(t0, t0, t1);
9ee6e8bb
PB		 7385 logic_cc = conds;
7386 break;
7387 case 2: /* orr */
396e467c 7388 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7389 logic_cc = conds;
7390 break;
7391 case 3: /* orn */
396e467c
FN		 7392 tcg_gen_not_i32(t1, t1);
7393 tcg_gen_or_i32(t0, t0, t1);
9ee6e8bb
PB		 7394 logic_cc = conds;
7395 break;
7396 case 4: /* eor */
396e467c 7397 tcg_gen_xor_i32(t0, t0, t1);
9ee6e8bb
PB		 7398 logic_cc = conds;
7399 break;
7400 case 8: /* add */
7401 if (conds)
396e467c 7402 gen_helper_add_cc(t0, t0, t1);
9ee6e8bb 7403 else
396e467c 7404 tcg_gen_add_i32(t0, t0, t1);
9ee6e8bb
PB		 7405 break;
7406 case 10: /* adc */
7407 if (conds)
396e467c 7408 gen_helper_adc_cc(t0, t0, t1);
9ee6e8bb 7409 else
396e467c 7410 gen_adc(t0, t1);
9ee6e8bb
PB		 7411 break;
7412 case 11: /* sbc */
7413 if (conds)
396e467c 7414 gen_helper_sbc_cc(t0, t0, t1);
9ee6e8bb 7415 else
396e467c 7416 gen_sub_carry(t0, t0, t1);
9ee6e8bb
PB		 7417 break;
7418 case 13: /* sub */
7419 if (conds)
396e467c 7420 gen_helper_sub_cc(t0, t0, t1);
9ee6e8bb 7421 else
396e467c 7422 tcg_gen_sub_i32(t0, t0, t1);
9ee6e8bb
PB		 7423 break;
7424 case 14: /* rsb */
7425 if (conds)
396e467c 7426 gen_helper_sub_cc(t0, t1, t0);
9ee6e8bb 7427 else
396e467c 7428 tcg_gen_sub_i32(t0, t1, t0);
9ee6e8bb
PB		 7429 break;
7430 default: /* 5, 6, 7, 9, 12, 15. */
7431 return 1;
7432 }
7433 if (logic_cc) {
396e467c 7434 gen_logic_CC(t0);
9ee6e8bb 7435 if (shifter_out)
396e467c 7436 gen_set_CF_bit31(t1);
9ee6e8bb
PB		 7437 }
7438 return 0;
7439}
7440
7441/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7442 is not legal. */
7443static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7444{
b0109805 7445 uint32_t insn, imm, shift, offset;
9ee6e8bb 7446 uint32_t rd, rn, rm, rs;
b26eefb6 7447 TCGv tmp;
6ddbc6e4
PB		 7448 TCGv tmp2;
7449 TCGv tmp3;
b0109805 7450 TCGv addr;
a7812ae4 7451 TCGv_i64 tmp64;
9ee6e8bb
PB		 7452 int op;
7453 int shiftop;
7454 int conds;
7455 int logic_cc;
7456
7457 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7458 || arm_feature (env, ARM_FEATURE_M))) {
601d70b9 7459 /* Thumb-1 cores may need to treat bl and blx as a pair of
9ee6e8bb
PB		 7460 16-bit instructions to get correct prefetch abort behavior. */
7461 insn = insn_hw1;
7462 if ((insn & (1 << 12)) == 0) {
7463 /* Second half of blx. */
7464 offset = ((insn & 0x7ff) << 1);
d9ba4830
PB		 7465 tmp = load_reg(s, 14);
7466 tcg_gen_addi_i32(tmp, tmp, offset);
7467 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
9ee6e8bb 7468
d9ba4830 7469 tmp2 = new_tmp();
b0109805 7470 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7471 store_reg(s, 14, tmp2);
7472 gen_bx(s, tmp);
9ee6e8bb
PB		 7473 return 0;
7474 }
7475 if (insn & (1 << 11)) {
7476 /* Second half of bl. */
7477 offset = ((insn & 0x7ff) << 1) | 1;
d9ba4830 7478 tmp = load_reg(s, 14);
6a0d8a1d 7479 tcg_gen_addi_i32(tmp, tmp, offset);
9ee6e8bb 7480
d9ba4830 7481 tmp2 = new_tmp();
b0109805 7482 tcg_gen_movi_i32(tmp2, s->pc | 1);
d9ba4830
PB		 7483 store_reg(s, 14, tmp2);
7484 gen_bx(s, tmp);
9ee6e8bb
PB		 7485 return 0;
7486 }
7487 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7488 /* Instruction spans a page boundary. Implement it as two
7489 16-bit instructions in case the second half causes an
7490 prefetch abort. */
7491 offset = ((int32_t)insn << 21) >> 9;
396e467c 7492 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
9ee6e8bb
PB		 7493 return 0;
7494 }
7495 /* Fall through to 32-bit decode. */
7496 }
7497
7498 insn = lduw_code(s->pc);
7499 s->pc += 2;
7500 insn |= (uint32_t)insn_hw1 << 16;
7501
7502 if ((insn & 0xf800e800) != 0xf000e800) {
7503 ARCH(6T2);
7504 }
7505
7506 rn = (insn >> 16) & 0xf;
7507 rs = (insn >> 12) & 0xf;
7508 rd = (insn >> 8) & 0xf;
7509 rm = insn & 0xf;
7510 switch ((insn >> 25) & 0xf) {
7511 case 0: case 1: case 2: case 3:
7512 /* 16-bit instructions. Should never happen. */
7513 abort();
7514 case 4:
7515 if (insn & (1 << 22)) {
7516 /* Other load/store, table branch. */
7517 if (insn & 0x01200000) {
7518 /* Load/store doubleword. */
7519 if (rn == 15) {
b0109805
PB		 7520 addr = new_tmp();
7521 tcg_gen_movi_i32(addr, s->pc & ~3);
9ee6e8bb 7522 } else {
b0109805 7523 addr = load_reg(s, rn);
9ee6e8bb
PB		 7524 }
7525 offset = (insn & 0xff) * 4;
7526 if ((insn & (1 << 23)) == 0)
7527 offset = -offset;
7528 if (insn & (1 << 24)) {
b0109805 7529 tcg_gen_addi_i32(addr, addr, offset);
9ee6e8bb
PB		 7530 offset = 0;
7531 }
7532 if (insn & (1 << 20)) {
7533 /* ldrd */
b0109805
PB		 7534 tmp = gen_ld32(addr, IS_USER(s));
7535 store_reg(s, rs, tmp);
7536 tcg_gen_addi_i32(addr, addr, 4);
7537 tmp = gen_ld32(addr, IS_USER(s));
7538 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7539 } else {
7540 /* strd */
b0109805
PB		 7541 tmp = load_reg(s, rs);
7542 gen_st32(tmp, addr, IS_USER(s));
7543 tcg_gen_addi_i32(addr, addr, 4);
7544 tmp = load_reg(s, rd);
7545 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb
PB		 7546 }
7547 if (insn & (1 << 21)) {
7548 /* Base writeback. */
7549 if (rn == 15)
7550 goto illegal_op;
b0109805
PB		 7551 tcg_gen_addi_i32(addr, addr, offset - 4);
7552 store_reg(s, rn, addr);
7553 } else {
7554 dead_tmp(addr);
9ee6e8bb
PB		 7555 }
7556 } else if ((insn & (1 << 23)) == 0) {
7557 /* Load/store exclusive word. */
3174f8e9 7558 addr = tcg_temp_local_new();
98a46317 7559 load_reg_var(s, addr, rn);
426f5abc 7560 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
2c0262af 7561 if (insn & (1 << 20)) {
426f5abc 7562 gen_load_exclusive(s, rs, 15, addr, 2);
9ee6e8bb 7563 } else {
426f5abc 7564 gen_store_exclusive(s, rd, rs, 15, addr, 2);
9ee6e8bb 7565 }
3174f8e9 7566 tcg_temp_free(addr);
9ee6e8bb
PB		 7567 } else if ((insn & (1 << 6)) == 0) {
7568 /* Table Branch. */
7569 if (rn == 15) {
b0109805
PB		 7570 addr = new_tmp();
7571 tcg_gen_movi_i32(addr, s->pc);
9ee6e8bb 7572 } else {
b0109805 7573 addr = load_reg(s, rn);
9ee6e8bb 7574 }
b26eefb6 7575 tmp = load_reg(s, rm);
b0109805 7576 tcg_gen_add_i32(addr, addr, tmp);
9ee6e8bb
PB		 7577 if (insn & (1 << 4)) {
7578 /* tbh */
b0109805 7579 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 7580 dead_tmp(tmp);
b0109805 7581 tmp = gen_ld16u(addr, IS_USER(s));
9ee6e8bb 7582 } else { /* tbb */
b26eefb6 7583 dead_tmp(tmp);
b0109805 7584 tmp = gen_ld8u(addr, IS_USER(s));
9ee6e8bb 7585 }
b0109805
PB		 7586 dead_tmp(addr);
7587 tcg_gen_shli_i32(tmp, tmp, 1);
7588 tcg_gen_addi_i32(tmp, tmp, s->pc);
7589 store_reg(s, 15, tmp);
9ee6e8bb
PB		 7590 } else {
7591 /* Load/store exclusive byte/halfword/doubleword. */
426f5abc 7592 ARCH(7);
9ee6e8bb 7593 op = (insn >> 4) & 0x3;
426f5abc
PB		 7594 if (op == 2) {
7595 goto illegal_op;
7596 }
3174f8e9 7597 addr = tcg_temp_local_new();
98a46317 7598 load_reg_var(s, addr, rn);
9ee6e8bb 7599 if (insn & (1 << 20)) {
426f5abc 7600 gen_load_exclusive(s, rs, rd, addr, op);
9ee6e8bb 7601 } else {
426f5abc 7602 gen_store_exclusive(s, rm, rs, rd, addr, op);
9ee6e8bb 7603 }
3174f8e9 7604 tcg_temp_free(addr);
9ee6e8bb
PB		 7605 }
7606 } else {
7607 /* Load/store multiple, RFE, SRS. */
7608 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7609 /* Not available in user mode. */
b0109805 7610 if (IS_USER(s))
9ee6e8bb
PB		 7611 goto illegal_op;
7612 if (insn & (1 << 20)) {
7613 /* rfe */
b0109805
PB		 7614 addr = load_reg(s, rn);
7615 if ((insn & (1 << 24)) == 0)
7616 tcg_gen_addi_i32(addr, addr, -8);
7617 /* Load PC into tmp and CPSR into tmp2. */
7618 tmp = gen_ld32(addr, 0);
7619 tcg_gen_addi_i32(addr, addr, 4);
7620 tmp2 = gen_ld32(addr, 0);
9ee6e8bb
PB		 7621 if (insn & (1 << 21)) {
7622 /* Base writeback. */
b0109805
PB		 7623 if (insn & (1 << 24)) {
7624 tcg_gen_addi_i32(addr, addr, 4);
7625 } else {
7626 tcg_gen_addi_i32(addr, addr, -4);
7627 }
7628 store_reg(s, rn, addr);
7629 } else {
7630 dead_tmp(addr);
9ee6e8bb 7631 }
b0109805 7632 gen_rfe(s, tmp, tmp2);
9ee6e8bb
PB		 7633 } else {
7634 /* srs */
7635 op = (insn & 0x1f);
39ea3d4e
PM		 7636 addr = new_tmp();
7637 tmp = tcg_const_i32(op);
7638 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7639 tcg_temp_free_i32(tmp);
9ee6e8bb 7640 if ((insn & (1 << 24)) == 0) {
b0109805 7641 tcg_gen_addi_i32(addr, addr, -8);
9ee6e8bb 7642 }
b0109805
PB		 7643 tmp = load_reg(s, 14);
7644 gen_st32(tmp, addr, 0);
7645 tcg_gen_addi_i32(addr, addr, 4);
7646 tmp = new_tmp();
7647 gen_helper_cpsr_read(tmp);
7648 gen_st32(tmp, addr, 0);
9ee6e8bb
PB		 7649 if (insn & (1 << 21)) {
7650 if ((insn & (1 << 24)) == 0) {
b0109805 7651 tcg_gen_addi_i32(addr, addr, -4);
9ee6e8bb 7652 } else {
b0109805 7653 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb 7654 }
39ea3d4e
PM		 7655 tmp = tcg_const_i32(op);
7656 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7657 tcg_temp_free_i32(tmp);
b0109805
PB		 7658 } else {
7659 dead_tmp(addr);
9ee6e8bb
PB		 7660 }
7661 }
7662 } else {
7663 int i;
7664 /* Load/store multiple. */
b0109805 7665 addr = load_reg(s, rn);
9ee6e8bb
PB		 7666 offset = 0;
7667 for (i = 0; i < 16; i++) {
7668 if (insn & (1 << i))
7669 offset += 4;
7670 }
7671 if (insn & (1 << 24)) {
b0109805 7672 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7673 }
7674
7675 for (i = 0; i < 16; i++) {
7676 if ((insn & (1 << i)) == 0)
7677 continue;
7678 if (insn & (1 << 20)) {
7679 /* Load. */
b0109805 7680 tmp = gen_ld32(addr, IS_USER(s));
9ee6e8bb 7681 if (i == 15) {
b0109805 7682 gen_bx(s, tmp);
9ee6e8bb 7683 } else {
b0109805 7684 store_reg(s, i, tmp);
9ee6e8bb
PB		 7685 }
7686 } else {
7687 /* Store. */
b0109805
PB		 7688 tmp = load_reg(s, i);
7689 gen_st32(tmp, addr, IS_USER(s));
9ee6e8bb 7690 }
b0109805 7691 tcg_gen_addi_i32(addr, addr, 4);
9ee6e8bb
PB		 7692 }
7693 if (insn & (1 << 21)) {
7694 /* Base register writeback. */
7695 if (insn & (1 << 24)) {
b0109805 7696 tcg_gen_addi_i32(addr, addr, -offset);
9ee6e8bb
PB		 7697 }
7698 /* Fault if writeback register is in register list. */
7699 if (insn & (1 << rn))
7700 goto illegal_op;
b0109805
PB		 7701 store_reg(s, rn, addr);
7702 } else {
7703 dead_tmp(addr);
9ee6e8bb
PB		 7704 }
7705 }
7706 }
7707 break;
2af9ab77
JB		 7708 case 5:
7709
9ee6e8bb 7710 op = (insn >> 21) & 0xf;
2af9ab77
JB		 7711 if (op == 6) {
7712 /* Halfword pack. */
7713 tmp = load_reg(s, rn);
7714 tmp2 = load_reg(s, rm);
7715 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7716 if (insn & (1 << 5)) {
7717 /* pkhtb */
7718 if (shift == 0)
7719 shift = 31;
7720 tcg_gen_sari_i32(tmp2, tmp2, shift);
7721 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7722 tcg_gen_ext16u_i32(tmp2, tmp2);
7723 } else {
7724 /* pkhbt */
7725 if (shift)
7726 tcg_gen_shli_i32(tmp2, tmp2, shift);
7727 tcg_gen_ext16u_i32(tmp, tmp);
7728 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7729 }
7730 tcg_gen_or_i32(tmp, tmp, tmp2);
7731 dead_tmp(tmp2);
3174f8e9
FN		 7732 store_reg(s, rd, tmp);
7733 } else {
2af9ab77
JB		 7734 /* Data processing register constant shift. */
7735 if (rn == 15) {
7736 tmp = new_tmp();
7737 tcg_gen_movi_i32(tmp, 0);
7738 } else {
7739 tmp = load_reg(s, rn);
7740 }
7741 tmp2 = load_reg(s, rm);
7742
7743 shiftop = (insn >> 4) & 3;
7744 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7745 conds = (insn & (1 << 20)) != 0;
7746 logic_cc = (conds && thumb2_logic_op(op));
7747 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7748 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7749 goto illegal_op;
7750 dead_tmp(tmp2);
7751 if (rd != 15) {
7752 store_reg(s, rd, tmp);
7753 } else {
7754 dead_tmp(tmp);
7755 }
3174f8e9 7756 }
9ee6e8bb
PB		 7757 break;
7758 case 13: /* Misc data processing. */
7759 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7760 if (op < 4 && (insn & 0xf000) != 0xf000)
7761 goto illegal_op;
7762 switch (op) {
7763 case 0: /* Register controlled shift. */
8984bd2e
PB		 7764 tmp = load_reg(s, rn);
7765 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7766 if ((insn & 0x70) != 0)
7767 goto illegal_op;
7768 op = (insn >> 21) & 3;
8984bd2e
PB		 7769 logic_cc = (insn & (1 << 20)) != 0;
7770 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7771 if (logic_cc)
7772 gen_logic_CC(tmp);
21aeb343 7773 store_reg_bx(env, s, rd, tmp);
9ee6e8bb
PB		 7774 break;
7775 case 1: /* Sign/zero extend. */
5e3f878a 7776 tmp = load_reg(s, rm);
9ee6e8bb
PB		 7777 shift = (insn >> 4) & 3;
7778 /* ??? In many cases it's not neccessary to do a
7779 rotate, a shift is sufficient. */
7780 if (shift != 0)
f669df27 7781 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9ee6e8bb
PB		 7782 op = (insn >> 20) & 7;
7783 switch (op) {
5e3f878a
PB		 7784 case 0: gen_sxth(tmp); break;
7785 case 1: gen_uxth(tmp); break;
7786 case 2: gen_sxtb16(tmp); break;
7787 case 3: gen_uxtb16(tmp); break;
7788 case 4: gen_sxtb(tmp); break;
7789 case 5: gen_uxtb(tmp); break;
9ee6e8bb
PB		 7790 default: goto illegal_op;
7791 }
7792 if (rn != 15) {
5e3f878a 7793 tmp2 = load_reg(s, rn);
9ee6e8bb 7794 if ((op >> 1) == 1) {
5e3f878a 7795 gen_add16(tmp, tmp2);
9ee6e8bb 7796 } else {
5e3f878a
PB		 7797 tcg_gen_add_i32(tmp, tmp, tmp2);
7798 dead_tmp(tmp2);
9ee6e8bb
PB		 7799 }
7800 }
5e3f878a 7801 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7802 break;
7803 case 2: /* SIMD add/subtract. */
7804 op = (insn >> 20) & 7;
7805 shift = (insn >> 4) & 7;
7806 if ((op & 3) == 3 || (shift & 3) == 3)
7807 goto illegal_op;
6ddbc6e4
PB		 7808 tmp = load_reg(s, rn);
7809 tmp2 = load_reg(s, rm);
7810 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7811 dead_tmp(tmp2);
7812 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7813 break;
7814 case 3: /* Other data processing. */
7815 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7816 if (op < 4) {
7817 /* Saturating add/subtract. */
d9ba4830
PB		 7818 tmp = load_reg(s, rn);
7819 tmp2 = load_reg(s, rm);
9ee6e8bb 7820 if (op & 1)
4809c612
JB		 7821 gen_helper_double_saturate(tmp, tmp);
7822 if (op & 2)
d9ba4830 7823 gen_helper_sub_saturate(tmp, tmp2, tmp);
9ee6e8bb 7824 else
d9ba4830
PB		 7825 gen_helper_add_saturate(tmp, tmp, tmp2);
7826 dead_tmp(tmp2);
9ee6e8bb 7827 } else {
d9ba4830 7828 tmp = load_reg(s, rn);
9ee6e8bb
PB		 7829 switch (op) {
7830 case 0x0a: /* rbit */
d9ba4830 7831 gen_helper_rbit(tmp, tmp);
9ee6e8bb
PB		 7832 break;
7833 case 0x08: /* rev */
66896cb8 7834 tcg_gen_bswap32_i32(tmp, tmp);
9ee6e8bb
PB		 7835 break;
7836 case 0x09: /* rev16 */
d9ba4830 7837 gen_rev16(tmp);
9ee6e8bb
PB		 7838 break;
7839 case 0x0b: /* revsh */
d9ba4830 7840 gen_revsh(tmp);
9ee6e8bb
PB		 7841 break;
7842 case 0x10: /* sel */
d9ba4830 7843 tmp2 = load_reg(s, rm);
6ddbc6e4
PB		 7844 tmp3 = new_tmp();
7845 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
d9ba4830 7846 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6ddbc6e4 7847 dead_tmp(tmp3);
d9ba4830 7848 dead_tmp(tmp2);
9ee6e8bb
PB		 7849 break;
7850 case 0x18: /* clz */
d9ba4830 7851 gen_helper_clz(tmp, tmp);
9ee6e8bb
PB		 7852 break;
7853 default:
7854 goto illegal_op;
7855 }
7856 }
d9ba4830 7857 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7858 break;
7859 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7860 op = (insn >> 4) & 0xf;
d9ba4830
PB		 7861 tmp = load_reg(s, rn);
7862 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7863 switch ((insn >> 20) & 7) {
7864 case 0: /* 32 x 32 -> 32 */
d9ba4830
PB		 7865 tcg_gen_mul_i32(tmp, tmp, tmp2);
7866 dead_tmp(tmp2);
9ee6e8bb 7867 if (rs != 15) {
d9ba4830 7868 tmp2 = load_reg(s, rs);
9ee6e8bb 7869 if (op)
d9ba4830 7870 tcg_gen_sub_i32(tmp, tmp2, tmp);
9ee6e8bb 7871 else
d9ba4830
PB		 7872 tcg_gen_add_i32(tmp, tmp, tmp2);
7873 dead_tmp(tmp2);
9ee6e8bb 7874 }
9ee6e8bb
PB		 7875 break;
7876 case 1: /* 16 x 16 -> 32 */
d9ba4830
PB		 7877 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7878 dead_tmp(tmp2);
9ee6e8bb 7879 if (rs != 15) {
d9ba4830
PB		 7880 tmp2 = load_reg(s, rs);
7881 gen_helper_add_setq(tmp, tmp, tmp2);
7882 dead_tmp(tmp2);
9ee6e8bb 7883 }
9ee6e8bb
PB		 7884 break;
7885 case 2: /* Dual multiply add. */
7886 case 4: /* Dual multiply subtract. */
7887 if (op)
d9ba4830
PB		 7888 gen_swap_half(tmp2);
7889 gen_smul_dual(tmp, tmp2);
9ee6e8bb
PB		 7890 /* This addition cannot overflow. */
7891 if (insn & (1 << 22)) {
d9ba4830 7892 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 7893 } else {
d9ba4830 7894 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 7895 }
d9ba4830 7896 dead_tmp(tmp2);
9ee6e8bb
PB		 7897 if (rs != 15)
7898 {
d9ba4830
PB		 7899 tmp2 = load_reg(s, rs);
7900 gen_helper_add_setq(tmp, tmp, tmp2);
7901 dead_tmp(tmp2);
9ee6e8bb 7902 }
9ee6e8bb
PB		 7903 break;
7904 case 3: /* 32 * 16 -> 32msb */
7905 if (op)
d9ba4830 7906 tcg_gen_sari_i32(tmp2, tmp2, 16);
9ee6e8bb 7907 else
d9ba4830 7908 gen_sxth(tmp2);
a7812ae4
PB		 7909 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7910 tcg_gen_shri_i64(tmp64, tmp64, 16);
5e3f878a 7911 tmp = new_tmp();
a7812ae4 7912 tcg_gen_trunc_i64_i32(tmp, tmp64);
b75263d6 7913 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7914 if (rs != 15)
7915 {
d9ba4830
PB		 7916 tmp2 = load_reg(s, rs);
7917 gen_helper_add_setq(tmp, tmp, tmp2);
7918 dead_tmp(tmp2);
9ee6e8bb 7919 }
9ee6e8bb 7920 break;
838fa72d
AJ		 7921 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7922 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7923 if (rs != 15) {
838fa72d
AJ		 7924 tmp = load_reg(s, rs);
7925 if (insn & (1 << 20)) {
7926 tmp64 = gen_addq_msw(tmp64, tmp);
99c475ab 7927 } else {
838fa72d 7928 tmp64 = gen_subq_msw(tmp64, tmp);
99c475ab 7929 }
2c0262af 7930 }
838fa72d
AJ		 7931 if (insn & (1 << 4)) {
7932 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7933 }
7934 tcg_gen_shri_i64(tmp64, tmp64, 32);
7935 tmp = new_tmp();
7936 tcg_gen_trunc_i64_i32(tmp, tmp64);
7937 tcg_temp_free_i64(tmp64);
9ee6e8bb
PB		 7938 break;
7939 case 7: /* Unsigned sum of absolute differences. */
d9ba4830
PB		 7940 gen_helper_usad8(tmp, tmp, tmp2);
7941 dead_tmp(tmp2);
9ee6e8bb 7942 if (rs != 15) {
d9ba4830
PB		 7943 tmp2 = load_reg(s, rs);
7944 tcg_gen_add_i32(tmp, tmp, tmp2);
7945 dead_tmp(tmp2);
5fd46862 7946 }
9ee6e8bb 7947 break;
2c0262af 7948 }
d9ba4830 7949 store_reg(s, rd, tmp);
2c0262af 7950 break;
9ee6e8bb
PB		 7951 case 6: case 7: /* 64-bit multiply, Divide. */
7952 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
5e3f878a
PB		 7953 tmp = load_reg(s, rn);
7954 tmp2 = load_reg(s, rm);
9ee6e8bb
PB		 7955 if ((op & 0x50) == 0x10) {
7956 /* sdiv, udiv */
7957 if (!arm_feature(env, ARM_FEATURE_DIV))
7958 goto illegal_op;
7959 if (op & 0x20)
5e3f878a 7960 gen_helper_udiv(tmp, tmp, tmp2);
2c0262af 7961 else
5e3f878a
PB		 7962 gen_helper_sdiv(tmp, tmp, tmp2);
7963 dead_tmp(tmp2);
7964 store_reg(s, rd, tmp);
9ee6e8bb
PB		 7965 } else if ((op & 0xe) == 0xc) {
7966 /* Dual multiply accumulate long. */
7967 if (op & 1)
5e3f878a
PB		 7968 gen_swap_half(tmp2);
7969 gen_smul_dual(tmp, tmp2);
9ee6e8bb 7970 if (op & 0x10) {
5e3f878a 7971 tcg_gen_sub_i32(tmp, tmp, tmp2);
b5ff1b31 7972 } else {
5e3f878a 7973 tcg_gen_add_i32(tmp, tmp, tmp2);
b5ff1b31 7974 }
5e3f878a 7975 dead_tmp(tmp2);
a7812ae4
PB		 7976 /* BUGFIX */
7977 tmp64 = tcg_temp_new_i64();
7978 tcg_gen_ext_i32_i64(tmp64, tmp);
7979 dead_tmp(tmp);
7980 gen_addq(s, tmp64, rs, rd);
7981 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 7982 tcg_temp_free_i64(tmp64);
2c0262af 7983 } else {
9ee6e8bb
PB		 7984 if (op & 0x20) {
7985 /* Unsigned 64-bit multiply */
a7812ae4 7986 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
b5ff1b31 7987 } else {
9ee6e8bb
PB		 7988 if (op & 8) {
7989 /* smlalxy */
5e3f878a
PB		 7990 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7991 dead_tmp(tmp2);
a7812ae4
PB		 7992 tmp64 = tcg_temp_new_i64();
7993 tcg_gen_ext_i32_i64(tmp64, tmp);
5e3f878a 7994 dead_tmp(tmp);
9ee6e8bb
PB		 7995 } else {
7996 /* Signed 64-bit multiply */
a7812ae4 7997 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9ee6e8bb 7998 }
b5ff1b31 7999 }
9ee6e8bb
PB		 8000 if (op & 4) {
8001 /* umaal */
a7812ae4
PB		 8002 gen_addq_lo(s, tmp64, rs);
8003 gen_addq_lo(s, tmp64, rd);
9ee6e8bb
PB		 8004 } else if (op & 0x40) {
8005 /* 64-bit accumulate. */
a7812ae4 8006 gen_addq(s, tmp64, rs, rd);
9ee6e8bb 8007 }
a7812ae4 8008 gen_storeq_reg(s, rs, rd, tmp64);
b75263d6 8009 tcg_temp_free_i64(tmp64);
5fd46862 8010 }
2c0262af 8011 break;
9ee6e8bb
PB		 8012 }
8013 break;
8014 case 6: case 7: case 14: case 15:
8015 /* Coprocessor. */
8016 if (((insn >> 24) & 3) == 3) {
8017 /* Translate into the equivalent ARM encoding. */
f06053e3 8018 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
9ee6e8bb
PB		 8019 if (disas_neon_data_insn(env, s, insn))
8020 goto illegal_op;
8021 } else {
8022 if (insn & (1 << 28))
8023 goto illegal_op;
8024 if (disas_coproc_insn (env, s, insn))
8025 goto illegal_op;
8026 }
8027 break;
8028 case 8: case 9: case 10: case 11:
8029 if (insn & (1 << 15)) {
8030 /* Branches, misc control. */
8031 if (insn & 0x5000) {
8032 /* Unconditional branch. */
8033 /* signextend(hw1[10:0]) -> offset[:12]. */
8034 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8035 /* hw1[10:0] -> offset[11:1]. */
8036 offset |= (insn & 0x7ff) << 1;
8037 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8038 offset[24:22] already have the same value because of the
8039 sign extension above. */
8040 offset ^= ((~insn) & (1 << 13)) << 10;
8041 offset ^= ((~insn) & (1 << 11)) << 11;
8042
9ee6e8bb
PB		 8043 if (insn & (1 << 14)) {
8044 /* Branch and link. */
3174f8e9 8045 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
b5ff1b31 8046 }
3b46e624 8047
b0109805 8048 offset += s->pc;
9ee6e8bb
PB		 8049 if (insn & (1 << 12)) {
8050 /* b/bl */
b0109805 8051 gen_jmp(s, offset);
9ee6e8bb
PB		 8052 } else {
8053 /* blx */
b0109805
PB		 8054 offset &= ~(uint32_t)2;
8055 gen_bx_im(s, offset);
2c0262af 8056 }
9ee6e8bb
PB		 8057 } else if (((insn >> 23) & 7) == 7) {
8058 /* Misc control */
8059 if (insn & (1 << 13))
8060 goto illegal_op;
8061
8062 if (insn & (1 << 26)) {
8063 /* Secure monitor call (v6Z) */
8064 goto illegal_op; /* not implemented. */
2c0262af 8065 } else {
9ee6e8bb
PB		 8066 op = (insn >> 20) & 7;
8067 switch (op) {
8068 case 0: /* msr cpsr. */
8069 if (IS_M(env)) {
8984bd2e
PB		 8070 tmp = load_reg(s, rn);
8071 addr = tcg_const_i32(insn & 0xff);
8072 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6
JR		 8073 tcg_temp_free_i32(addr);
8074 dead_tmp(tmp);
9ee6e8bb
PB		 8075 gen_lookup_tb(s);
8076 break;
8077 }
8078 /* fall through */
8079 case 1: /* msr spsr. */
8080 if (IS_M(env))
8081 goto illegal_op;
2fbac54b
FN		 8082 tmp = load_reg(s, rn);
8083 if (gen_set_psr(s,
9ee6e8bb 8084 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
2fbac54b 8085 op == 1, tmp))
9ee6e8bb
PB		 8086 goto illegal_op;
8087 break;
8088 case 2: /* cps, nop-hint. */
8089 if (((insn >> 8) & 7) == 0) {
8090 gen_nop_hint(s, insn & 0xff);
8091 }
8092 /* Implemented as NOP in user mode. */
8093 if (IS_USER(s))
8094 break;
8095 offset = 0;
8096 imm = 0;
8097 if (insn & (1 << 10)) {
8098 if (insn & (1 << 7))
8099 offset |= CPSR_A;
8100 if (insn & (1 << 6))
8101 offset |= CPSR_I;
8102 if (insn & (1 << 5))
8103 offset |= CPSR_F;
8104 if (insn & (1 << 9))
8105 imm = CPSR_A | CPSR_I | CPSR_F;
8106 }
8107 if (insn & (1 << 8)) {
8108 offset |= 0x1f;
8109 imm |= (insn & 0x1f);
8110 }
8111 if (offset) {
2fbac54b 8112 gen_set_psr_im(s, offset, 0, imm);
9ee6e8bb
PB		 8113 }
8114 break;
8115 case 3: /* Special control operations. */
426f5abc 8116 ARCH(7);
9ee6e8bb
PB		 8117 op = (insn >> 4) & 0xf;
8118 switch (op) {
8119 case 2: /* clrex */
426f5abc 8120 gen_clrex(s);
9ee6e8bb
PB		 8121 break;
8122 case 4: /* dsb */
8123 case 5: /* dmb */
8124 case 6: /* isb */
8125 /* These execute as NOPs. */
9ee6e8bb
PB		 8126 break;
8127 default:
8128 goto illegal_op;
8129 }
8130 break;
8131 case 4: /* bxj */
8132 /* Trivial implementation equivalent to bx. */
d9ba4830
PB		 8133 tmp = load_reg(s, rn);
8134 gen_bx(s, tmp);
9ee6e8bb
PB		 8135 break;
8136 case 5: /* Exception return. */
b8b45b68
RV		 8137 if (IS_USER(s)) {
8138 goto illegal_op;
8139 }
8140 if (rn != 14 || rd != 15) {
8141 goto illegal_op;
8142 }
8143 tmp = load_reg(s, rn);
8144 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8145 gen_exception_return(s, tmp);
8146 break;
9ee6e8bb 8147 case 6: /* mrs cpsr. */
8984bd2e 8148 tmp = new_tmp();
9ee6e8bb 8149 if (IS_M(env)) {
8984bd2e
PB		 8150 addr = tcg_const_i32(insn & 0xff);
8151 gen_helper_v7m_mrs(tmp, cpu_env, addr);
b75263d6 8152 tcg_temp_free_i32(addr);
9ee6e8bb 8153 } else {
8984bd2e 8154 gen_helper_cpsr_read(tmp);
9ee6e8bb 8155 }
8984bd2e 8156 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8157 break;
8158 case 7: /* mrs spsr. */
8159 /* Not accessible in user mode. */
8160 if (IS_USER(s) || IS_M(env))
8161 goto illegal_op;
d9ba4830
PB		 8162 tmp = load_cpu_field(spsr);
8163 store_reg(s, rd, tmp);
9ee6e8bb 8164 break;
2c0262af
FB		 8165 }
8166 }
9ee6e8bb
PB		 8167 } else {
8168 /* Conditional branch. */
8169 op = (insn >> 22) & 0xf;
8170 /* Generate a conditional jump to next instruction. */
8171 s->condlabel = gen_new_label();
d9ba4830 8172 gen_test_cc(op ^ 1, s->condlabel);
9ee6e8bb
PB		 8173 s->condjmp = 1;
8174
8175 /* offset[11:1] = insn[10:0] */
8176 offset = (insn & 0x7ff) << 1;
8177 /* offset[17:12] = insn[21:16]. */
8178 offset |= (insn & 0x003f0000) >> 4;
8179 /* offset[31:20] = insn[26]. */
8180 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8181 /* offset[18] = insn[13]. */
8182 offset |= (insn & (1 << 13)) << 5;
8183 /* offset[19] = insn[11]. */
8184 offset |= (insn & (1 << 11)) << 8;
8185
8186 /* jump to the offset */
b0109805 8187 gen_jmp(s, s->pc + offset);
9ee6e8bb
PB		 8188 }
8189 } else {
8190 /* Data processing immediate. */
8191 if (insn & (1 << 25)) {
8192 if (insn & (1 << 24)) {
8193 if (insn & (1 << 20))
8194 goto illegal_op;
8195 /* Bitfield/Saturate. */
8196 op = (insn >> 21) & 7;
8197 imm = insn & 0x1f;
8198 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
6ddbc6e4
PB		 8199 if (rn == 15) {
8200 tmp = new_tmp();
8201 tcg_gen_movi_i32(tmp, 0);
8202 } else {
8203 tmp = load_reg(s, rn);
8204 }
9ee6e8bb
PB		 8205 switch (op) {
8206 case 2: /* Signed bitfield extract. */
8207 imm++;
8208 if (shift + imm > 32)
8209 goto illegal_op;
8210 if (imm < 32)
6ddbc6e4 8211 gen_sbfx(tmp, shift, imm);
9ee6e8bb
PB		 8212 break;
8213 case 6: /* Unsigned bitfield extract. */
8214 imm++;
8215 if (shift + imm > 32)
8216 goto illegal_op;
8217 if (imm < 32)
6ddbc6e4 8218 gen_ubfx(tmp, shift, (1u << imm) - 1);
9ee6e8bb
PB		 8219 break;
8220 case 3: /* Bitfield insert/clear. */
8221 if (imm < shift)
8222 goto illegal_op;
8223 imm = imm + 1 - shift;
8224 if (imm != 32) {
6ddbc6e4 8225 tmp2 = load_reg(s, rd);
8f8e3aa4 8226 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
6ddbc6e4 8227 dead_tmp(tmp2);
9ee6e8bb
PB		 8228 }
8229 break;
8230 case 7:
8231 goto illegal_op;
8232 default: /* Saturate. */
9ee6e8bb
PB		 8233 if (shift) {
8234 if (op & 1)
6ddbc6e4 8235 tcg_gen_sari_i32(tmp, tmp, shift);
9ee6e8bb 8236 else
6ddbc6e4 8237 tcg_gen_shli_i32(tmp, tmp, shift);
9ee6e8bb 8238 }
6ddbc6e4 8239 tmp2 = tcg_const_i32(imm);
9ee6e8bb
PB		 8240 if (op & 4) {
8241 /* Unsigned. */
9ee6e8bb 8242 if ((op & 1) && shift == 0)
6ddbc6e4 8243 gen_helper_usat16(tmp, tmp, tmp2);
9ee6e8bb 8244 else
6ddbc6e4 8245 gen_helper_usat(tmp, tmp, tmp2);
2c0262af 8246 } else {
9ee6e8bb 8247 /* Signed. */
9ee6e8bb 8248 if ((op & 1) && shift == 0)
6ddbc6e4 8249 gen_helper_ssat16(tmp, tmp, tmp2);
9ee6e8bb 8250 else
6ddbc6e4 8251 gen_helper_ssat(tmp, tmp, tmp2);
2c0262af 8252 }
b75263d6 8253 tcg_temp_free_i32(tmp2);
9ee6e8bb 8254 break;
2c0262af 8255 }
6ddbc6e4 8256 store_reg(s, rd, tmp);
9ee6e8bb
PB		 8257 } else {
8258 imm = ((insn & 0x04000000) >> 15)
8259 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8260 if (insn & (1 << 22)) {
8261 /* 16-bit immediate. */
8262 imm |= (insn >> 4) & 0xf000;
8263 if (insn & (1 << 23)) {
8264 /* movt */
5e3f878a 8265 tmp = load_reg(s, rd);
86831435 8266 tcg_gen_ext16u_i32(tmp, tmp);
5e3f878a 8267 tcg_gen_ori_i32(tmp, tmp, imm << 16);
2c0262af 8268 } else {
9ee6e8bb 8269 /* movw */
5e3f878a
PB		 8270 tmp = new_tmp();
8271 tcg_gen_movi_i32(tmp, imm);
2c0262af
FB		 8272 }
8273 } else {
9ee6e8bb
PB		 8274 /* Add/sub 12-bit immediate. */
8275 if (rn == 15) {
b0109805 8276 offset = s->pc & ~(uint32_t)3;
9ee6e8bb 8277 if (insn & (1 << 23))
b0109805 8278 offset -= imm;
9ee6e8bb 8279 else
b0109805 8280 offset += imm;
5e3f878a
PB		 8281 tmp = new_tmp();
8282 tcg_gen_movi_i32(tmp, offset);
2c0262af 8283 } else {
5e3f878a 8284 tmp = load_reg(s, rn);
9ee6e8bb 8285 if (insn & (1 << 23))
5e3f878a 8286 tcg_gen_subi_i32(tmp, tmp, imm);
9ee6e8bb 8287 else
5e3f878a 8288 tcg_gen_addi_i32(tmp, tmp, imm);
2c0262af 8289 }
9ee6e8bb 8290 }
5e3f878a 8291 store_reg(s, rd, tmp);
191abaa2 8292 }
9ee6e8bb
PB		 8293 } else {
8294 int shifter_out = 0;
8295 /* modified 12-bit immediate. */
8296 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8297 imm = (insn & 0xff);
8298 switch (shift) {
8299 case 0: /* XY */
8300 /* Nothing to do. */
8301 break;
8302 case 1: /* 00XY00XY */
8303 imm |= imm << 16;
8304 break;
8305 case 2: /* XY00XY00 */
8306 imm |= imm << 16;
8307 imm <<= 8;
8308 break;
8309 case 3: /* XYXYXYXY */
8310 imm |= imm << 16;
8311 imm |= imm << 8;
8312 break;
8313 default: /* Rotated constant. */
8314 shift = (shift << 1) | (imm >> 7);
8315 imm |= 0x80;
8316 imm = imm << (32 - shift);
8317 shifter_out = 1;
8318 break;
b5ff1b31 8319 }
3174f8e9
FN		 8320 tmp2 = new_tmp();
8321 tcg_gen_movi_i32(tmp2, imm);
9ee6e8bb 8322 rn = (insn >> 16) & 0xf;
3174f8e9
FN		 8323 if (rn == 15) {
8324 tmp = new_tmp();
8325 tcg_gen_movi_i32(tmp, 0);
8326 } else {
8327 tmp = load_reg(s, rn);
8328 }
9ee6e8bb
PB		 8329 op = (insn >> 21) & 0xf;
8330 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
3174f8e9 8331 shifter_out, tmp, tmp2))
9ee6e8bb 8332 goto illegal_op;
3174f8e9 8333 dead_tmp(tmp2);
9ee6e8bb
PB		 8334 rd = (insn >> 8) & 0xf;
8335 if (rd != 15) {
3174f8e9
FN		 8336 store_reg(s, rd, tmp);
8337 } else {
8338 dead_tmp(tmp);
2c0262af 8339 }
2c0262af 8340 }
9ee6e8bb
PB		 8341 }
8342 break;
8343 case 12: /* Load/store single data item. */
8344 {
8345 int postinc = 0;
8346 int writeback = 0;
b0109805 8347 int user;
9ee6e8bb
PB		 8348 if ((insn & 0x01100000) == 0x01000000) {
8349 if (disas_neon_ls_insn(env, s, insn))
c1713132 8350 goto illegal_op;
9ee6e8bb
PB		 8351 break;
8352 }
a2fdc890
PM		 8353 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8354 if (rs == 15) {
8355 if (!(insn & (1 << 20))) {
8356 goto illegal_op;
8357 }
8358 if (op != 2) {
8359 /* Byte or halfword load space with dest == r15 : memory hints.
8360 * Catch them early so we don't emit pointless addressing code.
8361 * This space is a mix of:
8362 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8363 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8364 * cores)
8365 * unallocated hints, which must be treated as NOPs
8366 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8367 * which is easiest for the decoding logic
8368 * Some space which must UNDEF
8369 */
8370 int op1 = (insn >> 23) & 3;
8371 int op2 = (insn >> 6) & 0x3f;
8372 if (op & 2) {
8373 goto illegal_op;
8374 }
8375 if (rn == 15) {
8376 /* UNPREDICTABLE or unallocated hint */
8377 return 0;
8378 }
8379 if (op1 & 1) {
8380 return 0; /* PLD* or unallocated hint */
8381 }
8382 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8383 return 0; /* PLD* or unallocated hint */
8384 }
8385 /* UNDEF space, or an UNPREDICTABLE */
8386 return 1;
8387 }
8388 }
b0109805 8389 user = IS_USER(s);
9ee6e8bb 8390 if (rn == 15) {
b0109805 8391 addr = new_tmp();
9ee6e8bb
PB		 8392 /* PC relative. */
8393 /* s->pc has already been incremented by 4. */
8394 imm = s->pc & 0xfffffffc;
8395 if (insn & (1 << 23))
8396 imm += insn & 0xfff;
8397 else
8398 imm -= insn & 0xfff;
b0109805 8399 tcg_gen_movi_i32(addr, imm);
9ee6e8bb 8400 } else {
b0109805 8401 addr = load_reg(s, rn);
9ee6e8bb
PB		 8402 if (insn & (1 << 23)) {
8403 /* Positive offset. */
8404 imm = insn & 0xfff;
b0109805 8405 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb 8406 } else {
9ee6e8bb 8407 imm = insn & 0xff;
a2fdc890 8408 switch ((insn >> 8) & 7) {
9ee6e8bb
PB		 8409 case 0: case 8: /* Shifted Register. */
8410 shift = (insn >> 4) & 0xf;
8411 if (shift > 3)
18c9b560 8412 goto illegal_op;
b26eefb6 8413 tmp = load_reg(s, rm);
9ee6e8bb 8414 if (shift)
b26eefb6 8415 tcg_gen_shli_i32(tmp, tmp, shift);
b0109805 8416 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8417 dead_tmp(tmp);
9ee6e8bb
PB		 8418 break;
8419 case 4: /* Negative offset. */
b0109805 8420 tcg_gen_addi_i32(addr, addr, -imm);
9ee6e8bb
PB		 8421 break;
8422 case 6: /* User privilege. */
b0109805
PB		 8423 tcg_gen_addi_i32(addr, addr, imm);
8424 user = 1;
9ee6e8bb
PB		 8425 break;
8426 case 1: /* Post-decrement. */
8427 imm = -imm;
8428 /* Fall through. */
8429 case 3: /* Post-increment. */
9ee6e8bb
PB		 8430 postinc = 1;
8431 writeback = 1;
8432 break;
8433 case 5: /* Pre-decrement. */
8434 imm = -imm;
8435 /* Fall through. */
8436 case 7: /* Pre-increment. */
b0109805 8437 tcg_gen_addi_i32(addr, addr, imm);
9ee6e8bb
PB		 8438 writeback = 1;
8439 break;
8440 default:
b7bcbe95 8441 goto illegal_op;
9ee6e8bb
PB		 8442 }
8443 }
8444 }
9ee6e8bb
PB		 8445 if (insn & (1 << 20)) {
8446 /* Load. */
a2fdc890
PM		 8447 switch (op) {
8448 case 0: tmp = gen_ld8u(addr, user); break;
8449 case 4: tmp = gen_ld8s(addr, user); break;
8450 case 1: tmp = gen_ld16u(addr, user); break;
8451 case 5: tmp = gen_ld16s(addr, user); break;
8452 case 2: tmp = gen_ld32(addr, user); break;
8453 default: goto illegal_op;
8454 }
8455 if (rs == 15) {
8456 gen_bx(s, tmp);
9ee6e8bb 8457 } else {
a2fdc890 8458 store_reg(s, rs, tmp);
9ee6e8bb
PB		 8459 }
8460 } else {
8461 /* Store. */
b0109805 8462 tmp = load_reg(s, rs);
9ee6e8bb 8463 switch (op) {
b0109805
PB		 8464 case 0: gen_st8(tmp, addr, user); break;
8465 case 1: gen_st16(tmp, addr, user); break;
8466 case 2: gen_st32(tmp, addr, user); break;
9ee6e8bb 8467 default: goto illegal_op;
b7bcbe95 8468 }
2c0262af 8469 }
9ee6e8bb 8470 if (postinc)
b0109805
PB		 8471 tcg_gen_addi_i32(addr, addr, imm);
8472 if (writeback) {
8473 store_reg(s, rn, addr);
8474 } else {
8475 dead_tmp(addr);
8476 }
9ee6e8bb
PB		 8477 }
8478 break;
8479 default:
8480 goto illegal_op;
2c0262af 8481 }
9ee6e8bb
PB		 8482 return 0;
8483illegal_op:
8484 return 1;
2c0262af
FB		 8485}
8486
9ee6e8bb 8487static void disas_thumb_insn(CPUState *env, DisasContext *s)
99c475ab
FB		 8488{
8489 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8490 int32_t offset;
8491 int i;
b26eefb6 8492 TCGv tmp;
d9ba4830 8493 TCGv tmp2;
b0109805 8494 TCGv addr;
99c475ab 8495
9ee6e8bb
PB		 8496 if (s->condexec_mask) {
8497 cond = s->condexec_cond;
bedd2912
JB		 8498 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8499 s->condlabel = gen_new_label();
8500 gen_test_cc(cond ^ 1, s->condlabel);
8501 s->condjmp = 1;
8502 }
9ee6e8bb
PB		 8503 }
8504
b5ff1b31 8505 insn = lduw_code(s->pc);
99c475ab 8506 s->pc += 2;
b5ff1b31 8507
99c475ab
FB		 8508 switch (insn >> 12) {
8509 case 0: case 1:
396e467c 8510
99c475ab
FB		 8511 rd = insn & 7;
8512 op = (insn >> 11) & 3;
8513 if (op == 3) {
8514 /* add/subtract */
8515 rn = (insn >> 3) & 7;
396e467c 8516 tmp = load_reg(s, rn);
99c475ab
FB		 8517 if (insn & (1 << 10)) {
8518 /* immediate */
396e467c
FN		 8519 tmp2 = new_tmp();
8520 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
99c475ab
FB		 8521 } else {
8522 /* reg */
8523 rm = (insn >> 6) & 7;
396e467c 8524 tmp2 = load_reg(s, rm);
99c475ab 8525 }
9ee6e8bb
PB		 8526 if (insn & (1 << 9)) {
8527 if (s->condexec_mask)
396e467c 8528 tcg_gen_sub_i32(tmp, tmp, tmp2);
9ee6e8bb 8529 else
396e467c 8530 gen_helper_sub_cc(tmp, tmp, tmp2);
9ee6e8bb
PB		 8531 } else {
8532 if (s->condexec_mask)
396e467c 8533 tcg_gen_add_i32(tmp, tmp, tmp2);
9ee6e8bb 8534 else
396e467c 8535 gen_helper_add_cc(tmp, tmp, tmp2);
9ee6e8bb 8536 }
396e467c
FN		 8537 dead_tmp(tmp2);
8538 store_reg(s, rd, tmp);
99c475ab
FB		 8539 } else {
8540 /* shift immediate */
8541 rm = (insn >> 3) & 7;
8542 shift = (insn >> 6) & 0x1f;
9a119ff6
PB		 8543 tmp = load_reg(s, rm);
8544 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8545 if (!s->condexec_mask)
8546 gen_logic_CC(tmp);
8547 store_reg(s, rd, tmp);
99c475ab
FB		 8548 }
8549 break;
8550 case 2: case 3:
8551 /* arithmetic large immediate */
8552 op = (insn >> 11) & 3;
8553 rd = (insn >> 8) & 0x7;
396e467c
FN		 8554 if (op == 0) { /* mov */
8555 tmp = new_tmp();
8556 tcg_gen_movi_i32(tmp, insn & 0xff);
9ee6e8bb 8557 if (!s->condexec_mask)
396e467c
FN		 8558 gen_logic_CC(tmp);
8559 store_reg(s, rd, tmp);
8560 } else {
8561 tmp = load_reg(s, rd);
8562 tmp2 = new_tmp();
8563 tcg_gen_movi_i32(tmp2, insn & 0xff);
8564 switch (op) {
8565 case 1: /* cmp */
8566 gen_helper_sub_cc(tmp, tmp, tmp2);
8567 dead_tmp(tmp);
8568 dead_tmp(tmp2);
8569 break;
8570 case 2: /* add */
8571 if (s->condexec_mask)
8572 tcg_gen_add_i32(tmp, tmp, tmp2);
8573 else
8574 gen_helper_add_cc(tmp, tmp, tmp2);
8575 dead_tmp(tmp2);
8576 store_reg(s, rd, tmp);
8577 break;
8578 case 3: /* sub */
8579 if (s->condexec_mask)
8580 tcg_gen_sub_i32(tmp, tmp, tmp2);
8581 else
8582 gen_helper_sub_cc(tmp, tmp, tmp2);
8583 dead_tmp(tmp2);
8584 store_reg(s, rd, tmp);
8585 break;
8586 }
99c475ab 8587 }
99c475ab
FB		 8588 break;
8589 case 4:
8590 if (insn & (1 << 11)) {
8591 rd = (insn >> 8) & 7;
5899f386
FB		 8592 /* load pc-relative. Bit 1 of PC is ignored. */
8593 val = s->pc + 2 + ((insn & 0xff) * 4);
8594 val &= ~(uint32_t)2;
b0109805
PB		 8595 addr = new_tmp();
8596 tcg_gen_movi_i32(addr, val);
8597 tmp = gen_ld32(addr, IS_USER(s));
8598 dead_tmp(addr);
8599 store_reg(s, rd, tmp);
99c475ab
FB		 8600 break;
8601 }
8602 if (insn & (1 << 10)) {
8603 /* data processing extended or blx */
8604 rd = (insn & 7) | ((insn >> 4) & 8);
8605 rm = (insn >> 3) & 0xf;
8606 op = (insn >> 8) & 3;
8607 switch (op) {
8608 case 0: /* add */
396e467c
FN		 8609 tmp = load_reg(s, rd);
8610 tmp2 = load_reg(s, rm);
8611 tcg_gen_add_i32(tmp, tmp, tmp2);
8612 dead_tmp(tmp2);
8613 store_reg(s, rd, tmp);
99c475ab
FB		 8614 break;
8615 case 1: /* cmp */
396e467c
FN		 8616 tmp = load_reg(s, rd);
8617 tmp2 = load_reg(s, rm);
8618 gen_helper_sub_cc(tmp, tmp, tmp2);
8619 dead_tmp(tmp2);
8620 dead_tmp(tmp);
99c475ab
FB		 8621 break;
8622 case 2: /* mov/cpy */
396e467c
FN		 8623 tmp = load_reg(s, rm);
8624 store_reg(s, rd, tmp);
99c475ab
FB		 8625 break;
8626 case 3:/* branch [and link] exchange thumb register */
b0109805 8627 tmp = load_reg(s, rm);
99c475ab
FB		 8628 if (insn & (1 << 7)) {
8629 val = (uint32_t)s->pc | 1;
b0109805
PB		 8630 tmp2 = new_tmp();
8631 tcg_gen_movi_i32(tmp2, val);
8632 store_reg(s, 14, tmp2);
99c475ab 8633 }
d9ba4830 8634 gen_bx(s, tmp);
99c475ab
FB		 8635 break;
8636 }
8637 break;
8638 }
8639
8640 /* data processing register */
8641 rd = insn & 7;
8642 rm = (insn >> 3) & 7;
8643 op = (insn >> 6) & 0xf;
8644 if (op == 2 || op == 3 || op == 4 || op == 7) {
8645 /* the shift/rotate ops want the operands backwards */
8646 val = rm;
8647 rm = rd;
8648 rd = val;
8649 val = 1;
8650 } else {
8651 val = 0;
8652 }
8653
396e467c
FN		 8654 if (op == 9) { /* neg */
8655 tmp = new_tmp();
8656 tcg_gen_movi_i32(tmp, 0);
8657 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8658 tmp = load_reg(s, rd);
8659 } else {
8660 TCGV_UNUSED(tmp);
8661 }
99c475ab 8662
396e467c 8663 tmp2 = load_reg(s, rm);
5899f386 8664 switch (op) {
99c475ab 8665 case 0x0: /* and */
396e467c 8666 tcg_gen_and_i32(tmp, tmp, tmp2);
9ee6e8bb 8667 if (!s->condexec_mask)
396e467c 8668 gen_logic_CC(tmp);
99c475ab
FB		 8669 break;
8670 case 0x1: /* eor */
396e467c 8671 tcg_gen_xor_i32(tmp, tmp, tmp2);
9ee6e8bb 8672 if (!s->condexec_mask)
396e467c 8673 gen_logic_CC(tmp);
99c475ab
FB		 8674 break;
8675 case 0x2: /* lsl */
9ee6e8bb 8676 if (s->condexec_mask) {
396e467c 8677 gen_helper_shl(tmp2, tmp2, tmp);
9ee6e8bb 8678 } else {
396e467c
FN		 8679 gen_helper_shl_cc(tmp2, tmp2, tmp);
8680 gen_logic_CC(tmp2);
9ee6e8bb 8681 }
99c475ab
FB		 8682 break;
8683 case 0x3: /* lsr */
9ee6e8bb 8684 if (s->condexec_mask) {
396e467c 8685 gen_helper_shr(tmp2, tmp2, tmp);
9ee6e8bb 8686 } else {
396e467c
FN		 8687 gen_helper_shr_cc(tmp2, tmp2, tmp);
8688 gen_logic_CC(tmp2);
9ee6e8bb 8689 }
99c475ab
FB		 8690 break;
8691 case 0x4: /* asr */
9ee6e8bb 8692 if (s->condexec_mask) {
396e467c 8693 gen_helper_sar(tmp2, tmp2, tmp);
9ee6e8bb 8694 } else {
396e467c
FN		 8695 gen_helper_sar_cc(tmp2, tmp2, tmp);
8696 gen_logic_CC(tmp2);
9ee6e8bb 8697 }
99c475ab
FB		 8698 break;
8699 case 0x5: /* adc */
9ee6e8bb 8700 if (s->condexec_mask)
396e467c 8701 gen_adc(tmp, tmp2);
9ee6e8bb 8702 else
396e467c 8703 gen_helper_adc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8704 break;
8705 case 0x6: /* sbc */
9ee6e8bb 8706 if (s->condexec_mask)
396e467c 8707 gen_sub_carry(tmp, tmp, tmp2);
9ee6e8bb 8708 else
396e467c 8709 gen_helper_sbc_cc(tmp, tmp, tmp2);
99c475ab
FB		 8710 break;
8711 case 0x7: /* ror */
9ee6e8bb 8712 if (s->condexec_mask) {
f669df27
AJ		 8713 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8714 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9ee6e8bb 8715 } else {
396e467c
FN		 8716 gen_helper_ror_cc(tmp2, tmp2, tmp);
8717 gen_logic_CC(tmp2);
9ee6e8bb 8718 }
99c475ab
FB		 8719 break;
8720 case 0x8: /* tst */
396e467c
FN		 8721 tcg_gen_and_i32(tmp, tmp, tmp2);
8722 gen_logic_CC(tmp);
99c475ab 8723 rd = 16;
5899f386 8724 break;
99c475ab 8725 case 0x9: /* neg */
9ee6e8bb 8726 if (s->condexec_mask)
396e467c 8727 tcg_gen_neg_i32(tmp, tmp2);
9ee6e8bb 8728 else
396e467c 8729 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8730 break;
8731 case 0xa: /* cmp */
396e467c 8732 gen_helper_sub_cc(tmp, tmp, tmp2);
99c475ab
FB		 8733 rd = 16;
8734 break;
8735 case 0xb: /* cmn */
396e467c 8736 gen_helper_add_cc(tmp, tmp, tmp2);
99c475ab
FB		 8737 rd = 16;
8738 break;
8739 case 0xc: /* orr */
396e467c 8740 tcg_gen_or_i32(tmp, tmp, tmp2);
9ee6e8bb 8741 if (!s->condexec_mask)
396e467c 8742 gen_logic_CC(tmp);
99c475ab
FB		 8743 break;
8744 case 0xd: /* mul */
7b2919a0 8745 tcg_gen_mul_i32(tmp, tmp, tmp2);
9ee6e8bb 8746 if (!s->condexec_mask)
396e467c 8747 gen_logic_CC(tmp);
99c475ab
FB		 8748 break;
8749 case 0xe: /* bic */
f669df27 8750 tcg_gen_andc_i32(tmp, tmp, tmp2);
9ee6e8bb 8751 if (!s->condexec_mask)
396e467c 8752 gen_logic_CC(tmp);
99c475ab
FB		 8753 break;
8754 case 0xf: /* mvn */
396e467c 8755 tcg_gen_not_i32(tmp2, tmp2);
9ee6e8bb 8756 if (!s->condexec_mask)
396e467c 8757 gen_logic_CC(tmp2);
99c475ab 8758 val = 1;
5899f386 8759 rm = rd;
99c475ab
FB		 8760 break;
8761 }
8762 if (rd != 16) {
396e467c
FN		 8763 if (val) {
8764 store_reg(s, rm, tmp2);
8765 if (op != 0xf)
8766 dead_tmp(tmp);
8767 } else {
8768 store_reg(s, rd, tmp);
8769 dead_tmp(tmp2);
8770 }
8771 } else {
8772 dead_tmp(tmp);
8773 dead_tmp(tmp2);
99c475ab
FB		 8774 }
8775 break;
8776
8777 case 5:
8778 /* load/store register offset. */
8779 rd = insn & 7;
8780 rn = (insn >> 3) & 7;
8781 rm = (insn >> 6) & 7;
8782 op = (insn >> 9) & 7;
b0109805 8783 addr = load_reg(s, rn);
b26eefb6 8784 tmp = load_reg(s, rm);
b0109805 8785 tcg_gen_add_i32(addr, addr, tmp);
b26eefb6 8786 dead_tmp(tmp);
99c475ab
FB		 8787
8788 if (op < 3) /* store */
b0109805 8789 tmp = load_reg(s, rd);
99c475ab
FB		 8790
8791 switch (op) {
8792 case 0: /* str */
b0109805 8793 gen_st32(tmp, addr, IS_USER(s));
99c475ab
FB		 8794 break;
8795 case 1: /* strh */
b0109805 8796 gen_st16(tmp, addr, IS_USER(s));
99c475ab
FB		 8797 break;
8798 case 2: /* strb */
b0109805 8799 gen_st8(tmp, addr, IS_USER(s));
99c475ab
FB		 8800 break;
8801 case 3: /* ldrsb */
b0109805 8802 tmp = gen_ld8s(addr, IS_USER(s));
99c475ab
FB		 8803 break;
8804 case 4: /* ldr */
b0109805 8805 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8806 break;
8807 case 5: /* ldrh */
b0109805 8808 tmp = gen_ld16u(addr, IS_USER(s));
99c475ab
FB		 8809 break;
8810 case 6: /* ldrb */
b0109805 8811 tmp = gen_ld8u(addr, IS_USER(s));
99c475ab
FB		 8812 break;
8813 case 7: /* ldrsh */
b0109805 8814 tmp = gen_ld16s(addr, IS_USER(s));
99c475ab
FB		 8815 break;
8816 }
8817 if (op >= 3) /* load */
b0109805
PB		 8818 store_reg(s, rd, tmp);
8819 dead_tmp(addr);
99c475ab
FB		 8820 break;
8821
8822 case 6:
8823 /* load/store word immediate offset */
8824 rd = insn & 7;
8825 rn = (insn >> 3) & 7;
b0109805 8826 addr = load_reg(s, rn);
99c475ab 8827 val = (insn >> 4) & 0x7c;
b0109805 8828 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8829
8830 if (insn & (1 << 11)) {
8831 /* load */
b0109805
PB		 8832 tmp = gen_ld32(addr, IS_USER(s));
8833 store_reg(s, rd, tmp);
99c475ab
FB		 8834 } else {
8835 /* store */
b0109805
PB		 8836 tmp = load_reg(s, rd);
8837 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8838 }
b0109805 8839 dead_tmp(addr);
99c475ab
FB		 8840 break;
8841
8842 case 7:
8843 /* load/store byte immediate offset */
8844 rd = insn & 7;
8845 rn = (insn >> 3) & 7;
b0109805 8846 addr = load_reg(s, rn);
99c475ab 8847 val = (insn >> 6) & 0x1f;
b0109805 8848 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8849
8850 if (insn & (1 << 11)) {
8851 /* load */
b0109805
PB		 8852 tmp = gen_ld8u(addr, IS_USER(s));
8853 store_reg(s, rd, tmp);
99c475ab
FB		 8854 } else {
8855 /* store */
b0109805
PB		 8856 tmp = load_reg(s, rd);
8857 gen_st8(tmp, addr, IS_USER(s));
99c475ab 8858 }
b0109805 8859 dead_tmp(addr);
99c475ab
FB		 8860 break;
8861
8862 case 8:
8863 /* load/store halfword immediate offset */
8864 rd = insn & 7;
8865 rn = (insn >> 3) & 7;
b0109805 8866 addr = load_reg(s, rn);
99c475ab 8867 val = (insn >> 5) & 0x3e;
b0109805 8868 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8869
8870 if (insn & (1 << 11)) {
8871 /* load */
b0109805
PB		 8872 tmp = gen_ld16u(addr, IS_USER(s));
8873 store_reg(s, rd, tmp);
99c475ab
FB		 8874 } else {
8875 /* store */
b0109805
PB		 8876 tmp = load_reg(s, rd);
8877 gen_st16(tmp, addr, IS_USER(s));
99c475ab 8878 }
b0109805 8879 dead_tmp(addr);
99c475ab
FB		 8880 break;
8881
8882 case 9:
8883 /* load/store from stack */
8884 rd = (insn >> 8) & 7;
b0109805 8885 addr = load_reg(s, 13);
99c475ab 8886 val = (insn & 0xff) * 4;
b0109805 8887 tcg_gen_addi_i32(addr, addr, val);
99c475ab
FB		 8888
8889 if (insn & (1 << 11)) {
8890 /* load */
b0109805
PB		 8891 tmp = gen_ld32(addr, IS_USER(s));
8892 store_reg(s, rd, tmp);
99c475ab
FB		 8893 } else {
8894 /* store */
b0109805
PB		 8895 tmp = load_reg(s, rd);
8896 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8897 }
b0109805 8898 dead_tmp(addr);
99c475ab
FB		 8899 break;
8900
8901 case 10:
8902 /* add to high reg */
8903 rd = (insn >> 8) & 7;
5899f386
FB		 8904 if (insn & (1 << 11)) {
8905 /* SP */
5e3f878a 8906 tmp = load_reg(s, 13);
5899f386
FB		 8907 } else {
8908 /* PC. bit 1 is ignored. */
5e3f878a
PB		 8909 tmp = new_tmp();
8910 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
5899f386 8911 }
99c475ab 8912 val = (insn & 0xff) * 4;
5e3f878a
PB		 8913 tcg_gen_addi_i32(tmp, tmp, val);
8914 store_reg(s, rd, tmp);
99c475ab
FB		 8915 break;
8916
8917 case 11:
8918 /* misc */
8919 op = (insn >> 8) & 0xf;
8920 switch (op) {
8921 case 0:
8922 /* adjust stack pointer */
b26eefb6 8923 tmp = load_reg(s, 13);
99c475ab
FB		 8924 val = (insn & 0x7f) * 4;
8925 if (insn & (1 << 7))
6a0d8a1d 8926 val = -(int32_t)val;
b26eefb6
PB		 8927 tcg_gen_addi_i32(tmp, tmp, val);
8928 store_reg(s, 13, tmp);
99c475ab
FB		 8929 break;
8930
9ee6e8bb
PB		 8931 case 2: /* sign/zero extend. */
8932 ARCH(6);
8933 rd = insn & 7;
8934 rm = (insn >> 3) & 7;
b0109805 8935 tmp = load_reg(s, rm);
9ee6e8bb 8936 switch ((insn >> 6) & 3) {
b0109805
PB		 8937 case 0: gen_sxth(tmp); break;
8938 case 1: gen_sxtb(tmp); break;
8939 case 2: gen_uxth(tmp); break;
8940 case 3: gen_uxtb(tmp); break;
9ee6e8bb 8941 }
b0109805 8942 store_reg(s, rd, tmp);
9ee6e8bb 8943 break;
99c475ab
FB		 8944 case 4: case 5: case 0xc: case 0xd:
8945 /* push/pop */
b0109805 8946 addr = load_reg(s, 13);
5899f386
FB		 8947 if (insn & (1 << 8))
8948 offset = 4;
99c475ab 8949 else
5899f386
FB		 8950 offset = 0;
8951 for (i = 0; i < 8; i++) {
8952 if (insn & (1 << i))
8953 offset += 4;
8954 }
8955 if ((insn & (1 << 11)) == 0) {
b0109805 8956 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8957 }
99c475ab
FB		 8958 for (i = 0; i < 8; i++) {
8959 if (insn & (1 << i)) {
8960 if (insn & (1 << 11)) {
8961 /* pop */
b0109805
PB		 8962 tmp = gen_ld32(addr, IS_USER(s));
8963 store_reg(s, i, tmp);
99c475ab
FB		 8964 } else {
8965 /* push */
b0109805
PB		 8966 tmp = load_reg(s, i);
8967 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8968 }
5899f386 8969 /* advance to the next address. */
b0109805 8970 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 8971 }
8972 }
a50f5b91 8973 TCGV_UNUSED(tmp);
99c475ab
FB		 8974 if (insn & (1 << 8)) {
8975 if (insn & (1 << 11)) {
8976 /* pop pc */
b0109805 8977 tmp = gen_ld32(addr, IS_USER(s));
99c475ab
FB		 8978 /* don't set the pc until the rest of the instruction
8979 has completed */
8980 } else {
8981 /* push lr */
b0109805
PB		 8982 tmp = load_reg(s, 14);
8983 gen_st32(tmp, addr, IS_USER(s));
99c475ab 8984 }
b0109805 8985 tcg_gen_addi_i32(addr, addr, 4);
99c475ab 8986 }
5899f386 8987 if ((insn & (1 << 11)) == 0) {
b0109805 8988 tcg_gen_addi_i32(addr, addr, -offset);
5899f386 8989 }
99c475ab 8990 /* write back the new stack pointer */
b0109805 8991 store_reg(s, 13, addr);
99c475ab
FB		 8992 /* set the new PC value */
8993 if ((insn & 0x0900) == 0x0900)
b0109805 8994 gen_bx(s, tmp);
99c475ab
FB		 8995 break;
8996
9ee6e8bb
PB		 8997 case 1: case 3: case 9: case 11: /* czb */
8998 rm = insn & 7;
d9ba4830 8999 tmp = load_reg(s, rm);
9ee6e8bb
PB		 9000 s->condlabel = gen_new_label();
9001 s->condjmp = 1;
9002 if (insn & (1 << 11))
cb63669a 9003 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9ee6e8bb 9004 else
cb63669a 9005 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
d9ba4830 9006 dead_tmp(tmp);
9ee6e8bb
PB		 9007 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
9008 val = (uint32_t)s->pc + 2;
9009 val += offset;
9010 gen_jmp(s, val);
9011 break;
9012
9013 case 15: /* IT, nop-hint. */
9014 if ((insn & 0xf) == 0) {
9015 gen_nop_hint(s, (insn >> 4) & 0xf);
9016 break;
9017 }
9018 /* If Then. */
9019 s->condexec_cond = (insn >> 4) & 0xe;
9020 s->condexec_mask = insn & 0x1f;
9021 /* No actual code generated for this insn, just setup state. */
9022 break;
9023
06c949e6 9024 case 0xe: /* bkpt */
bc4a0de0 9025 gen_exception_insn(s, 2, EXCP_BKPT);
06c949e6
PB		 9026 break;
9027
9ee6e8bb
PB		 9028 case 0xa: /* rev */
9029 ARCH(6);
9030 rn = (insn >> 3) & 0x7;
9031 rd = insn & 0x7;
b0109805 9032 tmp = load_reg(s, rn);
9ee6e8bb 9033 switch ((insn >> 6) & 3) {
66896cb8 9034 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
b0109805
PB		 9035 case 1: gen_rev16(tmp); break;
9036 case 3: gen_revsh(tmp); break;
9ee6e8bb
PB		 9037 default: goto illegal_op;
9038 }
b0109805 9039 store_reg(s, rd, tmp);
9ee6e8bb
PB		 9040 break;
9041
9042 case 6: /* cps */
9043 ARCH(6);
9044 if (IS_USER(s))
9045 break;
9046 if (IS_M(env)) {
8984bd2e 9047 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9ee6e8bb 9048 /* PRIMASK */
8984bd2e
PB		 9049 if (insn & 1) {
9050 addr = tcg_const_i32(16);
9051 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9052 tcg_temp_free_i32(addr);
8984bd2e 9053 }
9ee6e8bb 9054 /* FAULTMASK */
8984bd2e
PB		 9055 if (insn & 2) {
9056 addr = tcg_const_i32(17);
9057 gen_helper_v7m_msr(cpu_env, addr, tmp);
b75263d6 9058 tcg_temp_free_i32(addr);
8984bd2e 9059 }
b75263d6 9060 tcg_temp_free_i32(tmp);
9ee6e8bb
PB		 9061 gen_lookup_tb(s);
9062 } else {
9063 if (insn & (1 << 4))
9064 shift = CPSR_A | CPSR_I | CPSR_F;
9065 else
9066 shift = 0;
fa26df03 9067 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9ee6e8bb
PB		 9068 }
9069 break;
9070
99c475ab
FB		 9071 default:
9072 goto undef;
9073 }
9074 break;
9075
9076 case 12:
9077 /* load/store multiple */
9078 rn = (insn >> 8) & 0x7;
b0109805 9079 addr = load_reg(s, rn);
99c475ab
FB		 9080 for (i = 0; i < 8; i++) {
9081 if (insn & (1 << i)) {
99c475ab
FB		 9082 if (insn & (1 << 11)) {
9083 /* load */
b0109805
PB		 9084 tmp = gen_ld32(addr, IS_USER(s));
9085 store_reg(s, i, tmp);
99c475ab
FB		 9086 } else {
9087 /* store */
b0109805
PB		 9088 tmp = load_reg(s, i);
9089 gen_st32(tmp, addr, IS_USER(s));
99c475ab 9090 }
5899f386 9091 /* advance to the next address */
b0109805 9092 tcg_gen_addi_i32(addr, addr, 4);
99c475ab
FB		 9093 }
9094 }
5899f386 9095 /* Base register writeback. */
b0109805
PB		 9096 if ((insn & (1 << rn)) == 0) {
9097 store_reg(s, rn, addr);
9098 } else {
9099 dead_tmp(addr);
9100 }
99c475ab
FB		 9101 break;
9102
9103 case 13:
9104 /* conditional branch or swi */
9105 cond = (insn >> 8) & 0xf;
9106 if (cond == 0xe)
9107 goto undef;
9108
9109 if (cond == 0xf) {
9110 /* swi */
422ebf69 9111 gen_set_pc_im(s->pc);
9ee6e8bb 9112 s->is_jmp = DISAS_SWI;
99c475ab
FB		 9113 break;
9114 }
9115 /* generate a conditional jump to next instruction */
e50e6a20 9116 s->condlabel = gen_new_label();
d9ba4830 9117 gen_test_cc(cond ^ 1, s->condlabel);
e50e6a20 9118 s->condjmp = 1;
99c475ab
FB		 9119
9120 /* jump to the offset */
5899f386 9121 val = (uint32_t)s->pc + 2;
99c475ab 9122 offset = ((int32_t)insn << 24) >> 24;
5899f386 9123 val += offset << 1;
8aaca4c0 9124 gen_jmp(s, val);
99c475ab
FB		 9125 break;
9126
9127 case 14:
358bf29e 9128 if (insn & (1 << 11)) {
9ee6e8bb
PB		 9129 if (disas_thumb2_insn(env, s, insn))
9130 goto undef32;
358bf29e
PB		 9131 break;
9132 }
9ee6e8bb 9133 /* unconditional branch */
99c475ab
FB		 9134 val = (uint32_t)s->pc;
9135 offset = ((int32_t)insn << 21) >> 21;
9136 val += (offset << 1) + 2;
8aaca4c0 9137 gen_jmp(s, val);
99c475ab
FB		 9138 break;
9139
9140 case 15:
9ee6e8bb 9141 if (disas_thumb2_insn(env, s, insn))
6a0d8a1d 9142 goto undef32;
9ee6e8bb 9143 break;
99c475ab
FB		 9144 }
9145 return;
9ee6e8bb 9146undef32:
bc4a0de0 9147 gen_exception_insn(s, 4, EXCP_UDEF);
9ee6e8bb
PB		 9148 return;
9149illegal_op:
99c475ab 9150undef:
bc4a0de0 9151 gen_exception_insn(s, 2, EXCP_UDEF);
99c475ab
FB		 9152}
9153
2c0262af
FB		 9154/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9155 basic block 'tb'. If search_pc is TRUE, also generate PC
9156 information for each intermediate instruction. */
2cfc5f17
TS		 9157static inline void gen_intermediate_code_internal(CPUState *env,
9158 TranslationBlock *tb,
9159 int search_pc)
2c0262af
FB		 9160{
9161 DisasContext dc1, *dc = &dc1;
a1d1bb31 9162 CPUBreakpoint *bp;
2c0262af
FB		 9163 uint16_t *gen_opc_end;
9164 int j, lj;
0fa85d43 9165 target_ulong pc_start;
b5ff1b31 9166 uint32_t next_page_start;
2e70f6ef
PB		 9167 int num_insns;
9168 int max_insns;
3b46e624 9169
2c0262af 9170 /* generate intermediate code */
b26eefb6 9171 num_temps = 0;
b26eefb6 9172
0fa85d43 9173 pc_start = tb->pc;
3b46e624 9174
2c0262af
FB		 9175 dc->tb = tb;
9176
2c0262af 9177 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2c0262af
FB		 9178
9179 dc->is_jmp = DISAS_NEXT;
9180 dc->pc = pc_start;
8aaca4c0 9181 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 9182 dc->condjmp = 0;
7204ab88 9183 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
98eac7ca
PM		 9184 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9185 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
b5ff1b31 9186#if !defined(CONFIG_USER_ONLY)
61f74d6a 9187 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
b5ff1b31 9188#endif
5df8bac1 9189 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
69d1fc22
PM		 9190 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9191 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
a7812ae4
PB		 9192 cpu_F0s = tcg_temp_new_i32();
9193 cpu_F1s = tcg_temp_new_i32();
9194 cpu_F0d = tcg_temp_new_i64();
9195 cpu_F1d = tcg_temp_new_i64();
ad69471c
PB		 9196 cpu_V0 = cpu_F0d;
9197 cpu_V1 = cpu_F1d;
e677137d 9198 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
a7812ae4 9199 cpu_M0 = tcg_temp_new_i64();
b5ff1b31 9200 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2c0262af 9201 lj = -1;
2e70f6ef
PB		 9202 num_insns = 0;
9203 max_insns = tb->cflags & CF_COUNT_MASK;
9204 if (max_insns == 0)
9205 max_insns = CF_COUNT_MASK;
9206
9207 gen_icount_start();
e12ce78d
PM		 9208
9209 /* A note on handling of the condexec (IT) bits:
9210 *
9211 * We want to avoid the overhead of having to write the updated condexec
9212 * bits back to the CPUState for every instruction in an IT block. So:
9213 * (1) if the condexec bits are not already zero then we write
9214 * zero back into the CPUState now. This avoids complications trying
9215 * to do it at the end of the block. (For example if we don't do this
9216 * it's hard to identify whether we can safely skip writing condexec
9217 * at the end of the TB, which we definitely want to do for the case
9218 * where a TB doesn't do anything with the IT state at all.)
9219 * (2) if we are going to leave the TB then we call gen_set_condexec()
9220 * which will write the correct value into CPUState if zero is wrong.
9221 * This is done both for leaving the TB at the end, and for leaving
9222 * it because of an exception we know will happen, which is done in
9223 * gen_exception_insn(). The latter is necessary because we need to
9224 * leave the TB with the PC/IT state just prior to execution of the
9225 * instruction which caused the exception.
9226 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9227 * then the CPUState will be wrong and we need to reset it.
9228 * This is handled in the same way as restoration of the
9229 * PC in these situations: we will be called again with search_pc=1
9230 * and generate a mapping of the condexec bits for each PC in
9231 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9232 * the condexec bits.
9233 *
9234 * Note that there are no instructions which can read the condexec
9235 * bits, and none which can write non-static values to them, so
9236 * we don't need to care about whether CPUState is correct in the
9237 * middle of a TB.
9238 */
9239
9ee6e8bb
PB		 9240 /* Reset the conditional execution bits immediately. This avoids
9241 complications trying to do it at the end of the block. */
98eac7ca 9242 if (dc->condexec_mask || dc->condexec_cond)
8f01245e
PB		 9243 {
9244 TCGv tmp = new_tmp();
9245 tcg_gen_movi_i32(tmp, 0);
d9ba4830 9246 store_cpu_field(tmp, condexec_bits);
8f01245e 9247 }
2c0262af 9248 do {
fbb4a2e3
PB		 9249#ifdef CONFIG_USER_ONLY
9250 /* Intercept jump to the magic kernel page. */
9251 if (dc->pc >= 0xffff0000) {
9252 /* We always get here via a jump, so know we are not in a
9253 conditional execution block. */
9254 gen_exception(EXCP_KERNEL_TRAP);
9255 dc->is_jmp = DISAS_UPDATE;
9256 break;
9257 }
9258#else
9ee6e8bb
PB		 9259 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9260 /* We always get here via a jump, so know we are not in a
9261 conditional execution block. */
d9ba4830 9262 gen_exception(EXCP_EXCEPTION_EXIT);
d60bb01c
PB		 9263 dc->is_jmp = DISAS_UPDATE;
9264 break;
9ee6e8bb
PB		 9265 }
9266#endif
9267
72cf2d4f
BS		 9268 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9269 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 9270 if (bp->pc == dc->pc) {
bc4a0de0 9271 gen_exception_insn(dc, 0, EXCP_DEBUG);
9ee6e8bb
PB		 9272 /* Advance PC so that clearing the breakpoint will
9273 invalidate this TB. */
9274 dc->pc += 2;
9275 goto done_generating;
1fddef4b
FB		 9276 break;
9277 }
9278 }
9279 }
2c0262af
FB		 9280 if (search_pc) {
9281 j = gen_opc_ptr - gen_opc_buf;
9282 if (lj < j) {
9283 lj++;
9284 while (lj < j)
9285 gen_opc_instr_start[lj++] = 0;
9286 }
0fa85d43 9287 gen_opc_pc[lj] = dc->pc;
e12ce78d 9288 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
2c0262af 9289 gen_opc_instr_start[lj] = 1;
2e70f6ef 9290 gen_opc_icount[lj] = num_insns;
2c0262af 9291 }
e50e6a20 9292
2e70f6ef
PB		 9293 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9294 gen_io_start();
9295
5642463a
PM		 9296 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9297 tcg_gen_debug_insn_start(dc->pc);
9298 }
9299
7204ab88 9300 if (dc->thumb) {
9ee6e8bb
PB		 9301 disas_thumb_insn(env, dc);
9302 if (dc->condexec_mask) {
9303 dc->condexec_cond = (dc->condexec_cond & 0xe)
9304 | ((dc->condexec_mask >> 4) & 1);
9305 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9306 if (dc->condexec_mask == 0) {
9307 dc->condexec_cond = 0;
9308 }
9309 }
9310 } else {
9311 disas_arm_insn(env, dc);
9312 }
b26eefb6
PB		 9313 if (num_temps) {
9314 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9315 num_temps = 0;
9316 }
e50e6a20
FB		 9317
9318 if (dc->condjmp && !dc->is_jmp) {
9319 gen_set_label(dc->condlabel);
9320 dc->condjmp = 0;
9321 }
aaf2d97d 9322 /* Translation stops when a conditional branch is encountered.
e50e6a20 9323 * Otherwise the subsequent code could get translated several times.
b5ff1b31 9324 * Also stop translation when a page boundary is reached. This
bf20dc07 9325 * ensures prefetch aborts occur at the right place. */
2e70f6ef 9326 num_insns ++;
1fddef4b
FB		 9327 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9328 !env->singlestep_enabled &&
1b530a6d 9329 !singlestep &&
2e70f6ef
PB		 9330 dc->pc < next_page_start &&
9331 num_insns < max_insns);
9332
9333 if (tb->cflags & CF_LAST_IO) {
9334 if (dc->condjmp) {
9335 /* FIXME: This can theoretically happen with self-modifying
9336 code. */
9337 cpu_abort(env, "IO on conditional branch instruction");
9338 }
9339 gen_io_end();
9340 }
9ee6e8bb 9341
b5ff1b31 9342 /* At this stage dc->condjmp will only be set when the skipped
9ee6e8bb
PB		 9343 instruction was a conditional branch or trap, and the PC has
9344 already been written. */
551bd27f 9345 if (unlikely(env->singlestep_enabled)) {
8aaca4c0 9346 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20 9347 if (dc->condjmp) {
9ee6e8bb
PB		 9348 gen_set_condexec(dc);
9349 if (dc->is_jmp == DISAS_SWI) {
d9ba4830 9350 gen_exception(EXCP_SWI);
9ee6e8bb 9351 } else {
d9ba4830 9352 gen_exception(EXCP_DEBUG);
9ee6e8bb 9353 }
e50e6a20
FB		 9354 gen_set_label(dc->condlabel);
9355 }
9356 if (dc->condjmp || !dc->is_jmp) {
5e3f878a 9357 gen_set_pc_im(dc->pc);
e50e6a20 9358 dc->condjmp = 0;
8aaca4c0 9359 }
9ee6e8bb
PB		 9360 gen_set_condexec(dc);
9361 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
d9ba4830 9362 gen_exception(EXCP_SWI);
9ee6e8bb
PB		 9363 } else {
9364 /* FIXME: Single stepping a WFI insn will not halt
9365 the CPU. */
d9ba4830 9366 gen_exception(EXCP_DEBUG);
9ee6e8bb 9367 }
8aaca4c0 9368 } else {
9ee6e8bb
PB		 9369 /* While branches must always occur at the end of an IT block,
9370 there are a few other things that can cause us to terminate
9371 the TB in the middel of an IT block:
9372 - Exception generating instructions (bkpt, swi, undefined).
9373 - Page boundaries.
9374 - Hardware watchpoints.
9375 Hardware breakpoints have already been handled and skip this code.
9376 */
9377 gen_set_condexec(dc);
8aaca4c0 9378 switch(dc->is_jmp) {
8aaca4c0 9379 case DISAS_NEXT:
6e256c93 9380 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 9381 break;
9382 default:
9383 case DISAS_JUMP:
9384 case DISAS_UPDATE:
9385 /* indicate that the hash table must be used to find the next TB */
57fec1fe 9386 tcg_gen_exit_tb(0);
8aaca4c0
FB		 9387 break;
9388 case DISAS_TB_JUMP:
9389 /* nothing more to generate */
9390 break;
9ee6e8bb 9391 case DISAS_WFI:
d9ba4830 9392 gen_helper_wfi();
9ee6e8bb
PB		 9393 break;
9394 case DISAS_SWI:
d9ba4830 9395 gen_exception(EXCP_SWI);
9ee6e8bb 9396 break;
8aaca4c0 9397 }
e50e6a20
FB		 9398 if (dc->condjmp) {
9399 gen_set_label(dc->condlabel);
9ee6e8bb 9400 gen_set_condexec(dc);
6e256c93 9401 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 9402 dc->condjmp = 0;
9403 }
2c0262af 9404 }
2e70f6ef 9405
9ee6e8bb 9406done_generating:
2e70f6ef 9407 gen_icount_end(tb, num_insns);
2c0262af
FB		 9408 *gen_opc_ptr = INDEX_op_end;
9409
9410#ifdef DEBUG_DISAS
8fec2b8c 9411 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 9412 qemu_log("----------------\n");
9413 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7204ab88 9414 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
93fcfe39 9415 qemu_log("\n");
2c0262af
FB		 9416 }
9417#endif
b5ff1b31
FB		 9418 if (search_pc) {
9419 j = gen_opc_ptr - gen_opc_buf;
9420 lj++;
9421 while (lj <= j)
9422 gen_opc_instr_start[lj++] = 0;
b5ff1b31 9423 } else {
2c0262af 9424 tb->size = dc->pc - pc_start;
2e70f6ef 9425 tb->icount = num_insns;
b5ff1b31 9426 }
2c0262af
FB		 9427}
9428
2cfc5f17 9429void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2c0262af 9430{
2cfc5f17 9431 gen_intermediate_code_internal(env, tb, 0);
2c0262af
FB		 9432}
9433
2cfc5f17 9434void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2c0262af 9435{
2cfc5f17 9436 gen_intermediate_code_internal(env, tb, 1);
2c0262af
FB		 9437}
9438
b5ff1b31
FB		 9439static const char *cpu_mode_names[16] = {
9440 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9441 "???", "???", "???", "und", "???", "???", "???", "sys"
9442};
9ee6e8bb 9443
9a78eead 9444void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
7fe48483 9445 int flags)
2c0262af
FB		 9446{
9447 int i;
06e80fc9 9448#if 0
bc380d17 9449 union {
b7bcbe95
FB		 9450 uint32_t i;
9451 float s;
9452 } s0, s1;
9453 CPU_DoubleU d;
a94a6abf
PB		 9454 /* ??? This assumes float64 and double have the same layout.
9455 Oh well, it's only debug dumps. */
9456 union {
9457 float64 f64;
9458 double d;
9459 } d0;
06e80fc9 9460#endif
b5ff1b31 9461 uint32_t psr;
2c0262af
FB		 9462
9463 for(i=0;i<16;i++) {
7fe48483 9464 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 9465 if ((i % 4) == 3)
7fe48483 9466 cpu_fprintf(f, "\n");
2c0262af 9467 else
7fe48483 9468 cpu_fprintf(f, " ");
2c0262af 9469 }
b5ff1b31 9470 psr = cpsr_read(env);
687fa640
TS		 9471 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9472 psr,
b5ff1b31
FB		 9473 psr & (1 << 31) ? 'N' : '-',
9474 psr & (1 << 30) ? 'Z' : '-',
9475 psr & (1 << 29) ? 'C' : '-',
9476 psr & (1 << 28) ? 'V' : '-',
5fafdf24 9477 psr & CPSR_T ? 'T' : 'A',
b5ff1b31 9478 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95 9479
5e3f878a 9480#if 0
b7bcbe95 9481 for (i = 0; i < 16; i++) {
8e96005d
FB		 9482 d.d = env->vfp.regs[i];
9483 s0.i = d.l.lower;
9484 s1.i = d.l.upper;
a94a6abf
PB		 9485 d0.f64 = d.d;
9486 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
b7bcbe95 9487 i * 2, (int)s0.i, s0.s,
a94a6abf 9488 i * 2 + 1, (int)s1.i, s1.s,
b7bcbe95 9489 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
a94a6abf 9490 d0.d);
b7bcbe95 9491 }
40f137e1 9492 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
5e3f878a 9493#endif
2c0262af 9494}
a6b025d3 9495
d2856f1a
AJ		 9496void gen_pc_load(CPUState *env, TranslationBlock *tb,
9497 unsigned long searched_pc, int pc_pos, void *puc)
9498{
9499 env->regs[15] = gen_opc_pc[pc_pos];
e12ce78d 9500 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
d2856f1a 9501}
Qemu copy for testing