]> git.proxmox.com Git - qemu.git/blame - target-cris/cpu.h
Turn MMU off on reset
[qemu.git] / target-cris / cpu.h
CommitLineData
81fdc5f8
TS
1/*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
fad6cb1a 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
81fdc5f8
TS
20 */
21#ifndef CPU_CRIS_H
22#define CPU_CRIS_H
23
24#define TARGET_LONG_BITS 32
25
26#include "cpu-defs.h"
27
81fdc5f8
TS
28#define TARGET_HAS_ICE 1
29
30#define ELF_MACHINE EM_CRIS
31
1b1a38b0
EI
32#define EXCP_NMI 1
33#define EXCP_GURU 2
34#define EXCP_BUSFAULT 3
35#define EXCP_IRQ 4
36#define EXCP_BREAK 5
81fdc5f8 37
b41f7df0
EI
38/* Register aliases. R0 - R15 */
39#define R_FP 8
40#define R_SP 14
41#define R_ACR 15
42
43/* Support regs, P0 - P15 */
44#define PR_BZ 0
45#define PR_VR 1
46#define PR_PID 2
47#define PR_SRS 3
48#define PR_WZ 4
49#define PR_EXS 5
50#define PR_EDA 6
51#define PR_MOF 7
52#define PR_DZ 8
53#define PR_EBP 9
54#define PR_ERP 10
55#define PR_SRP 11
1b1a38b0 56#define PR_NRP 12
b41f7df0
EI
57#define PR_CCS 13
58#define PR_USP 14
59#define PR_SPC 15
60
81fdc5f8 61/* CPU flags. */
1b1a38b0
EI
62#define Q_FLAG 0x80000000
63#define M_FLAG 0x40000000
81fdc5f8
TS
64#define S_FLAG 0x200
65#define R_FLAG 0x100
66#define P_FLAG 0x80
67#define U_FLAG 0x40
68#define P_FLAG 0x80
69#define U_FLAG 0x40
70#define I_FLAG 0x20
71#define X_FLAG 0x10
72#define N_FLAG 0x08
73#define Z_FLAG 0x04
74#define V_FLAG 0x02
75#define C_FLAG 0x01
76#define ALU_FLAGS 0x1F
77
78/* Condition codes. */
79#define CC_CC 0
80#define CC_CS 1
81#define CC_NE 2
82#define CC_EQ 3
83#define CC_VC 4
84#define CC_VS 5
85#define CC_PL 6
86#define CC_MI 7
87#define CC_LS 8
88#define CC_HI 9
89#define CC_GE 10
90#define CC_LT 11
91#define CC_GT 12
92#define CC_LE 13
93#define CC_A 14
94#define CC_P 15
95
96/* Internal flags for the implementation. */
97#define F_DELAYSLOT 1
98
6ebbf390
JM
99#define NB_MMU_MODES 2
100
81fdc5f8 101typedef struct CPUCRISState {
81fdc5f8 102 uint32_t regs[16];
b41f7df0 103 /* P0 - P15 are referred to as special registers in the docs. */
81fdc5f8 104 uint32_t pregs[16];
b41f7df0
EI
105
106 /* Pseudo register for the PC. Not directly accessable on CRIS. */
81fdc5f8 107 uint32_t pc;
81fdc5f8 108
b41f7df0
EI
109 /* Pseudo register for the kernel stack. */
110 uint32_t ksp;
111
cf1d97f0
EI
112 /* Branch. */
113 int dslot;
81fdc5f8 114 int btaken;
cf1d97f0 115 uint32_t btarget;
81fdc5f8 116
81fdc5f8
TS
117 /* Condition flag tracking. */
118 uint32_t cc_op;
119 uint32_t cc_mask;
120 uint32_t cc_dest;
121 uint32_t cc_src;
122 uint32_t cc_result;
81fdc5f8
TS
123 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
124 int cc_size;
30abcfc7 125 /* X flag at the time of cc snapshot. */
81fdc5f8
TS
126 int cc_x;
127
786c02f1
EI
128 int interrupt_vector;
129 int fault_vector;
130 int trap_vector;
131
b41f7df0
EI
132 /* FIXME: add a check in the translator to avoid writing to support
133 register sets beyond the 4th. The ISA allows up to 256! but in
134 practice there is no core that implements more than 4.
135
136 Support function registers are used to control units close to the
137 core. Accesses do not pass down the normal hierarchy.
138 */
139 uint32_t sregs[4][16];
140
44cd42ee
EI
141 /* Linear feedback shift reg in the mmu. Used to provide pseudo
142 randomness for the 'hint' the mmu gives to sw for chosing valid
143 sets on TLB refills. */
144 uint32_t mmu_rand_lfsr;
145
b41f7df0
EI
146 /*
147 * We just store the stores to the tlbset here for later evaluation
148 * when the hw needs access to them.
149 *
150 * One for I and another for D.
151 */
152 struct
153 {
154 uint32_t hi;
155 uint32_t lo;
156 } tlbsets[2][4][16];
157
81fdc5f8
TS
158 CPU_COMMON
159} CPUCRISState;
160
aaed909a 161CPUCRISState *cpu_cris_init(const char *cpu_model);
81fdc5f8
TS
162int cpu_cris_exec(CPUCRISState *s);
163void cpu_cris_close(CPUCRISState *s);
164void do_interrupt(CPUCRISState *env);
165/* you can call this signal handler from your SIGBUS and SIGSEGV
166 signal handlers to inform the virtual CPU of exceptions. non zero
167 is returned if the signal was handled by the virtual CPU. */
168int cpu_cris_signal_handler(int host_signum, void *pinfo,
169 void *puc);
81fdc5f8
TS
170
171enum {
172 CC_OP_DYNAMIC, /* Use env->cc_op */
173 CC_OP_FLAGS,
81fdc5f8
TS
174 CC_OP_CMP,
175 CC_OP_MOVE,
81fdc5f8
TS
176 CC_OP_ADD,
177 CC_OP_ADDC,
178 CC_OP_MCP,
179 CC_OP_ADDU,
180 CC_OP_SUB,
181 CC_OP_SUBU,
182 CC_OP_NEG,
183 CC_OP_BTST,
184 CC_OP_MULS,
185 CC_OP_MULU,
186 CC_OP_DSTEP,
187 CC_OP_BOUND,
188
189 CC_OP_OR,
190 CC_OP_AND,
191 CC_OP_XOR,
192 CC_OP_LSL,
193 CC_OP_LSR,
194 CC_OP_ASR,
195 CC_OP_LZ
196};
197
81fdc5f8
TS
198/* CRIS uses 8k pages. */
199#define TARGET_PAGE_BITS 13
bb7ec043 200#define MMAP_SHIFT TARGET_PAGE_BITS
81fdc5f8
TS
201
202#define CPUState CPUCRISState
203#define cpu_init cpu_cris_init
204#define cpu_exec cpu_cris_exec
205#define cpu_gen_code cpu_cris_gen_code
206#define cpu_signal_handler cpu_cris_signal_handler
207
b3c7724c
PB
208#define CPU_SAVE_VERSION 1
209
6ebbf390
JM
210/* MMU modes definitions */
211#define MMU_MODE0_SUFFIX _kernel
212#define MMU_MODE1_SUFFIX _user
213#define MMU_USER_IDX 1
6ebbf390
JM
214static inline int cpu_mmu_index (CPUState *env)
215{
b41f7df0 216 return !!(env->pregs[PR_CCS] & U_FLAG);
6ebbf390
JM
217}
218
6e68e076
PB
219#if defined(CONFIG_USER_ONLY)
220static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
221{
f8ed7070 222 if (newsp)
6e68e076
PB
223 env->regs[14] = newsp;
224 env->regs[10] = 0;
225}
226#endif
227
ef96779b
EI
228static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
229{
230 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
231}
232
9004627f 233/* Support function regs. */
81fdc5f8 234#define SFR_RW_GC_CFG 0][0
b41f7df0
EI
235#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
236#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
237#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
238#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
239#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
240#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
241#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
81fdc5f8 242
b41f7df0 243#include "cpu-all.h"
622ed360
AL
244#include "exec-all.h"
245
246static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
247{
248 env->pc = tb->pc;
249}
250
6b917547
AL
251static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
252 target_ulong *cs_base, int *flags)
253{
254 *pc = env->pc;
255 *cs_base = 0;
256 *flags = env->dslot |
257 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG));
258}
259
81fdc5f8 260#endif