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81fdc5f8 TS |
1 | /* |
2 | * CRIS virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2007 AXIS Communications AB | |
5 | * Written by Edgar E. Iglesias | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | #ifndef CPU_CRIS_H | |
22 | #define CPU_CRIS_H | |
23 | ||
24 | #define TARGET_LONG_BITS 32 | |
25 | ||
26 | #include "cpu-defs.h" | |
27 | ||
28 | #include "softfloat.h" | |
29 | ||
30 | #define TARGET_HAS_ICE 1 | |
31 | ||
32 | #define ELF_MACHINE EM_CRIS | |
33 | ||
34 | #define EXCP_MMU_EXEC 0 | |
35 | #define EXCP_MMU_READ 1 | |
36 | #define EXCP_MMU_WRITE 2 | |
37 | #define EXCP_MMU_FLUSH 3 | |
786c02f1 | 38 | #define EXCP_MMU_FAULT 4 |
81fdc5f8 TS |
39 | #define EXCP_BREAK 16 /* trap. */ |
40 | ||
41 | /* CPU flags. */ | |
42 | #define S_FLAG 0x200 | |
43 | #define R_FLAG 0x100 | |
44 | #define P_FLAG 0x80 | |
45 | #define U_FLAG 0x40 | |
46 | #define P_FLAG 0x80 | |
47 | #define U_FLAG 0x40 | |
48 | #define I_FLAG 0x20 | |
49 | #define X_FLAG 0x10 | |
50 | #define N_FLAG 0x08 | |
51 | #define Z_FLAG 0x04 | |
52 | #define V_FLAG 0x02 | |
53 | #define C_FLAG 0x01 | |
54 | #define ALU_FLAGS 0x1F | |
55 | ||
56 | /* Condition codes. */ | |
57 | #define CC_CC 0 | |
58 | #define CC_CS 1 | |
59 | #define CC_NE 2 | |
60 | #define CC_EQ 3 | |
61 | #define CC_VC 4 | |
62 | #define CC_VS 5 | |
63 | #define CC_PL 6 | |
64 | #define CC_MI 7 | |
65 | #define CC_LS 8 | |
66 | #define CC_HI 9 | |
67 | #define CC_GE 10 | |
68 | #define CC_LT 11 | |
69 | #define CC_GT 12 | |
70 | #define CC_LE 13 | |
71 | #define CC_A 14 | |
72 | #define CC_P 15 | |
73 | ||
74 | /* Internal flags for the implementation. */ | |
75 | #define F_DELAYSLOT 1 | |
76 | ||
6ebbf390 JM |
77 | #define NB_MMU_MODES 2 |
78 | ||
81fdc5f8 TS |
79 | typedef struct CPUCRISState { |
80 | uint32_t debug1; | |
81 | uint32_t debug2; | |
82 | uint32_t debug3; | |
83 | ||
84 | /* | |
85 | * We just store the stores to the tlbset here for later evaluation | |
86 | * when the hw needs access to them. | |
87 | * | |
88 | * One for I and another for D. | |
89 | */ | |
90 | struct | |
91 | { | |
92 | uint32_t hi; | |
93 | uint32_t lo; | |
94 | } tlbsets[2][4][16]; | |
95 | ||
96 | uint32_t sregs[256][16]; /* grrr why so many?? */ | |
97 | uint32_t regs[16]; | |
98 | uint32_t pregs[16]; | |
99 | uint32_t pc; | |
81fdc5f8 TS |
100 | |
101 | /* These are setup up by the guest code just before transfering the | |
102 | control back to the host. */ | |
103 | int jmp; | |
104 | uint32_t btarget; | |
105 | int btaken; | |
106 | ||
81fdc5f8 TS |
107 | /* Condition flag tracking. */ |
108 | uint32_t cc_op; | |
109 | uint32_t cc_mask; | |
110 | uint32_t cc_dest; | |
111 | uint32_t cc_src; | |
112 | uint32_t cc_result; | |
113 | ||
114 | /* size of the operation, 1 = byte, 2 = word, 4 = dword. */ | |
115 | int cc_size; | |
116 | ||
117 | /* extended arithmetics. */ | |
118 | int cc_x_live; | |
119 | int cc_x; | |
120 | ||
121 | int features; | |
122 | ||
81fdc5f8 | 123 | int exception_index; |
786c02f1 EI |
124 | int interrupt_request; |
125 | int interrupt_vector; | |
126 | int fault_vector; | |
127 | int trap_vector; | |
128 | ||
81fdc5f8 TS |
129 | int user_mode_only; |
130 | int halted; | |
131 | ||
132 | struct | |
133 | { | |
134 | int exec_insns; | |
135 | int exec_loads; | |
136 | int exec_stores; | |
137 | } stats; | |
138 | ||
81fdc5f8 TS |
139 | jmp_buf jmp_env; |
140 | CPU_COMMON | |
141 | } CPUCRISState; | |
142 | ||
aaed909a | 143 | CPUCRISState *cpu_cris_init(const char *cpu_model); |
81fdc5f8 TS |
144 | int cpu_cris_exec(CPUCRISState *s); |
145 | void cpu_cris_close(CPUCRISState *s); | |
146 | void do_interrupt(CPUCRISState *env); | |
147 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
148 | signal handlers to inform the virtual CPU of exceptions. non zero | |
149 | is returned if the signal was handled by the virtual CPU. */ | |
150 | int cpu_cris_signal_handler(int host_signum, void *pinfo, | |
151 | void *puc); | |
152 | void cpu_cris_flush_flags(CPUCRISState *, int); | |
153 | ||
154 | ||
155 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, | |
156 | int is_asi); | |
157 | ||
158 | enum { | |
159 | CC_OP_DYNAMIC, /* Use env->cc_op */ | |
160 | CC_OP_FLAGS, | |
161 | CC_OP_LOGIC, | |
162 | CC_OP_CMP, | |
163 | CC_OP_MOVE, | |
164 | CC_OP_MOVE_PD, | |
165 | CC_OP_MOVE_SD, | |
166 | CC_OP_ADD, | |
167 | CC_OP_ADDC, | |
168 | CC_OP_MCP, | |
169 | CC_OP_ADDU, | |
170 | CC_OP_SUB, | |
171 | CC_OP_SUBU, | |
172 | CC_OP_NEG, | |
173 | CC_OP_BTST, | |
174 | CC_OP_MULS, | |
175 | CC_OP_MULU, | |
176 | CC_OP_DSTEP, | |
177 | CC_OP_BOUND, | |
178 | ||
179 | CC_OP_OR, | |
180 | CC_OP_AND, | |
181 | CC_OP_XOR, | |
182 | CC_OP_LSL, | |
183 | CC_OP_LSR, | |
184 | CC_OP_ASR, | |
185 | CC_OP_LZ | |
186 | }; | |
187 | ||
188 | #define CCF_C 0x01 | |
189 | #define CCF_V 0x02 | |
190 | #define CCF_Z 0x04 | |
191 | #define CCF_N 0x08 | |
192 | #define CCF_X 0x10 | |
193 | ||
194 | #define CRIS_SSP 0 | |
195 | #define CRIS_USP 1 | |
196 | ||
81fdc5f8 TS |
197 | void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector); |
198 | void cris_set_macsr(CPUCRISState *env, uint32_t val); | |
199 | void cris_switch_sp(CPUCRISState *env); | |
200 | ||
201 | void do_cris_semihosting(CPUCRISState *env, int nr); | |
202 | ||
203 | enum cris_features { | |
204 | CRIS_FEATURE_CF_ISA_MUL, | |
205 | }; | |
206 | ||
207 | static inline int cris_feature(CPUCRISState *env, int feature) | |
208 | { | |
209 | return (env->features & (1u << feature)) != 0; | |
210 | } | |
211 | ||
212 | void register_cris_insns (CPUCRISState *env); | |
213 | ||
214 | /* CRIS uses 8k pages. */ | |
215 | #define TARGET_PAGE_BITS 13 | |
216 | ||
217 | #define CPUState CPUCRISState | |
218 | #define cpu_init cpu_cris_init | |
219 | #define cpu_exec cpu_cris_exec | |
220 | #define cpu_gen_code cpu_cris_gen_code | |
221 | #define cpu_signal_handler cpu_cris_signal_handler | |
222 | ||
6ebbf390 JM |
223 | /* MMU modes definitions */ |
224 | #define MMU_MODE0_SUFFIX _kernel | |
225 | #define MMU_MODE1_SUFFIX _user | |
226 | #define MMU_USER_IDX 1 | |
227 | /* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ | |
228 | static inline int cpu_mmu_index (CPUState *env) | |
229 | { | |
230 | return 0; | |
231 | } | |
232 | ||
81fdc5f8 TS |
233 | #include "cpu-all.h" |
234 | ||
9004627f EI |
235 | /* Register aliases. R0 - R15 */ |
236 | #define R_FP 8 | |
237 | #define R_SP 14 | |
238 | #define R_ACR 15 | |
239 | ||
240 | /* Support regs, P0 - P15 */ | |
786c02f1 EI |
241 | #define PR_BZ 0 |
242 | #define PR_VR 1 | |
9004627f EI |
243 | #define PR_PID 2 |
244 | #define PR_SRS 3 | |
786c02f1 | 245 | #define PR_WZ 4 |
9004627f | 246 | #define PR_MOF 7 |
786c02f1 | 247 | #define PR_DZ 8 |
9004627f EI |
248 | #define PR_EBP 9 |
249 | #define PR_ERP 10 | |
250 | #define PR_SRP 11 | |
251 | #define PR_CCS 13 | |
252 | ||
253 | /* Support function regs. */ | |
81fdc5f8 | 254 | #define SFR_RW_GC_CFG 0][0 |
786c02f1 EI |
255 | #define SFR_RW_MM_CFG 2][0 |
256 | #define SFR_RW_MM_KBASE_LO 2][1 | |
257 | #define SFR_RW_MM_KBASE_HI 2][2 | |
258 | #define SFR_R_MM_CAUSE 2][3 | |
259 | #define SFR_RW_MM_TLB_SEL 2][4 | |
260 | #define SFR_RW_MM_TLB_LO 2][5 | |
261 | #define SFR_RW_MM_TLB_HI 2][6 | |
81fdc5f8 TS |
262 | |
263 | #endif |