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[qemu.git] / target-cris / helper.c
CommitLineData
81fdc5f8
TS
1/*
2 * CRIS helper routines.
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8
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19 */
20
21#include <stdio.h>
22#include <string.h>
23
24#include "config.h"
25#include "cpu.h"
26#include "mmu.h"
27#include "exec-all.h"
941db528 28#include "host-utils.h"
81fdc5f8 29
d12d51d5
AL
30
31//#define CRIS_HELPER_DEBUG
32
33
34#ifdef CRIS_HELPER_DEBUG
35#define D(x) x
93fcfe39 36#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5 37#else
e62b5b13 38#define D(x)
d12d51d5
AL
39#define D_LOG(...) do { } while (0)
40#endif
e62b5b13 41
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42#if defined(CONFIG_USER_ONLY)
43
44void do_interrupt (CPUState *env)
45{
bbaf29c7
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46 env->exception_index = -1;
47 env->pregs[PR_ERP] = env->pc;
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48}
49
50int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390 51 int mmu_idx, int is_softmmu)
81fdc5f8 52{
bbaf29c7 53 env->exception_index = 0xaa;
30abcfc7 54 env->pregs[PR_EDA] = address;
bbaf29c7 55 cpu_dump_state(env, stderr, fprintf, 0);
bbaf29c7 56 return 1;
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57}
58
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59#else /* !CONFIG_USER_ONLY */
60
e62b5b13
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61
62static void cris_shift_ccs(CPUState *env)
63{
64 uint32_t ccs;
65 /* Apply the ccs shift. */
66 ccs = env->pregs[PR_CCS];
b41f7df0 67 ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
e62b5b13
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68 env->pregs[PR_CCS] = ccs;
69}
70
81fdc5f8 71int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 72 int mmu_idx, int is_softmmu)
81fdc5f8 73{
2fa73ec8 74 struct cris_mmu_result res;
81fdc5f8 75 int prot, miss;
e62b5b13 76 int r = -1;
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77 target_ulong phy;
78
b41f7df0 79 D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
be9f2ded 80 miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
9f5a1fae 81 rw, mmu_idx, 0);
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TS
82 if (miss)
83 {
1b1a38b0 84 if (env->exception_index == EXCP_BUSFAULT)
7a977356 85 cpu_abort(env,
ef29a70d 86 "CRIS: Illegal recursive bus fault."
7a977356
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87 "addr=%x rw=%d\n",
88 address, rw);
ef29a70d 89
be9f2ded 90 env->pregs[PR_EDA] = address;
1b1a38b0 91 env->exception_index = EXCP_BUSFAULT;
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92 env->fault_vector = res.bf_vec;
93 r = 1;
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94 }
95 else
96 {
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97 /*
98 * Mask off the cache selection bit. The ETRAX busses do not
99 * see the top bit.
100 */
101 phy = res.phy & ~0x80000000;
b41f7df0 102 prot = res.prot;
d4c430a8 103 tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
58aebb94 104 prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8 105 r = 0;
81fdc5f8 106 }
b41f7df0 107 if (r > 0)
d12d51d5 108 D_LOG("%s returns %d irqreq=%x addr=%x"
cf1d97f0
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109 " phy=%x ismmu=%d vec=%x pc=%x\n",
110 __func__, r, env->interrupt_request,
d12d51d5 111 address, res.phy, is_softmmu, res.bf_vec, env->pc);
e62b5b13 112 return r;
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113}
114
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115static void do_interruptv10(CPUState *env)
116{
117 int ex_vec = -1;
118
119 D_LOG( "exception index=%d interrupt_req=%d\n",
120 env->exception_index,
121 env->interrupt_request);
122
123 assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
124 switch (env->exception_index)
125 {
126 case EXCP_BREAK:
127 /* These exceptions are genereated by the core itself.
128 ERP should point to the insn following the brk. */
129 ex_vec = env->trap_vector;
130 env->pregs[PR_ERP] = env->pc;
131 break;
132
133 case EXCP_NMI:
134 /* NMI is hardwired to vector zero. */
135 ex_vec = 0;
136 env->pregs[PR_CCS] &= ~M_FLAG;
137 env->pregs[PR_NRP] = env->pc;
138 break;
139
140 case EXCP_BUSFAULT:
43dc2a64 141 cpu_abort(env, "Unhandled busfault");
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142 break;
143
144 default:
145 /* The interrupt controller gives us the vector. */
146 ex_vec = env->interrupt_vector;
147 /* Normal interrupts are taken between
148 TB's. env->pc is valid here. */
149 env->pregs[PR_ERP] = env->pc;
150 break;
151 }
152
153 if (env->pregs[PR_CCS] & U_FLAG) {
154 /* Swap stack pointers. */
155 env->pregs[PR_USP] = env->regs[R_SP];
156 env->regs[R_SP] = env->ksp;
157 }
158
159 /* Now that we are in kernel mode, load the handlers address. */
160 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
161 env->locked_irq = 1;
162
163 qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
164 __func__, env->pc, ex_vec,
165 env->pregs[PR_CCS],
166 env->pregs[PR_PID],
167 env->pregs[PR_ERP]);
168}
169
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170void do_interrupt(CPUState *env)
171{
e62b5b13 172 int ex_vec = -1;
81fdc5f8 173
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174 if (env->pregs[PR_VR] < 32)
175 return do_interruptv10(env);
176
d12d51d5 177 D_LOG( "exception index=%d interrupt_req=%d\n",
b41f7df0 178 env->exception_index,
d12d51d5 179 env->interrupt_request);
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180
181 switch (env->exception_index)
182 {
183 case EXCP_BREAK:
e62b5b13
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184 /* These exceptions are genereated by the core itself.
185 ERP should point to the insn following the brk. */
186 ex_vec = env->trap_vector;
a1aebcb8 187 env->pregs[PR_ERP] = env->pc;
81fdc5f8 188 break;
e62b5b13 189
1b1a38b0
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190 case EXCP_NMI:
191 /* NMI is hardwired to vector zero. */
192 ex_vec = 0;
193 env->pregs[PR_CCS] &= ~M_FLAG;
194 env->pregs[PR_NRP] = env->pc;
195 break;
196
197 case EXCP_BUSFAULT:
e62b5b13 198 ex_vec = env->fault_vector;
b41f7df0 199 env->pregs[PR_ERP] = env->pc;
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200 break;
201
202 default:
1b1a38b0 203 /* The interrupt controller gives us the vector. */
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204 ex_vec = env->interrupt_vector;
205 /* Normal interrupts are taken between
206 TB's. env->pc is valid here. */
207 env->pregs[PR_ERP] = env->pc;
208 break;
209 }
210
cddffe37
EI
211 /* Fill in the IDX field. */
212 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
213
cf1d97f0 214 if (env->dslot) {
d12d51d5 215 D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
cf1d97f0
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216 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
217 ex_vec, env->pc, env->dslot,
ef29a70d 218 env->regs[R_SP],
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219 env->pregs[PR_ERP], env->pregs[PR_PID],
220 env->pregs[PR_CCS],
d12d51d5 221 env->cc_op, env->cc_mask);
cf1d97f0
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222 /* We loose the btarget, btaken state here so rexec the
223 branch. */
224 env->pregs[PR_ERP] -= env->dslot;
225 /* Exception starts with dslot cleared. */
226 env->dslot = 0;
81fdc5f8 227 }
b41f7df0 228
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229 if (env->pregs[PR_CCS] & U_FLAG) {
230 /* Swap stack pointers. */
231 env->pregs[PR_USP] = env->regs[R_SP];
232 env->regs[R_SP] = env->ksp;
233 }
234
235 /* Apply the CRIS CCS shift. Clears U if set. */
e62b5b13 236 cris_shift_ccs(env);
218951ef 237
abdfd950
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238 /* Now that we are in kernel mode, load the handlers address.
239 This load may not fault, real hw leaves that behaviour as
240 undefined. */
218951ef
EI
241 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
242
abdfd950
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243 /* Clear the excption_index to avoid spurios hw_aborts for recursive
244 bus faults. */
245 env->exception_index = -1;
246
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247 D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
248 __func__, env->pc, ex_vec,
b41f7df0
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249 env->pregs[PR_CCS],
250 env->pregs[PR_PID],
d12d51d5 251 env->pregs[PR_ERP]);
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TS
252}
253
c227f099 254target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
81fdc5f8 255{
81fdc5f8 256 uint32_t phy = addr;
2fa73ec8 257 struct cris_mmu_result res;
81fdc5f8 258 int miss;
3c4fe427 259
9f5a1fae 260 miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
3c4fe427
EI
261 /* If D TLB misses, try I TLB. */
262 if (miss) {
9f5a1fae 263 miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
3c4fe427
EI
264 }
265
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266 if (!miss)
267 phy = res.phy;
e62b5b13 268 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
81fdc5f8
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269 return phy;
270}
271#endif