[qemu.git] / target-cris / helper.c

/*
 *  CRIS helper routines.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <stdio.h>
#include <string.h>

#include "config.h"
#include "cpu.h"
#include "mmu.h"
#include "host-utils.h"


//#define CRIS_HELPER_DEBUG


#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
	env->exception_index = -1;
	env->pregs[PR_ERP] = env->pc;
}

int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
                             int mmu_idx, int is_softmmu)
{
	env->exception_index = 0xaa;
	env->pregs[PR_EDA] = address;
	cpu_dump_state(env, stderr, fprintf, 0);
	return 1;
}

#else /* !CONFIG_USER_ONLY */


static void cris_shift_ccs(CPUState *env)
{
	uint32_t ccs;
	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
	env->pregs[PR_CCS] = ccs;
}

int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu)
{
	struct cris_mmu_result res;
	int prot, miss;
	int r = -1;
	target_ulong phy;

	D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
	miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
				  rw, mmu_idx, 0);
	if (miss)
	{
		if (env->exception_index == EXCP_BUSFAULT)
			cpu_abort(env,
				  "CRIS: Illegal recursive bus fault."
				 "addr=%x rw=%d\n",
				 address, rw);

		env->pregs[PR_EDA] = address;
		env->exception_index = EXCP_BUSFAULT;
		env->fault_vector = res.bf_vec;
		r = 1;
	}
	else
	{
		/*
		 * Mask off the cache selection bit. The ETRAX busses do not
		 * see the top bit.
		 */
		phy = res.phy & ~0x80000000;
		prot = res.prot;
		tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
                             prot, mmu_idx, TARGET_PAGE_SIZE);
                r = 0;
	}
	if (r > 0)
		D_LOG("%s returns %d irqreq=%x addr=%x"
			  " phy=%x ismmu=%d vec=%x pc=%x\n", 
			  __func__, r, env->interrupt_request, 
			  address, res.phy, is_softmmu, res.bf_vec, env->pc);
	return r;
}

static void do_interruptv10(CPUState *env)
{
	int ex_vec = -1;

	D_LOG( "exception index=%d interrupt_req=%d\n",
		   env->exception_index,
		   env->interrupt_request);

	assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
	switch (env->exception_index)
	{
		case EXCP_BREAK:
			/* These exceptions are genereated by the core itself.
			   ERP should point to the insn following the brk.  */
			ex_vec = env->trap_vector;
			env->pregs[PR_ERP] = env->pc;
			break;

		case EXCP_NMI:
			/* NMI is hardwired to vector zero.  */
			ex_vec = 0;
			env->pregs[PR_CCS] &= ~M_FLAG;
			env->pregs[PR_NRP] = env->pc;
			break;

		case EXCP_BUSFAULT:
                        cpu_abort(env, "Unhandled busfault");
			break;

		default:
			/* The interrupt controller gives us the vector.  */
			ex_vec = env->interrupt_vector;
			/* Normal interrupts are taken between
			   TB's.  env->pc is valid here.  */
			env->pregs[PR_ERP] = env->pc;
			break;
	}

	if (env->pregs[PR_CCS] & U_FLAG) {
		/* Swap stack pointers.  */
		env->pregs[PR_USP] = env->regs[R_SP];
		env->regs[R_SP] = env->ksp;
	}

	/* Now that we are in kernel mode, load the handlers address.  */
	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
	env->locked_irq = 1;

	qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 
		      __func__, env->pc, ex_vec, 
		      env->pregs[PR_CCS],
		      env->pregs[PR_PID], 
		      env->pregs[PR_ERP]);
}

void do_interrupt(CPUState *env)
{
	int ex_vec = -1;

	if (env->pregs[PR_VR] < 32)
		return do_interruptv10(env);

	D_LOG( "exception index=%d interrupt_req=%d\n",
		   env->exception_index,
		   env->interrupt_request);

	switch (env->exception_index)
	{
		case EXCP_BREAK:
			/* These exceptions are genereated by the core itself.
			   ERP should point to the insn following the brk.  */
			ex_vec = env->trap_vector;
			env->pregs[PR_ERP] = env->pc;
			break;

		case EXCP_NMI:
			/* NMI is hardwired to vector zero.  */
			ex_vec = 0;
			env->pregs[PR_CCS] &= ~M_FLAG;
			env->pregs[PR_NRP] = env->pc;
			break;

		case EXCP_BUSFAULT:
			ex_vec = env->fault_vector;
			env->pregs[PR_ERP] = env->pc;
			break;

		default:
			/* The interrupt controller gives us the vector.  */
			ex_vec = env->interrupt_vector;
			/* Normal interrupts are taken between
			   TB's.  env->pc is valid here.  */
			env->pregs[PR_ERP] = env->pc;
			break;
	}

	/* Fill in the IDX field.  */
	env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;

	if (env->dslot) {
		D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
			  " ERP=%x pid=%x ccs=%x cc=%d %x\n",
			  ex_vec, env->pc, env->dslot,
			  env->regs[R_SP],
			  env->pregs[PR_ERP], env->pregs[PR_PID],
			  env->pregs[PR_CCS],
			  env->cc_op, env->cc_mask);
		/* We loose the btarget, btaken state here so rexec the
		   branch.  */
		env->pregs[PR_ERP] -= env->dslot;
		/* Exception starts with dslot cleared.  */
		env->dslot = 0;
	}
	
	if (env->pregs[PR_CCS] & U_FLAG) {
		/* Swap stack pointers.  */
		env->pregs[PR_USP] = env->regs[R_SP];
		env->regs[R_SP] = env->ksp;
	}

	/* Apply the CRIS CCS shift. Clears U if set.  */
	cris_shift_ccs(env);

	/* Now that we are in kernel mode, load the handlers address.
	   This load may not fault, real hw leaves that behaviour as
	   undefined.  */
	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);

	/* Clear the excption_index to avoid spurios hw_aborts for recursive
	   bus faults.  */
	env->exception_index = -1;

	D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
		   __func__, env->pc, ex_vec,
		   env->pregs[PR_CCS],
		   env->pregs[PR_PID], 
		   env->pregs[PR_ERP]);
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
	uint32_t phy = addr;
	struct cris_mmu_result res;
	int miss;

	miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
	/* If D TLB misses, try I TLB.  */
	if (miss) {
		miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
	}

	if (!miss)
		phy = res.phy;
	D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
	return phy;
}
#endif
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
	20
	21	#include <stdio.h>
	22	#include <string.h>
	23
	24	#include "config.h"
	25	#include "cpu.h"
	26	#include "mmu.h"
941db528	27	#include "host-utils.h"
81fdc5f8	28
d12d51d5 AL	29
	30	//#define CRIS_HELPER_DEBUG
	31
	32
	33	#ifdef CRIS_HELPER_DEBUG
	34	#define D(x) x
93fcfe39	35	#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5	36	#else
e62b5b13	37	#define D(x)
d12d51d5 AL	38	#define D_LOG(...) do { } while (0)
d12d51d5 AL	39	#endif
e62b5b13	40
81fdc5f8 TS	41	#if defined(CONFIG_USER_ONLY)
	42
	43	void do_interrupt (CPUState *env)
	44	{
bbaf29c7 EI	45	env->exception_index = -1;
bbaf29c7 EI	46	env->pregs[PR_ERP] = env->pc;
81fdc5f8 TS	47	}
	48
	49	int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390	50	int mmu_idx, int is_softmmu)
81fdc5f8	51	{
bbaf29c7	52	env->exception_index = 0xaa;
30abcfc7	53	env->pregs[PR_EDA] = address;
bbaf29c7	54	cpu_dump_state(env, stderr, fprintf, 0);
bbaf29c7	55	return 1;
81fdc5f8 TS	56	}
81fdc5f8 TS	57
81fdc5f8 TS	58	#else /* !CONFIG_USER_ONLY */
81fdc5f8 TS	59
e62b5b13 EI	60
	61	static void cris_shift_ccs(CPUState *env)
	62	{
	63	uint32_t ccs;
	64	/* Apply the ccs shift. */
	65	ccs = env->pregs[PR_CCS];
b41f7df0	66	ccs = ((ccs & 0xc0000000) \| ((ccs << 12) >> 2)) & ~0x3ff;
e62b5b13 EI	67	env->pregs[PR_CCS] = ccs;
	68	}
	69
81fdc5f8	70	int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390	71	int mmu_idx, int is_softmmu)
81fdc5f8	72	{
2fa73ec8	73	struct cris_mmu_result res;
81fdc5f8	74	int prot, miss;
e62b5b13	75	int r = -1;
81fdc5f8 TS	76	target_ulong phy;
81fdc5f8 TS	77
b41f7df0	78	D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
be9f2ded	79	miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
9f5a1fae	80	rw, mmu_idx, 0);
81fdc5f8 TS	81	if (miss)
81fdc5f8 TS	82	{
1b1a38b0	83	if (env->exception_index == EXCP_BUSFAULT)
7a977356	84	cpu_abort(env,
ef29a70d	85	"CRIS: Illegal recursive bus fault."
7a977356 EI	86	"addr=%x rw=%d\n",
7a977356 EI	87	address, rw);
ef29a70d	88
be9f2ded	89	env->pregs[PR_EDA] = address;
1b1a38b0	90	env->exception_index = EXCP_BUSFAULT;
e62b5b13 EI	91	env->fault_vector = res.bf_vec;
e62b5b13 EI	92	r = 1;
81fdc5f8 TS	93	}
	94	else
	95	{
980f8a0b EI	96	/*
	97	* Mask off the cache selection bit. The ETRAX busses do not
	98	* see the top bit.
	99	*/
	100	phy = res.phy & ~0x80000000;
b41f7df0	101	prot = res.prot;
d4c430a8	102	tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
58aebb94	103	prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8	104	r = 0;
81fdc5f8	105	}
b41f7df0	106	if (r > 0)
d12d51d5	107	D_LOG("%s returns %d irqreq=%x addr=%x"
cf1d97f0 EI	108	" phy=%x ismmu=%d vec=%x pc=%x\n",
cf1d97f0 EI	109	__func__, r, env->interrupt_request,
d12d51d5	110	address, res.phy, is_softmmu, res.bf_vec, env->pc);
e62b5b13	111	return r;
81fdc5f8 TS	112	}
81fdc5f8 TS	113
7a977356 EI	114	static void do_interruptv10(CPUState *env)
	115	{
	116	int ex_vec = -1;
	117
	118	D_LOG( "exception index=%d interrupt_req=%d\n",
	119	env->exception_index,
	120	env->interrupt_request);
	121
	122	assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
	123	switch (env->exception_index)
	124	{
	125	case EXCP_BREAK:
	126	/* These exceptions are genereated by the core itself.
	127	ERP should point to the insn following the brk. */
	128	ex_vec = env->trap_vector;
	129	env->pregs[PR_ERP] = env->pc;
	130	break;
	131
	132	case EXCP_NMI:
	133	/* NMI is hardwired to vector zero. */
	134	ex_vec = 0;
	135	env->pregs[PR_CCS] &= ~M_FLAG;
	136	env->pregs[PR_NRP] = env->pc;
	137	break;
	138
	139	case EXCP_BUSFAULT:
43dc2a64	140	cpu_abort(env, "Unhandled busfault");
7a977356 EI	141	break;
	142
	143	default:
	144	/* The interrupt controller gives us the vector. */
	145	ex_vec = env->interrupt_vector;
	146	/* Normal interrupts are taken between
	147	TB's. env->pc is valid here. */
	148	env->pregs[PR_ERP] = env->pc;
	149	break;
	150	}
	151
	152	if (env->pregs[PR_CCS] & U_FLAG) {
	153	/* Swap stack pointers. */
	154	env->pregs[PR_USP] = env->regs[R_SP];
	155	env->regs[R_SP] = env->ksp;
	156	}
	157
	158	/* Now that we are in kernel mode, load the handlers address. */
	159	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
	160	env->locked_irq = 1;
	161
	162	qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
	163	__func__, env->pc, ex_vec,
	164	env->pregs[PR_CCS],
	165	env->pregs[PR_PID],
	166	env->pregs[PR_ERP]);
	167	}
	168
81fdc5f8 TS	169	void do_interrupt(CPUState *env)
81fdc5f8 TS	170	{
e62b5b13	171	int ex_vec = -1;
81fdc5f8	172
7a977356 EI	173	if (env->pregs[PR_VR] < 32)
	174	return do_interruptv10(env);
	175
d12d51d5	176	D_LOG( "exception index=%d interrupt_req=%d\n",
b41f7df0	177	env->exception_index,
d12d51d5	178	env->interrupt_request);
81fdc5f8 TS	179
	180	switch (env->exception_index)
	181	{
	182	case EXCP_BREAK:
e62b5b13 EI	183	/* These exceptions are genereated by the core itself.
	184	ERP should point to the insn following the brk. */
	185	ex_vec = env->trap_vector;
a1aebcb8	186	env->pregs[PR_ERP] = env->pc;
81fdc5f8	187	break;
e62b5b13	188
1b1a38b0 EI	189	case EXCP_NMI:
	190	/* NMI is hardwired to vector zero. */
	191	ex_vec = 0;
	192	env->pregs[PR_CCS] &= ~M_FLAG;
	193	env->pregs[PR_NRP] = env->pc;
	194	break;
	195
	196	case EXCP_BUSFAULT:
e62b5b13	197	ex_vec = env->fault_vector;
b41f7df0	198	env->pregs[PR_ERP] = env->pc;
81fdc5f8 TS	199	break;
	200
	201	default:
1b1a38b0	202	/* The interrupt controller gives us the vector. */
b41f7df0 EI	203	ex_vec = env->interrupt_vector;
	204	/* Normal interrupts are taken between
	205	TB's. env->pc is valid here. */
	206	env->pregs[PR_ERP] = env->pc;
	207	break;
	208	}
	209
cddffe37 EI	210	/* Fill in the IDX field. */
	211	env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
	212
cf1d97f0	213	if (env->dslot) {
d12d51d5	214	D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
cf1d97f0 EI	215	" ERP=%x pid=%x ccs=%x cc=%d %x\n",
cf1d97f0 EI	216	ex_vec, env->pc, env->dslot,
ef29a70d	217	env->regs[R_SP],
b41f7df0 EI	218	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	219	env->pregs[PR_CCS],
d12d51d5	220	env->cc_op, env->cc_mask);
cf1d97f0 EI	221	/* We loose the btarget, btaken state here so rexec the
	222	branch. */
	223	env->pregs[PR_ERP] -= env->dslot;
	224	/* Exception starts with dslot cleared. */
	225	env->dslot = 0;
81fdc5f8	226	}
b41f7df0	227
b41f7df0 EI	228	if (env->pregs[PR_CCS] & U_FLAG) {
	229	/* Swap stack pointers. */
	230	env->pregs[PR_USP] = env->regs[R_SP];
	231	env->regs[R_SP] = env->ksp;
	232	}
	233
	234	/* Apply the CRIS CCS shift. Clears U if set. */
e62b5b13	235	cris_shift_ccs(env);
218951ef	236
abdfd950 EI	237	/* Now that we are in kernel mode, load the handlers address.
	238	This load may not fault, real hw leaves that behaviour as
	239	undefined. */
218951ef EI	240	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
218951ef EI	241
abdfd950 EI	242	/* Clear the excption_index to avoid spurios hw_aborts for recursive
	243	bus faults. */
	244	env->exception_index = -1;
	245
7a977356 EI	246	D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
7a977356 EI	247	__func__, env->pc, ex_vec,
b41f7df0 EI	248	env->pregs[PR_CCS],
b41f7df0 EI	249	env->pregs[PR_PID],
d12d51d5	250	env->pregs[PR_ERP]);
81fdc5f8 TS	251	}
81fdc5f8 TS	252
c227f099	253	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
81fdc5f8	254	{
81fdc5f8	255	uint32_t phy = addr;
2fa73ec8	256	struct cris_mmu_result res;
81fdc5f8	257	int miss;
3c4fe427	258
9f5a1fae	259	miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
3c4fe427 EI	260	/* If D TLB misses, try I TLB. */
3c4fe427 EI	261	if (miss) {
9f5a1fae	262	miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
3c4fe427 EI	263	}
3c4fe427 EI	264
81fdc5f8 TS	265	if (!miss)
81fdc5f8 TS	266	phy = res.phy;
e62b5b13	267	D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
81fdc5f8 TS	268	return phy;
	269	}
	270	#endif