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81fdc5f8 TS |
1 | /* |
2 | * CRIS helper routines. | |
3 | * | |
4 | * Copyright (c) 2007 AXIS Communications AB | |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | ||
25 | #include "config.h" | |
26 | #include "cpu.h" | |
27 | #include "mmu.h" | |
28 | #include "exec-all.h" | |
941db528 | 29 | #include "host-utils.h" |
81fdc5f8 | 30 | |
e62b5b13 EI |
31 | #define D(x) |
32 | ||
81fdc5f8 TS |
33 | #if defined(CONFIG_USER_ONLY) |
34 | ||
35 | void do_interrupt (CPUState *env) | |
36 | { | |
bbaf29c7 EI |
37 | env->exception_index = -1; |
38 | env->pregs[PR_ERP] = env->pc; | |
81fdc5f8 TS |
39 | } |
40 | ||
41 | int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, | |
6ebbf390 | 42 | int mmu_idx, int is_softmmu) |
81fdc5f8 | 43 | { |
bbaf29c7 | 44 | env->exception_index = 0xaa; |
30abcfc7 | 45 | env->pregs[PR_EDA] = address; |
bbaf29c7 | 46 | cpu_dump_state(env, stderr, fprintf, 0); |
bbaf29c7 | 47 | return 1; |
81fdc5f8 TS |
48 | } |
49 | ||
50 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) | |
51 | { | |
bbaf29c7 | 52 | return addr; |
81fdc5f8 TS |
53 | } |
54 | ||
55 | #else /* !CONFIG_USER_ONLY */ | |
56 | ||
e62b5b13 EI |
57 | |
58 | static void cris_shift_ccs(CPUState *env) | |
59 | { | |
60 | uint32_t ccs; | |
61 | /* Apply the ccs shift. */ | |
62 | ccs = env->pregs[PR_CCS]; | |
b41f7df0 | 63 | ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff; |
e62b5b13 EI |
64 | env->pregs[PR_CCS] = ccs; |
65 | } | |
66 | ||
81fdc5f8 | 67 | int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 68 | int mmu_idx, int is_softmmu) |
81fdc5f8 TS |
69 | { |
70 | struct cris_mmu_result_t res; | |
71 | int prot, miss; | |
e62b5b13 | 72 | int r = -1; |
81fdc5f8 TS |
73 | target_ulong phy; |
74 | ||
b41f7df0 | 75 | D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw)); |
81fdc5f8 | 76 | address &= TARGET_PAGE_MASK; |
6ebbf390 | 77 | miss = cris_mmu_translate(&res, env, address, rw, mmu_idx); |
81fdc5f8 TS |
78 | if (miss) |
79 | { | |
1b1a38b0 | 80 | if (env->exception_index == EXCP_BUSFAULT) |
ef29a70d EI |
81 | cpu_abort(env, |
82 | "CRIS: Illegal recursive bus fault." | |
83 | "addr=%x rw=%d\n", | |
84 | address, rw); | |
85 | ||
1b1a38b0 | 86 | env->exception_index = EXCP_BUSFAULT; |
e62b5b13 EI |
87 | env->fault_vector = res.bf_vec; |
88 | r = 1; | |
81fdc5f8 TS |
89 | } |
90 | else | |
91 | { | |
92 | phy = res.phy; | |
b41f7df0 | 93 | prot = res.prot; |
e62b5b13 | 94 | r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); |
81fdc5f8 | 95 | } |
b41f7df0 | 96 | if (r > 0) |
cf1d97f0 EI |
97 | D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x" |
98 | " phy=%x ismmu=%d vec=%x pc=%x\n", | |
99 | __func__, r, env->interrupt_request, | |
100 | address, res.phy, is_softmmu, res.bf_vec, env->pc)); | |
e62b5b13 | 101 | return r; |
81fdc5f8 TS |
102 | } |
103 | ||
104 | void do_interrupt(CPUState *env) | |
105 | { | |
e62b5b13 | 106 | int ex_vec = -1; |
81fdc5f8 | 107 | |
ef29a70d | 108 | D(fprintf (logfile, "exception index=%d interrupt_req=%d\n", |
b41f7df0 EI |
109 | env->exception_index, |
110 | env->interrupt_request)); | |
81fdc5f8 TS |
111 | |
112 | switch (env->exception_index) | |
113 | { | |
114 | case EXCP_BREAK: | |
e62b5b13 EI |
115 | /* These exceptions are genereated by the core itself. |
116 | ERP should point to the insn following the brk. */ | |
117 | ex_vec = env->trap_vector; | |
9004627f | 118 | env->pregs[PR_ERP] = env->pc + 2; |
81fdc5f8 | 119 | break; |
e62b5b13 | 120 | |
1b1a38b0 EI |
121 | case EXCP_NMI: |
122 | /* NMI is hardwired to vector zero. */ | |
123 | ex_vec = 0; | |
124 | env->pregs[PR_CCS] &= ~M_FLAG; | |
125 | env->pregs[PR_NRP] = env->pc; | |
126 | break; | |
127 | ||
128 | case EXCP_BUSFAULT: | |
e62b5b13 | 129 | ex_vec = env->fault_vector; |
b41f7df0 | 130 | env->pregs[PR_ERP] = env->pc; |
81fdc5f8 TS |
131 | break; |
132 | ||
133 | default: | |
1b1a38b0 | 134 | /* The interrupt controller gives us the vector. */ |
b41f7df0 EI |
135 | ex_vec = env->interrupt_vector; |
136 | /* Normal interrupts are taken between | |
137 | TB's. env->pc is valid here. */ | |
138 | env->pregs[PR_ERP] = env->pc; | |
139 | break; | |
140 | } | |
141 | ||
cf1d97f0 EI |
142 | if (env->dslot) { |
143 | D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x" | |
144 | " ERP=%x pid=%x ccs=%x cc=%d %x\n", | |
145 | ex_vec, env->pc, env->dslot, | |
ef29a70d | 146 | env->regs[R_SP], |
b41f7df0 EI |
147 | env->pregs[PR_ERP], env->pregs[PR_PID], |
148 | env->pregs[PR_CCS], | |
149 | env->cc_op, env->cc_mask)); | |
cf1d97f0 EI |
150 | /* We loose the btarget, btaken state here so rexec the |
151 | branch. */ | |
152 | env->pregs[PR_ERP] -= env->dslot; | |
153 | /* Exception starts with dslot cleared. */ | |
154 | env->dslot = 0; | |
81fdc5f8 | 155 | } |
b41f7df0 | 156 | |
e62b5b13 | 157 | env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); |
b41f7df0 EI |
158 | |
159 | if (env->pregs[PR_CCS] & U_FLAG) { | |
160 | /* Swap stack pointers. */ | |
161 | env->pregs[PR_USP] = env->regs[R_SP]; | |
162 | env->regs[R_SP] = env->ksp; | |
163 | } | |
164 | ||
165 | /* Apply the CRIS CCS shift. Clears U if set. */ | |
e62b5b13 | 166 | cris_shift_ccs(env); |
b41f7df0 EI |
167 | D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", |
168 | __func__, env->pc, ex_vec, | |
169 | env->pregs[PR_CCS], | |
170 | env->pregs[PR_PID], | |
171 | env->pregs[PR_ERP])); | |
81fdc5f8 TS |
172 | } |
173 | ||
174 | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) | |
175 | { | |
81fdc5f8 TS |
176 | uint32_t phy = addr; |
177 | struct cris_mmu_result_t res; | |
178 | int miss; | |
179 | miss = cris_mmu_translate(&res, env, addr, 0, 0); | |
180 | if (!miss) | |
181 | phy = res.phy; | |
e62b5b13 | 182 | D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); |
81fdc5f8 TS |
183 | return phy; |
184 | } | |
185 | #endif |