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[qemu.git] / target-cris / helper.c
CommitLineData
81fdc5f8
TS
1/*
2 * CRIS helper routines.
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
fad6cb1a 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
81fdc5f8
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20 */
21
22#include <stdio.h>
23#include <string.h>
24
25#include "config.h"
26#include "cpu.h"
27#include "mmu.h"
28#include "exec-all.h"
941db528 29#include "host-utils.h"
81fdc5f8 30
d12d51d5
AL
31
32//#define CRIS_HELPER_DEBUG
33
34
35#ifdef CRIS_HELPER_DEBUG
36#define D(x) x
93fcfe39 37#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5 38#else
e62b5b13 39#define D(x)
d12d51d5
AL
40#define D_LOG(...) do { } while (0)
41#endif
e62b5b13 42
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43#if defined(CONFIG_USER_ONLY)
44
45void do_interrupt (CPUState *env)
46{
bbaf29c7
EI
47 env->exception_index = -1;
48 env->pregs[PR_ERP] = env->pc;
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49}
50
51int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
6ebbf390 52 int mmu_idx, int is_softmmu)
81fdc5f8 53{
bbaf29c7 54 env->exception_index = 0xaa;
30abcfc7 55 env->pregs[PR_EDA] = address;
bbaf29c7 56 cpu_dump_state(env, stderr, fprintf, 0);
bbaf29c7 57 return 1;
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58}
59
60target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
61{
bbaf29c7 62 return addr;
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63}
64
65#else /* !CONFIG_USER_ONLY */
66
e62b5b13
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67
68static void cris_shift_ccs(CPUState *env)
69{
70 uint32_t ccs;
71 /* Apply the ccs shift. */
72 ccs = env->pregs[PR_CCS];
b41f7df0 73 ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
e62b5b13
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74 env->pregs[PR_CCS] = ccs;
75}
76
81fdc5f8 77int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 78 int mmu_idx, int is_softmmu)
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79{
80 struct cris_mmu_result_t res;
81 int prot, miss;
e62b5b13 82 int r = -1;
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83 target_ulong phy;
84
b41f7df0 85 D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
81fdc5f8 86 address &= TARGET_PAGE_MASK;
6ebbf390 87 miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
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88 if (miss)
89 {
1b1a38b0 90 if (env->exception_index == EXCP_BUSFAULT)
ef29a70d
EI
91 cpu_abort(env,
92 "CRIS: Illegal recursive bus fault."
93 "addr=%x rw=%d\n",
94 address, rw);
95
1b1a38b0 96 env->exception_index = EXCP_BUSFAULT;
e62b5b13
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97 env->fault_vector = res.bf_vec;
98 r = 1;
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99 }
100 else
101 {
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102 /*
103 * Mask off the cache selection bit. The ETRAX busses do not
104 * see the top bit.
105 */
106 phy = res.phy & ~0x80000000;
b41f7df0 107 prot = res.prot;
e62b5b13 108 r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
81fdc5f8 109 }
b41f7df0 110 if (r > 0)
d12d51d5 111 D_LOG("%s returns %d irqreq=%x addr=%x"
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112 " phy=%x ismmu=%d vec=%x pc=%x\n",
113 __func__, r, env->interrupt_request,
d12d51d5 114 address, res.phy, is_softmmu, res.bf_vec, env->pc);
e62b5b13 115 return r;
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116}
117
118void do_interrupt(CPUState *env)
119{
e62b5b13 120 int ex_vec = -1;
81fdc5f8 121
d12d51d5 122 D_LOG( "exception index=%d interrupt_req=%d\n",
b41f7df0 123 env->exception_index,
d12d51d5 124 env->interrupt_request);
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125
126 switch (env->exception_index)
127 {
128 case EXCP_BREAK:
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129 /* These exceptions are genereated by the core itself.
130 ERP should point to the insn following the brk. */
131 ex_vec = env->trap_vector;
a1aebcb8 132 env->pregs[PR_ERP] = env->pc;
81fdc5f8 133 break;
e62b5b13 134
1b1a38b0
EI
135 case EXCP_NMI:
136 /* NMI is hardwired to vector zero. */
137 ex_vec = 0;
138 env->pregs[PR_CCS] &= ~M_FLAG;
139 env->pregs[PR_NRP] = env->pc;
140 break;
141
142 case EXCP_BUSFAULT:
e62b5b13 143 ex_vec = env->fault_vector;
b41f7df0 144 env->pregs[PR_ERP] = env->pc;
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145 break;
146
147 default:
1b1a38b0 148 /* The interrupt controller gives us the vector. */
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149 ex_vec = env->interrupt_vector;
150 /* Normal interrupts are taken between
151 TB's. env->pc is valid here. */
152 env->pregs[PR_ERP] = env->pc;
153 break;
154 }
155
cddffe37
EI
156 /* Fill in the IDX field. */
157 env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
158
cf1d97f0 159 if (env->dslot) {
d12d51d5 160 D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
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161 " ERP=%x pid=%x ccs=%x cc=%d %x\n",
162 ex_vec, env->pc, env->dslot,
ef29a70d 163 env->regs[R_SP],
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164 env->pregs[PR_ERP], env->pregs[PR_PID],
165 env->pregs[PR_CCS],
d12d51d5 166 env->cc_op, env->cc_mask);
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167 /* We loose the btarget, btaken state here so rexec the
168 branch. */
169 env->pregs[PR_ERP] -= env->dslot;
170 /* Exception starts with dslot cleared. */
171 env->dslot = 0;
81fdc5f8 172 }
b41f7df0 173
e62b5b13 174 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
b41f7df0
EI
175
176 if (env->pregs[PR_CCS] & U_FLAG) {
177 /* Swap stack pointers. */
178 env->pregs[PR_USP] = env->regs[R_SP];
179 env->regs[R_SP] = env->ksp;
180 }
181
182 /* Apply the CRIS CCS shift. Clears U if set. */
e62b5b13 183 cris_shift_ccs(env);
d12d51d5 184 D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
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EI
185 __func__, env->pc, ex_vec,
186 env->pregs[PR_CCS],
187 env->pregs[PR_PID],
d12d51d5 188 env->pregs[PR_ERP]);
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189}
190
191target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
192{
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193 uint32_t phy = addr;
194 struct cris_mmu_result_t res;
195 int miss;
196 miss = cris_mmu_translate(&res, env, addr, 0, 0);
197 if (!miss)
198 phy = res.phy;
e62b5b13 199 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
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TS
200 return phy;
201}
202#endif