[qemu.git] / target-cris / mmu.c

/*
 *  CRIS mmu emulation.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
 */

#ifndef CONFIG_USER_ONLY

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "config.h"
#include "cpu.h"
#include "mmu.h"
#include "exec-all.h"

#ifdef DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

void cris_mmu_init(CPUState *env)
{
	env->mmu_rand_lfsr = 0xcccc;
}

#define SR_POLYNOM 0x8805
static inline unsigned int compute_polynom(unsigned int sr)
{
	unsigned int i;
	unsigned int f;

	f = 0;
	for (i = 0; i < 16; i++)
		f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);

	return f;
}

static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
	return (rw_gc_cfg & 12) != 0;
}

static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
	return (1 << seg) & rw_mm_cfg;
}

static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
{
	uint32_t base;
	int i;

	if (seg < 8)
		base = env->sregs[SFR_RW_MM_KBASE_LO];
	else
		base = env->sregs[SFR_RW_MM_KBASE_HI];

	i = seg & 7;
	base >>= i * 4;
	base &= 15;

	base <<= 28;
	return base;
}
/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

static inline void set_field(uint32_t *dst, unsigned int val, 
			     unsigned int offset, unsigned int width)
{
	uint32_t mask;

	mask = (1 << width) - 1;
	mask <<= offset;
	val <<= offset;

	val &= mask;
	*dst &= ~(mask);
	*dst |= val;
}

#ifdef DEBUG
static void dump_tlb(CPUState *env, int mmu)
{
	int set;
	int idx;
	uint32_t hi, lo, tlb_vpn, tlb_pfn;

	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
}
#endif

/* rw 0 = read, 1 = write, 2 = exec.  */
static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
				   CPUState *env, uint32_t vaddr,
				   int rw, int usermode)
{
	unsigned int vpage;
	unsigned int idx;
	uint32_t pid, lo, hi;
	uint32_t tlb_vpn, tlb_pfn = 0;
	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	int cfg_v, cfg_k, cfg_w, cfg_x;	
	int set, match = 0;
	uint32_t r_cause;
	uint32_t r_cfg;
	int rwcause;
	int mmu = 1; /* Data mmu is default.  */
	int vect_base;

	r_cause = env->sregs[SFR_R_MM_CAUSE];
	r_cfg = env->sregs[SFR_RW_MM_CFG];
	pid = env->pregs[PR_PID] & 0xff;

	switch (rw) {
		case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
		case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
		default:
		case 0: rwcause = CRIS_MMU_ERR_READ; break;
	}

	/* I exception vectors 4 - 7, D 8 - 11.  */
	vect_base = (mmu + 1) * 4;

	vpage = vaddr >> 13;

	/* We know the index which to check on each set.
	   Scan both I and D.  */
#if 0
	for (set = 0; set < 4; set++) {
		for (idx = 0; idx < 16; idx++) {
			lo = env->tlbsets[mmu][set][idx].lo;
			hi = env->tlbsets[mmu][set][idx].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					set, idx, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
#endif

	idx = vpage & 15;
	for (set = 0; set < 4; set++)
	{
		lo = env->tlbsets[mmu][set][idx].lo;
		hi = env->tlbsets[mmu][set][idx].hi;

		tlb_vpn = hi >> 13;
		tlb_pid = EXTRACT_FIELD(hi, 0, 7);
		tlb_g  = EXTRACT_FIELD(lo, 4, 4);

		D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", 
			 mmu, set, idx, tlb_vpn, vpage, lo, hi);
		if ((tlb_g || (tlb_pid == pid))
		    && tlb_vpn == vpage) {
			match = 1;
			break;
		}
	}

	res->bf_vec = vect_base;
	if (match) {
		cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
		cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
		cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
		cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);

		tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
		tlb_v = EXTRACT_FIELD(lo, 3, 3);
		tlb_k = EXTRACT_FIELD(lo, 2, 2);
		tlb_w = EXTRACT_FIELD(lo, 1, 1);
		tlb_x = EXTRACT_FIELD(lo, 0, 0);

		/*
		set_exception_vector(0x04, i_mmu_refill);
		set_exception_vector(0x05, i_mmu_invalid);
		set_exception_vector(0x06, i_mmu_access);
		set_exception_vector(0x07, i_mmu_execute);
		set_exception_vector(0x08, d_mmu_refill);
		set_exception_vector(0x09, d_mmu_invalid);
		set_exception_vector(0x0a, d_mmu_access);
		set_exception_vector(0x0b, d_mmu_write);
		*/
		if (cfg_k && tlb_k && usermode) {
			D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 2;
		} else if (rw == 1 && cfg_w && !tlb_w) {
			D(printf ("tlb: write protected %x lo=%x pc=%x\n", 
				  vaddr, lo, env->pc));
			match = 0;
			/* write accesses never go through the I mmu.  */
			res->bf_vec = vect_base + 3;
		} else if (rw == 2 && cfg_x && !tlb_x) {
			D(printf ("tlb: exec protected %x lo=%x pc=%x\n", 
				 vaddr, lo, env->pc));
			match = 0;
			res->bf_vec = vect_base + 3;
		} else if (cfg_v && !tlb_v) {
			D(printf ("tlb: invalid %x\n", vaddr));
			match = 0;
			res->bf_vec = vect_base + 1;
		}

		res->prot = 0;
		if (match) {
			res->prot |= PAGE_READ;
			if (tlb_w)
				res->prot |= PAGE_WRITE;
			if (tlb_x)
				res->prot |= PAGE_EXEC;
		}
		else
			D(dump_tlb(env, mmu));
	} else {
		/* If refill, provide a randomized set.  */
		set = env->mmu_rand_lfsr & 3;
	}

	if (!match) {
		unsigned int f;

		/* Update lfsr at every fault.  */
		f = compute_polynom(env->mmu_rand_lfsr);
		env->mmu_rand_lfsr >>= 1;
		env->mmu_rand_lfsr |= (f << 15);
		env->mmu_rand_lfsr &= 0xffff;
		
		/* Compute index.  */
		idx = vpage & 15;

		/* Update RW_MM_TLB_SEL.  */
		env->sregs[SFR_RW_MM_TLB_SEL] = 0;
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);

		/* Update RW_MM_CAUSE.  */
		set_field(&r_cause, rwcause, 8, 2);
		set_field(&r_cause, vpage, 13, 19);
		set_field(&r_cause, pid, 0, 8);
		env->sregs[SFR_R_MM_CAUSE] = r_cause;
		D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
	}

	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
		  " %x cause=%x sel=%x sp=%x %x %x\n",
		  __func__, rw, match, env->pc,
		  vaddr, vpage,
		  tlb_vpn, tlb_pfn, tlb_pid, 
		  pid,
		  r_cause,
		  env->sregs[SFR_RW_MM_TLB_SEL],
		  env->regs[R_SP], env->pregs[PR_USP], env->ksp));

	res->phy = tlb_pfn << TARGET_PAGE_BITS;
	return !match;
}

void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
{
	target_ulong vaddr;
	unsigned int idx;
	uint32_t lo, hi;
	uint32_t tlb_vpn;
	int tlb_pid, tlb_g, tlb_v;
	unsigned int set;
	unsigned int mmu;

	pid &= 0xff;
	for (mmu = 0; mmu < 2; mmu++) {
		for (set = 0; set < 4; set++)
		{
			for (idx = 0; idx < 16; idx++) {
				lo = env->tlbsets[mmu][set][idx].lo;
				hi = env->tlbsets[mmu][set][idx].hi;
				
				tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
				tlb_pid = EXTRACT_FIELD(hi, 0, 7);
				tlb_g  = EXTRACT_FIELD(lo, 4, 4);
				tlb_v = EXTRACT_FIELD(lo, 3, 3);

				if (tlb_v && !tlb_g && (tlb_pid == pid)) {
					vaddr = tlb_vpn << TARGET_PAGE_BITS;
					D_LOG("flush pid=%x vaddr=%x\n", 
						  pid, vaddr);
					tlb_flush_page(env, vaddr);
				}
			}
		}
	}
}

int cris_mmu_translate(struct cris_mmu_result_t *res,
		       CPUState *env, uint32_t vaddr,
		       int rw, int mmu_idx)
{
	uint32_t phy = vaddr;
	int seg;
	int miss = 0;
	int is_user = mmu_idx == MMU_USER_IDX;
	uint32_t old_srs;

	old_srs= env->pregs[PR_SRS];

	/* rw == 2 means exec, map the access to the insn mmu.  */
	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;

	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
		res->phy = vaddr;
		res->prot = PAGE_BITS;
		goto done;
	}

	seg = vaddr >> 28;
	if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	{
		uint32_t base;

		miss = 0;
		base = cris_mmu_translate_seg(env, seg);
		phy = base | (0x0fffffff & vaddr);
		res->phy = phy;
		res->prot = PAGE_BITS;
	}
	else
		miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
  done:
	env->pregs[PR_SRS] = old_srs;
	return miss;
}
#endif
Commit	Line	Data
94cff60a TS	1	/*
	2	* CRIS mmu emulation.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, write to the Free Software
fad6cb1a	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
94cff60a TS	20	*/
	21
	22	#ifndef CONFIG_USER_ONLY
	23
	24	#include <stdio.h>
	25	#include <string.h>
	26	#include <stdlib.h>
	27
	28	#include "config.h"
	29	#include "cpu.h"
	30	#include "mmu.h"
	31	#include "exec-all.h"
	32
d297f464 EI	33	#ifdef DEBUG
d297f464 EI	34	#define D(x) x
93fcfe39	35	#define D_LOG(...) qemu_log(__VA__ARGS__)
d297f464	36	#else
786c02f1	37	#define D(x)
d12d51d5	38	#define D_LOG(...) do { } while (0)
d297f464	39	#endif
94cff60a	40
44cd42ee EI	41	void cris_mmu_init(CPUState *env)
	42	{
	43	env->mmu_rand_lfsr = 0xcccc;
	44	}
	45
	46	#define SR_POLYNOM 0x8805
	47	static inline unsigned int compute_polynom(unsigned int sr)
	48	{
	49	unsigned int i;
	50	unsigned int f;
	51
	52	f = 0;
	53	for (i = 0; i < 16; i++)
	54	f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
	55
	56	return f;
	57	}
	58
ef29a70d	59	static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
94cff60a TS	60	{
	61	return (rw_gc_cfg & 12) != 0;
	62	}
	63
ef29a70d	64	static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
94cff60a TS	65	{
	66	return (1 << seg) & rw_mm_cfg;
	67	}
	68
	69	static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
	70	{
	71	uint32_t base;
	72	int i;
	73
	74	if (seg < 8)
	75	base = env->sregs[SFR_RW_MM_KBASE_LO];
	76	else
	77	base = env->sregs[SFR_RW_MM_KBASE_HI];
	78
	79	i = seg & 7;
	80	base >>= i * 4;
	81	base &= 15;
	82
	83	base <<= 28;
	84	return base;
	85	}
	86	/* Used by the tlb decoder. */
	87	#define EXTRACT_FIELD(src, start, end) \
786c02f1 EI	88	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	89
	90	static inline void set_field(uint32_t *dst, unsigned int val,
	91	unsigned int offset, unsigned int width)
	92	{
	93	uint32_t mask;
	94
	95	mask = (1 << width) - 1;
	96	mask <<= offset;
	97	val <<= offset;
	98
	99	val &= mask;
786c02f1 EI	100	*dst &= ~(mask);
	101	*dst \|= val;
	102	}
94cff60a	103
d297f464	104	#ifdef DEBUG
b41f7df0 EI	105	static void dump_tlb(CPUState *env, int mmu)
	106	{
	107	int set;
	108	int idx;
	109	uint32_t hi, lo, tlb_vpn, tlb_pfn;
	110
	111	for (set = 0; set < 4; set++) {
	112	for (idx = 0; idx < 16; idx++) {
	113	lo = env->tlbsets[mmu][set][idx].lo;
	114	hi = env->tlbsets[mmu][set][idx].hi;
	115	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	116	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	117
	118	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
	119	set, idx, hi, lo, tlb_vpn, tlb_pfn);
	120	}
	121	}
	122	}
d297f464	123	#endif
b41f7df0 EI	124
b41f7df0 EI	125	/* rw 0 = read, 1 = write, 2 = exec. */
94cff60a TS	126	static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
	127	CPUState *env, uint32_t vaddr,
	128	int rw, int usermode)
	129	{
	130	unsigned int vpage;
	131	unsigned int idx;
b23761f9	132	uint32_t pid, lo, hi;
786c02f1 EI	133	uint32_t tlb_vpn, tlb_pfn = 0;
	134	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	135	int cfg_v, cfg_k, cfg_w, cfg_x;
b41f7df0	136	int set, match = 0;
786c02f1 EI	137	uint32_t r_cause;
	138	uint32_t r_cfg;
	139	int rwcause;
b41f7df0 EI	140	int mmu = 1; /* Data mmu is default. */
b41f7df0 EI	141	int vect_base;
786c02f1 EI	142
	143	r_cause = env->sregs[SFR_R_MM_CAUSE];
	144	r_cfg = env->sregs[SFR_RW_MM_CFG];
28de16da	145	pid = env->pregs[PR_PID] & 0xff;
b41f7df0 EI	146
	147	switch (rw) {
	148	case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
	149	case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
	150	default:
	151	case 0: rwcause = CRIS_MMU_ERR_READ; break;
	152	}
	153
	154	/* I exception vectors 4 - 7, D 8 - 11. */
	155	vect_base = (mmu + 1) * 4;
94cff60a TS	156
94cff60a TS	157	vpage = vaddr >> 13;
94cff60a TS	158
	159	/* We know the index which to check on each set.
	160	Scan both I and D. */
786c02f1	161	#if 0
b41f7df0 EI	162	for (set = 0; set < 4; set++) {
	163	for (idx = 0; idx < 16; idx++) {
	164	lo = env->tlbsets[mmu][set][idx].lo;
	165	hi = env->tlbsets[mmu][set][idx].hi;
786c02f1 EI	166	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	167	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	168
	169	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
b41f7df0	170	set, idx, hi, lo, tlb_vpn, tlb_pfn);
786c02f1 EI	171	}
	172	}
	173	#endif
b41f7df0 EI	174
	175	idx = vpage & 15;
	176	for (set = 0; set < 4; set++)
94cff60a	177	{
b41f7df0 EI	178	lo = env->tlbsets[mmu][set][idx].lo;
b41f7df0 EI	179	hi = env->tlbsets[mmu][set][idx].hi;
94cff60a	180
b23761f9	181	tlb_vpn = hi >> 13;
44cd42ee	182	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
44cd42ee	183	tlb_g = EXTRACT_FIELD(lo, 4, 4);
94cff60a	184
d12d51d5 AL	185	D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
d12d51d5 AL	186	mmu, set, idx, tlb_vpn, vpage, lo, hi);
b23761f9	187	if ((tlb_g \|\| (tlb_pid == pid))
44cd42ee	188	&& tlb_vpn == vpage) {
94cff60a TS	189	match = 1;
	190	break;
	191	}
	192	}
	193
b41f7df0	194	res->bf_vec = vect_base;
94cff60a	195	if (match) {
786c02f1 EI	196	cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
	197	cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
	198	cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
	199	cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
	200
786c02f1	201	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
786c02f1 EI	202	tlb_v = EXTRACT_FIELD(lo, 3, 3);
	203	tlb_k = EXTRACT_FIELD(lo, 2, 2);
	204	tlb_w = EXTRACT_FIELD(lo, 1, 1);
	205	tlb_x = EXTRACT_FIELD(lo, 0, 0);
	206
	207	/*
	208	set_exception_vector(0x04, i_mmu_refill);
	209	set_exception_vector(0x05, i_mmu_invalid);
	210	set_exception_vector(0x06, i_mmu_access);
	211	set_exception_vector(0x07, i_mmu_execute);
	212	set_exception_vector(0x08, d_mmu_refill);
	213	set_exception_vector(0x09, d_mmu_invalid);
	214	set_exception_vector(0x0a, d_mmu_access);
	215	set_exception_vector(0x0b, d_mmu_write);
	216	*/
44cd42ee	217	if (cfg_k && tlb_k && usermode) {
ef29a70d EI	218	D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
	219	vaddr, lo, env->pc));
	220	match = 0;
	221	res->bf_vec = vect_base + 2;
b41f7df0	222	} else if (rw == 1 && cfg_w && !tlb_w) {
ef29a70d EI	223	D(printf ("tlb: write protected %x lo=%x pc=%x\n",
	224	vaddr, lo, env->pc));
	225	match = 0;
	226	/* write accesses never go through the I mmu. */
	227	res->bf_vec = vect_base + 3;
	228	} else if (rw == 2 && cfg_x && !tlb_x) {
	229	D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
	230	vaddr, lo, env->pc));
786c02f1	231	match = 0;
b41f7df0 EI	232	res->bf_vec = vect_base + 3;
	233	} else if (cfg_v && !tlb_v) {
	234	D(printf ("tlb: invalid %x\n", vaddr));
786c02f1	235	match = 0;
b41f7df0	236	res->bf_vec = vect_base + 1;
786c02f1	237	}
786c02f1	238
b41f7df0 EI	239	res->prot = 0;
	240	if (match) {
	241	res->prot \|= PAGE_READ;
	242	if (tlb_w)
	243	res->prot \|= PAGE_WRITE;
	244	if (tlb_x)
	245	res->prot \|= PAGE_EXEC;
	246	}
	247	else
	248	D(dump_tlb(env, mmu));
44cd42ee EI	249	} else {
	250	/* If refill, provide a randomized set. */
	251	set = env->mmu_rand_lfsr & 3;
786c02f1 EI	252	}
	253
	254	if (!match) {
44cd42ee EI	255	unsigned int f;
	256
	257	/* Update lfsr at every fault. */
	258	f = compute_polynom(env->mmu_rand_lfsr);
	259	env->mmu_rand_lfsr >>= 1;
	260	env->mmu_rand_lfsr \|= (f << 15);
	261	env->mmu_rand_lfsr &= 0xffff;
	262
	263	/* Compute index. */
b41f7df0	264	idx = vpage & 15;
b41f7df0 EI	265
	266	/* Update RW_MM_TLB_SEL. */
	267	env->sregs[SFR_RW_MM_TLB_SEL] = 0;
	268	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
44cd42ee	269	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
b41f7df0 EI	270
	271	/* Update RW_MM_CAUSE. */
	272	set_field(&r_cause, rwcause, 8, 2);
786c02f1	273	set_field(&r_cause, vpage, 13, 19);
28de16da	274	set_field(&r_cause, pid, 0, 8);
786c02f1	275	env->sregs[SFR_R_MM_CAUSE] = r_cause;
b41f7df0	276	D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
94cff60a	277	}
b41f7df0	278
b41f7df0 EI	279	D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
	280	" %x cause=%x sel=%x sp=%x %x %x\n",
	281	__func__, rw, match, env->pc,
786c02f1 EI	282	vaddr, vpage,
786c02f1 EI	283	tlb_vpn, tlb_pfn, tlb_pid,
28de16da	284	pid,
786c02f1 EI	285	r_cause,
786c02f1 EI	286	env->sregs[SFR_RW_MM_TLB_SEL],
b41f7df0	287	env->regs[R_SP], env->pregs[PR_USP], env->ksp));
786c02f1	288
bf91ada5	289	res->phy = tlb_pfn << TARGET_PAGE_BITS;
94cff60a TS	290	return !match;
	291	}
	292
cf1d97f0	293	void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
786c02f1	294	{
cf1d97f0 EI	295	target_ulong vaddr;
	296	unsigned int idx;
	297	uint32_t lo, hi;
	298	uint32_t tlb_vpn;
80e1b265	299	int tlb_pid, tlb_g, tlb_v;
cf1d97f0 EI	300	unsigned int set;
	301	unsigned int mmu;
	302
	303	pid &= 0xff;
	304	for (mmu = 0; mmu < 2; mmu++) {
	305	for (set = 0; set < 4; set++)
	306	{
	307	for (idx = 0; idx < 16; idx++) {
	308	lo = env->tlbsets[mmu][set][idx].lo;
	309	hi = env->tlbsets[mmu][set][idx].hi;
	310
	311	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	312	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
	313	tlb_g = EXTRACT_FIELD(lo, 4, 4);
	314	tlb_v = EXTRACT_FIELD(lo, 3, 3);
cf1d97f0	315
80e1b265	316	if (tlb_v && !tlb_g && (tlb_pid == pid)) {
cf1d97f0	317	vaddr = tlb_vpn << TARGET_PAGE_BITS;
d12d51d5 AL	318	D_LOG("flush pid=%x vaddr=%x\n",
d12d51d5 AL	319	pid, vaddr);
cf1d97f0 EI	320	tlb_flush_page(env, vaddr);
	321	}
	322	}
	323	}
	324	}
786c02f1 EI	325	}
786c02f1 EI	326
94cff60a TS	327	int cris_mmu_translate(struct cris_mmu_result_t *res,
94cff60a TS	328	CPUState *env, uint32_t vaddr,
6ebbf390	329	int rw, int mmu_idx)
94cff60a TS	330	{
	331	uint32_t phy = vaddr;
	332	int seg;
	333	int miss = 0;
786c02f1	334	int is_user = mmu_idx == MMU_USER_IDX;
b41f7df0 EI	335	uint32_t old_srs;
	336
	337	old_srs= env->pregs[PR_SRS];
	338
	339	/* rw == 2 means exec, map the access to the insn mmu. */
	340	env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
94cff60a TS	341
	342	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
	343	res->phy = vaddr;
b23761f9	344	res->prot = PAGE_BITS;
b41f7df0	345	goto done;
94cff60a TS	346	}
	347
	348	seg = vaddr >> 28;
	349	if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	350	{
	351	uint32_t base;
	352
	353	miss = 0;
	354	base = cris_mmu_translate_seg(env, seg);
	355	phy = base \| (0x0fffffff & vaddr);
	356	res->phy = phy;
b23761f9	357	res->prot = PAGE_BITS;
94cff60a TS	358	}
94cff60a TS	359	else
94cff60a	360	miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
b41f7df0 EI	361	done:
b41f7df0 EI	362	env->pregs[PR_SRS] = old_srs;
94cff60a TS	363	return miss;
	364	}
	365	#endif