[qemu.git] / target-cris / mmu.c

/*
 *  CRIS mmu emulation.
 *
 *  Copyright (c) 2007 AXIS Communications AB
 *  Written by Edgar E. Iglesias.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef CONFIG_USER_ONLY

#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "config.h"
#include "cpu.h"
#include "mmu.h"
#include "exec-all.h"

#define D(x)

static int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
	return (rw_gc_cfg & 12) != 0;
}

static int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
	return (1 << seg) & rw_mm_cfg;
}

static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
{
	uint32_t base;
	int i;

	if (seg < 8)
		base = env->sregs[SFR_RW_MM_KBASE_LO];
	else
		base = env->sregs[SFR_RW_MM_KBASE_HI];

	i = seg & 7;
	base >>= i * 4;
	base &= 15;

	base <<= 28;
	return base;
}
/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

static inline void set_field(uint32_t *dst, unsigned int val, 
			     unsigned int offset, unsigned int width)
{
	uint32_t mask;

	mask = (1 << width) - 1;
	mask <<= offset;
	val <<= offset;

	val &= mask;
	D(printf ("val=%x mask=%x dst=%x\n", val, mask, *dst));
	*dst &= ~(mask);
	*dst |= val;
}

static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
				   CPUState *env, uint32_t vaddr,
				   int rw, int usermode)
{
	unsigned int vpage;
	unsigned int idx;
	uint32_t lo, hi;
	uint32_t tlb_vpn, tlb_pfn = 0;
	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	int cfg_v, cfg_k, cfg_w, cfg_x;	
	int i, match = 0;
	uint32_t r_cause;
	uint32_t r_cfg;
	int rwcause;
	int update_sel = 0;

	r_cause = env->sregs[SFR_R_MM_CAUSE];
	r_cfg = env->sregs[SFR_RW_MM_CFG];
	rwcause = rw ? CRIS_MMU_ERR_WRITE : CRIS_MMU_ERR_READ;

	vpage = vaddr >> 13;
	idx = vpage & 15;

	/* We know the index which to check on each set.
	   Scan both I and D.  */
#if 0
	for (i = 0; i < 4; i++) {
		int j;
		for (j = 0; j < 16; j++) {
			lo = env->tlbsets[1][i][j].lo;
			hi = env->tlbsets[1][i][j].hi;
			tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
			tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

			printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", 
					i, j, hi, lo, tlb_vpn, tlb_pfn);
		}
	}
#endif
	for (i = 0; i < 4; i++)
	{
		lo = env->tlbsets[1][i][idx].lo;
		hi = env->tlbsets[1][i][idx].hi;

		tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
		tlb_pfn = EXTRACT_FIELD(lo, 13, 31);

		D(printf ("TLB[%d][%d] tlbv=%x vpage=%x -> pfn=%x\n", 
				i, idx, tlb_vpn, vpage, tlb_pfn));
		if (tlb_vpn == vpage) {
			match = 1;
			break;
		}
	}

	if (match) {

		cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
		cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
		cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
		cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);

		tlb_pid = EXTRACT_FIELD(hi, 0, 7);
		tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
		tlb_g  = EXTRACT_FIELD(lo, 4, 4);
		tlb_v = EXTRACT_FIELD(lo, 3, 3);
		tlb_k = EXTRACT_FIELD(lo, 2, 2);
		tlb_w = EXTRACT_FIELD(lo, 1, 1);
		tlb_x = EXTRACT_FIELD(lo, 0, 0);

		/*
		set_exception_vector(0x04, i_mmu_refill);
		set_exception_vector(0x05, i_mmu_invalid);
		set_exception_vector(0x06, i_mmu_access);
		set_exception_vector(0x07, i_mmu_execute);
		set_exception_vector(0x08, d_mmu_refill);
		set_exception_vector(0x09, d_mmu_invalid);
		set_exception_vector(0x0a, d_mmu_access);
		set_exception_vector(0x0b, d_mmu_write);
		*/
		if (cfg_v && !tlb_v) {
			printf ("tlb: invalid\n");
			set_field(&r_cause, rwcause, 8, 9);
			match = 0;
			res->bf_vec = 0x9;
			update_sel = 1;
		}
		else if (!tlb_g 
			 && tlb_pid != 0xff
			 && tlb_pid != env->pregs[PR_PID]
			 && cfg_w && !tlb_w) {
			printf ("tlb: wrong pid\n");
			match = 0;
			res->bf_vec = 0xa;
		}
		else if (rw && cfg_w && !tlb_w) {
			printf ("tlb: write protected\n");
			match = 0;
			res->bf_vec = 0xb;
		}
	} else
		update_sel = 1;

	if (update_sel) {
		/* miss.  */
		env->sregs[SFR_RW_MM_TLB_SEL] = 0;
		D(printf ("tlb: miss %x vp=%x\n", 
			env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15));
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15, 0, 4);
		set_field(&env->sregs[SFR_RW_MM_TLB_SEL], 0, 4, 5);
		res->bf_vec = 0x8;
	}

	if (!match) {
		set_field(&r_cause, rwcause, 8, 9);
		set_field(&r_cause, vpage, 13, 19);
		set_field(&r_cause, env->pregs[PR_PID], 0, 8);
		env->sregs[SFR_R_MM_CAUSE] = r_cause;
	}
	D(printf ("%s mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
		  " %x cause=%x sel=%x r13=%x\n",
		  __func__, match, env->pc,
		  vaddr, vpage,
		  tlb_vpn, tlb_pfn, tlb_pid, 
		  env->pregs[PR_PID],
		  r_cause,
		  env->sregs[SFR_RW_MM_TLB_SEL],
		  env->regs[13]));

	res->pfn = tlb_pfn;
	return !match;
}

/* Give us the vaddr corresponding to the latest TLB update.  */
target_ulong cris_mmu_tlb_latest_update(CPUState *env, uint32_t new_lo)
{
	uint32_t sel = env->sregs[SFR_RW_MM_TLB_SEL];
	uint32_t vaddr;
	uint32_t hi;
	int set;
	int idx;

	idx = EXTRACT_FIELD(sel, 0, 4);
	set = EXTRACT_FIELD(sel, 4, 5);

	hi = env->tlbsets[1][set][idx].hi;
	vaddr = EXTRACT_FIELD(hi, 13, 31);
	return vaddr << TARGET_PAGE_BITS;
}

int cris_mmu_translate(struct cris_mmu_result_t *res,
		       CPUState *env, uint32_t vaddr,
		       int rw, int mmu_idx)
{
	uint32_t phy = vaddr;
	int seg;
	int miss = 0;
	int is_user = mmu_idx == MMU_USER_IDX;

	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
		res->phy = vaddr;
		return 0;
	}

	seg = vaddr >> 28;
	if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	{
		uint32_t base;

		miss = 0;
		base = cris_mmu_translate_seg(env, seg);
		phy = base | (0x0fffffff & vaddr);
		res->phy = phy;
	}
	else
	{
		miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
		if (!miss) {
			phy &= 8191;
			phy |= (res->pfn << 13);
			res->phy = phy;
		}
	}
	D(printf ("miss=%d v=%x -> p=%x\n", miss, vaddr, phy));
	return miss;
}
#endif
Commit	Line	Data
94cff60a TS	1	/*
	2	* CRIS mmu emulation.
	3	*
	4	* Copyright (c) 2007 AXIS Communications AB
	5	* Written by Edgar E. Iglesias.
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#ifndef CONFIG_USER_ONLY
	23
	24	#include <stdio.h>
	25	#include <string.h>
	26	#include <stdlib.h>
	27
	28	#include "config.h"
	29	#include "cpu.h"
	30	#include "mmu.h"
	31	#include "exec-all.h"
	32
786c02f1	33	#define D(x)
94cff60a TS	34
	35	static int cris_mmu_enabled(uint32_t rw_gc_cfg)
	36	{
	37	return (rw_gc_cfg & 12) != 0;
	38	}
	39
	40	static int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
	41	{
	42	return (1 << seg) & rw_mm_cfg;
	43	}
	44
	45	static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
	46	{
	47	uint32_t base;
	48	int i;
	49
	50	if (seg < 8)
	51	base = env->sregs[SFR_RW_MM_KBASE_LO];
	52	else
	53	base = env->sregs[SFR_RW_MM_KBASE_HI];
	54
	55	i = seg & 7;
	56	base >>= i * 4;
	57	base &= 15;
	58
	59	base <<= 28;
	60	return base;
	61	}
	62	/* Used by the tlb decoder. */
	63	#define EXTRACT_FIELD(src, start, end) \
786c02f1 EI	64	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	65
	66	static inline void set_field(uint32_t *dst, unsigned int val,
	67	unsigned int offset, unsigned int width)
	68	{
	69	uint32_t mask;
	70
	71	mask = (1 << width) - 1;
	72	mask <<= offset;
	73	val <<= offset;
	74
	75	val &= mask;
	76	D(printf ("val=%x mask=%x dst=%x\n", val, mask, *dst));
	77	*dst &= ~(mask);
	78	*dst \|= val;
	79	}
94cff60a TS	80
	81	static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
	82	CPUState *env, uint32_t vaddr,
	83	int rw, int usermode)
	84	{
	85	unsigned int vpage;
	86	unsigned int idx;
	87	uint32_t lo, hi;
786c02f1 EI	88	uint32_t tlb_vpn, tlb_pfn = 0;
	89	int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
	90	int cfg_v, cfg_k, cfg_w, cfg_x;
94cff60a	91	int i, match = 0;
786c02f1 EI	92	uint32_t r_cause;
	93	uint32_t r_cfg;
	94	int rwcause;
	95	int update_sel = 0;
	96
	97	r_cause = env->sregs[SFR_R_MM_CAUSE];
	98	r_cfg = env->sregs[SFR_RW_MM_CFG];
	99	rwcause = rw ? CRIS_MMU_ERR_WRITE : CRIS_MMU_ERR_READ;
94cff60a TS	100
94cff60a TS	101	vpage = vaddr >> 13;
786c02f1	102	idx = vpage & 15;
94cff60a TS	103
	104	/* We know the index which to check on each set.
	105	Scan both I and D. */
786c02f1 EI	106	#if 0
	107	for (i = 0; i < 4; i++) {
	108	int j;
	109	for (j = 0; j < 16; j++) {
	110	lo = env->tlbsets[1][i][j].lo;
	111	hi = env->tlbsets[1][i][j].hi;
	112	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
	113	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	114
	115	printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
	116	i, j, hi, lo, tlb_vpn, tlb_pfn);
	117	}
	118	}
	119	#endif
94cff60a TS	120	for (i = 0; i < 4; i++)
94cff60a TS	121	{
786c02f1 EI	122	lo = env->tlbsets[1][i][idx].lo;
786c02f1 EI	123	hi = env->tlbsets[1][i][idx].hi;
94cff60a	124
786c02f1 EI	125	tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
786c02f1 EI	126	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
94cff60a	127
786c02f1 EI	128	D(printf ("TLB[%d][%d] tlbv=%x vpage=%x -> pfn=%x\n",
	129	i, idx, tlb_vpn, vpage, tlb_pfn));
	130	if (tlb_vpn == vpage) {
94cff60a TS	131	match = 1;
	132	break;
	133	}
	134	}
	135
	136	if (match) {
786c02f1 EI	137
	138	cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
	139	cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
	140	cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
	141	cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
	142
	143	tlb_pid = EXTRACT_FIELD(hi, 0, 7);
	144	tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
	145	tlb_g = EXTRACT_FIELD(lo, 4, 4);
	146	tlb_v = EXTRACT_FIELD(lo, 3, 3);
	147	tlb_k = EXTRACT_FIELD(lo, 2, 2);
	148	tlb_w = EXTRACT_FIELD(lo, 1, 1);
	149	tlb_x = EXTRACT_FIELD(lo, 0, 0);
	150
	151	/*
	152	set_exception_vector(0x04, i_mmu_refill);
	153	set_exception_vector(0x05, i_mmu_invalid);
	154	set_exception_vector(0x06, i_mmu_access);
	155	set_exception_vector(0x07, i_mmu_execute);
	156	set_exception_vector(0x08, d_mmu_refill);
	157	set_exception_vector(0x09, d_mmu_invalid);
	158	set_exception_vector(0x0a, d_mmu_access);
	159	set_exception_vector(0x0b, d_mmu_write);
	160	*/
	161	if (cfg_v && !tlb_v) {
	162	printf ("tlb: invalid\n");
	163	set_field(&r_cause, rwcause, 8, 9);
	164	match = 0;
	165	res->bf_vec = 0x9;
	166	update_sel = 1;
	167	}
	168	else if (!tlb_g
	169	&& tlb_pid != 0xff
	170	&& tlb_pid != env->pregs[PR_PID]
	171	&& cfg_w && !tlb_w) {
	172	printf ("tlb: wrong pid\n");
	173	match = 0;
	174	res->bf_vec = 0xa;
	175	}
	176	else if (rw && cfg_w && !tlb_w) {
	177	printf ("tlb: write protected\n");
	178	match = 0;
	179	res->bf_vec = 0xb;
	180	}
	181	} else
	182	update_sel = 1;
	183
	184	if (update_sel) {
	185	/* miss. */
	186	env->sregs[SFR_RW_MM_TLB_SEL] = 0;
	187	D(printf ("tlb: miss %x vp=%x\n",
	188	env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15));
	189	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], vpage & 15, 0, 4);
	190	set_field(&env->sregs[SFR_RW_MM_TLB_SEL], 0, 4, 5);
	191	res->bf_vec = 0x8;
	192	}
	193
	194	if (!match) {
	195	set_field(&r_cause, rwcause, 8, 9);
	196	set_field(&r_cause, vpage, 13, 19);
	197	set_field(&r_cause, env->pregs[PR_PID], 0, 8);
	198	env->sregs[SFR_R_MM_CAUSE] = r_cause;
94cff60a	199	}
786c02f1 EI	200	D(printf ("%s mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
	201	" %x cause=%x sel=%x r13=%x\n",
	202	__func__, match, env->pc,
	203	vaddr, vpage,
	204	tlb_vpn, tlb_pfn, tlb_pid,
	205	env->pregs[PR_PID],
	206	r_cause,
	207	env->sregs[SFR_RW_MM_TLB_SEL],
	208	env->regs[13]));
	209
	210	res->pfn = tlb_pfn;
94cff60a TS	211	return !match;
	212	}
	213
786c02f1 EI	214	/* Give us the vaddr corresponding to the latest TLB update. */
	215	target_ulong cris_mmu_tlb_latest_update(CPUState *env, uint32_t new_lo)
	216	{
	217	uint32_t sel = env->sregs[SFR_RW_MM_TLB_SEL];
	218	uint32_t vaddr;
	219	uint32_t hi;
	220	int set;
	221	int idx;
	222
	223	idx = EXTRACT_FIELD(sel, 0, 4);
	224	set = EXTRACT_FIELD(sel, 4, 5);
	225
	226	hi = env->tlbsets[1][set][idx].hi;
	227	vaddr = EXTRACT_FIELD(hi, 13, 31);
	228	return vaddr << TARGET_PAGE_BITS;
	229	}
	230
94cff60a TS	231	int cris_mmu_translate(struct cris_mmu_result_t *res,
94cff60a TS	232	CPUState *env, uint32_t vaddr,
6ebbf390	233	int rw, int mmu_idx)
94cff60a TS	234	{
	235	uint32_t phy = vaddr;
	236	int seg;
	237	int miss = 0;
786c02f1	238	int is_user = mmu_idx == MMU_USER_IDX;
94cff60a TS	239
	240	if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
	241	res->phy = vaddr;
	242	return 0;
	243	}
	244
	245	seg = vaddr >> 28;
	246	if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
	247	{
	248	uint32_t base;
	249
	250	miss = 0;
	251	base = cris_mmu_translate_seg(env, seg);
	252	phy = base \| (0x0fffffff & vaddr);
	253	res->phy = phy;
	254	}
	255	else
	256	{
	257	miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
	258	if (!miss) {
	259	phy &= 8191;
	260	phy \|= (res->pfn << 13);
	261	res->phy = phy;
	262	}
	263	}
786c02f1	264	D(printf ("miss=%d v=%x -> p=%x\n", miss, vaddr, phy));
94cff60a TS	265	return miss;
	266	}
	267	#endif