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Debugger single step without interrupts (Jason Wessel).
[qemu.git] / target-cris / translate.c
CommitLineData
8170028d
TS		 1/*
2 * CRIS emulation for qemu: main translation routines.
3 *
05ba7d5f 4 * Copyright (c) 2008 AXIS Communications AB
8170028d
TS		 5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
b41f7df0
EI		 22/*
23 * FIXME:
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
26 */
27
8170028d
TS		 28#include <stdarg.h>
29#include <stdlib.h>
30#include <stdio.h>
31#include <string.h>
32#include <inttypes.h>
33#include <assert.h>
34
35#include "cpu.h"
36#include "exec-all.h"
37#include "disas.h"
57fec1fe 38#include "tcg-op.h"
05ba7d5f 39#include "helper.h"
8170028d 40#include "crisv32-decode.h"
ca10f867 41#include "qemu-common.h"
8170028d
TS		 42
43#define CRIS_STATS 0
44#if CRIS_STATS
45#define STATS(x) x
46#else
47#define STATS(x)
48#endif
49
50#define DISAS_CRIS 0
51#if DISAS_CRIS
52#define DIS(x) x
53#else
54#define DIS(x)
55#endif
56
b41f7df0 57#define D(x)
8170028d
TS		 58#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59#define BUG_ON(x) ({if (x) BUG();})
60
4f400ab5
EI		 61#define DISAS_SWI 5
62
8170028d
TS		 63/* Used by the decoder. */
64#define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
66
67#define CC_MASK_NZ 0xc
68#define CC_MASK_NZV 0xe
69#define CC_MASK_NZVC 0xf
70#define CC_MASK_RNZV 0x10e
71
a825e703
EI		 72TCGv cpu_env;
73TCGv cpu_T[2];
74TCGv cpu_R[16];
75TCGv cpu_PR[16];
76TCGv cc_src;
77TCGv cc_dest;
78TCGv cc_result;
79TCGv cc_op;
80TCGv cc_size;
81TCGv cc_mask;
05ba7d5f 82
b41f7df0
EI		 83TCGv env_btarget;
84TCGv env_pc;
85
8170028d
TS		 86/* This is the state at translation time. */
87typedef struct DisasContext {
88 CPUState *env;
b41f7df0 89 target_ulong pc, ppc;
8170028d
TS		 90
91 /* Decoder. */
92 uint32_t ir;
93 uint32_t opcode;
94 unsigned int op1;
95 unsigned int op2;
96 unsigned int zsize, zzsize;
97 unsigned int mode;
98 unsigned int postinc;
99
8170028d
TS		 100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
b41f7df0
EI		 104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
106 translation time. */
8170028d 107 int flags_x;
b41f7df0 108 int clear_x; /* Clear x after this insn? */
8170028d 109
b41f7df0 110 int user; /* user or kernel mode. */
8170028d
TS		 111 int is_jmp;
112 int dyn_jmp;
113
114 uint32_t delayed_pc;
115 int delayed_branch;
116 int bcc;
117 uint32_t condlabel;
118
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
121} DisasContext;
122
123void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124static void gen_BUG(DisasContext *dc, char *file, int line)
125{
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
129 fflush(NULL);
130 cris_prepare_jmp (dc, 0x70000000 + line);
131}
132
a825e703
EI		 133const char *regnames[] =
134{
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
139};
140const char *pregnames[] =
141{
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
146};
147
05ba7d5f
EI		 148/* We need this table to handle preg-moves with implicit width. */
149int preg_sizes[] = {
150 1, /* bz. */
151 1, /* vr. */
152 4, /* pid. */
153 1, /* srs. */
154 2, /* wz. */
155 4, 4, 4,
156 4, 4, 4, 4,
157 4, 4, 4, 4,
158};
159
160#define t_gen_mov_TN_env(tn, member) \
3157a0a9 161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
05ba7d5f 162#define t_gen_mov_env_TN(member, tn) \
3157a0a9 163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
05ba7d5f 164
b41f7df0
EI		 165static inline void t_gen_mov_TN_reg(TCGv tn, int r)
166{
167 if (r < 0 || r > 15)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
170}
171static inline void t_gen_mov_reg_TN(int r, TCGv tn)
172{
173 if (r < 0 || r > 15)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
176}
05ba7d5f
EI		 177
178static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
179{
b41f7df0
EI		 180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
05ba7d5f
EI		 182 tcg_gen_ld_tl(tn, cpu_env, offset);
183}
184static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
185{
b41f7df0
EI		 186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
05ba7d5f
EI		 188 tcg_gen_st_tl(tn, cpu_env, offset);
189}
190
191static inline void t_gen_mov_TN_preg(TCGv tn, int r)
192{
b41f7df0
EI		 193 if (r < 0 || r > 15)
194 fprintf(stderr, "wrong register read $p%d\n", r);
05ba7d5f 195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
3157a0a9 196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
05ba7d5f 197 else if (r == PR_VR)
3157a0a9 198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
b41f7df0
EI		 199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
202 }
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 }
05ba7d5f 207 else
a825e703 208 tcg_gen_mov_tl(tn, cpu_PR[r]);
05ba7d5f
EI		 209}
210static inline void t_gen_mov_preg_TN(int r, TCGv tn)
211{
b41f7df0
EI		 212 if (r < 0 || r > 15)
213 fprintf(stderr, "wrong register write $p%d\n", r);
05ba7d5f
EI		 214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
215 return;
b41f7df0
EI		 216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 else {
219 if (r == PR_PID) {
220 tcg_gen_helper_0_0(helper_tlb_flush);
221 }
a825e703 222 tcg_gen_mov_tl(cpu_PR[r], tn);
b41f7df0 223 }
05ba7d5f
EI		 224}
225
dceaf394 226static inline void t_gen_raise_exception(uint32_t index)
05ba7d5f 227{
dceaf394 228 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
05ba7d5f
EI		 229}
230
231static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
232{
233 int l1;
234
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
17ac9754 238 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
05ba7d5f
EI		 239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
241 gen_set_label(l1);
242}
243
244static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
245{
246 int l1;
247
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
17ac9754 251 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
05ba7d5f
EI		 252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
254 gen_set_label(l1);
255}
256
257static void t_gen_asr(TCGv d, TCGv a, TCGv b)
258{
259 int l1;
260
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
17ac9754 264 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
05ba7d5f 265 /* Clear dst if shift operands were to large. */
b41f7df0 266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
05ba7d5f
EI		 267 gen_set_label(l1);
268}
269
3157a0a9
EI		 270/* 64-bit signed mul, lower result in d and upper in d2. */
271static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
272{
273 TCGv t0, t1;
274
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
277
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
281
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
b41f7df0
EI		 285
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
3157a0a9
EI		 288}
289
290/* 64-bit unsigned muls, lower result in d and upper in d2. */
291static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
292{
293 TCGv t0, t1;
294
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
297
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
301
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
b41f7df0
EI		 305
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
3157a0a9
EI		 308}
309
d059c172
EI		 310/* 32bit branch-free binary search for counting leading zeros. */
311static void t_gen_lz_i32(TCGv d, TCGv x)
312{
313 TCGv y, m, n;
314
315 y = tcg_temp_new(TCG_TYPE_I32);
316 m = tcg_temp_new(TCG_TYPE_I32);
317 n = tcg_temp_new(TCG_TYPE_I32);
318
319 /* y = -(x >> 16) */
320 tcg_gen_shri_i32(y, x, 16);
390efc54 321 tcg_gen_neg_i32(y, y);
d059c172
EI		 322
323 /* m = (y >> 16) & 16 */
324 tcg_gen_sari_i32(m, y, 16);
325 tcg_gen_andi_i32(m, m, 16);
326
327 /* n = 16 - m */
328 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
329 /* x = x >> m */
330 tcg_gen_shr_i32(x, x, m);
331
332 /* y = x - 0x100 */
333 tcg_gen_subi_i32(y, x, 0x100);
334 /* m = (y >> 16) & 8 */
335 tcg_gen_sari_i32(m, y, 16);
336 tcg_gen_andi_i32(m, m, 8);
337 /* n = n + m */
338 tcg_gen_add_i32(n, n, m);
339 /* x = x << m */
340 tcg_gen_shl_i32(x, x, m);
341
342 /* y = x - 0x1000 */
343 tcg_gen_subi_i32(y, x, 0x1000);
344 /* m = (y >> 16) & 4 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 4);
347 /* n = n + m */
348 tcg_gen_add_i32(n, n, m);
349 /* x = x << m */
350 tcg_gen_shl_i32(x, x, m);
351
352 /* y = x - 0x4000 */
353 tcg_gen_subi_i32(y, x, 0x4000);
354 /* m = (y >> 16) & 2 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 2);
357 /* n = n + m */
358 tcg_gen_add_i32(n, n, m);
359 /* x = x << m */
360 tcg_gen_shl_i32(x, x, m);
361
362 /* y = x >> 14 */
363 tcg_gen_shri_i32(y, x, 14);
364 /* m = y & ~(y >> 1) */
365 tcg_gen_sari_i32(m, y, 1);
366 tcg_gen_xori_i32(m, m, 0xffffffff);
367 tcg_gen_and_i32(m, m, y);
368
369 /* d = n + 2 - m */
370 tcg_gen_addi_i32(d, n, 2);
371 tcg_gen_sub_i32(d, d, m);
372
373 tcg_gen_discard_i32(y);
374 tcg_gen_discard_i32(m);
375 tcg_gen_discard_i32(n);
376}
377
dceaf394
EI		 378static void t_gen_btst(TCGv d, TCGv s)
379{
380 TCGv sbit;
381 TCGv bset;
382 int l1;
383
384 /* des ref:
385 The N flag is set according to the selected bit in the dest reg.
386 The Z flag is set if the selected bit and all bits to the right are
387 zero.
388 The X flag is cleared.
389 Other flags are left untouched.
390 The destination reg is not affected.
391
392 unsigned int fz, sbit, bset, mask, masked_t0;
393
394 sbit = T1 & 31;
395 bset = !!(T0 & (1 << sbit));
396 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
397 masked_t0 = T0 & mask;
398 fz = !(masked_t0 | bset);
399
400 // Clear the X, N and Z flags.
401 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
402 // Set the N and Z flags accordingly.
403 T0 |= (bset << 3) | (fz << 2);
404 */
405
406 l1 = gen_new_label();
407 sbit = tcg_temp_new(TCG_TYPE_TL);
408 bset = tcg_temp_new(TCG_TYPE_TL);
409
410 /* Compute bset and sbit. */
411 tcg_gen_andi_tl(sbit, s, 31);
412 tcg_gen_shl_tl(s, tcg_const_tl(1), sbit);
413 tcg_gen_and_tl(bset, d, s);
414 tcg_gen_shr_tl(bset, bset, sbit);
415 /* Displace to N_FLAG. */
416 tcg_gen_shli_tl(bset, bset, 3);
417
418 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
419 tcg_gen_subi_tl(sbit, sbit, 1);
420 tcg_gen_and_tl(sbit, d, sbit);
421
422 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
423 /* or in the N_FLAG. */
424 tcg_gen_or_tl(d, d, bset);
425 tcg_gen_brcond_tl(TCG_COND_NE, sbit, tcg_const_tl(0), l1);
426 /* or in the Z_FLAG. */
427 tcg_gen_ori_tl(d, d, Z_FLAG);
428 gen_set_label(l1);
429
430 tcg_gen_discard_tl(sbit);
431 tcg_gen_discard_tl(bset);
432}
433
aae6b32a
EI		 434static void t_gen_cris_dstep(TCGv d, TCGv s)
435{
436 int l1;
437
438 l1 = gen_new_label();
439
440 /*
441 * d <<= 1
442 * if (d >= s)
443 * d -= s;
444 */
445 tcg_gen_shli_tl(d, d, 1);
446 tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
447 tcg_gen_sub_tl(d, d, s);
448 gen_set_label(l1);
449}
450
3157a0a9
EI		 451/* Extended arithmetics on CRIS. */
452static inline void t_gen_add_flag(TCGv d, int flag)
453{
454 TCGv c;
455
456 c = tcg_temp_new(TCG_TYPE_TL);
457 t_gen_mov_TN_preg(c, PR_CCS);
458 /* Propagate carry into d. */
459 tcg_gen_andi_tl(c, c, 1 << flag);
460 if (flag)
461 tcg_gen_shri_tl(c, c, flag);
462 tcg_gen_add_tl(d, d, c);
b41f7df0 463 tcg_gen_discard_tl(c);
3157a0a9
EI		 464}
465
466static inline void t_gen_addx_carry(TCGv d)
467{
468 TCGv x, c;
469
470 x = tcg_temp_new(TCG_TYPE_TL);
471 c = tcg_temp_new(TCG_TYPE_TL);
472 t_gen_mov_TN_preg(x, PR_CCS);
473 tcg_gen_mov_tl(c, x);
474
475 /* Propagate carry into d if X is set. Branch free. */
476 tcg_gen_andi_tl(c, c, C_FLAG);
477 tcg_gen_andi_tl(x, x, X_FLAG);
478 tcg_gen_shri_tl(x, x, 4);
479
480 tcg_gen_and_tl(x, x, c);
481 tcg_gen_add_tl(d, d, x);
b41f7df0
EI		 482 tcg_gen_discard_tl(x);
483 tcg_gen_discard_tl(c);
3157a0a9
EI		 484}
485
486static inline void t_gen_subx_carry(TCGv d)
487{
488 TCGv x, c;
489
490 x = tcg_temp_new(TCG_TYPE_TL);
491 c = tcg_temp_new(TCG_TYPE_TL);
492 t_gen_mov_TN_preg(x, PR_CCS);
493 tcg_gen_mov_tl(c, x);
494
495 /* Propagate carry into d if X is set. Branch free. */
496 tcg_gen_andi_tl(c, c, C_FLAG);
497 tcg_gen_andi_tl(x, x, X_FLAG);
498 tcg_gen_shri_tl(x, x, 4);
499
500 tcg_gen_and_tl(x, x, c);
501 tcg_gen_sub_tl(d, d, x);
b41f7df0
EI		 502 tcg_gen_discard_tl(x);
503 tcg_gen_discard_tl(c);
3157a0a9
EI		 504}
505
506/* Swap the two bytes within each half word of the s operand.
507 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
508static inline void t_gen_swapb(TCGv d, TCGv s)
509{
510 TCGv t, org_s;
511
512 t = tcg_temp_new(TCG_TYPE_TL);
513 org_s = tcg_temp_new(TCG_TYPE_TL);
514
515 /* d and s may refer to the same object. */
516 tcg_gen_mov_tl(org_s, s);
517 tcg_gen_shli_tl(t, org_s, 8);
518 tcg_gen_andi_tl(d, t, 0xff00ff00);
519 tcg_gen_shri_tl(t, org_s, 8);
520 tcg_gen_andi_tl(t, t, 0x00ff00ff);
521 tcg_gen_or_tl(d, d, t);
b41f7df0
EI		 522 tcg_gen_discard_tl(t);
523 tcg_gen_discard_tl(org_s);
3157a0a9
EI		 524}
525
526/* Swap the halfwords of the s operand. */
527static inline void t_gen_swapw(TCGv d, TCGv s)
528{
529 TCGv t;
530 /* d and s refer the same object. */
531 t = tcg_temp_new(TCG_TYPE_TL);
532 tcg_gen_mov_tl(t, s);
533 tcg_gen_shli_tl(d, t, 16);
534 tcg_gen_shri_tl(t, t, 16);
535 tcg_gen_or_tl(d, d, t);
b41f7df0 536 tcg_gen_discard_tl(t);
3157a0a9
EI		 537}
538
539/* Reverse the within each byte.
540 T0 = (((T0 << 7) & 0x80808080) |
541 ((T0 << 5) & 0x40404040) |
542 ((T0 << 3) & 0x20202020) |
543 ((T0 << 1) & 0x10101010) |
544 ((T0 >> 1) & 0x08080808) |
545 ((T0 >> 3) & 0x04040404) |
546 ((T0 >> 5) & 0x02020202) |
547 ((T0 >> 7) & 0x01010101));
548 */
549static inline void t_gen_swapr(TCGv d, TCGv s)
550{
551 struct {
552 int shift; /* LSL when positive, LSR when negative. */
553 uint32_t mask;
554 } bitrev [] = {
555 {7, 0x80808080},
556 {5, 0x40404040},
557 {3, 0x20202020},
558 {1, 0x10101010},
559 {-1, 0x08080808},
560 {-3, 0x04040404},
561 {-5, 0x02020202},
562 {-7, 0x01010101}
563 };
564 int i;
565 TCGv t, org_s;
566
567 /* d and s refer the same object. */
568 t = tcg_temp_new(TCG_TYPE_TL);
569 org_s = tcg_temp_new(TCG_TYPE_TL);
570 tcg_gen_mov_tl(org_s, s);
571
572 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
573 tcg_gen_andi_tl(d, t, bitrev[0].mask);
574 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
575 if (bitrev[i].shift >= 0) {
576 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
577 } else {
578 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
579 }
580 tcg_gen_andi_tl(t, t, bitrev[i].mask);
581 tcg_gen_or_tl(d, d, t);
582 }
b41f7df0
EI		 583 tcg_gen_discard_tl(t);
584 tcg_gen_discard_tl(org_s);
3157a0a9
EI		 585}
586
17ac9754
EI		 587static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
588{
589 TCGv btaken;
590 int l1;
591
592 l1 = gen_new_label();
593 btaken = tcg_temp_new(TCG_TYPE_TL);
594
595 /* Conditional jmp. */
596 t_gen_mov_TN_env(btaken, btaken);
597 tcg_gen_movi_tl(env_pc, pc_false);
598 tcg_gen_brcond_tl(TCG_COND_EQ, btaken, tcg_const_tl(0), l1);
599 tcg_gen_movi_tl(env_pc, pc_true);
600 gen_set_label(l1);
601
602 tcg_gen_discard_tl(btaken);
603}
604
8170028d
TS		 605static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
606{
607 TranslationBlock *tb;
608 tb = dc->tb;
609 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
05ba7d5f 610 tcg_gen_goto_tb(n);
50cfa95c 611 tcg_gen_movi_tl(env_pc, dest);
05ba7d5f 612 tcg_gen_exit_tb((long)tb + n);
8170028d 613 } else {
50cfa95c 614 tcg_gen_mov_tl(env_pc, cpu_T[0]);
05ba7d5f 615 tcg_gen_exit_tb(0);
8170028d 616 }
8170028d
TS		 617}
618
619/* Sign extend at translation time. */
620static int sign_extend(unsigned int val, unsigned int width)
621{
622 int sval;
623
624 /* LSL. */
625 val <<= 31 - width;
626 sval = val;
627 /* ASR. */
628 sval >>= 31 - width;
629 return sval;
630}
631
05ba7d5f
EI		 632static inline void cris_clear_x_flag(DisasContext *dc)
633{
b41f7df0
EI		 634 if (!dc->flagx_live
635 || (dc->flagx_live && dc->flags_x)
636 || dc->cc_op != CC_OP_FLAGS)
637 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
638 dc->flagx_live = 1;
639 dc->flags_x = 0;
05ba7d5f
EI		 640}
641
8170028d
TS		 642static void cris_evaluate_flags(DisasContext *dc)
643{
644 if (!dc->flags_live) {
b41f7df0
EI		 645 tcg_gen_movi_tl(cc_op, dc->cc_op);
646 tcg_gen_movi_tl(cc_size, dc->cc_size);
647 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
648
8170028d
TS		 649 switch (dc->cc_op)
650 {
651 case CC_OP_MCP:
b41f7df0 652 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
8170028d
TS		 653 break;
654 case CC_OP_MULS:
b41f7df0 655 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
8170028d
TS		 656 break;
657 case CC_OP_MULU:
b41f7df0 658 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
8170028d
TS		 659 break;
660 case CC_OP_MOVE:
661 switch (dc->cc_size)
662 {
663 case 4:
b41f7df0 664 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
8170028d
TS		 665 break;
666 case 2:
b41f7df0 667 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
8170028d
TS		 668 break;
669 default:
b41f7df0 670 tcg_gen_helper_0_0(helper_evaluate_flags);
8170028d
TS		 671 break;
672 }
673 break;
b41f7df0
EI		 674 case CC_OP_FLAGS:
675 /* live. */
676 break;
8170028d
TS		 677 default:
678 {
679 switch (dc->cc_size)
680 {
681 case 4:
b41f7df0 682 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
8170028d
TS		 683 break;
684 default:
b41f7df0 685 tcg_gen_helper_0_0(helper_evaluate_flags);
8170028d
TS		 686 break;
687 }
688 }
689 break;
690 }
691 dc->flags_live = 1;
692 }
693}
694
695static void cris_cc_mask(DisasContext *dc, unsigned int mask)
696{
697 uint32_t ovl;
698
fd56059f
AZ		 699 /* Check if we need to evaluate the condition codes due to
700 CC overlaying. */
8170028d
TS		 701 ovl = (dc->cc_mask ^ mask) & ~mask;
702 if (ovl) {
703 /* TODO: optimize this case. It trigs all the time. */
704 cris_evaluate_flags (dc);
705 }
706 dc->cc_mask = mask;
8170028d 707 dc->update_cc = 1;
a825e703 708
8170028d
TS		 709 if (mask == 0)
710 dc->update_cc = 0;
a825e703 711 else
8170028d 712 dc->flags_live = 0;
8170028d
TS		 713}
714
b41f7df0 715static void cris_update_cc_op(DisasContext *dc, int op, int size)
8170028d
TS		 716{
717 dc->cc_op = op;
8170028d 718 dc->cc_size = size;
b41f7df0 719 dc->flags_live = 0;
8170028d
TS		 720}
721
722/* op is the operation.
723 T0, T1 are the operands.
724 dst is the destination reg.
725*/
726static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
727{
728 int writeback = 1;
729 if (dc->update_cc) {
b41f7df0 730 cris_update_cc_op(dc, op, size);
a825e703 731 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
3157a0a9
EI		 732
733 /* FIXME: This shouldn't be needed. But we don't pass the
734 tests without it. Investigate. */
735 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
736 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
8170028d
TS		 737 }
738
739 /* Emit the ALU insns. */
740 switch (op)
741 {
742 case CC_OP_ADD:
05ba7d5f 743 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d 744 /* Extended arithmetics. */
3157a0a9 745 t_gen_addx_carry(cpu_T[0]);
8170028d
TS		 746 break;
747 case CC_OP_ADDC:
05ba7d5f 748 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3157a0a9 749 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
8170028d
TS		 750 break;
751 case CC_OP_MCP:
05ba7d5f 752 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3157a0a9 753 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
8170028d
TS		 754 break;
755 case CC_OP_SUB:
390efc54 756 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
05ba7d5f 757 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390efc54 758 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
8170028d 759 /* CRIS flag evaluation needs ~src. */
3157a0a9 760 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
8170028d
TS		 761
762 /* Extended arithmetics. */
3157a0a9 763 t_gen_subx_carry(cpu_T[0]);
8170028d
TS		 764 break;
765 case CC_OP_MOVE:
05ba7d5f 766 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
8170028d
TS		 767 break;
768 case CC_OP_OR:
05ba7d5f 769 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 770 break;
771 case CC_OP_AND:
05ba7d5f 772 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 773 break;
774 case CC_OP_XOR:
05ba7d5f 775 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 776 break;
777 case CC_OP_LSL:
05ba7d5f 778 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 779 break;
780 case CC_OP_LSR:
05ba7d5f 781 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 782 break;
783 case CC_OP_ASR:
05ba7d5f 784 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 785 break;
786 case CC_OP_NEG:
390efc54 787 tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
8170028d 788 /* Extended arithmetics. */
3157a0a9 789 t_gen_subx_carry(cpu_T[0]);
8170028d
TS		 790 break;
791 case CC_OP_LZ:
d059c172 792 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
8170028d
TS		 793 break;
794 case CC_OP_BTST:
dceaf394 795 t_gen_btst(cpu_T[0], cpu_T[1]);
8170028d
TS		 796 writeback = 0;
797 break;
798 case CC_OP_MULS:
3157a0a9
EI		 799 {
800 TCGv mof;
801 mof = tcg_temp_new(TCG_TYPE_TL);
802 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
803 t_gen_mov_preg_TN(PR_MOF, mof);
b41f7df0 804 tcg_gen_discard_tl(mof);
3157a0a9
EI		 805 }
806 break;
8170028d 807 case CC_OP_MULU:
3157a0a9
EI		 808 {
809 TCGv mof;
810 mof = tcg_temp_new(TCG_TYPE_TL);
811 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
812 t_gen_mov_preg_TN(PR_MOF, mof);
b41f7df0 813 tcg_gen_discard_tl(mof);
3157a0a9
EI		 814 }
815 break;
8170028d 816 case CC_OP_DSTEP:
aae6b32a 817 t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
8170028d
TS		 818 break;
819 case CC_OP_BOUND:
3157a0a9
EI		 820 {
821 int l1;
822 l1 = gen_new_label();
823 tcg_gen_brcond_tl(TCG_COND_LEU,
824 cpu_T[0], cpu_T[1], l1);
825 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
826 gen_set_label(l1);
827 }
828 break;
8170028d 829 case CC_OP_CMP:
390efc54 830 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
05ba7d5f
EI		 831 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
832 /* CRIS flag evaluation needs ~src. */
390efc54 833 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
8170028d 834 /* CRIS flag evaluation needs ~src. */
3157a0a9 835 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
8170028d
TS		 836
837 /* Extended arithmetics. */
3157a0a9 838 t_gen_subx_carry(cpu_T[0]);
8170028d
TS		 839 writeback = 0;
840 break;
841 default:
842 fprintf (logfile, "illegal ALU op.\n");
843 BUG();
844 break;
845 }
846
847 if (dc->update_cc)
a825e703 848 tcg_gen_mov_tl(cc_src, cpu_T[1]);
8170028d
TS		 849
850 if (size == 1)
05ba7d5f 851 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
8170028d 852 else if (size == 2)
05ba7d5f
EI		 853 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
854
8170028d
TS		 855 /* Writeback. */
856 if (writeback) {
857 if (size == 4)
05ba7d5f 858 t_gen_mov_reg_TN(rd, cpu_T[0]);
8170028d 859 else {
05ba7d5f
EI		 860 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
861 t_gen_mov_TN_reg(cpu_T[0], rd);
8170028d 862 if (size == 1)
05ba7d5f 863 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
8170028d 864 else
05ba7d5f
EI		 865 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
866 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
867 t_gen_mov_reg_TN(rd, cpu_T[0]);
868 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
8170028d
TS		 869 }
870 }
871 if (dc->update_cc)
a825e703 872 tcg_gen_mov_tl(cc_result, cpu_T[0]);
8170028d
TS		 873
874 {
875 /* TODO: Optimize this. */
876 if (!dc->flagx_live)
877 cris_evaluate_flags(dc);
878 }
879}
880
881static int arith_cc(DisasContext *dc)
882{
883 if (dc->update_cc) {
884 switch (dc->cc_op) {
885 case CC_OP_ADD: return 1;
886 case CC_OP_SUB: return 1;
887 case CC_OP_LSL: return 1;
888 case CC_OP_LSR: return 1;
889 case CC_OP_ASR: return 1;
890 case CC_OP_CMP: return 1;
891 default:
892 return 0;
893 }
894 }
895 return 0;
896}
897
898static void gen_tst_cc (DisasContext *dc, int cond)
899{
900 int arith_opt;
901
902 /* TODO: optimize more condition codes. */
dceaf394
EI		 903
904 /*
905 * If the flags are live, we've gotta look into the bits of CCS.
906 * Otherwise, if we just did an arithmetic operation we try to
907 * evaluate the condition code faster.
908 *
909 * When this function is done, T0 should be non-zero if the condition
910 * code is true.
911 */
8170028d
TS		 912 arith_opt = arith_cc(dc) && !dc->flags_live;
913 switch (cond) {
914 case CC_EQ:
dceaf394
EI		 915 if (arith_opt) {
916 /* If cc_result is zero, T0 should be
917 non-zero otherwise T0 should be zero. */
918 int l1;
919 l1 = gen_new_label();
920 tcg_gen_movi_tl(cpu_T[0], 0);
921 tcg_gen_brcond_tl(TCG_COND_NE, cc_result,
922 tcg_const_tl(0), l1);
923 tcg_gen_movi_tl(cpu_T[0], 1);
924 gen_set_label(l1);
925 }
8170028d
TS		 926 else {
927 cris_evaluate_flags(dc);
dceaf394
EI		 928 tcg_gen_andi_tl(cpu_T[0],
929 cpu_PR[PR_CCS], Z_FLAG);
8170028d
TS		 930 }
931 break;
932 case CC_NE:
933 if (arith_opt)
dceaf394 934 tcg_gen_mov_tl(cpu_T[0], cc_result);
8170028d
TS		 935 else {
936 cris_evaluate_flags(dc);
dceaf394
EI		 937 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
938 Z_FLAG);
939 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
8170028d
TS		 940 }
941 break;
942 case CC_CS:
943 cris_evaluate_flags(dc);
dceaf394 944 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
8170028d
TS		 945 break;
946 case CC_CC:
947 cris_evaluate_flags(dc);
dceaf394
EI		 948 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
949 C_FLAG);
950 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
8170028d
TS		 951 break;
952 case CC_VS:
953 cris_evaluate_flags(dc);
dceaf394 954 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
8170028d
TS		 955 break;
956 case CC_VC:
957 cris_evaluate_flags(dc);
dceaf394
EI		 958 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
959 V_FLAG);
960 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
8170028d
TS		 961 break;
962 case CC_PL:
963 if (arith_opt)
dceaf394 964 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
8170028d
TS		 965 else {
966 cris_evaluate_flags(dc);
dceaf394
EI		 967 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
968 N_FLAG);
969 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 970 }
971 break;
972 case CC_MI:
dceaf394
EI		 973 if (arith_opt) {
974 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
975 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
976 }
8170028d
TS		 977 else {
978 cris_evaluate_flags(dc);
dceaf394
EI		 979 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
980 N_FLAG);
8170028d
TS		 981 }
982 break;
983 case CC_LS:
984 cris_evaluate_flags(dc);
dceaf394
EI		 985 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
986 C_FLAG | Z_FLAG);
8170028d
TS		 987 break;
988 case CC_HI:
989 cris_evaluate_flags(dc);
dceaf394
EI		 990 {
991 TCGv tmp;
992
993 tmp = tcg_temp_new(TCG_TYPE_TL);
994 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
995 C_FLAG | Z_FLAG);
996 /* Overlay the C flag on top of the Z. */
997 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
998 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
999 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1000
1001 tcg_gen_discard_tl(tmp);
1002 }
8170028d
TS		 1003 break;
1004 case CC_GE:
1005 cris_evaluate_flags(dc);
dceaf394
EI		 1006 /* Overlay the V flag on top of the N. */
1007 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1008 tcg_gen_xor_tl(cpu_T[0],
1009 cpu_PR[PR_CCS], cpu_T[0]);
1010 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1011 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 1012 break;
1013 case CC_LT:
1014 cris_evaluate_flags(dc);
dceaf394
EI		 1015 /* Overlay the V flag on top of the N. */
1016 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1017 tcg_gen_xor_tl(cpu_T[0],
1018 cpu_PR[PR_CCS], cpu_T[0]);
1019 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 1020 break;
1021 case CC_GT:
1022 cris_evaluate_flags(dc);
dceaf394
EI		 1023 {
1024 TCGv n, z;
1025
1026 n = tcg_temp_new(TCG_TYPE_TL);
1027 z = tcg_temp_new(TCG_TYPE_TL);
1028
1029 /* To avoid a shift we overlay everything on
1030 the V flag. */
1031 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1032 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1033 /* invert Z. */
1034 tcg_gen_xori_tl(z, z, 2);
1035
1036 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1037 tcg_gen_xori_tl(n, n, 2);
1038 tcg_gen_and_tl(cpu_T[0], z, n);
1039 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1040
1041 tcg_gen_discard_tl(n);
1042 tcg_gen_discard_tl(z);
1043 }
8170028d
TS		 1044 break;
1045 case CC_LE:
1046 cris_evaluate_flags(dc);
dceaf394
EI		 1047 {
1048 TCGv n, z;
1049
1050 n = tcg_temp_new(TCG_TYPE_TL);
1051 z = tcg_temp_new(TCG_TYPE_TL);
1052
1053 /* To avoid a shift we overlay everything on
1054 the V flag. */
1055 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1056 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1057
1058 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1059 tcg_gen_or_tl(cpu_T[0], z, n);
1060 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1061
1062 tcg_gen_discard_tl(n);
1063 tcg_gen_discard_tl(z);
1064 }
8170028d
TS		 1065 break;
1066 case CC_P:
1067 cris_evaluate_flags(dc);
dceaf394 1068 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
8170028d
TS		 1069 break;
1070 case CC_A:
1071 cris_evaluate_flags(dc);
17ac9754 1072 tcg_gen_movi_tl(cpu_T[0], 1);
8170028d
TS		 1073 break;
1074 default:
1075 BUG();
1076 break;
1077 };
1078}
1079
1080static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
1081{
1082 /* This helps us re-schedule the micro-code to insns in delay-slots
1083 before the actual jump. */
1084 dc->delayed_branch = 2;
1085 dc->delayed_pc = dc->pc + offset;
1086 dc->bcc = cond;
1087 if (cond != CC_A)
1088 {
1089 gen_tst_cc (dc, cond);
dceaf394 1090 t_gen_mov_env_TN(btaken, cpu_T[0]);
8170028d 1091 }
b41f7df0 1092 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
8170028d
TS		 1093}
1094
b41f7df0 1095
8170028d
TS		 1096/* Dynamic jumps, when the dest is in a live reg for example. */
1097void cris_prepare_dyn_jmp (DisasContext *dc)
1098{
1099 /* This helps us re-schedule the micro-code to insns in delay-slots
1100 before the actual jump. */
1101 dc->delayed_branch = 2;
1102 dc->dyn_jmp = 1;
1103 dc->bcc = CC_A;
1104}
1105
1106void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
1107{
1108 /* This helps us re-schedule the micro-code to insns in delay-slots
1109 before the actual jump. */
1110 dc->delayed_branch = 2;
1111 dc->delayed_pc = dst;
1112 dc->dyn_jmp = 0;
1113 dc->bcc = CC_A;
1114}
1115
b41f7df0
EI		 1116void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1117 unsigned int size, int sign)
8170028d 1118{
b41f7df0
EI		 1119 int mem_index = cpu_mmu_index(dc->env);
1120
8170028d
TS		 1121 if (size == 1) {
1122 if (sign)
b41f7df0 1123 tcg_gen_qemu_ld8s(dst, addr, mem_index);
8170028d 1124 else
b41f7df0 1125 tcg_gen_qemu_ld8u(dst, addr, mem_index);
8170028d
TS		 1126 }
1127 else if (size == 2) {
1128 if (sign)
b41f7df0 1129 tcg_gen_qemu_ld16s(dst, addr, mem_index);
8170028d 1130 else
b41f7df0 1131 tcg_gen_qemu_ld16u(dst, addr, mem_index);
8170028d
TS		 1132 }
1133 else {
b41f7df0 1134 tcg_gen_qemu_ld32s(dst, addr, mem_index);
8170028d
TS		 1135 }
1136}
1137
17ac9754
EI		 1138void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1139 unsigned int size)
8170028d 1140{
b41f7df0
EI		 1141 int mem_index = cpu_mmu_index(dc->env);
1142
b41f7df0
EI		 1143 cris_evaluate_flags(dc);
1144
8170028d 1145 /* Remember, operands are flipped. CRIS has reversed order. */
b41f7df0 1146 if (size == 1)
17ac9754 1147 tcg_gen_qemu_st8(val, addr, mem_index);
b41f7df0 1148 else if (size == 2)
17ac9754 1149 tcg_gen_qemu_st16(val, addr, mem_index);
8170028d 1150 else
17ac9754 1151 tcg_gen_qemu_st32(val, addr, mem_index);
8170028d
TS		 1152}
1153
05ba7d5f 1154static inline void t_gen_sext(TCGv d, TCGv s, int size)
8170028d
TS		 1155{
1156 if (size == 1)
05ba7d5f 1157 tcg_gen_ext8s_i32(d, s);
8170028d 1158 else if (size == 2)
05ba7d5f 1159 tcg_gen_ext16s_i32(d, s);
50cfa95c
EI		 1160 else
1161 tcg_gen_mov_tl(d, s);
8170028d
TS		 1162}
1163
05ba7d5f 1164static inline void t_gen_zext(TCGv d, TCGv s, int size)
8170028d
TS		 1165{
1166 if (size == 1)
86831435 1167 tcg_gen_ext8u_i32(d, s);
8170028d 1168 else if (size == 2)
86831435 1169 tcg_gen_ext16u_i32(d, s);
50cfa95c
EI		 1170 else
1171 tcg_gen_mov_tl(d, s);
8170028d
TS		 1172}
1173
1174#if DISAS_CRIS
1175static char memsize_char(int size)
1176{
1177 switch (size)
1178 {
1179 case 1: return 'b'; break;
1180 case 2: return 'w'; break;
1181 case 4: return 'd'; break;
1182 default:
1183 return 'x';
1184 break;
1185 }
1186}
1187#endif
1188
1189static unsigned int memsize_z(DisasContext *dc)
1190{
1191 return dc->zsize + 1;
1192}
1193
1194static unsigned int memsize_zz(DisasContext *dc)
1195{
1196 switch (dc->zzsize)
1197 {
1198 case 0: return 1;
1199 case 1: return 2;
1200 default:
1201 return 4;
1202 }
1203}
1204
c7d05695 1205static inline void do_postinc (DisasContext *dc, int size)
8170028d 1206{
c7d05695
EI		 1207 if (dc->postinc)
1208 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
8170028d
TS		 1209}
1210
1211
1212static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1213 int size, int s_ext)
1214{
8170028d 1215 if (s_ext)
50cfa95c 1216 t_gen_sext(cpu_T[1], cpu_R[rs], size);
8170028d 1217 else
50cfa95c 1218 t_gen_zext(cpu_T[1], cpu_R[rs], size);
8170028d
TS		 1219}
1220
1221/* Prepare T0 and T1 for a register alu operation.
1222 s_ext decides if the operand1 should be sign-extended or zero-extended when
1223 needed. */
1224static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1225 int size, int s_ext)
1226{
1227 dec_prep_move_r(dc, rs, rd, size, s_ext);
1228
8170028d 1229 if (s_ext)
50cfa95c 1230 t_gen_sext(cpu_T[0], cpu_R[rd], size);
8170028d 1231 else
50cfa95c 1232 t_gen_zext(cpu_T[0], cpu_R[rd], size);
8170028d
TS		 1233}
1234
1235/* Prepare T0 and T1 for a memory + alu operation.
1236 s_ext decides if the operand1 should be sign-extended or zero-extended when
1237 needed. */
1238static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1239{
1240 unsigned int rs, rd;
1241 uint32_t imm;
1242 int is_imm;
1243 int insn_len = 2;
1244
1245 rs = dc->op1;
1246 rd = dc->op2;
1247 is_imm = rs == 15 && dc->postinc;
1248
1249 /* Load [$rs] onto T1. */
1250 if (is_imm) {
1251 insn_len = 2 + memsize;
1252 if (memsize == 1)
1253 insn_len++;
1254
8170028d
TS		 1255 if (memsize != 4) {
1256 if (s_ext) {
17ac9754
EI		 1257 if (memsize == 1)
1258 imm = ldsb_code(dc->pc + 2);
1259 else
1260 imm = ldsw_code(dc->pc + 2);
8170028d
TS		 1261 } else {
1262 if (memsize == 1)
17ac9754 1263 imm = ldub_code(dc->pc + 2);
8170028d 1264 else
17ac9754 1265 imm = lduw_code(dc->pc + 2);
8170028d 1266 }
17ac9754
EI		 1267 } else
1268 imm = ldl_code(dc->pc + 2);
1269
8170028d
TS		 1270 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1271 imm, rd, s_ext, memsize));
05ba7d5f 1272 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1273 dc->postinc = 0;
1274 } else {
b41f7df0 1275 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
8170028d 1276 if (s_ext)
05ba7d5f 1277 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
8170028d 1278 else
05ba7d5f 1279 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
8170028d
TS		 1280 }
1281
1282 /* put dest in T0. */
05ba7d5f 1283 t_gen_mov_TN_reg(cpu_T[0], rd);
8170028d
TS		 1284 return insn_len;
1285}
1286
1287#if DISAS_CRIS
1288static const char *cc_name(int cc)
1289{
1290 static char *cc_names[16] = {
1291 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1292 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1293 };
1294 assert(cc < 16);
1295 return cc_names[cc];
1296}
1297#endif
1298
b41f7df0
EI		 1299/* Start of insn decoders. */
1300
8170028d
TS		 1301static unsigned int dec_bccq(DisasContext *dc)
1302{
1303 int32_t offset;
1304 int sign;
1305 uint32_t cond = dc->op2;
1306 int tmp;
1307
1308 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1309 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1310
1311 offset *= 2;
1312 offset |= sign << 8;
1313 tmp = offset;
1314 offset = sign_extend(offset, 8);
1315
1316 /* op2 holds the condition-code. */
1317 cris_cc_mask(dc, 0);
1318 cris_prepare_cc_branch (dc, offset, cond);
1319 return 2;
1320}
1321static unsigned int dec_addoq(DisasContext *dc)
1322{
b41f7df0 1323 int32_t imm;
8170028d
TS		 1324
1325 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1326 imm = sign_extend(dc->op1, 7);
1327
1328 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1329 cris_cc_mask(dc, 0);
1330 /* Fetch register operand, */
b41f7df0 1331 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
8170028d
TS		 1332 return 2;
1333}
1334static unsigned int dec_addq(DisasContext *dc)
1335{
1336 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1337
1338 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1339
1340 cris_cc_mask(dc, CC_MASK_NZVC);
1341 /* Fetch register operand, */
05ba7d5f
EI		 1342 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1343 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1344 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1345 return 2;
1346}
1347static unsigned int dec_moveq(DisasContext *dc)
1348{
1349 uint32_t imm;
1350
1351 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1352 imm = sign_extend(dc->op1, 5);
1353 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1354
3157a0a9 1355 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
8170028d
TS		 1356 return 2;
1357}
1358static unsigned int dec_subq(DisasContext *dc)
1359{
1360 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1361
1362 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1363
1364 cris_cc_mask(dc, CC_MASK_NZVC);
1365 /* Fetch register operand, */
05ba7d5f 1366 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1367 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1368 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1369 return 2;
1370}
1371static unsigned int dec_cmpq(DisasContext *dc)
1372{
1373 uint32_t imm;
1374 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1375 imm = sign_extend(dc->op1, 5);
1376
1377 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1378 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1379 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1380 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1381 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1382 return 2;
1383}
1384static unsigned int dec_andq(DisasContext *dc)
1385{
1386 uint32_t imm;
1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1388 imm = sign_extend(dc->op1, 5);
1389
1390 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1391 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1392 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1393 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1394 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1395 return 2;
1396}
1397static unsigned int dec_orq(DisasContext *dc)
1398{
1399 uint32_t imm;
1400 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1401 imm = sign_extend(dc->op1, 5);
1402 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1403 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1404 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1405 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1406 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1407 return 2;
1408}
1409static unsigned int dec_btstq(DisasContext *dc)
1410{
1411 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1412 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
17ac9754 1413
8170028d 1414 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1415 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1416 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1417 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1418
b41f7df0 1419 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3157a0a9 1420 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
8170028d
TS		 1421 dc->flags_live = 1;
1422 return 2;
1423}
1424static unsigned int dec_asrq(DisasContext *dc)
1425{
1426 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1427 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1428 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1429 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1430 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1431 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1432 return 2;
1433}
1434static unsigned int dec_lslq(DisasContext *dc)
1435{
1436 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1437 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1438
1439 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1440 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1441 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1442 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1443 return 2;
1444}
1445static unsigned int dec_lsrq(DisasContext *dc)
1446{
1447 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1448 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1449
1450 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1451 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1452 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1453 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1454 return 2;
1455}
1456
1457static unsigned int dec_move_r(DisasContext *dc)
1458{
1459 int size = memsize_zz(dc);
1460
1461 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1462 memsize_char(size), dc->op1, dc->op2));
1463
1464 cris_cc_mask(dc, CC_MASK_NZ);
1465 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1466 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1467 return 2;
1468}
1469
1470static unsigned int dec_scc_r(DisasContext *dc)
1471{
1472 int cond = dc->op2;
1473
1474 DIS(fprintf (logfile, "s%s $r%u\n",
1475 cc_name(cond), dc->op1));
1476
1477 if (cond != CC_A)
1478 {
dceaf394
EI		 1479 int l1;
1480
8170028d 1481 gen_tst_cc (dc, cond);
dceaf394
EI		 1482
1483 l1 = gen_new_label();
1484 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1485 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
1486 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1487 gen_set_label(l1);
8170028d
TS		 1488 }
1489 else
dceaf394 1490 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
8170028d
TS		 1491
1492 cris_cc_mask(dc, 0);
8170028d
TS		 1493 return 2;
1494}
1495
1496static unsigned int dec_and_r(DisasContext *dc)
1497{
1498 int size = memsize_zz(dc);
1499
1500 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1501 memsize_char(size), dc->op1, dc->op2));
1502 cris_cc_mask(dc, CC_MASK_NZ);
1503 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1504 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1505 return 2;
1506}
1507
1508static unsigned int dec_lz_r(DisasContext *dc)
1509{
1510 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1511 dc->op1, dc->op2));
1512 cris_cc_mask(dc, CC_MASK_NZ);
1513 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1514 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1515 return 2;
1516}
1517
1518static unsigned int dec_lsl_r(DisasContext *dc)
1519{
1520 int size = memsize_zz(dc);
1521
1522 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1523 memsize_char(size), dc->op1, dc->op2));
1524 cris_cc_mask(dc, CC_MASK_NZ);
1525 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1526 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
8170028d
TS		 1527 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1528 return 2;
1529}
1530
1531static unsigned int dec_lsr_r(DisasContext *dc)
1532{
1533 int size = memsize_zz(dc);
1534
1535 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1536 memsize_char(size), dc->op1, dc->op2));
1537 cris_cc_mask(dc, CC_MASK_NZ);
1538 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1539 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
8170028d
TS		 1540 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1541 return 2;
1542}
1543
1544static unsigned int dec_asr_r(DisasContext *dc)
1545{
1546 int size = memsize_zz(dc);
1547
1548 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1549 memsize_char(size), dc->op1, dc->op2));
1550 cris_cc_mask(dc, CC_MASK_NZ);
1551 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
05ba7d5f 1552 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
8170028d
TS		 1553 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1554 return 2;
1555}
1556
1557static unsigned int dec_muls_r(DisasContext *dc)
1558{
1559 int size = memsize_zz(dc);
1560
1561 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1562 memsize_char(size), dc->op1, dc->op2));
1563 cris_cc_mask(dc, CC_MASK_NZV);
1564 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
05ba7d5f 1565 t_gen_sext(cpu_T[0], cpu_T[0], size);
8170028d
TS		 1566 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1567 return 2;
1568}
1569
1570static unsigned int dec_mulu_r(DisasContext *dc)
1571{
1572 int size = memsize_zz(dc);
1573
1574 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1575 memsize_char(size), dc->op1, dc->op2));
1576 cris_cc_mask(dc, CC_MASK_NZV);
1577 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1578 t_gen_zext(cpu_T[0], cpu_T[0], size);
8170028d
TS		 1579 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1580 return 2;
1581}
1582
1583
1584static unsigned int dec_dstep_r(DisasContext *dc)
1585{
1586 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1587 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f
EI		 1588 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1589 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1590 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1591 return 2;
1592}
1593
1594static unsigned int dec_xor_r(DisasContext *dc)
1595{
1596 int size = memsize_zz(dc);
1597 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1598 memsize_char(size), dc->op1, dc->op2));
1599 BUG_ON(size != 4); /* xor is dword. */
1600 cris_cc_mask(dc, CC_MASK_NZ);
1601 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1602 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1603 return 2;
1604}
1605
1606static unsigned int dec_bound_r(DisasContext *dc)
1607{
1608 int size = memsize_zz(dc);
1609 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1610 memsize_char(size), dc->op1, dc->op2));
1611 cris_cc_mask(dc, CC_MASK_NZ);
1612 /* TODO: needs optmimization. */
1613 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1614 /* rd should be 4. */
05ba7d5f 1615 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1616 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1617 return 2;
1618}
1619
1620static unsigned int dec_cmp_r(DisasContext *dc)
1621{
1622 int size = memsize_zz(dc);
1623 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1624 memsize_char(size), dc->op1, dc->op2));
1625 cris_cc_mask(dc, CC_MASK_NZVC);
1626 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1627 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1628 return 2;
1629}
1630
1631static unsigned int dec_abs_r(DisasContext *dc)
1632{
3157a0a9
EI		 1633 int l1;
1634
8170028d
TS		 1635 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1636 dc->op1, dc->op2));
1637 cris_cc_mask(dc, CC_MASK_NZ);
1638 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
3157a0a9
EI		 1639
1640 /* TODO: consider a branch free approach. */
1641 l1 = gen_new_label();
1642 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
390efc54 1643 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
3157a0a9 1644 gen_set_label(l1);
8170028d
TS		 1645 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1646 return 2;
1647}
1648
1649static unsigned int dec_add_r(DisasContext *dc)
1650{
1651 int size = memsize_zz(dc);
1652 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1653 memsize_char(size), dc->op1, dc->op2));
1654 cris_cc_mask(dc, CC_MASK_NZVC);
1655 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1656 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1657 return 2;
1658}
1659
1660static unsigned int dec_addc_r(DisasContext *dc)
1661{
1662 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1663 dc->op1, dc->op2));
1664 cris_evaluate_flags(dc);
1665 cris_cc_mask(dc, CC_MASK_NZVC);
1666 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1667 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1668 return 2;
1669}
1670
1671static unsigned int dec_mcp_r(DisasContext *dc)
1672{
1673 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1674 dc->op2, dc->op1));
1675 cris_evaluate_flags(dc);
1676 cris_cc_mask(dc, CC_MASK_RNZV);
05ba7d5f
EI		 1677 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1678 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
8170028d
TS		 1679 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1680 return 2;
1681}
1682
1683#if DISAS_CRIS
1684static char * swapmode_name(int mode, char *modename) {
1685 int i = 0;
1686 if (mode & 8)
1687 modename[i++] = 'n';
1688 if (mode & 4)
1689 modename[i++] = 'w';
1690 if (mode & 2)
1691 modename[i++] = 'b';
1692 if (mode & 1)
1693 modename[i++] = 'r';
1694 modename[i++] = 0;
1695 return modename;
1696}
1697#endif
1698
1699static unsigned int dec_swap_r(DisasContext *dc)
1700{
1701 DIS(char modename[4]);
1702 DIS(fprintf (logfile, "swap%s $r%u\n",
1703 swapmode_name(dc->op2, modename), dc->op1));
1704
1705 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1706 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
8170028d 1707 if (dc->op2 & 8)
3157a0a9 1708 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
8170028d 1709 if (dc->op2 & 4)
3157a0a9 1710 t_gen_swapw(cpu_T[0], cpu_T[0]);
8170028d 1711 if (dc->op2 & 2)
3157a0a9 1712 t_gen_swapb(cpu_T[0], cpu_T[0]);
8170028d 1713 if (dc->op2 & 1)
3157a0a9
EI		 1714 t_gen_swapr(cpu_T[0], cpu_T[0]);
1715 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
8170028d
TS		 1716 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1717 return 2;
1718}
1719
1720static unsigned int dec_or_r(DisasContext *dc)
1721{
1722 int size = memsize_zz(dc);
1723 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1724 memsize_char(size), dc->op1, dc->op2));
1725 cris_cc_mask(dc, CC_MASK_NZ);
1726 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1727 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1728 return 2;
1729}
1730
1731static unsigned int dec_addi_r(DisasContext *dc)
1732{
1733 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1734 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1735 cris_cc_mask(dc, 0);
1736 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
3157a0a9 1737 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
05ba7d5f
EI		 1738 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1739 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
8170028d
TS		 1740 return 2;
1741}
1742
1743static unsigned int dec_addi_acr(DisasContext *dc)
1744{
1745 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
b41f7df0 1746 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
8170028d
TS		 1747 cris_cc_mask(dc, 0);
1748 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
3157a0a9 1749 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
b41f7df0 1750
05ba7d5f
EI		 1751 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1752 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
8170028d
TS		 1753 return 2;
1754}
1755
1756static unsigned int dec_neg_r(DisasContext *dc)
1757{
1758 int size = memsize_zz(dc);
1759 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1760 memsize_char(size), dc->op1, dc->op2));
1761 cris_cc_mask(dc, CC_MASK_NZVC);
1762 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1763 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1764 return 2;
1765}
1766
1767static unsigned int dec_btst_r(DisasContext *dc)
1768{
1769 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1770 dc->op1, dc->op2));
8170028d
TS		 1771 cris_cc_mask(dc, CC_MASK_NZ);
1772 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1773 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1774
b41f7df0 1775 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3157a0a9 1776 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
8170028d
TS		 1777 dc->flags_live = 1;
1778 return 2;
1779}
1780
1781static unsigned int dec_sub_r(DisasContext *dc)
1782{
1783 int size = memsize_zz(dc);
1784 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1785 memsize_char(size), dc->op1, dc->op2));
1786 cris_cc_mask(dc, CC_MASK_NZVC);
1787 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1788 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1789 return 2;
1790}
1791
1792/* Zero extension. From size to dword. */
1793static unsigned int dec_movu_r(DisasContext *dc)
1794{
1795 int size = memsize_z(dc);
1796 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1797 memsize_char(size),
1798 dc->op1, dc->op2));
1799
1800 cris_cc_mask(dc, CC_MASK_NZ);
1801 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1802 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1803 return 2;
1804}
1805
1806/* Sign extension. From size to dword. */
1807static unsigned int dec_movs_r(DisasContext *dc)
1808{
1809 int size = memsize_z(dc);
1810 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1811 memsize_char(size),
1812 dc->op1, dc->op2));
1813
1814 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1815 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
8170028d 1816 /* Size can only be qi or hi. */
05ba7d5f 1817 t_gen_sext(cpu_T[1], cpu_T[0], size);
8170028d
TS		 1818 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1819 return 2;
1820}
1821
1822/* zero extension. From size to dword. */
1823static unsigned int dec_addu_r(DisasContext *dc)
1824{
1825 int size = memsize_z(dc);
1826 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1827 memsize_char(size),
1828 dc->op1, dc->op2));
1829
1830 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1831 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1832 /* Size can only be qi or hi. */
05ba7d5f
EI		 1833 t_gen_zext(cpu_T[1], cpu_T[1], size);
1834 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1835 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1836 return 2;
1837}
05ba7d5f 1838
8170028d
TS		 1839/* Sign extension. From size to dword. */
1840static unsigned int dec_adds_r(DisasContext *dc)
1841{
1842 int size = memsize_z(dc);
1843 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1844 memsize_char(size),
1845 dc->op1, dc->op2));
1846
1847 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1848 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1849 /* Size can only be qi or hi. */
05ba7d5f
EI		 1850 t_gen_sext(cpu_T[1], cpu_T[1], size);
1851 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1852
8170028d
TS		 1853 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1854 return 2;
1855}
1856
1857/* Zero extension. From size to dword. */
1858static unsigned int dec_subu_r(DisasContext *dc)
1859{
1860 int size = memsize_z(dc);
1861 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1862 memsize_char(size),
1863 dc->op1, dc->op2));
1864
1865 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1866 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1867 /* Size can only be qi or hi. */
05ba7d5f
EI		 1868 t_gen_zext(cpu_T[1], cpu_T[1], size);
1869 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1870 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1871 return 2;
1872}
1873
1874/* Sign extension. From size to dword. */
1875static unsigned int dec_subs_r(DisasContext *dc)
1876{
1877 int size = memsize_z(dc);
1878 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1879 memsize_char(size),
1880 dc->op1, dc->op2));
1881
1882 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1883 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1884 /* Size can only be qi or hi. */
05ba7d5f
EI		 1885 t_gen_sext(cpu_T[1], cpu_T[1], size);
1886 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1887 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1888 return 2;
1889}
1890
1891static unsigned int dec_setclrf(DisasContext *dc)
1892{
1893 uint32_t flags;
1894 int set = (~dc->opcode >> 2) & 1;
1895
1896 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1897 | EXTRACT_FIELD(dc->ir, 0, 3);
1898 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1899 if (set && flags == 0)
1900 DIS(fprintf (logfile, "nop\n"));
1901 else if (!set && (flags & 0x20))
1902 DIS(fprintf (logfile, "di\n"));
1903 else
1904 DIS(fprintf (logfile, "%sf %x\n",
1905 set ? "set" : "clr",
1906 flags));
1907
1908 if (set && (flags & X_FLAG)) {
1909 dc->flagx_live = 1;
1910 dc->flags_x = 1;
1911 }
1912
1913 /* Simply decode the flags. */
1914 cris_evaluate_flags (dc);
b41f7df0
EI		 1915 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1916 tcg_gen_movi_tl(cc_op, dc->cc_op);
1917
dceaf394
EI		 1918 if (set) {
1919 if (!dc->user && (flags & U_FLAG)) {
1920 /* Enter user mode. */
1921 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
1922 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
1923 dc->is_jmp = DISAS_UPDATE;
1924 }
1925 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
1926 }
8170028d 1927 else
dceaf394
EI		 1928 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
1929
8170028d 1930 dc->flags_live = 1;
b41f7df0 1931 dc->clear_x = 0;
8170028d
TS		 1932 return 2;
1933}
1934
1935static unsigned int dec_move_rs(DisasContext *dc)
1936{
1937 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1938 cris_cc_mask(dc, 0);
dceaf394
EI		 1939 tcg_gen_helper_0_2(helper_movl_sreg_reg,
1940 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
8170028d
TS		 1941 return 2;
1942}
1943static unsigned int dec_move_sr(DisasContext *dc)
1944{
05ba7d5f 1945 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
8170028d 1946 cris_cc_mask(dc, 0);
dceaf394
EI		 1947 tcg_gen_helper_0_2(helper_movl_reg_sreg,
1948 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
8170028d
TS		 1949 return 2;
1950}
dceaf394 1951
8170028d
TS		 1952static unsigned int dec_move_rp(DisasContext *dc)
1953{
1954 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1955 cris_cc_mask(dc, 0);
b41f7df0
EI		 1956
1957 if (dc->op2 == PR_CCS) {
1958 cris_evaluate_flags(dc);
1959 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1960 if (dc->user) {
1961 /* User space is not allowed to touch all flags. */
1962 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1963 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1964 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1965 }
1966 }
1967 else
1968 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1969
05ba7d5f 1970 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
b41f7df0
EI		 1971 if (dc->op2 == PR_CCS) {
1972 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1973 dc->flags_live = 1;
1974 }
8170028d
TS		 1975 return 2;
1976}
1977static unsigned int dec_move_pr(DisasContext *dc)
1978{
1979 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1980 cris_cc_mask(dc, 0);
fd56059f
AZ		 1981 /* Support register 0 is hardwired to zero.
1982 Treat it specially. */
1983 if (dc->op2 == 0)
05ba7d5f 1984 tcg_gen_movi_tl(cpu_T[1], 0);
b41f7df0
EI		 1985 else if (dc->op2 == PR_CCS) {
1986 cris_evaluate_flags(dc);
1987 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1988 } else
05ba7d5f 1989 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
8170028d
TS		 1990 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1991 return 2;
1992}
1993
1994static unsigned int dec_move_mr(DisasContext *dc)
1995{
1996 int memsize = memsize_zz(dc);
1997 int insn_len;
1998 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1999 memsize_char(memsize),
2000 dc->op1, dc->postinc ? "+]" : "]",
2001 dc->op2));
2002
8170028d 2003 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2004 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2005 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
2006 do_postinc(dc, memsize);
2007 return insn_len;
2008}
2009
2010static unsigned int dec_movs_m(DisasContext *dc)
2011{
2012 int memsize = memsize_z(dc);
2013 int insn_len;
2014 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2015 memsize_char(memsize),
2016 dc->op1, dc->postinc ? "+]" : "]",
2017 dc->op2));
2018
2019 /* sign extend. */
8170028d 2020 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2021 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2022 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2023 do_postinc(dc, memsize);
2024 return insn_len;
2025}
2026
2027static unsigned int dec_addu_m(DisasContext *dc)
2028{
2029 int memsize = memsize_z(dc);
2030 int insn_len;
2031 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2032 memsize_char(memsize),
2033 dc->op1, dc->postinc ? "+]" : "]",
2034 dc->op2));
2035
2036 /* sign extend. */
8170028d 2037 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2038 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2039 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2040 do_postinc(dc, memsize);
2041 return insn_len;
2042}
2043
2044static unsigned int dec_adds_m(DisasContext *dc)
2045{
2046 int memsize = memsize_z(dc);
2047 int insn_len;
2048 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2049 memsize_char(memsize),
2050 dc->op1, dc->postinc ? "+]" : "]",
2051 dc->op2));
2052
2053 /* sign extend. */
8170028d 2054 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2055 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2056 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2057 do_postinc(dc, memsize);
2058 return insn_len;
2059}
2060
2061static unsigned int dec_subu_m(DisasContext *dc)
2062{
2063 int memsize = memsize_z(dc);
2064 int insn_len;
2065 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2066 memsize_char(memsize),
2067 dc->op1, dc->postinc ? "+]" : "]",
2068 dc->op2));
2069
2070 /* sign extend. */
8170028d 2071 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2072 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2073 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2074 do_postinc(dc, memsize);
2075 return insn_len;
2076}
2077
2078static unsigned int dec_subs_m(DisasContext *dc)
2079{
2080 int memsize = memsize_z(dc);
2081 int insn_len;
2082 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2083 memsize_char(memsize),
2084 dc->op1, dc->postinc ? "+]" : "]",
2085 dc->op2));
2086
2087 /* sign extend. */
8170028d 2088 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2089 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2090 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2091 do_postinc(dc, memsize);
2092 return insn_len;
2093}
2094
2095static unsigned int dec_movu_m(DisasContext *dc)
2096{
2097 int memsize = memsize_z(dc);
2098 int insn_len;
2099
2100 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2101 memsize_char(memsize),
2102 dc->op1, dc->postinc ? "+]" : "]",
2103 dc->op2));
2104
8170028d 2105 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2106 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2107 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2108 do_postinc(dc, memsize);
2109 return insn_len;
2110}
2111
2112static unsigned int dec_cmpu_m(DisasContext *dc)
2113{
2114 int memsize = memsize_z(dc);
2115 int insn_len;
2116 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2117 memsize_char(memsize),
2118 dc->op1, dc->postinc ? "+]" : "]",
2119 dc->op2));
2120
8170028d 2121 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2122 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2123 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
2124 do_postinc(dc, memsize);
2125 return insn_len;
2126}
2127
2128static unsigned int dec_cmps_m(DisasContext *dc)
2129{
2130 int memsize = memsize_z(dc);
2131 int insn_len;
2132 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2133 memsize_char(memsize),
2134 dc->op1, dc->postinc ? "+]" : "]",
2135 dc->op2));
2136
8170028d 2137 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2138 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2139 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2140 do_postinc(dc, memsize);
2141 return insn_len;
2142}
2143
2144static unsigned int dec_cmp_m(DisasContext *dc)
2145{
2146 int memsize = memsize_zz(dc);
2147 int insn_len;
2148 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2149 memsize_char(memsize),
2150 dc->op1, dc->postinc ? "+]" : "]",
2151 dc->op2));
2152
8170028d 2153 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2154 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2155 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2156 do_postinc(dc, memsize);
2157 return insn_len;
2158}
2159
2160static unsigned int dec_test_m(DisasContext *dc)
2161{
2162 int memsize = memsize_zz(dc);
2163 int insn_len;
2164 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2165 memsize_char(memsize),
2166 dc->op1, dc->postinc ? "+]" : "]",
2167 dc->op2));
2168
dceaf394
EI		 2169 cris_evaluate_flags(dc);
2170
b41f7df0 2171 insn_len = dec_prep_alu_m(dc, 0, memsize);
8170028d 2172 cris_cc_mask(dc, CC_MASK_NZ);
dceaf394 2173 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
b41f7df0 2174
05ba7d5f
EI		 2175 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2176 tcg_gen_movi_tl(cpu_T[1], 0);
8170028d
TS		 2177 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2178 do_postinc(dc, memsize);
2179 return insn_len;
2180}
2181
2182static unsigned int dec_and_m(DisasContext *dc)
2183{
2184 int memsize = memsize_zz(dc);
2185 int insn_len;
2186 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2187 memsize_char(memsize),
2188 dc->op1, dc->postinc ? "+]" : "]",
2189 dc->op2));
2190
8170028d 2191 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2192 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2193 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
2194 do_postinc(dc, memsize);
2195 return insn_len;
2196}
2197
2198static unsigned int dec_add_m(DisasContext *dc)
2199{
2200 int memsize = memsize_zz(dc);
2201 int insn_len;
2202 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2203 memsize_char(memsize),
2204 dc->op1, dc->postinc ? "+]" : "]",
2205 dc->op2));
2206
8170028d 2207 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2208 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2209 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
2210 do_postinc(dc, memsize);
2211 return insn_len;
2212}
2213
2214static unsigned int dec_addo_m(DisasContext *dc)
2215{
2216 int memsize = memsize_zz(dc);
2217 int insn_len;
2218 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2219 memsize_char(memsize),
2220 dc->op1, dc->postinc ? "+]" : "]",
2221 dc->op2));
2222
8170028d 2223 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2224 cris_cc_mask(dc, 0);
9004627f 2225 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
8170028d
TS		 2226 do_postinc(dc, memsize);
2227 return insn_len;
2228}
2229
2230static unsigned int dec_bound_m(DisasContext *dc)
2231{
2232 int memsize = memsize_zz(dc);
2233 int insn_len;
2234 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2235 memsize_char(memsize),
2236 dc->op1, dc->postinc ? "+]" : "]",
2237 dc->op2));
2238
8170028d 2239 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2240 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2241 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
2242 do_postinc(dc, memsize);
2243 return insn_len;
2244}
2245
2246static unsigned int dec_addc_mr(DisasContext *dc)
2247{
2248 int insn_len = 2;
2249 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2250 dc->op1, dc->postinc ? "+]" : "]",
2251 dc->op2));
2252
2253 cris_evaluate_flags(dc);
8170028d 2254 insn_len = dec_prep_alu_m(dc, 0, 4);
b41f7df0 2255 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2256 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2257 do_postinc(dc, 4);
2258 return insn_len;
2259}
2260
2261static unsigned int dec_sub_m(DisasContext *dc)
2262{
2263 int memsize = memsize_zz(dc);
2264 int insn_len;
2265 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2266 memsize_char(memsize),
2267 dc->op1, dc->postinc ? "+]" : "]",
2268 dc->op2, dc->ir, dc->zzsize));
2269
8170028d 2270 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2271 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2272 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2273 do_postinc(dc, memsize);
2274 return insn_len;
2275}
2276
2277static unsigned int dec_or_m(DisasContext *dc)
2278{
2279 int memsize = memsize_zz(dc);
2280 int insn_len;
2281 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2282 memsize_char(memsize),
2283 dc->op1, dc->postinc ? "+]" : "]",
2284 dc->op2, dc->pc));
2285
8170028d 2286 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2287 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2288 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2289 do_postinc(dc, memsize);
2290 return insn_len;
2291}
2292
2293static unsigned int dec_move_mp(DisasContext *dc)
2294{
2295 int memsize = memsize_zz(dc);
2296 int insn_len = 2;
2297
2298 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2299 memsize_char(memsize),
2300 dc->op1,
2301 dc->postinc ? "+]" : "]",
2302 dc->op2));
2303
8170028d 2304 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0
EI		 2305 cris_cc_mask(dc, 0);
2306 if (dc->op2 == PR_CCS) {
2307 cris_evaluate_flags(dc);
2308 if (dc->user) {
2309 /* User space is not allowed to touch all flags. */
2310 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2311 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2312 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2313 }
2314 }
2315
05ba7d5f 2316 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
8170028d
TS		 2317
2318 do_postinc(dc, memsize);
2319 return insn_len;
2320}
2321
2322static unsigned int dec_move_pm(DisasContext *dc)
2323{
2324 int memsize;
2325
2326 memsize = preg_sizes[dc->op2];
2327
fd56059f
AZ		 2328 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2329 memsize_char(memsize),
2330 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
8170028d 2331
fd56059f 2332 /* prepare store. Address in T0, value in T1. */
17ac9754
EI		 2333 if (dc->op2 == PR_CCS)
2334 cris_evaluate_flags(dc);
05ba7d5f 2335 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
17ac9754 2336
17ac9754
EI		 2337 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2338
b41f7df0 2339 cris_cc_mask(dc, 0);
8170028d 2340 if (dc->postinc)
17ac9754 2341 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
8170028d
TS		 2342 return 2;
2343}
2344
2345static unsigned int dec_movem_mr(DisasContext *dc)
2346{
17ac9754 2347 TCGv tmp[16];
8170028d
TS		 2348 int i;
2349
2350 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2351 dc->postinc ? "+]" : "]", dc->op2));
2352
05ba7d5f 2353 /* fetch the address into T0 and T1. */
8170028d 2354 for (i = 0; i <= dc->op2; i++) {
17ac9754 2355 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
8170028d 2356 /* Perform the load onto regnum i. Always dword wide. */
17ac9754
EI		 2357 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2358 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
8170028d 2359 }
17ac9754
EI		 2360
2361 for (i = 0; i <= dc->op2; i++) {
2362 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2363 tcg_gen_discard_tl(tmp[i]);
2364 }
2365
05ba7d5f
EI		 2366 /* writeback the updated pointer value. */
2367 if (dc->postinc)
17ac9754 2368 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
b41f7df0
EI		 2369
2370 /* gen_load might want to evaluate the previous insns flags. */
2371 cris_cc_mask(dc, 0);
8170028d
TS		 2372 return 2;
2373}
2374
2375static unsigned int dec_movem_rm(DisasContext *dc)
2376{
2377 int i;
2378
2379 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2380 dc->postinc ? "+]" : "]"));
2381
8170028d 2382 for (i = 0; i <= dc->op2; i++) {
17ac9754
EI		 2383 /* Displace addr. */
2384 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
8170028d 2385 /* Perform the store. */
17ac9754 2386 gen_store(dc, cpu_T[0], cpu_R[i], 4);
8170028d 2387 }
17ac9754
EI		 2388 if (dc->postinc)
2389 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
b41f7df0 2390 cris_cc_mask(dc, 0);
8170028d
TS		 2391 return 2;
2392}
2393
2394static unsigned int dec_move_rm(DisasContext *dc)
2395{
2396 int memsize;
2397
2398 memsize = memsize_zz(dc);
2399
2400 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2401 memsize, dc->op2, dc->op1));
2402
8170028d 2403 /* prepare store. */
17ac9754
EI		 2404 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2405
8170028d 2406 if (dc->postinc)
17ac9754 2407 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
b41f7df0 2408 cris_cc_mask(dc, 0);
8170028d
TS		 2409 return 2;
2410}
2411
8170028d
TS		 2412static unsigned int dec_lapcq(DisasContext *dc)
2413{
2414 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2415 dc->pc + dc->op1*2, dc->op2));
2416 cris_cc_mask(dc, 0);
05ba7d5f 2417 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
8170028d
TS		 2418 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2419 return 2;
2420}
2421
2422static unsigned int dec_lapc_im(DisasContext *dc)
2423{
2424 unsigned int rd;
2425 int32_t imm;
b41f7df0 2426 int32_t pc;
8170028d
TS		 2427
2428 rd = dc->op2;
2429
2430 cris_cc_mask(dc, 0);
2431 imm = ldl_code(dc->pc + 2);
2432 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
b41f7df0
EI		 2433
2434 pc = dc->pc;
2435 pc += imm;
2436 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
05ba7d5f 2437 return 6;
8170028d
TS		 2438}
2439
2440/* Jump to special reg. */
2441static unsigned int dec_jump_p(DisasContext *dc)
2442{
2443 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
b41f7df0 2444
17ac9754
EI		 2445 if (dc->op2 == PR_CCS)
2446 cris_evaluate_flags(dc);
05ba7d5f 2447 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
b41f7df0
EI		 2448 /* rete will often have low bit set to indicate delayslot. */
2449 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
17ac9754 2450 cris_cc_mask(dc, 0);
8170028d
TS		 2451 cris_prepare_dyn_jmp(dc);
2452 return 2;
2453}
2454
2455/* Jump and save. */
2456static unsigned int dec_jas_r(DisasContext *dc)
2457{
2458 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2459 cris_cc_mask(dc, 0);
b41f7df0
EI		 2460 /* Store the return address in Pd. */
2461 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2462 if (dc->op2 > 15)
2463 abort();
17ac9754
EI		 2464 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
2465 tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
b41f7df0 2466
8170028d
TS		 2467 cris_prepare_dyn_jmp(dc);
2468 return 2;
2469}
2470
2471static unsigned int dec_jas_im(DisasContext *dc)
2472{
2473 uint32_t imm;
2474
2475 imm = ldl_code(dc->pc + 2);
2476
2477 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2478 cris_cc_mask(dc, 0);
17ac9754 2479 /* Store the return address in Pd. */
b41f7df0 2480 tcg_gen_movi_tl(env_btarget, imm);
a825e703 2481 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
8170028d
TS		 2482 cris_prepare_dyn_jmp(dc);
2483 return 6;
2484}
2485
2486static unsigned int dec_jasc_im(DisasContext *dc)
2487{
2488 uint32_t imm;
2489
2490 imm = ldl_code(dc->pc + 2);
2491
2492 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2493 cris_cc_mask(dc, 0);
17ac9754 2494 /* Store the return address in Pd. */
05ba7d5f 2495 tcg_gen_movi_tl(cpu_T[0], imm);
73e51723 2496 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f
EI		 2497 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2498 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
8170028d
TS		 2499 cris_prepare_dyn_jmp(dc);
2500 return 6;
2501}
2502
2503static unsigned int dec_jasc_r(DisasContext *dc)
2504{
2505 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2506 cris_cc_mask(dc, 0);
17ac9754 2507 /* Store the return address in Pd. */
05ba7d5f 2508 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
73e51723 2509 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f
EI		 2510 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2511 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
8170028d
TS		 2512 cris_prepare_dyn_jmp(dc);
2513 return 2;
2514}
2515
2516static unsigned int dec_bcc_im(DisasContext *dc)
2517{
2518 int32_t offset;
2519 uint32_t cond = dc->op2;
2520
17ac9754 2521 offset = ldsw_code(dc->pc + 2);
8170028d
TS		 2522
2523 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2524 cc_name(cond), offset,
2525 dc->pc, dc->pc + offset));
2526
2527 cris_cc_mask(dc, 0);
2528 /* op2 holds the condition-code. */
2529 cris_prepare_cc_branch (dc, offset, cond);
2530 return 4;
2531}
2532
2533static unsigned int dec_bas_im(DisasContext *dc)
2534{
2535 int32_t simm;
2536
2537
2538 simm = ldl_code(dc->pc + 2);
2539
2540 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2541 cris_cc_mask(dc, 0);
2542 /* Stor the return address in Pd. */
05ba7d5f 2543 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
73e51723 2544 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f
EI		 2545 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2546 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
8170028d
TS		 2547 cris_prepare_dyn_jmp(dc);
2548 return 6;
2549}
2550
2551static unsigned int dec_basc_im(DisasContext *dc)
2552{
2553 int32_t simm;
2554 simm = ldl_code(dc->pc + 2);
2555
2556 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2557 cris_cc_mask(dc, 0);
2558 /* Stor the return address in Pd. */
05ba7d5f 2559 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
73e51723 2560 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f
EI		 2561 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2562 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
8170028d
TS		 2563 cris_prepare_dyn_jmp(dc);
2564 return 6;
2565}
2566
2567static unsigned int dec_rfe_etc(DisasContext *dc)
2568{
2569 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2570 dc->opcode, dc->pc, dc->op1, dc->op2));
2571
2572 cris_cc_mask(dc, 0);
2573
2574 if (dc->op2 == 15) /* ignore halt. */
05ba7d5f 2575 return 2;
8170028d
TS		 2576
2577 switch (dc->op2 & 7) {
2578 case 2:
2579 /* rfe. */
2580 cris_evaluate_flags(dc);
b41f7df0
EI		 2581 tcg_gen_helper_0_0(helper_rfe);
2582 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2583 break;
2584 case 5:
2585 /* rfn. */
2586 BUG();
2587 break;
2588 case 6:
2589 /* break. */
05ba7d5f 2590 tcg_gen_movi_tl(cpu_T[0], dc->pc);
3157a0a9 2591 t_gen_mov_env_TN(pc, cpu_T[0]);
8170028d 2592 /* Breaks start at 16 in the exception vector. */
dceaf394
EI		 2593 t_gen_mov_env_TN(trap_vector,
2594 tcg_const_tl(dc->op1 + 16));
2595 t_gen_raise_exception(EXCP_BREAK);
b41f7df0 2596 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2597 break;
2598 default:
2599 printf ("op2=%x\n", dc->op2);
2600 BUG();
2601 break;
2602
2603 }
8170028d
TS		 2604 return 2;
2605}
2606
5d4a534d
EI		 2607static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2608{
2609 /* Ignore D-cache flushes. */
2610 return 2;
2611}
2612
2613static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2614{
2615 /* Ignore I-cache flushes. */
2616 return 2;
2617}
2618
8170028d
TS		 2619static unsigned int dec_null(DisasContext *dc)
2620{
2621 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2622 dc->pc, dc->opcode, dc->op1, dc->op2);
2623 fflush(NULL);
2624 BUG();
2625 return 2;
2626}
2627
2628struct decoder_info {
2629 struct {
2630 uint32_t bits;
2631 uint32_t mask;
2632 };
2633 unsigned int (*dec)(DisasContext *dc);
2634} decinfo[] = {
2635 /* Order matters here. */
2636 {DEC_MOVEQ, dec_moveq},
2637 {DEC_BTSTQ, dec_btstq},
2638 {DEC_CMPQ, dec_cmpq},
2639 {DEC_ADDOQ, dec_addoq},
2640 {DEC_ADDQ, dec_addq},
2641 {DEC_SUBQ, dec_subq},
2642 {DEC_ANDQ, dec_andq},
2643 {DEC_ORQ, dec_orq},
2644 {DEC_ASRQ, dec_asrq},
2645 {DEC_LSLQ, dec_lslq},
2646 {DEC_LSRQ, dec_lsrq},
2647 {DEC_BCCQ, dec_bccq},
2648
2649 {DEC_BCC_IM, dec_bcc_im},
2650 {DEC_JAS_IM, dec_jas_im},
2651 {DEC_JAS_R, dec_jas_r},
2652 {DEC_JASC_IM, dec_jasc_im},
2653 {DEC_JASC_R, dec_jasc_r},
2654 {DEC_BAS_IM, dec_bas_im},
2655 {DEC_BASC_IM, dec_basc_im},
2656 {DEC_JUMP_P, dec_jump_p},
2657 {DEC_LAPC_IM, dec_lapc_im},
2658 {DEC_LAPCQ, dec_lapcq},
2659
2660 {DEC_RFE_ETC, dec_rfe_etc},
2661 {DEC_ADDC_MR, dec_addc_mr},
2662
2663 {DEC_MOVE_MP, dec_move_mp},
2664 {DEC_MOVE_PM, dec_move_pm},
2665 {DEC_MOVEM_MR, dec_movem_mr},
2666 {DEC_MOVEM_RM, dec_movem_rm},
2667 {DEC_MOVE_PR, dec_move_pr},
2668 {DEC_SCC_R, dec_scc_r},
2669 {DEC_SETF, dec_setclrf},
2670 {DEC_CLEARF, dec_setclrf},
2671
2672 {DEC_MOVE_SR, dec_move_sr},
2673 {DEC_MOVE_RP, dec_move_rp},
2674 {DEC_SWAP_R, dec_swap_r},
2675 {DEC_ABS_R, dec_abs_r},
2676 {DEC_LZ_R, dec_lz_r},
2677 {DEC_MOVE_RS, dec_move_rs},
2678 {DEC_BTST_R, dec_btst_r},
2679 {DEC_ADDC_R, dec_addc_r},
2680
2681 {DEC_DSTEP_R, dec_dstep_r},
2682 {DEC_XOR_R, dec_xor_r},
2683 {DEC_MCP_R, dec_mcp_r},
2684 {DEC_CMP_R, dec_cmp_r},
2685
2686 {DEC_ADDI_R, dec_addi_r},
2687 {DEC_ADDI_ACR, dec_addi_acr},
2688
2689 {DEC_ADD_R, dec_add_r},
2690 {DEC_SUB_R, dec_sub_r},
2691
2692 {DEC_ADDU_R, dec_addu_r},
2693 {DEC_ADDS_R, dec_adds_r},
2694 {DEC_SUBU_R, dec_subu_r},
2695 {DEC_SUBS_R, dec_subs_r},
2696 {DEC_LSL_R, dec_lsl_r},
2697
2698 {DEC_AND_R, dec_and_r},
2699 {DEC_OR_R, dec_or_r},
2700 {DEC_BOUND_R, dec_bound_r},
2701 {DEC_ASR_R, dec_asr_r},
2702 {DEC_LSR_R, dec_lsr_r},
2703
2704 {DEC_MOVU_R, dec_movu_r},
2705 {DEC_MOVS_R, dec_movs_r},
2706 {DEC_NEG_R, dec_neg_r},
2707 {DEC_MOVE_R, dec_move_r},
2708
5d4a534d
EI		 2709 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2710 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
8170028d
TS		 2711
2712 {DEC_MULS_R, dec_muls_r},
2713 {DEC_MULU_R, dec_mulu_r},
2714
2715 {DEC_ADDU_M, dec_addu_m},
2716 {DEC_ADDS_M, dec_adds_m},
2717 {DEC_SUBU_M, dec_subu_m},
2718 {DEC_SUBS_M, dec_subs_m},
2719
2720 {DEC_CMPU_M, dec_cmpu_m},
2721 {DEC_CMPS_M, dec_cmps_m},
2722 {DEC_MOVU_M, dec_movu_m},
2723 {DEC_MOVS_M, dec_movs_m},
2724
2725 {DEC_CMP_M, dec_cmp_m},
2726 {DEC_ADDO_M, dec_addo_m},
2727 {DEC_BOUND_M, dec_bound_m},
2728 {DEC_ADD_M, dec_add_m},
2729 {DEC_SUB_M, dec_sub_m},
2730 {DEC_AND_M, dec_and_m},
2731 {DEC_OR_M, dec_or_m},
2732 {DEC_MOVE_RM, dec_move_rm},
2733 {DEC_TEST_M, dec_test_m},
2734 {DEC_MOVE_MR, dec_move_mr},
2735
2736 {{0, 0}, dec_null}
2737};
2738
2739static inline unsigned int
2740cris_decoder(DisasContext *dc)
2741{
2742 unsigned int insn_len = 2;
8170028d
TS		 2743 int i;
2744
2745 /* Load a halfword onto the instruction register. */
17ac9754 2746 dc->ir = lduw_code(dc->pc);
8170028d
TS		 2747
2748 /* Now decode it. */
2749 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2750 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2751 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2752 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2753 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2754 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2755
2756 /* Large switch for all insns. */
2757 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2758 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2759 {
2760 insn_len = decinfo[i].dec(dc);
2761 break;
2762 }
2763 }
2764
2765 return insn_len;
2766}
2767
2768static void check_breakpoint(CPUState *env, DisasContext *dc)
2769{
2770 int j;
2771 if (env->nb_breakpoints > 0) {
2772 for(j = 0; j < env->nb_breakpoints; j++) {
2773 if (env->breakpoints[j] == dc->pc) {
2774 cris_evaluate_flags (dc);
05ba7d5f 2775 tcg_gen_movi_tl(cpu_T[0], dc->pc);
3157a0a9 2776 t_gen_mov_env_TN(pc, cpu_T[0]);
dceaf394 2777 t_gen_raise_exception(EXCP_DEBUG);
8170028d
TS		 2778 dc->is_jmp = DISAS_UPDATE;
2779 }
2780 }
2781 }
2782}
2783
8170028d
TS		 2784/* generate intermediate code for basic block 'tb'. */
2785struct DisasContext ctx;
2786static int
2787gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2788 int search_pc)
2789{
2790 uint16_t *gen_opc_end;
2791 uint32_t pc_start;
2792 unsigned int insn_len;
2793 int j, lj;
2794 struct DisasContext *dc = &ctx;
2795 uint32_t next_page_start;
2796
a825e703
EI		 2797 if (!logfile)
2798 logfile = stderr;
2799
73e51723
EI		 2800 /* Odd PC indicates that branch is rexecuting due to exception in the
2801 * delayslot, like in real hw.
2802 * FIXME: we need to handle the case were the branch and the insn in
2803 * the delayslot do not share pages.
2804 */
2805 pc_start = tb->pc & ~1;
8170028d
TS		 2806 dc->env = env;
2807 dc->tb = tb;
2808
8170028d 2809 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8170028d
TS		 2810
2811 dc->is_jmp = DISAS_NEXT;
b41f7df0 2812 dc->ppc = pc_start;
8170028d
TS		 2813 dc->pc = pc_start;
2814 dc->singlestep_enabled = env->singlestep_enabled;
b41f7df0 2815 dc->flags_live = 1;
8170028d
TS		 2816 dc->flagx_live = 0;
2817 dc->flags_x = 0;
b41f7df0
EI		 2818 dc->cc_mask = 0;
2819 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2820
2821 dc->user = env->pregs[PR_CCS] & U_FLAG;
2822 dc->delayed_branch = 0;
2823
2824 if (loglevel & CPU_LOG_TB_IN_ASM) {
2825 fprintf(logfile,
dceaf394 2826 "search=%d pc=%x ccs=%x pid=%x usp=%x dbg=%x %x %x\n"
b41f7df0
EI		 2827 "%x.%x.%x.%x\n"
2828 "%x.%x.%x.%x\n"
2829 "%x.%x.%x.%x\n"
2830 "%x.%x.%x.%x\n",
2831 search_pc, env->pc, env->pregs[PR_CCS],
2832 env->pregs[PR_PID], env->pregs[PR_USP],
dceaf394 2833 env->debug1, env->debug2, env->debug3,
b41f7df0
EI		 2834 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2835 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2836 env->regs[8], env->regs[9],
2837 env->regs[10], env->regs[11],
2838 env->regs[12], env->regs[13],
2839 env->regs[14], env->regs[15]);
2840
2841 }
3157a0a9 2842
8170028d
TS		 2843 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2844 lj = -1;
2845 do
2846 {
2847 check_breakpoint(env, dc);
4f400ab5
EI		 2848 if (dc->is_jmp == DISAS_JUMP
2849 || dc->is_jmp == DISAS_SWI)
8170028d
TS		 2850 goto done;
2851
2852 if (search_pc) {
2853 j = gen_opc_ptr - gen_opc_buf;
2854 if (lj < j) {
2855 lj++;
2856 while (lj < j)
2857 gen_opc_instr_start[lj++] = 0;
2858 }
b41f7df0
EI		 2859 if (dc->delayed_branch == 1) {
2860 gen_opc_pc[lj] = dc->ppc | 1;
2861 gen_opc_instr_start[lj] = 0;
2862 }
2863 else {
2864 gen_opc_pc[lj] = dc->pc;
2865 gen_opc_instr_start[lj] = 1;
2866 }
8170028d
TS		 2867 }
2868
b41f7df0 2869 dc->clear_x = 1;
8170028d 2870 insn_len = cris_decoder(dc);
b41f7df0 2871 dc->ppc = dc->pc;
8170028d 2872 dc->pc += insn_len;
b41f7df0
EI		 2873 if (dc->clear_x)
2874 cris_clear_x_flag(dc);
8170028d
TS		 2875
2876 /* Check for delayed branches here. If we do it before
2877 actually genereating any host code, the simulator will just
2878 loop doing nothing for on this program location. */
2879 if (dc->delayed_branch) {
2880 dc->delayed_branch--;
2881 if (dc->delayed_branch == 0)
2882 {
2883 if (dc->bcc == CC_A) {
17ac9754 2884 tcg_gen_mov_tl(env_pc, env_btarget);
b41f7df0 2885 dc->is_jmp = DISAS_JUMP;
8170028d
TS		 2886 }
2887 else {
17ac9754 2888 t_gen_cc_jmp(dc->delayed_pc, dc->pc);
b41f7df0 2889 dc->is_jmp = DISAS_JUMP;
8170028d
TS		 2890 }
2891 }
2892 }
2893
73e51723
EI		 2894 /* If we are rexecuting a branch due to exceptions on
2895 delay slots dont break. */
2896 if (!(tb->pc & 1) && env->singlestep_enabled)
8170028d
TS		 2897 break;
2898 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
b41f7df0
EI		 2899 && ((dc->pc < next_page_start) || dc->delayed_branch));
2900
2901 if (dc->delayed_branch == 1) {
2902 /* Reexecute the last insn. */
73e51723 2903 dc->pc = dc->ppc | 1;
b41f7df0 2904 }
8170028d
TS		 2905
2906 if (!dc->is_jmp) {
b41f7df0
EI		 2907 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2908 dc->is_jmp, dc->delayed_branch));
2909 /* T0 and env_pc should hold the new pc. */
3157a0a9 2910 tcg_gen_movi_tl(cpu_T[0], dc->pc);
b41f7df0 2911 tcg_gen_mov_tl(env_pc, cpu_T[0]);
8170028d
TS		 2912 }
2913
2914 cris_evaluate_flags (dc);
2915 done:
2916 if (__builtin_expect(env->singlestep_enabled, 0)) {
dceaf394 2917 t_gen_raise_exception(EXCP_DEBUG);
8170028d
TS		 2918 } else {
2919 switch(dc->is_jmp) {
2920 case DISAS_NEXT:
2921 gen_goto_tb(dc, 1, dc->pc);
2922 break;
2923 default:
2924 case DISAS_JUMP:
2925 case DISAS_UPDATE:
2926 /* indicate that the hash table must be used
2927 to find the next TB */
57fec1fe 2928 tcg_gen_exit_tb(0);
8170028d 2929 break;
4f400ab5 2930 case DISAS_SWI:
8170028d
TS		 2931 case DISAS_TB_JUMP:
2932 /* nothing more to generate */
2933 break;
2934 }
2935 }
2936 *gen_opc_ptr = INDEX_op_end;
2937 if (search_pc) {
2938 j = gen_opc_ptr - gen_opc_buf;
2939 lj++;
2940 while (lj <= j)
2941 gen_opc_instr_start[lj++] = 0;
2942 } else {
2943 tb->size = dc->pc - pc_start;
2944 }
2945
2946#ifdef DEBUG_DISAS
2947 if (loglevel & CPU_LOG_TB_IN_ASM) {
2948 fprintf(logfile, "--------------\n");
2949 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
17ac9754 2950 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
b41f7df0
EI		 2951 fprintf(logfile, "\nisize=%d osize=%d\n",
2952 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
8170028d
TS		 2953 }
2954#endif
2955 return 0;
2956}
2957
2958int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2959{
2960 return gen_intermediate_code_internal(env, tb, 0);
2961}
2962
2963int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2964{
2965 return gen_intermediate_code_internal(env, tb, 1);
2966}
2967
2968void cpu_dump_state (CPUState *env, FILE *f,
2969 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2970 int flags)
2971{
2972 int i;
2973 uint32_t srs;
2974
2975 if (!env || !f)
2976 return;
2977
2978 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2979 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2980 "debug=%x %x %x\n",
9004627f 2981 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
8170028d
TS		 2982 env->cc_op,
2983 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2984 env->debug1, env->debug2, env->debug3);
2985
2986 for (i = 0; i < 16; i++) {
2987 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2988 if ((i + 1) % 4 == 0)
2989 cpu_fprintf(f, "\n");
2990 }
2991 cpu_fprintf(f, "\nspecial regs:\n");
2992 for (i = 0; i < 16; i++) {
2993 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2994 if ((i + 1) % 4 == 0)
2995 cpu_fprintf(f, "\n");
2996 }
9004627f 2997 srs = env->pregs[PR_SRS];
b41f7df0 2998 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
8170028d
TS		 2999 if (srs < 256) {
3000 for (i = 0; i < 16; i++) {
3001 cpu_fprintf(f, "s%2.2d=%8.8x ",
3002 i, env->sregs[srs][i]);
3003 if ((i + 1) % 4 == 0)
3004 cpu_fprintf(f, "\n");
3005 }
3006 }
3007 cpu_fprintf(f, "\n\n");
3008
3009}
3010
05ba7d5f
EI		 3011static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
3012{
3013}
3014
aaed909a 3015CPUCRISState *cpu_cris_init (const char *cpu_model)
8170028d
TS		 3016{
3017 CPUCRISState *env;
a825e703 3018 int i;
8170028d
TS		 3019
3020 env = qemu_mallocz(sizeof(CPUCRISState));
3021 if (!env)
3022 return NULL;
3023 cpu_exec_init(env);
05ba7d5f
EI		 3024
3025 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
3026 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3027#if TARGET_LONG_BITS > HOST_LONG_BITS
3028 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3029 TCG_AREG0, offsetof(CPUState, t0), "T0");
3030 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3031 TCG_AREG0, offsetof(CPUState, t1), "T1");
3032#else
3033 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3034 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3035#endif
3036
a825e703
EI		 3037 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3038 offsetof(CPUState, cc_src), "cc_src");
3039 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3040 offsetof(CPUState, cc_dest),
3041 "cc_dest");
3042 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3043 offsetof(CPUState, cc_result),
3044 "cc_result");
3045 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3046 offsetof(CPUState, cc_op), "cc_op");
3047 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3048 offsetof(CPUState, cc_size),
3049 "cc_size");
3050 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3051 offsetof(CPUState, cc_mask),
3052 "cc_mask");
3053
b41f7df0
EI		 3054 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3055 offsetof(CPUState, pc),
3056 "pc");
3057 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3058 offsetof(CPUState, btarget),
3059 "btarget");
3060
a825e703
EI		 3061 for (i = 0; i < 16; i++) {
3062 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3063 offsetof(CPUState, regs[i]),
3064 regnames[i]);
3065 }
3066 for (i = 0; i < 16; i++) {
3067 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3068 offsetof(CPUState, pregs[i]),
3069 pregnames[i]);
3070 }
3071
dceaf394 3072 TCG_HELPER(helper_raise_exception);
b41f7df0
EI		 3073 TCG_HELPER(helper_store);
3074 TCG_HELPER(helper_dump);
3075 TCG_HELPER(helper_dummy);
3076
dceaf394
EI		 3077 TCG_HELPER(helper_tlb_flush);
3078 TCG_HELPER(helper_movl_sreg_reg);
3079 TCG_HELPER(helper_movl_reg_sreg);
3080 TCG_HELPER(helper_rfe);
3081
b41f7df0
EI		 3082 TCG_HELPER(helper_evaluate_flags_muls);
3083 TCG_HELPER(helper_evaluate_flags_mulu);
3084 TCG_HELPER(helper_evaluate_flags_mcp);
3085 TCG_HELPER(helper_evaluate_flags_alu_4);
3086 TCG_HELPER(helper_evaluate_flags_move_4);
3087 TCG_HELPER(helper_evaluate_flags_move_2);
3088 TCG_HELPER(helper_evaluate_flags);
3089
8170028d
TS		 3090 cpu_reset(env);
3091 return env;
3092}
3093
3094void cpu_reset (CPUCRISState *env)
3095{
3096 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3097 tlb_flush(env, 1);
b41f7df0
EI		 3098
3099#if defined(CONFIG_USER_ONLY)
3100 /* start in user mode with interrupts enabled. */
3101 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3102#else
3103 env->pregs[PR_CCS] = 0;
3104#endif
8170028d 3105}
d2856f1a
AJ		 3106
3107void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3108 unsigned long searched_pc, int pc_pos, void *puc)
3109{
17ac9754 3110 env->pc = gen_opc_pc[pc_pos];
d2856f1a 3111}
Qemu copy for testing