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8170028d TS |
1 | /* |
2 | * CRIS emulation for qemu: main translation routines. | |
3 | * | |
05ba7d5f | 4 | * Copyright (c) 2008 AXIS Communications AB |
8170028d TS |
5 | * Written by Edgar E. Iglesias. |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
b41f7df0 EI |
22 | /* |
23 | * FIXME: | |
24 | * The condition code translation is in desperate need of attention. It's slow | |
25 | * and for system simulation it seems buggy. It sucks. | |
26 | */ | |
27 | ||
8170028d TS |
28 | #include <stdarg.h> |
29 | #include <stdlib.h> | |
30 | #include <stdio.h> | |
31 | #include <string.h> | |
32 | #include <inttypes.h> | |
33 | #include <assert.h> | |
34 | ||
35 | #include "cpu.h" | |
36 | #include "exec-all.h" | |
37 | #include "disas.h" | |
57fec1fe | 38 | #include "tcg-op.h" |
05ba7d5f | 39 | #include "helper.h" |
8170028d | 40 | #include "crisv32-decode.h" |
ca10f867 | 41 | #include "qemu-common.h" |
8170028d TS |
42 | |
43 | #define CRIS_STATS 0 | |
44 | #if CRIS_STATS | |
45 | #define STATS(x) x | |
46 | #else | |
47 | #define STATS(x) | |
48 | #endif | |
49 | ||
50 | #define DISAS_CRIS 0 | |
51 | #if DISAS_CRIS | |
52 | #define DIS(x) x | |
53 | #else | |
54 | #define DIS(x) | |
55 | #endif | |
56 | ||
b41f7df0 | 57 | #define D(x) |
8170028d TS |
58 | #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) |
59 | #define BUG_ON(x) ({if (x) BUG();}) | |
60 | ||
4f400ab5 EI |
61 | #define DISAS_SWI 5 |
62 | ||
8170028d TS |
63 | /* Used by the decoder. */ |
64 | #define EXTRACT_FIELD(src, start, end) \ | |
65 | (((src) >> start) & ((1 << (end - start + 1)) - 1)) | |
66 | ||
67 | #define CC_MASK_NZ 0xc | |
68 | #define CC_MASK_NZV 0xe | |
69 | #define CC_MASK_NZVC 0xf | |
70 | #define CC_MASK_RNZV 0x10e | |
71 | ||
a825e703 EI |
72 | TCGv cpu_env; |
73 | TCGv cpu_T[2]; | |
74 | TCGv cpu_R[16]; | |
75 | TCGv cpu_PR[16]; | |
76 | TCGv cc_src; | |
77 | TCGv cc_dest; | |
78 | TCGv cc_result; | |
79 | TCGv cc_op; | |
80 | TCGv cc_size; | |
81 | TCGv cc_mask; | |
05ba7d5f | 82 | |
b41f7df0 EI |
83 | TCGv env_btarget; |
84 | TCGv env_pc; | |
85 | ||
8170028d TS |
86 | /* This is the state at translation time. */ |
87 | typedef struct DisasContext { | |
88 | CPUState *env; | |
b41f7df0 | 89 | target_ulong pc, ppc; |
8170028d TS |
90 | |
91 | /* Decoder. */ | |
92 | uint32_t ir; | |
93 | uint32_t opcode; | |
94 | unsigned int op1; | |
95 | unsigned int op2; | |
96 | unsigned int zsize, zzsize; | |
97 | unsigned int mode; | |
98 | unsigned int postinc; | |
99 | ||
8170028d TS |
100 | int update_cc; |
101 | int cc_op; | |
102 | int cc_size; | |
103 | uint32_t cc_mask; | |
b41f7df0 EI |
104 | int flags_live; /* Wether or not $ccs is uptodate. */ |
105 | int flagx_live; /* Wether or not flags_x has the x flag known at | |
106 | translation time. */ | |
8170028d | 107 | int flags_x; |
b41f7df0 | 108 | int clear_x; /* Clear x after this insn? */ |
8170028d | 109 | |
b41f7df0 | 110 | int user; /* user or kernel mode. */ |
8170028d TS |
111 | int is_jmp; |
112 | int dyn_jmp; | |
113 | ||
114 | uint32_t delayed_pc; | |
115 | int delayed_branch; | |
116 | int bcc; | |
117 | uint32_t condlabel; | |
118 | ||
119 | struct TranslationBlock *tb; | |
120 | int singlestep_enabled; | |
121 | } DisasContext; | |
122 | ||
123 | void cris_prepare_jmp (DisasContext *dc, uint32_t dst); | |
124 | static void gen_BUG(DisasContext *dc, char *file, int line) | |
125 | { | |
126 | printf ("BUG: pc=%x %s %d\n", dc->pc, file, line); | |
127 | fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line); | |
128 | cpu_dump_state (dc->env, stdout, fprintf, 0); | |
129 | fflush(NULL); | |
130 | cris_prepare_jmp (dc, 0x70000000 + line); | |
131 | } | |
132 | ||
a825e703 EI |
133 | const char *regnames[] = |
134 | { | |
135 | "$r0", "$r1", "$r2", "$r3", | |
136 | "$r4", "$r5", "$r6", "$r7", | |
137 | "$r8", "$r9", "$r10", "$r11", | |
138 | "$r12", "$r13", "$sp", "$acr", | |
139 | }; | |
140 | const char *pregnames[] = | |
141 | { | |
142 | "$bz", "$vr", "$pid", "$srs", | |
143 | "$wz", "$exs", "$eda", "$mof", | |
144 | "$dz", "$ebp", "$erp", "$srp", | |
145 | "$nrp", "$ccs", "$usp", "$spc", | |
146 | }; | |
147 | ||
05ba7d5f EI |
148 | /* We need this table to handle preg-moves with implicit width. */ |
149 | int preg_sizes[] = { | |
150 | 1, /* bz. */ | |
151 | 1, /* vr. */ | |
152 | 4, /* pid. */ | |
153 | 1, /* srs. */ | |
154 | 2, /* wz. */ | |
155 | 4, 4, 4, | |
156 | 4, 4, 4, 4, | |
157 | 4, 4, 4, 4, | |
158 | }; | |
159 | ||
160 | #define t_gen_mov_TN_env(tn, member) \ | |
3157a0a9 | 161 | _t_gen_mov_TN_env((tn), offsetof(CPUState, member)) |
05ba7d5f | 162 | #define t_gen_mov_env_TN(member, tn) \ |
3157a0a9 | 163 | _t_gen_mov_env_TN(offsetof(CPUState, member), (tn)) |
05ba7d5f | 164 | |
b41f7df0 EI |
165 | static inline void t_gen_mov_TN_reg(TCGv tn, int r) |
166 | { | |
167 | if (r < 0 || r > 15) | |
168 | fprintf(stderr, "wrong register read $r%d\n", r); | |
169 | tcg_gen_mov_tl(tn, cpu_R[r]); | |
170 | } | |
171 | static inline void t_gen_mov_reg_TN(int r, TCGv tn) | |
172 | { | |
173 | if (r < 0 || r > 15) | |
174 | fprintf(stderr, "wrong register write $r%d\n", r); | |
175 | tcg_gen_mov_tl(cpu_R[r], tn); | |
176 | } | |
05ba7d5f EI |
177 | |
178 | static inline void _t_gen_mov_TN_env(TCGv tn, int offset) | |
179 | { | |
b41f7df0 EI |
180 | if (offset > sizeof (CPUState)) |
181 | fprintf(stderr, "wrong load from env from off=%d\n", offset); | |
05ba7d5f EI |
182 | tcg_gen_ld_tl(tn, cpu_env, offset); |
183 | } | |
184 | static inline void _t_gen_mov_env_TN(int offset, TCGv tn) | |
185 | { | |
b41f7df0 EI |
186 | if (offset > sizeof (CPUState)) |
187 | fprintf(stderr, "wrong store to env at off=%d\n", offset); | |
05ba7d5f EI |
188 | tcg_gen_st_tl(tn, cpu_env, offset); |
189 | } | |
190 | ||
191 | static inline void t_gen_mov_TN_preg(TCGv tn, int r) | |
192 | { | |
b41f7df0 EI |
193 | if (r < 0 || r > 15) |
194 | fprintf(stderr, "wrong register read $p%d\n", r); | |
05ba7d5f | 195 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) |
3157a0a9 | 196 | tcg_gen_mov_tl(tn, tcg_const_tl(0)); |
05ba7d5f | 197 | else if (r == PR_VR) |
3157a0a9 | 198 | tcg_gen_mov_tl(tn, tcg_const_tl(32)); |
b41f7df0 EI |
199 | else if (r == PR_EXS) { |
200 | printf("read from EXS!\n"); | |
201 | tcg_gen_mov_tl(tn, cpu_PR[r]); | |
202 | } | |
203 | else if (r == PR_EDA) { | |
204 | printf("read from EDA!\n"); | |
205 | tcg_gen_mov_tl(tn, cpu_PR[r]); | |
206 | } | |
05ba7d5f | 207 | else |
a825e703 | 208 | tcg_gen_mov_tl(tn, cpu_PR[r]); |
05ba7d5f EI |
209 | } |
210 | static inline void t_gen_mov_preg_TN(int r, TCGv tn) | |
211 | { | |
b41f7df0 EI |
212 | if (r < 0 || r > 15) |
213 | fprintf(stderr, "wrong register write $p%d\n", r); | |
05ba7d5f EI |
214 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) |
215 | return; | |
b41f7df0 EI |
216 | else if (r == PR_SRS) |
217 | tcg_gen_andi_tl(cpu_PR[r], tn, 3); | |
218 | else { | |
219 | if (r == PR_PID) { | |
220 | tcg_gen_helper_0_0(helper_tlb_flush); | |
221 | } | |
a825e703 | 222 | tcg_gen_mov_tl(cpu_PR[r], tn); |
b41f7df0 | 223 | } |
05ba7d5f EI |
224 | } |
225 | ||
226 | static inline void t_gen_mov_TN_im(TCGv tn, int32_t val) | |
227 | { | |
228 | tcg_gen_movi_tl(tn, val); | |
229 | } | |
230 | ||
231 | static void t_gen_lsl(TCGv d, TCGv a, TCGv b) | |
232 | { | |
233 | int l1; | |
234 | ||
235 | l1 = gen_new_label(); | |
236 | /* Speculative shift. */ | |
237 | tcg_gen_shl_tl(d, a, b); | |
3157a0a9 | 238 | tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1); |
05ba7d5f EI |
239 | /* Clear dst if shift operands were to large. */ |
240 | tcg_gen_movi_tl(d, 0); | |
241 | gen_set_label(l1); | |
242 | } | |
243 | ||
244 | static void t_gen_lsr(TCGv d, TCGv a, TCGv b) | |
245 | { | |
246 | int l1; | |
247 | ||
248 | l1 = gen_new_label(); | |
249 | /* Speculative shift. */ | |
250 | tcg_gen_shr_tl(d, a, b); | |
3157a0a9 | 251 | tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1); |
05ba7d5f EI |
252 | /* Clear dst if shift operands were to large. */ |
253 | tcg_gen_movi_tl(d, 0); | |
254 | gen_set_label(l1); | |
255 | } | |
256 | ||
257 | static void t_gen_asr(TCGv d, TCGv a, TCGv b) | |
258 | { | |
259 | int l1; | |
260 | ||
261 | l1 = gen_new_label(); | |
262 | /* Speculative shift. */ | |
263 | tcg_gen_sar_tl(d, a, b); | |
3157a0a9 | 264 | tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1); |
05ba7d5f | 265 | /* Clear dst if shift operands were to large. */ |
b41f7df0 | 266 | tcg_gen_sar_tl(d, a, tcg_const_tl(30)); |
05ba7d5f EI |
267 | gen_set_label(l1); |
268 | } | |
269 | ||
3157a0a9 EI |
270 | /* 64-bit signed mul, lower result in d and upper in d2. */ |
271 | static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b) | |
272 | { | |
273 | TCGv t0, t1; | |
274 | ||
275 | t0 = tcg_temp_new(TCG_TYPE_I64); | |
276 | t1 = tcg_temp_new(TCG_TYPE_I64); | |
277 | ||
278 | tcg_gen_ext32s_i64(t0, a); | |
279 | tcg_gen_ext32s_i64(t1, b); | |
280 | tcg_gen_mul_i64(t0, t0, t1); | |
281 | ||
282 | tcg_gen_trunc_i64_i32(d, t0); | |
283 | tcg_gen_shri_i64(t0, t0, 32); | |
284 | tcg_gen_trunc_i64_i32(d2, t0); | |
b41f7df0 EI |
285 | |
286 | tcg_gen_discard_i64(t0); | |
287 | tcg_gen_discard_i64(t1); | |
3157a0a9 EI |
288 | } |
289 | ||
290 | /* 64-bit unsigned muls, lower result in d and upper in d2. */ | |
291 | static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) | |
292 | { | |
293 | TCGv t0, t1; | |
294 | ||
295 | t0 = tcg_temp_new(TCG_TYPE_I64); | |
296 | t1 = tcg_temp_new(TCG_TYPE_I64); | |
297 | ||
298 | tcg_gen_extu_i32_i64(t0, a); | |
299 | tcg_gen_extu_i32_i64(t1, b); | |
300 | tcg_gen_mul_i64(t0, t0, t1); | |
301 | ||
302 | tcg_gen_trunc_i64_i32(d, t0); | |
303 | tcg_gen_shri_i64(t0, t0, 32); | |
304 | tcg_gen_trunc_i64_i32(d2, t0); | |
b41f7df0 EI |
305 | |
306 | tcg_gen_discard_i64(t0); | |
307 | tcg_gen_discard_i64(t1); | |
3157a0a9 EI |
308 | } |
309 | ||
d059c172 EI |
310 | /* 32bit branch-free binary search for counting leading zeros. */ |
311 | static void t_gen_lz_i32(TCGv d, TCGv x) | |
312 | { | |
313 | TCGv y, m, n; | |
314 | ||
315 | y = tcg_temp_new(TCG_TYPE_I32); | |
316 | m = tcg_temp_new(TCG_TYPE_I32); | |
317 | n = tcg_temp_new(TCG_TYPE_I32); | |
318 | ||
319 | /* y = -(x >> 16) */ | |
320 | tcg_gen_shri_i32(y, x, 16); | |
321 | tcg_gen_sub_i32(y, tcg_const_i32(0), y); | |
322 | ||
323 | /* m = (y >> 16) & 16 */ | |
324 | tcg_gen_sari_i32(m, y, 16); | |
325 | tcg_gen_andi_i32(m, m, 16); | |
326 | ||
327 | /* n = 16 - m */ | |
328 | tcg_gen_sub_i32(n, tcg_const_i32(16), m); | |
329 | /* x = x >> m */ | |
330 | tcg_gen_shr_i32(x, x, m); | |
331 | ||
332 | /* y = x - 0x100 */ | |
333 | tcg_gen_subi_i32(y, x, 0x100); | |
334 | /* m = (y >> 16) & 8 */ | |
335 | tcg_gen_sari_i32(m, y, 16); | |
336 | tcg_gen_andi_i32(m, m, 8); | |
337 | /* n = n + m */ | |
338 | tcg_gen_add_i32(n, n, m); | |
339 | /* x = x << m */ | |
340 | tcg_gen_shl_i32(x, x, m); | |
341 | ||
342 | /* y = x - 0x1000 */ | |
343 | tcg_gen_subi_i32(y, x, 0x1000); | |
344 | /* m = (y >> 16) & 4 */ | |
345 | tcg_gen_sari_i32(m, y, 16); | |
346 | tcg_gen_andi_i32(m, m, 4); | |
347 | /* n = n + m */ | |
348 | tcg_gen_add_i32(n, n, m); | |
349 | /* x = x << m */ | |
350 | tcg_gen_shl_i32(x, x, m); | |
351 | ||
352 | /* y = x - 0x4000 */ | |
353 | tcg_gen_subi_i32(y, x, 0x4000); | |
354 | /* m = (y >> 16) & 2 */ | |
355 | tcg_gen_sari_i32(m, y, 16); | |
356 | tcg_gen_andi_i32(m, m, 2); | |
357 | /* n = n + m */ | |
358 | tcg_gen_add_i32(n, n, m); | |
359 | /* x = x << m */ | |
360 | tcg_gen_shl_i32(x, x, m); | |
361 | ||
362 | /* y = x >> 14 */ | |
363 | tcg_gen_shri_i32(y, x, 14); | |
364 | /* m = y & ~(y >> 1) */ | |
365 | tcg_gen_sari_i32(m, y, 1); | |
366 | tcg_gen_xori_i32(m, m, 0xffffffff); | |
367 | tcg_gen_and_i32(m, m, y); | |
368 | ||
369 | /* d = n + 2 - m */ | |
370 | tcg_gen_addi_i32(d, n, 2); | |
371 | tcg_gen_sub_i32(d, d, m); | |
372 | ||
373 | tcg_gen_discard_i32(y); | |
374 | tcg_gen_discard_i32(m); | |
375 | tcg_gen_discard_i32(n); | |
376 | } | |
377 | ||
aae6b32a EI |
378 | static void t_gen_cris_dstep(TCGv d, TCGv s) |
379 | { | |
380 | int l1; | |
381 | ||
382 | l1 = gen_new_label(); | |
383 | ||
384 | /* | |
385 | * d <<= 1 | |
386 | * if (d >= s) | |
387 | * d -= s; | |
388 | */ | |
389 | tcg_gen_shli_tl(d, d, 1); | |
390 | tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1); | |
391 | tcg_gen_sub_tl(d, d, s); | |
392 | gen_set_label(l1); | |
393 | } | |
394 | ||
3157a0a9 EI |
395 | /* Extended arithmetics on CRIS. */ |
396 | static inline void t_gen_add_flag(TCGv d, int flag) | |
397 | { | |
398 | TCGv c; | |
399 | ||
400 | c = tcg_temp_new(TCG_TYPE_TL); | |
401 | t_gen_mov_TN_preg(c, PR_CCS); | |
402 | /* Propagate carry into d. */ | |
403 | tcg_gen_andi_tl(c, c, 1 << flag); | |
404 | if (flag) | |
405 | tcg_gen_shri_tl(c, c, flag); | |
406 | tcg_gen_add_tl(d, d, c); | |
b41f7df0 | 407 | tcg_gen_discard_tl(c); |
3157a0a9 EI |
408 | } |
409 | ||
410 | static inline void t_gen_addx_carry(TCGv d) | |
411 | { | |
412 | TCGv x, c; | |
413 | ||
414 | x = tcg_temp_new(TCG_TYPE_TL); | |
415 | c = tcg_temp_new(TCG_TYPE_TL); | |
416 | t_gen_mov_TN_preg(x, PR_CCS); | |
417 | tcg_gen_mov_tl(c, x); | |
418 | ||
419 | /* Propagate carry into d if X is set. Branch free. */ | |
420 | tcg_gen_andi_tl(c, c, C_FLAG); | |
421 | tcg_gen_andi_tl(x, x, X_FLAG); | |
422 | tcg_gen_shri_tl(x, x, 4); | |
423 | ||
424 | tcg_gen_and_tl(x, x, c); | |
425 | tcg_gen_add_tl(d, d, x); | |
b41f7df0 EI |
426 | tcg_gen_discard_tl(x); |
427 | tcg_gen_discard_tl(c); | |
3157a0a9 EI |
428 | } |
429 | ||
430 | static inline void t_gen_subx_carry(TCGv d) | |
431 | { | |
432 | TCGv x, c; | |
433 | ||
434 | x = tcg_temp_new(TCG_TYPE_TL); | |
435 | c = tcg_temp_new(TCG_TYPE_TL); | |
436 | t_gen_mov_TN_preg(x, PR_CCS); | |
437 | tcg_gen_mov_tl(c, x); | |
438 | ||
439 | /* Propagate carry into d if X is set. Branch free. */ | |
440 | tcg_gen_andi_tl(c, c, C_FLAG); | |
441 | tcg_gen_andi_tl(x, x, X_FLAG); | |
442 | tcg_gen_shri_tl(x, x, 4); | |
443 | ||
444 | tcg_gen_and_tl(x, x, c); | |
445 | tcg_gen_sub_tl(d, d, x); | |
b41f7df0 EI |
446 | tcg_gen_discard_tl(x); |
447 | tcg_gen_discard_tl(c); | |
3157a0a9 EI |
448 | } |
449 | ||
450 | /* Swap the two bytes within each half word of the s operand. | |
451 | T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */ | |
452 | static inline void t_gen_swapb(TCGv d, TCGv s) | |
453 | { | |
454 | TCGv t, org_s; | |
455 | ||
456 | t = tcg_temp_new(TCG_TYPE_TL); | |
457 | org_s = tcg_temp_new(TCG_TYPE_TL); | |
458 | ||
459 | /* d and s may refer to the same object. */ | |
460 | tcg_gen_mov_tl(org_s, s); | |
461 | tcg_gen_shli_tl(t, org_s, 8); | |
462 | tcg_gen_andi_tl(d, t, 0xff00ff00); | |
463 | tcg_gen_shri_tl(t, org_s, 8); | |
464 | tcg_gen_andi_tl(t, t, 0x00ff00ff); | |
465 | tcg_gen_or_tl(d, d, t); | |
b41f7df0 EI |
466 | tcg_gen_discard_tl(t); |
467 | tcg_gen_discard_tl(org_s); | |
3157a0a9 EI |
468 | } |
469 | ||
470 | /* Swap the halfwords of the s operand. */ | |
471 | static inline void t_gen_swapw(TCGv d, TCGv s) | |
472 | { | |
473 | TCGv t; | |
474 | /* d and s refer the same object. */ | |
475 | t = tcg_temp_new(TCG_TYPE_TL); | |
476 | tcg_gen_mov_tl(t, s); | |
477 | tcg_gen_shli_tl(d, t, 16); | |
478 | tcg_gen_shri_tl(t, t, 16); | |
479 | tcg_gen_or_tl(d, d, t); | |
b41f7df0 | 480 | tcg_gen_discard_tl(t); |
3157a0a9 EI |
481 | } |
482 | ||
483 | /* Reverse the within each byte. | |
484 | T0 = (((T0 << 7) & 0x80808080) | | |
485 | ((T0 << 5) & 0x40404040) | | |
486 | ((T0 << 3) & 0x20202020) | | |
487 | ((T0 << 1) & 0x10101010) | | |
488 | ((T0 >> 1) & 0x08080808) | | |
489 | ((T0 >> 3) & 0x04040404) | | |
490 | ((T0 >> 5) & 0x02020202) | | |
491 | ((T0 >> 7) & 0x01010101)); | |
492 | */ | |
493 | static inline void t_gen_swapr(TCGv d, TCGv s) | |
494 | { | |
495 | struct { | |
496 | int shift; /* LSL when positive, LSR when negative. */ | |
497 | uint32_t mask; | |
498 | } bitrev [] = { | |
499 | {7, 0x80808080}, | |
500 | {5, 0x40404040}, | |
501 | {3, 0x20202020}, | |
502 | {1, 0x10101010}, | |
503 | {-1, 0x08080808}, | |
504 | {-3, 0x04040404}, | |
505 | {-5, 0x02020202}, | |
506 | {-7, 0x01010101} | |
507 | }; | |
508 | int i; | |
509 | TCGv t, org_s; | |
510 | ||
511 | /* d and s refer the same object. */ | |
512 | t = tcg_temp_new(TCG_TYPE_TL); | |
513 | org_s = tcg_temp_new(TCG_TYPE_TL); | |
514 | tcg_gen_mov_tl(org_s, s); | |
515 | ||
516 | tcg_gen_shli_tl(t, org_s, bitrev[0].shift); | |
517 | tcg_gen_andi_tl(d, t, bitrev[0].mask); | |
518 | for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) { | |
519 | if (bitrev[i].shift >= 0) { | |
520 | tcg_gen_shli_tl(t, org_s, bitrev[i].shift); | |
521 | } else { | |
522 | tcg_gen_shri_tl(t, org_s, -bitrev[i].shift); | |
523 | } | |
524 | tcg_gen_andi_tl(t, t, bitrev[i].mask); | |
525 | tcg_gen_or_tl(d, d, t); | |
526 | } | |
b41f7df0 EI |
527 | tcg_gen_discard_tl(t); |
528 | tcg_gen_discard_tl(org_s); | |
3157a0a9 EI |
529 | } |
530 | ||
8170028d TS |
531 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
532 | { | |
533 | TranslationBlock *tb; | |
534 | tb = dc->tb; | |
535 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
05ba7d5f | 536 | tcg_gen_goto_tb(n); |
50cfa95c | 537 | tcg_gen_movi_tl(env_pc, dest); |
05ba7d5f | 538 | tcg_gen_exit_tb((long)tb + n); |
8170028d | 539 | } else { |
50cfa95c | 540 | tcg_gen_mov_tl(env_pc, cpu_T[0]); |
05ba7d5f | 541 | tcg_gen_exit_tb(0); |
8170028d | 542 | } |
8170028d TS |
543 | } |
544 | ||
545 | /* Sign extend at translation time. */ | |
546 | static int sign_extend(unsigned int val, unsigned int width) | |
547 | { | |
548 | int sval; | |
549 | ||
550 | /* LSL. */ | |
551 | val <<= 31 - width; | |
552 | sval = val; | |
553 | /* ASR. */ | |
554 | sval >>= 31 - width; | |
555 | return sval; | |
556 | } | |
557 | ||
05ba7d5f EI |
558 | static inline void cris_clear_x_flag(DisasContext *dc) |
559 | { | |
b41f7df0 EI |
560 | if (!dc->flagx_live |
561 | || (dc->flagx_live && dc->flags_x) | |
562 | || dc->cc_op != CC_OP_FLAGS) | |
563 | tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG); | |
564 | dc->flagx_live = 1; | |
565 | dc->flags_x = 0; | |
05ba7d5f EI |
566 | } |
567 | ||
8170028d TS |
568 | static void cris_evaluate_flags(DisasContext *dc) |
569 | { | |
570 | if (!dc->flags_live) { | |
b41f7df0 EI |
571 | tcg_gen_movi_tl(cc_op, dc->cc_op); |
572 | tcg_gen_movi_tl(cc_size, dc->cc_size); | |
573 | tcg_gen_movi_tl(cc_mask, dc->cc_mask); | |
574 | ||
8170028d TS |
575 | switch (dc->cc_op) |
576 | { | |
577 | case CC_OP_MCP: | |
b41f7df0 | 578 | tcg_gen_helper_0_0(helper_evaluate_flags_mcp); |
8170028d TS |
579 | break; |
580 | case CC_OP_MULS: | |
b41f7df0 | 581 | tcg_gen_helper_0_0(helper_evaluate_flags_muls); |
8170028d TS |
582 | break; |
583 | case CC_OP_MULU: | |
b41f7df0 | 584 | tcg_gen_helper_0_0(helper_evaluate_flags_mulu); |
8170028d TS |
585 | break; |
586 | case CC_OP_MOVE: | |
587 | switch (dc->cc_size) | |
588 | { | |
589 | case 4: | |
b41f7df0 | 590 | tcg_gen_helper_0_0(helper_evaluate_flags_move_4); |
8170028d TS |
591 | break; |
592 | case 2: | |
b41f7df0 | 593 | tcg_gen_helper_0_0(helper_evaluate_flags_move_2); |
8170028d TS |
594 | break; |
595 | default: | |
b41f7df0 | 596 | tcg_gen_helper_0_0(helper_evaluate_flags); |
8170028d TS |
597 | break; |
598 | } | |
599 | break; | |
b41f7df0 EI |
600 | case CC_OP_FLAGS: |
601 | /* live. */ | |
602 | break; | |
8170028d TS |
603 | default: |
604 | { | |
605 | switch (dc->cc_size) | |
606 | { | |
607 | case 4: | |
b41f7df0 | 608 | tcg_gen_helper_0_0(helper_evaluate_flags_alu_4); |
8170028d TS |
609 | break; |
610 | default: | |
b41f7df0 | 611 | tcg_gen_helper_0_0(helper_evaluate_flags); |
8170028d TS |
612 | break; |
613 | } | |
614 | } | |
615 | break; | |
616 | } | |
617 | dc->flags_live = 1; | |
618 | } | |
619 | } | |
620 | ||
621 | static void cris_cc_mask(DisasContext *dc, unsigned int mask) | |
622 | { | |
623 | uint32_t ovl; | |
624 | ||
fd56059f AZ |
625 | /* Check if we need to evaluate the condition codes due to |
626 | CC overlaying. */ | |
8170028d TS |
627 | ovl = (dc->cc_mask ^ mask) & ~mask; |
628 | if (ovl) { | |
629 | /* TODO: optimize this case. It trigs all the time. */ | |
630 | cris_evaluate_flags (dc); | |
631 | } | |
632 | dc->cc_mask = mask; | |
8170028d | 633 | dc->update_cc = 1; |
a825e703 | 634 | |
8170028d TS |
635 | if (mask == 0) |
636 | dc->update_cc = 0; | |
a825e703 | 637 | else |
8170028d | 638 | dc->flags_live = 0; |
8170028d TS |
639 | } |
640 | ||
b41f7df0 | 641 | static void cris_update_cc_op(DisasContext *dc, int op, int size) |
8170028d TS |
642 | { |
643 | dc->cc_op = op; | |
8170028d | 644 | dc->cc_size = size; |
b41f7df0 | 645 | dc->flags_live = 0; |
8170028d TS |
646 | } |
647 | ||
648 | /* op is the operation. | |
649 | T0, T1 are the operands. | |
650 | dst is the destination reg. | |
651 | */ | |
652 | static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size) | |
653 | { | |
654 | int writeback = 1; | |
655 | if (dc->update_cc) { | |
b41f7df0 | 656 | cris_update_cc_op(dc, op, size); |
a825e703 | 657 | tcg_gen_mov_tl(cc_dest, cpu_T[0]); |
3157a0a9 EI |
658 | |
659 | /* FIXME: This shouldn't be needed. But we don't pass the | |
660 | tests without it. Investigate. */ | |
661 | t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live)); | |
662 | t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x)); | |
8170028d TS |
663 | } |
664 | ||
665 | /* Emit the ALU insns. */ | |
666 | switch (op) | |
667 | { | |
668 | case CC_OP_ADD: | |
05ba7d5f | 669 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d | 670 | /* Extended arithmetics. */ |
3157a0a9 | 671 | t_gen_addx_carry(cpu_T[0]); |
8170028d TS |
672 | break; |
673 | case CC_OP_ADDC: | |
05ba7d5f | 674 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3157a0a9 | 675 | t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */ |
8170028d TS |
676 | break; |
677 | case CC_OP_MCP: | |
05ba7d5f | 678 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3157a0a9 | 679 | t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */ |
8170028d TS |
680 | break; |
681 | case CC_OP_SUB: | |
3157a0a9 | 682 | tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]); |
05ba7d5f | 683 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3157a0a9 | 684 | tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]); |
8170028d | 685 | /* CRIS flag evaluation needs ~src. */ |
3157a0a9 | 686 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
8170028d TS |
687 | |
688 | /* Extended arithmetics. */ | |
3157a0a9 | 689 | t_gen_subx_carry(cpu_T[0]); |
8170028d TS |
690 | break; |
691 | case CC_OP_MOVE: | |
05ba7d5f | 692 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); |
8170028d TS |
693 | break; |
694 | case CC_OP_OR: | |
05ba7d5f | 695 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d TS |
696 | break; |
697 | case CC_OP_AND: | |
05ba7d5f | 698 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d TS |
699 | break; |
700 | case CC_OP_XOR: | |
05ba7d5f | 701 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d TS |
702 | break; |
703 | case CC_OP_LSL: | |
05ba7d5f | 704 | t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d TS |
705 | break; |
706 | case CC_OP_LSR: | |
05ba7d5f | 707 | t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d TS |
708 | break; |
709 | case CC_OP_ASR: | |
05ba7d5f | 710 | t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]); |
8170028d TS |
711 | break; |
712 | case CC_OP_NEG: | |
3157a0a9 EI |
713 | /* Hopefully the TCG backend recognizes this pattern |
714 | and makes a real neg out of it. */ | |
715 | tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]); | |
8170028d | 716 | /* Extended arithmetics. */ |
3157a0a9 | 717 | t_gen_subx_carry(cpu_T[0]); |
8170028d TS |
718 | break; |
719 | case CC_OP_LZ: | |
d059c172 | 720 | t_gen_lz_i32(cpu_T[0], cpu_T[1]); |
8170028d TS |
721 | break; |
722 | case CC_OP_BTST: | |
723 | gen_op_btst_T0_T1(); | |
724 | writeback = 0; | |
725 | break; | |
726 | case CC_OP_MULS: | |
3157a0a9 EI |
727 | { |
728 | TCGv mof; | |
729 | mof = tcg_temp_new(TCG_TYPE_TL); | |
730 | t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]); | |
731 | t_gen_mov_preg_TN(PR_MOF, mof); | |
b41f7df0 | 732 | tcg_gen_discard_tl(mof); |
3157a0a9 EI |
733 | } |
734 | break; | |
8170028d | 735 | case CC_OP_MULU: |
3157a0a9 EI |
736 | { |
737 | TCGv mof; | |
738 | mof = tcg_temp_new(TCG_TYPE_TL); | |
739 | t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]); | |
740 | t_gen_mov_preg_TN(PR_MOF, mof); | |
b41f7df0 | 741 | tcg_gen_discard_tl(mof); |
3157a0a9 EI |
742 | } |
743 | break; | |
8170028d | 744 | case CC_OP_DSTEP: |
aae6b32a | 745 | t_gen_cris_dstep(cpu_T[0], cpu_T[1]); |
8170028d TS |
746 | break; |
747 | case CC_OP_BOUND: | |
3157a0a9 EI |
748 | { |
749 | int l1; | |
750 | l1 = gen_new_label(); | |
751 | tcg_gen_brcond_tl(TCG_COND_LEU, | |
752 | cpu_T[0], cpu_T[1], l1); | |
753 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
754 | gen_set_label(l1); | |
755 | } | |
756 | break; | |
8170028d | 757 | case CC_OP_CMP: |
3157a0a9 | 758 | tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]); |
05ba7d5f EI |
759 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
760 | /* CRIS flag evaluation needs ~src. */ | |
3157a0a9 | 761 | tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]); |
8170028d | 762 | /* CRIS flag evaluation needs ~src. */ |
3157a0a9 | 763 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
8170028d TS |
764 | |
765 | /* Extended arithmetics. */ | |
3157a0a9 | 766 | t_gen_subx_carry(cpu_T[0]); |
8170028d TS |
767 | writeback = 0; |
768 | break; | |
769 | default: | |
770 | fprintf (logfile, "illegal ALU op.\n"); | |
771 | BUG(); | |
772 | break; | |
773 | } | |
774 | ||
775 | if (dc->update_cc) | |
a825e703 | 776 | tcg_gen_mov_tl(cc_src, cpu_T[1]); |
8170028d TS |
777 | |
778 | if (size == 1) | |
05ba7d5f | 779 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); |
8170028d | 780 | else if (size == 2) |
05ba7d5f EI |
781 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
782 | ||
8170028d TS |
783 | /* Writeback. */ |
784 | if (writeback) { | |
785 | if (size == 4) | |
05ba7d5f | 786 | t_gen_mov_reg_TN(rd, cpu_T[0]); |
8170028d | 787 | else { |
05ba7d5f EI |
788 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
789 | t_gen_mov_TN_reg(cpu_T[0], rd); | |
8170028d | 790 | if (size == 1) |
05ba7d5f | 791 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff); |
8170028d | 792 | else |
05ba7d5f EI |
793 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff); |
794 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
795 | t_gen_mov_reg_TN(rd, cpu_T[0]); | |
796 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
8170028d TS |
797 | } |
798 | } | |
799 | if (dc->update_cc) | |
a825e703 | 800 | tcg_gen_mov_tl(cc_result, cpu_T[0]); |
8170028d TS |
801 | |
802 | { | |
803 | /* TODO: Optimize this. */ | |
804 | if (!dc->flagx_live) | |
805 | cris_evaluate_flags(dc); | |
806 | } | |
807 | } | |
808 | ||
809 | static int arith_cc(DisasContext *dc) | |
810 | { | |
811 | if (dc->update_cc) { | |
812 | switch (dc->cc_op) { | |
813 | case CC_OP_ADD: return 1; | |
814 | case CC_OP_SUB: return 1; | |
815 | case CC_OP_LSL: return 1; | |
816 | case CC_OP_LSR: return 1; | |
817 | case CC_OP_ASR: return 1; | |
818 | case CC_OP_CMP: return 1; | |
819 | default: | |
820 | return 0; | |
821 | } | |
822 | } | |
823 | return 0; | |
824 | } | |
825 | ||
826 | static void gen_tst_cc (DisasContext *dc, int cond) | |
827 | { | |
828 | int arith_opt; | |
829 | ||
830 | /* TODO: optimize more condition codes. */ | |
831 | arith_opt = arith_cc(dc) && !dc->flags_live; | |
832 | switch (cond) { | |
833 | case CC_EQ: | |
834 | if (arith_opt) | |
835 | gen_op_tst_cc_eq_fast (); | |
836 | else { | |
837 | cris_evaluate_flags(dc); | |
838 | gen_op_tst_cc_eq (); | |
839 | } | |
840 | break; | |
841 | case CC_NE: | |
842 | if (arith_opt) | |
843 | gen_op_tst_cc_ne_fast (); | |
844 | else { | |
845 | cris_evaluate_flags(dc); | |
846 | gen_op_tst_cc_ne (); | |
847 | } | |
848 | break; | |
849 | case CC_CS: | |
850 | cris_evaluate_flags(dc); | |
851 | gen_op_tst_cc_cs (); | |
852 | break; | |
853 | case CC_CC: | |
854 | cris_evaluate_flags(dc); | |
855 | gen_op_tst_cc_cc (); | |
856 | break; | |
857 | case CC_VS: | |
858 | cris_evaluate_flags(dc); | |
859 | gen_op_tst_cc_vs (); | |
860 | break; | |
861 | case CC_VC: | |
862 | cris_evaluate_flags(dc); | |
863 | gen_op_tst_cc_vc (); | |
864 | break; | |
865 | case CC_PL: | |
866 | if (arith_opt) | |
867 | gen_op_tst_cc_pl_fast (); | |
868 | else { | |
869 | cris_evaluate_flags(dc); | |
870 | gen_op_tst_cc_pl (); | |
871 | } | |
872 | break; | |
873 | case CC_MI: | |
874 | if (arith_opt) | |
875 | gen_op_tst_cc_mi_fast (); | |
876 | else { | |
877 | cris_evaluate_flags(dc); | |
878 | gen_op_tst_cc_mi (); | |
879 | } | |
880 | break; | |
881 | case CC_LS: | |
882 | cris_evaluate_flags(dc); | |
883 | gen_op_tst_cc_ls (); | |
884 | break; | |
885 | case CC_HI: | |
886 | cris_evaluate_flags(dc); | |
887 | gen_op_tst_cc_hi (); | |
888 | break; | |
889 | case CC_GE: | |
890 | cris_evaluate_flags(dc); | |
891 | gen_op_tst_cc_ge (); | |
892 | break; | |
893 | case CC_LT: | |
894 | cris_evaluate_flags(dc); | |
895 | gen_op_tst_cc_lt (); | |
896 | break; | |
897 | case CC_GT: | |
898 | cris_evaluate_flags(dc); | |
899 | gen_op_tst_cc_gt (); | |
900 | break; | |
901 | case CC_LE: | |
902 | cris_evaluate_flags(dc); | |
903 | gen_op_tst_cc_le (); | |
904 | break; | |
905 | case CC_P: | |
906 | cris_evaluate_flags(dc); | |
907 | gen_op_tst_cc_p (); | |
908 | break; | |
909 | case CC_A: | |
910 | cris_evaluate_flags(dc); | |
911 | gen_op_movl_T0_im (1); | |
912 | break; | |
913 | default: | |
914 | BUG(); | |
915 | break; | |
916 | }; | |
917 | } | |
918 | ||
919 | static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond) | |
920 | { | |
921 | /* This helps us re-schedule the micro-code to insns in delay-slots | |
922 | before the actual jump. */ | |
923 | dc->delayed_branch = 2; | |
924 | dc->delayed_pc = dc->pc + offset; | |
925 | dc->bcc = cond; | |
926 | if (cond != CC_A) | |
927 | { | |
928 | gen_tst_cc (dc, cond); | |
929 | gen_op_evaluate_bcc (); | |
930 | } | |
b41f7df0 | 931 | tcg_gen_movi_tl(env_btarget, dc->delayed_pc); |
8170028d TS |
932 | } |
933 | ||
b41f7df0 | 934 | |
8170028d TS |
935 | /* Dynamic jumps, when the dest is in a live reg for example. */ |
936 | void cris_prepare_dyn_jmp (DisasContext *dc) | |
937 | { | |
938 | /* This helps us re-schedule the micro-code to insns in delay-slots | |
939 | before the actual jump. */ | |
940 | dc->delayed_branch = 2; | |
941 | dc->dyn_jmp = 1; | |
942 | dc->bcc = CC_A; | |
943 | } | |
944 | ||
945 | void cris_prepare_jmp (DisasContext *dc, uint32_t dst) | |
946 | { | |
947 | /* This helps us re-schedule the micro-code to insns in delay-slots | |
948 | before the actual jump. */ | |
949 | dc->delayed_branch = 2; | |
950 | dc->delayed_pc = dst; | |
951 | dc->dyn_jmp = 0; | |
952 | dc->bcc = CC_A; | |
953 | } | |
954 | ||
b41f7df0 EI |
955 | void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
956 | unsigned int size, int sign) | |
8170028d | 957 | { |
b41f7df0 EI |
958 | int mem_index = cpu_mmu_index(dc->env); |
959 | ||
960 | /* FIXME: qemu_ld does not act as a barrier? */ | |
961 | tcg_gen_helper_0_0(helper_dummy); | |
962 | cris_evaluate_flags(dc); | |
8170028d TS |
963 | if (size == 1) { |
964 | if (sign) | |
b41f7df0 | 965 | tcg_gen_qemu_ld8s(dst, addr, mem_index); |
8170028d | 966 | else |
b41f7df0 | 967 | tcg_gen_qemu_ld8u(dst, addr, mem_index); |
8170028d TS |
968 | } |
969 | else if (size == 2) { | |
970 | if (sign) | |
b41f7df0 | 971 | tcg_gen_qemu_ld16s(dst, addr, mem_index); |
8170028d | 972 | else |
b41f7df0 | 973 | tcg_gen_qemu_ld16u(dst, addr, mem_index); |
8170028d TS |
974 | } |
975 | else { | |
b41f7df0 | 976 | tcg_gen_qemu_ld32s(dst, addr, mem_index); |
8170028d TS |
977 | } |
978 | } | |
979 | ||
980 | void gen_store_T0_T1 (DisasContext *dc, unsigned int size) | |
981 | { | |
b41f7df0 EI |
982 | int mem_index = cpu_mmu_index(dc->env); |
983 | ||
984 | /* FIXME: qemu_st does not act as a barrier? */ | |
985 | tcg_gen_helper_0_0(helper_dummy); | |
986 | cris_evaluate_flags(dc); | |
987 | ||
8170028d | 988 | /* Remember, operands are flipped. CRIS has reversed order. */ |
b41f7df0 EI |
989 | if (size == 1) |
990 | tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index); | |
991 | else if (size == 2) | |
992 | tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index); | |
8170028d | 993 | else |
b41f7df0 | 994 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index); |
8170028d TS |
995 | } |
996 | ||
05ba7d5f | 997 | static inline void t_gen_sext(TCGv d, TCGv s, int size) |
8170028d TS |
998 | { |
999 | if (size == 1) | |
05ba7d5f | 1000 | tcg_gen_ext8s_i32(d, s); |
8170028d | 1001 | else if (size == 2) |
05ba7d5f | 1002 | tcg_gen_ext16s_i32(d, s); |
50cfa95c EI |
1003 | else |
1004 | tcg_gen_mov_tl(d, s); | |
8170028d TS |
1005 | } |
1006 | ||
05ba7d5f | 1007 | static inline void t_gen_zext(TCGv d, TCGv s, int size) |
8170028d | 1008 | { |
05ba7d5f | 1009 | /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */ |
8170028d | 1010 | if (size == 1) |
05ba7d5f | 1011 | tcg_gen_andi_i32(d, s, 0xff); |
8170028d | 1012 | else if (size == 2) |
05ba7d5f | 1013 | tcg_gen_andi_i32(d, s, 0xffff); |
50cfa95c EI |
1014 | else |
1015 | tcg_gen_mov_tl(d, s); | |
8170028d TS |
1016 | } |
1017 | ||
1018 | #if DISAS_CRIS | |
1019 | static char memsize_char(int size) | |
1020 | { | |
1021 | switch (size) | |
1022 | { | |
1023 | case 1: return 'b'; break; | |
1024 | case 2: return 'w'; break; | |
1025 | case 4: return 'd'; break; | |
1026 | default: | |
1027 | return 'x'; | |
1028 | break; | |
1029 | } | |
1030 | } | |
1031 | #endif | |
1032 | ||
1033 | static unsigned int memsize_z(DisasContext *dc) | |
1034 | { | |
1035 | return dc->zsize + 1; | |
1036 | } | |
1037 | ||
1038 | static unsigned int memsize_zz(DisasContext *dc) | |
1039 | { | |
1040 | switch (dc->zzsize) | |
1041 | { | |
1042 | case 0: return 1; | |
1043 | case 1: return 2; | |
1044 | default: | |
1045 | return 4; | |
1046 | } | |
1047 | } | |
1048 | ||
c7d05695 | 1049 | static inline void do_postinc (DisasContext *dc, int size) |
8170028d | 1050 | { |
c7d05695 EI |
1051 | if (dc->postinc) |
1052 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size); | |
8170028d TS |
1053 | } |
1054 | ||
1055 | ||
1056 | static void dec_prep_move_r(DisasContext *dc, int rs, int rd, | |
1057 | int size, int s_ext) | |
1058 | { | |
8170028d | 1059 | if (s_ext) |
50cfa95c | 1060 | t_gen_sext(cpu_T[1], cpu_R[rs], size); |
8170028d | 1061 | else |
50cfa95c | 1062 | t_gen_zext(cpu_T[1], cpu_R[rs], size); |
8170028d TS |
1063 | } |
1064 | ||
1065 | /* Prepare T0 and T1 for a register alu operation. | |
1066 | s_ext decides if the operand1 should be sign-extended or zero-extended when | |
1067 | needed. */ | |
1068 | static void dec_prep_alu_r(DisasContext *dc, int rs, int rd, | |
1069 | int size, int s_ext) | |
1070 | { | |
1071 | dec_prep_move_r(dc, rs, rd, size, s_ext); | |
1072 | ||
8170028d | 1073 | if (s_ext) |
50cfa95c | 1074 | t_gen_sext(cpu_T[0], cpu_R[rd], size); |
8170028d | 1075 | else |
50cfa95c | 1076 | t_gen_zext(cpu_T[0], cpu_R[rd], size); |
8170028d TS |
1077 | } |
1078 | ||
1079 | /* Prepare T0 and T1 for a memory + alu operation. | |
1080 | s_ext decides if the operand1 should be sign-extended or zero-extended when | |
1081 | needed. */ | |
1082 | static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize) | |
1083 | { | |
1084 | unsigned int rs, rd; | |
1085 | uint32_t imm; | |
1086 | int is_imm; | |
1087 | int insn_len = 2; | |
1088 | ||
1089 | rs = dc->op1; | |
1090 | rd = dc->op2; | |
1091 | is_imm = rs == 15 && dc->postinc; | |
1092 | ||
1093 | /* Load [$rs] onto T1. */ | |
1094 | if (is_imm) { | |
1095 | insn_len = 2 + memsize; | |
1096 | if (memsize == 1) | |
1097 | insn_len++; | |
1098 | ||
1099 | imm = ldl_code(dc->pc + 2); | |
1100 | if (memsize != 4) { | |
1101 | if (s_ext) { | |
1102 | imm = sign_extend(imm, (memsize * 8) - 1); | |
1103 | } else { | |
1104 | if (memsize == 1) | |
1105 | imm &= 0xff; | |
1106 | else | |
1107 | imm &= 0xffff; | |
1108 | } | |
1109 | } | |
1110 | DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n", | |
1111 | imm, rd, s_ext, memsize)); | |
05ba7d5f | 1112 | tcg_gen_movi_tl(cpu_T[1], imm); |
8170028d TS |
1113 | dc->postinc = 0; |
1114 | } else { | |
b41f7df0 | 1115 | gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0); |
8170028d | 1116 | if (s_ext) |
05ba7d5f | 1117 | t_gen_sext(cpu_T[1], cpu_T[1], memsize); |
8170028d | 1118 | else |
05ba7d5f | 1119 | t_gen_zext(cpu_T[1], cpu_T[1], memsize); |
8170028d TS |
1120 | } |
1121 | ||
1122 | /* put dest in T0. */ | |
05ba7d5f | 1123 | t_gen_mov_TN_reg(cpu_T[0], rd); |
8170028d TS |
1124 | return insn_len; |
1125 | } | |
1126 | ||
1127 | #if DISAS_CRIS | |
1128 | static const char *cc_name(int cc) | |
1129 | { | |
1130 | static char *cc_names[16] = { | |
1131 | "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", | |
1132 | "ls", "hi", "ge", "lt", "gt", "le", "a", "p" | |
1133 | }; | |
1134 | assert(cc < 16); | |
1135 | return cc_names[cc]; | |
1136 | } | |
1137 | #endif | |
1138 | ||
b41f7df0 EI |
1139 | /* Start of insn decoders. */ |
1140 | ||
8170028d TS |
1141 | static unsigned int dec_bccq(DisasContext *dc) |
1142 | { | |
1143 | int32_t offset; | |
1144 | int sign; | |
1145 | uint32_t cond = dc->op2; | |
1146 | int tmp; | |
1147 | ||
1148 | offset = EXTRACT_FIELD (dc->ir, 1, 7); | |
1149 | sign = EXTRACT_FIELD(dc->ir, 0, 0); | |
1150 | ||
1151 | offset *= 2; | |
1152 | offset |= sign << 8; | |
1153 | tmp = offset; | |
1154 | offset = sign_extend(offset, 8); | |
1155 | ||
1156 | /* op2 holds the condition-code. */ | |
1157 | cris_cc_mask(dc, 0); | |
1158 | cris_prepare_cc_branch (dc, offset, cond); | |
1159 | return 2; | |
1160 | } | |
1161 | static unsigned int dec_addoq(DisasContext *dc) | |
1162 | { | |
b41f7df0 | 1163 | int32_t imm; |
8170028d TS |
1164 | |
1165 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); | |
1166 | imm = sign_extend(dc->op1, 7); | |
1167 | ||
1168 | DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2)); | |
1169 | cris_cc_mask(dc, 0); | |
1170 | /* Fetch register operand, */ | |
b41f7df0 | 1171 | tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); |
8170028d TS |
1172 | return 2; |
1173 | } | |
1174 | static unsigned int dec_addq(DisasContext *dc) | |
1175 | { | |
1176 | DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2)); | |
1177 | ||
1178 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1179 | ||
1180 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1181 | /* Fetch register operand, */ | |
05ba7d5f EI |
1182 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1183 | tcg_gen_movi_tl(cpu_T[1], dc->op1); | |
8170028d TS |
1184 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4); |
1185 | return 2; | |
1186 | } | |
1187 | static unsigned int dec_moveq(DisasContext *dc) | |
1188 | { | |
1189 | uint32_t imm; | |
1190 | ||
1191 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1192 | imm = sign_extend(dc->op1, 5); | |
1193 | DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2)); | |
1194 | ||
3157a0a9 | 1195 | t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm)); |
8170028d TS |
1196 | return 2; |
1197 | } | |
1198 | static unsigned int dec_subq(DisasContext *dc) | |
1199 | { | |
1200 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1201 | ||
1202 | DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2)); | |
1203 | ||
1204 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1205 | /* Fetch register operand, */ | |
05ba7d5f EI |
1206 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1207 | t_gen_mov_TN_im(cpu_T[1], dc->op1); | |
8170028d TS |
1208 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4); |
1209 | return 2; | |
1210 | } | |
1211 | static unsigned int dec_cmpq(DisasContext *dc) | |
1212 | { | |
1213 | uint32_t imm; | |
1214 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1215 | imm = sign_extend(dc->op1, 5); | |
1216 | ||
1217 | DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2)); | |
1218 | cris_cc_mask(dc, CC_MASK_NZVC); | |
05ba7d5f EI |
1219 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1220 | t_gen_mov_TN_im(cpu_T[1], imm); | |
8170028d TS |
1221 | crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4); |
1222 | return 2; | |
1223 | } | |
1224 | static unsigned int dec_andq(DisasContext *dc) | |
1225 | { | |
1226 | uint32_t imm; | |
1227 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1228 | imm = sign_extend(dc->op1, 5); | |
1229 | ||
1230 | DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2)); | |
1231 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f EI |
1232 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1233 | t_gen_mov_TN_im(cpu_T[1], imm); | |
8170028d TS |
1234 | crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4); |
1235 | return 2; | |
1236 | } | |
1237 | static unsigned int dec_orq(DisasContext *dc) | |
1238 | { | |
1239 | uint32_t imm; | |
1240 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); | |
1241 | imm = sign_extend(dc->op1, 5); | |
1242 | DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2)); | |
1243 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f EI |
1244 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1245 | t_gen_mov_TN_im(cpu_T[1], imm); | |
8170028d TS |
1246 | crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4); |
1247 | return 2; | |
1248 | } | |
1249 | static unsigned int dec_btstq(DisasContext *dc) | |
1250 | { | |
1251 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); | |
1252 | DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2)); | |
8170028d | 1253 | cris_cc_mask(dc, CC_MASK_NZ); |
05ba7d5f EI |
1254 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1255 | t_gen_mov_TN_im(cpu_T[1], dc->op1); | |
8170028d TS |
1256 | crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4); |
1257 | ||
b41f7df0 | 1258 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
3157a0a9 | 1259 | t_gen_mov_preg_TN(PR_CCS, cpu_T[0]); |
8170028d TS |
1260 | dc->flags_live = 1; |
1261 | return 2; | |
1262 | } | |
1263 | static unsigned int dec_asrq(DisasContext *dc) | |
1264 | { | |
1265 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); | |
1266 | DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2)); | |
1267 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f EI |
1268 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1269 | t_gen_mov_TN_im(cpu_T[1], dc->op1); | |
8170028d TS |
1270 | crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4); |
1271 | return 2; | |
1272 | } | |
1273 | static unsigned int dec_lslq(DisasContext *dc) | |
1274 | { | |
1275 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); | |
1276 | DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2)); | |
1277 | ||
1278 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f EI |
1279 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1280 | t_gen_mov_TN_im(cpu_T[1], dc->op1); | |
8170028d TS |
1281 | crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4); |
1282 | return 2; | |
1283 | } | |
1284 | static unsigned int dec_lsrq(DisasContext *dc) | |
1285 | { | |
1286 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); | |
1287 | DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2)); | |
1288 | ||
1289 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f EI |
1290 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
1291 | t_gen_mov_TN_im(cpu_T[1], dc->op1); | |
8170028d TS |
1292 | crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4); |
1293 | return 2; | |
1294 | } | |
1295 | ||
1296 | static unsigned int dec_move_r(DisasContext *dc) | |
1297 | { | |
1298 | int size = memsize_zz(dc); | |
1299 | ||
1300 | DIS(fprintf (logfile, "move.%c $r%u, $r%u\n", | |
1301 | memsize_char(size), dc->op1, dc->op2)); | |
1302 | ||
1303 | cris_cc_mask(dc, CC_MASK_NZ); | |
1304 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0); | |
1305 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size); | |
1306 | return 2; | |
1307 | } | |
1308 | ||
1309 | static unsigned int dec_scc_r(DisasContext *dc) | |
1310 | { | |
1311 | int cond = dc->op2; | |
1312 | ||
1313 | DIS(fprintf (logfile, "s%s $r%u\n", | |
1314 | cc_name(cond), dc->op1)); | |
1315 | ||
1316 | if (cond != CC_A) | |
1317 | { | |
1318 | gen_tst_cc (dc, cond); | |
3157a0a9 | 1319 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); |
8170028d TS |
1320 | } |
1321 | else | |
3157a0a9 | 1322 | tcg_gen_movi_tl(cpu_T[1], 1); |
8170028d TS |
1323 | |
1324 | cris_cc_mask(dc, 0); | |
1325 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4); | |
1326 | return 2; | |
1327 | } | |
1328 | ||
1329 | static unsigned int dec_and_r(DisasContext *dc) | |
1330 | { | |
1331 | int size = memsize_zz(dc); | |
1332 | ||
1333 | DIS(fprintf (logfile, "and.%c $r%u, $r%u\n", | |
1334 | memsize_char(size), dc->op1, dc->op2)); | |
1335 | cris_cc_mask(dc, CC_MASK_NZ); | |
1336 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1337 | crisv32_alu_op(dc, CC_OP_AND, dc->op2, size); | |
1338 | return 2; | |
1339 | } | |
1340 | ||
1341 | static unsigned int dec_lz_r(DisasContext *dc) | |
1342 | { | |
1343 | DIS(fprintf (logfile, "lz $r%u, $r%u\n", | |
1344 | dc->op1, dc->op2)); | |
1345 | cris_cc_mask(dc, CC_MASK_NZ); | |
1346 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); | |
1347 | crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4); | |
1348 | return 2; | |
1349 | } | |
1350 | ||
1351 | static unsigned int dec_lsl_r(DisasContext *dc) | |
1352 | { | |
1353 | int size = memsize_zz(dc); | |
1354 | ||
1355 | DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n", | |
1356 | memsize_char(size), dc->op1, dc->op2)); | |
1357 | cris_cc_mask(dc, CC_MASK_NZ); | |
1358 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
05ba7d5f | 1359 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63); |
8170028d TS |
1360 | crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size); |
1361 | return 2; | |
1362 | } | |
1363 | ||
1364 | static unsigned int dec_lsr_r(DisasContext *dc) | |
1365 | { | |
1366 | int size = memsize_zz(dc); | |
1367 | ||
1368 | DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n", | |
1369 | memsize_char(size), dc->op1, dc->op2)); | |
1370 | cris_cc_mask(dc, CC_MASK_NZ); | |
1371 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
05ba7d5f | 1372 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63); |
8170028d TS |
1373 | crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size); |
1374 | return 2; | |
1375 | } | |
1376 | ||
1377 | static unsigned int dec_asr_r(DisasContext *dc) | |
1378 | { | |
1379 | int size = memsize_zz(dc); | |
1380 | ||
1381 | DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n", | |
1382 | memsize_char(size), dc->op1, dc->op2)); | |
1383 | cris_cc_mask(dc, CC_MASK_NZ); | |
1384 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1); | |
05ba7d5f | 1385 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63); |
8170028d TS |
1386 | crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size); |
1387 | return 2; | |
1388 | } | |
1389 | ||
1390 | static unsigned int dec_muls_r(DisasContext *dc) | |
1391 | { | |
1392 | int size = memsize_zz(dc); | |
1393 | ||
1394 | DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n", | |
1395 | memsize_char(size), dc->op1, dc->op2)); | |
1396 | cris_cc_mask(dc, CC_MASK_NZV); | |
1397 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1); | |
05ba7d5f | 1398 | t_gen_sext(cpu_T[0], cpu_T[0], size); |
8170028d TS |
1399 | crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4); |
1400 | return 2; | |
1401 | } | |
1402 | ||
1403 | static unsigned int dec_mulu_r(DisasContext *dc) | |
1404 | { | |
1405 | int size = memsize_zz(dc); | |
1406 | ||
1407 | DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n", | |
1408 | memsize_char(size), dc->op1, dc->op2)); | |
1409 | cris_cc_mask(dc, CC_MASK_NZV); | |
1410 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
05ba7d5f | 1411 | t_gen_zext(cpu_T[0], cpu_T[0], size); |
8170028d TS |
1412 | crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4); |
1413 | return 2; | |
1414 | } | |
1415 | ||
1416 | ||
1417 | static unsigned int dec_dstep_r(DisasContext *dc) | |
1418 | { | |
1419 | DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2)); | |
1420 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f EI |
1421 | t_gen_mov_TN_reg(cpu_T[1], dc->op1); |
1422 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); | |
8170028d TS |
1423 | crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4); |
1424 | return 2; | |
1425 | } | |
1426 | ||
1427 | static unsigned int dec_xor_r(DisasContext *dc) | |
1428 | { | |
1429 | int size = memsize_zz(dc); | |
1430 | DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n", | |
1431 | memsize_char(size), dc->op1, dc->op2)); | |
1432 | BUG_ON(size != 4); /* xor is dword. */ | |
1433 | cris_cc_mask(dc, CC_MASK_NZ); | |
1434 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1435 | crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4); | |
1436 | return 2; | |
1437 | } | |
1438 | ||
1439 | static unsigned int dec_bound_r(DisasContext *dc) | |
1440 | { | |
1441 | int size = memsize_zz(dc); | |
1442 | DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n", | |
1443 | memsize_char(size), dc->op1, dc->op2)); | |
1444 | cris_cc_mask(dc, CC_MASK_NZ); | |
1445 | /* TODO: needs optmimization. */ | |
1446 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1447 | /* rd should be 4. */ | |
05ba7d5f | 1448 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); |
8170028d TS |
1449 | crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4); |
1450 | return 2; | |
1451 | } | |
1452 | ||
1453 | static unsigned int dec_cmp_r(DisasContext *dc) | |
1454 | { | |
1455 | int size = memsize_zz(dc); | |
1456 | DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n", | |
1457 | memsize_char(size), dc->op1, dc->op2)); | |
1458 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1459 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1460 | crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size); | |
1461 | return 2; | |
1462 | } | |
1463 | ||
1464 | static unsigned int dec_abs_r(DisasContext *dc) | |
1465 | { | |
3157a0a9 EI |
1466 | int l1; |
1467 | ||
8170028d TS |
1468 | DIS(fprintf (logfile, "abs $r%u, $r%u\n", |
1469 | dc->op1, dc->op2)); | |
1470 | cris_cc_mask(dc, CC_MASK_NZ); | |
1471 | dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0); | |
3157a0a9 EI |
1472 | |
1473 | /* TODO: consider a branch free approach. */ | |
1474 | l1 = gen_new_label(); | |
1475 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1); | |
1476 | tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]); | |
1477 | gen_set_label(l1); | |
8170028d TS |
1478 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4); |
1479 | return 2; | |
1480 | } | |
1481 | ||
1482 | static unsigned int dec_add_r(DisasContext *dc) | |
1483 | { | |
1484 | int size = memsize_zz(dc); | |
1485 | DIS(fprintf (logfile, "add.%c $r%u, $r%u\n", | |
1486 | memsize_char(size), dc->op1, dc->op2)); | |
1487 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1488 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1489 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size); | |
1490 | return 2; | |
1491 | } | |
1492 | ||
1493 | static unsigned int dec_addc_r(DisasContext *dc) | |
1494 | { | |
1495 | DIS(fprintf (logfile, "addc $r%u, $r%u\n", | |
1496 | dc->op1, dc->op2)); | |
1497 | cris_evaluate_flags(dc); | |
1498 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1499 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); | |
1500 | crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4); | |
1501 | return 2; | |
1502 | } | |
1503 | ||
1504 | static unsigned int dec_mcp_r(DisasContext *dc) | |
1505 | { | |
1506 | DIS(fprintf (logfile, "mcp $p%u, $r%u\n", | |
1507 | dc->op2, dc->op1)); | |
1508 | cris_evaluate_flags(dc); | |
1509 | cris_cc_mask(dc, CC_MASK_RNZV); | |
05ba7d5f EI |
1510 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
1511 | t_gen_mov_TN_preg(cpu_T[1], dc->op2); | |
8170028d TS |
1512 | crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4); |
1513 | return 2; | |
1514 | } | |
1515 | ||
1516 | #if DISAS_CRIS | |
1517 | static char * swapmode_name(int mode, char *modename) { | |
1518 | int i = 0; | |
1519 | if (mode & 8) | |
1520 | modename[i++] = 'n'; | |
1521 | if (mode & 4) | |
1522 | modename[i++] = 'w'; | |
1523 | if (mode & 2) | |
1524 | modename[i++] = 'b'; | |
1525 | if (mode & 1) | |
1526 | modename[i++] = 'r'; | |
1527 | modename[i++] = 0; | |
1528 | return modename; | |
1529 | } | |
1530 | #endif | |
1531 | ||
1532 | static unsigned int dec_swap_r(DisasContext *dc) | |
1533 | { | |
1534 | DIS(char modename[4]); | |
1535 | DIS(fprintf (logfile, "swap%s $r%u\n", | |
1536 | swapmode_name(dc->op2, modename), dc->op1)); | |
1537 | ||
1538 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f | 1539 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
8170028d | 1540 | if (dc->op2 & 8) |
3157a0a9 | 1541 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1); |
8170028d | 1542 | if (dc->op2 & 4) |
3157a0a9 | 1543 | t_gen_swapw(cpu_T[0], cpu_T[0]); |
8170028d | 1544 | if (dc->op2 & 2) |
3157a0a9 | 1545 | t_gen_swapb(cpu_T[0], cpu_T[0]); |
8170028d | 1546 | if (dc->op2 & 1) |
3157a0a9 EI |
1547 | t_gen_swapr(cpu_T[0], cpu_T[0]); |
1548 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); | |
8170028d TS |
1549 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4); |
1550 | return 2; | |
1551 | } | |
1552 | ||
1553 | static unsigned int dec_or_r(DisasContext *dc) | |
1554 | { | |
1555 | int size = memsize_zz(dc); | |
1556 | DIS(fprintf (logfile, "or.%c $r%u, $r%u\n", | |
1557 | memsize_char(size), dc->op1, dc->op2)); | |
1558 | cris_cc_mask(dc, CC_MASK_NZ); | |
1559 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1560 | crisv32_alu_op(dc, CC_OP_OR, dc->op2, size); | |
1561 | return 2; | |
1562 | } | |
1563 | ||
1564 | static unsigned int dec_addi_r(DisasContext *dc) | |
1565 | { | |
1566 | DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n", | |
1567 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1)); | |
1568 | cris_cc_mask(dc, 0); | |
1569 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); | |
3157a0a9 | 1570 | t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize)); |
05ba7d5f EI |
1571 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1572 | t_gen_mov_reg_TN(dc->op1, cpu_T[0]); | |
8170028d TS |
1573 | return 2; |
1574 | } | |
1575 | ||
1576 | static unsigned int dec_addi_acr(DisasContext *dc) | |
1577 | { | |
1578 | DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n", | |
b41f7df0 | 1579 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1)); |
8170028d TS |
1580 | cris_cc_mask(dc, 0); |
1581 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); | |
3157a0a9 | 1582 | t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize)); |
b41f7df0 | 1583 | |
05ba7d5f EI |
1584 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
1585 | t_gen_mov_reg_TN(R_ACR, cpu_T[0]); | |
8170028d TS |
1586 | return 2; |
1587 | } | |
1588 | ||
1589 | static unsigned int dec_neg_r(DisasContext *dc) | |
1590 | { | |
1591 | int size = memsize_zz(dc); | |
1592 | DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n", | |
1593 | memsize_char(size), dc->op1, dc->op2)); | |
1594 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1595 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1596 | crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size); | |
1597 | return 2; | |
1598 | } | |
1599 | ||
1600 | static unsigned int dec_btst_r(DisasContext *dc) | |
1601 | { | |
1602 | DIS(fprintf (logfile, "btst $r%u, $r%u\n", | |
1603 | dc->op1, dc->op2)); | |
8170028d TS |
1604 | cris_cc_mask(dc, CC_MASK_NZ); |
1605 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); | |
1606 | crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4); | |
1607 | ||
b41f7df0 | 1608 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
3157a0a9 | 1609 | t_gen_mov_preg_TN(PR_CCS, cpu_T[0]); |
8170028d TS |
1610 | dc->flags_live = 1; |
1611 | return 2; | |
1612 | } | |
1613 | ||
1614 | static unsigned int dec_sub_r(DisasContext *dc) | |
1615 | { | |
1616 | int size = memsize_zz(dc); | |
1617 | DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n", | |
1618 | memsize_char(size), dc->op1, dc->op2)); | |
1619 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1620 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0); | |
1621 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size); | |
1622 | return 2; | |
1623 | } | |
1624 | ||
1625 | /* Zero extension. From size to dword. */ | |
1626 | static unsigned int dec_movu_r(DisasContext *dc) | |
1627 | { | |
1628 | int size = memsize_z(dc); | |
1629 | DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n", | |
1630 | memsize_char(size), | |
1631 | dc->op1, dc->op2)); | |
1632 | ||
1633 | cris_cc_mask(dc, CC_MASK_NZ); | |
1634 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0); | |
1635 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4); | |
1636 | return 2; | |
1637 | } | |
1638 | ||
1639 | /* Sign extension. From size to dword. */ | |
1640 | static unsigned int dec_movs_r(DisasContext *dc) | |
1641 | { | |
1642 | int size = memsize_z(dc); | |
1643 | DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n", | |
1644 | memsize_char(size), | |
1645 | dc->op1, dc->op2)); | |
1646 | ||
1647 | cris_cc_mask(dc, CC_MASK_NZ); | |
05ba7d5f | 1648 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
8170028d | 1649 | /* Size can only be qi or hi. */ |
05ba7d5f | 1650 | t_gen_sext(cpu_T[1], cpu_T[0], size); |
8170028d TS |
1651 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4); |
1652 | return 2; | |
1653 | } | |
1654 | ||
1655 | /* zero extension. From size to dword. */ | |
1656 | static unsigned int dec_addu_r(DisasContext *dc) | |
1657 | { | |
1658 | int size = memsize_z(dc); | |
1659 | DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n", | |
1660 | memsize_char(size), | |
1661 | dc->op1, dc->op2)); | |
1662 | ||
1663 | cris_cc_mask(dc, CC_MASK_NZVC); | |
05ba7d5f | 1664 | t_gen_mov_TN_reg(cpu_T[1], dc->op1); |
8170028d | 1665 | /* Size can only be qi or hi. */ |
05ba7d5f EI |
1666 | t_gen_zext(cpu_T[1], cpu_T[1], size); |
1667 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); | |
8170028d TS |
1668 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4); |
1669 | return 2; | |
1670 | } | |
05ba7d5f | 1671 | |
8170028d TS |
1672 | /* Sign extension. From size to dword. */ |
1673 | static unsigned int dec_adds_r(DisasContext *dc) | |
1674 | { | |
1675 | int size = memsize_z(dc); | |
1676 | DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n", | |
1677 | memsize_char(size), | |
1678 | dc->op1, dc->op2)); | |
1679 | ||
1680 | cris_cc_mask(dc, CC_MASK_NZVC); | |
05ba7d5f | 1681 | t_gen_mov_TN_reg(cpu_T[1], dc->op1); |
8170028d | 1682 | /* Size can only be qi or hi. */ |
05ba7d5f EI |
1683 | t_gen_sext(cpu_T[1], cpu_T[1], size); |
1684 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); | |
1685 | ||
8170028d TS |
1686 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4); |
1687 | return 2; | |
1688 | } | |
1689 | ||
1690 | /* Zero extension. From size to dword. */ | |
1691 | static unsigned int dec_subu_r(DisasContext *dc) | |
1692 | { | |
1693 | int size = memsize_z(dc); | |
1694 | DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n", | |
1695 | memsize_char(size), | |
1696 | dc->op1, dc->op2)); | |
1697 | ||
1698 | cris_cc_mask(dc, CC_MASK_NZVC); | |
05ba7d5f | 1699 | t_gen_mov_TN_reg(cpu_T[1], dc->op1); |
8170028d | 1700 | /* Size can only be qi or hi. */ |
05ba7d5f EI |
1701 | t_gen_zext(cpu_T[1], cpu_T[1], size); |
1702 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); | |
8170028d TS |
1703 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4); |
1704 | return 2; | |
1705 | } | |
1706 | ||
1707 | /* Sign extension. From size to dword. */ | |
1708 | static unsigned int dec_subs_r(DisasContext *dc) | |
1709 | { | |
1710 | int size = memsize_z(dc); | |
1711 | DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n", | |
1712 | memsize_char(size), | |
1713 | dc->op1, dc->op2)); | |
1714 | ||
1715 | cris_cc_mask(dc, CC_MASK_NZVC); | |
05ba7d5f | 1716 | t_gen_mov_TN_reg(cpu_T[1], dc->op1); |
8170028d | 1717 | /* Size can only be qi or hi. */ |
05ba7d5f EI |
1718 | t_gen_sext(cpu_T[1], cpu_T[1], size); |
1719 | t_gen_mov_TN_reg(cpu_T[0], dc->op2); | |
8170028d TS |
1720 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4); |
1721 | return 2; | |
1722 | } | |
1723 | ||
1724 | static unsigned int dec_setclrf(DisasContext *dc) | |
1725 | { | |
1726 | uint32_t flags; | |
1727 | int set = (~dc->opcode >> 2) & 1; | |
1728 | ||
1729 | flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) | |
1730 | | EXTRACT_FIELD(dc->ir, 0, 3); | |
1731 | DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags)); | |
1732 | if (set && flags == 0) | |
1733 | DIS(fprintf (logfile, "nop\n")); | |
1734 | else if (!set && (flags & 0x20)) | |
1735 | DIS(fprintf (logfile, "di\n")); | |
1736 | else | |
1737 | DIS(fprintf (logfile, "%sf %x\n", | |
1738 | set ? "set" : "clr", | |
1739 | flags)); | |
1740 | ||
1741 | if (set && (flags & X_FLAG)) { | |
1742 | dc->flagx_live = 1; | |
1743 | dc->flags_x = 1; | |
1744 | } | |
1745 | ||
1746 | /* Simply decode the flags. */ | |
1747 | cris_evaluate_flags (dc); | |
b41f7df0 EI |
1748 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
1749 | tcg_gen_movi_tl(cc_op, dc->cc_op); | |
1750 | ||
8170028d | 1751 | if (set) |
a825e703 | 1752 | gen_op_setf(flags); |
8170028d | 1753 | else |
a825e703 | 1754 | gen_op_clrf(flags); |
8170028d | 1755 | dc->flags_live = 1; |
b41f7df0 | 1756 | dc->clear_x = 0; |
8170028d TS |
1757 | return 2; |
1758 | } | |
1759 | ||
1760 | static unsigned int dec_move_rs(DisasContext *dc) | |
1761 | { | |
1762 | DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2)); | |
1763 | cris_cc_mask(dc, 0); | |
05ba7d5f | 1764 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
8170028d TS |
1765 | gen_op_movl_sreg_T0(dc->op2); |
1766 | ||
05ba7d5f EI |
1767 | #if !defined(CONFIG_USER_ONLY) |
1768 | if (dc->op2 == 6) | |
1769 | gen_op_movl_tlb_hi_T0(); | |
1770 | else if (dc->op2 == 5) { /* srs is checked at runtime. */ | |
1771 | tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]); | |
8170028d | 1772 | gen_op_movl_tlb_lo_T0(); |
05ba7d5f EI |
1773 | } |
1774 | #endif | |
8170028d TS |
1775 | return 2; |
1776 | } | |
1777 | static unsigned int dec_move_sr(DisasContext *dc) | |
1778 | { | |
05ba7d5f | 1779 | DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1)); |
8170028d | 1780 | cris_cc_mask(dc, 0); |
05ba7d5f EI |
1781 | gen_op_movl_T0_sreg(dc->op2); |
1782 | tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); | |
1783 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4); | |
8170028d TS |
1784 | return 2; |
1785 | } | |
1786 | static unsigned int dec_move_rp(DisasContext *dc) | |
1787 | { | |
1788 | DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2)); | |
1789 | cris_cc_mask(dc, 0); | |
b41f7df0 EI |
1790 | |
1791 | if (dc->op2 == PR_CCS) { | |
1792 | cris_evaluate_flags(dc); | |
1793 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); | |
1794 | if (dc->user) { | |
1795 | /* User space is not allowed to touch all flags. */ | |
1796 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f); | |
1797 | tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f); | |
1798 | tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]); | |
1799 | } | |
1800 | } | |
1801 | else | |
1802 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); | |
1803 | ||
05ba7d5f | 1804 | t_gen_mov_preg_TN(dc->op2, cpu_T[0]); |
b41f7df0 EI |
1805 | if (dc->op2 == PR_CCS) { |
1806 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
1807 | dc->flags_live = 1; | |
1808 | } | |
8170028d TS |
1809 | return 2; |
1810 | } | |
1811 | static unsigned int dec_move_pr(DisasContext *dc) | |
1812 | { | |
1813 | DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2)); | |
1814 | cris_cc_mask(dc, 0); | |
fd56059f AZ |
1815 | /* Support register 0 is hardwired to zero. |
1816 | Treat it specially. */ | |
1817 | if (dc->op2 == 0) | |
05ba7d5f | 1818 | tcg_gen_movi_tl(cpu_T[1], 0); |
b41f7df0 EI |
1819 | else if (dc->op2 == PR_CCS) { |
1820 | cris_evaluate_flags(dc); | |
1821 | t_gen_mov_TN_preg(cpu_T[1], dc->op2); | |
1822 | } else | |
05ba7d5f | 1823 | t_gen_mov_TN_preg(cpu_T[1], dc->op2); |
8170028d TS |
1824 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]); |
1825 | return 2; | |
1826 | } | |
1827 | ||
1828 | static unsigned int dec_move_mr(DisasContext *dc) | |
1829 | { | |
1830 | int memsize = memsize_zz(dc); | |
1831 | int insn_len; | |
1832 | DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n", | |
1833 | memsize_char(memsize), | |
1834 | dc->op1, dc->postinc ? "+]" : "]", | |
1835 | dc->op2)); | |
1836 | ||
8170028d | 1837 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 1838 | cris_cc_mask(dc, CC_MASK_NZ); |
8170028d TS |
1839 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize); |
1840 | do_postinc(dc, memsize); | |
1841 | return insn_len; | |
1842 | } | |
1843 | ||
1844 | static unsigned int dec_movs_m(DisasContext *dc) | |
1845 | { | |
1846 | int memsize = memsize_z(dc); | |
1847 | int insn_len; | |
1848 | DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n", | |
1849 | memsize_char(memsize), | |
1850 | dc->op1, dc->postinc ? "+]" : "]", | |
1851 | dc->op2)); | |
1852 | ||
1853 | /* sign extend. */ | |
8170028d | 1854 | insn_len = dec_prep_alu_m(dc, 1, memsize); |
b41f7df0 | 1855 | cris_cc_mask(dc, CC_MASK_NZ); |
8170028d TS |
1856 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4); |
1857 | do_postinc(dc, memsize); | |
1858 | return insn_len; | |
1859 | } | |
1860 | ||
1861 | static unsigned int dec_addu_m(DisasContext *dc) | |
1862 | { | |
1863 | int memsize = memsize_z(dc); | |
1864 | int insn_len; | |
1865 | DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n", | |
1866 | memsize_char(memsize), | |
1867 | dc->op1, dc->postinc ? "+]" : "]", | |
1868 | dc->op2)); | |
1869 | ||
1870 | /* sign extend. */ | |
8170028d | 1871 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 1872 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1873 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4); |
1874 | do_postinc(dc, memsize); | |
1875 | return insn_len; | |
1876 | } | |
1877 | ||
1878 | static unsigned int dec_adds_m(DisasContext *dc) | |
1879 | { | |
1880 | int memsize = memsize_z(dc); | |
1881 | int insn_len; | |
1882 | DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n", | |
1883 | memsize_char(memsize), | |
1884 | dc->op1, dc->postinc ? "+]" : "]", | |
1885 | dc->op2)); | |
1886 | ||
1887 | /* sign extend. */ | |
8170028d | 1888 | insn_len = dec_prep_alu_m(dc, 1, memsize); |
b41f7df0 | 1889 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1890 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4); |
1891 | do_postinc(dc, memsize); | |
1892 | return insn_len; | |
1893 | } | |
1894 | ||
1895 | static unsigned int dec_subu_m(DisasContext *dc) | |
1896 | { | |
1897 | int memsize = memsize_z(dc); | |
1898 | int insn_len; | |
1899 | DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n", | |
1900 | memsize_char(memsize), | |
1901 | dc->op1, dc->postinc ? "+]" : "]", | |
1902 | dc->op2)); | |
1903 | ||
1904 | /* sign extend. */ | |
8170028d | 1905 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 1906 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1907 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4); |
1908 | do_postinc(dc, memsize); | |
1909 | return insn_len; | |
1910 | } | |
1911 | ||
1912 | static unsigned int dec_subs_m(DisasContext *dc) | |
1913 | { | |
1914 | int memsize = memsize_z(dc); | |
1915 | int insn_len; | |
1916 | DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n", | |
1917 | memsize_char(memsize), | |
1918 | dc->op1, dc->postinc ? "+]" : "]", | |
1919 | dc->op2)); | |
1920 | ||
1921 | /* sign extend. */ | |
8170028d | 1922 | insn_len = dec_prep_alu_m(dc, 1, memsize); |
b41f7df0 | 1923 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1924 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4); |
1925 | do_postinc(dc, memsize); | |
1926 | return insn_len; | |
1927 | } | |
1928 | ||
1929 | static unsigned int dec_movu_m(DisasContext *dc) | |
1930 | { | |
1931 | int memsize = memsize_z(dc); | |
1932 | int insn_len; | |
1933 | ||
1934 | DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n", | |
1935 | memsize_char(memsize), | |
1936 | dc->op1, dc->postinc ? "+]" : "]", | |
1937 | dc->op2)); | |
1938 | ||
8170028d | 1939 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 1940 | cris_cc_mask(dc, CC_MASK_NZ); |
8170028d TS |
1941 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4); |
1942 | do_postinc(dc, memsize); | |
1943 | return insn_len; | |
1944 | } | |
1945 | ||
1946 | static unsigned int dec_cmpu_m(DisasContext *dc) | |
1947 | { | |
1948 | int memsize = memsize_z(dc); | |
1949 | int insn_len; | |
1950 | DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n", | |
1951 | memsize_char(memsize), | |
1952 | dc->op1, dc->postinc ? "+]" : "]", | |
1953 | dc->op2)); | |
1954 | ||
8170028d | 1955 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 1956 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1957 | crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4); |
1958 | do_postinc(dc, memsize); | |
1959 | return insn_len; | |
1960 | } | |
1961 | ||
1962 | static unsigned int dec_cmps_m(DisasContext *dc) | |
1963 | { | |
1964 | int memsize = memsize_z(dc); | |
1965 | int insn_len; | |
1966 | DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n", | |
1967 | memsize_char(memsize), | |
1968 | dc->op1, dc->postinc ? "+]" : "]", | |
1969 | dc->op2)); | |
1970 | ||
8170028d | 1971 | insn_len = dec_prep_alu_m(dc, 1, memsize); |
b41f7df0 | 1972 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1973 | crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc)); |
1974 | do_postinc(dc, memsize); | |
1975 | return insn_len; | |
1976 | } | |
1977 | ||
1978 | static unsigned int dec_cmp_m(DisasContext *dc) | |
1979 | { | |
1980 | int memsize = memsize_zz(dc); | |
1981 | int insn_len; | |
1982 | DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n", | |
1983 | memsize_char(memsize), | |
1984 | dc->op1, dc->postinc ? "+]" : "]", | |
1985 | dc->op2)); | |
1986 | ||
8170028d | 1987 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 1988 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
1989 | crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc)); |
1990 | do_postinc(dc, memsize); | |
1991 | return insn_len; | |
1992 | } | |
1993 | ||
1994 | static unsigned int dec_test_m(DisasContext *dc) | |
1995 | { | |
1996 | int memsize = memsize_zz(dc); | |
1997 | int insn_len; | |
1998 | DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n", | |
1999 | memsize_char(memsize), | |
2000 | dc->op1, dc->postinc ? "+]" : "]", | |
2001 | dc->op2)); | |
2002 | ||
b41f7df0 | 2003 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
8170028d TS |
2004 | cris_cc_mask(dc, CC_MASK_NZ); |
2005 | gen_op_clrf(3); | |
b41f7df0 | 2006 | |
05ba7d5f EI |
2007 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); |
2008 | tcg_gen_movi_tl(cpu_T[1], 0); | |
8170028d TS |
2009 | crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc)); |
2010 | do_postinc(dc, memsize); | |
2011 | return insn_len; | |
2012 | } | |
2013 | ||
2014 | static unsigned int dec_and_m(DisasContext *dc) | |
2015 | { | |
2016 | int memsize = memsize_zz(dc); | |
2017 | int insn_len; | |
2018 | DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n", | |
2019 | memsize_char(memsize), | |
2020 | dc->op1, dc->postinc ? "+]" : "]", | |
2021 | dc->op2)); | |
2022 | ||
8170028d | 2023 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 2024 | cris_cc_mask(dc, CC_MASK_NZ); |
8170028d TS |
2025 | crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc)); |
2026 | do_postinc(dc, memsize); | |
2027 | return insn_len; | |
2028 | } | |
2029 | ||
2030 | static unsigned int dec_add_m(DisasContext *dc) | |
2031 | { | |
2032 | int memsize = memsize_zz(dc); | |
2033 | int insn_len; | |
2034 | DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n", | |
2035 | memsize_char(memsize), | |
2036 | dc->op1, dc->postinc ? "+]" : "]", | |
2037 | dc->op2)); | |
2038 | ||
8170028d | 2039 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 2040 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
2041 | crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc)); |
2042 | do_postinc(dc, memsize); | |
2043 | return insn_len; | |
2044 | } | |
2045 | ||
2046 | static unsigned int dec_addo_m(DisasContext *dc) | |
2047 | { | |
2048 | int memsize = memsize_zz(dc); | |
2049 | int insn_len; | |
2050 | DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n", | |
2051 | memsize_char(memsize), | |
2052 | dc->op1, dc->postinc ? "+]" : "]", | |
2053 | dc->op2)); | |
2054 | ||
8170028d | 2055 | insn_len = dec_prep_alu_m(dc, 1, memsize); |
b41f7df0 | 2056 | cris_cc_mask(dc, 0); |
9004627f | 2057 | crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4); |
8170028d TS |
2058 | do_postinc(dc, memsize); |
2059 | return insn_len; | |
2060 | } | |
2061 | ||
2062 | static unsigned int dec_bound_m(DisasContext *dc) | |
2063 | { | |
2064 | int memsize = memsize_zz(dc); | |
2065 | int insn_len; | |
2066 | DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n", | |
2067 | memsize_char(memsize), | |
2068 | dc->op1, dc->postinc ? "+]" : "]", | |
2069 | dc->op2)); | |
2070 | ||
8170028d | 2071 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 2072 | cris_cc_mask(dc, CC_MASK_NZ); |
8170028d TS |
2073 | crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4); |
2074 | do_postinc(dc, memsize); | |
2075 | return insn_len; | |
2076 | } | |
2077 | ||
2078 | static unsigned int dec_addc_mr(DisasContext *dc) | |
2079 | { | |
2080 | int insn_len = 2; | |
2081 | DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n", | |
2082 | dc->op1, dc->postinc ? "+]" : "]", | |
2083 | dc->op2)); | |
2084 | ||
2085 | cris_evaluate_flags(dc); | |
8170028d | 2086 | insn_len = dec_prep_alu_m(dc, 0, 4); |
b41f7df0 | 2087 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
2088 | crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4); |
2089 | do_postinc(dc, 4); | |
2090 | return insn_len; | |
2091 | } | |
2092 | ||
2093 | static unsigned int dec_sub_m(DisasContext *dc) | |
2094 | { | |
2095 | int memsize = memsize_zz(dc); | |
2096 | int insn_len; | |
2097 | DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", | |
2098 | memsize_char(memsize), | |
2099 | dc->op1, dc->postinc ? "+]" : "]", | |
2100 | dc->op2, dc->ir, dc->zzsize)); | |
2101 | ||
8170028d | 2102 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 2103 | cris_cc_mask(dc, CC_MASK_NZVC); |
8170028d TS |
2104 | crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize); |
2105 | do_postinc(dc, memsize); | |
2106 | return insn_len; | |
2107 | } | |
2108 | ||
2109 | static unsigned int dec_or_m(DisasContext *dc) | |
2110 | { | |
2111 | int memsize = memsize_zz(dc); | |
2112 | int insn_len; | |
2113 | DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n", | |
2114 | memsize_char(memsize), | |
2115 | dc->op1, dc->postinc ? "+]" : "]", | |
2116 | dc->op2, dc->pc)); | |
2117 | ||
8170028d | 2118 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 | 2119 | cris_cc_mask(dc, CC_MASK_NZ); |
8170028d TS |
2120 | crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc)); |
2121 | do_postinc(dc, memsize); | |
2122 | return insn_len; | |
2123 | } | |
2124 | ||
2125 | static unsigned int dec_move_mp(DisasContext *dc) | |
2126 | { | |
2127 | int memsize = memsize_zz(dc); | |
2128 | int insn_len = 2; | |
2129 | ||
2130 | DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n", | |
2131 | memsize_char(memsize), | |
2132 | dc->op1, | |
2133 | dc->postinc ? "+]" : "]", | |
2134 | dc->op2)); | |
2135 | ||
8170028d | 2136 | insn_len = dec_prep_alu_m(dc, 0, memsize); |
b41f7df0 EI |
2137 | cris_cc_mask(dc, 0); |
2138 | if (dc->op2 == PR_CCS) { | |
2139 | cris_evaluate_flags(dc); | |
2140 | if (dc->user) { | |
2141 | /* User space is not allowed to touch all flags. */ | |
2142 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f); | |
2143 | tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f); | |
2144 | tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]); | |
2145 | } | |
2146 | } | |
2147 | ||
05ba7d5f | 2148 | t_gen_mov_preg_TN(dc->op2, cpu_T[1]); |
8170028d TS |
2149 | |
2150 | do_postinc(dc, memsize); | |
2151 | return insn_len; | |
2152 | } | |
2153 | ||
2154 | static unsigned int dec_move_pm(DisasContext *dc) | |
2155 | { | |
2156 | int memsize; | |
2157 | ||
2158 | memsize = preg_sizes[dc->op2]; | |
2159 | ||
fd56059f AZ |
2160 | DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n", |
2161 | memsize_char(memsize), | |
2162 | dc->op2, dc->op1, dc->postinc ? "+]" : "]")); | |
8170028d | 2163 | |
fd56059f | 2164 | /* prepare store. Address in T0, value in T1. */ |
05ba7d5f EI |
2165 | t_gen_mov_TN_preg(cpu_T[1], dc->op2); |
2166 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); | |
8170028d | 2167 | gen_store_T0_T1(dc, memsize); |
b41f7df0 | 2168 | cris_cc_mask(dc, 0); |
8170028d TS |
2169 | if (dc->postinc) |
2170 | { | |
05ba7d5f EI |
2171 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize); |
2172 | t_gen_mov_reg_TN(dc->op1, cpu_T[0]); | |
8170028d TS |
2173 | } |
2174 | return 2; | |
2175 | } | |
2176 | ||
2177 | static unsigned int dec_movem_mr(DisasContext *dc) | |
2178 | { | |
2179 | int i; | |
2180 | ||
2181 | DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1, | |
2182 | dc->postinc ? "+]" : "]", dc->op2)); | |
2183 | ||
05ba7d5f EI |
2184 | /* fetch the address into T0 and T1. */ |
2185 | t_gen_mov_TN_reg(cpu_T[1], dc->op1); | |
8170028d TS |
2186 | for (i = 0; i <= dc->op2; i++) { |
2187 | /* Perform the load onto regnum i. Always dword wide. */ | |
05ba7d5f | 2188 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); |
b41f7df0 | 2189 | gen_load(dc, cpu_R[i], cpu_T[1], 4, 0); |
05ba7d5f | 2190 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4); |
8170028d | 2191 | } |
05ba7d5f EI |
2192 | /* writeback the updated pointer value. */ |
2193 | if (dc->postinc) | |
2194 | t_gen_mov_reg_TN(dc->op1, cpu_T[1]); | |
b41f7df0 EI |
2195 | |
2196 | /* gen_load might want to evaluate the previous insns flags. */ | |
2197 | cris_cc_mask(dc, 0); | |
8170028d TS |
2198 | return 2; |
2199 | } | |
2200 | ||
2201 | static unsigned int dec_movem_rm(DisasContext *dc) | |
2202 | { | |
2203 | int i; | |
2204 | ||
2205 | DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1, | |
2206 | dc->postinc ? "+]" : "]")); | |
2207 | ||
8170028d TS |
2208 | for (i = 0; i <= dc->op2; i++) { |
2209 | /* Fetch register i into T1. */ | |
05ba7d5f | 2210 | t_gen_mov_TN_reg(cpu_T[1], i); |
8170028d | 2211 | /* Fetch the address into T0. */ |
05ba7d5f | 2212 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
8170028d | 2213 | /* Displace it. */ |
05ba7d5f | 2214 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4); |
8170028d TS |
2215 | /* Perform the store. */ |
2216 | gen_store_T0_T1(dc, 4); | |
2217 | } | |
2218 | if (dc->postinc) { | |
05ba7d5f EI |
2219 | /* T0 should point to the last written addr, advance one more |
2220 | step. */ | |
2221 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4); | |
8170028d | 2222 | /* writeback the updated pointer value. */ |
05ba7d5f | 2223 | t_gen_mov_reg_TN(dc->op1, cpu_T[0]); |
8170028d | 2224 | } |
b41f7df0 | 2225 | cris_cc_mask(dc, 0); |
8170028d TS |
2226 | return 2; |
2227 | } | |
2228 | ||
2229 | static unsigned int dec_move_rm(DisasContext *dc) | |
2230 | { | |
2231 | int memsize; | |
2232 | ||
2233 | memsize = memsize_zz(dc); | |
2234 | ||
2235 | DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n", | |
2236 | memsize, dc->op2, dc->op1)); | |
2237 | ||
8170028d | 2238 | /* prepare store. */ |
05ba7d5f EI |
2239 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
2240 | t_gen_mov_TN_reg(cpu_T[1], dc->op2); | |
8170028d TS |
2241 | gen_store_T0_T1(dc, memsize); |
2242 | if (dc->postinc) | |
2243 | { | |
05ba7d5f EI |
2244 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize); |
2245 | t_gen_mov_reg_TN(dc->op1, cpu_T[0]); | |
8170028d | 2246 | } |
b41f7df0 | 2247 | cris_cc_mask(dc, 0); |
8170028d TS |
2248 | return 2; |
2249 | } | |
2250 | ||
8170028d TS |
2251 | static unsigned int dec_lapcq(DisasContext *dc) |
2252 | { | |
2253 | DIS(fprintf (logfile, "lapcq %x, $r%u\n", | |
2254 | dc->pc + dc->op1*2, dc->op2)); | |
2255 | cris_cc_mask(dc, 0); | |
05ba7d5f | 2256 | tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2); |
8170028d TS |
2257 | crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4); |
2258 | return 2; | |
2259 | } | |
2260 | ||
2261 | static unsigned int dec_lapc_im(DisasContext *dc) | |
2262 | { | |
2263 | unsigned int rd; | |
2264 | int32_t imm; | |
b41f7df0 | 2265 | int32_t pc; |
8170028d TS |
2266 | |
2267 | rd = dc->op2; | |
2268 | ||
2269 | cris_cc_mask(dc, 0); | |
2270 | imm = ldl_code(dc->pc + 2); | |
2271 | DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2)); | |
b41f7df0 EI |
2272 | |
2273 | pc = dc->pc; | |
2274 | pc += imm; | |
2275 | t_gen_mov_reg_TN(rd, tcg_const_tl(pc)); | |
05ba7d5f | 2276 | return 6; |
8170028d TS |
2277 | } |
2278 | ||
2279 | /* Jump to special reg. */ | |
2280 | static unsigned int dec_jump_p(DisasContext *dc) | |
2281 | { | |
2282 | DIS(fprintf (logfile, "jump $p%u\n", dc->op2)); | |
2283 | cris_cc_mask(dc, 0); | |
b41f7df0 | 2284 | |
05ba7d5f | 2285 | t_gen_mov_TN_preg(cpu_T[0], dc->op2); |
b41f7df0 EI |
2286 | /* rete will often have low bit set to indicate delayslot. */ |
2287 | tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1); | |
8170028d TS |
2288 | cris_prepare_dyn_jmp(dc); |
2289 | return 2; | |
2290 | } | |
2291 | ||
2292 | /* Jump and save. */ | |
2293 | static unsigned int dec_jas_r(DisasContext *dc) | |
2294 | { | |
2295 | DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2)); | |
2296 | cris_cc_mask(dc, 0); | |
b41f7df0 EI |
2297 | /* Store the return address in Pd. */ |
2298 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); | |
2299 | if (dc->op2 > 15) | |
2300 | abort(); | |
2301 | tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4); | |
2302 | ||
8170028d TS |
2303 | cris_prepare_dyn_jmp(dc); |
2304 | return 2; | |
2305 | } | |
2306 | ||
2307 | static unsigned int dec_jas_im(DisasContext *dc) | |
2308 | { | |
2309 | uint32_t imm; | |
2310 | ||
2311 | imm = ldl_code(dc->pc + 2); | |
2312 | ||
2313 | DIS(fprintf (logfile, "jas 0x%x\n", imm)); | |
2314 | cris_cc_mask(dc, 0); | |
2315 | /* Stor the return address in Pd. */ | |
b41f7df0 | 2316 | tcg_gen_movi_tl(env_btarget, imm); |
a825e703 | 2317 | t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8)); |
8170028d TS |
2318 | cris_prepare_dyn_jmp(dc); |
2319 | return 6; | |
2320 | } | |
2321 | ||
2322 | static unsigned int dec_jasc_im(DisasContext *dc) | |
2323 | { | |
2324 | uint32_t imm; | |
2325 | ||
2326 | imm = ldl_code(dc->pc + 2); | |
2327 | ||
2328 | DIS(fprintf (logfile, "jasc 0x%x\n", imm)); | |
2329 | cris_cc_mask(dc, 0); | |
2330 | /* Stor the return address in Pd. */ | |
05ba7d5f | 2331 | tcg_gen_movi_tl(cpu_T[0], imm); |
3157a0a9 | 2332 | t_gen_mov_env_TN(btarget, cpu_T[0]); |
05ba7d5f EI |
2333 | tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4); |
2334 | t_gen_mov_preg_TN(dc->op2, cpu_T[0]); | |
8170028d TS |
2335 | cris_prepare_dyn_jmp(dc); |
2336 | return 6; | |
2337 | } | |
2338 | ||
2339 | static unsigned int dec_jasc_r(DisasContext *dc) | |
2340 | { | |
2341 | DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2)); | |
2342 | cris_cc_mask(dc, 0); | |
2343 | /* Stor the return address in Pd. */ | |
05ba7d5f | 2344 | t_gen_mov_TN_reg(cpu_T[0], dc->op1); |
3157a0a9 | 2345 | t_gen_mov_env_TN(btarget, cpu_T[0]); |
05ba7d5f EI |
2346 | tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4); |
2347 | t_gen_mov_preg_TN(dc->op2, cpu_T[0]); | |
8170028d TS |
2348 | cris_prepare_dyn_jmp(dc); |
2349 | return 2; | |
2350 | } | |
2351 | ||
2352 | static unsigned int dec_bcc_im(DisasContext *dc) | |
2353 | { | |
2354 | int32_t offset; | |
2355 | uint32_t cond = dc->op2; | |
2356 | ||
2357 | offset = ldl_code(dc->pc + 2); | |
2358 | offset = sign_extend(offset, 15); | |
2359 | ||
2360 | DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n", | |
2361 | cc_name(cond), offset, | |
2362 | dc->pc, dc->pc + offset)); | |
2363 | ||
2364 | cris_cc_mask(dc, 0); | |
2365 | /* op2 holds the condition-code. */ | |
2366 | cris_prepare_cc_branch (dc, offset, cond); | |
2367 | return 4; | |
2368 | } | |
2369 | ||
2370 | static unsigned int dec_bas_im(DisasContext *dc) | |
2371 | { | |
2372 | int32_t simm; | |
2373 | ||
2374 | ||
2375 | simm = ldl_code(dc->pc + 2); | |
2376 | ||
2377 | DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2)); | |
2378 | cris_cc_mask(dc, 0); | |
2379 | /* Stor the return address in Pd. */ | |
05ba7d5f | 2380 | tcg_gen_movi_tl(cpu_T[0], dc->pc + simm); |
3157a0a9 | 2381 | t_gen_mov_env_TN(btarget, cpu_T[0]); |
05ba7d5f EI |
2382 | tcg_gen_movi_tl(cpu_T[0], dc->pc + 8); |
2383 | t_gen_mov_preg_TN(dc->op2, cpu_T[0]); | |
8170028d TS |
2384 | cris_prepare_dyn_jmp(dc); |
2385 | return 6; | |
2386 | } | |
2387 | ||
2388 | static unsigned int dec_basc_im(DisasContext *dc) | |
2389 | { | |
2390 | int32_t simm; | |
2391 | simm = ldl_code(dc->pc + 2); | |
2392 | ||
2393 | DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2)); | |
2394 | cris_cc_mask(dc, 0); | |
2395 | /* Stor the return address in Pd. */ | |
05ba7d5f | 2396 | tcg_gen_movi_tl(cpu_T[0], dc->pc + simm); |
3157a0a9 | 2397 | t_gen_mov_env_TN(btarget, cpu_T[0]); |
05ba7d5f EI |
2398 | tcg_gen_movi_tl(cpu_T[0], dc->pc + 12); |
2399 | t_gen_mov_preg_TN(dc->op2, cpu_T[0]); | |
8170028d TS |
2400 | cris_prepare_dyn_jmp(dc); |
2401 | return 6; | |
2402 | } | |
2403 | ||
2404 | static unsigned int dec_rfe_etc(DisasContext *dc) | |
2405 | { | |
2406 | DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n", | |
2407 | dc->opcode, dc->pc, dc->op1, dc->op2)); | |
2408 | ||
2409 | cris_cc_mask(dc, 0); | |
2410 | ||
2411 | if (dc->op2 == 15) /* ignore halt. */ | |
05ba7d5f | 2412 | return 2; |
8170028d TS |
2413 | |
2414 | switch (dc->op2 & 7) { | |
2415 | case 2: | |
2416 | /* rfe. */ | |
2417 | cris_evaluate_flags(dc); | |
2418 | gen_op_ccs_rshift(); | |
b41f7df0 EI |
2419 | /* FIXME: don't set the P-FLAG if R is set. */ |
2420 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG); | |
2421 | /* Debug helper. */ | |
2422 | tcg_gen_helper_0_0(helper_rfe); | |
2423 | dc->is_jmp = DISAS_UPDATE; | |
8170028d TS |
2424 | break; |
2425 | case 5: | |
2426 | /* rfn. */ | |
2427 | BUG(); | |
2428 | break; | |
2429 | case 6: | |
2430 | /* break. */ | |
05ba7d5f | 2431 | tcg_gen_movi_tl(cpu_T[0], dc->pc); |
3157a0a9 | 2432 | t_gen_mov_env_TN(pc, cpu_T[0]); |
8170028d TS |
2433 | /* Breaks start at 16 in the exception vector. */ |
2434 | gen_op_break_im(dc->op1 + 16); | |
b41f7df0 | 2435 | dc->is_jmp = DISAS_UPDATE; |
8170028d TS |
2436 | break; |
2437 | default: | |
2438 | printf ("op2=%x\n", dc->op2); | |
2439 | BUG(); | |
2440 | break; | |
2441 | ||
2442 | } | |
8170028d TS |
2443 | return 2; |
2444 | } | |
2445 | ||
5d4a534d EI |
2446 | static unsigned int dec_ftag_fidx_d_m(DisasContext *dc) |
2447 | { | |
2448 | /* Ignore D-cache flushes. */ | |
2449 | return 2; | |
2450 | } | |
2451 | ||
2452 | static unsigned int dec_ftag_fidx_i_m(DisasContext *dc) | |
2453 | { | |
2454 | /* Ignore I-cache flushes. */ | |
2455 | return 2; | |
2456 | } | |
2457 | ||
8170028d TS |
2458 | static unsigned int dec_null(DisasContext *dc) |
2459 | { | |
2460 | printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n", | |
2461 | dc->pc, dc->opcode, dc->op1, dc->op2); | |
2462 | fflush(NULL); | |
2463 | BUG(); | |
2464 | return 2; | |
2465 | } | |
2466 | ||
2467 | struct decoder_info { | |
2468 | struct { | |
2469 | uint32_t bits; | |
2470 | uint32_t mask; | |
2471 | }; | |
2472 | unsigned int (*dec)(DisasContext *dc); | |
2473 | } decinfo[] = { | |
2474 | /* Order matters here. */ | |
2475 | {DEC_MOVEQ, dec_moveq}, | |
2476 | {DEC_BTSTQ, dec_btstq}, | |
2477 | {DEC_CMPQ, dec_cmpq}, | |
2478 | {DEC_ADDOQ, dec_addoq}, | |
2479 | {DEC_ADDQ, dec_addq}, | |
2480 | {DEC_SUBQ, dec_subq}, | |
2481 | {DEC_ANDQ, dec_andq}, | |
2482 | {DEC_ORQ, dec_orq}, | |
2483 | {DEC_ASRQ, dec_asrq}, | |
2484 | {DEC_LSLQ, dec_lslq}, | |
2485 | {DEC_LSRQ, dec_lsrq}, | |
2486 | {DEC_BCCQ, dec_bccq}, | |
2487 | ||
2488 | {DEC_BCC_IM, dec_bcc_im}, | |
2489 | {DEC_JAS_IM, dec_jas_im}, | |
2490 | {DEC_JAS_R, dec_jas_r}, | |
2491 | {DEC_JASC_IM, dec_jasc_im}, | |
2492 | {DEC_JASC_R, dec_jasc_r}, | |
2493 | {DEC_BAS_IM, dec_bas_im}, | |
2494 | {DEC_BASC_IM, dec_basc_im}, | |
2495 | {DEC_JUMP_P, dec_jump_p}, | |
2496 | {DEC_LAPC_IM, dec_lapc_im}, | |
2497 | {DEC_LAPCQ, dec_lapcq}, | |
2498 | ||
2499 | {DEC_RFE_ETC, dec_rfe_etc}, | |
2500 | {DEC_ADDC_MR, dec_addc_mr}, | |
2501 | ||
2502 | {DEC_MOVE_MP, dec_move_mp}, | |
2503 | {DEC_MOVE_PM, dec_move_pm}, | |
2504 | {DEC_MOVEM_MR, dec_movem_mr}, | |
2505 | {DEC_MOVEM_RM, dec_movem_rm}, | |
2506 | {DEC_MOVE_PR, dec_move_pr}, | |
2507 | {DEC_SCC_R, dec_scc_r}, | |
2508 | {DEC_SETF, dec_setclrf}, | |
2509 | {DEC_CLEARF, dec_setclrf}, | |
2510 | ||
2511 | {DEC_MOVE_SR, dec_move_sr}, | |
2512 | {DEC_MOVE_RP, dec_move_rp}, | |
2513 | {DEC_SWAP_R, dec_swap_r}, | |
2514 | {DEC_ABS_R, dec_abs_r}, | |
2515 | {DEC_LZ_R, dec_lz_r}, | |
2516 | {DEC_MOVE_RS, dec_move_rs}, | |
2517 | {DEC_BTST_R, dec_btst_r}, | |
2518 | {DEC_ADDC_R, dec_addc_r}, | |
2519 | ||
2520 | {DEC_DSTEP_R, dec_dstep_r}, | |
2521 | {DEC_XOR_R, dec_xor_r}, | |
2522 | {DEC_MCP_R, dec_mcp_r}, | |
2523 | {DEC_CMP_R, dec_cmp_r}, | |
2524 | ||
2525 | {DEC_ADDI_R, dec_addi_r}, | |
2526 | {DEC_ADDI_ACR, dec_addi_acr}, | |
2527 | ||
2528 | {DEC_ADD_R, dec_add_r}, | |
2529 | {DEC_SUB_R, dec_sub_r}, | |
2530 | ||
2531 | {DEC_ADDU_R, dec_addu_r}, | |
2532 | {DEC_ADDS_R, dec_adds_r}, | |
2533 | {DEC_SUBU_R, dec_subu_r}, | |
2534 | {DEC_SUBS_R, dec_subs_r}, | |
2535 | {DEC_LSL_R, dec_lsl_r}, | |
2536 | ||
2537 | {DEC_AND_R, dec_and_r}, | |
2538 | {DEC_OR_R, dec_or_r}, | |
2539 | {DEC_BOUND_R, dec_bound_r}, | |
2540 | {DEC_ASR_R, dec_asr_r}, | |
2541 | {DEC_LSR_R, dec_lsr_r}, | |
2542 | ||
2543 | {DEC_MOVU_R, dec_movu_r}, | |
2544 | {DEC_MOVS_R, dec_movs_r}, | |
2545 | {DEC_NEG_R, dec_neg_r}, | |
2546 | {DEC_MOVE_R, dec_move_r}, | |
2547 | ||
5d4a534d EI |
2548 | {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m}, |
2549 | {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m}, | |
8170028d TS |
2550 | |
2551 | {DEC_MULS_R, dec_muls_r}, | |
2552 | {DEC_MULU_R, dec_mulu_r}, | |
2553 | ||
2554 | {DEC_ADDU_M, dec_addu_m}, | |
2555 | {DEC_ADDS_M, dec_adds_m}, | |
2556 | {DEC_SUBU_M, dec_subu_m}, | |
2557 | {DEC_SUBS_M, dec_subs_m}, | |
2558 | ||
2559 | {DEC_CMPU_M, dec_cmpu_m}, | |
2560 | {DEC_CMPS_M, dec_cmps_m}, | |
2561 | {DEC_MOVU_M, dec_movu_m}, | |
2562 | {DEC_MOVS_M, dec_movs_m}, | |
2563 | ||
2564 | {DEC_CMP_M, dec_cmp_m}, | |
2565 | {DEC_ADDO_M, dec_addo_m}, | |
2566 | {DEC_BOUND_M, dec_bound_m}, | |
2567 | {DEC_ADD_M, dec_add_m}, | |
2568 | {DEC_SUB_M, dec_sub_m}, | |
2569 | {DEC_AND_M, dec_and_m}, | |
2570 | {DEC_OR_M, dec_or_m}, | |
2571 | {DEC_MOVE_RM, dec_move_rm}, | |
2572 | {DEC_TEST_M, dec_test_m}, | |
2573 | {DEC_MOVE_MR, dec_move_mr}, | |
2574 | ||
2575 | {{0, 0}, dec_null} | |
2576 | }; | |
2577 | ||
2578 | static inline unsigned int | |
2579 | cris_decoder(DisasContext *dc) | |
2580 | { | |
2581 | unsigned int insn_len = 2; | |
2582 | uint32_t tmp; | |
2583 | int i; | |
2584 | ||
2585 | /* Load a halfword onto the instruction register. */ | |
2586 | tmp = ldl_code(dc->pc); | |
2587 | dc->ir = tmp & 0xffff; | |
2588 | ||
2589 | /* Now decode it. */ | |
2590 | dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11); | |
2591 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3); | |
2592 | dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15); | |
2593 | dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4); | |
2594 | dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5); | |
2595 | dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); | |
2596 | ||
2597 | /* Large switch for all insns. */ | |
2598 | for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) { | |
2599 | if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) | |
2600 | { | |
2601 | insn_len = decinfo[i].dec(dc); | |
2602 | break; | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | return insn_len; | |
2607 | } | |
2608 | ||
2609 | static void check_breakpoint(CPUState *env, DisasContext *dc) | |
2610 | { | |
2611 | int j; | |
2612 | if (env->nb_breakpoints > 0) { | |
2613 | for(j = 0; j < env->nb_breakpoints; j++) { | |
2614 | if (env->breakpoints[j] == dc->pc) { | |
2615 | cris_evaluate_flags (dc); | |
05ba7d5f | 2616 | tcg_gen_movi_tl(cpu_T[0], dc->pc); |
3157a0a9 | 2617 | t_gen_mov_env_TN(pc, cpu_T[0]); |
8170028d TS |
2618 | gen_op_debug(); |
2619 | dc->is_jmp = DISAS_UPDATE; | |
2620 | } | |
2621 | } | |
2622 | } | |
2623 | } | |
2624 | ||
8170028d TS |
2625 | /* generate intermediate code for basic block 'tb'. */ |
2626 | struct DisasContext ctx; | |
2627 | static int | |
2628 | gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, | |
2629 | int search_pc) | |
2630 | { | |
2631 | uint16_t *gen_opc_end; | |
2632 | uint32_t pc_start; | |
2633 | unsigned int insn_len; | |
2634 | int j, lj; | |
2635 | struct DisasContext *dc = &ctx; | |
2636 | uint32_t next_page_start; | |
2637 | ||
a825e703 EI |
2638 | if (!logfile) |
2639 | logfile = stderr; | |
2640 | ||
b41f7df0 EI |
2641 | if (tb->pc & 1) |
2642 | cpu_abort(env, "unaligned pc=%x erp=%x\n", | |
2643 | env->pc, env->pregs[PR_ERP]); | |
8170028d TS |
2644 | pc_start = tb->pc; |
2645 | dc->env = env; | |
2646 | dc->tb = tb; | |
2647 | ||
8170028d | 2648 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
8170028d TS |
2649 | |
2650 | dc->is_jmp = DISAS_NEXT; | |
b41f7df0 | 2651 | dc->ppc = pc_start; |
8170028d TS |
2652 | dc->pc = pc_start; |
2653 | dc->singlestep_enabled = env->singlestep_enabled; | |
b41f7df0 | 2654 | dc->flags_live = 1; |
8170028d TS |
2655 | dc->flagx_live = 0; |
2656 | dc->flags_x = 0; | |
b41f7df0 EI |
2657 | dc->cc_mask = 0; |
2658 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
2659 | ||
2660 | dc->user = env->pregs[PR_CCS] & U_FLAG; | |
2661 | dc->delayed_branch = 0; | |
2662 | ||
2663 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
2664 | fprintf(logfile, | |
2665 | "search=%d pc=%x ccs=%x pid=%x usp=%x\n" | |
2666 | "%x.%x.%x.%x\n" | |
2667 | "%x.%x.%x.%x\n" | |
2668 | "%x.%x.%x.%x\n" | |
2669 | "%x.%x.%x.%x\n", | |
2670 | search_pc, env->pc, env->pregs[PR_CCS], | |
2671 | env->pregs[PR_PID], env->pregs[PR_USP], | |
2672 | env->regs[0], env->regs[1], env->regs[2], env->regs[3], | |
2673 | env->regs[4], env->regs[5], env->regs[6], env->regs[7], | |
2674 | env->regs[8], env->regs[9], | |
2675 | env->regs[10], env->regs[11], | |
2676 | env->regs[12], env->regs[13], | |
2677 | env->regs[14], env->regs[15]); | |
2678 | ||
2679 | } | |
3157a0a9 | 2680 | |
8170028d TS |
2681 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
2682 | lj = -1; | |
2683 | do | |
2684 | { | |
2685 | check_breakpoint(env, dc); | |
4f400ab5 EI |
2686 | if (dc->is_jmp == DISAS_JUMP |
2687 | || dc->is_jmp == DISAS_SWI) | |
8170028d TS |
2688 | goto done; |
2689 | ||
2690 | if (search_pc) { | |
2691 | j = gen_opc_ptr - gen_opc_buf; | |
2692 | if (lj < j) { | |
2693 | lj++; | |
2694 | while (lj < j) | |
2695 | gen_opc_instr_start[lj++] = 0; | |
2696 | } | |
b41f7df0 EI |
2697 | if (dc->delayed_branch == 1) { |
2698 | gen_opc_pc[lj] = dc->ppc | 1; | |
2699 | gen_opc_instr_start[lj] = 0; | |
2700 | } | |
2701 | else { | |
2702 | gen_opc_pc[lj] = dc->pc; | |
2703 | gen_opc_instr_start[lj] = 1; | |
2704 | } | |
8170028d TS |
2705 | } |
2706 | ||
b41f7df0 | 2707 | dc->clear_x = 1; |
8170028d TS |
2708 | insn_len = cris_decoder(dc); |
2709 | STATS(gen_op_exec_insn()); | |
b41f7df0 | 2710 | dc->ppc = dc->pc; |
8170028d | 2711 | dc->pc += insn_len; |
b41f7df0 EI |
2712 | if (dc->clear_x) |
2713 | cris_clear_x_flag(dc); | |
8170028d TS |
2714 | |
2715 | /* Check for delayed branches here. If we do it before | |
2716 | actually genereating any host code, the simulator will just | |
2717 | loop doing nothing for on this program location. */ | |
2718 | if (dc->delayed_branch) { | |
2719 | dc->delayed_branch--; | |
2720 | if (dc->delayed_branch == 0) | |
2721 | { | |
2722 | if (dc->bcc == CC_A) { | |
57fec1fe | 2723 | gen_op_jmp1 (); |
b41f7df0 | 2724 | dc->is_jmp = DISAS_JUMP; |
8170028d TS |
2725 | } |
2726 | else { | |
2727 | /* Conditional jmp. */ | |
2728 | gen_op_cc_jmp (dc->delayed_pc, dc->pc); | |
b41f7df0 | 2729 | dc->is_jmp = DISAS_JUMP; |
8170028d TS |
2730 | } |
2731 | } | |
2732 | } | |
2733 | ||
2734 | if (env->singlestep_enabled) | |
2735 | break; | |
2736 | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end | |
b41f7df0 EI |
2737 | && ((dc->pc < next_page_start) || dc->delayed_branch)); |
2738 | ||
2739 | if (dc->delayed_branch == 1) { | |
2740 | /* Reexecute the last insn. */ | |
2741 | dc->pc = dc->ppc; | |
2742 | } | |
8170028d TS |
2743 | |
2744 | if (!dc->is_jmp) { | |
b41f7df0 EI |
2745 | D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc, |
2746 | dc->is_jmp, dc->delayed_branch)); | |
2747 | /* T0 and env_pc should hold the new pc. */ | |
3157a0a9 | 2748 | tcg_gen_movi_tl(cpu_T[0], dc->pc); |
b41f7df0 | 2749 | tcg_gen_mov_tl(env_pc, cpu_T[0]); |
8170028d TS |
2750 | } |
2751 | ||
2752 | cris_evaluate_flags (dc); | |
2753 | done: | |
2754 | if (__builtin_expect(env->singlestep_enabled, 0)) { | |
2755 | gen_op_debug(); | |
2756 | } else { | |
2757 | switch(dc->is_jmp) { | |
2758 | case DISAS_NEXT: | |
2759 | gen_goto_tb(dc, 1, dc->pc); | |
2760 | break; | |
2761 | default: | |
2762 | case DISAS_JUMP: | |
2763 | case DISAS_UPDATE: | |
2764 | /* indicate that the hash table must be used | |
2765 | to find the next TB */ | |
57fec1fe | 2766 | tcg_gen_exit_tb(0); |
8170028d | 2767 | break; |
4f400ab5 | 2768 | case DISAS_SWI: |
8170028d TS |
2769 | case DISAS_TB_JUMP: |
2770 | /* nothing more to generate */ | |
2771 | break; | |
2772 | } | |
2773 | } | |
2774 | *gen_opc_ptr = INDEX_op_end; | |
2775 | if (search_pc) { | |
2776 | j = gen_opc_ptr - gen_opc_buf; | |
2777 | lj++; | |
2778 | while (lj <= j) | |
2779 | gen_opc_instr_start[lj++] = 0; | |
2780 | } else { | |
2781 | tb->size = dc->pc - pc_start; | |
2782 | } | |
2783 | ||
2784 | #ifdef DEBUG_DISAS | |
2785 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
2786 | fprintf(logfile, "--------------\n"); | |
2787 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
2788 | target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0); | |
b41f7df0 EI |
2789 | fprintf(logfile, "\nisize=%d osize=%d\n", |
2790 | dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); | |
8170028d TS |
2791 | } |
2792 | #endif | |
2793 | return 0; | |
2794 | } | |
2795 | ||
2796 | int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) | |
2797 | { | |
2798 | return gen_intermediate_code_internal(env, tb, 0); | |
2799 | } | |
2800 | ||
2801 | int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) | |
2802 | { | |
2803 | return gen_intermediate_code_internal(env, tb, 1); | |
2804 | } | |
2805 | ||
2806 | void cpu_dump_state (CPUState *env, FILE *f, | |
2807 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
2808 | int flags) | |
2809 | { | |
2810 | int i; | |
2811 | uint32_t srs; | |
2812 | ||
2813 | if (!env || !f) | |
2814 | return; | |
2815 | ||
2816 | cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" | |
2817 | "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n" | |
2818 | "debug=%x %x %x\n", | |
9004627f | 2819 | env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, |
8170028d TS |
2820 | env->cc_op, |
2821 | env->cc_src, env->cc_dest, env->cc_result, env->cc_mask, | |
2822 | env->debug1, env->debug2, env->debug3); | |
2823 | ||
2824 | for (i = 0; i < 16; i++) { | |
2825 | cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); | |
2826 | if ((i + 1) % 4 == 0) | |
2827 | cpu_fprintf(f, "\n"); | |
2828 | } | |
2829 | cpu_fprintf(f, "\nspecial regs:\n"); | |
2830 | for (i = 0; i < 16; i++) { | |
2831 | cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]); | |
2832 | if ((i + 1) % 4 == 0) | |
2833 | cpu_fprintf(f, "\n"); | |
2834 | } | |
9004627f | 2835 | srs = env->pregs[PR_SRS]; |
b41f7df0 | 2836 | cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs); |
8170028d TS |
2837 | if (srs < 256) { |
2838 | for (i = 0; i < 16; i++) { | |
2839 | cpu_fprintf(f, "s%2.2d=%8.8x ", | |
2840 | i, env->sregs[srs][i]); | |
2841 | if ((i + 1) % 4 == 0) | |
2842 | cpu_fprintf(f, "\n"); | |
2843 | } | |
2844 | } | |
2845 | cpu_fprintf(f, "\n\n"); | |
2846 | ||
2847 | } | |
2848 | ||
05ba7d5f EI |
2849 | static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) |
2850 | { | |
2851 | } | |
2852 | ||
aaed909a | 2853 | CPUCRISState *cpu_cris_init (const char *cpu_model) |
8170028d TS |
2854 | { |
2855 | CPUCRISState *env; | |
a825e703 | 2856 | int i; |
8170028d TS |
2857 | |
2858 | env = qemu_mallocz(sizeof(CPUCRISState)); | |
2859 | if (!env) | |
2860 | return NULL; | |
2861 | cpu_exec_init(env); | |
05ba7d5f EI |
2862 | |
2863 | tcg_set_macro_func(&tcg_ctx, tcg_macro_func); | |
2864 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); | |
2865 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
2866 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, | |
2867 | TCG_AREG0, offsetof(CPUState, t0), "T0"); | |
2868 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, | |
2869 | TCG_AREG0, offsetof(CPUState, t1), "T1"); | |
2870 | #else | |
2871 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); | |
2872 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); | |
2873 | #endif | |
2874 | ||
a825e703 EI |
2875 | cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
2876 | offsetof(CPUState, cc_src), "cc_src"); | |
2877 | cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2878 | offsetof(CPUState, cc_dest), | |
2879 | "cc_dest"); | |
2880 | cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2881 | offsetof(CPUState, cc_result), | |
2882 | "cc_result"); | |
2883 | cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2884 | offsetof(CPUState, cc_op), "cc_op"); | |
2885 | cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2886 | offsetof(CPUState, cc_size), | |
2887 | "cc_size"); | |
2888 | cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2889 | offsetof(CPUState, cc_mask), | |
2890 | "cc_mask"); | |
2891 | ||
b41f7df0 EI |
2892 | env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
2893 | offsetof(CPUState, pc), | |
2894 | "pc"); | |
2895 | env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2896 | offsetof(CPUState, btarget), | |
2897 | "btarget"); | |
2898 | ||
a825e703 EI |
2899 | for (i = 0; i < 16; i++) { |
2900 | cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2901 | offsetof(CPUState, regs[i]), | |
2902 | regnames[i]); | |
2903 | } | |
2904 | for (i = 0; i < 16; i++) { | |
2905 | cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, | |
2906 | offsetof(CPUState, pregs[i]), | |
2907 | pregnames[i]); | |
2908 | } | |
2909 | ||
b41f7df0 EI |
2910 | TCG_HELPER(helper_tlb_update); |
2911 | TCG_HELPER(helper_tlb_flush); | |
2912 | TCG_HELPER(helper_rfe); | |
2913 | TCG_HELPER(helper_store); | |
2914 | TCG_HELPER(helper_dump); | |
2915 | TCG_HELPER(helper_dummy); | |
2916 | ||
2917 | TCG_HELPER(helper_evaluate_flags_muls); | |
2918 | TCG_HELPER(helper_evaluate_flags_mulu); | |
2919 | TCG_HELPER(helper_evaluate_flags_mcp); | |
2920 | TCG_HELPER(helper_evaluate_flags_alu_4); | |
2921 | TCG_HELPER(helper_evaluate_flags_move_4); | |
2922 | TCG_HELPER(helper_evaluate_flags_move_2); | |
2923 | TCG_HELPER(helper_evaluate_flags); | |
2924 | ||
8170028d TS |
2925 | cpu_reset(env); |
2926 | return env; | |
2927 | } | |
2928 | ||
2929 | void cpu_reset (CPUCRISState *env) | |
2930 | { | |
2931 | memset(env, 0, offsetof(CPUCRISState, breakpoints)); | |
2932 | tlb_flush(env, 1); | |
b41f7df0 EI |
2933 | |
2934 | #if defined(CONFIG_USER_ONLY) | |
2935 | /* start in user mode with interrupts enabled. */ | |
2936 | env->pregs[PR_CCS] |= U_FLAG | I_FLAG; | |
2937 | #else | |
2938 | env->pregs[PR_CCS] = 0; | |
2939 | #endif | |
8170028d | 2940 | } |
d2856f1a AJ |
2941 | |
2942 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, | |
2943 | unsigned long searched_pc, int pc_pos, void *puc) | |
2944 | { | |
b41f7df0 | 2945 | env->pc = gen_opc_pc[pc_pos]; |
d2856f1a | 2946 | } |