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40e9eddd EI |
1 | /* |
2 | * CRISv10 emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2010 AXIS Communications AB | |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA | |
20 | */ | |
21 | ||
22 | #include "crisv10-decode.h" | |
23 | ||
24 | static const char *regnames_v10[] = | |
25 | { | |
bf76bafa EI |
26 | "$r0", "$r1", "$r2", "$r3", |
27 | "$r4", "$r5", "$r6", "$r7", | |
28 | "$r8", "$r9", "$r10", "$r11", | |
29 | "$r12", "$r13", "$sp", "$pc", | |
40e9eddd EI |
30 | }; |
31 | ||
32 | static const char *pregnames_v10[] = | |
33 | { | |
bf76bafa EI |
34 | "$bz", "$vr", "$p2", "$p3", |
35 | "$wz", "$ccr", "$p6-prefix", "$mof", | |
36 | "$dz", "$ibr", "$irp", "$srp", | |
37 | "$bar", "$dccr", "$brp", "$usp", | |
40e9eddd EI |
38 | }; |
39 | ||
40 | /* We need this table to handle preg-moves with implicit width. */ | |
41 | static int preg_sizes_v10[] = { | |
bf76bafa EI |
42 | 1, /* bz. */ |
43 | 1, /* vr. */ | |
44 | 1, /* pid. */ | |
45 | 1, /* srs. */ | |
46 | 2, /* wz. */ | |
47 | 2, 2, 4, | |
48 | 4, 4, 4, 4, | |
49 | 4, 4, 4, 4, | |
40e9eddd EI |
50 | }; |
51 | ||
52 | static inline int dec10_size(unsigned int size) | |
53 | { | |
54 | size++; | |
55 | if (size == 3) | |
56 | size++; | |
57 | return size; | |
58 | } | |
59 | ||
60 | static inline void cris_illegal_insn(DisasContext *dc) | |
61 | { | |
62 | qemu_log("illegal insn at pc=%x\n", dc->pc); | |
63 | t_gen_raise_exception(EXCP_BREAK); | |
64 | } | |
65 | ||
66 | /* Prefix flag and register are used to handle the more complex | |
67 | addressing modes. */ | |
68 | static void cris_set_prefix(DisasContext *dc) | |
69 | { | |
70 | dc->clear_prefix = 0; | |
71 | dc->tb_flags |= PFIX_FLAG; | |
72 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], PFIX_FLAG); | |
73 | ||
74 | /* prefix insns dont clear the x flag. */ | |
75 | dc->clear_x = 0; | |
76 | cris_lock_irq(dc); | |
77 | } | |
78 | ||
79 | static void crisv10_prepare_memaddr(DisasContext *dc, | |
80 | TCGv addr, unsigned int size) | |
81 | { | |
82 | if (dc->tb_flags & PFIX_FLAG) { | |
83 | tcg_gen_mov_tl(addr, cpu_PR[PR_PREFIX]); | |
84 | } else { | |
85 | tcg_gen_mov_tl(addr, cpu_R[dc->src]); | |
86 | } | |
87 | } | |
88 | ||
89 | static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size) | |
90 | { | |
91 | unsigned int insn_len = 0; | |
92 | ||
93 | if (dc->tb_flags & PFIX_FLAG) { | |
94 | if (dc->mode == CRISV10_MODE_AUTOINC) { | |
95 | tcg_gen_mov_tl(cpu_R[dc->src], cpu_PR[PR_PREFIX]); | |
96 | } | |
97 | } else { | |
98 | if (dc->mode == CRISV10_MODE_AUTOINC) { | |
99 | if (dc->src == 15) { | |
100 | insn_len += size & ~1; | |
101 | } else { | |
102 | tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], size); | |
103 | } | |
104 | } | |
105 | } | |
106 | return insn_len; | |
107 | } | |
108 | ||
109 | static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize, | |
110 | TCGv dst) | |
111 | { | |
bf76bafa EI |
112 | unsigned int rs, rd; |
113 | uint32_t imm; | |
114 | int is_imm; | |
115 | int insn_len = 0; | |
116 | ||
117 | rs = dc->src; | |
118 | rd = dc->dst; | |
119 | is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG); | |
120 | LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n", | |
121 | rs, rd, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG); | |
122 | ||
123 | /* Load [$rs] onto T1. */ | |
124 | if (is_imm) { | |
125 | if (memsize != 4) { | |
126 | if (s_ext) { | |
127 | if (memsize == 1) | |
128 | imm = ldsb_code(dc->pc + 2); | |
40e9eddd | 129 | else |
bf76bafa EI |
130 | imm = ldsw_code(dc->pc + 2); |
131 | } else { | |
132 | if (memsize == 1) | |
133 | imm = ldub_code(dc->pc + 2); | |
134 | else | |
135 | imm = lduw_code(dc->pc + 2); | |
136 | } | |
137 | } else | |
138 | imm = ldl_code(dc->pc + 2); | |
139 | ||
140 | tcg_gen_movi_tl(dst, imm); | |
40e9eddd | 141 | |
bf76bafa EI |
142 | if (dc->mode == CRISV10_MODE_AUTOINC) { |
143 | insn_len += memsize; | |
144 | if (memsize == 1) | |
145 | insn_len++; | |
146 | tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len); | |
40e9eddd | 147 | } |
bf76bafa EI |
148 | } else { |
149 | TCGv addr; | |
150 | ||
151 | addr = tcg_temp_new(); | |
152 | cris_flush_cc_state(dc); | |
153 | crisv10_prepare_memaddr(dc, addr, memsize); | |
154 | gen_load(dc, dst, addr, memsize, 0); | |
155 | if (s_ext) | |
156 | t_gen_sext(dst, dst, memsize); | |
157 | else | |
158 | t_gen_zext(dst, dst, memsize); | |
159 | insn_len += crisv10_post_memaddr(dc, memsize); | |
160 | tcg_temp_free(addr); | |
161 | } | |
162 | ||
163 | if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) { | |
164 | dc->dst = dc->src; | |
165 | } | |
166 | return insn_len; | |
40e9eddd EI |
167 | } |
168 | ||
169 | static unsigned int dec10_quick_imm(DisasContext *dc) | |
170 | { | |
171 | int32_t imm, simm; | |
172 | int op; | |
173 | ||
174 | /* sign extend. */ | |
175 | imm = dc->ir & ((1 << 6) - 1); | |
176 | simm = (int8_t) (imm << 2); | |
177 | simm >>= 2; | |
178 | switch (dc->opcode) { | |
179 | case CRISV10_QIMM_BDAP_R0: | |
180 | case CRISV10_QIMM_BDAP_R1: | |
181 | case CRISV10_QIMM_BDAP_R2: | |
182 | case CRISV10_QIMM_BDAP_R3: | |
183 | simm = (int8_t)dc->ir; | |
184 | LOG_DIS("bdap %d $r%d\n", simm, dc->dst); | |
185 | LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", | |
186 | dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); | |
187 | cris_set_prefix(dc); | |
188 | if (dc->dst == 15) { | |
189 | tcg_gen_movi_tl(cpu_PR[PR_PREFIX], dc->pc + 2 + simm); | |
190 | } else { | |
191 | tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); | |
192 | } | |
193 | break; | |
194 | ||
195 | case CRISV10_QIMM_MOVEQ: | |
196 | LOG_DIS("moveq %d, $r%d\n", simm, dc->dst); | |
197 | ||
198 | cris_cc_mask(dc, CC_MASK_NZVC); | |
199 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], | |
200 | cpu_R[dc->dst], tcg_const_tl(simm), 4); | |
201 | break; | |
202 | case CRISV10_QIMM_CMPQ: | |
203 | LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst); | |
204 | ||
205 | cris_cc_mask(dc, CC_MASK_NZVC); | |
206 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], | |
207 | cpu_R[dc->dst], tcg_const_tl(simm), 4); | |
208 | break; | |
209 | case CRISV10_QIMM_ADDQ: | |
210 | LOG_DIS("addq %d, $r%d\n", imm, dc->dst); | |
211 | ||
212 | cris_cc_mask(dc, CC_MASK_NZVC); | |
213 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], | |
214 | cpu_R[dc->dst], tcg_const_tl(imm), 4); | |
215 | break; | |
216 | case CRISV10_QIMM_ANDQ: | |
217 | LOG_DIS("andq %d, $r%d\n", simm, dc->dst); | |
218 | ||
219 | cris_cc_mask(dc, CC_MASK_NZVC); | |
220 | cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], | |
221 | cpu_R[dc->dst], tcg_const_tl(simm), 4); | |
222 | break; | |
223 | case CRISV10_QIMM_ASHQ: | |
224 | LOG_DIS("ashq %d, $r%d\n", simm, dc->dst); | |
225 | ||
226 | cris_cc_mask(dc, CC_MASK_NZVC); | |
227 | op = imm & (1 << 5); | |
228 | imm &= 0x1f; | |
229 | if (op) { | |
230 | cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst], | |
231 | cpu_R[dc->dst], tcg_const_tl(imm), 4); | |
232 | } else { | |
233 | /* BTST */ | |
234 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
235 | gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst], | |
236 | tcg_const_tl(imm), cpu_PR[PR_CCS]); | |
237 | } | |
238 | break; | |
239 | case CRISV10_QIMM_LSHQ: | |
240 | LOG_DIS("lshq %d, $r%d\n", simm, dc->dst); | |
241 | ||
242 | op = CC_OP_LSL; | |
243 | if (imm & (1 << 5)) { | |
244 | op = CC_OP_LSR; | |
245 | } | |
246 | imm &= 0x1f; | |
247 | cris_cc_mask(dc, CC_MASK_NZVC); | |
248 | cris_alu(dc, op, cpu_R[dc->dst], | |
249 | cpu_R[dc->dst], tcg_const_tl(imm), 4); | |
250 | break; | |
251 | case CRISV10_QIMM_SUBQ: | |
252 | LOG_DIS("subq %d, $r%d\n", imm, dc->dst); | |
253 | ||
254 | cris_cc_mask(dc, CC_MASK_NZVC); | |
255 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], | |
256 | cpu_R[dc->dst], tcg_const_tl(imm), 4); | |
257 | break; | |
258 | case CRISV10_QIMM_ORQ: | |
259 | LOG_DIS("andq %d, $r%d\n", simm, dc->dst); | |
260 | ||
261 | cris_cc_mask(dc, CC_MASK_NZVC); | |
262 | cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], | |
263 | cpu_R[dc->dst], tcg_const_tl(simm), 4); | |
264 | break; | |
265 | ||
266 | case CRISV10_QIMM_BCC_R0: | |
267 | if (!dc->ir) { | |
268 | cpu_abort(dc->env, "opcode zero\n"); | |
269 | } | |
270 | case CRISV10_QIMM_BCC_R1: | |
271 | case CRISV10_QIMM_BCC_R2: | |
272 | case CRISV10_QIMM_BCC_R3: | |
273 | imm = dc->ir & 0xff; | |
274 | /* bit 0 is a sign bit. */ | |
275 | if (imm & 1) { | |
276 | imm |= 0xffffff00; /* sign extend. */ | |
277 | imm &= ~1; /* get rid of the sign bit. */ | |
278 | } | |
279 | imm += 2; | |
280 | LOG_DIS("b%s %d\n", cc_name(dc->cond), imm); | |
281 | ||
282 | cris_cc_mask(dc, 0); | |
283 | cris_prepare_cc_branch(dc, imm, dc->cond); | |
284 | break; | |
285 | ||
286 | default: | |
287 | LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", | |
288 | dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); | |
289 | assert(0); | |
290 | break; | |
291 | } | |
292 | return 2; | |
293 | } | |
294 | ||
295 | static unsigned int dec10_setclrf(DisasContext *dc) | |
296 | { | |
297 | uint32_t flags; | |
298 | unsigned int set = ~dc->opcode & 1; | |
299 | ||
300 | flags = EXTRACT_FIELD(dc->ir, 0, 3) | |
301 | | (EXTRACT_FIELD(dc->ir, 12, 15) << 4); | |
302 | LOG_DIS("%s set=%d flags=%x\n", __func__, set, flags); | |
303 | ||
304 | ||
305 | if (flags & X_FLAG) { | |
306 | dc->flagx_known = 1; | |
307 | if (set) | |
308 | dc->flags_x = X_FLAG; | |
309 | else | |
310 | dc->flags_x = 0; | |
311 | } | |
312 | ||
313 | cris_evaluate_flags (dc); | |
314 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
315 | cris_update_cc_x(dc); | |
316 | tcg_gen_movi_tl(cc_op, dc->cc_op); | |
317 | ||
318 | if (set) { | |
319 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); | |
320 | } else { | |
321 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); | |
322 | } | |
323 | ||
324 | dc->flags_uptodate = 1; | |
325 | dc->clear_x = 0; | |
326 | cris_lock_irq(dc); | |
327 | return 2; | |
328 | } | |
329 | ||
330 | static inline void dec10_reg_prep_sext(DisasContext *dc, int size, int sext, | |
331 | TCGv dd, TCGv ds, TCGv sd, TCGv ss) | |
332 | { | |
333 | if (sext) { | |
334 | t_gen_sext(dd, sd, size); | |
335 | t_gen_sext(ds, ss, size); | |
336 | } else { | |
337 | t_gen_zext(dd, sd, size); | |
338 | t_gen_zext(ds, ss, size); | |
339 | } | |
340 | } | |
341 | ||
342 | static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext) | |
343 | { | |
344 | TCGv t[2]; | |
345 | ||
346 | t[0] = tcg_temp_new(); | |
347 | t[1] = tcg_temp_new(); | |
348 | dec10_reg_prep_sext(dc, size, sext, | |
349 | t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); | |
350 | ||
351 | if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) { | |
352 | tcg_gen_andi_tl(t[1], t[1], 63); | |
353 | } | |
354 | ||
355 | assert(dc->dst != 15); | |
356 | cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size); | |
357 | tcg_temp_free(t[0]); | |
358 | tcg_temp_free(t[1]); | |
359 | } | |
360 | ||
361 | static void dec10_reg_bound(DisasContext *dc, int size) | |
362 | { | |
363 | TCGv t; | |
364 | ||
365 | t = tcg_temp_local_new(); | |
366 | t_gen_zext(t, cpu_R[dc->src], size); | |
367 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); | |
368 | tcg_temp_free(t); | |
369 | } | |
370 | ||
371 | static void dec10_reg_mul(DisasContext *dc, int size, int sext) | |
372 | { | |
373 | int op = sext ? CC_OP_MULS : CC_OP_MULU; | |
374 | TCGv t[2]; | |
375 | ||
376 | t[0] = tcg_temp_new(); | |
377 | t[1] = tcg_temp_new(); | |
378 | dec10_reg_prep_sext(dc, size, sext, | |
379 | t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); | |
380 | ||
381 | cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4); | |
382 | ||
383 | tcg_temp_free(t[0]); | |
384 | tcg_temp_free(t[1]); | |
385 | } | |
386 | ||
387 | ||
388 | static void dec10_reg_movs(DisasContext *dc) | |
389 | { | |
390 | int size = (dc->size & 1) + 1; | |
391 | TCGv t; | |
392 | ||
393 | LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); | |
394 | cris_cc_mask(dc, CC_MASK_NZVC); | |
395 | ||
396 | t = tcg_temp_new(); | |
397 | if (dc->ir & 32) | |
398 | t_gen_sext(t, cpu_R[dc->src], size); | |
399 | else | |
400 | t_gen_zext(t, cpu_R[dc->src], size); | |
401 | ||
402 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); | |
403 | tcg_temp_free(t); | |
404 | } | |
405 | ||
406 | static void dec10_reg_alux(DisasContext *dc, int op) | |
407 | { | |
408 | int size = (dc->size & 1) + 1; | |
409 | TCGv t; | |
410 | ||
411 | LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); | |
412 | cris_cc_mask(dc, CC_MASK_NZVC); | |
413 | ||
414 | t = tcg_temp_new(); | |
415 | if (dc->ir & 32) | |
416 | t_gen_sext(t, cpu_R[dc->src], size); | |
417 | else | |
418 | t_gen_zext(t, cpu_R[dc->src], size); | |
419 | ||
420 | cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); | |
421 | tcg_temp_free(t); | |
422 | } | |
423 | ||
424 | static void dec10_reg_mov_pr(DisasContext *dc) | |
425 | { | |
426 | LOG_DIS("move p%d r%d sz=%d\n", dc->dst, dc->src, preg_sizes_v10[dc->dst]); | |
427 | cris_lock_irq(dc); | |
428 | if (dc->src == 15) { | |
429 | tcg_gen_mov_tl(env_btarget, cpu_PR[dc->dst]); | |
430 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
431 | return; | |
432 | } | |
433 | if (dc->dst == PR_CCS) { | |
434 | cris_evaluate_flags(dc); | |
435 | } | |
436 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], | |
437 | cpu_R[dc->src], cpu_PR[dc->dst], preg_sizes_v10[dc->dst]); | |
438 | } | |
439 | ||
440 | static void dec10_reg_abs(DisasContext *dc) | |
441 | { | |
bf76bafa | 442 | TCGv t0; |
40e9eddd | 443 | |
bf76bafa | 444 | LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst); |
40e9eddd | 445 | |
bf76bafa EI |
446 | assert(dc->dst != 15); |
447 | t0 = tcg_temp_new(); | |
448 | tcg_gen_sari_tl(t0, cpu_R[dc->src], 31); | |
449 | tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0); | |
450 | tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0); | |
40e9eddd | 451 | |
bf76bafa EI |
452 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4); |
453 | tcg_temp_free(t0); | |
40e9eddd EI |
454 | } |
455 | ||
456 | static void dec10_reg_swap(DisasContext *dc) | |
457 | { | |
458 | TCGv t0; | |
459 | ||
460 | LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst); | |
461 | ||
462 | cris_cc_mask(dc, CC_MASK_NZVC); | |
463 | t0 = tcg_temp_new(); | |
464 | t_gen_mov_TN_reg(t0, dc->src); | |
465 | if (dc->dst & 8) | |
466 | tcg_gen_not_tl(t0, t0); | |
467 | if (dc->dst & 4) | |
468 | t_gen_swapw(t0, t0); | |
469 | if (dc->dst & 2) | |
470 | t_gen_swapb(t0, t0); | |
471 | if (dc->dst & 1) | |
472 | t_gen_swapr(t0, t0); | |
473 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4); | |
474 | tcg_temp_free(t0); | |
475 | } | |
476 | ||
477 | static void dec10_reg_scc(DisasContext *dc) | |
478 | { | |
bf76bafa | 479 | int cond = dc->dst; |
40e9eddd | 480 | |
bf76bafa | 481 | LOG_DIS("s%s $r%u\n", cc_name(cond), dc->src); |
40e9eddd | 482 | |
bf76bafa EI |
483 | if (cond != CC_A) |
484 | { | |
485 | int l1; | |
40e9eddd | 486 | |
bf76bafa EI |
487 | gen_tst_cc (dc, cpu_R[dc->src], cond); |
488 | l1 = gen_new_label(); | |
489 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->src], 0, l1); | |
490 | tcg_gen_movi_tl(cpu_R[dc->src], 1); | |
491 | gen_set_label(l1); | |
492 | } else { | |
493 | tcg_gen_movi_tl(cpu_R[dc->src], 1); | |
494 | } | |
40e9eddd | 495 | |
bf76bafa | 496 | cris_cc_mask(dc, 0); |
40e9eddd EI |
497 | } |
498 | ||
499 | static unsigned int dec10_reg(DisasContext *dc) | |
500 | { | |
501 | TCGv t; | |
502 | unsigned int insn_len = 2; | |
503 | unsigned int size = dec10_size(dc->size); | |
504 | unsigned int tmp; | |
505 | ||
506 | if (dc->size != 3) { | |
507 | switch (dc->opcode) { | |
508 | case CRISV10_REG_MOVE_R: | |
509 | LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst); | |
510 | cris_cc_mask(dc, CC_MASK_NZVC); | |
511 | dec10_reg_alu(dc, CC_OP_MOVE, size, 0); | |
512 | if (dc->dst == 15) { | |
513 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); | |
514 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
515 | dc->delayed_branch = 1; | |
516 | } | |
517 | break; | |
518 | case CRISV10_REG_MOVX: | |
519 | cris_cc_mask(dc, CC_MASK_NZVC); | |
520 | dec10_reg_movs(dc); | |
521 | break; | |
522 | case CRISV10_REG_ADDX: | |
523 | cris_cc_mask(dc, CC_MASK_NZVC); | |
524 | dec10_reg_alux(dc, CC_OP_ADD); | |
525 | break; | |
526 | case CRISV10_REG_SUBX: | |
527 | cris_cc_mask(dc, CC_MASK_NZVC); | |
528 | dec10_reg_alux(dc, CC_OP_SUB); | |
529 | break; | |
530 | case CRISV10_REG_ADD: | |
531 | LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
532 | cris_cc_mask(dc, CC_MASK_NZVC); | |
533 | dec10_reg_alu(dc, CC_OP_ADD, size, 0); | |
534 | break; | |
535 | case CRISV10_REG_SUB: | |
536 | LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
537 | cris_cc_mask(dc, CC_MASK_NZVC); | |
538 | dec10_reg_alu(dc, CC_OP_SUB, size, 0); | |
539 | break; | |
540 | case CRISV10_REG_CMP: | |
541 | LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
542 | cris_cc_mask(dc, CC_MASK_NZVC); | |
543 | dec10_reg_alu(dc, CC_OP_CMP, size, 0); | |
544 | break; | |
545 | case CRISV10_REG_BOUND: | |
546 | LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
547 | cris_cc_mask(dc, CC_MASK_NZVC); | |
548 | dec10_reg_bound(dc, size); | |
549 | break; | |
550 | case CRISV10_REG_AND: | |
551 | LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
552 | cris_cc_mask(dc, CC_MASK_NZVC); | |
553 | dec10_reg_alu(dc, CC_OP_AND, size, 0); | |
554 | break; | |
555 | case CRISV10_REG_ADDI: | |
556 | if (dc->src == 15) { | |
557 | /* nop. */ | |
558 | return 2; | |
559 | } | |
560 | t = tcg_temp_new(); | |
561 | LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size); | |
562 | tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3); | |
563 | tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t); | |
564 | tcg_temp_free(t); | |
565 | break; | |
566 | case CRISV10_REG_LSL: | |
567 | LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
568 | cris_cc_mask(dc, CC_MASK_NZVC); | |
569 | dec10_reg_alu(dc, CC_OP_LSL, size, 0); | |
570 | break; | |
571 | case CRISV10_REG_LSR: | |
572 | LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
573 | cris_cc_mask(dc, CC_MASK_NZVC); | |
574 | dec10_reg_alu(dc, CC_OP_LSR, size, 0); | |
575 | break; | |
576 | case CRISV10_REG_ASR: | |
577 | LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
578 | cris_cc_mask(dc, CC_MASK_NZVC); | |
579 | dec10_reg_alu(dc, CC_OP_ASR, size, 1); | |
580 | break; | |
581 | case CRISV10_REG_OR: | |
582 | LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
583 | cris_cc_mask(dc, CC_MASK_NZVC); | |
584 | dec10_reg_alu(dc, CC_OP_OR, size, 0); | |
585 | break; | |
586 | case CRISV10_REG_NEG: | |
587 | LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
588 | cris_cc_mask(dc, CC_MASK_NZVC); | |
589 | dec10_reg_alu(dc, CC_OP_NEG, size, 0); | |
590 | break; | |
591 | case CRISV10_REG_BIAP: | |
592 | LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc, | |
593 | dc->opcode, dc->src, dc->dst, size); | |
594 | switch (size) { | |
595 | case 4: tmp = 2; break; | |
596 | case 2: tmp = 1; break; | |
597 | case 1: tmp = 0; break; | |
598 | default: assert(0); break; | |
599 | } | |
600 | ||
601 | t = tcg_temp_new(); | |
602 | tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp); | |
603 | if (dc->src == 15) { | |
604 | tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1); | |
605 | } else { | |
606 | tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t); | |
607 | } | |
608 | tcg_temp_free(t); | |
609 | cris_set_prefix(dc); | |
610 | break; | |
611 | ||
612 | default: | |
613 | LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, | |
614 | dc->opcode, dc->src, dc->dst); | |
615 | assert(0); | |
616 | break; | |
617 | } | |
618 | } else { | |
619 | switch (dc->opcode) { | |
620 | case CRISV10_REG_MOVX: | |
621 | cris_cc_mask(dc, CC_MASK_NZVC); | |
622 | dec10_reg_movs(dc); | |
623 | break; | |
624 | case CRISV10_REG_ADDX: | |
625 | cris_cc_mask(dc, CC_MASK_NZVC); | |
626 | dec10_reg_alux(dc, CC_OP_ADD); | |
627 | break; | |
628 | case CRISV10_REG_SUBX: | |
629 | cris_cc_mask(dc, CC_MASK_NZVC); | |
630 | dec10_reg_alux(dc, CC_OP_SUB); | |
631 | break; | |
632 | case CRISV10_REG_MOVE_SPR_R: | |
633 | cris_evaluate_flags(dc); | |
634 | cris_cc_mask(dc, 0); | |
635 | dec10_reg_mov_pr(dc); | |
636 | break; | |
637 | case CRISV10_REG_MOVE_R_SPR: | |
638 | LOG_DIS("move r%d p%d\n", dc->src, dc->dst); | |
639 | cris_evaluate_flags(dc); | |
640 | if (dc->src != 11) /* fast for srp. */ | |
641 | dc->cpustate_changed = 1; | |
642 | t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]); | |
643 | break; | |
644 | case CRISV10_REG_SETF: | |
645 | case CRISV10_REG_CLEARF: | |
646 | dec10_setclrf(dc); | |
647 | break; | |
648 | case CRISV10_REG_SWAP: | |
649 | dec10_reg_swap(dc); | |
650 | break; | |
651 | case CRISV10_REG_ABS: | |
652 | cris_cc_mask(dc, CC_MASK_NZVC); | |
653 | dec10_reg_abs(dc); | |
654 | break; | |
655 | case CRISV10_REG_LZ: | |
656 | LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
657 | cris_cc_mask(dc, CC_MASK_NZVC); | |
658 | dec10_reg_alu(dc, CC_OP_LZ, 4, 0); | |
659 | break; | |
660 | case CRISV10_REG_XOR: | |
661 | LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
662 | cris_cc_mask(dc, CC_MASK_NZVC); | |
663 | dec10_reg_alu(dc, CC_OP_XOR, 4, 0); | |
664 | break; | |
665 | case CRISV10_REG_BTST: | |
666 | LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
667 | cris_cc_mask(dc, CC_MASK_NZVC); | |
668 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); | |
669 | gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst], | |
670 | cpu_R[dc->src], cpu_PR[PR_CCS]); | |
671 | break; | |
672 | case CRISV10_REG_DSTEP: | |
673 | LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
674 | cris_cc_mask(dc, CC_MASK_NZVC); | |
675 | cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst], | |
676 | cpu_R[dc->dst], cpu_R[dc->src], 4); | |
677 | break; | |
678 | case CRISV10_REG_MSTEP: | |
679 | LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); | |
680 | cris_evaluate_flags(dc); | |
681 | cris_cc_mask(dc, CC_MASK_NZVC); | |
682 | cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst], | |
683 | cpu_R[dc->dst], cpu_R[dc->src], 4); | |
684 | break; | |
685 | case CRISV10_REG_SCC: | |
686 | dec10_reg_scc(dc); | |
687 | break; | |
688 | default: | |
689 | LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, | |
690 | dc->opcode, dc->src, dc->dst); | |
691 | assert(0); | |
692 | break; | |
693 | } | |
694 | } | |
695 | return insn_len; | |
696 | } | |
697 | ||
698 | static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size) | |
699 | { | |
700 | unsigned int insn_len = 2; | |
701 | TCGv t; | |
702 | ||
703 | LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__, | |
704 | size, dc->src, dc->dst); | |
705 | ||
706 | cris_cc_mask(dc, CC_MASK_NZVC); | |
707 | t = tcg_temp_new(); | |
708 | insn_len += dec10_prep_move_m(dc, 0, size, t); | |
709 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size); | |
710 | if (dc->dst == 15) { | |
711 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); | |
712 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
713 | dc->delayed_branch = 1; | |
714 | return insn_len; | |
715 | } | |
716 | ||
717 | tcg_temp_free(t); | |
718 | return insn_len; | |
719 | } | |
720 | ||
721 | static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size) | |
722 | { | |
723 | unsigned int insn_len = 2; | |
724 | TCGv addr; | |
725 | ||
726 | LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst); | |
727 | addr = tcg_temp_new(); | |
728 | crisv10_prepare_memaddr(dc, addr, size); | |
729 | gen_store(dc, addr, cpu_R[dc->dst], size); | |
730 | insn_len += crisv10_post_memaddr(dc, size); | |
731 | ||
732 | return insn_len; | |
733 | } | |
734 | ||
735 | static unsigned int dec10_ind_move_m_pr(DisasContext *dc) | |
736 | { | |
737 | unsigned int insn_len = 2, rd = dc->dst; | |
738 | TCGv t, addr; | |
739 | ||
740 | LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); | |
741 | cris_lock_irq(dc); | |
742 | ||
743 | addr = tcg_temp_new(); | |
744 | t = tcg_temp_new(); | |
745 | insn_len += dec10_prep_move_m(dc, 0, 4, t); | |
746 | if (rd == 15) { | |
747 | tcg_gen_mov_tl(env_btarget, t); | |
748 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
749 | dc->delayed_branch = 1; | |
750 | return insn_len; | |
751 | } | |
752 | ||
753 | tcg_gen_mov_tl(cpu_PR[rd], t); | |
754 | dc->cpustate_changed = 1; | |
755 | tcg_temp_free(addr); | |
756 | tcg_temp_free(t); | |
757 | return insn_len; | |
758 | } | |
759 | ||
760 | static unsigned int dec10_ind_move_pr_m(DisasContext *dc) | |
761 | { | |
762 | unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst]; | |
763 | TCGv addr, t0; | |
764 | ||
765 | LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); | |
766 | ||
767 | addr = tcg_temp_new(); | |
768 | crisv10_prepare_memaddr(dc, addr, size); | |
769 | if (dc->dst == PR_CCS) { | |
770 | t0 = tcg_temp_new(); | |
771 | cris_evaluate_flags(dc); | |
772 | tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); | |
773 | gen_store(dc, addr, t0, size); | |
774 | tcg_temp_free(t0); | |
775 | } else { | |
776 | gen_store(dc, addr, cpu_PR[dc->dst], size); | |
777 | } | |
778 | t0 = tcg_temp_new(); | |
779 | insn_len += crisv10_post_memaddr(dc, size); | |
780 | cris_lock_irq(dc); | |
781 | ||
782 | return insn_len; | |
783 | } | |
784 | ||
785 | static void dec10_movem_r_m(DisasContext *dc) | |
786 | { | |
787 | int i, pfix = dc->tb_flags & PFIX_FLAG; | |
788 | TCGv addr, t0; | |
789 | ||
790 | LOG_DIS("%s r%d, [r%d] pi=%d ir=%x\n", __func__, | |
791 | dc->dst, dc->src, dc->postinc, dc->ir); | |
792 | ||
793 | addr = tcg_temp_new(); | |
794 | t0 = tcg_temp_new(); | |
795 | crisv10_prepare_memaddr(dc, addr, 4); | |
796 | tcg_gen_mov_tl(t0, addr); | |
797 | for (i = dc->dst; i >= 0; i--) { | |
798 | if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) { | |
799 | gen_store(dc, addr, t0, 4); | |
800 | } else { | |
801 | gen_store(dc, addr, cpu_R[i], 4); | |
802 | } | |
803 | tcg_gen_addi_tl(addr, addr, 4); | |
804 | } | |
805 | ||
806 | if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { | |
807 | tcg_gen_mov_tl(cpu_R[dc->src], t0); | |
808 | } | |
809 | ||
810 | if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { | |
811 | tcg_gen_mov_tl(cpu_R[dc->src], addr); | |
812 | } | |
813 | tcg_temp_free(addr); | |
814 | tcg_temp_free(t0); | |
815 | } | |
816 | ||
817 | static void dec10_movem_m_r(DisasContext *dc) | |
818 | { | |
819 | int i, pfix = dc->tb_flags & PFIX_FLAG; | |
820 | TCGv addr, t0; | |
821 | ||
822 | LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__, | |
823 | dc->src, dc->dst, dc->postinc, dc->ir); | |
824 | ||
825 | addr = tcg_temp_new(); | |
826 | t0 = tcg_temp_new(); | |
827 | crisv10_prepare_memaddr(dc, addr, 4); | |
828 | tcg_gen_mov_tl(t0, addr); | |
829 | for (i = dc->dst; i >= 0; i--) { | |
830 | gen_load(dc, cpu_R[i], addr, 4, 0); | |
831 | tcg_gen_addi_tl(addr, addr, 4); | |
832 | } | |
833 | ||
834 | if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { | |
835 | tcg_gen_mov_tl(cpu_R[dc->src], t0); | |
836 | } | |
837 | ||
40e9eddd EI |
838 | if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { |
839 | tcg_gen_mov_tl(cpu_R[dc->src], addr); | |
840 | } | |
841 | tcg_temp_free(addr); | |
842 | tcg_temp_free(t0); | |
843 | } | |
844 | ||
845 | static int dec10_ind_alu(DisasContext *dc, int op, unsigned int size) | |
846 | { | |
847 | int insn_len = 0; | |
848 | int rd = dc->dst; | |
849 | TCGv t[2]; | |
850 | ||
851 | cris_alu_m_alloc_temps(t); | |
852 | insn_len += dec10_prep_move_m(dc, 0, size, t[0]); | |
853 | cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t[0], size); | |
854 | if (dc->dst == 15) { | |
855 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); | |
856 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
857 | dc->delayed_branch = 1; | |
858 | return insn_len; | |
859 | } | |
860 | ||
861 | cris_alu_m_free_temps(t); | |
862 | ||
863 | return insn_len; | |
864 | } | |
865 | ||
866 | static int dec10_ind_bound(DisasContext *dc, unsigned int size) | |
867 | { | |
868 | int insn_len = 0; | |
869 | int rd = dc->dst; | |
870 | TCGv t; | |
871 | ||
872 | t = tcg_temp_local_new(); | |
873 | insn_len += dec10_prep_move_m(dc, 0, size, t); | |
874 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4); | |
875 | if (dc->dst == 15) { | |
876 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); | |
877 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
878 | dc->delayed_branch = 1; | |
879 | return insn_len; | |
880 | } | |
881 | ||
882 | tcg_temp_free(t); | |
883 | return insn_len; | |
884 | } | |
885 | ||
886 | static int dec10_alux_m(DisasContext *dc, int op) | |
887 | { | |
888 | unsigned int size = (dc->size & 1) ? 2 : 1; | |
889 | unsigned int sx = !!(dc->size & 2); | |
890 | int insn_len = 2; | |
891 | int rd = dc->dst; | |
892 | TCGv t; | |
893 | ||
894 | LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst); | |
895 | ||
896 | t = tcg_temp_new(); | |
897 | ||
898 | cris_cc_mask(dc, CC_MASK_NZVC); | |
899 | insn_len += dec10_prep_move_m(dc, sx, size, t); | |
900 | cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4); | |
901 | if (dc->dst == 15) { | |
902 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); | |
903 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
904 | dc->delayed_branch = 1; | |
905 | return insn_len; | |
906 | } | |
907 | ||
908 | tcg_temp_free(t); | |
909 | return insn_len; | |
910 | } | |
911 | ||
912 | static int dec10_dip(DisasContext *dc) | |
913 | { | |
914 | int insn_len = 2; | |
915 | uint32_t imm; | |
916 | ||
917 | LOG_DIS("dip pc=%x opcode=%d r%d r%d\n", | |
918 | dc->pc, dc->opcode, dc->src, dc->dst); | |
919 | if (dc->src == 15) { | |
920 | imm = ldl_code(dc->pc + 2); | |
921 | tcg_gen_movi_tl(cpu_PR[PR_PREFIX], imm); | |
922 | if (dc->postinc) | |
923 | insn_len += 4; | |
924 | tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len - 2); | |
925 | } else { | |
926 | gen_load(dc, cpu_PR[PR_PREFIX], cpu_R[dc->src], 4, 0); | |
927 | if (dc->postinc) | |
928 | tcg_gen_addi_tl(cpu_R[dc->src], cpu_R[dc->src], 4); | |
929 | } | |
930 | ||
931 | cris_set_prefix(dc); | |
932 | return insn_len; | |
933 | } | |
934 | ||
935 | static int dec10_bdap_m(DisasContext *dc, int size) | |
936 | { | |
937 | int insn_len = 2; | |
938 | int rd = dc->dst; | |
939 | ||
940 | LOG_DIS("bdap_m pc=%x opcode=%d r%d r%d sz=%d\n", | |
941 | dc->pc, dc->opcode, dc->src, dc->dst, size); | |
942 | ||
943 | assert(dc->dst != 15); | |
944 | #if 0 | |
945 | /* 8bit embedded offset? */ | |
946 | if (!dc->postinc && (dc->ir & (1 << 11))) { | |
947 | int simm = dc->ir & 0xff; | |
948 | ||
949 | // assert(0); | |
950 | /* sign extended. */ | |
951 | simm = (int8_t)simm; | |
952 | ||
953 | tcg_gen_addi_tl(cpu_PR[PR_PREFIX], cpu_R[dc->dst], simm); | |
954 | ||
955 | cris_set_prefix(dc); | |
956 | return insn_len; | |
957 | } | |
958 | #endif | |
959 | /* Now the rest of the modes are truely indirect. */ | |
960 | insn_len += dec10_prep_move_m(dc, 1, size, cpu_PR[PR_PREFIX]); | |
961 | tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]); | |
962 | cris_set_prefix(dc); | |
963 | return insn_len; | |
964 | } | |
965 | ||
966 | static unsigned int dec10_ind(DisasContext *dc) | |
967 | { | |
968 | unsigned int insn_len = 2; | |
969 | unsigned int size = dec10_size(dc->size); | |
970 | uint32_t imm; | |
971 | int32_t simm; | |
972 | TCGv t[2]; | |
973 | ||
974 | if (dc->size != 3) { | |
975 | switch (dc->opcode) { | |
976 | case CRISV10_IND_MOVE_M_R: | |
977 | return dec10_ind_move_m_r(dc, size); | |
978 | break; | |
979 | case CRISV10_IND_MOVE_R_M: | |
980 | return dec10_ind_move_r_m(dc, size); | |
981 | break; | |
982 | case CRISV10_IND_CMP: | |
983 | LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst); | |
984 | cris_cc_mask(dc, CC_MASK_NZVC); | |
985 | insn_len += dec10_ind_alu(dc, CC_OP_CMP, size); | |
986 | break; | |
987 | case CRISV10_IND_TEST: | |
988 | LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst); | |
989 | ||
990 | cris_evaluate_flags(dc); | |
991 | cris_cc_mask(dc, CC_MASK_NZVC); | |
992 | cris_alu_m_alloc_temps(t); | |
993 | insn_len += dec10_prep_move_m(dc, 0, size, t[0]); | |
994 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); | |
995 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], | |
996 | t[0], tcg_const_tl(0), size); | |
997 | cris_alu_m_free_temps(t); | |
998 | break; | |
999 | case CRISV10_IND_ADD: | |
1000 | LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst); | |
1001 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1002 | insn_len += dec10_ind_alu(dc, CC_OP_ADD, size); | |
1003 | break; | |
1004 | case CRISV10_IND_SUB: | |
1005 | LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst); | |
1006 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1007 | insn_len += dec10_ind_alu(dc, CC_OP_SUB, size); | |
1008 | break; | |
1009 | case CRISV10_IND_BOUND: | |
1010 | LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst); | |
1011 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1012 | insn_len += dec10_ind_bound(dc, size); | |
1013 | break; | |
1014 | case CRISV10_IND_AND: | |
1015 | LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst); | |
1016 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1017 | insn_len += dec10_ind_alu(dc, CC_OP_AND, size); | |
1018 | break; | |
1019 | case CRISV10_IND_OR: | |
1020 | LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst); | |
1021 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1022 | insn_len += dec10_ind_alu(dc, CC_OP_OR, size); | |
1023 | break; | |
1024 | case CRISV10_IND_MOVX: | |
1025 | insn_len = dec10_alux_m(dc, CC_OP_MOVE); | |
1026 | break; | |
1027 | case CRISV10_IND_ADDX: | |
1028 | insn_len = dec10_alux_m(dc, CC_OP_ADD); | |
1029 | break; | |
1030 | case CRISV10_IND_SUBX: | |
1031 | insn_len = dec10_alux_m(dc, CC_OP_SUB); | |
1032 | break; | |
1033 | case CRISV10_IND_CMPX: | |
1034 | insn_len = dec10_alux_m(dc, CC_OP_CMP); | |
1035 | break; | |
1036 | case CRISV10_IND_MUL: | |
1037 | /* This is a reg insn coded in the mem indir space. */ | |
1038 | LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode); | |
1039 | cris_cc_mask(dc, CC_MASK_NZVC); | |
1040 | dec10_reg_mul(dc, size, dc->ir & (1 << 10)); | |
1041 | break; | |
1042 | case CRISV10_IND_BDAP_M: | |
1043 | insn_len = dec10_bdap_m(dc, size); | |
1044 | break; | |
1045 | default: | |
1046 | LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", | |
1047 | dc->pc, size, dc->opcode, dc->src, dc->dst); | |
1048 | assert(0); | |
1049 | break; | |
1050 | } | |
1051 | return insn_len; | |
1052 | } | |
1053 | ||
1054 | switch (dc->opcode) { | |
1055 | case CRISV10_IND_MOVE_M_SPR: | |
1056 | insn_len = dec10_ind_move_m_pr(dc); | |
1057 | break; | |
1058 | case CRISV10_IND_MOVE_SPR_M: | |
1059 | insn_len = dec10_ind_move_pr_m(dc); | |
1060 | break; | |
1061 | case CRISV10_IND_JUMP_M: | |
1062 | if (dc->src == 15) { | |
1063 | LOG_DIS("jump.%d %d r%d r%d\n", size, | |
1064 | dc->opcode, dc->src, dc->dst); | |
1065 | imm = ldl_code(dc->pc + 2); | |
1066 | if (dc->mode == CRISV10_MODE_AUTOINC) | |
1067 | insn_len += size; | |
1068 | ||
1069 | t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); | |
1070 | tcg_gen_movi_tl(env_btarget, imm); | |
1071 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
1072 | dc->delayed_branch--; /* v10 has no dslot here. */ | |
1073 | } else { | |
1074 | if (dc->dst == 14) { | |
1075 | LOG_DIS("break %d\n", dc->src); | |
1076 | cris_evaluate_flags(dc); | |
1077 | tcg_gen_movi_tl(env_pc, dc->pc + 2); | |
1078 | t_gen_raise_exception(EXCP_BREAK); | |
1079 | dc->is_jmp = DISAS_UPDATE; | |
1080 | return insn_len; | |
1081 | } | |
1082 | LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size, | |
1083 | dc->opcode, dc->src, dc->dst); | |
1084 | t[0] = tcg_temp_new(); | |
1085 | t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); | |
1086 | crisv10_prepare_memaddr(dc, t[0], size); | |
1087 | gen_load(dc, env_btarget, t[0], 4, 0); | |
1088 | insn_len += crisv10_post_memaddr(dc, size); | |
1089 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
1090 | dc->delayed_branch--; /* v10 has no dslot here. */ | |
1091 | tcg_temp_free(t[0]); | |
1092 | } | |
1093 | break; | |
1094 | ||
1095 | case CRISV10_IND_MOVEM_R_M: | |
1096 | LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n", | |
1097 | dc->pc, dc->opcode, dc->dst, dc->src); | |
1098 | dec10_movem_r_m(dc); | |
1099 | break; | |
1100 | case CRISV10_IND_MOVEM_M_R: | |
1101 | LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode); | |
1102 | dec10_movem_m_r(dc); | |
1103 | break; | |
1104 | case CRISV10_IND_JUMP_R: | |
1105 | LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n", | |
1106 | dc->pc, dc->opcode, dc->dst, dc->src); | |
1107 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); | |
1108 | t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); | |
1109 | cris_prepare_jmp(dc, JMP_INDIRECT); | |
1110 | dc->delayed_branch--; /* v10 has no dslot here. */ | |
1111 | break; | |
1112 | case CRISV10_IND_MOVX: | |
1113 | insn_len = dec10_alux_m(dc, CC_OP_MOVE); | |
1114 | break; | |
1115 | case CRISV10_IND_ADDX: | |
1116 | insn_len = dec10_alux_m(dc, CC_OP_ADD); | |
1117 | break; | |
1118 | case CRISV10_IND_SUBX: | |
1119 | insn_len = dec10_alux_m(dc, CC_OP_SUB); | |
1120 | break; | |
1121 | case CRISV10_IND_CMPX: | |
1122 | insn_len = dec10_alux_m(dc, CC_OP_CMP); | |
1123 | break; | |
1124 | case CRISV10_IND_DIP: | |
1125 | insn_len = dec10_dip(dc); | |
1126 | break; | |
1127 | case CRISV10_IND_BCC_M: | |
1128 | ||
1129 | cris_cc_mask(dc, 0); | |
1130 | imm = ldsw_code(dc->pc + 2); | |
1131 | simm = (int16_t)imm; | |
1132 | simm += 4; | |
1133 | ||
1134 | LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm); | |
1135 | cris_prepare_cc_branch(dc, simm, dc->cond); | |
1136 | insn_len = 4; | |
1137 | break; | |
1138 | default: | |
1139 | LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); | |
1140 | assert(0); | |
1141 | break; | |
1142 | } | |
1143 | ||
1144 | return insn_len; | |
1145 | } | |
1146 | ||
1147 | static unsigned int crisv10_decoder(DisasContext *dc) | |
1148 | { | |
1149 | unsigned int insn_len = 2; | |
1150 | ||
1151 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) | |
1152 | tcg_gen_debug_insn_start(dc->pc); | |
1153 | ||
1154 | /* Load a halfword onto the instruction register. */ | |
1155 | dc->ir = lduw_code(dc->pc); | |
1156 | ||
1157 | /* Now decode it. */ | |
1158 | dc->opcode = EXTRACT_FIELD(dc->ir, 6, 9); | |
1159 | dc->mode = EXTRACT_FIELD(dc->ir, 10, 11); | |
1160 | dc->src = EXTRACT_FIELD(dc->ir, 0, 3); | |
1161 | dc->size = EXTRACT_FIELD(dc->ir, 4, 5); | |
1162 | dc->cond = dc->dst = EXTRACT_FIELD(dc->ir, 12, 15); | |
1163 | dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); | |
1164 | ||
1165 | dc->clear_prefix = 1; | |
1166 | ||
1167 | /* FIXME: What if this insn insn't 2 in length?? */ | |
1168 | if (dc->src == 15 || dc->dst == 15) | |
1169 | tcg_gen_movi_tl(cpu_R[15], dc->pc + 2); | |
1170 | ||
1171 | switch (dc->mode) { | |
1172 | case CRISV10_MODE_QIMMEDIATE: | |
1173 | insn_len = dec10_quick_imm(dc); | |
1174 | break; | |
1175 | case CRISV10_MODE_REG: | |
1176 | insn_len = dec10_reg(dc); | |
1177 | break; | |
1178 | case CRISV10_MODE_AUTOINC: | |
1179 | case CRISV10_MODE_INDIRECT: | |
1180 | insn_len = dec10_ind(dc); | |
1181 | break; | |
1182 | } | |
1183 | ||
1184 | if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) { | |
1185 | dc->tb_flags &= ~PFIX_FLAG; | |
1186 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG); | |
1187 | dc->cpustate_changed = 1; | |
1188 | } | |
1189 | ||
4ffb9ae2 EI |
1190 | /* CRISv10 locks out interrupts on dslots. */ |
1191 | if (dc->delayed_branch == 2) { | |
1192 | cris_lock_irq(dc); | |
1193 | } | |
40e9eddd EI |
1194 | return insn_len; |
1195 | } | |
1196 | ||
1197 | static CPUCRISState *cpu_crisv10_init (CPUState *env) | |
1198 | { | |
1199 | int i; | |
1200 | ||
1201 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
1202 | cc_x = tcg_global_mem_new(TCG_AREG0, | |
1203 | offsetof(CPUState, cc_x), "cc_x"); | |
1204 | cc_src = tcg_global_mem_new(TCG_AREG0, | |
1205 | offsetof(CPUState, cc_src), "cc_src"); | |
1206 | cc_dest = tcg_global_mem_new(TCG_AREG0, | |
1207 | offsetof(CPUState, cc_dest), | |
1208 | "cc_dest"); | |
1209 | cc_result = tcg_global_mem_new(TCG_AREG0, | |
1210 | offsetof(CPUState, cc_result), | |
1211 | "cc_result"); | |
1212 | cc_op = tcg_global_mem_new(TCG_AREG0, | |
1213 | offsetof(CPUState, cc_op), "cc_op"); | |
1214 | cc_size = tcg_global_mem_new(TCG_AREG0, | |
1215 | offsetof(CPUState, cc_size), | |
1216 | "cc_size"); | |
1217 | cc_mask = tcg_global_mem_new(TCG_AREG0, | |
1218 | offsetof(CPUState, cc_mask), | |
1219 | "cc_mask"); | |
1220 | ||
1221 | env_pc = tcg_global_mem_new(TCG_AREG0, | |
1222 | offsetof(CPUState, pc), | |
1223 | "pc"); | |
1224 | env_btarget = tcg_global_mem_new(TCG_AREG0, | |
1225 | offsetof(CPUState, btarget), | |
1226 | "btarget"); | |
1227 | env_btaken = tcg_global_mem_new(TCG_AREG0, | |
1228 | offsetof(CPUState, btaken), | |
1229 | "btaken"); | |
1230 | for (i = 0; i < 16; i++) { | |
1231 | cpu_R[i] = tcg_global_mem_new(TCG_AREG0, | |
1232 | offsetof(CPUState, regs[i]), | |
1233 | regnames_v10[i]); | |
1234 | } | |
1235 | for (i = 0; i < 16; i++) { | |
1236 | cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, | |
1237 | offsetof(CPUState, pregs[i]), | |
1238 | pregnames_v10[i]); | |
1239 | } | |
1240 | ||
1241 | return env; | |
1242 | } | |
1243 |