[qemu.git] / target-i386 / arch_dump.c

/*
 * i386 memory mapping
 *
 * Copyright Fujitsu, Corp. 2011, 2012
 *
 * Authors:
 *     Wen Congyang <wency@cn.fujitsu.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include "cpu.h"
#include "exec/cpu-all.h"
#include "sysemu/dump.h"
#include "elf.h"

#ifdef TARGET_X86_64
typedef struct {
    target_ulong r15, r14, r13, r12, rbp, rbx, r11, r10;
    target_ulong r9, r8, rax, rcx, rdx, rsi, rdi, orig_rax;
    target_ulong rip, cs, eflags;
    target_ulong rsp, ss;
    target_ulong fs_base, gs_base;
    target_ulong ds, es, fs, gs;
} x86_64_user_regs_struct;

typedef struct {
    char pad1[32];
    uint32_t pid;
    char pad2[76];
    x86_64_user_regs_struct regs;
    char pad3[8];
} x86_64_elf_prstatus;

static int x86_64_write_elf64_note(WriteCoreDumpFunction f,
                                   CPUArchState *env, int id,
                                   void *opaque)
{
    x86_64_user_regs_struct regs;
    Elf64_Nhdr *note;
    char *buf;
    int descsz, note_size, name_size = 5;
    const char *name = "CORE";
    int ret;

    regs.r15 = env->regs[15];
    regs.r14 = env->regs[14];
    regs.r13 = env->regs[13];
    regs.r12 = env->regs[12];
    regs.r11 = env->regs[11];
    regs.r10 = env->regs[10];
    regs.r9  = env->regs[9];
    regs.r8  = env->regs[8];
    regs.rbp = env->regs[R_EBP];
    regs.rsp = env->regs[R_ESP];
    regs.rdi = env->regs[R_EDI];
    regs.rsi = env->regs[R_ESI];
    regs.rdx = env->regs[R_EDX];
    regs.rcx = env->regs[R_ECX];
    regs.rbx = env->regs[R_EBX];
    regs.rax = env->regs[R_EAX];
    regs.rip = env->eip;
    regs.eflags = env->eflags;

    regs.orig_rax = 0; /* FIXME */
    regs.cs = env->segs[R_CS].selector;
    regs.ss = env->segs[R_SS].selector;
    regs.fs_base = env->segs[R_FS].base;
    regs.gs_base = env->segs[R_GS].base;
    regs.ds = env->segs[R_DS].selector;
    regs.es = env->segs[R_ES].selector;
    regs.fs = env->segs[R_FS].selector;
    regs.gs = env->segs[R_GS].selector;

    descsz = sizeof(x86_64_elf_prstatus);
    note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
                (descsz + 3) / 4) * 4;
    note = g_malloc(note_size);

    memset(note, 0, note_size);
    note->n_namesz = cpu_to_le32(name_size);
    note->n_descsz = cpu_to_le32(descsz);
    note->n_type = cpu_to_le32(NT_PRSTATUS);
    buf = (char *)note;
    buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
    memcpy(buf, name, name_size);
    buf += ((name_size + 3) / 4) * 4;
    memcpy(buf + 32, &id, 4); /* pr_pid */
    buf += descsz - sizeof(x86_64_user_regs_struct)-sizeof(target_ulong);
    memcpy(buf, &regs, sizeof(x86_64_user_regs_struct));

    ret = f(note, note_size, opaque);
    g_free(note);
    if (ret < 0) {
        return -1;
    }

    return 0;
}
#endif

typedef struct {
    uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
    unsigned short ds, __ds, es, __es;
    unsigned short fs, __fs, gs, __gs;
    uint32_t orig_eax, eip;
    unsigned short cs, __cs;
    uint32_t eflags, esp;
    unsigned short ss, __ss;
} x86_user_regs_struct;

typedef struct {
    char pad1[24];
    uint32_t pid;
    char pad2[44];
    x86_user_regs_struct regs;
    char pad3[4];
} x86_elf_prstatus;

static void x86_fill_elf_prstatus(x86_elf_prstatus *prstatus, CPUArchState *env,
                                  int id)
{
    memset(prstatus, 0, sizeof(x86_elf_prstatus));
    prstatus->regs.ebp = env->regs[R_EBP] & 0xffffffff;
    prstatus->regs.esp = env->regs[R_ESP] & 0xffffffff;
    prstatus->regs.edi = env->regs[R_EDI] & 0xffffffff;
    prstatus->regs.esi = env->regs[R_ESI] & 0xffffffff;
    prstatus->regs.edx = env->regs[R_EDX] & 0xffffffff;
    prstatus->regs.ecx = env->regs[R_ECX] & 0xffffffff;
    prstatus->regs.ebx = env->regs[R_EBX] & 0xffffffff;
    prstatus->regs.eax = env->regs[R_EAX] & 0xffffffff;
    prstatus->regs.eip = env->eip & 0xffffffff;
    prstatus->regs.eflags = env->eflags & 0xffffffff;

    prstatus->regs.cs = env->segs[R_CS].selector;
    prstatus->regs.ss = env->segs[R_SS].selector;
    prstatus->regs.ds = env->segs[R_DS].selector;
    prstatus->regs.es = env->segs[R_ES].selector;
    prstatus->regs.fs = env->segs[R_FS].selector;
    prstatus->regs.gs = env->segs[R_GS].selector;

    prstatus->pid = id;
}

static int x86_write_elf64_note(WriteCoreDumpFunction f, CPUArchState *env,
                                int id, void *opaque)
{
    x86_elf_prstatus prstatus;
    Elf64_Nhdr *note;
    char *buf;
    int descsz, note_size, name_size = 5;
    const char *name = "CORE";
    int ret;

    x86_fill_elf_prstatus(&prstatus, env, id);
    descsz = sizeof(x86_elf_prstatus);
    note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
                (descsz + 3) / 4) * 4;
    note = g_malloc(note_size);

    memset(note, 0, note_size);
    note->n_namesz = cpu_to_le32(name_size);
    note->n_descsz = cpu_to_le32(descsz);
    note->n_type = cpu_to_le32(NT_PRSTATUS);
    buf = (char *)note;
    buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
    memcpy(buf, name, name_size);
    buf += ((name_size + 3) / 4) * 4;
    memcpy(buf, &prstatus, sizeof(prstatus));

    ret = f(note, note_size, opaque);
    g_free(note);
    if (ret < 0) {
        return -1;
    }

    return 0;
}

int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
                             int cpuid, void *opaque)
{
    X86CPU *cpu = X86_CPU(cs);
    int ret;
#ifdef TARGET_X86_64
    bool lma = !!(first_cpu->hflags & HF_LMA_MASK);

    if (lma) {
        ret = x86_64_write_elf64_note(f, &cpu->env, cpuid, opaque);
    } else {
#endif
        ret = x86_write_elf64_note(f, &cpu->env, cpuid, opaque);
#ifdef TARGET_X86_64
    }
#endif

    return ret;
}

int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
                             int cpuid, void *opaque)
{
    X86CPU *cpu = X86_CPU(cs);
    x86_elf_prstatus prstatus;
    Elf32_Nhdr *note;
    char *buf;
    int descsz, note_size, name_size = 5;
    const char *name = "CORE";
    int ret;

    x86_fill_elf_prstatus(&prstatus, &cpu->env, cpuid);
    descsz = sizeof(x86_elf_prstatus);
    note_size = ((sizeof(Elf32_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
                (descsz + 3) / 4) * 4;
    note = g_malloc(note_size);

    memset(note, 0, note_size);
    note->n_namesz = cpu_to_le32(name_size);
    note->n_descsz = cpu_to_le32(descsz);
    note->n_type = cpu_to_le32(NT_PRSTATUS);
    buf = (char *)note;
    buf += ((sizeof(Elf32_Nhdr) + 3) / 4) * 4;
    memcpy(buf, name, name_size);
    buf += ((name_size + 3) / 4) * 4;
    memcpy(buf, &prstatus, sizeof(prstatus));

    ret = f(note, note_size, opaque);
    g_free(note);
    if (ret < 0) {
        return -1;
    }

    return 0;
}

/*
 * please count up QEMUCPUSTATE_VERSION if you have changed definition of
 * QEMUCPUState, and modify the tools using this information accordingly.
 */
#define QEMUCPUSTATE_VERSION (1)

struct QEMUCPUSegment {
    uint32_t selector;
    uint32_t limit;
    uint32_t flags;
    uint32_t pad;
    uint64_t base;
};

typedef struct QEMUCPUSegment QEMUCPUSegment;

struct QEMUCPUState {
    uint32_t version;
    uint32_t size;
    uint64_t rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp;
    uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
    uint64_t rip, rflags;
    QEMUCPUSegment cs, ds, es, fs, gs, ss;
    QEMUCPUSegment ldt, tr, gdt, idt;
    uint64_t cr[5];
};

typedef struct QEMUCPUState QEMUCPUState;

static void copy_segment(QEMUCPUSegment *d, SegmentCache *s)
{
    d->pad = 0;
    d->selector = s->selector;
    d->limit = s->limit;
    d->flags = s->flags;
    d->base = s->base;
}

static void qemu_get_cpustate(QEMUCPUState *s, CPUArchState *env)
{
    memset(s, 0, sizeof(QEMUCPUState));

    s->version = QEMUCPUSTATE_VERSION;
    s->size = sizeof(QEMUCPUState);

    s->rax = env->regs[R_EAX];
    s->rbx = env->regs[R_EBX];
    s->rcx = env->regs[R_ECX];
    s->rdx = env->regs[R_EDX];
    s->rsi = env->regs[R_ESI];
    s->rdi = env->regs[R_EDI];
    s->rsp = env->regs[R_ESP];
    s->rbp = env->regs[R_EBP];
#ifdef TARGET_X86_64
    s->r8  = env->regs[8];
    s->r9  = env->regs[9];
    s->r10 = env->regs[10];
    s->r11 = env->regs[11];
    s->r12 = env->regs[12];
    s->r13 = env->regs[13];
    s->r14 = env->regs[14];
    s->r15 = env->regs[15];
#endif
    s->rip = env->eip;
    s->rflags = env->eflags;

    copy_segment(&s->cs, &env->segs[R_CS]);
    copy_segment(&s->ds, &env->segs[R_DS]);
    copy_segment(&s->es, &env->segs[R_ES]);
    copy_segment(&s->fs, &env->segs[R_FS]);
    copy_segment(&s->gs, &env->segs[R_GS]);
    copy_segment(&s->ss, &env->segs[R_SS]);
    copy_segment(&s->ldt, &env->ldt);
    copy_segment(&s->tr, &env->tr);
    copy_segment(&s->gdt, &env->gdt);
    copy_segment(&s->idt, &env->idt);

    s->cr[0] = env->cr[0];
    s->cr[1] = env->cr[1];
    s->cr[2] = env->cr[2];
    s->cr[3] = env->cr[3];
    s->cr[4] = env->cr[4];
}

static inline int cpu_write_qemu_note(WriteCoreDumpFunction f,
                                      CPUArchState *env,
                                      void *opaque,
                                      int type)
{
    QEMUCPUState state;
    Elf64_Nhdr *note64;
    Elf32_Nhdr *note32;
    void *note;
    char *buf;
    int descsz, note_size, name_size = 5, note_head_size;
    const char *name = "QEMU";
    int ret;

    qemu_get_cpustate(&state, env);

    descsz = sizeof(state);
    if (type == 0) {
        note_head_size = sizeof(Elf32_Nhdr);
    } else {
        note_head_size = sizeof(Elf64_Nhdr);
    }
    note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
                (descsz + 3) / 4) * 4;
    note = g_malloc(note_size);

    memset(note, 0, note_size);
    if (type == 0) {
        note32 = note;
        note32->n_namesz = cpu_to_le32(name_size);
        note32->n_descsz = cpu_to_le32(descsz);
        note32->n_type = 0;
    } else {
        note64 = note;
        note64->n_namesz = cpu_to_le32(name_size);
        note64->n_descsz = cpu_to_le32(descsz);
        note64->n_type = 0;
    }
    buf = note;
    buf += ((note_head_size + 3) / 4) * 4;
    memcpy(buf, name, name_size);
    buf += ((name_size + 3) / 4) * 4;
    memcpy(buf, &state, sizeof(state));

    ret = f(note, note_size, opaque);
    g_free(note);
    if (ret < 0) {
        return -1;
    }

    return 0;
}

int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cs,
                                 void *opaque)
{
    X86CPU *cpu = X86_CPU(cs);

    return cpu_write_qemu_note(f, &cpu->env, opaque, 1);
}

int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cs,
                                 void *opaque)
{
    X86CPU *cpu = X86_CPU(cs);

    return cpu_write_qemu_note(f, &cpu->env, opaque, 0);
}

int cpu_get_dump_info(ArchDumpInfo *info)
{
    bool lma = false;
    RAMBlock *block;

#ifdef TARGET_X86_64
    lma = !!(first_cpu->hflags & HF_LMA_MASK);
#endif

    if (lma) {
        info->d_machine = EM_X86_64;
    } else {
        info->d_machine = EM_386;
    }
    info->d_endian = ELFDATA2LSB;

    if (lma) {
        info->d_class = ELFCLASS64;
    } else {
        info->d_class = ELFCLASS32;

        QTAILQ_FOREACH(block, &ram_list.blocks, next) {
            if (block->offset + block->length > UINT_MAX) {
                /* The memory size is greater than 4G */
                info->d_class = ELFCLASS64;
                break;
            }
        }
    }

    return 0;
}

ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
    int name_size = 5; /* "CORE" or "QEMU" */
    size_t elf_note_size = 0;
    size_t qemu_note_size = 0;
    int elf_desc_size = 0;
    int qemu_desc_size = 0;
    int note_head_size;

    if (class == ELFCLASS32) {
        note_head_size = sizeof(Elf32_Nhdr);
    } else {
        note_head_size = sizeof(Elf64_Nhdr);
    }

    if (machine == EM_386) {
        elf_desc_size = sizeof(x86_elf_prstatus);
    }
#ifdef TARGET_X86_64
    else {
        elf_desc_size = sizeof(x86_64_elf_prstatus);
    }
#endif
    qemu_desc_size = sizeof(QEMUCPUState);

    elf_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
                     (elf_desc_size + 3) / 4) * 4;
    qemu_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
                      (qemu_desc_size + 3) / 4) * 4;

    return (elf_note_size + qemu_note_size) * nr_cpus;
}
Commit	Line	Data
9fecbed0 WC	1	/*
	2	* i386 memory mapping
	3	*
	4	* Copyright Fujitsu, Corp. 2011, 2012
	5	*
	6	* Authors:
	7	* Wen Congyang <wency@cn.fujitsu.com>
	8	*
fc0608ac SW	9	* This work is licensed under the terms of the GNU GPL, version 2 or later.
fc0608ac SW	10	* See the COPYING file in the top-level directory.
9fecbed0 WC	11	*
	12	*/
	13
	14	#include "cpu.h"
022c62cb	15	#include "exec/cpu-all.h"
9c17d615	16	#include "sysemu/dump.h"
9fecbed0 WC	17	#include "elf.h"
	18
	19	#ifdef TARGET_X86_64
	20	typedef struct {
	21	target_ulong r15, r14, r13, r12, rbp, rbx, r11, r10;
	22	target_ulong r9, r8, rax, rcx, rdx, rsi, rdi, orig_rax;
	23	target_ulong rip, cs, eflags;
	24	target_ulong rsp, ss;
	25	target_ulong fs_base, gs_base;
	26	target_ulong ds, es, fs, gs;
	27	} x86_64_user_regs_struct;
	28
	29	typedef struct {
	30	char pad1[32];
	31	uint32_t pid;
	32	char pad2[76];
	33	x86_64_user_regs_struct regs;
	34	char pad3[8];
	35	} x86_64_elf_prstatus;
	36
c72bf468	37	static int x86_64_write_elf64_note(WriteCoreDumpFunction f,
9fecbed0 WC	38	CPUArchState *env, int id,
	39	void *opaque)
	40	{
	41	x86_64_user_regs_struct regs;
	42	Elf64_Nhdr *note;
	43	char *buf;
	44	int descsz, note_size, name_size = 5;
	45	const char *name = "CORE";
	46	int ret;
	47
	48	regs.r15 = env->regs[15];
	49	regs.r14 = env->regs[14];
	50	regs.r13 = env->regs[13];
	51	regs.r12 = env->regs[12];
	52	regs.r11 = env->regs[11];
	53	regs.r10 = env->regs[10];
	54	regs.r9 = env->regs[9];
	55	regs.r8 = env->regs[8];
	56	regs.rbp = env->regs[R_EBP];
	57	regs.rsp = env->regs[R_ESP];
	58	regs.rdi = env->regs[R_EDI];
	59	regs.rsi = env->regs[R_ESI];
	60	regs.rdx = env->regs[R_EDX];
	61	regs.rcx = env->regs[R_ECX];
	62	regs.rbx = env->regs[R_EBX];
	63	regs.rax = env->regs[R_EAX];
	64	regs.rip = env->eip;
	65	regs.eflags = env->eflags;
	66
	67	regs.orig_rax = 0; /* FIXME */
	68	regs.cs = env->segs[R_CS].selector;
	69	regs.ss = env->segs[R_SS].selector;
	70	regs.fs_base = env->segs[R_FS].base;
	71	regs.gs_base = env->segs[R_GS].base;
	72	regs.ds = env->segs[R_DS].selector;
	73	regs.es = env->segs[R_ES].selector;
	74	regs.fs = env->segs[R_FS].selector;
	75	regs.gs = env->segs[R_GS].selector;
	76
	77	descsz = sizeof(x86_64_elf_prstatus);
	78	note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
	79	(descsz + 3) / 4) * 4;
	80	note = g_malloc(note_size);
	81
	82	memset(note, 0, note_size);
	83	note->n_namesz = cpu_to_le32(name_size);
	84	note->n_descsz = cpu_to_le32(descsz);
	85	note->n_type = cpu_to_le32(NT_PRSTATUS);
	86	buf = (char *)note;
	87	buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
	88	memcpy(buf, name, name_size);
	89	buf += ((name_size + 3) / 4) * 4;
	90	memcpy(buf + 32, &id, 4); /* pr_pid */
	91	buf += descsz - sizeof(x86_64_user_regs_struct)-sizeof(target_ulong);
	92	memcpy(buf, &regs, sizeof(x86_64_user_regs_struct));
	93
	94	ret = f(note, note_size, opaque);
	95	g_free(note);
	96	if (ret < 0) {
	97	return -1;
	98	}
	99
	100	return 0;
	101	}
102	#endif
103
104	typedef struct {
105	uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
106	unsigned short ds, __ds, es, __es;
107	unsigned short fs, __fs, gs, __gs;
108	uint32_t orig_eax, eip;
109	unsigned short cs, __cs;
110	uint32_t eflags, esp;
111	unsigned short ss, __ss;
112	} x86_user_regs_struct;
113
114	typedef struct {
115	char pad1[24];
116	uint32_t pid;
117	char pad2[44];
118	x86_user_regs_struct regs;
119	char pad3[4];
120	} x86_elf_prstatus;
121
122	static void x86_fill_elf_prstatus(x86_elf_prstatus prstatus, CPUArchState env,
123	int id)
124	{
125	memset(prstatus, 0, sizeof(x86_elf_prstatus));
126	prstatus->regs.ebp = env->regs[R_EBP] & 0xffffffff;
127	prstatus->regs.esp = env->regs[R_ESP] & 0xffffffff;
128	prstatus->regs.edi = env->regs[R_EDI] & 0xffffffff;
129	prstatus->regs.esi = env->regs[R_ESI] & 0xffffffff;
130	prstatus->regs.edx = env->regs[R_EDX] & 0xffffffff;
131	prstatus->regs.ecx = env->regs[R_ECX] & 0xffffffff;
132	prstatus->regs.ebx = env->regs[R_EBX] & 0xffffffff;
133	prstatus->regs.eax = env->regs[R_EAX] & 0xffffffff;
134	prstatus->regs.eip = env->eip & 0xffffffff;
135	prstatus->regs.eflags = env->eflags & 0xffffffff;
136
137	prstatus->regs.cs = env->segs[R_CS].selector;
138	prstatus->regs.ss = env->segs[R_SS].selector;
139	prstatus->regs.ds = env->segs[R_DS].selector;
140	prstatus->regs.es = env->segs[R_ES].selector;
141	prstatus->regs.fs = env->segs[R_FS].selector;
142	prstatus->regs.gs = env->segs[R_GS].selector;
143
144	prstatus->pid = id;
145	}
146
c72bf468	147	static int x86_write_elf64_note(WriteCoreDumpFunction f, CPUArchState *env,
9fecbed0 WC	148	int id, void *opaque)
	149	{
	150	x86_elf_prstatus prstatus;
	151	Elf64_Nhdr *note;
	152	char *buf;
	153	int descsz, note_size, name_size = 5;
	154	const char *name = "CORE";
	155	int ret;
	156
	157	x86_fill_elf_prstatus(&prstatus, env, id);
	158	descsz = sizeof(x86_elf_prstatus);
	159	note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
	160	(descsz + 3) / 4) * 4;
	161	note = g_malloc(note_size);
	162
	163	memset(note, 0, note_size);
	164	note->n_namesz = cpu_to_le32(name_size);
	165	note->n_descsz = cpu_to_le32(descsz);
	166	note->n_type = cpu_to_le32(NT_PRSTATUS);
	167	buf = (char *)note;
	168	buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
	169	memcpy(buf, name, name_size);
	170	buf += ((name_size + 3) / 4) * 4;
	171	memcpy(buf, &prstatus, sizeof(prstatus));
	172
	173	ret = f(note, note_size, opaque);
	174	g_free(note);
	175	if (ret < 0) {
	176	return -1;
	177	}
	178
	179	return 0;
	180	}
	181
c72bf468 JF	182	int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
c72bf468 JF	183	int cpuid, void *opaque)
9fecbed0	184	{
c72bf468	185	X86CPU *cpu = X86_CPU(cs);
9fecbed0 WC	186	int ret;
	187	#ifdef TARGET_X86_64
	188	bool lma = !!(first_cpu->hflags & HF_LMA_MASK);
	189
	190	if (lma) {
c72bf468	191	ret = x86_64_write_elf64_note(f, &cpu->env, cpuid, opaque);
9fecbed0 WC	192	} else {
9fecbed0 WC	193	#endif
c72bf468	194	ret = x86_write_elf64_note(f, &cpu->env, cpuid, opaque);
9fecbed0 WC	195	#ifdef TARGET_X86_64
	196	}
	197	#endif
	198
	199	return ret;
	200	}
	201
c72bf468 JF	202	int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
c72bf468 JF	203	int cpuid, void *opaque)
9fecbed0	204	{
c72bf468	205	X86CPU *cpu = X86_CPU(cs);
9fecbed0 WC	206	x86_elf_prstatus prstatus;
	207	Elf32_Nhdr *note;
	208	char *buf;
	209	int descsz, note_size, name_size = 5;
	210	const char *name = "CORE";
	211	int ret;
	212
c72bf468	213	x86_fill_elf_prstatus(&prstatus, &cpu->env, cpuid);
9fecbed0 WC	214	descsz = sizeof(x86_elf_prstatus);
	215	note_size = ((sizeof(Elf32_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
	216	(descsz + 3) / 4) * 4;
	217	note = g_malloc(note_size);
	218
	219	memset(note, 0, note_size);
	220	note->n_namesz = cpu_to_le32(name_size);
	221	note->n_descsz = cpu_to_le32(descsz);
	222	note->n_type = cpu_to_le32(NT_PRSTATUS);
	223	buf = (char *)note;
	224	buf += ((sizeof(Elf32_Nhdr) + 3) / 4) * 4;
	225	memcpy(buf, name, name_size);
	226	buf += ((name_size + 3) / 4) * 4;
	227	memcpy(buf, &prstatus, sizeof(prstatus));
	228
	229	ret = f(note, note_size, opaque);
	230	g_free(note);
	231	if (ret < 0) {
	232	return -1;
	233	}
	234
	235	return 0;
	236	}
90166b71 WC	237
	238	/*
	239	* please count up QEMUCPUSTATE_VERSION if you have changed definition of
	240	* QEMUCPUState, and modify the tools using this information accordingly.
	241	*/
	242	#define QEMUCPUSTATE_VERSION (1)
	243
	244	struct QEMUCPUSegment {
	245	uint32_t selector;
	246	uint32_t limit;
	247	uint32_t flags;
	248	uint32_t pad;
	249	uint64_t base;
	250	};
	251
	252	typedef struct QEMUCPUSegment QEMUCPUSegment;
	253
	254	struct QEMUCPUState {
	255	uint32_t version;
	256	uint32_t size;
	257	uint64_t rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp;
	258	uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
	259	uint64_t rip, rflags;
	260	QEMUCPUSegment cs, ds, es, fs, gs, ss;
	261	QEMUCPUSegment ldt, tr, gdt, idt;
	262	uint64_t cr[5];
	263	};
	264
	265	typedef struct QEMUCPUState QEMUCPUState;
	266
	267	static void copy_segment(QEMUCPUSegment d, SegmentCache s)
	268	{
	269	d->pad = 0;
	270	d->selector = s->selector;
	271	d->limit = s->limit;
	272	d->flags = s->flags;
	273	d->base = s->base;
	274	}
	275
	276	static void qemu_get_cpustate(QEMUCPUState s, CPUArchState env)
	277	{
	278	memset(s, 0, sizeof(QEMUCPUState));
	279
	280	s->version = QEMUCPUSTATE_VERSION;
	281	s->size = sizeof(QEMUCPUState);
	282
	283	s->rax = env->regs[R_EAX];
	284	s->rbx = env->regs[R_EBX];
	285	s->rcx = env->regs[R_ECX];
	286	s->rdx = env->regs[R_EDX];
	287	s->rsi = env->regs[R_ESI];
	288	s->rdi = env->regs[R_EDI];
	289	s->rsp = env->regs[R_ESP];
	290	s->rbp = env->regs[R_EBP];
	291	#ifdef TARGET_X86_64
	292	s->r8 = env->regs[8];
	293	s->r9 = env->regs[9];
	294	s->r10 = env->regs[10];
	295	s->r11 = env->regs[11];
	296	s->r12 = env->regs[12];
	297	s->r13 = env->regs[13];
	298	s->r14 = env->regs[14];
	299	s->r15 = env->regs[15];
	300	#endif
301	s->rip = env->eip;
302	s->rflags = env->eflags;
303
304	copy_segment(&s->cs, &env->segs[R_CS]);
305	copy_segment(&s->ds, &env->segs[R_DS]);
306	copy_segment(&s->es, &env->segs[R_ES]);
307	copy_segment(&s->fs, &env->segs[R_FS]);
308	copy_segment(&s->gs, &env->segs[R_GS]);
309	copy_segment(&s->ss, &env->segs[R_SS]);
310	copy_segment(&s->ldt, &env->ldt);
311	copy_segment(&s->tr, &env->tr);
312	copy_segment(&s->gdt, &env->gdt);
313	copy_segment(&s->idt, &env->idt);
314
315	s->cr[0] = env->cr[0];
316	s->cr[1] = env->cr[1];
317	s->cr[2] = env->cr[2];
318	s->cr[3] = env->cr[3];
319	s->cr[4] = env->cr[4];
320	}
321
c72bf468	322	static inline int cpu_write_qemu_note(WriteCoreDumpFunction f,
90166b71 WC	323	CPUArchState *env,
	324	void *opaque,
	325	int type)
	326	{
	327	QEMUCPUState state;
	328	Elf64_Nhdr *note64;
	329	Elf32_Nhdr *note32;
	330	void *note;
	331	char *buf;
	332	int descsz, note_size, name_size = 5, note_head_size;
	333	const char *name = "QEMU";
	334	int ret;
	335
	336	qemu_get_cpustate(&state, env);
	337
	338	descsz = sizeof(state);
	339	if (type == 0) {
	340	note_head_size = sizeof(Elf32_Nhdr);
	341	} else {
	342	note_head_size = sizeof(Elf64_Nhdr);
	343	}
	344	note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
	345	(descsz + 3) / 4) * 4;
	346	note = g_malloc(note_size);
	347
	348	memset(note, 0, note_size);
	349	if (type == 0) {
	350	note32 = note;
	351	note32->n_namesz = cpu_to_le32(name_size);
	352	note32->n_descsz = cpu_to_le32(descsz);
	353	note32->n_type = 0;
	354	} else {
	355	note64 = note;
	356	note64->n_namesz = cpu_to_le32(name_size);
	357	note64->n_descsz = cpu_to_le32(descsz);
	358	note64->n_type = 0;
	359	}
	360	buf = note;
	361	buf += ((note_head_size + 3) / 4) * 4;
	362	memcpy(buf, name, name_size);
	363	buf += ((name_size + 3) / 4) * 4;
	364	memcpy(buf, &state, sizeof(state));
	365
	366	ret = f(note, note_size, opaque);
	367	g_free(note);
	368	if (ret < 0) {
	369	return -1;
	370	}
	371
	372	return 0;
	373	}
	374
c72bf468 JF	375	int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cs,
c72bf468 JF	376	void *opaque)
90166b71	377	{
c72bf468 JF	378	X86CPU *cpu = X86_CPU(cs);
	379
	380	return cpu_write_qemu_note(f, &cpu->env, opaque, 1);
90166b71 WC	381	}
90166b71 WC	382
c72bf468 JF	383	int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cs,
c72bf468 JF	384	void *opaque)
90166b71	385	{
c72bf468 JF	386	X86CPU *cpu = X86_CPU(cs);
	387
	388	return cpu_write_qemu_note(f, &cpu->env, opaque, 0);
90166b71	389	}
25ae9c1d WC	390
	391	int cpu_get_dump_info(ArchDumpInfo *info)
	392	{
	393	bool lma = false;
	394	RAMBlock *block;
	395
	396	#ifdef TARGET_X86_64
	397	lma = !!(first_cpu->hflags & HF_LMA_MASK);
	398	#endif
	399
	400	if (lma) {
	401	info->d_machine = EM_X86_64;
	402	} else {
	403	info->d_machine = EM_386;
	404	}
	405	info->d_endian = ELFDATA2LSB;
	406
	407	if (lma) {
	408	info->d_class = ELFCLASS64;
	409	} else {
	410	info->d_class = ELFCLASS32;
	411
a3161038	412	QTAILQ_FOREACH(block, &ram_list.blocks, next) {
25ae9c1d WC	413	if (block->offset + block->length > UINT_MAX) {
	414	/* The memory size is greater than 4G */
	415	info->d_class = ELFCLASS64;
	416	break;
	417	}
	418	}
	419	}
	420
	421	return 0;
	422	}
0038ffb0	423
4720bd05	424	ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
0038ffb0 WC	425	{
	426	int name_size = 5; /* "CORE" or "QEMU" */
	427	size_t elf_note_size = 0;
	428	size_t qemu_note_size = 0;
	429	int elf_desc_size = 0;
	430	int qemu_desc_size = 0;
	431	int note_head_size;
	432
	433	if (class == ELFCLASS32) {
	434	note_head_size = sizeof(Elf32_Nhdr);
	435	} else {
	436	note_head_size = sizeof(Elf64_Nhdr);
	437	}
	438
	439	if (machine == EM_386) {
	440	elf_desc_size = sizeof(x86_elf_prstatus);
	441	}
	442	#ifdef TARGET_X86_64
	443	else {
	444	elf_desc_size = sizeof(x86_64_elf_prstatus);
	445	}
	446	#endif
	447	qemu_desc_size = sizeof(QEMUCPUState);
	448
	449	elf_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
	450	(elf_desc_size + 3) / 4) * 4;
	451	qemu_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
	452	(qemu_desc_size + 3) / 4) * 4;
	453
	454	return (elf_note_size + qemu_note_size) * nr_cpus;
	455	}