[qemu.git] / target-i386 / cpu.h

/*
 * i386 virtual CPU header
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_I386_H
#define CPU_I386_H

#include "config.h"

#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif

/* target supports implicit self modifying code */
#define TARGET_HAS_SMC
/* support for self modifying code even if the modified instruction is
   close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC

#include "cpu-defs.h"

#include "softfloat.h"

#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
#define USE_CODE_COPY
#endif

#define R_EAX 0
#define R_ECX 1
#define R_EDX 2
#define R_EBX 3
#define R_ESP 4
#define R_EBP 5
#define R_ESI 6
#define R_EDI 7

#define R_AL 0
#define R_CL 1
#define R_DL 2
#define R_BL 3
#define R_AH 4
#define R_CH 5
#define R_DH 6
#define R_BH 7

#define R_ES 0
#define R_CS 1
#define R_SS 2
#define R_DS 3
#define R_FS 4
#define R_GS 5

/* segment descriptor fields */
#define DESC_G_MASK     (1 << 23)
#define DESC_B_SHIFT    22
#define DESC_B_MASK     (1 << DESC_B_SHIFT)
#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
#define DESC_L_MASK     (1 << DESC_L_SHIFT)
#define DESC_AVL_MASK   (1 << 20)
#define DESC_P_MASK     (1 << 15)
#define DESC_DPL_SHIFT  13
#define DESC_S_MASK     (1 << 12)
#define DESC_TYPE_SHIFT 8
#define DESC_A_MASK     (1 << 8)

#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
#define DESC_C_MASK     (1 << 10) /* code: conforming */
#define DESC_R_MASK     (1 << 9)  /* code: readable */

#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
#define DESC_W_MASK     (1 << 9)  /* data: writable */

#define DESC_TSS_BUSY_MASK (1 << 9)

/* eflags masks */
#define CC_C   	0x0001
#define CC_P 	0x0004
#define CC_A	0x0010
#define CC_Z	0x0040
#define CC_S    0x0080
#define CC_O    0x0800

#define TF_SHIFT   8
#define IOPL_SHIFT 12
#define VM_SHIFT   17

#define TF_MASK 		0x00000100
#define IF_MASK 		0x00000200
#define DF_MASK 		0x00000400
#define IOPL_MASK		0x00003000
#define NT_MASK	         	0x00004000
#define RF_MASK			0x00010000
#define VM_MASK			0x00020000
#define AC_MASK			0x00040000 
#define VIF_MASK                0x00080000
#define VIP_MASK                0x00100000
#define ID_MASK                 0x00200000

/* hidden flags - used internally by qemu to represent additionnal cpu
   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
   with eflags. */
/* current cpl */
#define HF_CPL_SHIFT         0
/* true if soft mmu is being used */
#define HF_SOFTMMU_SHIFT     2
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
#define HF_CS32_SHIFT        4
#define HF_SS32_SHIFT        5
/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
#define HF_ADDSEG_SHIFT      6
/* copy of CR0.PE (protected mode) */
#define HF_PE_SHIFT          7
#define HF_TF_SHIFT          8 /* must be same as eflags */
#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
#define HF_EM_SHIFT         10
#define HF_TS_SHIFT         11
#define HF_IOPL_SHIFT       12 /* must be same as eflags */
#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
#define HF_VM_SHIFT         17 /* must be same as eflags */

#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
#define HF_PE_MASK           (1 << HF_PE_SHIFT)
#define HF_TF_MASK           (1 << HF_TF_SHIFT)
#define HF_MP_MASK           (1 << HF_MP_SHIFT)
#define HF_EM_MASK           (1 << HF_EM_SHIFT)
#define HF_TS_MASK           (1 << HF_TS_SHIFT)
#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)

#define CR0_PE_MASK  (1 << 0)
#define CR0_MP_MASK  (1 << 1)
#define CR0_EM_MASK  (1 << 2)
#define CR0_TS_MASK  (1 << 3)
#define CR0_ET_MASK  (1 << 4)
#define CR0_NE_MASK  (1 << 5)
#define CR0_WP_MASK  (1 << 16)
#define CR0_AM_MASK  (1 << 18)
#define CR0_PG_MASK  (1 << 31)

#define CR4_VME_MASK  (1 << 0)
#define CR4_PVI_MASK  (1 << 1)
#define CR4_TSD_MASK  (1 << 2)
#define CR4_DE_MASK   (1 << 3)
#define CR4_PSE_MASK  (1 << 4)
#define CR4_PAE_MASK  (1 << 5)
#define CR4_PGE_MASK  (1 << 7)
#define CR4_PCE_MASK  (1 << 8)
#define CR4_OSFXSR_MASK (1 << 9)
#define CR4_OSXMMEXCPT_MASK  (1 << 10)

#define PG_PRESENT_BIT	0
#define PG_RW_BIT	1
#define PG_USER_BIT	2
#define PG_PWT_BIT	3
#define PG_PCD_BIT	4
#define PG_ACCESSED_BIT	5
#define PG_DIRTY_BIT	6
#define PG_PSE_BIT	7
#define PG_GLOBAL_BIT	8

#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
#define PG_RW_MASK	 (1 << PG_RW_BIT)
#define PG_USER_MASK	 (1 << PG_USER_BIT)
#define PG_PWT_MASK	 (1 << PG_PWT_BIT)
#define PG_PCD_MASK	 (1 << PG_PCD_BIT)
#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
#define PG_PSE_MASK	 (1 << PG_PSE_BIT)
#define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)

#define PG_ERROR_W_BIT     1

#define PG_ERROR_P_MASK    0x01
#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
#define PG_ERROR_U_MASK    0x04
#define PG_ERROR_RSVD_MASK 0x08

#define MSR_IA32_APICBASE               0x1b
#define MSR_IA32_APICBASE_BSP           (1<<8)
#define MSR_IA32_APICBASE_ENABLE        (1<<11)
#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

#define MSR_IA32_SYSENTER_CS            0x174
#define MSR_IA32_SYSENTER_ESP           0x175
#define MSR_IA32_SYSENTER_EIP           0x176

#define MSR_EFER                        0xc0000080

#define MSR_EFER_SCE   (1 << 0)
#define MSR_EFER_LME   (1 << 8)
#define MSR_EFER_LMA   (1 << 10)
#define MSR_EFER_NXE   (1 << 11)
#define MSR_EFER_FFXSR (1 << 14)

#define MSR_STAR                        0xc0000081
#define MSR_LSTAR                       0xc0000082
#define MSR_CSTAR                       0xc0000083
#define MSR_FMASK                       0xc0000084
#define MSR_FSBASE                      0xc0000100
#define MSR_GSBASE                      0xc0000101
#define MSR_KERNELGSBASE                0xc0000102

/* cpuid_features bits */
#define CPUID_FP87 (1 << 0)
#define CPUID_VME  (1 << 1)
#define CPUID_DE   (1 << 2)
#define CPUID_PSE  (1 << 3)
#define CPUID_TSC  (1 << 4)
#define CPUID_MSR  (1 << 5)
#define CPUID_PAE  (1 << 6)
#define CPUID_MCE  (1 << 7)
#define CPUID_CX8  (1 << 8)
#define CPUID_APIC (1 << 9)
#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
#define CPUID_MTRR (1 << 12)
#define CPUID_PGE  (1 << 13)
#define CPUID_MCA  (1 << 14)
#define CPUID_CMOV (1 << 15)
/* ... */
#define CPUID_MMX  (1 << 23)
#define CPUID_FXSR (1 << 24)
#define CPUID_SSE  (1 << 25)
#define CPUID_SSE2 (1 << 26)

#define CPUID_EXT_SS3      (1 << 0)
#define CPUID_EXT_MONITOR  (1 << 3)
#define CPUID_EXT_CX16     (1 << 13)

#define CPUID_EXT2_SYSCALL (1 << 11)
#define CPUID_EXT2_NX      (1 << 20)
#define CPUID_EXT2_LM      (1 << 29)

#define EXCP00_DIVZ	0
#define EXCP01_SSTP	1
#define EXCP02_NMI	2
#define EXCP03_INT3	3
#define EXCP04_INTO	4
#define EXCP05_BOUND	5
#define EXCP06_ILLOP	6
#define EXCP07_PREX	7
#define EXCP08_DBLE	8
#define EXCP09_XERR	9
#define EXCP0A_TSS	10
#define EXCP0B_NOSEG	11
#define EXCP0C_STACK	12
#define EXCP0D_GPF	13
#define EXCP0E_PAGE	14
#define EXCP10_COPR	16
#define EXCP11_ALGN	17
#define EXCP12_MCHK	18

enum {
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */

    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
    CC_OP_MULW,
    CC_OP_MULL,
    CC_OP_MULQ,

    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADDW,
    CC_OP_ADDL,
    CC_OP_ADDQ,

    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADCW,
    CC_OP_ADCL,
    CC_OP_ADCQ,

    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUBW,
    CC_OP_SUBL,
    CC_OP_SUBQ,

    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SBBW,
    CC_OP_SBBL,
    CC_OP_SBBQ,

    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
    CC_OP_LOGICW,
    CC_OP_LOGICL,
    CC_OP_LOGICQ,

    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
    CC_OP_INCW,
    CC_OP_INCL,
    CC_OP_INCQ,

    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
    CC_OP_DECW,
    CC_OP_DECL,
    CC_OP_DECQ,

    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
    CC_OP_SHLW,
    CC_OP_SHLL,
    CC_OP_SHLQ,

    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SARW,
    CC_OP_SARL,
    CC_OP_SARQ,

    CC_OP_NB,
};

#ifdef FLOATX80
#define USE_X86LDOUBLE
#endif

#ifdef USE_X86LDOUBLE
typedef floatx80 CPU86_LDouble;
#else
typedef float64 CPU86_LDouble;
#endif

typedef struct SegmentCache {
    uint32_t selector;
    target_ulong base;
    uint32_t limit;
    uint32_t flags;
} SegmentCache;

typedef union {
    uint8_t _b[16];
    uint16_t _w[8];
    uint32_t _l[4];
    uint64_t _q[2];
    float32 _s[4];
    float64 _d[2];
} XMMReg;

typedef union {
    uint8_t _b[8];
    uint16_t _w[2];
    uint32_t _l[1];
    uint64_t q;
} MMXReg;

#ifdef WORDS_BIGENDIAN
#define XMM_B(n) _b[15 - (n)]
#define XMM_W(n) _w[7 - (n)]
#define XMM_L(n) _l[3 - (n)]
#define XMM_S(n) _s[3 - (n)]
#define XMM_Q(n) _q[1 - (n)]
#define XMM_D(n) _d[1 - (n)]

#define MMX_B(n) _b[7 - (n)]
#define MMX_W(n) _w[3 - (n)]
#define MMX_L(n) _l[1 - (n)]
#else
#define XMM_B(n) _b[n]
#define XMM_W(n) _w[n]
#define XMM_L(n) _l[n]
#define XMM_S(n) _s[n]
#define XMM_Q(n) _q[n]
#define XMM_D(n) _d[n]

#define MMX_B(n) _b[n]
#define MMX_W(n) _w[n]
#define MMX_L(n) _l[n]
#endif
#define MMX_Q(n) q

#ifdef TARGET_X86_64
#define CPU_NB_REGS 16
#else
#define CPU_NB_REGS 8
#endif

typedef struct CPUX86State {
#if TARGET_LONG_BITS > HOST_LONG_BITS
    /* temporaries if we cannot store them in host registers */
    target_ulong t0, t1, t2;
#endif

    /* standard registers */
    target_ulong regs[CPU_NB_REGS];
    target_ulong eip;
    target_ulong eflags; /* eflags register. During CPU emulation, CC
                        flags and DF are set to zero because they are
                        stored elsewhere */

    /* emulator internal eflags handling */
    target_ulong cc_src;
    target_ulong cc_dst;
    uint32_t cc_op;
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
    uint32_t hflags; /* hidden flags, see HF_xxx constants */

    /* segments */
    SegmentCache segs[6]; /* selector values */
    SegmentCache ldt;
    SegmentCache tr;
    SegmentCache gdt; /* only base and limit are used */
    SegmentCache idt; /* only base and limit are used */

    target_ulong cr[5]; /* NOTE: cr1 is unused */
    uint32_t a20_mask;

    /* FPU state */
    unsigned int fpstt; /* top of stack index */
    unsigned int fpus;
    unsigned int fpuc;
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
    union {
#ifdef USE_X86LDOUBLE
        CPU86_LDouble d __attribute__((aligned(16)));
#else
        CPU86_LDouble d;
#endif
        MMXReg mmx;
    } fpregs[8];

    /* emulator internal variables */
    float_status fp_status;
    CPU86_LDouble ft0;
    union {
	float f;
        double d;
	int i32;
        int64_t i64;
    } fp_convert;
    
    float_status sse_status;
    uint32_t mxcsr;
    XMMReg xmm_regs[CPU_NB_REGS];
    XMMReg xmm_t0;
    MMXReg mmx_t0;

    /* sysenter registers */
    uint32_t sysenter_cs;
    uint32_t sysenter_esp;
    uint32_t sysenter_eip;
#ifdef TARGET_X86_64
    target_ulong efer;
    target_ulong star;
    target_ulong lstar;
    target_ulong cstar;
    target_ulong fmask;
    target_ulong kernelgsbase;
#endif

    /* temporary data for USE_CODE_COPY mode */
#ifdef USE_CODE_COPY
    uint32_t tmp0;
    uint32_t saved_esp;
    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
#endif
    
    /* exception/interrupt handling */
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int exception_is_int;
    target_ulong exception_next_eip;
    struct TranslationBlock *current_tb; /* currently executing TB */
    target_ulong dr[8]; /* debug registers */
    int interrupt_request; 
    int user_mode_only; /* user mode only simulation */

    /* soft mmu support */
    /* in order to avoid passing too many arguments to the memory
       write helpers, we store some rarely used information in the CPU
       context) */
    unsigned long mem_write_pc; /* host pc at which the memory was
                                   written */
    target_ulong mem_write_vaddr; /* target virtual addr at which the
                                     memory was written */
    /* 0 = kernel, 1 = user */
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
    
    /* from this point: preserved by CPU reset */
    /* ice debug support */
    target_ulong breakpoints[MAX_BREAKPOINTS];
    int nb_breakpoints;
    int singlestep_enabled;

    /* processor features (e.g. for CPUID insn) */
    uint32_t cpuid_vendor1;
    uint32_t cpuid_vendor2;
    uint32_t cpuid_vendor3;
    uint32_t cpuid_version;
    uint32_t cpuid_features;
    uint32_t cpuid_ext_features;

#ifdef USE_KQEMU
    int kqemu_enabled;
#endif
    /* in order to simplify APIC support, we leave this pointer to the
       user */
    struct APICState *apic_state;
    /* user data */
    void *opaque;
} CPUX86State;

CPUX86State *cpu_x86_init(void);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void cpu_set_ferr(CPUX86State *s);

/* this function must always be used to load data in the segment
   cache: it synchronizes the hflags with the segment cache values */
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
                                          int seg_reg, unsigned int selector,
                                          uint32_t base, unsigned int limit, 
                                          unsigned int flags)
{
    SegmentCache *sc;
    unsigned int new_hflags;
    
    sc = &env->segs[seg_reg];
    sc->selector = selector;
    sc->base = base;
    sc->limit = limit;
    sc->flags = flags;

    /* update the hidden flags */
    {
        if (seg_reg == R_CS) {
#ifdef TARGET_X86_64
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
                /* long mode */
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
                env->hflags &= ~(HF_ADDSEG_MASK);
            } else 
#endif
            {
                /* legacy / compatibility case */
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
                    new_hflags;
            }
        }
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
        if (env->hflags & HF_CS64_MASK) {
            /* zero base assumed for DS, ES and SS in long mode */
        } else if (!(env->cr[0] & CR0_PE_MASK) || 
                   (env->eflags & VM_MASK) ||
                   !(env->hflags & HF_CS32_MASK)) {
            /* XXX: try to avoid this test. The problem comes from the
               fact that is real mode or vm86 mode we only modify the
               'base' and 'selector' fields of the segment cache to go
               faster. A solution may be to force addseg to one in
               translate-i386.c. */
            new_hflags |= HF_ADDSEG_MASK;
        } else {
            new_hflags |= ((env->segs[R_DS].base | 
                            env->segs[R_ES].base |
                            env->segs[R_SS].base) != 0) << 
                HF_ADDSEG_SHIFT;
        }
        env->hflags = (env->hflags & 
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
    }
}

/* wrapper, just in case memory mappings must be changed */
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
{
#if HF_CPL_MASK == 3
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
#else
#error HF_CPL_MASK is hardcoded
#endif
}

/* used for debug or cpu save/restore */
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);

/* the following helpers are only usable in user mode simulation as
   they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
struct siginfo;
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc);
void cpu_x86_set_a20(CPUX86State *env, int a20_state);

uint64_t cpu_get_tsc(CPUX86State *env);

void cpu_set_apic_base(CPUX86State *env, uint64_t val);
uint64_t cpu_get_apic_base(CPUX86State *env);
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
#ifndef NO_CPU_IO_DEFS
uint8_t cpu_get_apic_tpr(CPUX86State *env);
#endif

/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);

/* used to debug */
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

#endif /* CPU_I386_H */
Commit	Line	Data
2c0262af FB	1	/*
	2	* i386 virtual CPU header
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_I386_H
	21	#define CPU_I386_H
	22
14ce26e7 FB	23	#include "config.h"
	24
	25	#ifdef TARGET_X86_64
	26	#define TARGET_LONG_BITS 64
	27	#else
3cf1e035	28	#define TARGET_LONG_BITS 32
14ce26e7	29	#endif
3cf1e035	30
d720b93d FB	31	/* target supports implicit self modifying code */
	32	#define TARGET_HAS_SMC
	33	/* support for self modifying code even if the modified instruction is
	34	close to the modifying instruction */
	35	#define TARGET_HAS_PRECISE_SMC
	36
2c0262af FB	37	#include "cpu-defs.h"
2c0262af FB	38
7a0e1f41 FB	39	#include "softfloat.h"
7a0e1f41 FB	40
58fe2f10 FB	41	#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
	42	#define USE_CODE_COPY
	43	#endif
	44
2c0262af FB	45	#define R_EAX 0
	46	#define R_ECX 1
	47	#define R_EDX 2
	48	#define R_EBX 3
	49	#define R_ESP 4
	50	#define R_EBP 5
	51	#define R_ESI 6
	52	#define R_EDI 7
	53
	54	#define R_AL 0
	55	#define R_CL 1
	56	#define R_DL 2
	57	#define R_BL 3
	58	#define R_AH 4
	59	#define R_CH 5
	60	#define R_DH 6
	61	#define R_BH 7
	62
	63	#define R_ES 0
	64	#define R_CS 1
	65	#define R_SS 2
	66	#define R_DS 3
	67	#define R_FS 4
	68	#define R_GS 5
	69
	70	/* segment descriptor fields */
	71	#define DESC_G_MASK (1 << 23)
	72	#define DESC_B_SHIFT 22
	73	#define DESC_B_MASK (1 << DESC_B_SHIFT)
14ce26e7 FB	74	#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
14ce26e7 FB	75	#define DESC_L_MASK (1 << DESC_L_SHIFT)
2c0262af FB	76	#define DESC_AVL_MASK (1 << 20)
	77	#define DESC_P_MASK (1 << 15)
	78	#define DESC_DPL_SHIFT 13
	79	#define DESC_S_MASK (1 << 12)
	80	#define DESC_TYPE_SHIFT 8
	81	#define DESC_A_MASK (1 << 8)
	82
e670b89e FB	83	#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
	84	#define DESC_C_MASK (1 << 10) /* code: conforming */
	85	#define DESC_R_MASK (1 << 9) /* code: readable */
2c0262af	86
e670b89e FB	87	#define DESC_E_MASK (1 << 10) /* data: expansion direction */
	88	#define DESC_W_MASK (1 << 9) /* data: writable */
	89
	90	#define DESC_TSS_BUSY_MASK (1 << 9)
2c0262af FB	91
	92	/* eflags masks */
	93	#define CC_C 0x0001
	94	#define CC_P 0x0004
	95	#define CC_A 0x0010
	96	#define CC_Z 0x0040
	97	#define CC_S 0x0080
	98	#define CC_O 0x0800
	99
	100	#define TF_SHIFT 8
	101	#define IOPL_SHIFT 12
	102	#define VM_SHIFT 17
	103
	104	#define TF_MASK 0x00000100
	105	#define IF_MASK 0x00000200
	106	#define DF_MASK 0x00000400
	107	#define IOPL_MASK 0x00003000
	108	#define NT_MASK 0x00004000
	109	#define RF_MASK 0x00010000
	110	#define VM_MASK 0x00020000
	111	#define AC_MASK 0x00040000
	112	#define VIF_MASK 0x00080000
	113	#define VIP_MASK 0x00100000
	114	#define ID_MASK 0x00200000
	115
	116	/* hidden flags - used internally by qemu to represent additionnal cpu
	117	states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
	118	using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
	119	with eflags. */
	120	/* current cpl */
	121	#define HF_CPL_SHIFT 0
	122	/* true if soft mmu is being used */
	123	#define HF_SOFTMMU_SHIFT 2
	124	/* true if hardware interrupts must be disabled for next instruction */
	125	#define HF_INHIBIT_IRQ_SHIFT 3
	126	/* 16 or 32 segments */
	127	#define HF_CS32_SHIFT 4
	128	#define HF_SS32_SHIFT 5
dc196a57	129	/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
2c0262af	130	#define HF_ADDSEG_SHIFT 6
65262d57 FB	131	/* copy of CR0.PE (protected mode) */
	132	#define HF_PE_SHIFT 7
	133	#define HF_TF_SHIFT 8 /* must be same as eflags */
7eee2a50 FB	134	#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
	135	#define HF_EM_SHIFT 10
	136	#define HF_TS_SHIFT 11
65262d57	137	#define HF_IOPL_SHIFT 12 /* must be same as eflags */
14ce26e7 FB	138	#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
14ce26e7 FB	139	#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
664e0f19	140	#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
65262d57	141	#define HF_VM_SHIFT 17 /* must be same as eflags */
2c0262af FB	142
	143	#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
	144	#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
	145	#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
	146	#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
	147	#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
	148	#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
65262d57	149	#define HF_PE_MASK (1 << HF_PE_SHIFT)
58fe2f10	150	#define HF_TF_MASK (1 << HF_TF_SHIFT)
7eee2a50 FB	151	#define HF_MP_MASK (1 << HF_MP_SHIFT)
	152	#define HF_EM_MASK (1 << HF_EM_SHIFT)
	153	#define HF_TS_MASK (1 << HF_TS_SHIFT)
14ce26e7 FB	154	#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
14ce26e7 FB	155	#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
664e0f19	156	#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
2c0262af FB	157
2c0262af FB	158	#define CR0_PE_MASK (1 << 0)
7eee2a50 FB	159	#define CR0_MP_MASK (1 << 1)
7eee2a50 FB	160	#define CR0_EM_MASK (1 << 2)
2c0262af	161	#define CR0_TS_MASK (1 << 3)
2ee73ac3	162	#define CR0_ET_MASK (1 << 4)
7eee2a50	163	#define CR0_NE_MASK (1 << 5)
2c0262af FB	164	#define CR0_WP_MASK (1 << 16)
	165	#define CR0_AM_MASK (1 << 18)
	166	#define CR0_PG_MASK (1 << 31)
	167
	168	#define CR4_VME_MASK (1 << 0)
	169	#define CR4_PVI_MASK (1 << 1)
	170	#define CR4_TSD_MASK (1 << 2)
	171	#define CR4_DE_MASK (1 << 3)
	172	#define CR4_PSE_MASK (1 << 4)
64a595f2 FB	173	#define CR4_PAE_MASK (1 << 5)
64a595f2 FB	174	#define CR4_PGE_MASK (1 << 7)
14ce26e7 FB	175	#define CR4_PCE_MASK (1 << 8)
	176	#define CR4_OSFXSR_MASK (1 << 9)
	177	#define CR4_OSXMMEXCPT_MASK (1 << 10)
2c0262af FB	178
	179	#define PG_PRESENT_BIT 0
	180	#define PG_RW_BIT 1
	181	#define PG_USER_BIT 2
	182	#define PG_PWT_BIT 3
	183	#define PG_PCD_BIT 4
	184	#define PG_ACCESSED_BIT 5
	185	#define PG_DIRTY_BIT 6
	186	#define PG_PSE_BIT 7
	187	#define PG_GLOBAL_BIT 8
	188
	189	#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
	190	#define PG_RW_MASK (1 << PG_RW_BIT)
	191	#define PG_USER_MASK (1 << PG_USER_BIT)
	192	#define PG_PWT_MASK (1 << PG_PWT_BIT)
	193	#define PG_PCD_MASK (1 << PG_PCD_BIT)
	194	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	195	#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
	196	#define PG_PSE_MASK (1 << PG_PSE_BIT)
	197	#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
	198
	199	#define PG_ERROR_W_BIT 1
	200
	201	#define PG_ERROR_P_MASK 0x01
	202	#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
	203	#define PG_ERROR_U_MASK 0x04
	204	#define PG_ERROR_RSVD_MASK 0x08
	205
	206	#define MSR_IA32_APICBASE 0x1b
	207	#define MSR_IA32_APICBASE_BSP (1<<8)
	208	#define MSR_IA32_APICBASE_ENABLE (1<<11)
	209	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
	210
	211	#define MSR_IA32_SYSENTER_CS 0x174
	212	#define MSR_IA32_SYSENTER_ESP 0x175
	213	#define MSR_IA32_SYSENTER_EIP 0x176
	214
14ce26e7 FB	215	#define MSR_EFER 0xc0000080
	216
	217	#define MSR_EFER_SCE (1 << 0)
	218	#define MSR_EFER_LME (1 << 8)
	219	#define MSR_EFER_LMA (1 << 10)
	220	#define MSR_EFER_NXE (1 << 11)
	221	#define MSR_EFER_FFXSR (1 << 14)
	222
	223	#define MSR_STAR 0xc0000081
	224	#define MSR_LSTAR 0xc0000082
	225	#define MSR_CSTAR 0xc0000083
	226	#define MSR_FMASK 0xc0000084
	227	#define MSR_FSBASE 0xc0000100
	228	#define MSR_GSBASE 0xc0000101
	229	#define MSR_KERNELGSBASE 0xc0000102
	230
	231	/* cpuid_features bits */
	232	#define CPUID_FP87 (1 << 0)
	233	#define CPUID_VME (1 << 1)
	234	#define CPUID_DE (1 << 2)
	235	#define CPUID_PSE (1 << 3)
	236	#define CPUID_TSC (1 << 4)
	237	#define CPUID_MSR (1 << 5)
	238	#define CPUID_PAE (1 << 6)
	239	#define CPUID_MCE (1 << 7)
	240	#define CPUID_CX8 (1 << 8)
	241	#define CPUID_APIC (1 << 9)
	242	#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
	243	#define CPUID_MTRR (1 << 12)
	244	#define CPUID_PGE (1 << 13)
	245	#define CPUID_MCA (1 << 14)
	246	#define CPUID_CMOV (1 << 15)
	247	/* ... */
	248	#define CPUID_MMX (1 << 23)
	249	#define CPUID_FXSR (1 << 24)
	250	#define CPUID_SSE (1 << 25)
	251	#define CPUID_SSE2 (1 << 26)
	252
9df217a3 FB	253	#define CPUID_EXT_SS3 (1 << 0)
	254	#define CPUID_EXT_MONITOR (1 << 3)
	255	#define CPUID_EXT_CX16 (1 << 13)
	256
	257	#define CPUID_EXT2_SYSCALL (1 << 11)
	258	#define CPUID_EXT2_NX (1 << 20)
	259	#define CPUID_EXT2_LM (1 << 29)
	260
2c0262af FB	261	#define EXCP00_DIVZ 0
	262	#define EXCP01_SSTP 1
	263	#define EXCP02_NMI 2
	264	#define EXCP03_INT3 3
	265	#define EXCP04_INTO 4
	266	#define EXCP05_BOUND 5
	267	#define EXCP06_ILLOP 6
	268	#define EXCP07_PREX 7
	269	#define EXCP08_DBLE 8
	270	#define EXCP09_XERR 9
	271	#define EXCP0A_TSS 10
	272	#define EXCP0B_NOSEG 11
	273	#define EXCP0C_STACK 12
	274	#define EXCP0D_GPF 13
	275	#define EXCP0E_PAGE 14
	276	#define EXCP10_COPR 16
	277	#define EXCP11_ALGN 17
	278	#define EXCP12_MCHK 18
	279
	280	enum {
	281	CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
	282	CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
d36cd60e FB	283
	284	CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
	285	CC_OP_MULW,
	286	CC_OP_MULL,
14ce26e7	287	CC_OP_MULQ,
2c0262af FB	288
	289	CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	290	CC_OP_ADDW,
	291	CC_OP_ADDL,
14ce26e7	292	CC_OP_ADDQ,
2c0262af FB	293
	294	CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	295	CC_OP_ADCW,
	296	CC_OP_ADCL,
14ce26e7	297	CC_OP_ADCQ,
2c0262af FB	298
	299	CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	300	CC_OP_SUBW,
	301	CC_OP_SUBL,
14ce26e7	302	CC_OP_SUBQ,
2c0262af FB	303
	304	CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	305	CC_OP_SBBW,
	306	CC_OP_SBBL,
14ce26e7	307	CC_OP_SBBQ,
2c0262af FB	308
	309	CC_OP_LOGICB, /* modify all flags, CC_DST = res */
	310	CC_OP_LOGICW,
	311	CC_OP_LOGICL,
14ce26e7	312	CC_OP_LOGICQ,
2c0262af FB	313
	314	CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	315	CC_OP_INCW,
	316	CC_OP_INCL,
14ce26e7	317	CC_OP_INCQ,
2c0262af FB	318
	319	CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	320	CC_OP_DECW,
	321	CC_OP_DECL,
14ce26e7	322	CC_OP_DECQ,
2c0262af	323
6b652794	324	CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
2c0262af FB	325	CC_OP_SHLW,
2c0262af FB	326	CC_OP_SHLL,
14ce26e7	327	CC_OP_SHLQ,
2c0262af FB	328
	329	CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
	330	CC_OP_SARW,
	331	CC_OP_SARL,
14ce26e7	332	CC_OP_SARQ,
2c0262af FB	333
	334	CC_OP_NB,
	335	};
	336
7a0e1f41	337	#ifdef FLOATX80
2c0262af FB	338	#define USE_X86LDOUBLE
	339	#endif
	340
	341	#ifdef USE_X86LDOUBLE
7a0e1f41	342	typedef floatx80 CPU86_LDouble;
2c0262af	343	#else
7a0e1f41	344	typedef float64 CPU86_LDouble;
2c0262af FB	345	#endif
	346
	347	typedef struct SegmentCache {
	348	uint32_t selector;
14ce26e7	349	target_ulong base;
2c0262af FB	350	uint32_t limit;
	351	uint32_t flags;
	352	} SegmentCache;
	353
826461bb	354	typedef union {
664e0f19 FB	355	uint8_t _b[16];
	356	uint16_t _w[8];
	357	uint32_t _l[4];
	358	uint64_t _q[2];
7a0e1f41 FB	359	float32 _s[4];
7a0e1f41 FB	360	float64 _d[2];
14ce26e7 FB	361	} XMMReg;
14ce26e7 FB	362
826461bb FB	363	typedef union {
	364	uint8_t _b[8];
	365	uint16_t _w[2];
	366	uint32_t _l[1];
	367	uint64_t q;
	368	} MMXReg;
	369
	370	#ifdef WORDS_BIGENDIAN
	371	#define XMM_B(n) _b[15 - (n)]
	372	#define XMM_W(n) _w[7 - (n)]
	373	#define XMM_L(n) _l[3 - (n)]
664e0f19	374	#define XMM_S(n) _s[3 - (n)]
826461bb	375	#define XMM_Q(n) _q[1 - (n)]
664e0f19	376	#define XMM_D(n) _d[1 - (n)]
826461bb FB	377
	378	#define MMX_B(n) _b[7 - (n)]
	379	#define MMX_W(n) _w[3 - (n)]
	380	#define MMX_L(n) _l[1 - (n)]
	381	#else
	382	#define XMM_B(n) _b[n]
	383	#define XMM_W(n) _w[n]
	384	#define XMM_L(n) _l[n]
664e0f19	385	#define XMM_S(n) _s[n]
826461bb	386	#define XMM_Q(n) _q[n]
664e0f19	387	#define XMM_D(n) _d[n]
826461bb FB	388
	389	#define MMX_B(n) _b[n]
	390	#define MMX_W(n) _w[n]
	391	#define MMX_L(n) _l[n]
	392	#endif
664e0f19	393	#define MMX_Q(n) q
826461bb	394
14ce26e7 FB	395	#ifdef TARGET_X86_64
	396	#define CPU_NB_REGS 16
	397	#else
	398	#define CPU_NB_REGS 8
	399	#endif
	400
2c0262af	401	typedef struct CPUX86State {
14ce26e7 FB	402	#if TARGET_LONG_BITS > HOST_LONG_BITS
	403	/* temporaries if we cannot store them in host registers */
	404	target_ulong t0, t1, t2;
	405	#endif
	406
2c0262af	407	/* standard registers */
14ce26e7 FB	408	target_ulong regs[CPU_NB_REGS];
	409	target_ulong eip;
	410	target_ulong eflags; /* eflags register. During CPU emulation, CC
2c0262af FB	411	flags and DF are set to zero because they are
	412	stored elsewhere */
	413
	414	/* emulator internal eflags handling */
14ce26e7 FB	415	target_ulong cc_src;
14ce26e7 FB	416	target_ulong cc_dst;
2c0262af FB	417	uint32_t cc_op;
	418	int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
	419	uint32_t hflags; /* hidden flags, see HF_xxx constants */
	420
9df217a3 FB	421	/* segments */
	422	SegmentCache segs[6]; /* selector values */
	423	SegmentCache ldt;
	424	SegmentCache tr;
	425	SegmentCache gdt; /* only base and limit are used */
	426	SegmentCache idt; /* only base and limit are used */
	427
	428	target_ulong cr[5]; /* NOTE: cr1 is unused */
	429	uint32_t a20_mask;
	430
2c0262af FB	431	/* FPU state */
	432	unsigned int fpstt; /* top of stack index */
	433	unsigned int fpus;
	434	unsigned int fpuc;
	435	uint8_t fptags[8]; /* 0 = valid, 1 = empty */
664e0f19 FB	436	union {
	437	#ifdef USE_X86LDOUBLE
	438	CPU86_LDouble d __attribute__((aligned(16)));
	439	#else
	440	CPU86_LDouble d;
	441	#endif
	442	MMXReg mmx;
	443	} fpregs[8];
2c0262af FB	444
2c0262af FB	445	/* emulator internal variables */
7a0e1f41	446	float_status fp_status;
2c0262af FB	447	CPU86_LDouble ft0;
	448	union {
	449	float f;
	450	double d;
	451	int i32;
	452	int64_t i64;
	453	} fp_convert;
	454
7a0e1f41	455	float_status sse_status;
664e0f19	456	uint32_t mxcsr;
14ce26e7 FB	457	XMMReg xmm_regs[CPU_NB_REGS];
14ce26e7 FB	458	XMMReg xmm_t0;
664e0f19	459	MMXReg mmx_t0;
14ce26e7	460
2c0262af FB	461	/* sysenter registers */
	462	uint32_t sysenter_cs;
	463	uint32_t sysenter_esp;
	464	uint32_t sysenter_eip;
14ce26e7 FB	465	#ifdef TARGET_X86_64
	466	target_ulong efer;
	467	target_ulong star;
	468	target_ulong lstar;
	469	target_ulong cstar;
	470	target_ulong fmask;
	471	target_ulong kernelgsbase;
	472	#endif
58fe2f10 FB	473
58fe2f10 FB	474	/* temporary data for USE_CODE_COPY mode */
7eee2a50	475	#ifdef USE_CODE_COPY
58fe2f10 FB	476	uint32_t tmp0;
58fe2f10 FB	477	uint32_t saved_esp;
7eee2a50 FB	478	int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
7eee2a50 FB	479	#endif
2c0262af FB	480
	481	/* exception/interrupt handling */
	482	jmp_buf jmp_env;
	483	int exception_index;
	484	int error_code;
	485	int exception_is_int;
826461bb	486	target_ulong exception_next_eip;
2c0262af	487	struct TranslationBlock current_tb; / currently executing TB */
14ce26e7	488	target_ulong dr[8]; /* debug registers */
2c0262af FB	489	int interrupt_request;
	490	int user_mode_only; /* user mode only simulation */
	491
d720b93d FB	492	/* soft mmu support */
	493	/* in order to avoid passing too many arguments to the memory
	494	write helpers, we store some rarely used information in the CPU
	495	context) */
	496	unsigned long mem_write_pc; /* host pc at which the memory was
	497	written */
14ce26e7 FB	498	target_ulong mem_write_vaddr; /* target virtual addr at which the
14ce26e7 FB	499	memory was written */
2c0262af FB	500	/* 0 = kernel, 1 = user */
	501	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
	502	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
	503
ffddfee3	504	/* from this point: preserved by CPU reset */
2c0262af	505	/* ice debug support */
14ce26e7	506	target_ulong breakpoints[MAX_BREAKPOINTS];
2c0262af FB	507	int nb_breakpoints;
	508	int singlestep_enabled;
	509
14ce26e7 FB	510	/* processor features (e.g. for CPUID insn) */
	511	uint32_t cpuid_vendor1;
	512	uint32_t cpuid_vendor2;
	513	uint32_t cpuid_vendor3;
	514	uint32_t cpuid_version;
	515	uint32_t cpuid_features;
9df217a3	516	uint32_t cpuid_ext_features;
14ce26e7	517
9df217a3 FB	518	#ifdef USE_KQEMU
	519	int kqemu_enabled;
	520	#endif
14ce26e7 FB	521	/* in order to simplify APIC support, we leave this pointer to the
	522	user */
	523	struct APICState *apic_state;
2c0262af FB	524	/* user data */
	525	void *opaque;
	526	} CPUX86State;
	527
2c0262af FB	528	CPUX86State *cpu_x86_init(void);
	529	int cpu_x86_exec(CPUX86State *s);
	530	void cpu_x86_close(CPUX86State *s);
d720b93d	531	int cpu_get_pic_interrupt(CPUX86State *s);
2ee73ac3 FB	532	/* MSDOS compatibility mode FPU exception support */
2ee73ac3 FB	533	void cpu_set_ferr(CPUX86State *s);
2c0262af FB	534
	535	/* this function must always be used to load data in the segment
	536	cache: it synchronizes the hflags with the segment cache values */
	537	static inline void cpu_x86_load_seg_cache(CPUX86State *env,
	538	int seg_reg, unsigned int selector,
14ce26e7	539	uint32_t base, unsigned int limit,
2c0262af FB	540	unsigned int flags)
	541	{
	542	SegmentCache *sc;
	543	unsigned int new_hflags;
	544
	545	sc = &env->segs[seg_reg];
	546	sc->selector = selector;
	547	sc->base = base;
	548	sc->limit = limit;
	549	sc->flags = flags;
	550
	551	/* update the hidden flags */
14ce26e7 FB	552	{
	553	if (seg_reg == R_CS) {
	554	#ifdef TARGET_X86_64
	555	if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
	556	/* long mode */
	557	env->hflags \|= HF_CS32_MASK \| HF_SS32_MASK \| HF_CS64_MASK;
	558	env->hflags &= ~(HF_ADDSEG_MASK);
	559	} else
	560	#endif
	561	{
	562	/* legacy / compatibility case */
	563	new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
	564	>> (DESC_B_SHIFT - HF_CS32_SHIFT);
	565	env->hflags = (env->hflags & ~(HF_CS32_MASK \| HF_CS64_MASK)) \|
	566	new_hflags;
	567	}
	568	}
	569	new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
	570	>> (DESC_B_SHIFT - HF_SS32_SHIFT);
	571	if (env->hflags & HF_CS64_MASK) {
	572	/* zero base assumed for DS, ES and SS in long mode */
	573	} else if (!(env->cr[0] & CR0_PE_MASK) \|\|
735a8fd3 FB	574	(env->eflags & VM_MASK) \|\|
735a8fd3 FB	575	!(env->hflags & HF_CS32_MASK)) {
14ce26e7 FB	576	/* XXX: try to avoid this test. The problem comes from the
	577	fact that is real mode or vm86 mode we only modify the
	578	'base' and 'selector' fields of the segment cache to go
	579	faster. A solution may be to force addseg to one in
	580	translate-i386.c. */
	581	new_hflags \|= HF_ADDSEG_MASK;
	582	} else {
735a8fd3 FB	583	new_hflags \|= ((env->segs[R_DS].base \|
	584	env->segs[R_ES].base \|
	585	env->segs[R_SS].base) != 0) <<
14ce26e7 FB	586	HF_ADDSEG_SHIFT;
	587	}
	588	env->hflags = (env->hflags &
	589	~(HF_SS32_MASK \| HF_ADDSEG_MASK)) \| new_hflags;
2c0262af	590	}
2c0262af FB	591	}
	592
	593	/* wrapper, just in case memory mappings must be changed */
	594	static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
	595	{
	596	#if HF_CPL_MASK == 3
	597	s->hflags = (s->hflags & ~HF_CPL_MASK) \| cpl;
	598	#else
	599	#error HF_CPL_MASK is hardcoded
	600	#endif
	601	}
	602
1f1af9fd FB	603	/* used for debug or cpu save/restore */
	604	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f);
	605	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
	606
2c0262af FB	607	/* the following helpers are only usable in user mode simulation as
	608	they can trigger unexpected exceptions */
	609	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
	610	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32);
	611	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32);
	612
	613	/* you can call this signal handler from your SIGBUS and SIGSEGV
	614	signal handlers to inform the virtual CPU of exceptions. non zero
	615	is returned if the signal was handled by the virtual CPU. */
	616	struct siginfo;
	617	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	618	void *puc);
461c0471	619	void cpu_x86_set_a20(CPUX86State *env, int a20_state);
2c0262af	620
28ab0e2e FB	621	uint64_t cpu_get_tsc(CPUX86State *env);
28ab0e2e FB	622
14ce26e7 FB	623	void cpu_set_apic_base(CPUX86State *env, uint64_t val);
14ce26e7 FB	624	uint64_t cpu_get_apic_base(CPUX86State *env);
9230e66e FB	625	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
	626	#ifndef NO_CPU_IO_DEFS
	627	uint8_t cpu_get_apic_tpr(CPUX86State *env);
	628	#endif
14ce26e7	629
64a595f2 FB	630	/* will be suppressed */
	631	void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
	632
2c0262af FB	633	/* used to debug */
	634	#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
	635	#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
2c0262af FB	636
	637	#define TARGET_PAGE_BITS 12
	638	#include "cpu-all.h"
	639
	640	#endif /* CPU_I386_H */