[mirror_qemu.git] / target-i386 / cpu.h

/*
 * i386 virtual CPU header
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_I386_H
#define CPU_I386_H

#define TARGET_LONG_BITS 32

#include "cpu-defs.h"

#define R_EAX 0
#define R_ECX 1
#define R_EDX 2
#define R_EBX 3
#define R_ESP 4
#define R_EBP 5
#define R_ESI 6
#define R_EDI 7

#define R_AL 0
#define R_CL 1
#define R_DL 2
#define R_BL 3
#define R_AH 4
#define R_CH 5
#define R_DH 6
#define R_BH 7

#define R_ES 0
#define R_CS 1
#define R_SS 2
#define R_DS 3
#define R_FS 4
#define R_GS 5

/* segment descriptor fields */
#define DESC_G_MASK     (1 << 23)
#define DESC_B_SHIFT    22
#define DESC_B_MASK     (1 << DESC_B_SHIFT)
#define DESC_AVL_MASK   (1 << 20)
#define DESC_P_MASK     (1 << 15)
#define DESC_DPL_SHIFT  13
#define DESC_S_MASK     (1 << 12)
#define DESC_TYPE_SHIFT 8
#define DESC_A_MASK     (1 << 8)

#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
#define DESC_C_MASK     (1 << 10) /* code: conforming */
#define DESC_R_MASK     (1 << 9)  /* code: readable */

#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
#define DESC_W_MASK     (1 << 9)  /* data: writable */

#define DESC_TSS_BUSY_MASK (1 << 9)

/* eflags masks */
#define CC_C   	0x0001
#define CC_P 	0x0004
#define CC_A	0x0010
#define CC_Z	0x0040
#define CC_S    0x0080
#define CC_O    0x0800

#define TF_SHIFT   8
#define IOPL_SHIFT 12
#define VM_SHIFT   17

#define TF_MASK 		0x00000100
#define IF_MASK 		0x00000200
#define DF_MASK 		0x00000400
#define IOPL_MASK		0x00003000
#define NT_MASK	         	0x00004000
#define RF_MASK			0x00010000
#define VM_MASK			0x00020000
#define AC_MASK			0x00040000 
#define VIF_MASK                0x00080000
#define VIP_MASK                0x00100000
#define ID_MASK                 0x00200000

/* hidden flags - used internally by qemu to represent additionnal cpu
   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
   with eflags. */
/* current cpl */
#define HF_CPL_SHIFT         0
/* true if soft mmu is being used */
#define HF_SOFTMMU_SHIFT     2
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
#define HF_CS32_SHIFT        4
#define HF_SS32_SHIFT        5
/* zero base for DS, ES and SS */
#define HF_ADDSEG_SHIFT      6
/* copy of CR0.PE (protected mode) */
#define HF_PE_SHIFT          7
#define HF_TF_SHIFT          8 /* must be same as eflags */
#define HF_IOPL_SHIFT       12 /* must be same as eflags */
#define HF_VM_SHIFT         17 /* must be same as eflags */

#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
#define HF_PE_MASK           (1 << HF_PE_SHIFT)

#define CR0_PE_MASK  (1 << 0)
#define CR0_TS_MASK  (1 << 3)
#define CR0_WP_MASK  (1 << 16)
#define CR0_AM_MASK  (1 << 18)
#define CR0_PG_MASK  (1 << 31)

#define CR4_VME_MASK  (1 << 0)
#define CR4_PVI_MASK  (1 << 1)
#define CR4_TSD_MASK  (1 << 2)
#define CR4_DE_MASK   (1 << 3)
#define CR4_PSE_MASK  (1 << 4)

#define PG_PRESENT_BIT	0
#define PG_RW_BIT	1
#define PG_USER_BIT	2
#define PG_PWT_BIT	3
#define PG_PCD_BIT	4
#define PG_ACCESSED_BIT	5
#define PG_DIRTY_BIT	6
#define PG_PSE_BIT	7
#define PG_GLOBAL_BIT	8

#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
#define PG_RW_MASK	 (1 << PG_RW_BIT)
#define PG_USER_MASK	 (1 << PG_USER_BIT)
#define PG_PWT_MASK	 (1 << PG_PWT_BIT)
#define PG_PCD_MASK	 (1 << PG_PCD_BIT)
#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
#define PG_PSE_MASK	 (1 << PG_PSE_BIT)
#define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)

#define PG_ERROR_W_BIT     1

#define PG_ERROR_P_MASK    0x01
#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
#define PG_ERROR_U_MASK    0x04
#define PG_ERROR_RSVD_MASK 0x08

#define MSR_IA32_APICBASE               0x1b
#define MSR_IA32_APICBASE_BSP           (1<<8)
#define MSR_IA32_APICBASE_ENABLE        (1<<11)
#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

#define MSR_IA32_SYSENTER_CS            0x174
#define MSR_IA32_SYSENTER_ESP           0x175
#define MSR_IA32_SYSENTER_EIP           0x176

#define EXCP00_DIVZ	0
#define EXCP01_SSTP	1
#define EXCP02_NMI	2
#define EXCP03_INT3	3
#define EXCP04_INTO	4
#define EXCP05_BOUND	5
#define EXCP06_ILLOP	6
#define EXCP07_PREX	7
#define EXCP08_DBLE	8
#define EXCP09_XERR	9
#define EXCP0A_TSS	10
#define EXCP0B_NOSEG	11
#define EXCP0C_STACK	12
#define EXCP0D_GPF	13
#define EXCP0E_PAGE	14
#define EXCP10_COPR	16
#define EXCP11_ALGN	17
#define EXCP12_MCHK	18

enum {
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */

    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
    CC_OP_MULW,
    CC_OP_MULL,

    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADDW,
    CC_OP_ADDL,

    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADCW,
    CC_OP_ADCL,

    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUBW,
    CC_OP_SUBL,

    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SBBW,
    CC_OP_SBBL,

    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
    CC_OP_LOGICW,
    CC_OP_LOGICL,

    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
    CC_OP_INCW,
    CC_OP_INCL,

    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
    CC_OP_DECW,
    CC_OP_DECL,

    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SHLW,
    CC_OP_SHLL,

    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SARW,
    CC_OP_SARL,

    CC_OP_NB,
};

#ifdef __i386__
#define USE_X86LDOUBLE
#endif

#ifdef USE_X86LDOUBLE
typedef long double CPU86_LDouble;
#else
typedef double CPU86_LDouble;
#endif

typedef struct SegmentCache {
    uint32_t selector;
    uint8_t *base;
    uint32_t limit;
    uint32_t flags;
} SegmentCache;

typedef struct CPUX86State {
    /* standard registers */
    uint32_t regs[8];
    uint32_t eip;
    uint32_t eflags; /* eflags register. During CPU emulation, CC
                        flags and DF are set to zero because they are
                        stored elsewhere */

    /* emulator internal eflags handling */
    uint32_t cc_src;
    uint32_t cc_dst;
    uint32_t cc_op;
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
    uint32_t hflags; /* hidden flags, see HF_xxx constants */

    /* FPU state */
    unsigned int fpstt; /* top of stack index */
    unsigned int fpus;
    unsigned int fpuc;
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
    CPU86_LDouble fpregs[8];    

    /* emulator internal variables */
    CPU86_LDouble ft0;
    union {
	float f;
        double d;
	int i32;
        int64_t i64;
    } fp_convert;
    
    /* segments */
    SegmentCache segs[6]; /* selector values */
    SegmentCache ldt;
    SegmentCache tr;
    SegmentCache gdt; /* only base and limit are used */
    SegmentCache idt; /* only base and limit are used */
    
    /* sysenter registers */
    uint32_t sysenter_cs;
    uint32_t sysenter_esp;
    uint32_t sysenter_eip;
    
    /* exception/interrupt handling */
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int exception_is_int;
    int exception_next_eip;
    struct TranslationBlock *current_tb; /* currently executing TB */
    uint32_t cr[5]; /* NOTE: cr1 is unused */
    uint32_t dr[8]; /* debug registers */
    int interrupt_request; 
    int user_mode_only; /* user mode only simulation */

    /* soft mmu support */
    /* 0 = kernel, 1 = user */
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
    
    /* ice debug support */
    uint32_t breakpoints[MAX_BREAKPOINTS];
    int nb_breakpoints;
    int singlestep_enabled;

    /* user data */
    void *opaque;
} CPUX86State;

#ifndef IN_OP_I386
void cpu_x86_outb(CPUX86State *env, int addr, int val);
void cpu_x86_outw(CPUX86State *env, int addr, int val);
void cpu_x86_outl(CPUX86State *env, int addr, int val);
int cpu_x86_inb(CPUX86State *env, int addr);
int cpu_x86_inw(CPUX86State *env, int addr);
int cpu_x86_inl(CPUX86State *env, int addr);
#endif

CPUX86State *cpu_x86_init(void);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
int cpu_x86_get_pic_interrupt(CPUX86State *s);

/* this function must always be used to load data in the segment
   cache: it synchronizes the hflags with the segment cache values */
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
                                          int seg_reg, unsigned int selector,
                                          uint8_t *base, unsigned int limit, 
                                          unsigned int flags)
{
    SegmentCache *sc;
    unsigned int new_hflags;
    
    sc = &env->segs[seg_reg];
    sc->selector = selector;
    sc->base = base;
    sc->limit = limit;
    sc->flags = flags;

    /* update the hidden flags */
    new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
        >> (DESC_B_SHIFT - HF_CS32_SHIFT);
    new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
        >> (DESC_B_SHIFT - HF_SS32_SHIFT);
    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
        /* XXX: try to avoid this test. The problem comes from the
           fact that is real mode or vm86 mode we only modify the
           'base' and 'selector' fields of the segment cache to go
           faster. A solution may be to force addseg to one in
           translate-i386.c. */
        new_hflags |= HF_ADDSEG_MASK;
    } else {
        new_hflags |= (((unsigned long)env->segs[R_DS].base | 
                        (unsigned long)env->segs[R_ES].base |
                        (unsigned long)env->segs[R_SS].base) != 0) << 
            HF_ADDSEG_SHIFT;
    }
    env->hflags = (env->hflags & 
                   ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
}

/* wrapper, just in case memory mappings must be changed */
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
{
#if HF_CPL_MASK == 3
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
#else
#error HF_CPL_MASK is hardcoded
#endif
}

/* the following helpers are only usable in user mode simulation as
   they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
struct siginfo;
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc);

/* MMU defines */
void cpu_x86_init_mmu(CPUX86State *env);
extern int a20_enabled;

void cpu_x86_set_a20(CPUX86State *env, int a20_state);

/* used to debug */
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

#endif /* CPU_I386_H */
Commit	Line	Data
2c0262af FB	1	/*
	2	* i386 virtual CPU header
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_I386_H
	21	#define CPU_I386_H
	22
3cf1e035 FB	23	#define TARGET_LONG_BITS 32
3cf1e035 FB	24
2c0262af FB	25	#include "cpu-defs.h"
	26
	27	#define R_EAX 0
	28	#define R_ECX 1
	29	#define R_EDX 2
	30	#define R_EBX 3
	31	#define R_ESP 4
	32	#define R_EBP 5
	33	#define R_ESI 6
	34	#define R_EDI 7
	35
	36	#define R_AL 0
	37	#define R_CL 1
	38	#define R_DL 2
	39	#define R_BL 3
	40	#define R_AH 4
	41	#define R_CH 5
	42	#define R_DH 6
	43	#define R_BH 7
	44
	45	#define R_ES 0
	46	#define R_CS 1
	47	#define R_SS 2
	48	#define R_DS 3
	49	#define R_FS 4
	50	#define R_GS 5
	51
	52	/* segment descriptor fields */
	53	#define DESC_G_MASK (1 << 23)
	54	#define DESC_B_SHIFT 22
	55	#define DESC_B_MASK (1 << DESC_B_SHIFT)
	56	#define DESC_AVL_MASK (1 << 20)
	57	#define DESC_P_MASK (1 << 15)
	58	#define DESC_DPL_SHIFT 13
	59	#define DESC_S_MASK (1 << 12)
	60	#define DESC_TYPE_SHIFT 8
	61	#define DESC_A_MASK (1 << 8)
	62
e670b89e FB	63	#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
	64	#define DESC_C_MASK (1 << 10) /* code: conforming */
	65	#define DESC_R_MASK (1 << 9) /* code: readable */
2c0262af	66
e670b89e FB	67	#define DESC_E_MASK (1 << 10) /* data: expansion direction */
	68	#define DESC_W_MASK (1 << 9) /* data: writable */
	69
	70	#define DESC_TSS_BUSY_MASK (1 << 9)
2c0262af FB	71
	72	/* eflags masks */
	73	#define CC_C 0x0001
	74	#define CC_P 0x0004
	75	#define CC_A 0x0010
	76	#define CC_Z 0x0040
	77	#define CC_S 0x0080
	78	#define CC_O 0x0800
	79
	80	#define TF_SHIFT 8
	81	#define IOPL_SHIFT 12
	82	#define VM_SHIFT 17
	83
	84	#define TF_MASK 0x00000100
	85	#define IF_MASK 0x00000200
	86	#define DF_MASK 0x00000400
	87	#define IOPL_MASK 0x00003000
	88	#define NT_MASK 0x00004000
	89	#define RF_MASK 0x00010000
	90	#define VM_MASK 0x00020000
	91	#define AC_MASK 0x00040000
	92	#define VIF_MASK 0x00080000
	93	#define VIP_MASK 0x00100000
	94	#define ID_MASK 0x00200000
	95
	96	/* hidden flags - used internally by qemu to represent additionnal cpu
	97	states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
	98	using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
	99	with eflags. */
	100	/* current cpl */
	101	#define HF_CPL_SHIFT 0
	102	/* true if soft mmu is being used */
	103	#define HF_SOFTMMU_SHIFT 2
	104	/* true if hardware interrupts must be disabled for next instruction */
	105	#define HF_INHIBIT_IRQ_SHIFT 3
	106	/* 16 or 32 segments */
	107	#define HF_CS32_SHIFT 4
	108	#define HF_SS32_SHIFT 5
	109	/* zero base for DS, ES and SS */
	110	#define HF_ADDSEG_SHIFT 6
65262d57 FB	111	/* copy of CR0.PE (protected mode) */
	112	#define HF_PE_SHIFT 7
	113	#define HF_TF_SHIFT 8 /* must be same as eflags */
	114	#define HF_IOPL_SHIFT 12 /* must be same as eflags */
	115	#define HF_VM_SHIFT 17 /* must be same as eflags */
2c0262af FB	116
	117	#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
	118	#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
	119	#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
	120	#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
	121	#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
	122	#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
65262d57	123	#define HF_PE_MASK (1 << HF_PE_SHIFT)
2c0262af FB	124
	125	#define CR0_PE_MASK (1 << 0)
	126	#define CR0_TS_MASK (1 << 3)
	127	#define CR0_WP_MASK (1 << 16)
	128	#define CR0_AM_MASK (1 << 18)
	129	#define CR0_PG_MASK (1 << 31)
	130
	131	#define CR4_VME_MASK (1 << 0)
	132	#define CR4_PVI_MASK (1 << 1)
	133	#define CR4_TSD_MASK (1 << 2)
	134	#define CR4_DE_MASK (1 << 3)
	135	#define CR4_PSE_MASK (1 << 4)
	136
	137	#define PG_PRESENT_BIT 0
	138	#define PG_RW_BIT 1
	139	#define PG_USER_BIT 2
	140	#define PG_PWT_BIT 3
	141	#define PG_PCD_BIT 4
	142	#define PG_ACCESSED_BIT 5
	143	#define PG_DIRTY_BIT 6
	144	#define PG_PSE_BIT 7
	145	#define PG_GLOBAL_BIT 8
	146
	147	#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
	148	#define PG_RW_MASK (1 << PG_RW_BIT)
	149	#define PG_USER_MASK (1 << PG_USER_BIT)
	150	#define PG_PWT_MASK (1 << PG_PWT_BIT)
	151	#define PG_PCD_MASK (1 << PG_PCD_BIT)
	152	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	153	#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
	154	#define PG_PSE_MASK (1 << PG_PSE_BIT)
	155	#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
	156
	157	#define PG_ERROR_W_BIT 1
	158
	159	#define PG_ERROR_P_MASK 0x01
	160	#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
	161	#define PG_ERROR_U_MASK 0x04
	162	#define PG_ERROR_RSVD_MASK 0x08
	163
	164	#define MSR_IA32_APICBASE 0x1b
	165	#define MSR_IA32_APICBASE_BSP (1<<8)
	166	#define MSR_IA32_APICBASE_ENABLE (1<<11)
	167	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
	168
	169	#define MSR_IA32_SYSENTER_CS 0x174
	170	#define MSR_IA32_SYSENTER_ESP 0x175
	171	#define MSR_IA32_SYSENTER_EIP 0x176
	172
	173	#define EXCP00_DIVZ 0
	174	#define EXCP01_SSTP 1
	175	#define EXCP02_NMI 2
	176	#define EXCP03_INT3 3
	177	#define EXCP04_INTO 4
	178	#define EXCP05_BOUND 5
	179	#define EXCP06_ILLOP 6
	180	#define EXCP07_PREX 7
	181	#define EXCP08_DBLE 8
	182	#define EXCP09_XERR 9
	183	#define EXCP0A_TSS 10
	184	#define EXCP0B_NOSEG 11
	185	#define EXCP0C_STACK 12
	186	#define EXCP0D_GPF 13
	187	#define EXCP0E_PAGE 14
188	#define EXCP10_COPR 16
189	#define EXCP11_ALGN 17
190	#define EXCP12_MCHK 18
191
192	enum {
193	CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
194	CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
d36cd60e FB	195
	196	CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
	197	CC_OP_MULW,
	198	CC_OP_MULL,
2c0262af FB	199
	200	CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	201	CC_OP_ADDW,
	202	CC_OP_ADDL,
	203
	204	CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	205	CC_OP_ADCW,
	206	CC_OP_ADCL,
	207
	208	CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	209	CC_OP_SUBW,
	210	CC_OP_SUBL,
	211
	212	CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	213	CC_OP_SBBW,
	214	CC_OP_SBBL,
	215
	216	CC_OP_LOGICB, /* modify all flags, CC_DST = res */
	217	CC_OP_LOGICW,
	218	CC_OP_LOGICL,
	219
	220	CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	221	CC_OP_INCW,
	222	CC_OP_INCL,
	223
	224	CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	225	CC_OP_DECW,
	226	CC_OP_DECL,
	227
	228	CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
	229	CC_OP_SHLW,
	230	CC_OP_SHLL,
	231
	232	CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
	233	CC_OP_SARW,
	234	CC_OP_SARL,
	235
	236	CC_OP_NB,
	237	};
	238
	239	#ifdef __i386__
	240	#define USE_X86LDOUBLE
	241	#endif
	242
	243	#ifdef USE_X86LDOUBLE
	244	typedef long double CPU86_LDouble;
	245	#else
	246	typedef double CPU86_LDouble;
	247	#endif
	248
	249	typedef struct SegmentCache {
	250	uint32_t selector;
	251	uint8_t *base;
	252	uint32_t limit;
	253	uint32_t flags;
	254	} SegmentCache;
	255
	256	typedef struct CPUX86State {
	257	/* standard registers */
	258	uint32_t regs[8];
	259	uint32_t eip;
	260	uint32_t eflags; /* eflags register. During CPU emulation, CC
	261	flags and DF are set to zero because they are
	262	stored elsewhere */
263
264	/* emulator internal eflags handling */
265	uint32_t cc_src;
266	uint32_t cc_dst;
267	uint32_t cc_op;
268	int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
269	uint32_t hflags; /* hidden flags, see HF_xxx constants */
270
271	/* FPU state */
272	unsigned int fpstt; /* top of stack index */
273	unsigned int fpus;
274	unsigned int fpuc;
275	uint8_t fptags[8]; /* 0 = valid, 1 = empty */
276	CPU86_LDouble fpregs[8];
277
278	/* emulator internal variables */
279	CPU86_LDouble ft0;
280	union {
281	float f;
282	double d;
283	int i32;
284	int64_t i64;
285	} fp_convert;
286
287	/* segments */
288	SegmentCache segs[6]; /* selector values */
289	SegmentCache ldt;
290	SegmentCache tr;
291	SegmentCache gdt; /* only base and limit are used */
292	SegmentCache idt; /* only base and limit are used */
293
294	/* sysenter registers */
295	uint32_t sysenter_cs;
296	uint32_t sysenter_esp;
297	uint32_t sysenter_eip;
298
299	/* exception/interrupt handling */
300	jmp_buf jmp_env;
301	int exception_index;
302	int error_code;
303	int exception_is_int;
304	int exception_next_eip;
305	struct TranslationBlock current_tb; / currently executing TB */
306	uint32_t cr[5]; /* NOTE: cr1 is unused */
307	uint32_t dr[8]; /* debug registers */
308	int interrupt_request;
309	int user_mode_only; /* user mode only simulation */
310
311	/* soft mmu support */
312	/* 0 = kernel, 1 = user */
313	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
314	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
315
316	/* ice debug support */
317	uint32_t breakpoints[MAX_BREAKPOINTS];
318	int nb_breakpoints;
319	int singlestep_enabled;
320
321	/* user data */
322	void *opaque;
323	} CPUX86State;
324
325	#ifndef IN_OP_I386
326	void cpu_x86_outb(CPUX86State *env, int addr, int val);
327	void cpu_x86_outw(CPUX86State *env, int addr, int val);
328	void cpu_x86_outl(CPUX86State *env, int addr, int val);
329	int cpu_x86_inb(CPUX86State *env, int addr);
330	int cpu_x86_inw(CPUX86State *env, int addr);
331	int cpu_x86_inl(CPUX86State *env, int addr);
332	#endif
333
334	CPUX86State *cpu_x86_init(void);
335	int cpu_x86_exec(CPUX86State *s);
336	void cpu_x86_close(CPUX86State *s);
337	int cpu_x86_get_pic_interrupt(CPUX86State *s);
338
339	/* this function must always be used to load data in the segment
340	cache: it synchronizes the hflags with the segment cache values */
341	static inline void cpu_x86_load_seg_cache(CPUX86State *env,
342	int seg_reg, unsigned int selector,
343	uint8_t *base, unsigned int limit,
344	unsigned int flags)
345	{
346	SegmentCache *sc;
347	unsigned int new_hflags;
348
349	sc = &env->segs[seg_reg];
350	sc->selector = selector;
351	sc->base = base;
352	sc->limit = limit;
353	sc->flags = flags;
354
355	/* update the hidden flags */
356	new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
357	>> (DESC_B_SHIFT - HF_CS32_SHIFT);
358	new_hflags \|= (env->segs[R_SS].flags & DESC_B_MASK)
359	>> (DESC_B_SHIFT - HF_SS32_SHIFT);
360	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
361	/* XXX: try to avoid this test. The problem comes from the
362	fact that is real mode or vm86 mode we only modify the
363	'base' and 'selector' fields of the segment cache to go
364	faster. A solution may be to force addseg to one in
365	translate-i386.c. */
366	new_hflags \|= HF_ADDSEG_MASK;
367	} else {
368	new_hflags \|= (((unsigned long)env->segs[R_DS].base \|
369	(unsigned long)env->segs[R_ES].base \|
370	(unsigned long)env->segs[R_SS].base) != 0) <<
371	HF_ADDSEG_SHIFT;
372	}
373	env->hflags = (env->hflags &
374	~(HF_CS32_MASK \| HF_SS32_MASK \| HF_ADDSEG_MASK)) \| new_hflags;
375	}
376
377	/* wrapper, just in case memory mappings must be changed */
378	static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
379	{
380	#if HF_CPL_MASK == 3
381	s->hflags = (s->hflags & ~HF_CPL_MASK) \| cpl;
382	#else
383	#error HF_CPL_MASK is hardcoded
384	#endif
385	}
386
387	/* the following helpers are only usable in user mode simulation as
388	they can trigger unexpected exceptions */
389	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
390	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32);
391	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32);
392
393	/* you can call this signal handler from your SIGBUS and SIGSEGV
394	signal handlers to inform the virtual CPU of exceptions. non zero
395	is returned if the signal was handled by the virtual CPU. */
396	struct siginfo;
397	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
398	void *puc);
399
400	/* MMU defines */
401	void cpu_x86_init_mmu(CPUX86State *env);
461c0471 FB	402	extern int a20_enabled;
	403
	404	void cpu_x86_set_a20(CPUX86State *env, int a20_state);
2c0262af FB	405
	406	/* used to debug */
	407	#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
	408	#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
	409	void cpu_x86_dump_state(CPUX86State env, FILE f, int flags);
	410
	411	#define TARGET_PAGE_BITS 12
	412	#include "cpu-all.h"
	413
	414	#endif /* CPU_I386_H */