[mirror_qemu.git] / target-i386 / cpu.h

/*
 * i386 virtual CPU header
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_I386_H
#define CPU_I386_H

#define TARGET_LONG_BITS 32

#include "cpu-defs.h"

#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
#define USE_CODE_COPY
#endif

#define R_EAX 0
#define R_ECX 1
#define R_EDX 2
#define R_EBX 3
#define R_ESP 4
#define R_EBP 5
#define R_ESI 6
#define R_EDI 7

#define R_AL 0
#define R_CL 1
#define R_DL 2
#define R_BL 3
#define R_AH 4
#define R_CH 5
#define R_DH 6
#define R_BH 7

#define R_ES 0
#define R_CS 1
#define R_SS 2
#define R_DS 3
#define R_FS 4
#define R_GS 5

/* segment descriptor fields */
#define DESC_G_MASK     (1 << 23)
#define DESC_B_SHIFT    22
#define DESC_B_MASK     (1 << DESC_B_SHIFT)
#define DESC_AVL_MASK   (1 << 20)
#define DESC_P_MASK     (1 << 15)
#define DESC_DPL_SHIFT  13
#define DESC_S_MASK     (1 << 12)
#define DESC_TYPE_SHIFT 8
#define DESC_A_MASK     (1 << 8)

#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
#define DESC_C_MASK     (1 << 10) /* code: conforming */
#define DESC_R_MASK     (1 << 9)  /* code: readable */

#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
#define DESC_W_MASK     (1 << 9)  /* data: writable */

#define DESC_TSS_BUSY_MASK (1 << 9)

/* eflags masks */
#define CC_C   	0x0001
#define CC_P 	0x0004
#define CC_A	0x0010
#define CC_Z	0x0040
#define CC_S    0x0080
#define CC_O    0x0800

#define TF_SHIFT   8
#define IOPL_SHIFT 12
#define VM_SHIFT   17

#define TF_MASK 		0x00000100
#define IF_MASK 		0x00000200
#define DF_MASK 		0x00000400
#define IOPL_MASK		0x00003000
#define NT_MASK	         	0x00004000
#define RF_MASK			0x00010000
#define VM_MASK			0x00020000
#define AC_MASK			0x00040000 
#define VIF_MASK                0x00080000
#define VIP_MASK                0x00100000
#define ID_MASK                 0x00200000

/* hidden flags - used internally by qemu to represent additionnal cpu
   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
   with eflags. */
/* current cpl */
#define HF_CPL_SHIFT         0
/* true if soft mmu is being used */
#define HF_SOFTMMU_SHIFT     2
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
#define HF_CS32_SHIFT        4
#define HF_SS32_SHIFT        5
/* zero base for DS, ES and SS */
#define HF_ADDSEG_SHIFT      6
/* copy of CR0.PE (protected mode) */
#define HF_PE_SHIFT          7
#define HF_TF_SHIFT          8 /* must be same as eflags */
#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
#define HF_EM_SHIFT         10
#define HF_TS_SHIFT         11
#define HF_IOPL_SHIFT       12 /* must be same as eflags */
#define HF_VM_SHIFT         17 /* must be same as eflags */

#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
#define HF_PE_MASK           (1 << HF_PE_SHIFT)
#define HF_TF_MASK           (1 << HF_TF_SHIFT)
#define HF_MP_MASK           (1 << HF_MP_SHIFT)
#define HF_EM_MASK           (1 << HF_EM_SHIFT)
#define HF_TS_MASK           (1 << HF_TS_SHIFT)

#define CR0_PE_MASK  (1 << 0)
#define CR0_MP_MASK  (1 << 1)
#define CR0_EM_MASK  (1 << 2)
#define CR0_TS_MASK  (1 << 3)
#define CR0_NE_MASK  (1 << 5)
#define CR0_WP_MASK  (1 << 16)
#define CR0_AM_MASK  (1 << 18)
#define CR0_PG_MASK  (1 << 31)

#define CR4_VME_MASK  (1 << 0)
#define CR4_PVI_MASK  (1 << 1)
#define CR4_TSD_MASK  (1 << 2)
#define CR4_DE_MASK   (1 << 3)
#define CR4_PSE_MASK  (1 << 4)
#define CR4_PAE_MASK  (1 << 5)
#define CR4_PGE_MASK  (1 << 7)

#define PG_PRESENT_BIT	0
#define PG_RW_BIT	1
#define PG_USER_BIT	2
#define PG_PWT_BIT	3
#define PG_PCD_BIT	4
#define PG_ACCESSED_BIT	5
#define PG_DIRTY_BIT	6
#define PG_PSE_BIT	7
#define PG_GLOBAL_BIT	8

#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
#define PG_RW_MASK	 (1 << PG_RW_BIT)
#define PG_USER_MASK	 (1 << PG_USER_BIT)
#define PG_PWT_MASK	 (1 << PG_PWT_BIT)
#define PG_PCD_MASK	 (1 << PG_PCD_BIT)
#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
#define PG_PSE_MASK	 (1 << PG_PSE_BIT)
#define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)

#define PG_ERROR_W_BIT     1

#define PG_ERROR_P_MASK    0x01
#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
#define PG_ERROR_U_MASK    0x04
#define PG_ERROR_RSVD_MASK 0x08

#define MSR_IA32_APICBASE               0x1b
#define MSR_IA32_APICBASE_BSP           (1<<8)
#define MSR_IA32_APICBASE_ENABLE        (1<<11)
#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

#define MSR_IA32_SYSENTER_CS            0x174
#define MSR_IA32_SYSENTER_ESP           0x175
#define MSR_IA32_SYSENTER_EIP           0x176

#define EXCP00_DIVZ	0
#define EXCP01_SSTP	1
#define EXCP02_NMI	2
#define EXCP03_INT3	3
#define EXCP04_INTO	4
#define EXCP05_BOUND	5
#define EXCP06_ILLOP	6
#define EXCP07_PREX	7
#define EXCP08_DBLE	8
#define EXCP09_XERR	9
#define EXCP0A_TSS	10
#define EXCP0B_NOSEG	11
#define EXCP0C_STACK	12
#define EXCP0D_GPF	13
#define EXCP0E_PAGE	14
#define EXCP10_COPR	16
#define EXCP11_ALGN	17
#define EXCP12_MCHK	18

enum {
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */

    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
    CC_OP_MULW,
    CC_OP_MULL,

    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADDW,
    CC_OP_ADDL,

    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADCW,
    CC_OP_ADCL,

    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUBW,
    CC_OP_SUBL,

    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SBBW,
    CC_OP_SBBL,

    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
    CC_OP_LOGICW,
    CC_OP_LOGICL,

    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
    CC_OP_INCW,
    CC_OP_INCL,

    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
    CC_OP_DECW,
    CC_OP_DECL,

    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SHLW,
    CC_OP_SHLL,

    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SARW,
    CC_OP_SARL,

    CC_OP_NB,
};

#if defined(__i386__) || defined(__x86_64__)
#define USE_X86LDOUBLE
#endif

#ifdef USE_X86LDOUBLE
typedef long double CPU86_LDouble;
#else
typedef double CPU86_LDouble;
#endif

typedef struct SegmentCache {
    uint32_t selector;
    uint8_t *base;
    uint32_t limit;
    uint32_t flags;
} SegmentCache;

typedef struct CPUX86State {
    /* standard registers */
    uint32_t regs[8];
    uint32_t eip;
    uint32_t eflags; /* eflags register. During CPU emulation, CC
                        flags and DF are set to zero because they are
                        stored elsewhere */

    /* emulator internal eflags handling */
    uint32_t cc_src;
    uint32_t cc_dst;
    uint32_t cc_op;
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
    uint32_t hflags; /* hidden flags, see HF_xxx constants */

    /* FPU state */
    unsigned int fpstt; /* top of stack index */
    unsigned int fpus;
    unsigned int fpuc;
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
    CPU86_LDouble fpregs[8];

    /* emulator internal variables */
    CPU86_LDouble ft0;
    union {
	float f;
        double d;
	int i32;
        int64_t i64;
    } fp_convert;
    
    /* segments */
    SegmentCache segs[6]; /* selector values */
    SegmentCache ldt;
    SegmentCache tr;
    SegmentCache gdt; /* only base and limit are used */
    SegmentCache idt; /* only base and limit are used */
    
    /* sysenter registers */
    uint32_t sysenter_cs;
    uint32_t sysenter_esp;
    uint32_t sysenter_eip;

    /* temporary data for USE_CODE_COPY mode */
#ifdef USE_CODE_COPY
    uint32_t tmp0;
    uint32_t saved_esp;
    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
#endif
    
    /* exception/interrupt handling */
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int exception_is_int;
    int exception_next_eip;
    struct TranslationBlock *current_tb; /* currently executing TB */
    uint32_t cr[5]; /* NOTE: cr1 is unused */
    uint32_t dr[8]; /* debug registers */
    int interrupt_request; 
    int user_mode_only; /* user mode only simulation */

    /* soft mmu support */
    uint32_t a20_mask;
    /* 0 = kernel, 1 = user */
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
    
    /* ice debug support */
    uint32_t breakpoints[MAX_BREAKPOINTS];
    int nb_breakpoints;
    int singlestep_enabled;

    /* user data */
    void *opaque;
} CPUX86State;

#ifndef IN_OP_I386
void cpu_x86_outb(CPUX86State *env, int addr, int val);
void cpu_x86_outw(CPUX86State *env, int addr, int val);
void cpu_x86_outl(CPUX86State *env, int addr, int val);
int cpu_x86_inb(CPUX86State *env, int addr);
int cpu_x86_inw(CPUX86State *env, int addr);
int cpu_x86_inl(CPUX86State *env, int addr);
#endif

CPUX86State *cpu_x86_init(void);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
int cpu_x86_get_pic_interrupt(CPUX86State *s);

/* this function must always be used to load data in the segment
   cache: it synchronizes the hflags with the segment cache values */
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
                                          int seg_reg, unsigned int selector,
                                          uint8_t *base, unsigned int limit, 
                                          unsigned int flags)
{
    SegmentCache *sc;
    unsigned int new_hflags;
    
    sc = &env->segs[seg_reg];
    sc->selector = selector;
    sc->base = base;
    sc->limit = limit;
    sc->flags = flags;

    /* update the hidden flags */
    new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
        >> (DESC_B_SHIFT - HF_CS32_SHIFT);
    new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
        >> (DESC_B_SHIFT - HF_SS32_SHIFT);
    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
        /* XXX: try to avoid this test. The problem comes from the
           fact that is real mode or vm86 mode we only modify the
           'base' and 'selector' fields of the segment cache to go
           faster. A solution may be to force addseg to one in
           translate-i386.c. */
        new_hflags |= HF_ADDSEG_MASK;
    } else {
        new_hflags |= (((unsigned long)env->segs[R_DS].base | 
                        (unsigned long)env->segs[R_ES].base |
                        (unsigned long)env->segs[R_SS].base) != 0) << 
            HF_ADDSEG_SHIFT;
    }
    env->hflags = (env->hflags & 
                   ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
}

/* wrapper, just in case memory mappings must be changed */
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
{
#if HF_CPL_MASK == 3
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
#else
#error HF_CPL_MASK is hardcoded
#endif
}

/* the following helpers are only usable in user mode simulation as
   they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
struct siginfo;
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc);
void cpu_x86_set_a20(CPUX86State *env, int a20_state);

/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);

/* used to debug */
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

#endif /* CPU_I386_H */
Commit	Line	Data
2c0262af FB	1	/*
	2	* i386 virtual CPU header
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_I386_H
	21	#define CPU_I386_H
	22
3cf1e035 FB	23	#define TARGET_LONG_BITS 32
3cf1e035 FB	24
2c0262af FB	25	#include "cpu-defs.h"
2c0262af FB	26
58fe2f10 FB	27	#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
	28	#define USE_CODE_COPY
	29	#endif
	30
2c0262af FB	31	#define R_EAX 0
	32	#define R_ECX 1
	33	#define R_EDX 2
	34	#define R_EBX 3
	35	#define R_ESP 4
	36	#define R_EBP 5
	37	#define R_ESI 6
	38	#define R_EDI 7
	39
	40	#define R_AL 0
	41	#define R_CL 1
	42	#define R_DL 2
	43	#define R_BL 3
	44	#define R_AH 4
	45	#define R_CH 5
	46	#define R_DH 6
	47	#define R_BH 7
	48
	49	#define R_ES 0
	50	#define R_CS 1
	51	#define R_SS 2
	52	#define R_DS 3
	53	#define R_FS 4
	54	#define R_GS 5
	55
	56	/* segment descriptor fields */
	57	#define DESC_G_MASK (1 << 23)
	58	#define DESC_B_SHIFT 22
	59	#define DESC_B_MASK (1 << DESC_B_SHIFT)
	60	#define DESC_AVL_MASK (1 << 20)
	61	#define DESC_P_MASK (1 << 15)
	62	#define DESC_DPL_SHIFT 13
	63	#define DESC_S_MASK (1 << 12)
	64	#define DESC_TYPE_SHIFT 8
	65	#define DESC_A_MASK (1 << 8)
	66
e670b89e FB	67	#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
	68	#define DESC_C_MASK (1 << 10) /* code: conforming */
	69	#define DESC_R_MASK (1 << 9) /* code: readable */
2c0262af	70
e670b89e FB	71	#define DESC_E_MASK (1 << 10) /* data: expansion direction */
	72	#define DESC_W_MASK (1 << 9) /* data: writable */
	73
	74	#define DESC_TSS_BUSY_MASK (1 << 9)
2c0262af FB	75
	76	/* eflags masks */
	77	#define CC_C 0x0001
	78	#define CC_P 0x0004
	79	#define CC_A 0x0010
	80	#define CC_Z 0x0040
	81	#define CC_S 0x0080
	82	#define CC_O 0x0800
	83
	84	#define TF_SHIFT 8
	85	#define IOPL_SHIFT 12
	86	#define VM_SHIFT 17
	87
	88	#define TF_MASK 0x00000100
	89	#define IF_MASK 0x00000200
	90	#define DF_MASK 0x00000400
	91	#define IOPL_MASK 0x00003000
	92	#define NT_MASK 0x00004000
	93	#define RF_MASK 0x00010000
	94	#define VM_MASK 0x00020000
	95	#define AC_MASK 0x00040000
	96	#define VIF_MASK 0x00080000
	97	#define VIP_MASK 0x00100000
	98	#define ID_MASK 0x00200000
	99
	100	/* hidden flags - used internally by qemu to represent additionnal cpu
	101	states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
	102	using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
	103	with eflags. */
	104	/* current cpl */
	105	#define HF_CPL_SHIFT 0
	106	/* true if soft mmu is being used */
	107	#define HF_SOFTMMU_SHIFT 2
	108	/* true if hardware interrupts must be disabled for next instruction */
	109	#define HF_INHIBIT_IRQ_SHIFT 3
	110	/* 16 or 32 segments */
	111	#define HF_CS32_SHIFT 4
	112	#define HF_SS32_SHIFT 5
	113	/* zero base for DS, ES and SS */
	114	#define HF_ADDSEG_SHIFT 6
65262d57 FB	115	/* copy of CR0.PE (protected mode) */
	116	#define HF_PE_SHIFT 7
	117	#define HF_TF_SHIFT 8 /* must be same as eflags */
7eee2a50 FB	118	#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
	119	#define HF_EM_SHIFT 10
	120	#define HF_TS_SHIFT 11
65262d57 FB	121	#define HF_IOPL_SHIFT 12 /* must be same as eflags */
65262d57 FB	122	#define HF_VM_SHIFT 17 /* must be same as eflags */
2c0262af FB	123
	124	#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
	125	#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
	126	#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
	127	#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
	128	#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
	129	#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
65262d57	130	#define HF_PE_MASK (1 << HF_PE_SHIFT)
58fe2f10	131	#define HF_TF_MASK (1 << HF_TF_SHIFT)
7eee2a50 FB	132	#define HF_MP_MASK (1 << HF_MP_SHIFT)
	133	#define HF_EM_MASK (1 << HF_EM_SHIFT)
	134	#define HF_TS_MASK (1 << HF_TS_SHIFT)
2c0262af FB	135
2c0262af FB	136	#define CR0_PE_MASK (1 << 0)
7eee2a50 FB	137	#define CR0_MP_MASK (1 << 1)
7eee2a50 FB	138	#define CR0_EM_MASK (1 << 2)
2c0262af	139	#define CR0_TS_MASK (1 << 3)
7eee2a50	140	#define CR0_NE_MASK (1 << 5)
2c0262af FB	141	#define CR0_WP_MASK (1 << 16)
	142	#define CR0_AM_MASK (1 << 18)
	143	#define CR0_PG_MASK (1 << 31)
	144
	145	#define CR4_VME_MASK (1 << 0)
	146	#define CR4_PVI_MASK (1 << 1)
	147	#define CR4_TSD_MASK (1 << 2)
	148	#define CR4_DE_MASK (1 << 3)
	149	#define CR4_PSE_MASK (1 << 4)
64a595f2 FB	150	#define CR4_PAE_MASK (1 << 5)
64a595f2 FB	151	#define CR4_PGE_MASK (1 << 7)
2c0262af FB	152
	153	#define PG_PRESENT_BIT 0
	154	#define PG_RW_BIT 1
	155	#define PG_USER_BIT 2
	156	#define PG_PWT_BIT 3
	157	#define PG_PCD_BIT 4
	158	#define PG_ACCESSED_BIT 5
	159	#define PG_DIRTY_BIT 6
	160	#define PG_PSE_BIT 7
	161	#define PG_GLOBAL_BIT 8
	162
	163	#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
	164	#define PG_RW_MASK (1 << PG_RW_BIT)
	165	#define PG_USER_MASK (1 << PG_USER_BIT)
	166	#define PG_PWT_MASK (1 << PG_PWT_BIT)
	167	#define PG_PCD_MASK (1 << PG_PCD_BIT)
	168	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	169	#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
	170	#define PG_PSE_MASK (1 << PG_PSE_BIT)
	171	#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
	172
	173	#define PG_ERROR_W_BIT 1
	174
	175	#define PG_ERROR_P_MASK 0x01
	176	#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
	177	#define PG_ERROR_U_MASK 0x04
	178	#define PG_ERROR_RSVD_MASK 0x08
	179
	180	#define MSR_IA32_APICBASE 0x1b
	181	#define MSR_IA32_APICBASE_BSP (1<<8)
	182	#define MSR_IA32_APICBASE_ENABLE (1<<11)
	183	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
	184
	185	#define MSR_IA32_SYSENTER_CS 0x174
	186	#define MSR_IA32_SYSENTER_ESP 0x175
	187	#define MSR_IA32_SYSENTER_EIP 0x176
	188
	189	#define EXCP00_DIVZ 0
	190	#define EXCP01_SSTP 1
	191	#define EXCP02_NMI 2
	192	#define EXCP03_INT3 3
	193	#define EXCP04_INTO 4
	194	#define EXCP05_BOUND 5
	195	#define EXCP06_ILLOP 6
	196	#define EXCP07_PREX 7
	197	#define EXCP08_DBLE 8
	198	#define EXCP09_XERR 9
	199	#define EXCP0A_TSS 10
	200	#define EXCP0B_NOSEG 11
	201	#define EXCP0C_STACK 12
	202	#define EXCP0D_GPF 13
	203	#define EXCP0E_PAGE 14
	204	#define EXCP10_COPR 16
	205	#define EXCP11_ALGN 17
	206	#define EXCP12_MCHK 18
	207
	208	enum {
	209	CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
	210	CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
d36cd60e FB	211
	212	CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
	213	CC_OP_MULW,
	214	CC_OP_MULL,
2c0262af FB	215
	216	CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	217	CC_OP_ADDW,
	218	CC_OP_ADDL,
	219
	220	CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	221	CC_OP_ADCW,
	222	CC_OP_ADCL,
	223
	224	CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	225	CC_OP_SUBW,
	226	CC_OP_SUBL,
	227
	228	CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	229	CC_OP_SBBW,
	230	CC_OP_SBBL,
	231
	232	CC_OP_LOGICB, /* modify all flags, CC_DST = res */
	233	CC_OP_LOGICW,
	234	CC_OP_LOGICL,
	235
	236	CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	237	CC_OP_INCW,
	238	CC_OP_INCL,
	239
	240	CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	241	CC_OP_DECW,
	242	CC_OP_DECL,
	243
	244	CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
	245	CC_OP_SHLW,
	246	CC_OP_SHLL,
	247
	248	CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
	249	CC_OP_SARW,
	250	CC_OP_SARL,
	251
	252	CC_OP_NB,
	253	};
	254
bc51c5c9	255	#if defined(__i386__) \|\| defined(__x86_64__)
2c0262af FB	256	#define USE_X86LDOUBLE
	257	#endif
	258
	259	#ifdef USE_X86LDOUBLE
	260	typedef long double CPU86_LDouble;
	261	#else
	262	typedef double CPU86_LDouble;
	263	#endif
	264
	265	typedef struct SegmentCache {
	266	uint32_t selector;
	267	uint8_t *base;
	268	uint32_t limit;
	269	uint32_t flags;
	270	} SegmentCache;
	271
	272	typedef struct CPUX86State {
	273	/* standard registers */
	274	uint32_t regs[8];
	275	uint32_t eip;
	276	uint32_t eflags; /* eflags register. During CPU emulation, CC
	277	flags and DF are set to zero because they are
	278	stored elsewhere */
	279
	280	/* emulator internal eflags handling */
	281	uint32_t cc_src;
	282	uint32_t cc_dst;
	283	uint32_t cc_op;
	284	int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
	285	uint32_t hflags; /* hidden flags, see HF_xxx constants */
	286
	287	/* FPU state */
	288	unsigned int fpstt; /* top of stack index */
	289	unsigned int fpus;
	290	unsigned int fpuc;
	291	uint8_t fptags[8]; /* 0 = valid, 1 = empty */
7eee2a50	292	CPU86_LDouble fpregs[8];
2c0262af FB	293
	294	/* emulator internal variables */
	295	CPU86_LDouble ft0;
	296	union {
	297	float f;
	298	double d;
	299	int i32;
	300	int64_t i64;
	301	} fp_convert;
	302
	303	/* segments */
	304	SegmentCache segs[6]; /* selector values */
	305	SegmentCache ldt;
	306	SegmentCache tr;
	307	SegmentCache gdt; /* only base and limit are used */
	308	SegmentCache idt; /* only base and limit are used */
	309
	310	/* sysenter registers */
	311	uint32_t sysenter_cs;
	312	uint32_t sysenter_esp;
	313	uint32_t sysenter_eip;
58fe2f10 FB	314
58fe2f10 FB	315	/* temporary data for USE_CODE_COPY mode */
7eee2a50	316	#ifdef USE_CODE_COPY
58fe2f10 FB	317	uint32_t tmp0;
58fe2f10 FB	318	uint32_t saved_esp;
7eee2a50 FB	319	int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
7eee2a50 FB	320	#endif
2c0262af FB	321
	322	/* exception/interrupt handling */
	323	jmp_buf jmp_env;
	324	int exception_index;
	325	int error_code;
	326	int exception_is_int;
	327	int exception_next_eip;
	328	struct TranslationBlock current_tb; / currently executing TB */
	329	uint32_t cr[5]; /* NOTE: cr1 is unused */
	330	uint32_t dr[8]; /* debug registers */
	331	int interrupt_request;
	332	int user_mode_only; /* user mode only simulation */
	333
	334	/* soft mmu support */
64a595f2	335	uint32_t a20_mask;
2c0262af FB	336	/* 0 = kernel, 1 = user */
	337	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
	338	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
	339
	340	/* ice debug support */
	341	uint32_t breakpoints[MAX_BREAKPOINTS];
	342	int nb_breakpoints;
	343	int singlestep_enabled;
	344
	345	/* user data */
	346	void *opaque;
	347	} CPUX86State;
	348
	349	#ifndef IN_OP_I386
	350	void cpu_x86_outb(CPUX86State *env, int addr, int val);
	351	void cpu_x86_outw(CPUX86State *env, int addr, int val);
	352	void cpu_x86_outl(CPUX86State *env, int addr, int val);
	353	int cpu_x86_inb(CPUX86State *env, int addr);
	354	int cpu_x86_inw(CPUX86State *env, int addr);
	355	int cpu_x86_inl(CPUX86State *env, int addr);
	356	#endif
	357
	358	CPUX86State *cpu_x86_init(void);
	359	int cpu_x86_exec(CPUX86State *s);
	360	void cpu_x86_close(CPUX86State *s);
	361	int cpu_x86_get_pic_interrupt(CPUX86State *s);
	362
	363	/* this function must always be used to load data in the segment
	364	cache: it synchronizes the hflags with the segment cache values */
	365	static inline void cpu_x86_load_seg_cache(CPUX86State *env,
	366	int seg_reg, unsigned int selector,
	367	uint8_t *base, unsigned int limit,
	368	unsigned int flags)
	369	{
	370	SegmentCache *sc;
	371	unsigned int new_hflags;
	372
	373	sc = &env->segs[seg_reg];
	374	sc->selector = selector;
	375	sc->base = base;
	376	sc->limit = limit;
	377	sc->flags = flags;
	378
	379	/* update the hidden flags */
	380	new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
	381	>> (DESC_B_SHIFT - HF_CS32_SHIFT);
	382	new_hflags \|= (env->segs[R_SS].flags & DESC_B_MASK)
	383	>> (DESC_B_SHIFT - HF_SS32_SHIFT);
	384	if (!(env->cr[0] & CR0_PE_MASK) \|\| (env->eflags & VM_MASK)) {
	385	/* XXX: try to avoid this test. The problem comes from the
	386	fact that is real mode or vm86 mode we only modify the
	387	'base' and 'selector' fields of the segment cache to go
	388	faster. A solution may be to force addseg to one in
	389	translate-i386.c. */
	390	new_hflags \|= HF_ADDSEG_MASK;
	391	} else {
	392	new_hflags \|= (((unsigned long)env->segs[R_DS].base \|
	393	(unsigned long)env->segs[R_ES].base \|
	394	(unsigned long)env->segs[R_SS].base) != 0) <<
	395	HF_ADDSEG_SHIFT;
	396	}
	397	env->hflags = (env->hflags &
	398	~(HF_CS32_MASK \| HF_SS32_MASK \| HF_ADDSEG_MASK)) \| new_hflags;
	399	}
400
401	/* wrapper, just in case memory mappings must be changed */
402	static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
403	{
404	#if HF_CPL_MASK == 3
405	s->hflags = (s->hflags & ~HF_CPL_MASK) \| cpl;
406	#else
407	#error HF_CPL_MASK is hardcoded
408	#endif
409	}
410
411	/* the following helpers are only usable in user mode simulation as
412	they can trigger unexpected exceptions */
413	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
414	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32);
415	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32);
416
417	/* you can call this signal handler from your SIGBUS and SIGSEGV
418	signal handlers to inform the virtual CPU of exceptions. non zero
419	is returned if the signal was handled by the virtual CPU. */
420	struct siginfo;
421	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
422	void *puc);
461c0471	423	void cpu_x86_set_a20(CPUX86State *env, int a20_state);
2c0262af	424
64a595f2 FB	425	/* will be suppressed */
	426	void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
	427
2c0262af FB	428	/* used to debug */
	429	#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
	430	#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
	431	void cpu_x86_dump_state(CPUX86State env, FILE f, int flags);
	432
	433	#define TARGET_PAGE_BITS 12
	434	#include "cpu-all.h"
	435
	436	#endif /* CPU_I386_H */