[mirror_qemu.git] / target-i386 / cpu.h

/*
 * i386 virtual CPU header
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_I386_H
#define CPU_I386_H

#include "config.h"

#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif

/* target supports implicit self modifying code */
#define TARGET_HAS_SMC
/* support for self modifying code even if the modified instruction is
   close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC

#include "cpu-defs.h"

#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
#define USE_CODE_COPY
#endif

#define R_EAX 0
#define R_ECX 1
#define R_EDX 2
#define R_EBX 3
#define R_ESP 4
#define R_EBP 5
#define R_ESI 6
#define R_EDI 7

#define R_AL 0
#define R_CL 1
#define R_DL 2
#define R_BL 3
#define R_AH 4
#define R_CH 5
#define R_DH 6
#define R_BH 7

#define R_ES 0
#define R_CS 1
#define R_SS 2
#define R_DS 3
#define R_FS 4
#define R_GS 5

/* segment descriptor fields */
#define DESC_G_MASK     (1 << 23)
#define DESC_B_SHIFT    22
#define DESC_B_MASK     (1 << DESC_B_SHIFT)
#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
#define DESC_L_MASK     (1 << DESC_L_SHIFT)
#define DESC_AVL_MASK   (1 << 20)
#define DESC_P_MASK     (1 << 15)
#define DESC_DPL_SHIFT  13
#define DESC_S_MASK     (1 << 12)
#define DESC_TYPE_SHIFT 8
#define DESC_A_MASK     (1 << 8)

#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
#define DESC_C_MASK     (1 << 10) /* code: conforming */
#define DESC_R_MASK     (1 << 9)  /* code: readable */

#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
#define DESC_W_MASK     (1 << 9)  /* data: writable */

#define DESC_TSS_BUSY_MASK (1 << 9)

/* eflags masks */
#define CC_C   	0x0001
#define CC_P 	0x0004
#define CC_A	0x0010
#define CC_Z	0x0040
#define CC_S    0x0080
#define CC_O    0x0800

#define TF_SHIFT   8
#define IOPL_SHIFT 12
#define VM_SHIFT   17

#define TF_MASK 		0x00000100
#define IF_MASK 		0x00000200
#define DF_MASK 		0x00000400
#define IOPL_MASK		0x00003000
#define NT_MASK	         	0x00004000
#define RF_MASK			0x00010000
#define VM_MASK			0x00020000
#define AC_MASK			0x00040000 
#define VIF_MASK                0x00080000
#define VIP_MASK                0x00100000
#define ID_MASK                 0x00200000

/* hidden flags - used internally by qemu to represent additionnal cpu
   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
   with eflags. */
/* current cpl */
#define HF_CPL_SHIFT         0
/* true if soft mmu is being used */
#define HF_SOFTMMU_SHIFT     2
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
#define HF_CS32_SHIFT        4
#define HF_SS32_SHIFT        5
/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
#define HF_ADDSEG_SHIFT      6
/* copy of CR0.PE (protected mode) */
#define HF_PE_SHIFT          7
#define HF_TF_SHIFT          8 /* must be same as eflags */
#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
#define HF_EM_SHIFT         10
#define HF_TS_SHIFT         11
#define HF_IOPL_SHIFT       12 /* must be same as eflags */
#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
#define HF_VM_SHIFT         17 /* must be same as eflags */

#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
#define HF_PE_MASK           (1 << HF_PE_SHIFT)
#define HF_TF_MASK           (1 << HF_TF_SHIFT)
#define HF_MP_MASK           (1 << HF_MP_SHIFT)
#define HF_EM_MASK           (1 << HF_EM_SHIFT)
#define HF_TS_MASK           (1 << HF_TS_SHIFT)
#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)

#define CR0_PE_MASK  (1 << 0)
#define CR0_MP_MASK  (1 << 1)
#define CR0_EM_MASK  (1 << 2)
#define CR0_TS_MASK  (1 << 3)
#define CR0_ET_MASK  (1 << 4)
#define CR0_NE_MASK  (1 << 5)
#define CR0_WP_MASK  (1 << 16)
#define CR0_AM_MASK  (1 << 18)
#define CR0_PG_MASK  (1 << 31)

#define CR4_VME_MASK  (1 << 0)
#define CR4_PVI_MASK  (1 << 1)
#define CR4_TSD_MASK  (1 << 2)
#define CR4_DE_MASK   (1 << 3)
#define CR4_PSE_MASK  (1 << 4)
#define CR4_PAE_MASK  (1 << 5)
#define CR4_PGE_MASK  (1 << 7)
#define CR4_PCE_MASK  (1 << 8)
#define CR4_OSFXSR_MASK (1 << 9)
#define CR4_OSXMMEXCPT_MASK  (1 << 10)

#define PG_PRESENT_BIT	0
#define PG_RW_BIT	1
#define PG_USER_BIT	2
#define PG_PWT_BIT	3
#define PG_PCD_BIT	4
#define PG_ACCESSED_BIT	5
#define PG_DIRTY_BIT	6
#define PG_PSE_BIT	7
#define PG_GLOBAL_BIT	8

#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
#define PG_RW_MASK	 (1 << PG_RW_BIT)
#define PG_USER_MASK	 (1 << PG_USER_BIT)
#define PG_PWT_MASK	 (1 << PG_PWT_BIT)
#define PG_PCD_MASK	 (1 << PG_PCD_BIT)
#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
#define PG_PSE_MASK	 (1 << PG_PSE_BIT)
#define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)

#define PG_ERROR_W_BIT     1

#define PG_ERROR_P_MASK    0x01
#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
#define PG_ERROR_U_MASK    0x04
#define PG_ERROR_RSVD_MASK 0x08

#define MSR_IA32_APICBASE               0x1b
#define MSR_IA32_APICBASE_BSP           (1<<8)
#define MSR_IA32_APICBASE_ENABLE        (1<<11)
#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

#define MSR_IA32_SYSENTER_CS            0x174
#define MSR_IA32_SYSENTER_ESP           0x175
#define MSR_IA32_SYSENTER_EIP           0x176

#define MSR_EFER                        0xc0000080

#define MSR_EFER_SCE   (1 << 0)
#define MSR_EFER_LME   (1 << 8)
#define MSR_EFER_LMA   (1 << 10)
#define MSR_EFER_NXE   (1 << 11)
#define MSR_EFER_FFXSR (1 << 14)

#define MSR_STAR                        0xc0000081
#define MSR_LSTAR                       0xc0000082
#define MSR_CSTAR                       0xc0000083
#define MSR_FMASK                       0xc0000084
#define MSR_FSBASE                      0xc0000100
#define MSR_GSBASE                      0xc0000101
#define MSR_KERNELGSBASE                0xc0000102

/* cpuid_features bits */
#define CPUID_FP87 (1 << 0)
#define CPUID_VME  (1 << 1)
#define CPUID_DE   (1 << 2)
#define CPUID_PSE  (1 << 3)
#define CPUID_TSC  (1 << 4)
#define CPUID_MSR  (1 << 5)
#define CPUID_PAE  (1 << 6)
#define CPUID_MCE  (1 << 7)
#define CPUID_CX8  (1 << 8)
#define CPUID_APIC (1 << 9)
#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
#define CPUID_MTRR (1 << 12)
#define CPUID_PGE  (1 << 13)
#define CPUID_MCA  (1 << 14)
#define CPUID_CMOV (1 << 15)
/* ... */
#define CPUID_MMX  (1 << 23)
#define CPUID_FXSR (1 << 24)
#define CPUID_SSE  (1 << 25)
#define CPUID_SSE2 (1 << 26)

#define EXCP00_DIVZ	0
#define EXCP01_SSTP	1
#define EXCP02_NMI	2
#define EXCP03_INT3	3
#define EXCP04_INTO	4
#define EXCP05_BOUND	5
#define EXCP06_ILLOP	6
#define EXCP07_PREX	7
#define EXCP08_DBLE	8
#define EXCP09_XERR	9
#define EXCP0A_TSS	10
#define EXCP0B_NOSEG	11
#define EXCP0C_STACK	12
#define EXCP0D_GPF	13
#define EXCP0E_PAGE	14
#define EXCP10_COPR	16
#define EXCP11_ALGN	17
#define EXCP12_MCHK	18

enum {
    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */

    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
    CC_OP_MULW,
    CC_OP_MULL,
    CC_OP_MULQ,

    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADDW,
    CC_OP_ADDL,
    CC_OP_ADDQ,

    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADCW,
    CC_OP_ADCL,
    CC_OP_ADCQ,

    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUBW,
    CC_OP_SUBL,
    CC_OP_SUBQ,

    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SBBW,
    CC_OP_SBBL,
    CC_OP_SBBQ,

    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
    CC_OP_LOGICW,
    CC_OP_LOGICL,
    CC_OP_LOGICQ,

    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
    CC_OP_INCW,
    CC_OP_INCL,
    CC_OP_INCQ,

    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
    CC_OP_DECW,
    CC_OP_DECL,
    CC_OP_DECQ,

    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
    CC_OP_SHLW,
    CC_OP_SHLL,
    CC_OP_SHLQ,

    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SARW,
    CC_OP_SARL,
    CC_OP_SARQ,

    CC_OP_NB,
};

#if (defined(__i386__) || defined(__x86_64__)) && !defined(_BSD)
#define USE_X86LDOUBLE
#endif

#ifdef USE_X86LDOUBLE
typedef long double CPU86_LDouble;
#else
typedef double CPU86_LDouble;
#endif

typedef struct SegmentCache {
    uint32_t selector;
    target_ulong base;
    uint32_t limit;
    uint32_t flags;
} SegmentCache;

typedef union {
    uint8_t _b[16];
    uint16_t _w[8];
    uint32_t _l[4];
    uint64_t _q[2];
    float _s[4];
    double _d[2];
} XMMReg;

typedef union {
    uint8_t _b[8];
    uint16_t _w[2];
    uint32_t _l[1];
    uint64_t q;
} MMXReg;

#ifdef WORDS_BIGENDIAN
#define XMM_B(n) _b[15 - (n)]
#define XMM_W(n) _w[7 - (n)]
#define XMM_L(n) _l[3 - (n)]
#define XMM_S(n) _s[3 - (n)]
#define XMM_Q(n) _q[1 - (n)]
#define XMM_D(n) _d[1 - (n)]

#define MMX_B(n) _b[7 - (n)]
#define MMX_W(n) _w[3 - (n)]
#define MMX_L(n) _l[1 - (n)]
#else
#define XMM_B(n) _b[n]
#define XMM_W(n) _w[n]
#define XMM_L(n) _l[n]
#define XMM_S(n) _s[n]
#define XMM_Q(n) _q[n]
#define XMM_D(n) _d[n]

#define MMX_B(n) _b[n]
#define MMX_W(n) _w[n]
#define MMX_L(n) _l[n]
#endif
#define MMX_Q(n) q

#ifdef TARGET_X86_64
#define CPU_NB_REGS 16
#else
#define CPU_NB_REGS 8
#endif

typedef struct CPUX86State {
#if TARGET_LONG_BITS > HOST_LONG_BITS
    /* temporaries if we cannot store them in host registers */
    target_ulong t0, t1, t2;
#endif

    /* standard registers */
    target_ulong regs[CPU_NB_REGS];
    target_ulong eip;
    target_ulong eflags; /* eflags register. During CPU emulation, CC
                        flags and DF are set to zero because they are
                        stored elsewhere */

    /* emulator internal eflags handling */
    target_ulong cc_src;
    target_ulong cc_dst;
    uint32_t cc_op;
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
    uint32_t hflags; /* hidden flags, see HF_xxx constants */

    /* FPU state */
    unsigned int fpstt; /* top of stack index */
    unsigned int fpus;
    unsigned int fpuc;
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
    union {
#ifdef USE_X86LDOUBLE
        CPU86_LDouble d __attribute__((aligned(16)));
#else
        CPU86_LDouble d;
#endif
        MMXReg mmx;
    } fpregs[8];

    /* emulator internal variables */
    CPU86_LDouble ft0;
    union {
	float f;
        double d;
	int i32;
        int64_t i64;
    } fp_convert;
    
    /* segments */
    SegmentCache segs[6]; /* selector values */
    SegmentCache ldt;
    SegmentCache tr;
    SegmentCache gdt; /* only base and limit are used */
    SegmentCache idt; /* only base and limit are used */

    uint32_t mxcsr;
    XMMReg xmm_regs[CPU_NB_REGS];
    XMMReg xmm_t0;
    MMXReg mmx_t0;

    /* sysenter registers */
    uint32_t sysenter_cs;
    uint32_t sysenter_esp;
    uint32_t sysenter_eip;
#ifdef TARGET_X86_64
    target_ulong efer;
    target_ulong star;
    target_ulong lstar;
    target_ulong cstar;
    target_ulong fmask;
    target_ulong kernelgsbase;
#endif

    /* temporary data for USE_CODE_COPY mode */
#ifdef USE_CODE_COPY
    uint32_t tmp0;
    uint32_t saved_esp;
    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
#endif
    
    /* exception/interrupt handling */
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int exception_is_int;
    target_ulong exception_next_eip;
    struct TranslationBlock *current_tb; /* currently executing TB */
    target_ulong cr[5]; /* NOTE: cr1 is unused */
    target_ulong dr[8]; /* debug registers */
    int interrupt_request; 
    int user_mode_only; /* user mode only simulation */

    uint32_t a20_mask;

    /* soft mmu support */
    /* in order to avoid passing too many arguments to the memory
       write helpers, we store some rarely used information in the CPU
       context) */
    unsigned long mem_write_pc; /* host pc at which the memory was
                                   written */
    target_ulong mem_write_vaddr; /* target virtual addr at which the
                                     memory was written */
    /* 0 = kernel, 1 = user */
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
    
    /* from this point: preserved by CPU reset */
    /* ice debug support */
    target_ulong breakpoints[MAX_BREAKPOINTS];
    int nb_breakpoints;
    int singlestep_enabled;

    /* processor features (e.g. for CPUID insn) */
    uint32_t cpuid_vendor1;
    uint32_t cpuid_vendor2;
    uint32_t cpuid_vendor3;
    uint32_t cpuid_version;
    uint32_t cpuid_features;

    /* in order to simplify APIC support, we leave this pointer to the
       user */
    struct APICState *apic_state;
    /* user data */
    void *opaque;
} CPUX86State;

CPUX86State *cpu_x86_init(void);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void cpu_set_ferr(CPUX86State *s);

/* this function must always be used to load data in the segment
   cache: it synchronizes the hflags with the segment cache values */
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
                                          int seg_reg, unsigned int selector,
                                          uint32_t base, unsigned int limit, 
                                          unsigned int flags)
{
    SegmentCache *sc;
    unsigned int new_hflags;
    
    sc = &env->segs[seg_reg];
    sc->selector = selector;
    sc->base = base;
    sc->limit = limit;
    sc->flags = flags;

    /* update the hidden flags */
    {
        if (seg_reg == R_CS) {
#ifdef TARGET_X86_64
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
                /* long mode */
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
                env->hflags &= ~(HF_ADDSEG_MASK);
            } else 
#endif
            {
                /* legacy / compatibility case */
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
                    new_hflags;
            }
        }
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
        if (env->hflags & HF_CS64_MASK) {
            /* zero base assumed for DS, ES and SS in long mode */
        } else if (!(env->cr[0] & CR0_PE_MASK) || 
                   (env->eflags & VM_MASK) ||
                   !(env->hflags & HF_CS32_MASK)) {
            /* XXX: try to avoid this test. The problem comes from the
               fact that is real mode or vm86 mode we only modify the
               'base' and 'selector' fields of the segment cache to go
               faster. A solution may be to force addseg to one in
               translate-i386.c. */
            new_hflags |= HF_ADDSEG_MASK;
        } else {
            new_hflags |= ((env->segs[R_DS].base | 
                            env->segs[R_ES].base |
                            env->segs[R_SS].base) != 0) << 
                HF_ADDSEG_SHIFT;
        }
        env->hflags = (env->hflags & 
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
    }
}

/* wrapper, just in case memory mappings must be changed */
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
{
#if HF_CPL_MASK == 3
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
#else
#error HF_CPL_MASK is hardcoded
#endif
}

/* used for debug or cpu save/restore */
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);

/* the following helpers are only usable in user mode simulation as
   they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
struct siginfo;
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc);
void cpu_x86_set_a20(CPUX86State *env, int a20_state);

uint64_t cpu_get_tsc(CPUX86State *env);

void cpu_set_apic_base(CPUX86State *env, uint64_t val);
uint64_t cpu_get_apic_base(CPUX86State *env);
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
#ifndef NO_CPU_IO_DEFS
uint8_t cpu_get_apic_tpr(CPUX86State *env);
#endif

/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);

/* used to debug */
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

#endif /* CPU_I386_H */
Commit	Line	Data
2c0262af FB	1	/*
	2	* i386 virtual CPU header
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_I386_H
	21	#define CPU_I386_H
	22
14ce26e7 FB	23	#include "config.h"
	24
	25	#ifdef TARGET_X86_64
	26	#define TARGET_LONG_BITS 64
	27	#else
3cf1e035	28	#define TARGET_LONG_BITS 32
14ce26e7	29	#endif
3cf1e035	30
d720b93d FB	31	/* target supports implicit self modifying code */
	32	#define TARGET_HAS_SMC
	33	/* support for self modifying code even if the modified instruction is
	34	close to the modifying instruction */
	35	#define TARGET_HAS_PRECISE_SMC
	36
2c0262af FB	37	#include "cpu-defs.h"
2c0262af FB	38
58fe2f10 FB	39	#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
	40	#define USE_CODE_COPY
	41	#endif
	42
2c0262af FB	43	#define R_EAX 0
	44	#define R_ECX 1
	45	#define R_EDX 2
	46	#define R_EBX 3
	47	#define R_ESP 4
	48	#define R_EBP 5
	49	#define R_ESI 6
	50	#define R_EDI 7
	51
	52	#define R_AL 0
	53	#define R_CL 1
	54	#define R_DL 2
	55	#define R_BL 3
	56	#define R_AH 4
	57	#define R_CH 5
	58	#define R_DH 6
	59	#define R_BH 7
	60
	61	#define R_ES 0
	62	#define R_CS 1
	63	#define R_SS 2
	64	#define R_DS 3
	65	#define R_FS 4
	66	#define R_GS 5
	67
	68	/* segment descriptor fields */
	69	#define DESC_G_MASK (1 << 23)
	70	#define DESC_B_SHIFT 22
	71	#define DESC_B_MASK (1 << DESC_B_SHIFT)
14ce26e7 FB	72	#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
14ce26e7 FB	73	#define DESC_L_MASK (1 << DESC_L_SHIFT)
2c0262af FB	74	#define DESC_AVL_MASK (1 << 20)
	75	#define DESC_P_MASK (1 << 15)
	76	#define DESC_DPL_SHIFT 13
	77	#define DESC_S_MASK (1 << 12)
	78	#define DESC_TYPE_SHIFT 8
	79	#define DESC_A_MASK (1 << 8)
	80
e670b89e FB	81	#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
	82	#define DESC_C_MASK (1 << 10) /* code: conforming */
	83	#define DESC_R_MASK (1 << 9) /* code: readable */
2c0262af	84
e670b89e FB	85	#define DESC_E_MASK (1 << 10) /* data: expansion direction */
	86	#define DESC_W_MASK (1 << 9) /* data: writable */
	87
	88	#define DESC_TSS_BUSY_MASK (1 << 9)
2c0262af FB	89
	90	/* eflags masks */
	91	#define CC_C 0x0001
	92	#define CC_P 0x0004
	93	#define CC_A 0x0010
	94	#define CC_Z 0x0040
	95	#define CC_S 0x0080
	96	#define CC_O 0x0800
	97
	98	#define TF_SHIFT 8
	99	#define IOPL_SHIFT 12
	100	#define VM_SHIFT 17
	101
	102	#define TF_MASK 0x00000100
	103	#define IF_MASK 0x00000200
	104	#define DF_MASK 0x00000400
	105	#define IOPL_MASK 0x00003000
	106	#define NT_MASK 0x00004000
	107	#define RF_MASK 0x00010000
	108	#define VM_MASK 0x00020000
	109	#define AC_MASK 0x00040000
	110	#define VIF_MASK 0x00080000
	111	#define VIP_MASK 0x00100000
	112	#define ID_MASK 0x00200000
	113
	114	/* hidden flags - used internally by qemu to represent additionnal cpu
	115	states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
	116	using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
	117	with eflags. */
	118	/* current cpl */
	119	#define HF_CPL_SHIFT 0
	120	/* true if soft mmu is being used */
	121	#define HF_SOFTMMU_SHIFT 2
	122	/* true if hardware interrupts must be disabled for next instruction */
	123	#define HF_INHIBIT_IRQ_SHIFT 3
	124	/* 16 or 32 segments */
	125	#define HF_CS32_SHIFT 4
	126	#define HF_SS32_SHIFT 5
dc196a57	127	/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
2c0262af	128	#define HF_ADDSEG_SHIFT 6
65262d57 FB	129	/* copy of CR0.PE (protected mode) */
	130	#define HF_PE_SHIFT 7
	131	#define HF_TF_SHIFT 8 /* must be same as eflags */
7eee2a50 FB	132	#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
	133	#define HF_EM_SHIFT 10
	134	#define HF_TS_SHIFT 11
65262d57	135	#define HF_IOPL_SHIFT 12 /* must be same as eflags */
14ce26e7 FB	136	#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
14ce26e7 FB	137	#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
664e0f19	138	#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
65262d57	139	#define HF_VM_SHIFT 17 /* must be same as eflags */
2c0262af FB	140
	141	#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
	142	#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
	143	#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
	144	#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
	145	#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
	146	#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
65262d57	147	#define HF_PE_MASK (1 << HF_PE_SHIFT)
58fe2f10	148	#define HF_TF_MASK (1 << HF_TF_SHIFT)
7eee2a50 FB	149	#define HF_MP_MASK (1 << HF_MP_SHIFT)
	150	#define HF_EM_MASK (1 << HF_EM_SHIFT)
	151	#define HF_TS_MASK (1 << HF_TS_SHIFT)
14ce26e7 FB	152	#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
14ce26e7 FB	153	#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
664e0f19	154	#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
2c0262af FB	155
2c0262af FB	156	#define CR0_PE_MASK (1 << 0)
7eee2a50 FB	157	#define CR0_MP_MASK (1 << 1)
7eee2a50 FB	158	#define CR0_EM_MASK (1 << 2)
2c0262af	159	#define CR0_TS_MASK (1 << 3)
2ee73ac3	160	#define CR0_ET_MASK (1 << 4)
7eee2a50	161	#define CR0_NE_MASK (1 << 5)
2c0262af FB	162	#define CR0_WP_MASK (1 << 16)
	163	#define CR0_AM_MASK (1 << 18)
	164	#define CR0_PG_MASK (1 << 31)
	165
	166	#define CR4_VME_MASK (1 << 0)
	167	#define CR4_PVI_MASK (1 << 1)
	168	#define CR4_TSD_MASK (1 << 2)
	169	#define CR4_DE_MASK (1 << 3)
	170	#define CR4_PSE_MASK (1 << 4)
64a595f2 FB	171	#define CR4_PAE_MASK (1 << 5)
64a595f2 FB	172	#define CR4_PGE_MASK (1 << 7)
14ce26e7 FB	173	#define CR4_PCE_MASK (1 << 8)
	174	#define CR4_OSFXSR_MASK (1 << 9)
	175	#define CR4_OSXMMEXCPT_MASK (1 << 10)
2c0262af FB	176
	177	#define PG_PRESENT_BIT 0
	178	#define PG_RW_BIT 1
	179	#define PG_USER_BIT 2
	180	#define PG_PWT_BIT 3
	181	#define PG_PCD_BIT 4
	182	#define PG_ACCESSED_BIT 5
	183	#define PG_DIRTY_BIT 6
	184	#define PG_PSE_BIT 7
	185	#define PG_GLOBAL_BIT 8
	186
	187	#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
	188	#define PG_RW_MASK (1 << PG_RW_BIT)
	189	#define PG_USER_MASK (1 << PG_USER_BIT)
	190	#define PG_PWT_MASK (1 << PG_PWT_BIT)
	191	#define PG_PCD_MASK (1 << PG_PCD_BIT)
	192	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	193	#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
	194	#define PG_PSE_MASK (1 << PG_PSE_BIT)
	195	#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
	196
	197	#define PG_ERROR_W_BIT 1
	198
	199	#define PG_ERROR_P_MASK 0x01
	200	#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
	201	#define PG_ERROR_U_MASK 0x04
	202	#define PG_ERROR_RSVD_MASK 0x08
	203
	204	#define MSR_IA32_APICBASE 0x1b
	205	#define MSR_IA32_APICBASE_BSP (1<<8)
	206	#define MSR_IA32_APICBASE_ENABLE (1<<11)
	207	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
	208
	209	#define MSR_IA32_SYSENTER_CS 0x174
	210	#define MSR_IA32_SYSENTER_ESP 0x175
	211	#define MSR_IA32_SYSENTER_EIP 0x176
	212
14ce26e7 FB	213	#define MSR_EFER 0xc0000080
	214
	215	#define MSR_EFER_SCE (1 << 0)
	216	#define MSR_EFER_LME (1 << 8)
	217	#define MSR_EFER_LMA (1 << 10)
	218	#define MSR_EFER_NXE (1 << 11)
	219	#define MSR_EFER_FFXSR (1 << 14)
	220
	221	#define MSR_STAR 0xc0000081
	222	#define MSR_LSTAR 0xc0000082
	223	#define MSR_CSTAR 0xc0000083
	224	#define MSR_FMASK 0xc0000084
	225	#define MSR_FSBASE 0xc0000100
	226	#define MSR_GSBASE 0xc0000101
	227	#define MSR_KERNELGSBASE 0xc0000102
	228
	229	/* cpuid_features bits */
	230	#define CPUID_FP87 (1 << 0)
	231	#define CPUID_VME (1 << 1)
	232	#define CPUID_DE (1 << 2)
	233	#define CPUID_PSE (1 << 3)
	234	#define CPUID_TSC (1 << 4)
	235	#define CPUID_MSR (1 << 5)
	236	#define CPUID_PAE (1 << 6)
	237	#define CPUID_MCE (1 << 7)
	238	#define CPUID_CX8 (1 << 8)
	239	#define CPUID_APIC (1 << 9)
	240	#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
	241	#define CPUID_MTRR (1 << 12)
	242	#define CPUID_PGE (1 << 13)
	243	#define CPUID_MCA (1 << 14)
	244	#define CPUID_CMOV (1 << 15)
	245	/* ... */
	246	#define CPUID_MMX (1 << 23)
	247	#define CPUID_FXSR (1 << 24)
	248	#define CPUID_SSE (1 << 25)
	249	#define CPUID_SSE2 (1 << 26)
	250
2c0262af FB	251	#define EXCP00_DIVZ 0
	252	#define EXCP01_SSTP 1
	253	#define EXCP02_NMI 2
	254	#define EXCP03_INT3 3
	255	#define EXCP04_INTO 4
	256	#define EXCP05_BOUND 5
	257	#define EXCP06_ILLOP 6
	258	#define EXCP07_PREX 7
	259	#define EXCP08_DBLE 8
	260	#define EXCP09_XERR 9
	261	#define EXCP0A_TSS 10
	262	#define EXCP0B_NOSEG 11
	263	#define EXCP0C_STACK 12
	264	#define EXCP0D_GPF 13
	265	#define EXCP0E_PAGE 14
	266	#define EXCP10_COPR 16
	267	#define EXCP11_ALGN 17
	268	#define EXCP12_MCHK 18
	269
	270	enum {
	271	CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
	272	CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
d36cd60e FB	273
	274	CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
	275	CC_OP_MULW,
	276	CC_OP_MULL,
14ce26e7	277	CC_OP_MULQ,
2c0262af FB	278
	279	CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	280	CC_OP_ADDW,
	281	CC_OP_ADDL,
14ce26e7	282	CC_OP_ADDQ,
2c0262af FB	283
	284	CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	285	CC_OP_ADCW,
	286	CC_OP_ADCL,
14ce26e7	287	CC_OP_ADCQ,
2c0262af FB	288
	289	CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	290	CC_OP_SUBW,
	291	CC_OP_SUBL,
14ce26e7	292	CC_OP_SUBQ,
2c0262af FB	293
	294	CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
	295	CC_OP_SBBW,
	296	CC_OP_SBBL,
14ce26e7	297	CC_OP_SBBQ,
2c0262af FB	298
	299	CC_OP_LOGICB, /* modify all flags, CC_DST = res */
	300	CC_OP_LOGICW,
	301	CC_OP_LOGICL,
14ce26e7	302	CC_OP_LOGICQ,
2c0262af FB	303
	304	CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	305	CC_OP_INCW,
	306	CC_OP_INCL,
14ce26e7	307	CC_OP_INCQ,
2c0262af FB	308
	309	CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
	310	CC_OP_DECW,
	311	CC_OP_DECL,
14ce26e7	312	CC_OP_DECQ,
2c0262af	313
6b652794	314	CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
2c0262af FB	315	CC_OP_SHLW,
2c0262af FB	316	CC_OP_SHLL,
14ce26e7	317	CC_OP_SHLQ,
2c0262af FB	318
	319	CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
	320	CC_OP_SARW,
	321	CC_OP_SARL,
14ce26e7	322	CC_OP_SARQ,
2c0262af FB	323
	324	CC_OP_NB,
	325	};
	326
7d3505c5	327	#if (defined(__i386__) \|\| defined(__x86_64__)) && !defined(_BSD)
2c0262af FB	328	#define USE_X86LDOUBLE
	329	#endif
	330
	331	#ifdef USE_X86LDOUBLE
	332	typedef long double CPU86_LDouble;
	333	#else
	334	typedef double CPU86_LDouble;
	335	#endif
	336
	337	typedef struct SegmentCache {
	338	uint32_t selector;
14ce26e7	339	target_ulong base;
2c0262af FB	340	uint32_t limit;
	341	uint32_t flags;
	342	} SegmentCache;
	343
826461bb	344	typedef union {
664e0f19 FB	345	uint8_t _b[16];
	346	uint16_t _w[8];
	347	uint32_t _l[4];
	348	uint64_t _q[2];
	349	float _s[4];
	350	double _d[2];
14ce26e7 FB	351	} XMMReg;
14ce26e7 FB	352
826461bb FB	353	typedef union {
	354	uint8_t _b[8];
	355	uint16_t _w[2];
	356	uint32_t _l[1];
	357	uint64_t q;
	358	} MMXReg;
	359
	360	#ifdef WORDS_BIGENDIAN
	361	#define XMM_B(n) _b[15 - (n)]
	362	#define XMM_W(n) _w[7 - (n)]
	363	#define XMM_L(n) _l[3 - (n)]
664e0f19	364	#define XMM_S(n) _s[3 - (n)]
826461bb	365	#define XMM_Q(n) _q[1 - (n)]
664e0f19	366	#define XMM_D(n) _d[1 - (n)]
826461bb FB	367
	368	#define MMX_B(n) _b[7 - (n)]
	369	#define MMX_W(n) _w[3 - (n)]
	370	#define MMX_L(n) _l[1 - (n)]
	371	#else
	372	#define XMM_B(n) _b[n]
	373	#define XMM_W(n) _w[n]
	374	#define XMM_L(n) _l[n]
664e0f19	375	#define XMM_S(n) _s[n]
826461bb	376	#define XMM_Q(n) _q[n]
664e0f19	377	#define XMM_D(n) _d[n]
826461bb FB	378
	379	#define MMX_B(n) _b[n]
	380	#define MMX_W(n) _w[n]
	381	#define MMX_L(n) _l[n]
	382	#endif
664e0f19	383	#define MMX_Q(n) q
826461bb	384
14ce26e7 FB	385	#ifdef TARGET_X86_64
	386	#define CPU_NB_REGS 16
	387	#else
	388	#define CPU_NB_REGS 8
	389	#endif
	390
2c0262af	391	typedef struct CPUX86State {
14ce26e7 FB	392	#if TARGET_LONG_BITS > HOST_LONG_BITS
	393	/* temporaries if we cannot store them in host registers */
	394	target_ulong t0, t1, t2;
	395	#endif
	396
2c0262af	397	/* standard registers */
14ce26e7 FB	398	target_ulong regs[CPU_NB_REGS];
	399	target_ulong eip;
	400	target_ulong eflags; /* eflags register. During CPU emulation, CC
2c0262af FB	401	flags and DF are set to zero because they are
	402	stored elsewhere */
	403
	404	/* emulator internal eflags handling */
14ce26e7 FB	405	target_ulong cc_src;
14ce26e7 FB	406	target_ulong cc_dst;
2c0262af FB	407	uint32_t cc_op;
	408	int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
	409	uint32_t hflags; /* hidden flags, see HF_xxx constants */
	410
	411	/* FPU state */
	412	unsigned int fpstt; /* top of stack index */
	413	unsigned int fpus;
	414	unsigned int fpuc;
	415	uint8_t fptags[8]; /* 0 = valid, 1 = empty */
664e0f19 FB	416	union {
	417	#ifdef USE_X86LDOUBLE
	418	CPU86_LDouble d __attribute__((aligned(16)));
	419	#else
	420	CPU86_LDouble d;
	421	#endif
	422	MMXReg mmx;
	423	} fpregs[8];
2c0262af FB	424
	425	/* emulator internal variables */
	426	CPU86_LDouble ft0;
	427	union {
	428	float f;
	429	double d;
	430	int i32;
	431	int64_t i64;
	432	} fp_convert;
	433
	434	/* segments */
	435	SegmentCache segs[6]; /* selector values */
	436	SegmentCache ldt;
	437	SegmentCache tr;
	438	SegmentCache gdt; /* only base and limit are used */
	439	SegmentCache idt; /* only base and limit are used */
664e0f19 FB	440
664e0f19 FB	441	uint32_t mxcsr;
14ce26e7 FB	442	XMMReg xmm_regs[CPU_NB_REGS];
14ce26e7 FB	443	XMMReg xmm_t0;
664e0f19	444	MMXReg mmx_t0;
14ce26e7	445
2c0262af FB	446	/* sysenter registers */
	447	uint32_t sysenter_cs;
	448	uint32_t sysenter_esp;
	449	uint32_t sysenter_eip;
14ce26e7 FB	450	#ifdef TARGET_X86_64
	451	target_ulong efer;
	452	target_ulong star;
	453	target_ulong lstar;
	454	target_ulong cstar;
	455	target_ulong fmask;
	456	target_ulong kernelgsbase;
	457	#endif
58fe2f10 FB	458
58fe2f10 FB	459	/* temporary data for USE_CODE_COPY mode */
7eee2a50	460	#ifdef USE_CODE_COPY
58fe2f10 FB	461	uint32_t tmp0;
58fe2f10 FB	462	uint32_t saved_esp;
7eee2a50 FB	463	int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
7eee2a50 FB	464	#endif
2c0262af FB	465
	466	/* exception/interrupt handling */
	467	jmp_buf jmp_env;
	468	int exception_index;
	469	int error_code;
	470	int exception_is_int;
826461bb	471	target_ulong exception_next_eip;
2c0262af	472	struct TranslationBlock current_tb; / currently executing TB */
14ce26e7 FB	473	target_ulong cr[5]; /* NOTE: cr1 is unused */
14ce26e7 FB	474	target_ulong dr[8]; /* debug registers */
2c0262af FB	475	int interrupt_request;
	476	int user_mode_only; /* user mode only simulation */
	477
64a595f2	478	uint32_t a20_mask;
d720b93d FB	479
	480	/* soft mmu support */
	481	/* in order to avoid passing too many arguments to the memory
	482	write helpers, we store some rarely used information in the CPU
	483	context) */
	484	unsigned long mem_write_pc; /* host pc at which the memory was
	485	written */
14ce26e7 FB	486	target_ulong mem_write_vaddr; /* target virtual addr at which the
14ce26e7 FB	487	memory was written */
2c0262af FB	488	/* 0 = kernel, 1 = user */
	489	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
	490	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
	491
ffddfee3	492	/* from this point: preserved by CPU reset */
2c0262af	493	/* ice debug support */
14ce26e7	494	target_ulong breakpoints[MAX_BREAKPOINTS];
2c0262af FB	495	int nb_breakpoints;
	496	int singlestep_enabled;
	497
14ce26e7 FB	498	/* processor features (e.g. for CPUID insn) */
	499	uint32_t cpuid_vendor1;
	500	uint32_t cpuid_vendor2;
	501	uint32_t cpuid_vendor3;
	502	uint32_t cpuid_version;
	503	uint32_t cpuid_features;
	504
	505	/* in order to simplify APIC support, we leave this pointer to the
	506	user */
	507	struct APICState *apic_state;
2c0262af FB	508	/* user data */
	509	void *opaque;
	510	} CPUX86State;
	511
2c0262af FB	512	CPUX86State *cpu_x86_init(void);
	513	int cpu_x86_exec(CPUX86State *s);
	514	void cpu_x86_close(CPUX86State *s);
d720b93d	515	int cpu_get_pic_interrupt(CPUX86State *s);
2ee73ac3 FB	516	/* MSDOS compatibility mode FPU exception support */
2ee73ac3 FB	517	void cpu_set_ferr(CPUX86State *s);
2c0262af FB	518
	519	/* this function must always be used to load data in the segment
	520	cache: it synchronizes the hflags with the segment cache values */
	521	static inline void cpu_x86_load_seg_cache(CPUX86State *env,
	522	int seg_reg, unsigned int selector,
14ce26e7	523	uint32_t base, unsigned int limit,
2c0262af FB	524	unsigned int flags)
	525	{
	526	SegmentCache *sc;
	527	unsigned int new_hflags;
	528
	529	sc = &env->segs[seg_reg];
	530	sc->selector = selector;
	531	sc->base = base;
	532	sc->limit = limit;
	533	sc->flags = flags;
	534
	535	/* update the hidden flags */
14ce26e7 FB	536	{
	537	if (seg_reg == R_CS) {
	538	#ifdef TARGET_X86_64
	539	if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
	540	/* long mode */
	541	env->hflags \|= HF_CS32_MASK \| HF_SS32_MASK \| HF_CS64_MASK;
	542	env->hflags &= ~(HF_ADDSEG_MASK);
	543	} else
	544	#endif
	545	{
	546	/* legacy / compatibility case */
	547	new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
	548	>> (DESC_B_SHIFT - HF_CS32_SHIFT);
	549	env->hflags = (env->hflags & ~(HF_CS32_MASK \| HF_CS64_MASK)) \|
	550	new_hflags;
	551	}
	552	}
	553	new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
	554	>> (DESC_B_SHIFT - HF_SS32_SHIFT);
	555	if (env->hflags & HF_CS64_MASK) {
	556	/* zero base assumed for DS, ES and SS in long mode */
	557	} else if (!(env->cr[0] & CR0_PE_MASK) \|\|
735a8fd3 FB	558	(env->eflags & VM_MASK) \|\|
735a8fd3 FB	559	!(env->hflags & HF_CS32_MASK)) {
14ce26e7 FB	560	/* XXX: try to avoid this test. The problem comes from the
	561	fact that is real mode or vm86 mode we only modify the
	562	'base' and 'selector' fields of the segment cache to go
	563	faster. A solution may be to force addseg to one in
	564	translate-i386.c. */
	565	new_hflags \|= HF_ADDSEG_MASK;
	566	} else {
735a8fd3 FB	567	new_hflags \|= ((env->segs[R_DS].base \|
	568	env->segs[R_ES].base \|
	569	env->segs[R_SS].base) != 0) <<
14ce26e7 FB	570	HF_ADDSEG_SHIFT;
	571	}
	572	env->hflags = (env->hflags &
	573	~(HF_SS32_MASK \| HF_ADDSEG_MASK)) \| new_hflags;
2c0262af	574	}
2c0262af FB	575	}
	576
	577	/* wrapper, just in case memory mappings must be changed */
	578	static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
	579	{
	580	#if HF_CPL_MASK == 3
	581	s->hflags = (s->hflags & ~HF_CPL_MASK) \| cpl;
	582	#else
	583	#error HF_CPL_MASK is hardcoded
	584	#endif
	585	}
	586
1f1af9fd FB	587	/* used for debug or cpu save/restore */
	588	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f);
	589	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
	590
2c0262af FB	591	/* the following helpers are only usable in user mode simulation as
	592	they can trigger unexpected exceptions */
	593	void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
	594	void cpu_x86_fsave(CPUX86State s, uint8_t ptr, int data32);
	595	void cpu_x86_frstor(CPUX86State s, uint8_t ptr, int data32);
	596
	597	/* you can call this signal handler from your SIGBUS and SIGSEGV
	598	signal handlers to inform the virtual CPU of exceptions. non zero
	599	is returned if the signal was handled by the virtual CPU. */
	600	struct siginfo;
	601	int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
	602	void *puc);
461c0471	603	void cpu_x86_set_a20(CPUX86State *env, int a20_state);
2c0262af	604
28ab0e2e FB	605	uint64_t cpu_get_tsc(CPUX86State *env);
28ab0e2e FB	606
14ce26e7 FB	607	void cpu_set_apic_base(CPUX86State *env, uint64_t val);
14ce26e7 FB	608	uint64_t cpu_get_apic_base(CPUX86State *env);
9230e66e FB	609	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
	610	#ifndef NO_CPU_IO_DEFS
	611	uint8_t cpu_get_apic_tpr(CPUX86State *env);
	612	#endif
14ce26e7	613
64a595f2 FB	614	/* will be suppressed */
	615	void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
	616
2c0262af FB	617	/* used to debug */
	618	#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
	619	#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
2c0262af FB	620
	621	#define TARGET_PAGE_BITS 12
	622	#include "cpu-all.h"
	623
	624	#endif /* CPU_I386_H */