projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 2c0262af FB |
1 | /* |
| 2 | * i386 virtual CPU header | |
| 3 | * | |
| 4 | * Copyright (c) 2003 Fabrice Bellard | |
| 5 | * | |
| 6 | * This library is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU Lesser General Public | |
| 8 | * License as published by the Free Software Foundation; either | |
| 9 | * version 2 of the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This library is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | * Lesser General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU Lesser General Public | |
| 17 | * License along with this library; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 19 | */ | |
| 20 | #ifndef CPU_I386_H | |
| 21 | #define CPU_I386_H | |
| 22 | ||
| 14ce26e7 FB |
23 | #include "config.h" |
| 24 | ||
| 25 | #ifdef TARGET_X86_64 | |
| 26 | #define TARGET_LONG_BITS 64 | |
| 27 | #else | |
| 3cf1e035 | 28 | #define TARGET_LONG_BITS 32 |
| 14ce26e7 | 29 | #endif |
| 3cf1e035 | 30 | |
| d720b93d FB |
31 | /* target supports implicit self modifying code */ |
| 32 | #define TARGET_HAS_SMC | |
| 33 | /* support for self modifying code even if the modified instruction is | |
| 34 | close to the modifying instruction */ | |
| 35 | #define TARGET_HAS_PRECISE_SMC | |
| 36 | ||
| 1fddef4b FB |
37 | #define TARGET_HAS_ICE 1 |
| 38 | ||
| 9042c0e2 TS |
39 | #ifdef TARGET_X86_64 |
| 40 | #define ELF_MACHINE EM_X86_64 | |
| 41 | #else | |
| 42 | #define ELF_MACHINE EM_386 | |
| 43 | #endif | |
| 44 | ||
| 2c0262af FB |
45 | #include "cpu-defs.h" |
| 46 | ||
| 7a0e1f41 FB |
47 | #include "softfloat.h" |
| 48 | ||
| 26a16623 | 49 | #if defined(__i386__) && !defined(CONFIG_SOFTMMU) && !defined(__APPLE__) |
| 58fe2f10 FB |
50 | #define USE_CODE_COPY |
| 51 | #endif | |
| 52 | ||
| 2c0262af FB |
53 | #define R_EAX 0 |
| 54 | #define R_ECX 1 | |
| 55 | #define R_EDX 2 | |
| 56 | #define R_EBX 3 | |
| 57 | #define R_ESP 4 | |
| 58 | #define R_EBP 5 | |
| 59 | #define R_ESI 6 | |
| 60 | #define R_EDI 7 | |
| 61 | ||
| 62 | #define R_AL 0 | |
| 63 | #define R_CL 1 | |
| 64 | #define R_DL 2 | |
| 65 | #define R_BL 3 | |
| 66 | #define R_AH 4 | |
| 67 | #define R_CH 5 | |
| 68 | #define R_DH 6 | |
| 69 | #define R_BH 7 | |
| 70 | ||
| 71 | #define R_ES 0 | |
| 72 | #define R_CS 1 | |
| 73 | #define R_SS 2 | |
| 74 | #define R_DS 3 | |
| 75 | #define R_FS 4 | |
| 76 | #define R_GS 5 | |
| 77 | ||
| 78 | /* segment descriptor fields */ | |
| 79 | #define DESC_G_MASK (1 << 23) | |
| 80 | #define DESC_B_SHIFT 22 | |
| 81 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
| 14ce26e7 FB |
82 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
| 83 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
| 2c0262af FB |
84 | #define DESC_AVL_MASK (1 << 20) |
| 85 | #define DESC_P_MASK (1 << 15) | |
| 86 | #define DESC_DPL_SHIFT 13 | |
| 87 | #define DESC_S_MASK (1 << 12) | |
| 88 | #define DESC_TYPE_SHIFT 8 | |
| 89 | #define DESC_A_MASK (1 << 8) | |
| 90 | ||
| e670b89e FB |
91 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
| 92 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
| 93 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
| 2c0262af | 94 | |
| e670b89e FB |
95 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
| 96 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
| 97 | ||
| 98 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
| 2c0262af FB |
99 | |
| 100 | /* eflags masks */ | |
| 101 | #define CC_C 0x0001 | |
| 102 | #define CC_P 0x0004 | |
| 103 | #define CC_A 0x0010 | |
| 104 | #define CC_Z 0x0040 | |
| 105 | #define CC_S 0x0080 | |
| 106 | #define CC_O 0x0800 | |
| 107 | ||
| 108 | #define TF_SHIFT 8 | |
| 109 | #define IOPL_SHIFT 12 | |
| 110 | #define VM_SHIFT 17 | |
| 111 | ||
| 112 | #define TF_MASK 0x00000100 | |
| 113 | #define IF_MASK 0x00000200 | |
| 114 | #define DF_MASK 0x00000400 | |
| 115 | #define IOPL_MASK 0x00003000 | |
| 116 | #define NT_MASK 0x00004000 | |
| 117 | #define RF_MASK 0x00010000 | |
| 118 | #define VM_MASK 0x00020000 | |
| 119 | #define AC_MASK 0x00040000 | |
| 120 | #define VIF_MASK 0x00080000 | |
| 121 | #define VIP_MASK 0x00100000 | |
| 122 | #define ID_MASK 0x00200000 | |
| 123 | ||
| 124 | /* hidden flags - used internally by qemu to represent additionnal cpu | |
| d2ac63e0 | 125 | states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid |
| 2c0262af FB |
126 | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring |
| 127 | with eflags. */ | |
| 128 | /* current cpl */ | |
| 129 | #define HF_CPL_SHIFT 0 | |
| 130 | /* true if soft mmu is being used */ | |
| 131 | #define HF_SOFTMMU_SHIFT 2 | |
| 132 | /* true if hardware interrupts must be disabled for next instruction */ | |
| 133 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
| 134 | /* 16 or 32 segments */ | |
| 135 | #define HF_CS32_SHIFT 4 | |
| 136 | #define HF_SS32_SHIFT 5 | |
| dc196a57 | 137 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
| 2c0262af | 138 | #define HF_ADDSEG_SHIFT 6 |
| 65262d57 FB |
139 | /* copy of CR0.PE (protected mode) */ |
| 140 | #define HF_PE_SHIFT 7 | |
| 141 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
| 7eee2a50 FB |
142 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
| 143 | #define HF_EM_SHIFT 10 | |
| 144 | #define HF_TS_SHIFT 11 | |
| 65262d57 | 145 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
| 14ce26e7 FB |
146 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
| 147 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
| 664e0f19 | 148 | #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
| 65262d57 | 149 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
| d2ac63e0 | 150 | #define HF_HALTED_SHIFT 18 /* CPU halted */ |
| 3b21e03e | 151 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
| 2c0262af FB |
152 | |
| 153 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
| 154 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) | |
| 155 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) | |
| 156 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
| 157 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
| 158 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
| 65262d57 | 159 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
| 58fe2f10 | 160 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
| 7eee2a50 FB |
161 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
| 162 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
| 163 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
| 14ce26e7 FB |
164 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
| 165 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
| 664e0f19 | 166 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
| d2ac63e0 | 167 | #define HF_HALTED_MASK (1 << HF_HALTED_SHIFT) |
| 3b21e03e | 168 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
| 2c0262af FB |
169 | |
| 170 | #define CR0_PE_MASK (1 << 0) | |
| 7eee2a50 FB |
171 | #define CR0_MP_MASK (1 << 1) |
| 172 | #define CR0_EM_MASK (1 << 2) | |
| 2c0262af | 173 | #define CR0_TS_MASK (1 << 3) |
| 2ee73ac3 | 174 | #define CR0_ET_MASK (1 << 4) |
| 7eee2a50 | 175 | #define CR0_NE_MASK (1 << 5) |
| 2c0262af FB |
176 | #define CR0_WP_MASK (1 << 16) |
| 177 | #define CR0_AM_MASK (1 << 18) | |
| 178 | #define CR0_PG_MASK (1 << 31) | |
| 179 | ||
| 180 | #define CR4_VME_MASK (1 << 0) | |
| 181 | #define CR4_PVI_MASK (1 << 1) | |
| 182 | #define CR4_TSD_MASK (1 << 2) | |
| 183 | #define CR4_DE_MASK (1 << 3) | |
| 184 | #define CR4_PSE_MASK (1 << 4) | |
| 64a595f2 FB |
185 | #define CR4_PAE_MASK (1 << 5) |
| 186 | #define CR4_PGE_MASK (1 << 7) | |
| 14ce26e7 FB |
187 | #define CR4_PCE_MASK (1 << 8) |
| 188 | #define CR4_OSFXSR_MASK (1 << 9) | |
| 189 | #define CR4_OSXMMEXCPT_MASK (1 << 10) | |
| 2c0262af FB |
190 | |
| 191 | #define PG_PRESENT_BIT 0 | |
| 192 | #define PG_RW_BIT 1 | |
| 193 | #define PG_USER_BIT 2 | |
| 194 | #define PG_PWT_BIT 3 | |
| 195 | #define PG_PCD_BIT 4 | |
| 196 | #define PG_ACCESSED_BIT 5 | |
| 197 | #define PG_DIRTY_BIT 6 | |
| 198 | #define PG_PSE_BIT 7 | |
| 199 | #define PG_GLOBAL_BIT 8 | |
| 5cf38396 | 200 | #define PG_NX_BIT 63 |
| 2c0262af FB |
201 | |
| 202 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
| 203 | #define PG_RW_MASK (1 << PG_RW_BIT) | |
| 204 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
| 205 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
| 206 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
| 207 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
| 208 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) | |
| 209 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
| 210 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
| 5cf38396 | 211 | #define PG_NX_MASK (1LL << PG_NX_BIT) |
| 2c0262af FB |
212 | |
| 213 | #define PG_ERROR_W_BIT 1 | |
| 214 | ||
| 215 | #define PG_ERROR_P_MASK 0x01 | |
| 216 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
| 217 | #define PG_ERROR_U_MASK 0x04 | |
| 218 | #define PG_ERROR_RSVD_MASK 0x08 | |
| 5cf38396 | 219 | #define PG_ERROR_I_D_MASK 0x10 |
| 2c0262af FB |
220 | |
| 221 | #define MSR_IA32_APICBASE 0x1b | |
| 222 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
| 223 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
| 224 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
| 225 | ||
| 226 | #define MSR_IA32_SYSENTER_CS 0x174 | |
| 227 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
| 228 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
| 229 | ||
| 8f091a59 FB |
230 | #define MSR_MCG_CAP 0x179 |
| 231 | #define MSR_MCG_STATUS 0x17a | |
| 232 | #define MSR_MCG_CTL 0x17b | |
| 233 | ||
| 234 | #define MSR_PAT 0x277 | |
| 235 | ||
| 14ce26e7 FB |
236 | #define MSR_EFER 0xc0000080 |
| 237 | ||
| 238 | #define MSR_EFER_SCE (1 << 0) | |
| 239 | #define MSR_EFER_LME (1 << 8) | |
| 240 | #define MSR_EFER_LMA (1 << 10) | |
| 241 | #define MSR_EFER_NXE (1 << 11) | |
| 242 | #define MSR_EFER_FFXSR (1 << 14) | |
| 243 | ||
| 244 | #define MSR_STAR 0xc0000081 | |
| 245 | #define MSR_LSTAR 0xc0000082 | |
| 246 | #define MSR_CSTAR 0xc0000083 | |
| 247 | #define MSR_FMASK 0xc0000084 | |
| 248 | #define MSR_FSBASE 0xc0000100 | |
| 249 | #define MSR_GSBASE 0xc0000101 | |
| 250 | #define MSR_KERNELGSBASE 0xc0000102 | |
| 251 | ||
| 252 | /* cpuid_features bits */ | |
| 253 | #define CPUID_FP87 (1 << 0) | |
| 254 | #define CPUID_VME (1 << 1) | |
| 255 | #define CPUID_DE (1 << 2) | |
| 256 | #define CPUID_PSE (1 << 3) | |
| 257 | #define CPUID_TSC (1 << 4) | |
| 258 | #define CPUID_MSR (1 << 5) | |
| 259 | #define CPUID_PAE (1 << 6) | |
| 260 | #define CPUID_MCE (1 << 7) | |
| 261 | #define CPUID_CX8 (1 << 8) | |
| 262 | #define CPUID_APIC (1 << 9) | |
| 263 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ | |
| 264 | #define CPUID_MTRR (1 << 12) | |
| 265 | #define CPUID_PGE (1 << 13) | |
| 266 | #define CPUID_MCA (1 << 14) | |
| 267 | #define CPUID_CMOV (1 << 15) | |
| 8f091a59 | 268 | #define CPUID_PAT (1 << 16) |
| 8988ae89 | 269 | #define CPUID_PSE36 (1 << 17) |
| 8f091a59 | 270 | #define CPUID_CLFLUSH (1 << 19) |
| 14ce26e7 FB |
271 | /* ... */ |
| 272 | #define CPUID_MMX (1 << 23) | |
| 273 | #define CPUID_FXSR (1 << 24) | |
| 274 | #define CPUID_SSE (1 << 25) | |
| 275 | #define CPUID_SSE2 (1 << 26) | |
| 276 | ||
| 465e9838 | 277 | #define CPUID_EXT_SSE3 (1 << 0) |
| 9df217a3 FB |
278 | #define CPUID_EXT_MONITOR (1 << 3) |
| 279 | #define CPUID_EXT_CX16 (1 << 13) | |
| 280 | ||
| 281 | #define CPUID_EXT2_SYSCALL (1 << 11) | |
| 282 | #define CPUID_EXT2_NX (1 << 20) | |
| 8d9bfc2b | 283 | #define CPUID_EXT2_FFXSR (1 << 25) |
| 9df217a3 FB |
284 | #define CPUID_EXT2_LM (1 << 29) |
| 285 | ||
| 2c0262af FB |
286 | #define EXCP00_DIVZ 0 |
| 287 | #define EXCP01_SSTP 1 | |
| 288 | #define EXCP02_NMI 2 | |
| 289 | #define EXCP03_INT3 3 | |
| 290 | #define EXCP04_INTO 4 | |
| 291 | #define EXCP05_BOUND 5 | |
| 292 | #define EXCP06_ILLOP 6 | |
| 293 | #define EXCP07_PREX 7 | |
| 294 | #define EXCP08_DBLE 8 | |
| 295 | #define EXCP09_XERR 9 | |
| 296 | #define EXCP0A_TSS 10 | |
| 297 | #define EXCP0B_NOSEG 11 | |
| 298 | #define EXCP0C_STACK 12 | |
| 299 | #define EXCP0D_GPF 13 | |
| 300 | #define EXCP0E_PAGE 14 | |
| 301 | #define EXCP10_COPR 16 | |
| 302 | #define EXCP11_ALGN 17 | |
| 303 | #define EXCP12_MCHK 18 | |
| 304 | ||
| 305 | enum { | |
| 306 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
| 307 | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */ | |
| d36cd60e FB |
308 | |
| 309 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
| 310 | CC_OP_MULW, | |
| 311 | CC_OP_MULL, | |
| 14ce26e7 | 312 | CC_OP_MULQ, |
| 2c0262af FB |
313 | |
| 314 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
| 315 | CC_OP_ADDW, | |
| 316 | CC_OP_ADDL, | |
| 14ce26e7 | 317 | CC_OP_ADDQ, |
| 2c0262af FB |
318 | |
| 319 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
| 320 | CC_OP_ADCW, | |
| 321 | CC_OP_ADCL, | |
| 14ce26e7 | 322 | CC_OP_ADCQ, |
| 2c0262af FB |
323 | |
| 324 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
| 325 | CC_OP_SUBW, | |
| 326 | CC_OP_SUBL, | |
| 14ce26e7 | 327 | CC_OP_SUBQ, |
| 2c0262af FB |
328 | |
| 329 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
| 330 | CC_OP_SBBW, | |
| 331 | CC_OP_SBBL, | |
| 14ce26e7 | 332 | CC_OP_SBBQ, |
| 2c0262af FB |
333 | |
| 334 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
| 335 | CC_OP_LOGICW, | |
| 336 | CC_OP_LOGICL, | |
| 14ce26e7 | 337 | CC_OP_LOGICQ, |
| 2c0262af FB |
338 | |
| 339 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
| 340 | CC_OP_INCW, | |
| 341 | CC_OP_INCL, | |
| 14ce26e7 | 342 | CC_OP_INCQ, |
| 2c0262af FB |
343 | |
| 344 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
| 345 | CC_OP_DECW, | |
| 346 | CC_OP_DECL, | |
| 14ce26e7 | 347 | CC_OP_DECQ, |
| 2c0262af | 348 | |
| 6b652794 | 349 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
| 2c0262af FB |
350 | CC_OP_SHLW, |
| 351 | CC_OP_SHLL, | |
| 14ce26e7 | 352 | CC_OP_SHLQ, |
| 2c0262af FB |
353 | |
| 354 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
| 355 | CC_OP_SARW, | |
| 356 | CC_OP_SARL, | |
| 14ce26e7 | 357 | CC_OP_SARQ, |
| 2c0262af FB |
358 | |
| 359 | CC_OP_NB, | |
| 360 | }; | |
| 361 | ||
| 7a0e1f41 | 362 | #ifdef FLOATX80 |
| 2c0262af FB |
363 | #define USE_X86LDOUBLE |
| 364 | #endif | |
| 365 | ||
| 366 | #ifdef USE_X86LDOUBLE | |
| 7a0e1f41 | 367 | typedef floatx80 CPU86_LDouble; |
| 2c0262af | 368 | #else |
| 7a0e1f41 | 369 | typedef float64 CPU86_LDouble; |
| 2c0262af FB |
370 | #endif |
| 371 | ||
| 372 | typedef struct SegmentCache { | |
| 373 | uint32_t selector; | |
| 14ce26e7 | 374 | target_ulong base; |
| 2c0262af FB |
375 | uint32_t limit; |
| 376 | uint32_t flags; | |
| 377 | } SegmentCache; | |
| 378 | ||
| 826461bb | 379 | typedef union { |
| 664e0f19 FB |
380 | uint8_t _b[16]; |
| 381 | uint16_t _w[8]; | |
| 382 | uint32_t _l[4]; | |
| 383 | uint64_t _q[2]; | |
| 7a0e1f41 FB |
384 | float32 _s[4]; |
| 385 | float64 _d[2]; | |
| 14ce26e7 FB |
386 | } XMMReg; |
| 387 | ||
| 826461bb FB |
388 | typedef union { |
| 389 | uint8_t _b[8]; | |
| 390 | uint16_t _w[2]; | |
| 391 | uint32_t _l[1]; | |
| 392 | uint64_t q; | |
| 393 | } MMXReg; | |
| 394 | ||
| 395 | #ifdef WORDS_BIGENDIAN | |
| 396 | #define XMM_B(n) _b[15 - (n)] | |
| 397 | #define XMM_W(n) _w[7 - (n)] | |
| 398 | #define XMM_L(n) _l[3 - (n)] | |
| 664e0f19 | 399 | #define XMM_S(n) _s[3 - (n)] |
| 826461bb | 400 | #define XMM_Q(n) _q[1 - (n)] |
| 664e0f19 | 401 | #define XMM_D(n) _d[1 - (n)] |
| 826461bb FB |
402 | |
| 403 | #define MMX_B(n) _b[7 - (n)] | |
| 404 | #define MMX_W(n) _w[3 - (n)] | |
| 405 | #define MMX_L(n) _l[1 - (n)] | |
| 406 | #else | |
| 407 | #define XMM_B(n) _b[n] | |
| 408 | #define XMM_W(n) _w[n] | |
| 409 | #define XMM_L(n) _l[n] | |
| 664e0f19 | 410 | #define XMM_S(n) _s[n] |
| 826461bb | 411 | #define XMM_Q(n) _q[n] |
| 664e0f19 | 412 | #define XMM_D(n) _d[n] |
| 826461bb FB |
413 | |
| 414 | #define MMX_B(n) _b[n] | |
| 415 | #define MMX_W(n) _w[n] | |
| 416 | #define MMX_L(n) _l[n] | |
| 417 | #endif | |
| 664e0f19 | 418 | #define MMX_Q(n) q |
| 826461bb | 419 | |
| 14ce26e7 FB |
420 | #ifdef TARGET_X86_64 |
| 421 | #define CPU_NB_REGS 16 | |
| 422 | #else | |
| 423 | #define CPU_NB_REGS 8 | |
| 424 | #endif | |
| 425 | ||
| 2c0262af | 426 | typedef struct CPUX86State { |
| 14ce26e7 FB |
427 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
| 428 | /* temporaries if we cannot store them in host registers */ | |
| 429 | target_ulong t0, t1, t2; | |
| 430 | #endif | |
| 431 | ||
| 2c0262af | 432 | /* standard registers */ |
| 14ce26e7 FB |
433 | target_ulong regs[CPU_NB_REGS]; |
| 434 | target_ulong eip; | |
| 435 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
| 2c0262af FB |
436 | flags and DF are set to zero because they are |
| 437 | stored elsewhere */ | |
| 438 | ||
| 439 | /* emulator internal eflags handling */ | |
| 14ce26e7 FB |
440 | target_ulong cc_src; |
| 441 | target_ulong cc_dst; | |
| 2c0262af FB |
442 | uint32_t cc_op; |
| 443 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
| 444 | uint32_t hflags; /* hidden flags, see HF_xxx constants */ | |
| 445 | ||
| 9df217a3 FB |
446 | /* segments */ |
| 447 | SegmentCache segs[6]; /* selector values */ | |
| 448 | SegmentCache ldt; | |
| 449 | SegmentCache tr; | |
| 450 | SegmentCache gdt; /* only base and limit are used */ | |
| 451 | SegmentCache idt; /* only base and limit are used */ | |
| 452 | ||
| 453 | target_ulong cr[5]; /* NOTE: cr1 is unused */ | |
| 454 | uint32_t a20_mask; | |
| 455 | ||
| 2c0262af FB |
456 | /* FPU state */ |
| 457 | unsigned int fpstt; /* top of stack index */ | |
| 458 | unsigned int fpus; | |
| 459 | unsigned int fpuc; | |
| 460 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ | |
| 664e0f19 FB |
461 | union { |
| 462 | #ifdef USE_X86LDOUBLE | |
| 463 | CPU86_LDouble d __attribute__((aligned(16))); | |
| 464 | #else | |
| 465 | CPU86_LDouble d; | |
| 466 | #endif | |
| 467 | MMXReg mmx; | |
| 468 | } fpregs[8]; | |
| 2c0262af FB |
469 | |
| 470 | /* emulator internal variables */ | |
| 7a0e1f41 | 471 | float_status fp_status; |
| 2c0262af FB |
472 | CPU86_LDouble ft0; |
| 473 | union { | |
| 474 | float f; | |
| 475 | double d; | |
| 476 | int i32; | |
| 477 | int64_t i64; | |
| 478 | } fp_convert; | |
| 479 | ||
| 7a0e1f41 | 480 | float_status sse_status; |
| 664e0f19 | 481 | uint32_t mxcsr; |
| 14ce26e7 FB |
482 | XMMReg xmm_regs[CPU_NB_REGS]; |
| 483 | XMMReg xmm_t0; | |
| 664e0f19 | 484 | MMXReg mmx_t0; |
| 14ce26e7 | 485 | |
| 2c0262af FB |
486 | /* sysenter registers */ |
| 487 | uint32_t sysenter_cs; | |
| 488 | uint32_t sysenter_esp; | |
| 489 | uint32_t sysenter_eip; | |
| 8d9bfc2b FB |
490 | uint64_t efer; |
| 491 | uint64_t star; | |
| 14ce26e7 | 492 | #ifdef TARGET_X86_64 |
| 14ce26e7 FB |
493 | target_ulong lstar; |
| 494 | target_ulong cstar; | |
| 495 | target_ulong fmask; | |
| 496 | target_ulong kernelgsbase; | |
| 497 | #endif | |
| 58fe2f10 | 498 | |
| 8f091a59 FB |
499 | uint64_t pat; |
| 500 | ||
| 58fe2f10 | 501 | /* temporary data for USE_CODE_COPY mode */ |
| 7eee2a50 | 502 | #ifdef USE_CODE_COPY |
| 58fe2f10 FB |
503 | uint32_t tmp0; |
| 504 | uint32_t saved_esp; | |
| 7eee2a50 FB |
505 | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
| 506 | #endif | |
| 2c0262af FB |
507 | |
| 508 | /* exception/interrupt handling */ | |
| 509 | jmp_buf jmp_env; | |
| 510 | int exception_index; | |
| 511 | int error_code; | |
| 512 | int exception_is_int; | |
| 826461bb | 513 | target_ulong exception_next_eip; |
| 14ce26e7 | 514 | target_ulong dr[8]; /* debug registers */ |
| 3b21e03e | 515 | uint32_t smbase; |
| 2c0262af FB |
516 | int interrupt_request; |
| 517 | int user_mode_only; /* user mode only simulation */ | |
| 518 | ||
| a316d335 | 519 | CPU_COMMON |
| 2c0262af | 520 | |
| 14ce26e7 | 521 | /* processor features (e.g. for CPUID insn) */ |
| 8d9bfc2b | 522 | uint32_t cpuid_level; |
| 14ce26e7 FB |
523 | uint32_t cpuid_vendor1; |
| 524 | uint32_t cpuid_vendor2; | |
| 525 | uint32_t cpuid_vendor3; | |
| 526 | uint32_t cpuid_version; | |
| 527 | uint32_t cpuid_features; | |
| 9df217a3 | 528 | uint32_t cpuid_ext_features; |
| 8d9bfc2b FB |
529 | uint32_t cpuid_xlevel; |
| 530 | uint32_t cpuid_model[12]; | |
| 531 | uint32_t cpuid_ext2_features; | |
| 532 | ||
| 9df217a3 FB |
533 | #ifdef USE_KQEMU |
| 534 | int kqemu_enabled; | |
| f1c85677 | 535 | int last_io_time; |
| 9df217a3 | 536 | #endif |
| 14ce26e7 FB |
537 | /* in order to simplify APIC support, we leave this pointer to the |
| 538 | user */ | |
| 539 | struct APICState *apic_state; | |
| 2c0262af FB |
540 | } CPUX86State; |
| 541 | ||
| 2c0262af FB |
542 | CPUX86State *cpu_x86_init(void); |
| 543 | int cpu_x86_exec(CPUX86State *s); | |
| 544 | void cpu_x86_close(CPUX86State *s); | |
| d720b93d | 545 | int cpu_get_pic_interrupt(CPUX86State *s); |
| 2ee73ac3 FB |
546 | /* MSDOS compatibility mode FPU exception support */ |
| 547 | void cpu_set_ferr(CPUX86State *s); | |
| 2c0262af FB |
548 | |
| 549 | /* this function must always be used to load data in the segment | |
| 550 | cache: it synchronizes the hflags with the segment cache values */ | |
| 551 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, | |
| 552 | int seg_reg, unsigned int selector, | |
| 8988ae89 FB |
553 | target_ulong base, |
| 554 | unsigned int limit, | |
| 2c0262af FB |
555 | unsigned int flags) |
| 556 | { | |
| 557 | SegmentCache *sc; | |
| 558 | unsigned int new_hflags; | |
| 559 | ||
| 560 | sc = &env->segs[seg_reg]; | |
| 561 | sc->selector = selector; | |
| 562 | sc->base = base; | |
| 563 | sc->limit = limit; | |
| 564 | sc->flags = flags; | |
| 565 | ||
| 566 | /* update the hidden flags */ | |
| 14ce26e7 FB |
567 | { |
| 568 | if (seg_reg == R_CS) { | |
| 569 | #ifdef TARGET_X86_64 | |
| 570 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
| 571 | /* long mode */ | |
| 572 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
| 573 | env->hflags &= ~(HF_ADDSEG_MASK); | |
| 574 | } else | |
| 575 | #endif | |
| 576 | { | |
| 577 | /* legacy / compatibility case */ | |
| 578 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
| 579 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
| 580 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
| 581 | new_hflags; | |
| 582 | } | |
| 583 | } | |
| 584 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
| 585 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
| 586 | if (env->hflags & HF_CS64_MASK) { | |
| 587 | /* zero base assumed for DS, ES and SS in long mode */ | |
| 588 | } else if (!(env->cr[0] & CR0_PE_MASK) || | |
| 735a8fd3 FB |
589 | (env->eflags & VM_MASK) || |
| 590 | !(env->hflags & HF_CS32_MASK)) { | |
| 14ce26e7 FB |
591 | /* XXX: try to avoid this test. The problem comes from the |
| 592 | fact that is real mode or vm86 mode we only modify the | |
| 593 | 'base' and 'selector' fields of the segment cache to go | |
| 594 | faster. A solution may be to force addseg to one in | |
| 595 | translate-i386.c. */ | |
| 596 | new_hflags |= HF_ADDSEG_MASK; | |
| 597 | } else { | |
| 735a8fd3 FB |
598 | new_hflags |= ((env->segs[R_DS].base | |
| 599 | env->segs[R_ES].base | | |
| 600 | env->segs[R_SS].base) != 0) << | |
| 14ce26e7 FB |
601 | HF_ADDSEG_SHIFT; |
| 602 | } | |
| 603 | env->hflags = (env->hflags & | |
| 604 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; | |
| 2c0262af | 605 | } |
| 2c0262af FB |
606 | } |
| 607 | ||
| 608 | /* wrapper, just in case memory mappings must be changed */ | |
| 609 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) | |
| 610 | { | |
| 611 | #if HF_CPL_MASK == 3 | |
| 612 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; | |
| 613 | #else | |
| 614 | #error HF_CPL_MASK is hardcoded | |
| 615 | #endif | |
| 616 | } | |
| 617 | ||
| 1f1af9fd FB |
618 | /* used for debug or cpu save/restore */ |
| 619 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f); | |
| 620 | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); | |
| 621 | ||
| 2c0262af FB |
622 | /* the following helpers are only usable in user mode simulation as |
| 623 | they can trigger unexpected exceptions */ | |
| 624 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); | |
| 625 | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); | |
| 626 | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); | |
| 627 | ||
| 628 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
| 629 | signal handlers to inform the virtual CPU of exceptions. non zero | |
| 630 | is returned if the signal was handled by the virtual CPU. */ | |
| 5a7b542b | 631 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
| 2c0262af | 632 | void *puc); |
| 461c0471 | 633 | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
| 2c0262af | 634 | |
| 28ab0e2e FB |
635 | uint64_t cpu_get_tsc(CPUX86State *env); |
| 636 | ||
| 14ce26e7 FB |
637 | void cpu_set_apic_base(CPUX86State *env, uint64_t val); |
| 638 | uint64_t cpu_get_apic_base(CPUX86State *env); | |
| 9230e66e FB |
639 | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val); |
| 640 | #ifndef NO_CPU_IO_DEFS | |
| 641 | uint8_t cpu_get_apic_tpr(CPUX86State *env); | |
| 642 | #endif | |
| 3b21e03e | 643 | void cpu_smm_update(CPUX86State *env); |
| 14ce26e7 | 644 | |
| 64a595f2 FB |
645 | /* will be suppressed */ |
| 646 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
| 647 | ||
| 2c0262af FB |
648 | /* used to debug */ |
| 649 | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ | |
| 650 | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ | |
| 2c0262af | 651 | |
| f1c85677 FB |
652 | #ifdef USE_KQEMU |
| 653 | static inline int cpu_get_time_fast(void) | |
| 654 | { | |
| 655 | int low, high; | |
| 656 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); | |
| 657 | return low; | |
| 658 | } | |
| 659 | #endif | |
| 660 | ||
| 2c0262af FB |
661 | #define TARGET_PAGE_BITS 12 |
| 662 | #include "cpu-all.h" | |
| 663 | ||
| 664 | #endif /* CPU_I386_H */ |