]>
Commit | Line | Data |
---|---|---|
2c0262af FB |
1 | /* |
2 | * i386 virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #ifndef CPU_I386_H | |
20 | #define CPU_I386_H | |
21 | ||
14ce26e7 | 22 | #include "config.h" |
9a78eead | 23 | #include "qemu-common.h" |
14ce26e7 FB |
24 | |
25 | #ifdef TARGET_X86_64 | |
26 | #define TARGET_LONG_BITS 64 | |
27 | #else | |
3cf1e035 | 28 | #define TARGET_LONG_BITS 32 |
14ce26e7 | 29 | #endif |
3cf1e035 | 30 | |
d720b93d FB |
31 | /* target supports implicit self modifying code */ |
32 | #define TARGET_HAS_SMC | |
33 | /* support for self modifying code even if the modified instruction is | |
34 | close to the modifying instruction */ | |
35 | #define TARGET_HAS_PRECISE_SMC | |
36 | ||
1fddef4b FB |
37 | #define TARGET_HAS_ICE 1 |
38 | ||
9042c0e2 TS |
39 | #ifdef TARGET_X86_64 |
40 | #define ELF_MACHINE EM_X86_64 | |
41 | #else | |
42 | #define ELF_MACHINE EM_386 | |
43 | #endif | |
44 | ||
9349b4f9 | 45 | #define CPUArchState struct CPUX86State |
c2764719 | 46 | |
2c0262af FB |
47 | #include "cpu-defs.h" |
48 | ||
7a0e1f41 FB |
49 | #include "softfloat.h" |
50 | ||
2c0262af FB |
51 | #define R_EAX 0 |
52 | #define R_ECX 1 | |
53 | #define R_EDX 2 | |
54 | #define R_EBX 3 | |
55 | #define R_ESP 4 | |
56 | #define R_EBP 5 | |
57 | #define R_ESI 6 | |
58 | #define R_EDI 7 | |
59 | ||
60 | #define R_AL 0 | |
61 | #define R_CL 1 | |
62 | #define R_DL 2 | |
63 | #define R_BL 3 | |
64 | #define R_AH 4 | |
65 | #define R_CH 5 | |
66 | #define R_DH 6 | |
67 | #define R_BH 7 | |
68 | ||
69 | #define R_ES 0 | |
70 | #define R_CS 1 | |
71 | #define R_SS 2 | |
72 | #define R_DS 3 | |
73 | #define R_FS 4 | |
74 | #define R_GS 5 | |
75 | ||
76 | /* segment descriptor fields */ | |
77 | #define DESC_G_MASK (1 << 23) | |
78 | #define DESC_B_SHIFT 22 | |
79 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
14ce26e7 FB |
80 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
81 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
2c0262af FB |
82 | #define DESC_AVL_MASK (1 << 20) |
83 | #define DESC_P_MASK (1 << 15) | |
84 | #define DESC_DPL_SHIFT 13 | |
a3867ed2 | 85 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
2c0262af FB |
86 | #define DESC_S_MASK (1 << 12) |
87 | #define DESC_TYPE_SHIFT 8 | |
a3867ed2 | 88 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
2c0262af FB |
89 | #define DESC_A_MASK (1 << 8) |
90 | ||
e670b89e FB |
91 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
92 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
93 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
2c0262af | 94 | |
e670b89e FB |
95 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
96 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
97 | ||
98 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
2c0262af FB |
99 | |
100 | /* eflags masks */ | |
101 | #define CC_C 0x0001 | |
102 | #define CC_P 0x0004 | |
103 | #define CC_A 0x0010 | |
104 | #define CC_Z 0x0040 | |
105 | #define CC_S 0x0080 | |
106 | #define CC_O 0x0800 | |
107 | ||
108 | #define TF_SHIFT 8 | |
109 | #define IOPL_SHIFT 12 | |
110 | #define VM_SHIFT 17 | |
111 | ||
112 | #define TF_MASK 0x00000100 | |
113 | #define IF_MASK 0x00000200 | |
114 | #define DF_MASK 0x00000400 | |
115 | #define IOPL_MASK 0x00003000 | |
116 | #define NT_MASK 0x00004000 | |
117 | #define RF_MASK 0x00010000 | |
118 | #define VM_MASK 0x00020000 | |
5fafdf24 | 119 | #define AC_MASK 0x00040000 |
2c0262af FB |
120 | #define VIF_MASK 0x00080000 |
121 | #define VIP_MASK 0x00100000 | |
122 | #define ID_MASK 0x00200000 | |
123 | ||
aa1f17c1 | 124 | /* hidden flags - used internally by qemu to represent additional cpu |
33c263df FB |
125 | states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not |
126 | redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit | |
127 | position to ease oring with eflags. */ | |
2c0262af FB |
128 | /* current cpl */ |
129 | #define HF_CPL_SHIFT 0 | |
130 | /* true if soft mmu is being used */ | |
131 | #define HF_SOFTMMU_SHIFT 2 | |
132 | /* true if hardware interrupts must be disabled for next instruction */ | |
133 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
134 | /* 16 or 32 segments */ | |
135 | #define HF_CS32_SHIFT 4 | |
136 | #define HF_SS32_SHIFT 5 | |
dc196a57 | 137 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
2c0262af | 138 | #define HF_ADDSEG_SHIFT 6 |
65262d57 FB |
139 | /* copy of CR0.PE (protected mode) */ |
140 | #define HF_PE_SHIFT 7 | |
141 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
7eee2a50 FB |
142 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
143 | #define HF_EM_SHIFT 10 | |
144 | #define HF_TS_SHIFT 11 | |
65262d57 | 145 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
14ce26e7 FB |
146 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
147 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
a2397807 | 148 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
65262d57 | 149 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
3b21e03e | 150 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
db620f46 FB |
151 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
152 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ | |
a2397807 | 153 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
2c0262af FB |
154 | |
155 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
156 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) | |
157 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) | |
158 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
159 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
160 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
65262d57 | 161 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
58fe2f10 | 162 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
7eee2a50 FB |
163 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
164 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
165 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
0650f1ab | 166 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
14ce26e7 FB |
167 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
168 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
a2397807 | 169 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
0650f1ab | 170 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
3b21e03e | 171 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
872929aa FB |
172 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
173 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) | |
a2397807 | 174 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
2c0262af | 175 | |
db620f46 FB |
176 | /* hflags2 */ |
177 | ||
178 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ | |
179 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
180 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
181 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
182 | ||
183 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
184 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
185 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
186 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
187 | ||
0650f1ab AL |
188 | #define CR0_PE_SHIFT 0 |
189 | #define CR0_MP_SHIFT 1 | |
190 | ||
2c0262af | 191 | #define CR0_PE_MASK (1 << 0) |
7eee2a50 FB |
192 | #define CR0_MP_MASK (1 << 1) |
193 | #define CR0_EM_MASK (1 << 2) | |
2c0262af | 194 | #define CR0_TS_MASK (1 << 3) |
2ee73ac3 | 195 | #define CR0_ET_MASK (1 << 4) |
7eee2a50 | 196 | #define CR0_NE_MASK (1 << 5) |
2c0262af FB |
197 | #define CR0_WP_MASK (1 << 16) |
198 | #define CR0_AM_MASK (1 << 18) | |
199 | #define CR0_PG_MASK (1 << 31) | |
200 | ||
201 | #define CR4_VME_MASK (1 << 0) | |
202 | #define CR4_PVI_MASK (1 << 1) | |
203 | #define CR4_TSD_MASK (1 << 2) | |
204 | #define CR4_DE_MASK (1 << 3) | |
205 | #define CR4_PSE_MASK (1 << 4) | |
64a595f2 | 206 | #define CR4_PAE_MASK (1 << 5) |
79c4f6b0 | 207 | #define CR4_MCE_MASK (1 << 6) |
64a595f2 | 208 | #define CR4_PGE_MASK (1 << 7) |
14ce26e7 | 209 | #define CR4_PCE_MASK (1 << 8) |
0650f1ab AL |
210 | #define CR4_OSFXSR_SHIFT 9 |
211 | #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) | |
14ce26e7 | 212 | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
2c0262af | 213 | |
01df040b AL |
214 | #define DR6_BD (1 << 13) |
215 | #define DR6_BS (1 << 14) | |
216 | #define DR6_BT (1 << 15) | |
217 | #define DR6_FIXED_1 0xffff0ff0 | |
218 | ||
219 | #define DR7_GD (1 << 13) | |
220 | #define DR7_TYPE_SHIFT 16 | |
221 | #define DR7_LEN_SHIFT 18 | |
222 | #define DR7_FIXED_1 0x00000400 | |
223 | ||
2c0262af FB |
224 | #define PG_PRESENT_BIT 0 |
225 | #define PG_RW_BIT 1 | |
226 | #define PG_USER_BIT 2 | |
227 | #define PG_PWT_BIT 3 | |
228 | #define PG_PCD_BIT 4 | |
229 | #define PG_ACCESSED_BIT 5 | |
230 | #define PG_DIRTY_BIT 6 | |
231 | #define PG_PSE_BIT 7 | |
232 | #define PG_GLOBAL_BIT 8 | |
5cf38396 | 233 | #define PG_NX_BIT 63 |
2c0262af FB |
234 | |
235 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
236 | #define PG_RW_MASK (1 << PG_RW_BIT) | |
237 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
238 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
239 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
240 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
241 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) | |
242 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
243 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
3f2cbf0d | 244 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
5cf38396 | 245 | #define PG_NX_MASK (1LL << PG_NX_BIT) |
2c0262af FB |
246 | |
247 | #define PG_ERROR_W_BIT 1 | |
248 | ||
249 | #define PG_ERROR_P_MASK 0x01 | |
250 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
251 | #define PG_ERROR_U_MASK 0x04 | |
252 | #define PG_ERROR_RSVD_MASK 0x08 | |
5cf38396 | 253 | #define PG_ERROR_I_D_MASK 0x10 |
2c0262af | 254 | |
c0532a76 MT |
255 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
256 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
79c4f6b0 | 257 | |
c0532a76 | 258 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
79c4f6b0 HY |
259 | #define MCE_BANKS_DEF 10 |
260 | ||
c0532a76 MT |
261 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
262 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
e6a0575e | 263 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
79c4f6b0 | 264 | |
e6a0575e AL |
265 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
266 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
267 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
c0532a76 MT |
268 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
269 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
270 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
271 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
272 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
273 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
274 | ||
275 | /* MISC register defines */ | |
276 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ | |
277 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
278 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
279 | #define MCM_ADDR_MEM 3 /* memory address */ | |
280 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
79c4f6b0 | 281 | |
0650f1ab | 282 | #define MSR_IA32_TSC 0x10 |
2c0262af FB |
283 | #define MSR_IA32_APICBASE 0x1b |
284 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
285 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
286 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
aa82ba54 | 287 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
2c0262af | 288 | |
dd5e3b17 AL |
289 | #define MSR_MTRRcap 0xfe |
290 | #define MSR_MTRRcap_VCNT 8 | |
291 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
292 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
293 | ||
2c0262af FB |
294 | #define MSR_IA32_SYSENTER_CS 0x174 |
295 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
296 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
297 | ||
8f091a59 FB |
298 | #define MSR_MCG_CAP 0x179 |
299 | #define MSR_MCG_STATUS 0x17a | |
300 | #define MSR_MCG_CTL 0x17b | |
301 | ||
e737b32a AZ |
302 | #define MSR_IA32_PERF_STATUS 0x198 |
303 | ||
21e87c46 AK |
304 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
305 | /* Indicates good rep/movs microcode on some processors: */ | |
306 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
307 | ||
165d9b82 AL |
308 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
309 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
310 | ||
311 | #define MSR_MTRRfix64K_00000 0x250 | |
312 | #define MSR_MTRRfix16K_80000 0x258 | |
313 | #define MSR_MTRRfix16K_A0000 0x259 | |
314 | #define MSR_MTRRfix4K_C0000 0x268 | |
315 | #define MSR_MTRRfix4K_C8000 0x269 | |
316 | #define MSR_MTRRfix4K_D0000 0x26a | |
317 | #define MSR_MTRRfix4K_D8000 0x26b | |
318 | #define MSR_MTRRfix4K_E0000 0x26c | |
319 | #define MSR_MTRRfix4K_E8000 0x26d | |
320 | #define MSR_MTRRfix4K_F0000 0x26e | |
321 | #define MSR_MTRRfix4K_F8000 0x26f | |
322 | ||
8f091a59 FB |
323 | #define MSR_PAT 0x277 |
324 | ||
165d9b82 AL |
325 | #define MSR_MTRRdefType 0x2ff |
326 | ||
79c4f6b0 HY |
327 | #define MSR_MC0_CTL 0x400 |
328 | #define MSR_MC0_STATUS 0x401 | |
329 | #define MSR_MC0_ADDR 0x402 | |
330 | #define MSR_MC0_MISC 0x403 | |
331 | ||
14ce26e7 FB |
332 | #define MSR_EFER 0xc0000080 |
333 | ||
334 | #define MSR_EFER_SCE (1 << 0) | |
335 | #define MSR_EFER_LME (1 << 8) | |
336 | #define MSR_EFER_LMA (1 << 10) | |
337 | #define MSR_EFER_NXE (1 << 11) | |
872929aa | 338 | #define MSR_EFER_SVME (1 << 12) |
14ce26e7 FB |
339 | #define MSR_EFER_FFXSR (1 << 14) |
340 | ||
341 | #define MSR_STAR 0xc0000081 | |
342 | #define MSR_LSTAR 0xc0000082 | |
343 | #define MSR_CSTAR 0xc0000083 | |
344 | #define MSR_FMASK 0xc0000084 | |
345 | #define MSR_FSBASE 0xc0000100 | |
346 | #define MSR_GSBASE 0xc0000101 | |
347 | #define MSR_KERNELGSBASE 0xc0000102 | |
1b050077 | 348 | #define MSR_TSC_AUX 0xc0000103 |
14ce26e7 | 349 | |
0573fbfc TS |
350 | #define MSR_VM_HSAVE_PA 0xc0010117 |
351 | ||
14ce26e7 FB |
352 | /* cpuid_features bits */ |
353 | #define CPUID_FP87 (1 << 0) | |
354 | #define CPUID_VME (1 << 1) | |
355 | #define CPUID_DE (1 << 2) | |
356 | #define CPUID_PSE (1 << 3) | |
357 | #define CPUID_TSC (1 << 4) | |
358 | #define CPUID_MSR (1 << 5) | |
359 | #define CPUID_PAE (1 << 6) | |
360 | #define CPUID_MCE (1 << 7) | |
361 | #define CPUID_CX8 (1 << 8) | |
362 | #define CPUID_APIC (1 << 9) | |
363 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ | |
364 | #define CPUID_MTRR (1 << 12) | |
365 | #define CPUID_PGE (1 << 13) | |
366 | #define CPUID_MCA (1 << 14) | |
367 | #define CPUID_CMOV (1 << 15) | |
8f091a59 | 368 | #define CPUID_PAT (1 << 16) |
8988ae89 | 369 | #define CPUID_PSE36 (1 << 17) |
a049de61 | 370 | #define CPUID_PN (1 << 18) |
8f091a59 | 371 | #define CPUID_CLFLUSH (1 << 19) |
a049de61 FB |
372 | #define CPUID_DTS (1 << 21) |
373 | #define CPUID_ACPI (1 << 22) | |
14ce26e7 FB |
374 | #define CPUID_MMX (1 << 23) |
375 | #define CPUID_FXSR (1 << 24) | |
376 | #define CPUID_SSE (1 << 25) | |
377 | #define CPUID_SSE2 (1 << 26) | |
a049de61 FB |
378 | #define CPUID_SS (1 << 27) |
379 | #define CPUID_HT (1 << 28) | |
380 | #define CPUID_TM (1 << 29) | |
381 | #define CPUID_IA64 (1 << 30) | |
382 | #define CPUID_PBE (1 << 31) | |
14ce26e7 | 383 | |
465e9838 | 384 | #define CPUID_EXT_SSE3 (1 << 0) |
558fa836 | 385 | #define CPUID_EXT_DTES64 (1 << 2) |
9df217a3 | 386 | #define CPUID_EXT_MONITOR (1 << 3) |
a049de61 FB |
387 | #define CPUID_EXT_DSCPL (1 << 4) |
388 | #define CPUID_EXT_VMX (1 << 5) | |
389 | #define CPUID_EXT_SMX (1 << 6) | |
390 | #define CPUID_EXT_EST (1 << 7) | |
391 | #define CPUID_EXT_TM2 (1 << 8) | |
392 | #define CPUID_EXT_SSSE3 (1 << 9) | |
393 | #define CPUID_EXT_CID (1 << 10) | |
9df217a3 | 394 | #define CPUID_EXT_CX16 (1 << 13) |
a049de61 | 395 | #define CPUID_EXT_XTPR (1 << 14) |
558fa836 PB |
396 | #define CPUID_EXT_PDCM (1 << 15) |
397 | #define CPUID_EXT_DCA (1 << 18) | |
398 | #define CPUID_EXT_SSE41 (1 << 19) | |
399 | #define CPUID_EXT_SSE42 (1 << 20) | |
400 | #define CPUID_EXT_X2APIC (1 << 21) | |
401 | #define CPUID_EXT_MOVBE (1 << 22) | |
402 | #define CPUID_EXT_POPCNT (1 << 23) | |
a75b3e0f | 403 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) |
558fa836 PB |
404 | #define CPUID_EXT_XSAVE (1 << 26) |
405 | #define CPUID_EXT_OSXSAVE (1 << 27) | |
6c0d7ee8 | 406 | #define CPUID_EXT_HYPERVISOR (1 << 31) |
9df217a3 FB |
407 | |
408 | #define CPUID_EXT2_SYSCALL (1 << 11) | |
a049de61 | 409 | #define CPUID_EXT2_MP (1 << 19) |
9df217a3 | 410 | #define CPUID_EXT2_NX (1 << 20) |
a049de61 | 411 | #define CPUID_EXT2_MMXEXT (1 << 22) |
8d9bfc2b | 412 | #define CPUID_EXT2_FFXSR (1 << 25) |
a049de61 FB |
413 | #define CPUID_EXT2_PDPE1GB (1 << 26) |
414 | #define CPUID_EXT2_RDTSCP (1 << 27) | |
9df217a3 | 415 | #define CPUID_EXT2_LM (1 << 29) |
a049de61 FB |
416 | #define CPUID_EXT2_3DNOWEXT (1 << 30) |
417 | #define CPUID_EXT2_3DNOW (1 << 31) | |
9df217a3 | 418 | |
a049de61 FB |
419 | #define CPUID_EXT3_LAHF_LM (1 << 0) |
420 | #define CPUID_EXT3_CMP_LEG (1 << 1) | |
0573fbfc | 421 | #define CPUID_EXT3_SVM (1 << 2) |
a049de61 FB |
422 | #define CPUID_EXT3_EXTAPIC (1 << 3) |
423 | #define CPUID_EXT3_CR8LEG (1 << 4) | |
424 | #define CPUID_EXT3_ABM (1 << 5) | |
425 | #define CPUID_EXT3_SSE4A (1 << 6) | |
426 | #define CPUID_EXT3_MISALIGNSSE (1 << 7) | |
427 | #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) | |
428 | #define CPUID_EXT3_OSVW (1 << 9) | |
429 | #define CPUID_EXT3_IBS (1 << 10) | |
872929aa | 430 | #define CPUID_EXT3_SKINIT (1 << 12) |
0573fbfc | 431 | |
296acb64 JR |
432 | #define CPUID_SVM_NPT (1 << 0) |
433 | #define CPUID_SVM_LBRV (1 << 1) | |
434 | #define CPUID_SVM_SVMLOCK (1 << 2) | |
435 | #define CPUID_SVM_NRIPSAVE (1 << 3) | |
436 | #define CPUID_SVM_TSCSCALE (1 << 4) | |
437 | #define CPUID_SVM_VMCBCLEAN (1 << 5) | |
438 | #define CPUID_SVM_FLUSHASID (1 << 6) | |
439 | #define CPUID_SVM_DECODEASSIST (1 << 7) | |
440 | #define CPUID_SVM_PAUSEFILTER (1 << 10) | |
441 | #define CPUID_SVM_PFTHRESHOLD (1 << 12) | |
442 | ||
c5096daf AZ |
443 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
444 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
445 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
446 | ||
447 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
b3baa152 | 448 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
c5096daf AZ |
449 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
450 | ||
b3baa152 | 451 | #define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ |
452 | #define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ | |
453 | #define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ | |
454 | ||
e737b32a | 455 | #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
a876e289 | 456 | #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
e737b32a | 457 | |
2c0262af | 458 | #define EXCP00_DIVZ 0 |
01df040b | 459 | #define EXCP01_DB 1 |
2c0262af FB |
460 | #define EXCP02_NMI 2 |
461 | #define EXCP03_INT3 3 | |
462 | #define EXCP04_INTO 4 | |
463 | #define EXCP05_BOUND 5 | |
464 | #define EXCP06_ILLOP 6 | |
465 | #define EXCP07_PREX 7 | |
466 | #define EXCP08_DBLE 8 | |
467 | #define EXCP09_XERR 9 | |
468 | #define EXCP0A_TSS 10 | |
469 | #define EXCP0B_NOSEG 11 | |
470 | #define EXCP0C_STACK 12 | |
471 | #define EXCP0D_GPF 13 | |
472 | #define EXCP0E_PAGE 14 | |
473 | #define EXCP10_COPR 16 | |
474 | #define EXCP11_ALGN 17 | |
475 | #define EXCP12_MCHK 18 | |
476 | ||
d2fd1af7 FB |
477 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
478 | for syscall instruction */ | |
479 | ||
00a152b4 RH |
480 | /* i386-specific interrupt pending bits. */ |
481 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 | |
85097db6 | 482 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
00a152b4 RH |
483 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
484 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
485 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 | |
486 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 | |
d362e757 | 487 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 |
00a152b4 RH |
488 | |
489 | ||
2c0262af FB |
490 | enum { |
491 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
1235fc06 | 492 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
d36cd60e FB |
493 | |
494 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
495 | CC_OP_MULW, | |
496 | CC_OP_MULL, | |
14ce26e7 | 497 | CC_OP_MULQ, |
2c0262af FB |
498 | |
499 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
500 | CC_OP_ADDW, | |
501 | CC_OP_ADDL, | |
14ce26e7 | 502 | CC_OP_ADDQ, |
2c0262af FB |
503 | |
504 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
505 | CC_OP_ADCW, | |
506 | CC_OP_ADCL, | |
14ce26e7 | 507 | CC_OP_ADCQ, |
2c0262af FB |
508 | |
509 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
510 | CC_OP_SUBW, | |
511 | CC_OP_SUBL, | |
14ce26e7 | 512 | CC_OP_SUBQ, |
2c0262af FB |
513 | |
514 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
515 | CC_OP_SBBW, | |
516 | CC_OP_SBBL, | |
14ce26e7 | 517 | CC_OP_SBBQ, |
2c0262af FB |
518 | |
519 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
520 | CC_OP_LOGICW, | |
521 | CC_OP_LOGICL, | |
14ce26e7 | 522 | CC_OP_LOGICQ, |
2c0262af FB |
523 | |
524 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
525 | CC_OP_INCW, | |
526 | CC_OP_INCL, | |
14ce26e7 | 527 | CC_OP_INCQ, |
2c0262af FB |
528 | |
529 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
530 | CC_OP_DECW, | |
531 | CC_OP_DECL, | |
14ce26e7 | 532 | CC_OP_DECQ, |
2c0262af | 533 | |
6b652794 | 534 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
2c0262af FB |
535 | CC_OP_SHLW, |
536 | CC_OP_SHLL, | |
14ce26e7 | 537 | CC_OP_SHLQ, |
2c0262af FB |
538 | |
539 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
540 | CC_OP_SARW, | |
541 | CC_OP_SARL, | |
14ce26e7 | 542 | CC_OP_SARQ, |
2c0262af FB |
543 | |
544 | CC_OP_NB, | |
545 | }; | |
546 | ||
2c0262af FB |
547 | typedef struct SegmentCache { |
548 | uint32_t selector; | |
14ce26e7 | 549 | target_ulong base; |
2c0262af FB |
550 | uint32_t limit; |
551 | uint32_t flags; | |
552 | } SegmentCache; | |
553 | ||
826461bb | 554 | typedef union { |
664e0f19 FB |
555 | uint8_t _b[16]; |
556 | uint16_t _w[8]; | |
557 | uint32_t _l[4]; | |
558 | uint64_t _q[2]; | |
7a0e1f41 FB |
559 | float32 _s[4]; |
560 | float64 _d[2]; | |
14ce26e7 FB |
561 | } XMMReg; |
562 | ||
826461bb FB |
563 | typedef union { |
564 | uint8_t _b[8]; | |
a35f3ec7 AJ |
565 | uint16_t _w[4]; |
566 | uint32_t _l[2]; | |
567 | float32 _s[2]; | |
826461bb FB |
568 | uint64_t q; |
569 | } MMXReg; | |
570 | ||
e2542fe2 | 571 | #ifdef HOST_WORDS_BIGENDIAN |
826461bb FB |
572 | #define XMM_B(n) _b[15 - (n)] |
573 | #define XMM_W(n) _w[7 - (n)] | |
574 | #define XMM_L(n) _l[3 - (n)] | |
664e0f19 | 575 | #define XMM_S(n) _s[3 - (n)] |
826461bb | 576 | #define XMM_Q(n) _q[1 - (n)] |
664e0f19 | 577 | #define XMM_D(n) _d[1 - (n)] |
826461bb FB |
578 | |
579 | #define MMX_B(n) _b[7 - (n)] | |
580 | #define MMX_W(n) _w[3 - (n)] | |
581 | #define MMX_L(n) _l[1 - (n)] | |
a35f3ec7 | 582 | #define MMX_S(n) _s[1 - (n)] |
826461bb FB |
583 | #else |
584 | #define XMM_B(n) _b[n] | |
585 | #define XMM_W(n) _w[n] | |
586 | #define XMM_L(n) _l[n] | |
664e0f19 | 587 | #define XMM_S(n) _s[n] |
826461bb | 588 | #define XMM_Q(n) _q[n] |
664e0f19 | 589 | #define XMM_D(n) _d[n] |
826461bb FB |
590 | |
591 | #define MMX_B(n) _b[n] | |
592 | #define MMX_W(n) _w[n] | |
593 | #define MMX_L(n) _l[n] | |
a35f3ec7 | 594 | #define MMX_S(n) _s[n] |
826461bb | 595 | #endif |
664e0f19 | 596 | #define MMX_Q(n) q |
826461bb | 597 | |
acc68836 | 598 | typedef union { |
c31da136 | 599 | floatx80 d __attribute__((aligned(16))); |
acc68836 JQ |
600 | MMXReg mmx; |
601 | } FPReg; | |
602 | ||
c1a54d57 JQ |
603 | typedef struct { |
604 | uint64_t base; | |
605 | uint64_t mask; | |
606 | } MTRRVar; | |
607 | ||
5f30fa18 JK |
608 | #define CPU_NB_REGS64 16 |
609 | #define CPU_NB_REGS32 8 | |
610 | ||
14ce26e7 | 611 | #ifdef TARGET_X86_64 |
5f30fa18 | 612 | #define CPU_NB_REGS CPU_NB_REGS64 |
14ce26e7 | 613 | #else |
5f30fa18 | 614 | #define CPU_NB_REGS CPU_NB_REGS32 |
14ce26e7 FB |
615 | #endif |
616 | ||
6ebbf390 JM |
617 | #define NB_MMU_MODES 2 |
618 | ||
d362e757 JK |
619 | typedef enum TPRAccess { |
620 | TPR_ACCESS_READ, | |
621 | TPR_ACCESS_WRITE, | |
622 | } TPRAccess; | |
623 | ||
2c0262af FB |
624 | typedef struct CPUX86State { |
625 | /* standard registers */ | |
14ce26e7 FB |
626 | target_ulong regs[CPU_NB_REGS]; |
627 | target_ulong eip; | |
628 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
2c0262af FB |
629 | flags and DF are set to zero because they are |
630 | stored elsewhere */ | |
631 | ||
632 | /* emulator internal eflags handling */ | |
14ce26e7 FB |
633 | target_ulong cc_src; |
634 | target_ulong cc_dst; | |
2c0262af FB |
635 | uint32_t cc_op; |
636 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
db620f46 FB |
637 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
638 | are known at translation time. */ | |
639 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
2c0262af | 640 | |
9df217a3 FB |
641 | /* segments */ |
642 | SegmentCache segs[6]; /* selector values */ | |
643 | SegmentCache ldt; | |
644 | SegmentCache tr; | |
645 | SegmentCache gdt; /* only base and limit are used */ | |
646 | SegmentCache idt; /* only base and limit are used */ | |
647 | ||
db620f46 | 648 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
5ee0ffaa | 649 | int32_t a20_mask; |
9df217a3 | 650 | |
2c0262af FB |
651 | /* FPU state */ |
652 | unsigned int fpstt; /* top of stack index */ | |
67b8f419 | 653 | uint16_t fpus; |
eb831623 | 654 | uint16_t fpuc; |
2c0262af | 655 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
acc68836 | 656 | FPReg fpregs[8]; |
42cc8fa6 JK |
657 | /* KVM-only so far */ |
658 | uint16_t fpop; | |
659 | uint64_t fpip; | |
660 | uint64_t fpdp; | |
2c0262af FB |
661 | |
662 | /* emulator internal variables */ | |
7a0e1f41 | 663 | float_status fp_status; |
c31da136 | 664 | floatx80 ft0; |
3b46e624 | 665 | |
a35f3ec7 | 666 | float_status mmx_status; /* for 3DNow! float ops */ |
7a0e1f41 | 667 | float_status sse_status; |
664e0f19 | 668 | uint32_t mxcsr; |
14ce26e7 FB |
669 | XMMReg xmm_regs[CPU_NB_REGS]; |
670 | XMMReg xmm_t0; | |
664e0f19 | 671 | MMXReg mmx_t0; |
1e4840bf | 672 | target_ulong cc_tmp; /* temporary for rcr/rcl */ |
14ce26e7 | 673 | |
2c0262af FB |
674 | /* sysenter registers */ |
675 | uint32_t sysenter_cs; | |
2436b61a AZ |
676 | target_ulong sysenter_esp; |
677 | target_ulong sysenter_eip; | |
8d9bfc2b FB |
678 | uint64_t efer; |
679 | uint64_t star; | |
0573fbfc | 680 | |
5cc1d1e6 FB |
681 | uint64_t vm_hsave; |
682 | uint64_t vm_vmcb; | |
33c263df | 683 | uint64_t tsc_offset; |
0573fbfc TS |
684 | uint64_t intercept; |
685 | uint16_t intercept_cr_read; | |
686 | uint16_t intercept_cr_write; | |
687 | uint16_t intercept_dr_read; | |
688 | uint16_t intercept_dr_write; | |
689 | uint32_t intercept_exceptions; | |
db620f46 | 690 | uint8_t v_tpr; |
0573fbfc | 691 | |
14ce26e7 | 692 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
693 | target_ulong lstar; |
694 | target_ulong cstar; | |
695 | target_ulong fmask; | |
696 | target_ulong kernelgsbase; | |
697 | #endif | |
1a03675d GC |
698 | uint64_t system_time_msr; |
699 | uint64_t wall_clock_msr; | |
f6584ee2 | 700 | uint64_t async_pf_en_msr; |
58fe2f10 | 701 | |
7ba1e619 | 702 | uint64_t tsc; |
aa82ba54 | 703 | uint64_t tsc_deadline; |
7ba1e619 | 704 | |
18559232 | 705 | uint64_t mcg_status; |
21e87c46 | 706 | uint64_t msr_ia32_misc_enable; |
18559232 | 707 | |
2c0262af | 708 | /* exception/interrupt handling */ |
2c0262af FB |
709 | int error_code; |
710 | int exception_is_int; | |
826461bb | 711 | target_ulong exception_next_eip; |
14ce26e7 | 712 | target_ulong dr[8]; /* debug registers */ |
01df040b AL |
713 | union { |
714 | CPUBreakpoint *cpu_breakpoint[4]; | |
715 | CPUWatchpoint *cpu_watchpoint[4]; | |
716 | }; /* break/watchpoints for dr[0..3] */ | |
3b21e03e | 717 | uint32_t smbase; |
678dde13 | 718 | int old_exception; /* exception in flight */ |
2c0262af | 719 | |
d8f771d9 JK |
720 | /* KVM states, automatically cleared on reset */ |
721 | uint8_t nmi_injected; | |
722 | uint8_t nmi_pending; | |
723 | ||
a316d335 | 724 | CPU_COMMON |
2c0262af | 725 | |
ebda377f JK |
726 | uint64_t pat; |
727 | ||
14ce26e7 | 728 | /* processor features (e.g. for CPUID insn) */ |
8d9bfc2b | 729 | uint32_t cpuid_level; |
14ce26e7 FB |
730 | uint32_t cpuid_vendor1; |
731 | uint32_t cpuid_vendor2; | |
732 | uint32_t cpuid_vendor3; | |
733 | uint32_t cpuid_version; | |
734 | uint32_t cpuid_features; | |
9df217a3 | 735 | uint32_t cpuid_ext_features; |
8d9bfc2b FB |
736 | uint32_t cpuid_xlevel; |
737 | uint32_t cpuid_model[12]; | |
738 | uint32_t cpuid_ext2_features; | |
0573fbfc | 739 | uint32_t cpuid_ext3_features; |
eae7629b | 740 | uint32_t cpuid_apic_id; |
ef768138 | 741 | int cpuid_vendor_override; |
b3baa152 | 742 | /* Store the results of Centaur's CPUID instructions */ |
743 | uint32_t cpuid_xlevel2; | |
744 | uint32_t cpuid_ext4_features; | |
13526728 EH |
745 | /* Flags from CPUID[EAX=7,ECX=0].EBX */ |
746 | uint32_t cpuid_7_0_ebx; | |
3b46e624 | 747 | |
165d9b82 AL |
748 | /* MTRRs */ |
749 | uint64_t mtrr_fixed[11]; | |
750 | uint64_t mtrr_deftype; | |
c1a54d57 | 751 | MTRRVar mtrr_var[8]; |
165d9b82 | 752 | |
7ba1e619 | 753 | /* For KVM */ |
f8d926e9 | 754 | uint32_t mp_state; |
31827373 | 755 | int32_t exception_injected; |
0e607a80 | 756 | int32_t interrupt_injected; |
a0fb002c | 757 | uint8_t soft_interrupt; |
a0fb002c JK |
758 | uint8_t has_error_code; |
759 | uint32_t sipi_vector; | |
bb0300dc | 760 | uint32_t cpuid_kvm_features; |
296acb64 | 761 | uint32_t cpuid_svm_features; |
b8cc45d6 | 762 | bool tsc_valid; |
b862d1fe | 763 | int tsc_khz; |
fabacc0f JK |
764 | void *kvm_xsave_buf; |
765 | ||
14ce26e7 FB |
766 | /* in order to simplify APIC support, we leave this pointer to the |
767 | user */ | |
92a16d7a | 768 | struct DeviceState *apic_state; |
79c4f6b0 | 769 | |
ac6c4120 | 770 | uint64_t mcg_cap; |
ac6c4120 AF |
771 | uint64_t mcg_ctl; |
772 | uint64_t mce_banks[MCE_BANKS_DEF*4]; | |
1b050077 AP |
773 | |
774 | uint64_t tsc_aux; | |
5a2d0e57 AJ |
775 | |
776 | /* vmstate */ | |
777 | uint16_t fpus_vmstate; | |
778 | uint16_t fptag_vmstate; | |
779 | uint16_t fpregs_format_vmstate; | |
f1665b21 SY |
780 | |
781 | uint64_t xstate_bv; | |
782 | XMMReg ymmh_regs[CPU_NB_REGS]; | |
783 | ||
784 | uint64_t xcr0; | |
d362e757 JK |
785 | |
786 | TPRAccess tpr_access_type; | |
2c0262af FB |
787 | } CPUX86State; |
788 | ||
5fd2087a AF |
789 | #include "cpu-qom.h" |
790 | ||
b47ed996 | 791 | X86CPU *cpu_x86_init(const char *cpu_model); |
2c0262af | 792 | int cpu_x86_exec(CPUX86State *s); |
9a78eead | 793 | void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg); |
b5ec5ce0 | 794 | void x86_cpudef_setup(void); |
317ac620 | 795 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
b5ec5ce0 | 796 | |
d720b93d | 797 | int cpu_get_pic_interrupt(CPUX86State *s); |
2ee73ac3 FB |
798 | /* MSDOS compatibility mode FPU exception support */ |
799 | void cpu_set_ferr(CPUX86State *s); | |
2c0262af FB |
800 | |
801 | /* this function must always be used to load data in the segment | |
802 | cache: it synchronizes the hflags with the segment cache values */ | |
5fafdf24 | 803 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
2c0262af | 804 | int seg_reg, unsigned int selector, |
8988ae89 | 805 | target_ulong base, |
5fafdf24 | 806 | unsigned int limit, |
2c0262af FB |
807 | unsigned int flags) |
808 | { | |
809 | SegmentCache *sc; | |
810 | unsigned int new_hflags; | |
3b46e624 | 811 | |
2c0262af FB |
812 | sc = &env->segs[seg_reg]; |
813 | sc->selector = selector; | |
814 | sc->base = base; | |
815 | sc->limit = limit; | |
816 | sc->flags = flags; | |
817 | ||
818 | /* update the hidden flags */ | |
14ce26e7 FB |
819 | { |
820 | if (seg_reg == R_CS) { | |
821 | #ifdef TARGET_X86_64 | |
822 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
823 | /* long mode */ | |
824 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
825 | env->hflags &= ~(HF_ADDSEG_MASK); | |
5fafdf24 | 826 | } else |
14ce26e7 FB |
827 | #endif |
828 | { | |
829 | /* legacy / compatibility case */ | |
830 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
831 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
832 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
833 | new_hflags; | |
834 | } | |
835 | } | |
836 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
837 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
838 | if (env->hflags & HF_CS64_MASK) { | |
839 | /* zero base assumed for DS, ES and SS in long mode */ | |
5fafdf24 | 840 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
735a8fd3 FB |
841 | (env->eflags & VM_MASK) || |
842 | !(env->hflags & HF_CS32_MASK)) { | |
14ce26e7 FB |
843 | /* XXX: try to avoid this test. The problem comes from the |
844 | fact that is real mode or vm86 mode we only modify the | |
845 | 'base' and 'selector' fields of the segment cache to go | |
846 | faster. A solution may be to force addseg to one in | |
847 | translate-i386.c. */ | |
848 | new_hflags |= HF_ADDSEG_MASK; | |
849 | } else { | |
5fafdf24 | 850 | new_hflags |= ((env->segs[R_DS].base | |
735a8fd3 | 851 | env->segs[R_ES].base | |
5fafdf24 | 852 | env->segs[R_SS].base) != 0) << |
14ce26e7 FB |
853 | HF_ADDSEG_SHIFT; |
854 | } | |
5fafdf24 | 855 | env->hflags = (env->hflags & |
14ce26e7 | 856 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
2c0262af | 857 | } |
2c0262af FB |
858 | } |
859 | ||
0e26b7b8 BS |
860 | static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env, |
861 | int sipi_vector) | |
862 | { | |
863 | env->eip = 0; | |
864 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
865 | sipi_vector << 12, | |
866 | env->segs[R_CS].limit, | |
867 | env->segs[R_CS].flags); | |
868 | env->halted = 0; | |
869 | } | |
870 | ||
84273177 JK |
871 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
872 | target_ulong *base, unsigned int *limit, | |
873 | unsigned int *flags); | |
874 | ||
2c0262af FB |
875 | /* wrapper, just in case memory mappings must be changed */ |
876 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) | |
877 | { | |
878 | #if HF_CPL_MASK == 3 | |
879 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; | |
880 | #else | |
881 | #error HF_CPL_MASK is hardcoded | |
882 | #endif | |
883 | } | |
884 | ||
d9957a8b | 885 | /* op_helper.c */ |
1f1af9fd | 886 | /* used for debug or cpu save/restore */ |
c31da136 AJ |
887 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); |
888 | floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); | |
1f1af9fd | 889 | |
d9957a8b | 890 | /* cpu-exec.c */ |
2c0262af FB |
891 | /* the following helpers are only usable in user mode simulation as |
892 | they can trigger unexpected exceptions */ | |
893 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); | |
6f12a2a6 FB |
894 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
895 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
2c0262af FB |
896 | |
897 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
898 | signal handlers to inform the virtual CPU of exceptions. non zero | |
899 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 900 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
2c0262af | 901 | void *puc); |
d9957a8b | 902 | |
c6dc6f63 AP |
903 | /* cpuid.c */ |
904 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, | |
905 | uint32_t *eax, uint32_t *ebx, | |
906 | uint32_t *ecx, uint32_t *edx); | |
61dcd775 | 907 | int cpu_x86_register(X86CPU *cpu, const char *cpu_model); |
0e26b7b8 | 908 | void cpu_clear_apic_feature(CPUX86State *env); |
bb44e0d1 JK |
909 | void host_cpuid(uint32_t function, uint32_t count, |
910 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
c6dc6f63 | 911 | |
d9957a8b BS |
912 | /* helper.c */ |
913 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, | |
97b348e7 | 914 | int is_write, int mmu_idx); |
0b5c1ce8 | 915 | #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault |
461c0471 | 916 | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
2c0262af | 917 | |
d9957a8b BS |
918 | static inline int hw_breakpoint_enabled(unsigned long dr7, int index) |
919 | { | |
920 | return (dr7 >> (index * 2)) & 3; | |
921 | } | |
28ab0e2e | 922 | |
d9957a8b BS |
923 | static inline int hw_breakpoint_type(unsigned long dr7, int index) |
924 | { | |
d46272c7 | 925 | return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3; |
d9957a8b BS |
926 | } |
927 | ||
928 | static inline int hw_breakpoint_len(unsigned long dr7, int index) | |
929 | { | |
d46272c7 | 930 | int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3); |
d9957a8b BS |
931 | return (len == 2) ? 8 : len + 1; |
932 | } | |
933 | ||
934 | void hw_breakpoint_insert(CPUX86State *env, int index); | |
935 | void hw_breakpoint_remove(CPUX86State *env, int index); | |
936 | int check_hw_breakpoints(CPUX86State *env, int force_dr6_update); | |
937 | ||
938 | /* will be suppressed */ | |
939 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
940 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
941 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
942 | ||
d9957a8b BS |
943 | /* hw/pc.c */ |
944 | void cpu_smm_update(CPUX86State *env); | |
945 | uint64_t cpu_get_tsc(CPUX86State *env); | |
6fd805e1 | 946 | |
2c0262af FB |
947 | /* used to debug */ |
948 | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ | |
949 | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ | |
2c0262af FB |
950 | |
951 | #define TARGET_PAGE_BITS 12 | |
9467d44c | 952 | |
52705890 RH |
953 | #ifdef TARGET_X86_64 |
954 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 | |
955 | /* ??? This is really 48 bits, sign-extended, but the only thing | |
956 | accessible to userland with bit 48 set is the VSYSCALL, and that | |
957 | is handled via other mechanisms. */ | |
958 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 | |
959 | #else | |
960 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
961 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
962 | #endif | |
963 | ||
b47ed996 AF |
964 | static inline CPUX86State *cpu_init(const char *cpu_model) |
965 | { | |
966 | X86CPU *cpu = cpu_x86_init(cpu_model); | |
967 | if (cpu == NULL) { | |
968 | return NULL; | |
969 | } | |
970 | return &cpu->env; | |
971 | } | |
972 | ||
9467d44c TS |
973 | #define cpu_exec cpu_x86_exec |
974 | #define cpu_gen_code cpu_x86_gen_code | |
975 | #define cpu_signal_handler cpu_x86_signal_handler | |
b5ec5ce0 | 976 | #define cpu_list_id x86_cpu_list |
977 | #define cpudef_setup x86_cpudef_setup | |
9467d44c | 978 | |
38d2c27e | 979 | #define CPU_SAVE_VERSION 12 |
b3c7724c | 980 | |
6ebbf390 JM |
981 | /* MMU modes definitions */ |
982 | #define MMU_MODE0_SUFFIX _kernel | |
983 | #define MMU_MODE1_SUFFIX _user | |
984 | #define MMU_USER_IDX 1 | |
317ac620 | 985 | static inline int cpu_mmu_index (CPUX86State *env) |
6ebbf390 JM |
986 | { |
987 | return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; | |
988 | } | |
989 | ||
f081c76c BS |
990 | #undef EAX |
991 | #define EAX (env->regs[R_EAX]) | |
992 | #undef ECX | |
993 | #define ECX (env->regs[R_ECX]) | |
994 | #undef EDX | |
995 | #define EDX (env->regs[R_EDX]) | |
996 | #undef EBX | |
997 | #define EBX (env->regs[R_EBX]) | |
998 | #undef ESP | |
999 | #define ESP (env->regs[R_ESP]) | |
1000 | #undef EBP | |
1001 | #define EBP (env->regs[R_EBP]) | |
1002 | #undef ESI | |
1003 | #define ESI (env->regs[R_ESI]) | |
1004 | #undef EDI | |
1005 | #define EDI (env->regs[R_EDI]) | |
1006 | #undef EIP | |
1007 | #define EIP (env->eip) | |
1008 | #define DF (env->df) | |
1009 | ||
1010 | #define CC_SRC (env->cc_src) | |
1011 | #define CC_DST (env->cc_dst) | |
1012 | #define CC_OP (env->cc_op) | |
1013 | ||
5918fffb BS |
1014 | /* n must be a constant to be efficient */ |
1015 | static inline target_long lshift(target_long x, int n) | |
1016 | { | |
1017 | if (n >= 0) { | |
1018 | return x << n; | |
1019 | } else { | |
1020 | return x >> (-n); | |
1021 | } | |
1022 | } | |
1023 | ||
f081c76c BS |
1024 | /* float macros */ |
1025 | #define FT0 (env->ft0) | |
1026 | #define ST0 (env->fpregs[env->fpstt].d) | |
1027 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
1028 | #define ST1 ST(1) | |
1029 | ||
d9957a8b | 1030 | /* translate.c */ |
26a5f13b FB |
1031 | void optimize_flags_init(void); |
1032 | ||
6e68e076 | 1033 | #if defined(CONFIG_USER_ONLY) |
317ac620 | 1034 | static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) |
6e68e076 | 1035 | { |
f8ed7070 | 1036 | if (newsp) |
6e68e076 PB |
1037 | env->regs[R_ESP] = newsp; |
1038 | env->regs[R_EAX] = 0; | |
1039 | } | |
1040 | #endif | |
1041 | ||
2c0262af | 1042 | #include "cpu-all.h" |
0573fbfc TS |
1043 | #include "svm.h" |
1044 | ||
0e26b7b8 BS |
1045 | #if !defined(CONFIG_USER_ONLY) |
1046 | #include "hw/apic.h" | |
1047 | #endif | |
1048 | ||
317ac620 | 1049 | static inline bool cpu_has_work(CPUX86State *env) |
f081c76c BS |
1050 | { |
1051 | return ((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1052 | (env->eflags & IF_MASK)) || | |
1053 | (env->interrupt_request & (CPU_INTERRUPT_NMI | | |
1054 | CPU_INTERRUPT_INIT | | |
1055 | CPU_INTERRUPT_SIPI | | |
1056 | CPU_INTERRUPT_MCE)); | |
1057 | } | |
1058 | ||
1059 | #include "exec-all.h" | |
1060 | ||
317ac620 | 1061 | static inline void cpu_pc_from_tb(CPUX86State *env, TranslationBlock *tb) |
f081c76c BS |
1062 | { |
1063 | env->eip = tb->pc - tb->cs_base; | |
1064 | } | |
1065 | ||
317ac620 | 1066 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
6b917547 AL |
1067 | target_ulong *cs_base, int *flags) |
1068 | { | |
1069 | *cs_base = env->segs[R_CS].base; | |
1070 | *pc = *cs_base + env->eip; | |
a2397807 JK |
1071 | *flags = env->hflags | |
1072 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); | |
6b917547 AL |
1073 | } |
1074 | ||
232fc23b AF |
1075 | void do_cpu_init(X86CPU *cpu); |
1076 | void do_cpu_sipi(X86CPU *cpu); | |
2fa11da0 | 1077 | |
747461c7 JK |
1078 | #define MCE_INJECT_BROADCAST 1 |
1079 | #define MCE_INJECT_UNCOND_AO 2 | |
1080 | ||
317ac620 | 1081 | void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank, |
316378e4 | 1082 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
747461c7 | 1083 | uint64_t misc, int flags); |
2fa11da0 | 1084 | |
599b9a5a | 1085 | /* excp_helper.c */ |
77b2bc2c BS |
1086 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
1087 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, | |
1088 | int error_code); | |
599b9a5a BS |
1089 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
1090 | int error_code, int next_eip_addend); | |
1091 | ||
5918fffb BS |
1092 | /* cc_helper.c */ |
1093 | extern const uint8_t parity_table[256]; | |
1094 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); | |
1095 | ||
1096 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
1097 | { | |
1098 | return env->eflags | cpu_cc_compute_all(env, CC_OP) | (DF & DF_MASK); | |
1099 | } | |
1100 | ||
1101 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ | |
1102 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, | |
1103 | int update_mask) | |
1104 | { | |
1105 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
1106 | DF = 1 - (2 * ((eflags >> 10) & 1)); | |
1107 | env->eflags = (env->eflags & ~update_mask) | | |
1108 | (eflags & update_mask) | 0x2; | |
1109 | } | |
1110 | ||
1111 | /* load efer and update the corresponding hflags. XXX: do consistency | |
1112 | checks with cpuid bits? */ | |
1113 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) | |
1114 | { | |
1115 | env->efer = val; | |
1116 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
1117 | if (env->efer & MSR_EFER_LMA) { | |
1118 | env->hflags |= HF_LMA_MASK; | |
1119 | } | |
1120 | if (env->efer & MSR_EFER_SVME) { | |
1121 | env->hflags |= HF_SVME_MASK; | |
1122 | } | |
1123 | } | |
1124 | ||
6bada5e8 BS |
1125 | /* svm_helper.c */ |
1126 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
1127 | uint64_t param); | |
1128 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1); | |
1129 | ||
599b9a5a BS |
1130 | /* op_helper.c */ |
1131 | void do_interrupt(CPUX86State *env); | |
1132 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); | |
e694d4e2 | 1133 | |
317ac620 | 1134 | void do_smm_enter(CPUX86State *env1); |
e694d4e2 | 1135 | |
317ac620 | 1136 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
d362e757 | 1137 | |
2c0262af | 1138 | #endif /* CPU_I386_H */ |