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Commit | Line | Data |
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2c0262af | 1 | /* |
5fafdf24 | 2 | * i386 execution defines |
2c0262af FB |
3 | * |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 18 | */ |
7d3505c5 | 19 | #include "config.h" |
2c0262af FB |
20 | #include "dyngen-exec.h" |
21 | ||
14ce26e7 | 22 | /* XXX: factorize this mess */ |
14ce26e7 FB |
23 | #ifdef TARGET_X86_64 |
24 | #define TARGET_LONG_BITS 64 | |
25 | #else | |
26 | #define TARGET_LONG_BITS 32 | |
27 | #endif | |
28 | ||
d785e6be FB |
29 | #include "cpu-defs.h" |
30 | ||
2c0262af | 31 | register struct CPUX86State *env asm(AREG0); |
14ce26e7 | 32 | |
7d99a001 | 33 | #include "qemu-common.h" |
79383c9c | 34 | #include "qemu-log.h" |
2c0262af | 35 | |
aba1d00a | 36 | #undef EAX |
2c0262af | 37 | #define EAX (env->regs[R_EAX]) |
aba1d00a | 38 | #undef ECX |
2c0262af | 39 | #define ECX (env->regs[R_ECX]) |
aba1d00a | 40 | #undef EDX |
2c0262af | 41 | #define EDX (env->regs[R_EDX]) |
aba1d00a | 42 | #undef EBX |
2c0262af | 43 | #define EBX (env->regs[R_EBX]) |
aba1d00a | 44 | #undef ESP |
2c0262af | 45 | #define ESP (env->regs[R_ESP]) |
aba1d00a | 46 | #undef EBP |
2c0262af | 47 | #define EBP (env->regs[R_EBP]) |
aba1d00a | 48 | #undef ESI |
2c0262af | 49 | #define ESI (env->regs[R_ESI]) |
aba1d00a | 50 | #undef EDI |
2c0262af | 51 | #define EDI (env->regs[R_EDI]) |
aba1d00a | 52 | #undef EIP |
1e4840bf | 53 | #define EIP (env->eip) |
2c0262af FB |
54 | #define DF (env->df) |
55 | ||
56 | #define CC_SRC (env->cc_src) | |
57 | #define CC_DST (env->cc_dst) | |
58 | #define CC_OP (env->cc_op) | |
59 | ||
60 | /* float macros */ | |
61 | #define FT0 (env->ft0) | |
664e0f19 FB |
62 | #define ST0 (env->fpregs[env->fpstt].d) |
63 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
2c0262af FB |
64 | #define ST1 ST(1) |
65 | ||
2c0262af FB |
66 | #include "cpu.h" |
67 | #include "exec-all.h" | |
68 | ||
d9957a8b | 69 | /* op_helper.c */ |
5fafdf24 | 70 | void do_interrupt(int intno, int is_int, int error_code, |
14ce26e7 | 71 | target_ulong next_eip, int is_hw); |
5fafdf24 | 72 | void do_interrupt_user(int intno, int is_int, int error_code, |
14ce26e7 | 73 | target_ulong next_eip); |
a5e50b26 | 74 | void QEMU_NORETURN raise_exception_err(int exception_index, int error_code); |
75 | void QEMU_NORETURN raise_exception(int exception_index); | |
63a54736 | 76 | void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv); |
3b21e03e | 77 | void do_smm_enter(void); |
2c0262af | 78 | |
b6abf97d FB |
79 | /* n must be a constant to be efficient */ |
80 | static inline target_long lshift(target_long x, int n) | |
81 | { | |
82 | if (n >= 0) | |
83 | return x << n; | |
84 | else | |
85 | return x >> (-n); | |
86 | } | |
87 | ||
57fec1fe FB |
88 | #include "helper.h" |
89 | ||
b8b6a50b FB |
90 | static inline void svm_check_intercept(uint32_t type) |
91 | { | |
92 | helper_svm_check_intercept_param(type, 0); | |
93 | } | |
3e25f951 | 94 | |
9951bf39 FB |
95 | #if !defined(CONFIG_USER_ONLY) |
96 | ||
a9049a07 | 97 | #include "softmmu_exec.h" |
9951bf39 | 98 | |
9951bf39 FB |
99 | #endif /* !defined(CONFIG_USER_ONLY) */ |
100 | ||
2c0262af FB |
101 | #define RC_MASK 0xc00 |
102 | #define RC_NEAR 0x000 | |
103 | #define RC_DOWN 0x400 | |
104 | #define RC_UP 0x800 | |
105 | #define RC_CHOP 0xc00 | |
106 | ||
107 | #define MAXTAN 9223372036854775808.0 | |
108 | ||
2c0262af FB |
109 | /* the following deal with x86 long double-precision numbers */ |
110 | #define MAXEXPD 0x7fff | |
111 | #define EXPBIAS 16383 | |
112 | #define EXPD(fp) (fp.l.upper & 0x7fff) | |
113 | #define SIGND(fp) ((fp.l.upper) & 0x8000) | |
114 | #define MANTD(fp) (fp.l.lower) | |
115 | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS | |
116 | ||
2c0262af FB |
117 | static inline void fpush(void) |
118 | { | |
119 | env->fpstt = (env->fpstt - 1) & 7; | |
120 | env->fptags[env->fpstt] = 0; /* validate stack entry */ | |
121 | } | |
122 | ||
123 | static inline void fpop(void) | |
124 | { | |
125 | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ | |
126 | env->fpstt = (env->fpstt + 1) & 7; | |
127 | } | |
128 | ||
c31da136 | 129 | static inline floatx80 helper_fldt(target_ulong ptr) |
2c0262af | 130 | { |
c31da136 | 131 | CPU_LDoubleU temp; |
9951bf39 FB |
132 | |
133 | temp.l.lower = ldq(ptr); | |
134 | temp.l.upper = lduw(ptr + 8); | |
135 | return temp.d; | |
136 | } | |
137 | ||
c31da136 | 138 | static inline void helper_fstt(floatx80 f, target_ulong ptr) |
9951bf39 | 139 | { |
c31da136 | 140 | CPU_LDoubleU temp; |
3b46e624 | 141 | |
9951bf39 FB |
142 | temp.d = f; |
143 | stq(ptr, temp.l.lower); | |
144 | stw(ptr + 8, temp.l.upper); | |
145 | } | |
146 | ||
2ee73ac3 FB |
147 | #define FPUS_IE (1 << 0) |
148 | #define FPUS_DE (1 << 1) | |
149 | #define FPUS_ZE (1 << 2) | |
150 | #define FPUS_OE (1 << 3) | |
151 | #define FPUS_UE (1 << 4) | |
152 | #define FPUS_PE (1 << 5) | |
153 | #define FPUS_SF (1 << 6) | |
154 | #define FPUS_SE (1 << 7) | |
155 | #define FPUS_B (1 << 15) | |
156 | ||
157 | #define FPUC_EM 0x3f | |
158 | ||
2c0262af FB |
159 | static inline uint32_t compute_eflags(void) |
160 | { | |
a7812ae4 | 161 | return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
2c0262af FB |
162 | } |
163 | ||
2c0262af FB |
164 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ |
165 | static inline void load_eflags(int eflags, int update_mask) | |
166 | { | |
167 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
168 | DF = 1 - (2 * ((eflags >> 10) & 1)); | |
5fafdf24 | 169 | env->eflags = (env->eflags & ~update_mask) | |
093f8f06 | 170 | (eflags & update_mask) | 0x2; |
2c0262af FB |
171 | } |
172 | ||
6a4955a8 AL |
173 | static inline int cpu_has_work(CPUState *env) |
174 | { | |
ac098781 JK |
175 | return ((env->interrupt_request & CPU_INTERRUPT_HARD) && |
176 | (env->eflags & IF_MASK)) || | |
177 | (env->interrupt_request & (CPU_INTERRUPT_NMI | | |
178 | CPU_INTERRUPT_INIT | | |
179 | CPU_INTERRUPT_SIPI | | |
180 | CPU_INTERRUPT_MCE)); | |
6a4955a8 AL |
181 | } |
182 | ||
5efc27bb FB |
183 | /* load efer and update the corresponding hflags. XXX: do consistency |
184 | checks with cpuid bits ? */ | |
185 | static inline void cpu_load_efer(CPUState *env, uint64_t val) | |
186 | { | |
187 | env->efer = val; | |
188 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
189 | if (env->efer & MSR_EFER_LMA) | |
190 | env->hflags |= HF_LMA_MASK; | |
191 | if (env->efer & MSR_EFER_SVME) | |
192 | env->hflags |= HF_SVME_MASK; | |
193 | } | |
10eb0cc0 PB |
194 | |
195 | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) | |
196 | { | |
197 | env->eip = tb->pc - tb->cs_base; | |
198 | } | |
199 |