]> git.proxmox.com Git - qemu.git/blame - target-i386/helper.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Introduce BP_CPU as a breakpoint type (Jan Kiszka)
[qemu.git] / target-i386 / helper.c
CommitLineData
2c0262af 1/*
eaa728ee 2 * i386 helpers (without register variable usage)
5fafdf24 3 *
2c0262af
FB		 4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
eaa728ee
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
2c0262af 27
eaa728ee
FB		 28#include "cpu.h"
29#include "exec-all.h"
30#include "svm.h"
31#include "qemu-common.h"
7ba1e619 32#include "kvm.h"
a7812ae4 33#include "helper.h"
f3f2d9be 34
eaa728ee 35//#define DEBUG_MMU
2c0262af 36
eaa728ee 37static int cpu_x86_register (CPUX86State *env, const char *cpu_model);
2c0262af 38
eaa728ee
FB		 39static void add_flagname_to_bitmaps(char *flagname, uint32_t *features,
40 uint32_t *ext_features,
41 uint32_t *ext2_features,
42 uint32_t *ext3_features)
43{
44 int i;
45 /* feature flags taken from "Intel Processor Identification and the CPUID
46 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
47 * about feature names, the Linux name is used. */
40f8e2fa 48 static const char *feature_name[] = {
eaa728ee
FB		 49 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
50 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
51 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, NULL, "ds" /* Intel dts */, "acpi", "mmx",
52 "fxsr", "sse", "sse2", "ss", "ht" /* Intel htt */, "tm", "ia64", "pbe",
53 };
40f8e2fa 54 static const char *ext_feature_name[] = {
eaa728ee
FB		 55 "pni" /* Intel,AMD sse3 */, NULL, NULL, "monitor", "ds_cpl", "vmx", NULL /* Linux smx */, "est",
56 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
57 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
58 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
59 };
40f8e2fa 60 static const char *ext2_feature_name[] = {
eaa728ee
FB		 61 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
62 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", "mttr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL, NULL /* Linux mp */, "nx" /* Intel xd */, NULL, "mmxext", "mmx",
64 "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp", NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
65 };
40f8e2fa 66 static const char *ext3_feature_name[] = {
eaa728ee
FB		 67 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
68 "3dnowprefetch", "osvw", NULL /* Linux ibs */, NULL, "skinit", "wdt", NULL, NULL,
69 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
70 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
71 };
72
73 for ( i = 0 ; i < 32 ; i++ )
74 if (feature_name[i] && !strcmp (flagname, feature_name[i])) {
75 *features |= 1 << i;
76 return;
77 }
78 for ( i = 0 ; i < 32 ; i++ )
79 if (ext_feature_name[i] && !strcmp (flagname, ext_feature_name[i])) {
80 *ext_features |= 1 << i;
81 return;
82 }
83 for ( i = 0 ; i < 32 ; i++ )
84 if (ext2_feature_name[i] && !strcmp (flagname, ext2_feature_name[i])) {
85 *ext2_features |= 1 << i;
86 return;
87 }
88 for ( i = 0 ; i < 32 ; i++ )
89 if (ext3_feature_name[i] && !strcmp (flagname, ext3_feature_name[i])) {
90 *ext3_features |= 1 << i;
91 return;
92 }
93 fprintf(stderr, "CPU feature %s not found\n", flagname);
94}
2c0262af 95
eaa728ee 96CPUX86State *cpu_x86_init(const char *cpu_model)
2c0262af 97{
eaa728ee
FB		 98 CPUX86State *env;
99 static int inited;
3b46e624 100
eaa728ee
FB		 101 env = qemu_mallocz(sizeof(CPUX86State));
102 if (!env)
103 return NULL;
104 cpu_exec_init(env);
105 env->cpu_model_str = cpu_model;
2c0262af 106
eaa728ee
FB		 107 /* init various static tables */
108 if (!inited) {
109 inited = 1;
110 optimize_flags_init();
111 }
112 if (cpu_x86_register(env, cpu_model) < 0) {
113 cpu_x86_close(env);
114 return NULL;
115 }
116 cpu_reset(env);
117#ifdef USE_KQEMU
118 kqemu_init(env);
119#endif
7ba1e619
AL		 120 if (kvm_enabled())
121 kvm_init_vcpu(env);
eaa728ee
FB		 122 return env;
123}
124
125typedef struct x86_def_t {
126 const char *name;
127 uint32_t level;
128 uint32_t vendor1, vendor2, vendor3;
129 int family;
130 int model;
131 int stepping;
132 uint32_t features, ext_features, ext2_features, ext3_features;
133 uint32_t xlevel;
40f8e2fa 134 char model_id[48];
eaa728ee
FB		 135} x86_def_t;
136
137#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
138#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
139 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX)
140#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
141 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
142 CPUID_PSE36 | CPUID_FXSR)
143#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
144#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
145 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
146 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
147 CPUID_PAE | CPUID_SEP | CPUID_APIC)
148static x86_def_t x86_defs[] = {
149#ifdef TARGET_X86_64
150 {
151 .name = "qemu64",
152 .level = 2,
c5096daf
AZ		 153 .vendor1 = CPUID_VENDOR_AMD_1,
154 .vendor2 = CPUID_VENDOR_AMD_2,
155 .vendor3 = CPUID_VENDOR_AMD_3,
eaa728ee
FB		 156 .family = 6,
157 .model = 2,
158 .stepping = 3,
159 .features = PPRO_FEATURES |
160 /* these features are needed for Win64 and aren't fully implemented */
161 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
162 /* this feature is needed for Solaris and isn't fully implemented */
163 CPUID_PSE36,
164 .ext_features = CPUID_EXT_SSE3,
165 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
166 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
167 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
168 .ext3_features = CPUID_EXT3_SVM,
169 .xlevel = 0x8000000A,
40f8e2fa 170 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
eaa728ee 171 },
e737b32a
AZ		 172 {
173 .name = "core2duo",
558fa836 174 .level = 10,
e737b32a
AZ		 175 .family = 6,
176 .model = 15,
177 .stepping = 11,
558fa836
PB		 178 /* The original CPU also implements these features:
179 CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
180 CPUID_TM, CPUID_PBE */
0086de1c 181 .features = PPRO_FEATURES |
e737b32a
AZ		 182 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
183 CPUID_PSE36,
558fa836
PB		 184 /* The original CPU also implements these ext features:
185 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
186 CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
0086de1c 187 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3,
558fa836
PB		 188 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
189 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
45fd08ef 190 .xlevel = 0x80000008,
e737b32a
AZ		 191 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
192 },
eaa728ee
FB		 193#endif
194 {
195 .name = "qemu32",
196 .level = 2,
197 .family = 6,
198 .model = 3,
199 .stepping = 3,
200 .features = PPRO_FEATURES,
201 .ext_features = CPUID_EXT_SSE3,
202 .xlevel = 0,
40f8e2fa 203 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
eaa728ee 204 },
45fd08ef
AJ		 205 {
206 .name = "coreduo",
207 .level = 10,
208 .family = 6,
209 .model = 14,
210 .stepping = 8,
211 /* The original CPU also implements these features:
212 CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
213 CPUID_TM, CPUID_PBE */
214 .features = PPRO_FEATURES | CPUID_VME |
215 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA,
216 /* The original CPU also implements these ext features:
217 CPUID_EXT_VMX, CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_XTPR,
218 CPUID_EXT_PDCM */
219 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
220 .ext2_features = CPUID_EXT2_NX,
221 .xlevel = 0x80000008,
222 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
223 },
eaa728ee
FB		 224 {
225 .name = "486",
226 .level = 0,
227 .family = 4,
228 .model = 0,
229 .stepping = 0,
230 .features = I486_FEATURES,
231 .xlevel = 0,
232 },
233 {
234 .name = "pentium",
235 .level = 1,
236 .family = 5,
237 .model = 4,
238 .stepping = 3,
239 .features = PENTIUM_FEATURES,
240 .xlevel = 0,
241 },
242 {
243 .name = "pentium2",
244 .level = 2,
245 .family = 6,
246 .model = 5,
247 .stepping = 2,
248 .features = PENTIUM2_FEATURES,
249 .xlevel = 0,
250 },
251 {
252 .name = "pentium3",
253 .level = 2,
254 .family = 6,
255 .model = 7,
256 .stepping = 3,
257 .features = PENTIUM3_FEATURES,
258 .xlevel = 0,
259 },
260 {
261 .name = "athlon",
262 .level = 2,
263 .vendor1 = 0x68747541, /* "Auth" */
264 .vendor2 = 0x69746e65, /* "enti" */
265 .vendor3 = 0x444d4163, /* "cAMD" */
266 .family = 6,
267 .model = 2,
268 .stepping = 3,
558fa836 269 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
eaa728ee
FB		 270 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
271 .xlevel = 0x80000008,
40f8e2fa
FB		 272 /* XXX: put another string ? */
273 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
eaa728ee 274 },
0086de1c 275 {
c0d82995 276 .name = "n270",
0086de1c
AZ		 277 /* original is on level 10 */
278 .level = 5,
279 .family = 6,
280 .model = 28,
281 .stepping = 2,
282 .features = PPRO_FEATURES |
283 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME,
284 /* Missing: CPUID_DTS | CPUID_ACPI | CPUID_SS |
285 * CPUID_HT | CPUID_TM | CPUID_PBE */
286 /* Some CPUs got no CPUID_SEP */
287 .ext_features = CPUID_EXT_MONITOR |
853f6931 288 CPUID_EXT_SSE3 /* PNI */ | CPUID_EXT_SSSE3,
0086de1c
AZ		 289 /* Missing: CPUID_EXT_DSCPL | CPUID_EXT_EST |
290 * CPUID_EXT_TM2 | CPUID_EXT_XTPR */
291 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_NX,
292 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
293 .xlevel = 0x8000000A,
294 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
295 },
eaa728ee 296};
2c0262af 297
eaa728ee 298static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
2c0262af 299{
eaa728ee
FB		 300 unsigned int i;
301 x86_def_t *def;
2c0262af 302
eaa728ee
FB		 303 char *s = strdup(cpu_model);
304 char *featurestr, *name = strtok(s, ",");
305 uint32_t plus_features = 0, plus_ext_features = 0, plus_ext2_features = 0, plus_ext3_features = 0;
306 uint32_t minus_features = 0, minus_ext_features = 0, minus_ext2_features = 0, minus_ext3_features = 0;
307 int family = -1, model = -1, stepping = -1;
2c0262af 308
eaa728ee
FB		 309 def = NULL;
310 for (i = 0; i < sizeof(x86_defs) / sizeof(x86_def_t); i++) {
311 if (strcmp(name, x86_defs[i].name) == 0) {
312 def = &x86_defs[i];
313 break;
314 }
315 }
316 if (!def)
317 goto error;
318 memcpy(x86_cpu_def, def, sizeof(*def));
319
320 featurestr = strtok(NULL, ",");
321
322 while (featurestr) {
323 char *val;
324 if (featurestr[0] == '+') {
325 add_flagname_to_bitmaps(featurestr + 1, &plus_features, &plus_ext_features, &plus_ext2_features, &plus_ext3_features);
326 } else if (featurestr[0] == '-') {
327 add_flagname_to_bitmaps(featurestr + 1, &minus_features, &minus_ext_features, &minus_ext2_features, &minus_ext3_features);
328 } else if ((val = strchr(featurestr, '='))) {
329 *val = 0; val++;
330 if (!strcmp(featurestr, "family")) {
331 char *err;
332 family = strtol(val, &err, 10);
333 if (!*val || *err || family < 0) {
334 fprintf(stderr, "bad numerical value %s\n", val);
eaa728ee
FB		 335 goto error;
336 }
337 x86_cpu_def->family = family;
338 } else if (!strcmp(featurestr, "model")) {
339 char *err;
340 model = strtol(val, &err, 10);
59795a1f 341 if (!*val || *err || model < 0 || model > 0xff) {
eaa728ee 342 fprintf(stderr, "bad numerical value %s\n", val);
eaa728ee
FB		 343 goto error;
344 }
345 x86_cpu_def->model = model;
346 } else if (!strcmp(featurestr, "stepping")) {
347 char *err;
348 stepping = strtol(val, &err, 10);
349 if (!*val || *err || stepping < 0 || stepping > 0xf) {
350 fprintf(stderr, "bad numerical value %s\n", val);
eaa728ee
FB		 351 goto error;
352 }
353 x86_cpu_def->stepping = stepping;
40f8e2fa
FB		 354 } else if (!strcmp(featurestr, "vendor")) {
355 if (strlen(val) != 12) {
356 fprintf(stderr, "vendor string must be 12 chars long\n");
357 goto error;
358 }
359 x86_cpu_def->vendor1 = 0;
360 x86_cpu_def->vendor2 = 0;
361 x86_cpu_def->vendor3 = 0;
362 for(i = 0; i < 4; i++) {
363 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
364 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
365 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
366 }
367 } else if (!strcmp(featurestr, "model_id")) {
368 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
369 val);
eaa728ee
FB		 370 } else {
371 fprintf(stderr, "unrecognized feature %s\n", featurestr);
eaa728ee
FB		 372 goto error;
373 }
374 } else {
375 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
eaa728ee
FB		 376 goto error;
377 }
378 featurestr = strtok(NULL, ",");
379 }
380 x86_cpu_def->features |= plus_features;
381 x86_cpu_def->ext_features |= plus_ext_features;
382 x86_cpu_def->ext2_features |= plus_ext2_features;
383 x86_cpu_def->ext3_features |= plus_ext3_features;
384 x86_cpu_def->features &= ~minus_features;
385 x86_cpu_def->ext_features &= ~minus_ext_features;
386 x86_cpu_def->ext2_features &= ~minus_ext2_features;
387 x86_cpu_def->ext3_features &= ~minus_ext3_features;
388 free(s);
389 return 0;
390
391error:
392 free(s);
393 return -1;
bd7a7b33
FB		 394}
395
eaa728ee 396void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
bd7a7b33 397{
eaa728ee
FB		 398 unsigned int i;
399
400 for (i = 0; i < sizeof(x86_defs) / sizeof(x86_def_t); i++)
401 (*cpu_fprintf)(f, "x86 %16s\n", x86_defs[i].name);
bd7a7b33
FB		 402}
403
eaa728ee 404static int cpu_x86_register (CPUX86State *env, const char *cpu_model)
7e84c249 405{
eaa728ee 406 x86_def_t def1, *def = &def1;
7e84c249 407
eaa728ee 408 if (cpu_x86_find_by_name(def, cpu_model) < 0)
7e84c249 409 return -1;
eaa728ee
FB		 410 if (def->vendor1) {
411 env->cpuid_vendor1 = def->vendor1;
412 env->cpuid_vendor2 = def->vendor2;
413 env->cpuid_vendor3 = def->vendor3;
414 } else {
c5096daf
AZ		 415 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
416 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
417 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
eaa728ee
FB		 418 }
419 env->cpuid_level = def->level;
59795a1f
AZ		 420 if (def->family > 0x0f)
421 env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20);
422 else
423 env->cpuid_version = def->family << 8;
424 env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16);
425 env->cpuid_version |= def->stepping;
eaa728ee
FB		 426 env->cpuid_features = def->features;
427 env->pat = 0x0007040600070406ULL;
428 env->cpuid_ext_features = def->ext_features;
429 env->cpuid_ext2_features = def->ext2_features;
430 env->cpuid_xlevel = def->xlevel;
431 env->cpuid_ext3_features = def->ext3_features;
432 {
40f8e2fa 433 const char *model_id = def->model_id;
eaa728ee 434 int c, len, i;
40f8e2fa
FB		 435 if (!model_id)
436 model_id = "";
eaa728ee
FB		 437 len = strlen(model_id);
438 for(i = 0; i < 48; i++) {
439 if (i >= len)
440 c = '\0';
441 else
40f8e2fa 442 c = (uint8_t)model_id[i];
eaa728ee
FB		 443 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
444 }
445 }
7e84c249
FB		 446 return 0;
447}
3b46e624 448
eaa728ee
FB		 449/* NOTE: must be called outside the CPU execute loop */
450void cpu_reset(CPUX86State *env)
7e84c249 451{
eaa728ee 452 int i;
7e84c249 453
eaa728ee 454 memset(env, 0, offsetof(CPUX86State, breakpoints));
7e84c249 455
eaa728ee 456 tlb_flush(env, 1);
7e84c249 457
eaa728ee 458 env->old_exception = -1;
7e84c249 459
eaa728ee 460 /* init to reset state */
3b46e624 461
eaa728ee
FB		 462#ifdef CONFIG_SOFTMMU
463 env->hflags |= HF_SOFTMMU_MASK;
2c0262af 464#endif
db620f46 465 env->hflags2 |= HF2_GIF_MASK;
2c0262af 466
eaa728ee
FB		 467 cpu_x86_update_cr0(env, 0x60000010);
468 env->a20_mask = ~0x0;
469 env->smbase = 0x30000;
7e84c249 470
eaa728ee
FB		 471 env->idt.limit = 0xffff;
472 env->gdt.limit = 0xffff;
473 env->ldt.limit = 0xffff;
262ffdae 474 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
eaa728ee 475 env->tr.limit = 0xffff;
23e6c399 476 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
262ffdae
FB		 477
478 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
479 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
480 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
481 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
482 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
483 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
484 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
485 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
486 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
487 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
488 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
489 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
7e84c249 490
eaa728ee
FB		 491 env->eip = 0xfff0;
492 env->regs[R_EDX] = env->cpuid_version;
2c0262af 493
eaa728ee 494 env->eflags = 0x2;
7e84c249 495
eaa728ee
FB		 496 /* FPU init */
497 for(i = 0;i < 8; i++)
498 env->fptags[i] = 1;
499 env->fpuc = 0x37f;
7e84c249 500
eaa728ee
FB		 501 env->mxcsr = 0x1f80;
502}
7e84c249 503
eaa728ee
FB		 504void cpu_x86_close(CPUX86State *env)
505{
bb332cb2 506 qemu_free(env);
eaa728ee 507}
7e84c249 508
eaa728ee
FB		 509/***********************************************************/
510/* x86 debug */
3b46e624 511
eaa728ee
FB		 512static const char *cc_op_str[] = {
513 "DYNAMIC",
514 "EFLAGS",
7e84c249 515
eaa728ee
FB		 516 "MULB",
517 "MULW",
518 "MULL",
519 "MULQ",
3b46e624 520
eaa728ee
FB		 521 "ADDB",
522 "ADDW",
523 "ADDL",
524 "ADDQ",
3b46e624 525
eaa728ee
FB		 526 "ADCB",
527 "ADCW",
528 "ADCL",
529 "ADCQ",
3b46e624 530
eaa728ee
FB		 531 "SUBB",
532 "SUBW",
533 "SUBL",
534 "SUBQ",
7e84c249 535
eaa728ee
FB		 536 "SBBB",
537 "SBBW",
538 "SBBL",
539 "SBBQ",
7e84c249 540
eaa728ee
FB		 541 "LOGICB",
542 "LOGICW",
543 "LOGICL",
544 "LOGICQ",
7e84c249 545
eaa728ee
FB		 546 "INCB",
547 "INCW",
548 "INCL",
549 "INCQ",
3b46e624 550
eaa728ee
FB		 551 "DECB",
552 "DECW",
553 "DECL",
554 "DECQ",
3b46e624 555
eaa728ee
FB		 556 "SHLB",
557 "SHLW",
558 "SHLL",
559 "SHLQ",
3b46e624 560
eaa728ee
FB		 561 "SARB",
562 "SARW",
563 "SARL",
564 "SARQ",
565};
7e84c249 566
eaa728ee
FB		 567void cpu_dump_state(CPUState *env, FILE *f,
568 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
569 int flags)
570{
571 int eflags, i, nb;
572 char cc_op_name[32];
573 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
7e84c249 574
eaa728ee
FB		 575 eflags = env->eflags;
576#ifdef TARGET_X86_64
577 if (env->hflags & HF_CS64_MASK) {
578 cpu_fprintf(f,
579 "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
580 "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
581 "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
582 "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
583 "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
584 env->regs[R_EAX],
585 env->regs[R_EBX],
586 env->regs[R_ECX],
587 env->regs[R_EDX],
588 env->regs[R_ESI],
589 env->regs[R_EDI],
590 env->regs[R_EBP],
591 env->regs[R_ESP],
592 env->regs[8],
593 env->regs[9],
594 env->regs[10],
595 env->regs[11],
596 env->regs[12],
597 env->regs[13],
598 env->regs[14],
599 env->regs[15],
600 env->eip, eflags,
601 eflags & DF_MASK ? 'D' : '-',
602 eflags & CC_O ? 'O' : '-',
603 eflags & CC_S ? 'S' : '-',
604 eflags & CC_Z ? 'Z' : '-',
605 eflags & CC_A ? 'A' : '-',
606 eflags & CC_P ? 'P' : '-',
607 eflags & CC_C ? 'C' : '-',
608 env->hflags & HF_CPL_MASK,
609 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
610 (int)(env->a20_mask >> 20) & 1,
611 (env->hflags >> HF_SMM_SHIFT) & 1,
ce5232c5 612 env->halted);
eaa728ee
FB		 613 } else
614#endif
615 {
616 cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
617 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
618 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
619 (uint32_t)env->regs[R_EAX],
620 (uint32_t)env->regs[R_EBX],
621 (uint32_t)env->regs[R_ECX],
622 (uint32_t)env->regs[R_EDX],
623 (uint32_t)env->regs[R_ESI],
624 (uint32_t)env->regs[R_EDI],
625 (uint32_t)env->regs[R_EBP],
626 (uint32_t)env->regs[R_ESP],
627 (uint32_t)env->eip, eflags,
628 eflags & DF_MASK ? 'D' : '-',
629 eflags & CC_O ? 'O' : '-',
630 eflags & CC_S ? 'S' : '-',
631 eflags & CC_Z ? 'Z' : '-',
632 eflags & CC_A ? 'A' : '-',
633 eflags & CC_P ? 'P' : '-',
634 eflags & CC_C ? 'C' : '-',
635 env->hflags & HF_CPL_MASK,
636 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
637 (int)(env->a20_mask >> 20) & 1,
638 (env->hflags >> HF_SMM_SHIFT) & 1,
ce5232c5 639 env->halted);
8145122b 640 }
3b46e624 641
eaa728ee
FB		 642#ifdef TARGET_X86_64
643 if (env->hflags & HF_LMA_MASK) {
644 for(i = 0; i < 6; i++) {
645 SegmentCache *sc = &env->segs[i];
646 cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x\n",
647 seg_name[i],
648 sc->selector,
649 sc->base,
650 sc->limit,
651 sc->flags);
652 }
653 cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x\n",
654 env->ldt.selector,
655 env->ldt.base,
656 env->ldt.limit,
657 env->ldt.flags);
658 cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x\n",
659 env->tr.selector,
660 env->tr.base,
661 env->tr.limit,
662 env->tr.flags);
663 cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
664 env->gdt.base, env->gdt.limit);
665 cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
666 env->idt.base, env->idt.limit);
667 cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
668 (uint32_t)env->cr[0],
669 env->cr[2],
670 env->cr[3],
671 (uint32_t)env->cr[4]);
672 } else
673#endif
674 {
675 for(i = 0; i < 6; i++) {
676 SegmentCache *sc = &env->segs[i];
677 cpu_fprintf(f, "%s =%04x %08x %08x %08x\n",
678 seg_name[i],
679 sc->selector,
680 (uint32_t)sc->base,
681 sc->limit,
682 sc->flags);
683 }
684 cpu_fprintf(f, "LDT=%04x %08x %08x %08x\n",
685 env->ldt.selector,
686 (uint32_t)env->ldt.base,
687 env->ldt.limit,
688 env->ldt.flags);
689 cpu_fprintf(f, "TR =%04x %08x %08x %08x\n",
690 env->tr.selector,
691 (uint32_t)env->tr.base,
692 env->tr.limit,
693 env->tr.flags);
694 cpu_fprintf(f, "GDT= %08x %08x\n",
695 (uint32_t)env->gdt.base, env->gdt.limit);
696 cpu_fprintf(f, "IDT= %08x %08x\n",
697 (uint32_t)env->idt.base, env->idt.limit);
698 cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
699 (uint32_t)env->cr[0],
700 (uint32_t)env->cr[2],
701 (uint32_t)env->cr[3],
702 (uint32_t)env->cr[4]);
703 }
704 if (flags & X86_DUMP_CCOP) {
705 if ((unsigned)env->cc_op < CC_OP_NB)
706 snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
707 else
708 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
709#ifdef TARGET_X86_64
710 if (env->hflags & HF_CS64_MASK) {
711 cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
712 env->cc_src, env->cc_dst,
713 cc_op_name);
714 } else
715#endif
716 {
717 cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
718 (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
719 cc_op_name);
720 }
7e84c249 721 }
eaa728ee
FB		 722 if (flags & X86_DUMP_FPU) {
723 int fptag;
724 fptag = 0;
725 for(i = 0; i < 8; i++) {
726 fptag |= ((!env->fptags[i]) << i);
727 }
728 cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
729 env->fpuc,
730 (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
731 env->fpstt,
732 fptag,
733 env->mxcsr);
734 for(i=0;i<8;i++) {
735#if defined(USE_X86LDOUBLE)
736 union {
737 long double d;
738 struct {
739 uint64_t lower;
740 uint16_t upper;
741 } l;
742 } tmp;
743 tmp.d = env->fpregs[i].d;
744 cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
745 i, tmp.l.lower, tmp.l.upper);
746#else
747 cpu_fprintf(f, "FPR%d=%016" PRIx64,
748 i, env->fpregs[i].mmx.q);
749#endif
750 if ((i & 1) == 1)
751 cpu_fprintf(f, "\n");
752 else
753 cpu_fprintf(f, " ");
754 }
755 if (env->hflags & HF_CS64_MASK)
756 nb = 16;
757 else
758 nb = 8;
759 for(i=0;i<nb;i++) {
760 cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
761 i,
762 env->xmm_regs[i].XMM_L(3),
763 env->xmm_regs[i].XMM_L(2),
764 env->xmm_regs[i].XMM_L(1),
765 env->xmm_regs[i].XMM_L(0));
766 if ((i & 1) == 1)
767 cpu_fprintf(f, "\n");
768 else
769 cpu_fprintf(f, " ");
770 }
7e84c249 771 }
2c0262af 772}
7e84c249 773
eaa728ee
FB		 774/***********************************************************/
775/* x86 mmu */
776/* XXX: add PGE support */
777
778void cpu_x86_set_a20(CPUX86State *env, int a20_state)
2c0262af 779{
eaa728ee
FB		 780 a20_state = (a20_state != 0);
781 if (a20_state != ((env->a20_mask >> 20) & 1)) {
782#if defined(DEBUG_MMU)
783 printf("A20 update: a20=%d\n", a20_state);
784#endif
785 /* if the cpu is currently executing code, we must unlink it and
786 all the potentially executing TB */
787 cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
3b46e624 788
eaa728ee
FB		 789 /* when a20 is changed, all the MMU mappings are invalid, so
790 we must flush everything */
791 tlb_flush(env, 1);
792 env->a20_mask = (~0x100000) | (a20_state << 20);
7e84c249 793 }
2c0262af
FB		 794}
795
eaa728ee 796void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
2c0262af 797{
eaa728ee 798 int pe_state;
2c0262af 799
eaa728ee
FB		 800#if defined(DEBUG_MMU)
801 printf("CR0 update: CR0=0x%08x\n", new_cr0);
802#endif
803 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
804 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
805 tlb_flush(env, 1);
806 }
2c0262af 807
eaa728ee
FB		 808#ifdef TARGET_X86_64
809 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
810 (env->efer & MSR_EFER_LME)) {
811 /* enter in long mode */
812 /* XXX: generate an exception */
813 if (!(env->cr[4] & CR4_PAE_MASK))
814 return;
815 env->efer |= MSR_EFER_LMA;
816 env->hflags |= HF_LMA_MASK;
817 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
818 (env->efer & MSR_EFER_LMA)) {
819 /* exit long mode */
820 env->efer &= ~MSR_EFER_LMA;
821 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
822 env->eip &= 0xffffffff;
823 }
824#endif
825 env->cr[0] = new_cr0 | CR0_ET_MASK;
7e84c249 826
eaa728ee
FB		 827 /* update PE flag in hidden flags */
828 pe_state = (env->cr[0] & CR0_PE_MASK);
829 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
830 /* ensure that ADDSEG is always set in real mode */
831 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
832 /* update FPU flags */
833 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
834 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
7e84c249
FB		 835}
836
eaa728ee
FB		 837/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
838 the PDPT */
839void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
7e84c249 840{
eaa728ee
FB		 841 env->cr[3] = new_cr3;
842 if (env->cr[0] & CR0_PG_MASK) {
843#if defined(DEBUG_MMU)
844 printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
845#endif
846 tlb_flush(env, 0);
847 }
7e84c249
FB		 848}
849
eaa728ee 850void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
7e84c249 851{
eaa728ee
FB		 852#if defined(DEBUG_MMU)
853 printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
854#endif
855 if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
856 (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
857 tlb_flush(env, 1);
858 }
859 /* SSE handling */
860 if (!(env->cpuid_features & CPUID_SSE))
861 new_cr4 &= ~CR4_OSFXSR_MASK;
862 if (new_cr4 & CR4_OSFXSR_MASK)
863 env->hflags |= HF_OSFXSR_MASK;
864 else
865 env->hflags &= ~HF_OSFXSR_MASK;
b8b6a50b 866
eaa728ee 867 env->cr[4] = new_cr4;
b8b6a50b
FB		 868}
869
eaa728ee
FB		 870/* XXX: also flush 4MB pages */
871void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr)
b8b6a50b 872{
eaa728ee 873 tlb_flush_page(env, addr);
b8b6a50b
FB		 874}
875
eaa728ee
FB		 876#if defined(CONFIG_USER_ONLY)
877
878int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
879 int is_write, int mmu_idx, int is_softmmu)
b8b6a50b 880{
eaa728ee
FB		 881 /* user mode only emulation */
882 is_write &= 1;
883 env->cr[2] = addr;
884 env->error_code = (is_write << PG_ERROR_W_BIT);
885 env->error_code |= PG_ERROR_U_MASK;
886 env->exception_index = EXCP0E_PAGE;
887 return 1;
2c0262af
FB		 888}
889
eaa728ee 890target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
891b38e4 891{
eaa728ee 892 return addr;
891b38e4
FB		 893}
894
8d7b0fbb 895#else
891b38e4 896
eaa728ee
FB		 897/* XXX: This value should match the one returned by CPUID
898 * and in exec.c */
899#if defined(USE_KQEMU)
2c90d794 900#define PHYS_ADDR_MASK 0xfffff000LL
eaa728ee
FB		 901#else
902# if defined(TARGET_X86_64)
2c90d794 903# define PHYS_ADDR_MASK 0xfffffff000LL
eaa728ee 904# else
2c90d794 905# define PHYS_ADDR_MASK 0xffffff000LL
eaa728ee
FB		 906# endif
907#endif
908
909/* return value:
910 -1 = cannot handle fault
911 0 = nothing more to do
912 1 = generate PF fault
913 2 = soft MMU activation required for this block
914*/
915int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
916 int is_write1, int mmu_idx, int is_softmmu)
917{
918 uint64_t ptep, pte;
919 target_ulong pde_addr, pte_addr;
920 int error_code, is_dirty, prot, page_size, ret, is_write, is_user;
921 target_phys_addr_t paddr;
922 uint32_t page_offset;
923 target_ulong vaddr, virt_addr;
924
925 is_user = mmu_idx == MMU_USER_IDX;
926#if defined(DEBUG_MMU)
927 printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
928 addr, is_write1, is_user, env->eip);
929#endif
930 is_write = is_write1 & 1;
931
932 if (!(env->cr[0] & CR0_PG_MASK)) {
933 pte = addr;
934 virt_addr = addr & TARGET_PAGE_MASK;
935 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
936 page_size = 4096;
937 goto do_mapping;
938 }
939
940 if (env->cr[4] & CR4_PAE_MASK) {
941 uint64_t pde, pdpe;
942 target_ulong pdpe_addr;
2c0262af 943
eaa728ee
FB		 944#ifdef TARGET_X86_64
945 if (env->hflags & HF_LMA_MASK) {
946 uint64_t pml4e_addr, pml4e;
947 int32_t sext;
948
949 /* test virtual address sign extension */
950 sext = (int64_t)addr >> 47;
951 if (sext != 0 && sext != -1) {
952 env->error_code = 0;
953 env->exception_index = EXCP0D_GPF;
954 return 1;
955 }
0573fbfc 956
eaa728ee
FB		 957 pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
958 env->a20_mask;
959 pml4e = ldq_phys(pml4e_addr);
960 if (!(pml4e & PG_PRESENT_MASK)) {
961 error_code = 0;
962 goto do_fault;
963 }
964 if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
965 error_code = PG_ERROR_RSVD_MASK;
966 goto do_fault;
967 }
968 if (!(pml4e & PG_ACCESSED_MASK)) {
969 pml4e |= PG_ACCESSED_MASK;
970 stl_phys_notdirty(pml4e_addr, pml4e);
971 }
972 ptep = pml4e ^ PG_NX_MASK;
973 pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
974 env->a20_mask;
975 pdpe = ldq_phys(pdpe_addr);
976 if (!(pdpe & PG_PRESENT_MASK)) {
977 error_code = 0;
978 goto do_fault;
979 }
980 if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
981 error_code = PG_ERROR_RSVD_MASK;
982 goto do_fault;
983 }
984 ptep &= pdpe ^ PG_NX_MASK;
985 if (!(pdpe & PG_ACCESSED_MASK)) {
986 pdpe |= PG_ACCESSED_MASK;
987 stl_phys_notdirty(pdpe_addr, pdpe);
988 }
989 } else
990#endif
991 {
992 /* XXX: load them when cr3 is loaded ? */
993 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
994 env->a20_mask;
995 pdpe = ldq_phys(pdpe_addr);
996 if (!(pdpe & PG_PRESENT_MASK)) {
997 error_code = 0;
998 goto do_fault;
999 }
1000 ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
7e84c249 1001 }
7e84c249 1002
eaa728ee
FB		 1003 pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
1004 env->a20_mask;
1005 pde = ldq_phys(pde_addr);
1006 if (!(pde & PG_PRESENT_MASK)) {
1007 error_code = 0;
1008 goto do_fault;
1009 }
1010 if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
1011 error_code = PG_ERROR_RSVD_MASK;
1012 goto do_fault;
1013 }
1014 ptep &= pde ^ PG_NX_MASK;
1015 if (pde & PG_PSE_MASK) {
1016 /* 2 MB page */
1017 page_size = 2048 * 1024;
1018 ptep ^= PG_NX_MASK;
1019 if ((ptep & PG_NX_MASK) && is_write1 == 2)
1020 goto do_fault_protect;
1021 if (is_user) {
1022 if (!(ptep & PG_USER_MASK))
1023 goto do_fault_protect;
1024 if (is_write && !(ptep & PG_RW_MASK))
1025 goto do_fault_protect;
1026 } else {
1027 if ((env->cr[0] & CR0_WP_MASK) &&
1028 is_write && !(ptep & PG_RW_MASK))
1029 goto do_fault_protect;
1030 }
1031 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
1032 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
1033 pde |= PG_ACCESSED_MASK;
1034 if (is_dirty)
1035 pde |= PG_DIRTY_MASK;
1036 stl_phys_notdirty(pde_addr, pde);
1037 }
1038 /* align to page_size */
1039 pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
1040 virt_addr = addr & ~(page_size - 1);
1041 } else {
1042 /* 4 KB page */
1043 if (!(pde & PG_ACCESSED_MASK)) {
1044 pde |= PG_ACCESSED_MASK;
1045 stl_phys_notdirty(pde_addr, pde);
1046 }
1047 pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
1048 env->a20_mask;
1049 pte = ldq_phys(pte_addr);
1050 if (!(pte & PG_PRESENT_MASK)) {
1051 error_code = 0;
1052 goto do_fault;
1053 }
1054 if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
1055 error_code = PG_ERROR_RSVD_MASK;
1056 goto do_fault;
1057 }
1058 /* combine pde and pte nx, user and rw protections */
1059 ptep &= pte ^ PG_NX_MASK;
1060 ptep ^= PG_NX_MASK;
1061 if ((ptep & PG_NX_MASK) && is_write1 == 2)
1062 goto do_fault_protect;
1063 if (is_user) {
1064 if (!(ptep & PG_USER_MASK))
1065 goto do_fault_protect;
1066 if (is_write && !(ptep & PG_RW_MASK))
1067 goto do_fault_protect;
1068 } else {
1069 if ((env->cr[0] & CR0_WP_MASK) &&
1070 is_write && !(ptep & PG_RW_MASK))
1071 goto do_fault_protect;
1072 }
1073 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
1074 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
1075 pte |= PG_ACCESSED_MASK;
1076 if (is_dirty)
1077 pte |= PG_DIRTY_MASK;
1078 stl_phys_notdirty(pte_addr, pte);
1079 }
1080 page_size = 4096;
1081 virt_addr = addr & ~0xfff;
1082 pte = pte & (PHYS_ADDR_MASK | 0xfff);
7e84c249 1083 }
2c0262af 1084 } else {
eaa728ee
FB		 1085 uint32_t pde;
1086
1087 /* page directory entry */
1088 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
1089 env->a20_mask;
1090 pde = ldl_phys(pde_addr);
1091 if (!(pde & PG_PRESENT_MASK)) {
1092 error_code = 0;
1093 goto do_fault;
1094 }
1095 /* if PSE bit is set, then we use a 4MB page */
1096 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
1097 page_size = 4096 * 1024;
1098 if (is_user) {
1099 if (!(pde & PG_USER_MASK))
1100 goto do_fault_protect;
1101 if (is_write && !(pde & PG_RW_MASK))
1102 goto do_fault_protect;
1103 } else {
1104 if ((env->cr[0] & CR0_WP_MASK) &&
1105 is_write && !(pde & PG_RW_MASK))
1106 goto do_fault_protect;
1107 }
1108 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
1109 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
1110 pde |= PG_ACCESSED_MASK;
1111 if (is_dirty)
1112 pde |= PG_DIRTY_MASK;
1113 stl_phys_notdirty(pde_addr, pde);
1114 }
2c0262af 1115
eaa728ee
FB		 1116 pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
1117 ptep = pte;
1118 virt_addr = addr & ~(page_size - 1);
1119 } else {
1120 if (!(pde & PG_ACCESSED_MASK)) {
1121 pde |= PG_ACCESSED_MASK;
1122 stl_phys_notdirty(pde_addr, pde);
1123 }
891b38e4 1124
eaa728ee
FB		 1125 /* page directory entry */
1126 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
1127 env->a20_mask;
1128 pte = ldl_phys(pte_addr);
1129 if (!(pte & PG_PRESENT_MASK)) {
1130 error_code = 0;
1131 goto do_fault;
8e682019 1132 }
eaa728ee
FB		 1133 /* combine pde and pte user and rw protections */
1134 ptep = pte & pde;
1135 if (is_user) {
1136 if (!(ptep & PG_USER_MASK))
1137 goto do_fault_protect;
1138 if (is_write && !(ptep & PG_RW_MASK))
1139 goto do_fault_protect;
1140 } else {
1141 if ((env->cr[0] & CR0_WP_MASK) &&
1142 is_write && !(ptep & PG_RW_MASK))
1143 goto do_fault_protect;
8e682019 1144 }
eaa728ee
FB		 1145 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
1146 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
1147 pte |= PG_ACCESSED_MASK;
1148 if (is_dirty)
1149 pte |= PG_DIRTY_MASK;
1150 stl_phys_notdirty(pte_addr, pte);
1151 }
1152 page_size = 4096;
1153 virt_addr = addr & ~0xfff;
2c0262af
FB		 1154 }
1155 }
eaa728ee
FB		 1156 /* the page can be put in the TLB */
1157 prot = PAGE_READ;
1158 if (!(ptep & PG_NX_MASK))
1159 prot |= PAGE_EXEC;
1160 if (pte & PG_DIRTY_MASK) {
1161 /* only set write access if already dirty... otherwise wait
1162 for dirty access */
1163 if (is_user) {
1164 if (ptep & PG_RW_MASK)
1165 prot |= PAGE_WRITE;
1166 } else {
1167 if (!(env->cr[0] & CR0_WP_MASK) ||
1168 (ptep & PG_RW_MASK))
1169 prot |= PAGE_WRITE;
8e682019 1170 }
891b38e4 1171 }
eaa728ee
FB		 1172 do_mapping:
1173 pte = pte & env->a20_mask;
1174
1175 /* Even if 4MB pages, we map only one 4KB page in the cache to
1176 avoid filling it too fast */
1177 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1178 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1179 vaddr = virt_addr + page_offset;
1180
1181 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
1182 return ret;
1183 do_fault_protect:
1184 error_code = PG_ERROR_P_MASK;
1185 do_fault:
1186 error_code |= (is_write << PG_ERROR_W_BIT);
1187 if (is_user)
1188 error_code |= PG_ERROR_U_MASK;
1189 if (is_write1 == 2 &&
1190 (env->efer & MSR_EFER_NXE) &&
1191 (env->cr[4] & CR4_PAE_MASK))
1192 error_code |= PG_ERROR_I_D_MASK;
872929aa
FB		 1193 if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
1194 /* cr2 is not modified in case of exceptions */
1195 stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
1196 addr);
eaa728ee
FB		 1197 } else {
1198 env->cr[2] = addr;
2c0262af 1199 }
eaa728ee
FB		 1200 env->error_code = error_code;
1201 env->exception_index = EXCP0E_PAGE;
eaa728ee 1202 return 1;
14ce26e7
FB		 1203}
1204
eaa728ee 1205target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
14ce26e7 1206{
eaa728ee
FB		 1207 target_ulong pde_addr, pte_addr;
1208 uint64_t pte;
1209 target_phys_addr_t paddr;
1210 uint32_t page_offset;
1211 int page_size;
14ce26e7 1212
eaa728ee
FB		 1213 if (env->cr[4] & CR4_PAE_MASK) {
1214 target_ulong pdpe_addr;
1215 uint64_t pde, pdpe;
14ce26e7 1216
eaa728ee
FB		 1217#ifdef TARGET_X86_64
1218 if (env->hflags & HF_LMA_MASK) {
1219 uint64_t pml4e_addr, pml4e;
1220 int32_t sext;
1221
1222 /* test virtual address sign extension */
1223 sext = (int64_t)addr >> 47;
1224 if (sext != 0 && sext != -1)
1225 return -1;
1226
1227 pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
1228 env->a20_mask;
1229 pml4e = ldq_phys(pml4e_addr);
1230 if (!(pml4e & PG_PRESENT_MASK))
1231 return -1;
1232
1233 pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
1234 env->a20_mask;
1235 pdpe = ldq_phys(pdpe_addr);
1236 if (!(pdpe & PG_PRESENT_MASK))
1237 return -1;
1238 } else
1239#endif
1240 {
1241 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
1242 env->a20_mask;
1243 pdpe = ldq_phys(pdpe_addr);
1244 if (!(pdpe & PG_PRESENT_MASK))
1245 return -1;
14ce26e7 1246 }
14ce26e7 1247
eaa728ee
FB		 1248 pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
1249 env->a20_mask;
1250 pde = ldq_phys(pde_addr);
1251 if (!(pde & PG_PRESENT_MASK)) {
1252 return -1;
1253 }
1254 if (pde & PG_PSE_MASK) {
1255 /* 2 MB page */
1256 page_size = 2048 * 1024;
1257 pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
1258 } else {
1259 /* 4 KB page */
1260 pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
1261 env->a20_mask;
1262 page_size = 4096;
1263 pte = ldq_phys(pte_addr);
1264 }
ca1c9e15
AL		 1265 if (!(pte & PG_PRESENT_MASK))
1266 return -1;
14ce26e7 1267 } else {
eaa728ee 1268 uint32_t pde;
3b46e624 1269
eaa728ee
FB		 1270 if (!(env->cr[0] & CR0_PG_MASK)) {
1271 pte = addr;
1272 page_size = 4096;
1273 } else {
1274 /* page directory entry */
1275 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
1276 pde = ldl_phys(pde_addr);
1277 if (!(pde & PG_PRESENT_MASK))
1278 return -1;
1279 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
1280 pte = pde & ~0x003ff000; /* align to 4MB */
1281 page_size = 4096 * 1024;
1282 } else {
1283 /* page directory entry */
1284 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
1285 pte = ldl_phys(pte_addr);
1286 if (!(pte & PG_PRESENT_MASK))
1287 return -1;
1288 page_size = 4096;
1289 }
1290 }
1291 pte = pte & env->a20_mask;
14ce26e7 1292 }
14ce26e7 1293
eaa728ee
FB		 1294 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1295 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1296 return paddr;
3b21e03e 1297}
74ce674f 1298#endif /* !CONFIG_USER_ONLY */
6fd805e1 1299
7ba1e619
AL		 1300static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
1301 uint32_t *ecx, uint32_t *edx)
1302{
10781c09 1303#if defined(CONFIG_KVM)
7ba1e619
AL		 1304 uint32_t vec[4];
1305
1306#ifdef __x86_64__
1307 asm volatile("cpuid"
1308 : "=a"(vec[0]), "=b"(vec[1]),
1309 "=c"(vec[2]), "=d"(vec[3])
1310 : "0"(function) : "cc");
1311#else
1312 asm volatile("pusha \n\t"
1313 "cpuid \n\t"
1314 "mov %%eax, 0(%1) \n\t"
1315 "mov %%ebx, 4(%1) \n\t"
1316 "mov %%ecx, 8(%1) \n\t"
1317 "mov %%edx, 12(%1) \n\t"
1318 "popa"
1319 : : "a"(function), "S"(vec)
1320 : "memory", "cc");
1321#endif
1322
1323 if (eax)
1324 *eax = vec[0];
1325 if (ebx)
1326 *ebx = vec[1];
1327 if (ecx)
1328 *ecx = vec[2];
1329 if (edx)
1330 *edx = vec[3];
7ba1e619 1331#endif
10781c09 1332}
7ba1e619 1333
6fd805e1
AL		 1334void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
1335 uint32_t *eax, uint32_t *ebx,
1336 uint32_t *ecx, uint32_t *edx)
1337{
1338 /* test if maximum index reached */
1339 if (index & 0x80000000) {
1340 if (index > env->cpuid_xlevel)
1341 index = env->cpuid_level;
1342 } else {
1343 if (index > env->cpuid_level)
1344 index = env->cpuid_level;
1345 }
1346
1347 switch(index) {
1348 case 0:
1349 *eax = env->cpuid_level;
1350 *ebx = env->cpuid_vendor1;
1351 *edx = env->cpuid_vendor2;
1352 *ecx = env->cpuid_vendor3;
7ba1e619
AL		 1353
1354 /* sysenter isn't supported on compatibility mode on AMD. and syscall
1355 * isn't supported in compatibility mode on Intel. so advertise the
1356 * actuall cpu, and say goodbye to migration between different vendors
1357 * is you use compatibility mode. */
1358 if (kvm_enabled())
1359 host_cpuid(0, NULL, ebx, ecx, edx);
6fd805e1
AL		 1360 break;
1361 case 1:
1362 *eax = env->cpuid_version;
1363 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1364 *ecx = env->cpuid_ext_features;
1365 *edx = env->cpuid_features;
7ba1e619
AL		 1366
1367 /* "Hypervisor present" bit required for Microsoft SVVP */
1368 if (kvm_enabled())
1369 *ecx |= (1 << 31);
6fd805e1
AL		 1370 break;
1371 case 2:
1372 /* cache info: needed for Pentium Pro compatibility */
1373 *eax = 1;
1374 *ebx = 0;
1375 *ecx = 0;
1376 *edx = 0x2c307d;
1377 break;
1378 case 4:
1379 /* cache info: needed for Core compatibility */
1380 switch (*ecx) {
1381 case 0: /* L1 dcache info */
1382 *eax = 0x0000121;
1383 *ebx = 0x1c0003f;
1384 *ecx = 0x000003f;
1385 *edx = 0x0000001;
1386 break;
1387 case 1: /* L1 icache info */
1388 *eax = 0x0000122;
1389 *ebx = 0x1c0003f;
1390 *ecx = 0x000003f;
1391 *edx = 0x0000001;
1392 break;
1393 case 2: /* L2 cache info */
1394 *eax = 0x0000143;
1395 *ebx = 0x3c0003f;
1396 *ecx = 0x0000fff;
1397 *edx = 0x0000001;
1398 break;
1399 default: /* end of info */
1400 *eax = 0;
1401 *ebx = 0;
1402 *ecx = 0;
1403 *edx = 0;
1404 break;
1405 }
1406
1407 break;
1408 case 5:
1409 /* mwait info: needed for Core compatibility */
1410 *eax = 0; /* Smallest monitor-line size in bytes */
1411 *ebx = 0; /* Largest monitor-line size in bytes */
1412 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1413 *edx = 0;
1414 break;
1415 case 6:
1416 /* Thermal and Power Leaf */
1417 *eax = 0;
1418 *ebx = 0;
1419 *ecx = 0;
1420 *edx = 0;
1421 break;
1422 case 9:
1423 /* Direct Cache Access Information Leaf */
1424 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1425 *ebx = 0;
1426 *ecx = 0;
1427 *edx = 0;
1428 break;
1429 case 0xA:
1430 /* Architectural Performance Monitoring Leaf */
1431 *eax = 0;
1432 *ebx = 0;
1433 *ecx = 0;
1434 *edx = 0;
1435 break;
1436 case 0x80000000:
1437 *eax = env->cpuid_xlevel;
1438 *ebx = env->cpuid_vendor1;
1439 *edx = env->cpuid_vendor2;
1440 *ecx = env->cpuid_vendor3;
1441 break;
1442 case 0x80000001:
1443 *eax = env->cpuid_features;
1444 *ebx = 0;
1445 *ecx = env->cpuid_ext3_features;
1446 *edx = env->cpuid_ext2_features;
7ba1e619
AL		 1447
1448 if (kvm_enabled()) {
1449 uint32_t h_eax, h_edx;
1450
1451 host_cpuid(0x80000001, &h_eax, NULL, NULL, &h_edx);
1452
1453 /* disable CPU features that the host does not support */
1454
1455 /* long mode */
1456 if ((h_edx & 0x20000000) == 0 /* || !lm_capable_kernel */)
1457 *edx &= ~0x20000000;
1458 /* syscall */
1459 if ((h_edx & 0x00000800) == 0)
1460 *edx &= ~0x00000800;
1461 /* nx */
1462 if ((h_edx & 0x00100000) == 0)
1463 *edx &= ~0x00100000;
1464
1465 /* disable CPU features that KVM cannot support */
1466
1467 /* svm */
1468 *ecx &= ~4UL;
1469 /* 3dnow */
57003085 1470 *edx &= ~0xc0000000;
7ba1e619 1471 }
6fd805e1
AL		 1472 break;
1473 case 0x80000002:
1474 case 0x80000003:
1475 case 0x80000004:
1476 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1477 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1478 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1479 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1480 break;
1481 case 0x80000005:
1482 /* cache info (L1 cache) */
1483 *eax = 0x01ff01ff;
1484 *ebx = 0x01ff01ff;
1485 *ecx = 0x40020140;
1486 *edx = 0x40020140;
1487 break;
1488 case 0x80000006:
1489 /* cache info (L2 cache) */
1490 *eax = 0;
1491 *ebx = 0x42004200;
1492 *ecx = 0x02008140;
1493 *edx = 0;
1494 break;
1495 case 0x80000008:
1496 /* virtual & phys address size in low 2 bytes. */
1497/* XXX: This value must match the one used in the MMU code. */
1498 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1499 /* 64 bit processor */
1500#if defined(USE_KQEMU)
1501 *eax = 0x00003020; /* 48 bits virtual, 32 bits physical */
1502#else
1503/* XXX: The physical address space is limited to 42 bits in exec.c. */
1504 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1505#endif
1506 } else {
1507#if defined(USE_KQEMU)
1508 *eax = 0x00000020; /* 32 bits physical */
1509#else
1510 if (env->cpuid_features & CPUID_PSE36)
1511 *eax = 0x00000024; /* 36 bits physical */
1512 else
1513 *eax = 0x00000020; /* 32 bits physical */
1514#endif
1515 }
1516 *ebx = 0;
1517 *ecx = 0;
1518 *edx = 0;
1519 break;
1520 case 0x8000000A:
1521 *eax = 0x00000001; /* SVM Revision */
1522 *ebx = 0x00000010; /* nr of ASIDs */
1523 *ecx = 0;
1524 *edx = 0; /* optional features */
1525 break;
1526 default:
1527 /* reserved values: zero */
1528 *eax = 0;
1529 *ebx = 0;
1530 *ecx = 0;
1531 *edx = 0;
1532 break;
1533 }
1534}
Qemu copy for testing