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PCI IRC routing fix.
[qemu.git] / target-i386 / helper.c
CommitLineData
2c0262af
FB		 1/*
2 * i386 helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "exec.h"
21
f3f2d9be
FB		 22//#define DEBUG_PCALL
23
8145122b
FB		 24#if 0
25#define raise_exception_err(a, b)\
26do {\
9540a78b
FB		 27 if (logfile)\
28 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
8145122b
FB		 29 (raise_exception_err)(a, b);\
30} while (0)
31#endif
32
2c0262af
FB		 33const uint8_t parity_table[256] = {
34 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
37 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
38 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
41 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
42 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
43 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
44 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
45 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
46 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
57 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
58 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
59 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
61 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
66};
67
68/* modulo 17 table */
69const uint8_t rclw_table[32] = {
70 0, 1, 2, 3, 4, 5, 6, 7,
71 8, 9,10,11,12,13,14,15,
72 16, 0, 1, 2, 3, 4, 5, 6,
73 7, 8, 9,10,11,12,13,14,
74};
75
76/* modulo 9 table */
77const uint8_t rclb_table[32] = {
78 0, 1, 2, 3, 4, 5, 6, 7,
79 8, 0, 1, 2, 3, 4, 5, 6,
80 7, 8, 0, 1, 2, 3, 4, 5,
81 6, 7, 8, 0, 1, 2, 3, 4,
82};
83
84const CPU86_LDouble f15rk[7] =
85{
86 0.00000000000000000000L,
87 1.00000000000000000000L,
88 3.14159265358979323851L, /*pi*/
89 0.30102999566398119523L, /*lg2*/
90 0.69314718055994530943L, /*ln2*/
91 1.44269504088896340739L, /*l2e*/
92 3.32192809488736234781L, /*l2t*/
93};
94
95/* thread support */
96
97spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
98
99void cpu_lock(void)
100{
101 spin_lock(&global_cpu_lock);
102}
103
104void cpu_unlock(void)
105{
106 spin_unlock(&global_cpu_lock);
107}
108
109void cpu_loop_exit(void)
110{
111 /* NOTE: the register at this point must be saved by hand because
112 longjmp restore them */
0d1a29f9 113 regs_to_env();
2c0262af
FB		 114 longjmp(env->jmp_env, 1);
115}
116
7e84c249
FB		 117/* return non zero if error */
118static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
119 int selector)
120{
121 SegmentCache *dt;
122 int index;
14ce26e7 123 target_ulong ptr;
7e84c249
FB		 124
125 if (selector & 0x4)
126 dt = &env->ldt;
127 else
128 dt = &env->gdt;
129 index = selector & ~7;
130 if ((index + 7) > dt->limit)
131 return -1;
132 ptr = dt->base + index;
133 *e1_ptr = ldl_kernel(ptr);
134 *e2_ptr = ldl_kernel(ptr + 4);
135 return 0;
136}
137
138static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
139{
140 unsigned int limit;
141 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
142 if (e2 & DESC_G_MASK)
143 limit = (limit << 12) | 0xfff;
144 return limit;
145}
146
14ce26e7 147static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
7e84c249 148{
14ce26e7 149 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
7e84c249
FB		 150}
151
152static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
153{
154 sc->base = get_seg_base(e1, e2);
155 sc->limit = get_seg_limit(e1, e2);
156 sc->flags = e2;
157}
158
159/* init the segment cache in vm86 mode. */
160static inline void load_seg_vm(int seg, int selector)
161{
162 selector &= 0xffff;
163 cpu_x86_load_seg_cache(env, seg, selector,
14ce26e7 164 (selector << 4), 0xffff, 0);
7e84c249
FB		 165}
166
2c0262af
FB		 167static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
168 uint32_t *esp_ptr, int dpl)
169{
170 int type, index, shift;
171
172#if 0
173 {
174 int i;
175 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
176 for(i=0;i<env->tr.limit;i++) {
177 printf("%02x ", env->tr.base[i]);
178 if ((i & 7) == 7) printf("\n");
179 }
180 printf("\n");
181 }
182#endif
183
184 if (!(env->tr.flags & DESC_P_MASK))
185 cpu_abort(env, "invalid tss");
186 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
187 if ((type & 7) != 1)
188 cpu_abort(env, "invalid tss type");
189 shift = type >> 3;
190 index = (dpl * 4 + 2) << shift;
191 if (index + (4 << shift) - 1 > env->tr.limit)
192 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
193 if (shift == 0) {
61382a50
FB		 194 *esp_ptr = lduw_kernel(env->tr.base + index);
195 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
2c0262af 196 } else {
61382a50
FB		 197 *esp_ptr = ldl_kernel(env->tr.base + index);
198 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
2c0262af
FB		 199 }
200}
201
7e84c249
FB		 202/* XXX: merge with load_seg() */
203static void tss_load_seg(int seg_reg, int selector)
204{
205 uint32_t e1, e2;
206 int rpl, dpl, cpl;
207
208 if ((selector & 0xfffc) != 0) {
209 if (load_segment(&e1, &e2, selector) != 0)
210 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
211 if (!(e2 & DESC_S_MASK))
212 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
213 rpl = selector & 3;
214 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
215 cpl = env->hflags & HF_CPL_MASK;
216 if (seg_reg == R_CS) {
217 if (!(e2 & DESC_CS_MASK))
218 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
9540a78b 219 /* XXX: is it correct ? */
7e84c249
FB		 220 if (dpl != rpl)
221 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
222 if ((e2 & DESC_C_MASK) && dpl > rpl)
223 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
7e84c249
FB		 224 } else if (seg_reg == R_SS) {
225 /* SS must be writable data */
226 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
227 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
228 if (dpl != cpl || dpl != rpl)
229 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
230 } else {
231 /* not readable code */
232 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
233 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
234 /* if data or non conforming code, checks the rights */
235 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
236 if (dpl < cpl || dpl < rpl)
237 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
238 }
239 }
240 if (!(e2 & DESC_P_MASK))
241 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
242 cpu_x86_load_seg_cache(env, seg_reg, selector,
243 get_seg_base(e1, e2),
244 get_seg_limit(e1, e2),
245 e2);
246 } else {
247 if (seg_reg == R_SS || seg_reg == R_CS)
248 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
249 }
250}
251
252#define SWITCH_TSS_JMP 0
253#define SWITCH_TSS_IRET 1
254#define SWITCH_TSS_CALL 2
255
256/* XXX: restore CPU state in registers (PowerPC case) */
257static void switch_tss(int tss_selector,
883da8e2
FB		 258 uint32_t e1, uint32_t e2, int source,
259 uint32_t next_eip)
2c0262af 260{
7e84c249 261 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
14ce26e7 262 target_ulong tss_base;
7e84c249
FB		 263 uint32_t new_regs[8], new_segs[6];
264 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
265 uint32_t old_eflags, eflags_mask;
2c0262af
FB		 266 SegmentCache *dt;
267 int index;
14ce26e7 268 target_ulong ptr;
2c0262af 269
7e84c249 270 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
dc6f57fd 271#ifdef DEBUG_PCALL
e19e89a5 272 if (loglevel & CPU_LOG_PCALL)
dc6f57fd
FB		 273 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
274#endif
7e84c249
FB		 275
276 /* if task gate, we read the TSS segment and we load it */
277 if (type == 5) {
278 if (!(e2 & DESC_P_MASK))
279 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
280 tss_selector = e1 >> 16;
281 if (tss_selector & 4)
282 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
283 if (load_segment(&e1, &e2, tss_selector) != 0)
284 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
285 if (e2 & DESC_S_MASK)
286 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
287 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
288 if ((type & 7) != 1)
289 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
290 }
291
292 if (!(e2 & DESC_P_MASK))
293 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
294
295 if (type & 8)
296 tss_limit_max = 103;
2c0262af 297 else
7e84c249
FB		 298 tss_limit_max = 43;
299 tss_limit = get_seg_limit(e1, e2);
300 tss_base = get_seg_base(e1, e2);
301 if ((tss_selector & 4) != 0 ||
302 tss_limit < tss_limit_max)
303 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
304 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
305 if (old_type & 8)
306 old_tss_limit_max = 103;
307 else
308 old_tss_limit_max = 43;
309
310 /* read all the registers from the new TSS */
311 if (type & 8) {
312 /* 32 bit */
313 new_cr3 = ldl_kernel(tss_base + 0x1c);
314 new_eip = ldl_kernel(tss_base + 0x20);
315 new_eflags = ldl_kernel(tss_base + 0x24);
316 for(i = 0; i < 8; i++)
317 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
318 for(i = 0; i < 6; i++)
319 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
320 new_ldt = lduw_kernel(tss_base + 0x60);
321 new_trap = ldl_kernel(tss_base + 0x64);
322 } else {
323 /* 16 bit */
324 new_cr3 = 0;
325 new_eip = lduw_kernel(tss_base + 0x0e);
326 new_eflags = lduw_kernel(tss_base + 0x10);
327 for(i = 0; i < 8; i++)
328 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
329 for(i = 0; i < 4; i++)
330 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
331 new_ldt = lduw_kernel(tss_base + 0x2a);
332 new_segs[R_FS] = 0;
333 new_segs[R_GS] = 0;
334 new_trap = 0;
335 }
336
337 /* NOTE: we must avoid memory exceptions during the task switch,
338 so we make dummy accesses before */
339 /* XXX: it can still fail in some cases, so a bigger hack is
340 necessary to valid the TLB after having done the accesses */
341
342 v1 = ldub_kernel(env->tr.base);
265d3497 343 v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
7e84c249
FB		 344 stb_kernel(env->tr.base, v1);
345 stb_kernel(env->tr.base + old_tss_limit_max, v2);
346
347 /* clear busy bit (it is restartable) */
348 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
14ce26e7 349 target_ulong ptr;
7e84c249 350 uint32_t e2;
883da8e2 351 ptr = env->gdt.base + (env->tr.selector & ~7);
7e84c249
FB		 352 e2 = ldl_kernel(ptr + 4);
353 e2 &= ~DESC_TSS_BUSY_MASK;
354 stl_kernel(ptr + 4, e2);
355 }
356 old_eflags = compute_eflags();
357 if (source == SWITCH_TSS_IRET)
358 old_eflags &= ~NT_MASK;
359
360 /* save the current state in the old TSS */
361 if (type & 8) {
362 /* 32 bit */
883da8e2 363 stl_kernel(env->tr.base + 0x20, next_eip);
7e84c249 364 stl_kernel(env->tr.base + 0x24, old_eflags);
0d1a29f9
FB		 365 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
366 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
367 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
368 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
369 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
370 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
371 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
372 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
7e84c249
FB		 373 for(i = 0; i < 6; i++)
374 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
375 } else {
376 /* 16 bit */
883da8e2 377 stw_kernel(env->tr.base + 0x0e, next_eip);
7e84c249 378 stw_kernel(env->tr.base + 0x10, old_eflags);
0d1a29f9
FB		 379 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
380 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
381 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
382 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
383 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
384 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
385 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
386 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
7e84c249
FB		 387 for(i = 0; i < 4; i++)
388 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
389 }
390
391 /* now if an exception occurs, it will occurs in the next task
392 context */
393
394 if (source == SWITCH_TSS_CALL) {
395 stw_kernel(tss_base, env->tr.selector);
396 new_eflags |= NT_MASK;
397 }
398
399 /* set busy bit */
400 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
14ce26e7 401 target_ulong ptr;
7e84c249 402 uint32_t e2;
883da8e2 403 ptr = env->gdt.base + (tss_selector & ~7);
7e84c249
FB		 404 e2 = ldl_kernel(ptr + 4);
405 e2 |= DESC_TSS_BUSY_MASK;
406 stl_kernel(ptr + 4, e2);
407 }
408
409 /* set the new CPU state */
410 /* from this point, any exception which occurs can give problems */
411 env->cr[0] |= CR0_TS_MASK;
883da8e2 412 env->hflags |= HF_TS_MASK;
7e84c249
FB		 413 env->tr.selector = tss_selector;
414 env->tr.base = tss_base;
415 env->tr.limit = tss_limit;
416 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
417
418 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
1ac157da 419 cpu_x86_update_cr3(env, new_cr3);
7e84c249
FB		 420 }
421
422 /* load all registers without an exception, then reload them with
423 possible exception */
424 env->eip = new_eip;
4136f33c 425 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
8145122b 426 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
7e84c249
FB		 427 if (!(type & 8))
428 eflags_mask &= 0xffff;
429 load_eflags(new_eflags, eflags_mask);
0d1a29f9
FB		 430 /* XXX: what to do in 16 bit case ? */
431 EAX = new_regs[0];
432 ECX = new_regs[1];
433 EDX = new_regs[2];
434 EBX = new_regs[3];
435 ESP = new_regs[4];
436 EBP = new_regs[5];
437 ESI = new_regs[6];
438 EDI = new_regs[7];
7e84c249
FB		 439 if (new_eflags & VM_MASK) {
440 for(i = 0; i < 6; i++)
441 load_seg_vm(i, new_segs[i]);
442 /* in vm86, CPL is always 3 */
443 cpu_x86_set_cpl(env, 3);
444 } else {
445 /* CPL is set the RPL of CS */
446 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
447 /* first just selectors as the rest may trigger exceptions */
448 for(i = 0; i < 6; i++)
14ce26e7 449 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
7e84c249
FB		 450 }
451
452 env->ldt.selector = new_ldt & ~4;
14ce26e7 453 env->ldt.base = 0;
7e84c249
FB		 454 env->ldt.limit = 0;
455 env->ldt.flags = 0;
456
457 /* load the LDT */
458 if (new_ldt & 4)
459 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
460
8145122b
FB		 461 if ((new_ldt & 0xfffc) != 0) {
462 dt = &env->gdt;
463 index = new_ldt & ~7;
464 if ((index + 7) > dt->limit)
465 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
466 ptr = dt->base + index;
467 e1 = ldl_kernel(ptr);
468 e2 = ldl_kernel(ptr + 4);
469 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
470 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
471 if (!(e2 & DESC_P_MASK))
472 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
473 load_seg_cache_raw_dt(&env->ldt, e1, e2);
474 }
7e84c249
FB		 475
476 /* load the segments */
477 if (!(new_eflags & VM_MASK)) {
478 tss_load_seg(R_CS, new_segs[R_CS]);
479 tss_load_seg(R_SS, new_segs[R_SS]);
480 tss_load_seg(R_ES, new_segs[R_ES]);
481 tss_load_seg(R_DS, new_segs[R_DS]);
482 tss_load_seg(R_FS, new_segs[R_FS]);
483 tss_load_seg(R_GS, new_segs[R_GS]);
484 }
485
486 /* check that EIP is in the CS segment limits */
487 if (new_eip > env->segs[R_CS].limit) {
883da8e2 488 /* XXX: different exception if CALL ? */
7e84c249
FB		 489 raise_exception_err(EXCP0D_GPF, 0);
490 }
2c0262af 491}
7e84c249
FB		 492
493/* check if Port I/O is allowed in TSS */
494static inline void check_io(int addr, int size)
2c0262af 495{
7e84c249
FB		 496 int io_offset, val, mask;
497
498 /* TSS must be a valid 32 bit one */
499 if (!(env->tr.flags & DESC_P_MASK) ||
500 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
501 env->tr.limit < 103)
502 goto fail;
503 io_offset = lduw_kernel(env->tr.base + 0x66);
504 io_offset += (addr >> 3);
505 /* Note: the check needs two bytes */
506 if ((io_offset + 1) > env->tr.limit)
507 goto fail;
508 val = lduw_kernel(env->tr.base + io_offset);
509 val >>= (addr & 7);
510 mask = (1 << size) - 1;
511 /* all bits must be zero to allow the I/O */
512 if ((val & mask) != 0) {
513 fail:
514 raise_exception_err(EXCP0D_GPF, 0);
515 }
2c0262af
FB		 516}
517
7e84c249 518void check_iob_T0(void)
2c0262af 519{
7e84c249 520 check_io(T0, 1);
2c0262af
FB		 521}
522
7e84c249 523void check_iow_T0(void)
2c0262af 524{
7e84c249 525 check_io(T0, 2);
2c0262af
FB		 526}
527
7e84c249 528void check_iol_T0(void)
2c0262af 529{
7e84c249
FB		 530 check_io(T0, 4);
531}
532
533void check_iob_DX(void)
534{
535 check_io(EDX & 0xffff, 1);
536}
537
538void check_iow_DX(void)
539{
540 check_io(EDX & 0xffff, 2);
541}
542
543void check_iol_DX(void)
544{
545 check_io(EDX & 0xffff, 4);
2c0262af
FB		 546}
547
891b38e4
FB		 548static inline unsigned int get_sp_mask(unsigned int e2)
549{
550 if (e2 & DESC_B_MASK)
551 return 0xffffffff;
552 else
553 return 0xffff;
554}
555
556/* XXX: add a is_user flag to have proper security support */
557#define PUSHW(ssp, sp, sp_mask, val)\
558{\
559 sp -= 2;\
560 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
561}
562
563#define PUSHL(ssp, sp, sp_mask, val)\
564{\
565 sp -= 4;\
566 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
567}
568
569#define POPW(ssp, sp, sp_mask, val)\
570{\
571 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
572 sp += 2;\
573}
574
575#define POPL(ssp, sp, sp_mask, val)\
576{\
14ce26e7 577 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
891b38e4
FB		 578 sp += 4;\
579}
580
2c0262af
FB		 581/* protected mode interrupt */
582static void do_interrupt_protected(int intno, int is_int, int error_code,
583 unsigned int next_eip, int is_hw)
584{
585 SegmentCache *dt;
14ce26e7 586 target_ulong ptr, ssp;
891b38e4 587 int type, dpl, selector, ss_dpl, cpl, sp_mask;
2c0262af 588 int has_error_code, new_stack, shift;
891b38e4
FB		 589 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
590 uint32_t old_eip;
2c0262af 591
7e84c249
FB		 592 has_error_code = 0;
593 if (!is_int && !is_hw) {
594 switch(intno) {
595 case 8:
596 case 10:
597 case 11:
598 case 12:
599 case 13:
600 case 14:
601 case 17:
602 has_error_code = 1;
603 break;
604 }
605 }
883da8e2
FB		 606 if (is_int)
607 old_eip = next_eip;
608 else
609 old_eip = env->eip;
7e84c249 610
2c0262af
FB		 611 dt = &env->idt;
612 if (intno * 8 + 7 > dt->limit)
613 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
614 ptr = dt->base + intno * 8;
61382a50
FB		 615 e1 = ldl_kernel(ptr);
616 e2 = ldl_kernel(ptr + 4);
2c0262af
FB		 617 /* check gate type */
618 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
619 switch(type) {
620 case 5: /* task gate */
7e84c249
FB		 621 /* must do that check here to return the correct error code */
622 if (!(e2 & DESC_P_MASK))
623 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
883da8e2 624 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
7e84c249 625 if (has_error_code) {
3f20e1dd 626 int mask, type;
7e84c249 627 /* push the error code */
3f20e1dd
FB		 628 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
629 shift = type >> 3;
7e84c249
FB		 630 if (env->segs[R_SS].flags & DESC_B_MASK)
631 mask = 0xffffffff;
632 else
633 mask = 0xffff;
0d1a29f9 634 esp = (ESP - (2 << shift)) & mask;
7e84c249
FB		 635 ssp = env->segs[R_SS].base + esp;
636 if (shift)
637 stl_kernel(ssp, error_code);
638 else
639 stw_kernel(ssp, error_code);
0d1a29f9 640 ESP = (esp & mask) | (ESP & ~mask);
7e84c249
FB		 641 }
642 return;
2c0262af
FB		 643 case 6: /* 286 interrupt gate */
644 case 7: /* 286 trap gate */
645 case 14: /* 386 interrupt gate */
646 case 15: /* 386 trap gate */
647 break;
648 default:
649 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
650 break;
651 }
652 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
653 cpl = env->hflags & HF_CPL_MASK;
654 /* check privledge if software int */
655 if (is_int && dpl < cpl)
656 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
657 /* check valid bit */
658 if (!(e2 & DESC_P_MASK))
659 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
660 selector = e1 >> 16;
661 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
662 if ((selector & 0xfffc) == 0)
663 raise_exception_err(EXCP0D_GPF, 0);
664
665 if (load_segment(&e1, &e2, selector) != 0)
666 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
667 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
668 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
669 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
670 if (dpl > cpl)
671 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
672 if (!(e2 & DESC_P_MASK))
673 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
674 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
675 /* to inner priviledge */
676 get_ss_esp_from_tss(&ss, &esp, dpl);
677 if ((ss & 0xfffc) == 0)
678 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
679 if ((ss & 3) != dpl)
680 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
681 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
682 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
683 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
684 if (ss_dpl != dpl)
685 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
686 if (!(ss_e2 & DESC_S_MASK) ||
687 (ss_e2 & DESC_CS_MASK) ||
688 !(ss_e2 & DESC_W_MASK))
689 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
690 if (!(ss_e2 & DESC_P_MASK))
691 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
692 new_stack = 1;
891b38e4
FB		 693 sp_mask = get_sp_mask(ss_e2);
694 ssp = get_seg_base(ss_e1, ss_e2);
2c0262af
FB		 695 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
696 /* to same priviledge */
8e682019
FB		 697 if (env->eflags & VM_MASK)
698 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2c0262af 699 new_stack = 0;
891b38e4
FB		 700 sp_mask = get_sp_mask(env->segs[R_SS].flags);
701 ssp = env->segs[R_SS].base;
702 esp = ESP;
4796f5e9 703 dpl = cpl;
2c0262af
FB		 704 } else {
705 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
706 new_stack = 0; /* avoid warning */
891b38e4 707 sp_mask = 0; /* avoid warning */
14ce26e7 708 ssp = 0; /* avoid warning */
891b38e4 709 esp = 0; /* avoid warning */
2c0262af
FB		 710 }
711
712 shift = type >> 3;
891b38e4
FB		 713
714#if 0
715 /* XXX: check that enough room is available */
2c0262af
FB		 716 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
717 if (env->eflags & VM_MASK)
718 push_size += 8;
719 push_size <<= shift;
891b38e4 720#endif
2c0262af 721 if (shift == 1) {
2c0262af 722 if (new_stack) {
8e682019
FB		 723 if (env->eflags & VM_MASK) {
724 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
725 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
726 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
727 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
728 }
891b38e4
FB		 729 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
730 PUSHL(ssp, esp, sp_mask, ESP);
2c0262af 731 }
891b38e4
FB		 732 PUSHL(ssp, esp, sp_mask, compute_eflags());
733 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
734 PUSHL(ssp, esp, sp_mask, old_eip);
2c0262af 735 if (has_error_code) {
891b38e4 736 PUSHL(ssp, esp, sp_mask, error_code);
2c0262af
FB		 737 }
738 } else {
739 if (new_stack) {
8e682019
FB		 740 if (env->eflags & VM_MASK) {
741 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
742 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
743 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
744 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
745 }
891b38e4
FB		 746 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
747 PUSHW(ssp, esp, sp_mask, ESP);
2c0262af 748 }
891b38e4
FB		 749 PUSHW(ssp, esp, sp_mask, compute_eflags());
750 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
751 PUSHW(ssp, esp, sp_mask, old_eip);
2c0262af 752 if (has_error_code) {
891b38e4 753 PUSHW(ssp, esp, sp_mask, error_code);
2c0262af
FB		 754 }
755 }
756
891b38e4 757 if (new_stack) {
8e682019 758 if (env->eflags & VM_MASK) {
14ce26e7
FB		 759 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
760 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
761 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
762 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
8e682019 763 }
891b38e4
FB		 764 ss = (ss & ~3) | dpl;
765 cpu_x86_load_seg_cache(env, R_SS, ss,
766 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
767 }
768 ESP = (ESP & ~sp_mask) | (esp & sp_mask);
769
770 selector = (selector & ~3) | dpl;
771 cpu_x86_load_seg_cache(env, R_CS, selector,
772 get_seg_base(e1, e2),
773 get_seg_limit(e1, e2),
774 e2);
775 cpu_x86_set_cpl(env, dpl);
776 env->eip = offset;
777
2c0262af
FB		 778 /* interrupt gate clear IF mask */
779 if ((type & 1) == 0) {
780 env->eflags &= ~IF_MASK;
781 }
782 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
783}
784
14ce26e7
FB		 785#ifdef TARGET_X86_64
786
787#define PUSHQ(sp, val)\
788{\
789 sp -= 8;\
790 stq_kernel(sp, (val));\
791}
792
793#define POPQ(sp, val)\
794{\
795 val = ldq_kernel(sp);\
796 sp += 8;\
797}
798
799static inline target_ulong get_rsp_from_tss(int level)
800{
801 int index;
802
803#if 0
804 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
805 env->tr.base, env->tr.limit);
806#endif
807
808 if (!(env->tr.flags & DESC_P_MASK))
809 cpu_abort(env, "invalid tss");
810 index = 8 * level + 4;
811 if ((index + 7) > env->tr.limit)
812 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
813 return ldq_kernel(env->tr.base + index);
814}
815
816/* 64 bit interrupt */
817static void do_interrupt64(int intno, int is_int, int error_code,
818 target_ulong next_eip, int is_hw)
819{
820 SegmentCache *dt;
821 target_ulong ptr;
822 int type, dpl, selector, cpl, ist;
823 int has_error_code, new_stack;
824 uint32_t e1, e2, e3, ss;
825 target_ulong old_eip, esp, offset;
826
827 has_error_code = 0;
828 if (!is_int && !is_hw) {
829 switch(intno) {
830 case 8:
831 case 10:
832 case 11:
833 case 12:
834 case 13:
835 case 14:
836 case 17:
837 has_error_code = 1;
838 break;
839 }
840 }
841 if (is_int)
842 old_eip = next_eip;
843 else
844 old_eip = env->eip;
845
846 dt = &env->idt;
847 if (intno * 16 + 15 > dt->limit)
848 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
849 ptr = dt->base + intno * 16;
850 e1 = ldl_kernel(ptr);
851 e2 = ldl_kernel(ptr + 4);
852 e3 = ldl_kernel(ptr + 8);
853 /* check gate type */
854 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
855 switch(type) {
856 case 14: /* 386 interrupt gate */
857 case 15: /* 386 trap gate */
858 break;
859 default:
860 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
861 break;
862 }
863 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
864 cpl = env->hflags & HF_CPL_MASK;
865 /* check privledge if software int */
866 if (is_int && dpl < cpl)
867 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
868 /* check valid bit */
869 if (!(e2 & DESC_P_MASK))
870 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
871 selector = e1 >> 16;
872 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
873 ist = e2 & 7;
874 if ((selector & 0xfffc) == 0)
875 raise_exception_err(EXCP0D_GPF, 0);
876
877 if (load_segment(&e1, &e2, selector) != 0)
878 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
879 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
880 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
881 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
882 if (dpl > cpl)
883 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
884 if (!(e2 & DESC_P_MASK))
885 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
886 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
887 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
888 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
889 /* to inner priviledge */
890 if (ist != 0)
891 esp = get_rsp_from_tss(ist + 3);
892 else
893 esp = get_rsp_from_tss(dpl);
9540a78b 894 esp &= ~0xfLL; /* align stack */
14ce26e7
FB		 895 ss = 0;
896 new_stack = 1;
897 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
898 /* to same priviledge */
899 if (env->eflags & VM_MASK)
900 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
901 new_stack = 0;
9540a78b
FB		 902 if (ist != 0)
903 esp = get_rsp_from_tss(ist + 3);
904 else
905 esp = ESP;
906 esp &= ~0xfLL; /* align stack */
14ce26e7
FB		 907 dpl = cpl;
908 } else {
909 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
910 new_stack = 0; /* avoid warning */
911 esp = 0; /* avoid warning */
912 }
913
914 PUSHQ(esp, env->segs[R_SS].selector);
915 PUSHQ(esp, ESP);
916 PUSHQ(esp, compute_eflags());
917 PUSHQ(esp, env->segs[R_CS].selector);
918 PUSHQ(esp, old_eip);
919 if (has_error_code) {
920 PUSHQ(esp, error_code);
921 }
922
923 if (new_stack) {
924 ss = 0 | dpl;
925 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
926 }
927 ESP = esp;
928
929 selector = (selector & ~3) | dpl;
930 cpu_x86_load_seg_cache(env, R_CS, selector,
931 get_seg_base(e1, e2),
932 get_seg_limit(e1, e2),
933 e2);
934 cpu_x86_set_cpl(env, dpl);
935 env->eip = offset;
936
937 /* interrupt gate clear IF mask */
938 if ((type & 1) == 0) {
939 env->eflags &= ~IF_MASK;
940 }
941 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
942}
f419b321 943#endif
14ce26e7 944
06c2f506 945void helper_syscall(int next_eip_addend)
14ce26e7
FB		 946{
947 int selector;
948
949 if (!(env->efer & MSR_EFER_SCE)) {
950 raise_exception_err(EXCP06_ILLOP, 0);
951 }
952 selector = (env->star >> 32) & 0xffff;
f419b321 953#ifdef TARGET_X86_64
14ce26e7 954 if (env->hflags & HF_LMA_MASK) {
9540a78b
FB		 955 int code64;
956
06c2f506 957 ECX = env->eip + next_eip_addend;
14ce26e7 958 env->regs[11] = compute_eflags();
9540a78b
FB		 959
960 code64 = env->hflags & HF_CS64_MASK;
14ce26e7
FB		 961
962 cpu_x86_set_cpl(env, 0);
963 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
964 0, 0xffffffff,
965 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
966 DESC_S_MASK |
967 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
968 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
969 0, 0xffffffff,
970 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
971 DESC_S_MASK |
972 DESC_W_MASK | DESC_A_MASK);
973 env->eflags &= ~env->fmask;
9540a78b 974 if (code64)
14ce26e7
FB		 975 env->eip = env->lstar;
976 else
977 env->eip = env->cstar;
f419b321
FB		 978 } else
979#endif
980 {
06c2f506 981 ECX = (uint32_t)(env->eip + next_eip_addend);
14ce26e7
FB		 982
983 cpu_x86_set_cpl(env, 0);
984 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
985 0, 0xffffffff,
986 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
987 DESC_S_MASK |
988 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
989 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
990 0, 0xffffffff,
991 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
992 DESC_S_MASK |
993 DESC_W_MASK | DESC_A_MASK);
994 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
995 env->eip = (uint32_t)env->star;
996 }
997}
998
999void helper_sysret(int dflag)
1000{
1001 int cpl, selector;
1002
f419b321
FB		 1003 if (!(env->efer & MSR_EFER_SCE)) {
1004 raise_exception_err(EXCP06_ILLOP, 0);
1005 }
14ce26e7
FB		 1006 cpl = env->hflags & HF_CPL_MASK;
1007 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1008 raise_exception_err(EXCP0D_GPF, 0);
1009 }
1010 selector = (env->star >> 48) & 0xffff;
f419b321 1011#ifdef TARGET_X86_64
14ce26e7
FB		 1012 if (env->hflags & HF_LMA_MASK) {
1013 if (dflag == 2) {
1014 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1015 0, 0xffffffff,
1016 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1017 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1018 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1019 DESC_L_MASK);
1020 env->eip = ECX;
1021 } else {
1022 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1023 0, 0xffffffff,
1024 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1025 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1026 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1027 env->eip = (uint32_t)ECX;
1028 }
1029 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1030 0, 0xffffffff,
1031 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1032 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1033 DESC_W_MASK | DESC_A_MASK);
31313213
FB		 1034 load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1035 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
14ce26e7 1036 cpu_x86_set_cpl(env, 3);
f419b321
FB		 1037 } else
1038#endif
1039 {
14ce26e7
FB		 1040 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1041 0, 0xffffffff,
1042 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1043 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1044 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1045 env->eip = (uint32_t)ECX;
1046 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1047 0, 0xffffffff,
1048 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1049 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1050 DESC_W_MASK | DESC_A_MASK);
1051 env->eflags |= IF_MASK;
1052 cpu_x86_set_cpl(env, 3);
1053 }
f419b321
FB		 1054#ifdef USE_KQEMU
1055 if (kqemu_is_ok(env)) {
1056 if (env->hflags & HF_LMA_MASK)
1057 CC_OP = CC_OP_EFLAGS;
1058 env->exception_index = -1;
1059 cpu_loop_exit();
1060 }
14ce26e7 1061#endif
f419b321 1062}
14ce26e7 1063
2c0262af
FB		 1064/* real mode interrupt */
1065static void do_interrupt_real(int intno, int is_int, int error_code,
4136f33c 1066 unsigned int next_eip)
2c0262af
FB		 1067{
1068 SegmentCache *dt;
14ce26e7 1069 target_ulong ptr, ssp;
2c0262af
FB		 1070 int selector;
1071 uint32_t offset, esp;
1072 uint32_t old_cs, old_eip;
1073
1074 /* real mode (simpler !) */
1075 dt = &env->idt;
1076 if (intno * 4 + 3 > dt->limit)
1077 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1078 ptr = dt->base + intno * 4;
61382a50
FB		 1079 offset = lduw_kernel(ptr);
1080 selector = lduw_kernel(ptr + 2);
2c0262af
FB		 1081 esp = ESP;
1082 ssp = env->segs[R_SS].base;
1083 if (is_int)
1084 old_eip = next_eip;
1085 else
1086 old_eip = env->eip;
1087 old_cs = env->segs[R_CS].selector;
891b38e4
FB		 1088 /* XXX: use SS segment size ? */
1089 PUSHW(ssp, esp, 0xffff, compute_eflags());
1090 PUSHW(ssp, esp, 0xffff, old_cs);
1091 PUSHW(ssp, esp, 0xffff, old_eip);
2c0262af
FB		 1092
1093 /* update processor state */
1094 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1095 env->eip = offset;
1096 env->segs[R_CS].selector = selector;
14ce26e7 1097 env->segs[R_CS].base = (selector << 4);
2c0262af
FB		 1098 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1099}
1100
1101/* fake user mode interrupt */
1102void do_interrupt_user(int intno, int is_int, int error_code,
14ce26e7 1103 target_ulong next_eip)
2c0262af
FB		 1104{
1105 SegmentCache *dt;
14ce26e7 1106 target_ulong ptr;
2c0262af
FB		 1107 int dpl, cpl;
1108 uint32_t e2;
1109
1110 dt = &env->idt;
1111 ptr = dt->base + (intno * 8);
61382a50 1112 e2 = ldl_kernel(ptr + 4);
2c0262af
FB		 1113
1114 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1115 cpl = env->hflags & HF_CPL_MASK;
1116 /* check privledge if software int */
1117 if (is_int && dpl < cpl)
1118 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1119
1120 /* Since we emulate only user space, we cannot do more than
1121 exiting the emulation with the suitable exception and error
1122 code */
1123 if (is_int)
1124 EIP = next_eip;
1125}
1126
1127/*
e19e89a5 1128 * Begin execution of an interruption. is_int is TRUE if coming from
2c0262af
FB		 1129 * the int instruction. next_eip is the EIP value AFTER the interrupt
1130 * instruction. It is only relevant if is_int is TRUE.
1131 */
1132void do_interrupt(int intno, int is_int, int error_code,
14ce26e7 1133 target_ulong next_eip, int is_hw)
2c0262af 1134{
1247c5f7 1135 if (loglevel & CPU_LOG_INT) {
e19e89a5
FB		 1136 if ((env->cr[0] & CR0_PE_MASK)) {
1137 static int count;
14ce26e7 1138 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
dc6f57fd
FB		 1139 count, intno, error_code, is_int,
1140 env->hflags & HF_CPL_MASK,
1141 env->segs[R_CS].selector, EIP,
2ee73ac3 1142 (int)env->segs[R_CS].base + EIP,
8145122b
FB		 1143 env->segs[R_SS].selector, ESP);
1144 if (intno == 0x0e) {
14ce26e7 1145 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
8145122b 1146 } else {
14ce26e7 1147 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
8145122b 1148 }
e19e89a5 1149 fprintf(logfile, "\n");
06c2f506 1150 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1247c5f7 1151#if 0
e19e89a5
FB		 1152 {
1153 int i;
1154 uint8_t *ptr;
1155 fprintf(logfile, " code=");
1156 ptr = env->segs[R_CS].base + env->eip;
1157 for(i = 0; i < 16; i++) {
1158 fprintf(logfile, " %02x", ldub(ptr + i));
dc6f57fd 1159 }
e19e89a5 1160 fprintf(logfile, "\n");
dc6f57fd 1161 }
8e682019 1162#endif
e19e89a5 1163 count++;
4136f33c 1164 }
4136f33c 1165 }
2c0262af 1166 if (env->cr[0] & CR0_PE_MASK) {
14ce26e7
FB		 1167#if TARGET_X86_64
1168 if (env->hflags & HF_LMA_MASK) {
1169 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1170 } else
1171#endif
1172 {
1173 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1174 }
2c0262af
FB		 1175 } else {
1176 do_interrupt_real(intno, is_int, error_code, next_eip);
1177 }
1178}
1179
1180/*
1181 * Signal an interruption. It is executed in the main CPU loop.
1182 * is_int is TRUE if coming from the int instruction. next_eip is the
1183 * EIP value AFTER the interrupt instruction. It is only relevant if
1184 * is_int is TRUE.
1185 */
1186void raise_interrupt(int intno, int is_int, int error_code,
a8ede8ba 1187 int next_eip_addend)
2c0262af
FB		 1188{
1189 env->exception_index = intno;
1190 env->error_code = error_code;
1191 env->exception_is_int = is_int;
a8ede8ba 1192 env->exception_next_eip = env->eip + next_eip_addend;
2c0262af
FB		 1193 cpu_loop_exit();
1194}
1195
0d1a29f9
FB		 1196/* same as raise_exception_err, but do not restore global registers */
1197static void raise_exception_err_norestore(int exception_index, int error_code)
1198{
1199 env->exception_index = exception_index;
1200 env->error_code = error_code;
1201 env->exception_is_int = 0;
1202 env->exception_next_eip = 0;
1203 longjmp(env->jmp_env, 1);
1204}
1205
2c0262af 1206/* shortcuts to generate exceptions */
8145122b
FB		 1207
1208void (raise_exception_err)(int exception_index, int error_code)
2c0262af
FB		 1209{
1210 raise_interrupt(exception_index, 0, error_code, 0);
1211}
1212
1213void raise_exception(int exception_index)
1214{
1215 raise_interrupt(exception_index, 0, 0, 0);
1216}
1217
3b21e03e
FB		 1218/* SMM support */
1219
74ce674f
FB		 1220#if defined(CONFIG_USER_ONLY)
1221
1222void do_smm_enter(void)
1223{
1224}
1225
1226void helper_rsm(void)
1227{
1228}
1229
1230#else
1231
3b21e03e
FB		 1232#ifdef TARGET_X86_64
1233#define SMM_REVISION_ID 0x00020064
1234#else
1235#define SMM_REVISION_ID 0x00020000
1236#endif
1237
1238void do_smm_enter(void)
1239{
1240 target_ulong sm_state;
1241 SegmentCache *dt;
1242 int i, offset;
1243
1244 if (loglevel & CPU_LOG_INT) {
1245 fprintf(logfile, "SMM: enter\n");
1246 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1247 }
1248
1249 env->hflags |= HF_SMM_MASK;
1250 cpu_smm_update(env);
1251
1252 sm_state = env->smbase + 0x8000;
1253
1254#ifdef TARGET_X86_64
1255 for(i = 0; i < 6; i++) {
1256 dt = &env->segs[i];
1257 offset = 0x7e00 + i * 16;
1258 stw_phys(sm_state + offset, dt->selector);
1259 stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1260 stl_phys(sm_state + offset + 4, dt->limit);
1261 stq_phys(sm_state + offset + 8, dt->base);
1262 }
1263
1264 stq_phys(sm_state + 0x7e68, env->gdt.base);
1265 stl_phys(sm_state + 0x7e64, env->gdt.limit);
1266
1267 stw_phys(sm_state + 0x7e70, env->ldt.selector);
1268 stq_phys(sm_state + 0x7e78, env->ldt.base);
1269 stl_phys(sm_state + 0x7e74, env->ldt.limit);
1270 stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1271
1272 stq_phys(sm_state + 0x7e88, env->idt.base);
1273 stl_phys(sm_state + 0x7e84, env->idt.limit);
1274
1275 stw_phys(sm_state + 0x7e90, env->tr.selector);
1276 stq_phys(sm_state + 0x7e98, env->tr.base);
1277 stl_phys(sm_state + 0x7e94, env->tr.limit);
1278 stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1279
1280 stq_phys(sm_state + 0x7ed0, env->efer);
1281
1282 stq_phys(sm_state + 0x7ff8, EAX);
1283 stq_phys(sm_state + 0x7ff0, ECX);
1284 stq_phys(sm_state + 0x7fe8, EDX);
1285 stq_phys(sm_state + 0x7fe0, EBX);
1286 stq_phys(sm_state + 0x7fd8, ESP);
1287 stq_phys(sm_state + 0x7fd0, EBP);
1288 stq_phys(sm_state + 0x7fc8, ESI);
1289 stq_phys(sm_state + 0x7fc0, EDI);
1290 for(i = 8; i < 16; i++)
1291 stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1292 stq_phys(sm_state + 0x7f78, env->eip);
1293 stl_phys(sm_state + 0x7f70, compute_eflags());
1294 stl_phys(sm_state + 0x7f68, env->dr[6]);
1295 stl_phys(sm_state + 0x7f60, env->dr[7]);
1296
1297 stl_phys(sm_state + 0x7f48, env->cr[4]);
1298 stl_phys(sm_state + 0x7f50, env->cr[3]);
1299 stl_phys(sm_state + 0x7f58, env->cr[0]);
1300
1301 stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1302 stl_phys(sm_state + 0x7f00, env->smbase);
1303#else
1304 stl_phys(sm_state + 0x7ffc, env->cr[0]);
1305 stl_phys(sm_state + 0x7ff8, env->cr[3]);
1306 stl_phys(sm_state + 0x7ff4, compute_eflags());
1307 stl_phys(sm_state + 0x7ff0, env->eip);
1308 stl_phys(sm_state + 0x7fec, EDI);
1309 stl_phys(sm_state + 0x7fe8, ESI);
1310 stl_phys(sm_state + 0x7fe4, EBP);
1311 stl_phys(sm_state + 0x7fe0, ESP);
1312 stl_phys(sm_state + 0x7fdc, EBX);
1313 stl_phys(sm_state + 0x7fd8, EDX);
1314 stl_phys(sm_state + 0x7fd4, ECX);
1315 stl_phys(sm_state + 0x7fd0, EAX);
1316 stl_phys(sm_state + 0x7fcc, env->dr[6]);
1317 stl_phys(sm_state + 0x7fc8, env->dr[7]);
1318
1319 stl_phys(sm_state + 0x7fc4, env->tr.selector);
1320 stl_phys(sm_state + 0x7f64, env->tr.base);
1321 stl_phys(sm_state + 0x7f60, env->tr.limit);
1322 stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1323
1324 stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1325 stl_phys(sm_state + 0x7f80, env->ldt.base);
1326 stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1327 stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1328
1329 stl_phys(sm_state + 0x7f74, env->gdt.base);
1330 stl_phys(sm_state + 0x7f70, env->gdt.limit);
1331
1332 stl_phys(sm_state + 0x7f58, env->idt.base);
1333 stl_phys(sm_state + 0x7f54, env->idt.limit);
1334
1335 for(i = 0; i < 6; i++) {
1336 dt = &env->segs[i];
1337 if (i < 3)
1338 offset = 0x7f84 + i * 12;
1339 else
1340 offset = 0x7f2c + (i - 3) * 12;
1341 stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1342 stl_phys(sm_state + offset + 8, dt->base);
1343 stl_phys(sm_state + offset + 4, dt->limit);
1344 stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1345 }
1346 stl_phys(sm_state + 0x7f14, env->cr[4]);
1347
1348 stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1349 stl_phys(sm_state + 0x7ef8, env->smbase);
1350#endif
1351 /* init SMM cpu state */
1352
8988ae89
FB		 1353#ifdef TARGET_X86_64
1354 env->efer = 0;
1355 env->hflags &= ~HF_LMA_MASK;
1356#endif
3b21e03e
FB		 1357 load_eflags(0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1358 env->eip = 0x00008000;
1359 cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1360 0xffffffff, 0);
1361 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1362 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1363 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1364 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1365 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1366
1367 cpu_x86_update_cr0(env,
1368 env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK));
1369 cpu_x86_update_cr4(env, 0);
1370 env->dr[7] = 0x00000400;
3b21e03e
FB		 1371 CC_OP = CC_OP_EFLAGS;
1372}
1373
1374void helper_rsm(void)
1375{
1376 target_ulong sm_state;
1377 int i, offset;
1378 uint32_t val;
1379
1380 sm_state = env->smbase + 0x8000;
1381#ifdef TARGET_X86_64
8988ae89
FB		 1382 env->efer = ldq_phys(sm_state + 0x7ed0);
1383 if (env->efer & MSR_EFER_LMA)
1384 env->hflags |= HF_LMA_MASK;
1385 else
1386 env->hflags &= ~HF_LMA_MASK;
1387
3b21e03e
FB		 1388 for(i = 0; i < 6; i++) {
1389 offset = 0x7e00 + i * 16;
1390 cpu_x86_load_seg_cache(env, i,
1391 lduw_phys(sm_state + offset),
1392 ldq_phys(sm_state + offset + 8),
1393 ldl_phys(sm_state + offset + 4),
1394 (lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1395 }
1396
1397 env->gdt.base = ldq_phys(sm_state + 0x7e68);
1398 env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1399
1400 env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1401 env->ldt.base = ldq_phys(sm_state + 0x7e78);
1402 env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1403 env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1404
1405 env->idt.base = ldq_phys(sm_state + 0x7e88);
1406 env->idt.limit = ldl_phys(sm_state + 0x7e84);
1407
1408 env->tr.selector = lduw_phys(sm_state + 0x7e90);
1409 env->tr.base = ldq_phys(sm_state + 0x7e98);
1410 env->tr.limit = ldl_phys(sm_state + 0x7e94);
1411 env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1412
3b21e03e
FB		 1413 EAX = ldq_phys(sm_state + 0x7ff8);
1414 ECX = ldq_phys(sm_state + 0x7ff0);
1415 EDX = ldq_phys(sm_state + 0x7fe8);
1416 EBX = ldq_phys(sm_state + 0x7fe0);
1417 ESP = ldq_phys(sm_state + 0x7fd8);
1418 EBP = ldq_phys(sm_state + 0x7fd0);
1419 ESI = ldq_phys(sm_state + 0x7fc8);
1420 EDI = ldq_phys(sm_state + 0x7fc0);
1421 for(i = 8; i < 16; i++)
1422 env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1423 env->eip = ldq_phys(sm_state + 0x7f78);
1424 load_eflags(ldl_phys(sm_state + 0x7f70),
1425 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1426 env->dr[6] = ldl_phys(sm_state + 0x7f68);
1427 env->dr[7] = ldl_phys(sm_state + 0x7f60);
1428
1429 cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1430 cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1431 cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1432
1433 val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1434 if (val & 0x20000) {
1435 env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1436 }
1437#else
1438 cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1439 cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1440 load_eflags(ldl_phys(sm_state + 0x7ff4),
1441 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1442 env->eip = ldl_phys(sm_state + 0x7ff0);
1443 EDI = ldl_phys(sm_state + 0x7fec);
1444 ESI = ldl_phys(sm_state + 0x7fe8);
1445 EBP = ldl_phys(sm_state + 0x7fe4);
1446 ESP = ldl_phys(sm_state + 0x7fe0);
1447 EBX = ldl_phys(sm_state + 0x7fdc);
1448 EDX = ldl_phys(sm_state + 0x7fd8);
1449 ECX = ldl_phys(sm_state + 0x7fd4);
1450 EAX = ldl_phys(sm_state + 0x7fd0);
1451 env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1452 env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1453
1454 env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1455 env->tr.base = ldl_phys(sm_state + 0x7f64);
1456 env->tr.limit = ldl_phys(sm_state + 0x7f60);
1457 env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1458
1459 env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1460 env->ldt.base = ldl_phys(sm_state + 0x7f80);
1461 env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1462 env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1463
1464 env->gdt.base = ldl_phys(sm_state + 0x7f74);
1465 env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1466
1467 env->idt.base = ldl_phys(sm_state + 0x7f58);
1468 env->idt.limit = ldl_phys(sm_state + 0x7f54);
1469
1470 for(i = 0; i < 6; i++) {
1471 if (i < 3)
1472 offset = 0x7f84 + i * 12;
1473 else
1474 offset = 0x7f2c + (i - 3) * 12;
1475 cpu_x86_load_seg_cache(env, i,
1476 ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1477 ldl_phys(sm_state + offset + 8),
1478 ldl_phys(sm_state + offset + 4),
1479 (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1480 }
1481 cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1482
1483 val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1484 if (val & 0x20000) {
1485 env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1486 }
1487#endif
1488 CC_OP = CC_OP_EFLAGS;
1489 env->hflags &= ~HF_SMM_MASK;
1490 cpu_smm_update(env);
1491
1492 if (loglevel & CPU_LOG_INT) {
1493 fprintf(logfile, "SMM: after RSM\n");
1494 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1495 }
1496}
1497
74ce674f
FB		 1498#endif /* !CONFIG_USER_ONLY */
1499
1500
2c0262af
FB		 1501#ifdef BUGGY_GCC_DIV64
1502/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1503 call it from another function */
45bbbb46 1504uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
2c0262af
FB		 1505{
1506 *q_ptr = num / den;
1507 return num % den;
1508}
1509
45bbbb46 1510int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
2c0262af
FB		 1511{
1512 *q_ptr = num / den;
1513 return num % den;
1514}
1515#endif
1516
14ce26e7 1517void helper_divl_EAX_T0(void)
2c0262af 1518{
45bbbb46
FB		 1519 unsigned int den, r;
1520 uint64_t num, q;
2c0262af 1521
31313213 1522 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2c0262af
FB		 1523 den = T0;
1524 if (den == 0) {
2c0262af
FB		 1525 raise_exception(EXCP00_DIVZ);
1526 }
1527#ifdef BUGGY_GCC_DIV64
14ce26e7 1528 r = div32(&q, num, den);
2c0262af
FB		 1529#else
1530 q = (num / den);
1531 r = (num % den);
1532#endif
45bbbb46
FB		 1533 if (q > 0xffffffff)
1534 raise_exception(EXCP00_DIVZ);
14ce26e7
FB		 1535 EAX = (uint32_t)q;
1536 EDX = (uint32_t)r;
2c0262af
FB		 1537}
1538
14ce26e7 1539void helper_idivl_EAX_T0(void)
2c0262af 1540{
45bbbb46
FB		 1541 int den, r;
1542 int64_t num, q;
2c0262af 1543
31313213 1544 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2c0262af
FB		 1545 den = T0;
1546 if (den == 0) {
2c0262af
FB		 1547 raise_exception(EXCP00_DIVZ);
1548 }
1549#ifdef BUGGY_GCC_DIV64
14ce26e7 1550 r = idiv32(&q, num, den);
2c0262af
FB		 1551#else
1552 q = (num / den);
1553 r = (num % den);
1554#endif
45bbbb46
FB		 1555 if (q != (int32_t)q)
1556 raise_exception(EXCP00_DIVZ);
14ce26e7
FB		 1557 EAX = (uint32_t)q;
1558 EDX = (uint32_t)r;
2c0262af
FB		 1559}
1560
1561void helper_cmpxchg8b(void)
1562{
1563 uint64_t d;
1564 int eflags;
1565
1566 eflags = cc_table[CC_OP].compute_all();
14ce26e7 1567 d = ldq(A0);
2c0262af 1568 if (d == (((uint64_t)EDX << 32) | EAX)) {
14ce26e7 1569 stq(A0, ((uint64_t)ECX << 32) | EBX);
2c0262af
FB		 1570 eflags |= CC_Z;
1571 } else {
1572 EDX = d >> 32;
1573 EAX = d;
1574 eflags &= ~CC_Z;
1575 }
1576 CC_SRC = eflags;
1577}
1578
2c0262af
FB		 1579void helper_cpuid(void)
1580{
f419b321
FB		 1581 uint32_t index;
1582 index = (uint32_t)EAX;
1583
1584 /* test if maximum index reached */
1585 if (index & 0x80000000) {
1586 if (index > env->cpuid_xlevel)
1587 index = env->cpuid_level;
1588 } else {
1589 if (index > env->cpuid_level)
1590 index = env->cpuid_level;
1591 }
1592
1593 switch(index) {
8e682019 1594 case 0:
f419b321 1595 EAX = env->cpuid_level;
14ce26e7
FB		 1596 EBX = env->cpuid_vendor1;
1597 EDX = env->cpuid_vendor2;
1598 ECX = env->cpuid_vendor3;
8e682019
FB		 1599 break;
1600 case 1:
14ce26e7 1601 EAX = env->cpuid_version;
1f3358c8 1602 EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
9df217a3 1603 ECX = env->cpuid_ext_features;
14ce26e7 1604 EDX = env->cpuid_features;
8e682019 1605 break;
f419b321 1606 case 2:
8e682019
FB		 1607 /* cache info: needed for Pentium Pro compatibility */
1608 EAX = 0x410601;
2c0262af
FB		 1609 EBX = 0;
1610 ECX = 0;
8e682019
FB		 1611 EDX = 0;
1612 break;
14ce26e7 1613 case 0x80000000:
f419b321 1614 EAX = env->cpuid_xlevel;
14ce26e7
FB		 1615 EBX = env->cpuid_vendor1;
1616 EDX = env->cpuid_vendor2;
1617 ECX = env->cpuid_vendor3;
1618 break;
1619 case 0x80000001:
1620 EAX = env->cpuid_features;
1621 EBX = 0;
1622 ECX = 0;
f419b321
FB		 1623 EDX = env->cpuid_ext2_features;
1624 break;
1625 case 0x80000002:
1626 case 0x80000003:
1627 case 0x80000004:
1628 EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1629 EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1630 ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1631 EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
14ce26e7 1632 break;
8f091a59
FB		 1633 case 0x80000005:
1634 /* cache info (L1 cache) */
1635 EAX = 0x01ff01ff;
1636 EBX = 0x01ff01ff;
1637 ECX = 0x40020140;
1638 EDX = 0x40020140;
1639 break;
1640 case 0x80000006:
1641 /* cache info (L2 cache) */
1642 EAX = 0;
1643 EBX = 0x42004200;
1644 ECX = 0x02008140;
1645 EDX = 0;
1646 break;
14ce26e7
FB		 1647 case 0x80000008:
1648 /* virtual & phys address size in low 2 bytes. */
1649 EAX = 0x00003028;
1650 EBX = 0;
1651 ECX = 0;
1652 EDX = 0;
1653 break;
f419b321
FB		 1654 default:
1655 /* reserved values: zero */
1656 EAX = 0;
1657 EBX = 0;
1658 ECX = 0;
1659 EDX = 0;
1660 break;
2c0262af
FB		 1661 }
1662}
1663
61a8c4ec
FB		 1664void helper_enter_level(int level, int data32)
1665{
14ce26e7 1666 target_ulong ssp;
61a8c4ec
FB		 1667 uint32_t esp_mask, esp, ebp;
1668
1669 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1670 ssp = env->segs[R_SS].base;
1671 ebp = EBP;
1672 esp = ESP;
1673 if (data32) {
1674 /* 32 bit */
1675 esp -= 4;
1676 while (--level) {
1677 esp -= 4;
1678 ebp -= 4;
1679 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1680 }
1681 esp -= 4;
1682 stl(ssp + (esp & esp_mask), T1);
1683 } else {
1684 /* 16 bit */
1685 esp -= 2;
1686 while (--level) {
1687 esp -= 2;
1688 ebp -= 2;
1689 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1690 }
1691 esp -= 2;
1692 stw(ssp + (esp & esp_mask), T1);
1693 }
1694}
1695
8f091a59
FB		 1696#ifdef TARGET_X86_64
1697void helper_enter64_level(int level, int data64)
1698{
1699 target_ulong esp, ebp;
1700 ebp = EBP;
1701 esp = ESP;
1702
1703 if (data64) {
1704 /* 64 bit */
1705 esp -= 8;
1706 while (--level) {
1707 esp -= 8;
1708 ebp -= 8;
1709 stq(esp, ldq(ebp));
1710 }
1711 esp -= 8;
1712 stq(esp, T1);
1713 } else {
1714 /* 16 bit */
1715 esp -= 2;
1716 while (--level) {
1717 esp -= 2;
1718 ebp -= 2;
1719 stw(esp, lduw(ebp));
1720 }
1721 esp -= 2;
1722 stw(esp, T1);
1723 }
1724}
1725#endif
1726
2c0262af
FB		 1727void helper_lldt_T0(void)
1728{
1729 int selector;
1730 SegmentCache *dt;
1731 uint32_t e1, e2;
14ce26e7
FB		 1732 int index, entry_limit;
1733 target_ulong ptr;
2c0262af
FB		 1734
1735 selector = T0 & 0xffff;
1736 if ((selector & 0xfffc) == 0) {
1737 /* XXX: NULL selector case: invalid LDT */
14ce26e7 1738 env->ldt.base = 0;
2c0262af
FB		 1739 env->ldt.limit = 0;
1740 } else {
1741 if (selector & 0x4)
1742 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1743 dt = &env->gdt;
1744 index = selector & ~7;
14ce26e7
FB		 1745#ifdef TARGET_X86_64
1746 if (env->hflags & HF_LMA_MASK)
1747 entry_limit = 15;
1748 else
1749#endif
1750 entry_limit = 7;
1751 if ((index + entry_limit) > dt->limit)
2c0262af
FB		 1752 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1753 ptr = dt->base + index;
61382a50
FB		 1754 e1 = ldl_kernel(ptr);
1755 e2 = ldl_kernel(ptr + 4);
2c0262af
FB		 1756 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1757 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1758 if (!(e2 & DESC_P_MASK))
1759 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
14ce26e7
FB		 1760#ifdef TARGET_X86_64
1761 if (env->hflags & HF_LMA_MASK) {
1762 uint32_t e3;
1763 e3 = ldl_kernel(ptr + 8);
1764 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1765 env->ldt.base |= (target_ulong)e3 << 32;
1766 } else
1767#endif
1768 {
1769 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1770 }
2c0262af
FB		 1771 }
1772 env->ldt.selector = selector;
1773}
1774
1775void helper_ltr_T0(void)
1776{
1777 int selector;
1778 SegmentCache *dt;
1779 uint32_t e1, e2;
14ce26e7
FB		 1780 int index, type, entry_limit;
1781 target_ulong ptr;
2c0262af
FB		 1782
1783 selector = T0 & 0xffff;
1784 if ((selector & 0xfffc) == 0) {
14ce26e7
FB		 1785 /* NULL selector case: invalid TR */
1786 env->tr.base = 0;
2c0262af
FB		 1787 env->tr.limit = 0;
1788 env->tr.flags = 0;
1789 } else {
1790 if (selector & 0x4)
1791 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1792 dt = &env->gdt;
1793 index = selector & ~7;
14ce26e7
FB		 1794#ifdef TARGET_X86_64
1795 if (env->hflags & HF_LMA_MASK)
1796 entry_limit = 15;
1797 else
1798#endif
1799 entry_limit = 7;
1800 if ((index + entry_limit) > dt->limit)
2c0262af
FB		 1801 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1802 ptr = dt->base + index;
61382a50
FB		 1803 e1 = ldl_kernel(ptr);
1804 e2 = ldl_kernel(ptr + 4);
2c0262af
FB		 1805 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1806 if ((e2 & DESC_S_MASK) ||
7e84c249 1807 (type != 1 && type != 9))
2c0262af
FB		 1808 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1809 if (!(e2 & DESC_P_MASK))
1810 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
14ce26e7
FB		 1811#ifdef TARGET_X86_64
1812 if (env->hflags & HF_LMA_MASK) {
1813 uint32_t e3;
1814 e3 = ldl_kernel(ptr + 8);
1815 load_seg_cache_raw_dt(&env->tr, e1, e2);
1816 env->tr.base |= (target_ulong)e3 << 32;
1817 } else
1818#endif
1819 {
1820 load_seg_cache_raw_dt(&env->tr, e1, e2);
1821 }
8e682019 1822 e2 |= DESC_TSS_BUSY_MASK;
61382a50 1823 stl_kernel(ptr + 4, e2);
2c0262af
FB		 1824 }
1825 env->tr.selector = selector;
1826}
1827
3ab493de 1828/* only works if protected mode and not VM86. seg_reg must be != R_CS */
8e682019 1829void load_seg(int seg_reg, int selector)
2c0262af
FB		 1830{
1831 uint32_t e1, e2;
3ab493de
FB		 1832 int cpl, dpl, rpl;
1833 SegmentCache *dt;
1834 int index;
14ce26e7 1835 target_ulong ptr;
3ab493de 1836
8e682019 1837 selector &= 0xffff;
b359d4e7 1838 cpl = env->hflags & HF_CPL_MASK;
2c0262af
FB		 1839 if ((selector & 0xfffc) == 0) {
1840 /* null selector case */
4d6b6c0a
FB		 1841 if (seg_reg == R_SS
1842#ifdef TARGET_X86_64
b359d4e7 1843 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
4d6b6c0a
FB		 1844#endif
1845 )
2c0262af 1846 raise_exception_err(EXCP0D_GPF, 0);
14ce26e7 1847 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2c0262af 1848 } else {
3ab493de
FB		 1849
1850 if (selector & 0x4)
1851 dt = &env->ldt;
1852 else
1853 dt = &env->gdt;
1854 index = selector & ~7;
8e682019 1855 if ((index + 7) > dt->limit)
2c0262af 1856 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
3ab493de
FB		 1857 ptr = dt->base + index;
1858 e1 = ldl_kernel(ptr);
1859 e2 = ldl_kernel(ptr + 4);
14ce26e7 1860
8e682019 1861 if (!(e2 & DESC_S_MASK))
2c0262af 1862 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
3ab493de
FB		 1863 rpl = selector & 3;
1864 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2c0262af 1865 if (seg_reg == R_SS) {
3ab493de 1866 /* must be writable segment */
8e682019 1867 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
2c0262af 1868 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
8e682019 1869 if (rpl != cpl || dpl != cpl)
3ab493de 1870 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2c0262af 1871 } else {
3ab493de 1872 /* must be readable segment */
8e682019 1873 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
2c0262af 1874 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
3ab493de
FB		 1875
1876 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1877 /* if not conforming code, test rights */
89984cd2 1878 if (dpl < cpl || dpl < rpl)
3ab493de 1879 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
3ab493de 1880 }
2c0262af
FB		 1881 }
1882
1883 if (!(e2 & DESC_P_MASK)) {
2c0262af
FB		 1884 if (seg_reg == R_SS)
1885 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1886 else
1887 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1888 }
3ab493de
FB		 1889
1890 /* set the access bit if not already set */
1891 if (!(e2 & DESC_A_MASK)) {
1892 e2 |= DESC_A_MASK;
1893 stl_kernel(ptr + 4, e2);
1894 }
1895
2c0262af
FB		 1896 cpu_x86_load_seg_cache(env, seg_reg, selector,
1897 get_seg_base(e1, e2),
1898 get_seg_limit(e1, e2),
1899 e2);
1900#if 0
1901 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1902 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1903#endif
1904 }
1905}
1906
1907/* protected mode jump */
f419b321 1908void helper_ljmp_protected_T0_T1(int next_eip_addend)
2c0262af 1909{
14ce26e7 1910 int new_cs, gate_cs, type;
2c0262af 1911 uint32_t e1, e2, cpl, dpl, rpl, limit;
f419b321 1912 target_ulong new_eip, next_eip;
14ce26e7 1913
2c0262af
FB		 1914 new_cs = T0;
1915 new_eip = T1;
1916 if ((new_cs & 0xfffc) == 0)
1917 raise_exception_err(EXCP0D_GPF, 0);
1918 if (load_segment(&e1, &e2, new_cs) != 0)
1919 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1920 cpl = env->hflags & HF_CPL_MASK;
1921 if (e2 & DESC_S_MASK) {
1922 if (!(e2 & DESC_CS_MASK))
1923 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1924 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
7e84c249 1925 if (e2 & DESC_C_MASK) {
2c0262af
FB		 1926 /* conforming code segment */
1927 if (dpl > cpl)
1928 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1929 } else {
1930 /* non conforming code segment */
1931 rpl = new_cs & 3;
1932 if (rpl > cpl)
1933 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1934 if (dpl != cpl)
1935 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1936 }
1937 if (!(e2 & DESC_P_MASK))
1938 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1939 limit = get_seg_limit(e1, e2);
ca954f6d
FB		 1940 if (new_eip > limit &&
1941 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2c0262af
FB		 1942 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1943 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1944 get_seg_base(e1, e2), limit, e2);
1945 EIP = new_eip;
1946 } else {
7e84c249
FB		 1947 /* jump to call or task gate */
1948 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1949 rpl = new_cs & 3;
1950 cpl = env->hflags & HF_CPL_MASK;
1951 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1952 switch(type) {
1953 case 1: /* 286 TSS */
1954 case 9: /* 386 TSS */
1955 case 5: /* task gate */
1956 if (dpl < cpl || dpl < rpl)
1957 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
f419b321 1958 next_eip = env->eip + next_eip_addend;
08cea4ee 1959 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
447c2cef 1960 CC_OP = CC_OP_EFLAGS;
7e84c249
FB		 1961 break;
1962 case 4: /* 286 call gate */
1963 case 12: /* 386 call gate */
1964 if ((dpl < cpl) || (dpl < rpl))
1965 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1966 if (!(e2 & DESC_P_MASK))
1967 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1968 gate_cs = e1 >> 16;
516633dc
FB		 1969 new_eip = (e1 & 0xffff);
1970 if (type == 12)
1971 new_eip |= (e2 & 0xffff0000);
7e84c249
FB		 1972 if (load_segment(&e1, &e2, gate_cs) != 0)
1973 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1974 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1975 /* must be code segment */
1976 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1977 (DESC_S_MASK | DESC_CS_MASK)))
1978 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
14ce26e7 1979 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
7e84c249
FB		 1980 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
1981 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1982 if (!(e2 & DESC_P_MASK))
1983 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
7e84c249
FB		 1984 limit = get_seg_limit(e1, e2);
1985 if (new_eip > limit)
1986 raise_exception_err(EXCP0D_GPF, 0);
1987 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1988 get_seg_base(e1, e2), limit, e2);
1989 EIP = new_eip;
1990 break;
1991 default:
1992 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1993 break;
1994 }
2c0262af
FB		 1995 }
1996}
1997
1998/* real mode call */
1999void helper_lcall_real_T0_T1(int shift, int next_eip)
2000{
2001 int new_cs, new_eip;
2002 uint32_t esp, esp_mask;
14ce26e7 2003 target_ulong ssp;
2c0262af
FB		 2004
2005 new_cs = T0;
2006 new_eip = T1;
2007 esp = ESP;
891b38e4 2008 esp_mask = get_sp_mask(env->segs[R_SS].flags);
2c0262af
FB		 2009 ssp = env->segs[R_SS].base;
2010 if (shift) {
891b38e4
FB		 2011 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2012 PUSHL(ssp, esp, esp_mask, next_eip);
2c0262af 2013 } else {
891b38e4
FB		 2014 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2015 PUSHW(ssp, esp, esp_mask, next_eip);
2c0262af
FB		 2016 }
2017
891b38e4 2018 ESP = (ESP & ~esp_mask) | (esp & esp_mask);
2c0262af
FB		 2019 env->eip = new_eip;
2020 env->segs[R_CS].selector = new_cs;
14ce26e7 2021 env->segs[R_CS].base = (new_cs << 4);
2c0262af
FB		 2022}
2023
2024/* protected mode call */
f419b321 2025void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2c0262af 2026{
649ea05a 2027 int new_cs, new_stack, i;
2c0262af 2028 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
891b38e4
FB		 2029 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2030 uint32_t val, limit, old_sp_mask;
649ea05a 2031 target_ulong ssp, old_ssp, next_eip, new_eip;
2c0262af
FB		 2032
2033 new_cs = T0;
2034 new_eip = T1;
f419b321 2035 next_eip = env->eip + next_eip_addend;
f3f2d9be 2036#ifdef DEBUG_PCALL
e19e89a5
FB		 2037 if (loglevel & CPU_LOG_PCALL) {
2038 fprintf(logfile, "lcall %04x:%08x s=%d\n",
649ea05a 2039 new_cs, (uint32_t)new_eip, shift);
7fe48483 2040 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
f3f2d9be
FB		 2041 }
2042#endif
2c0262af
FB		 2043 if ((new_cs & 0xfffc) == 0)
2044 raise_exception_err(EXCP0D_GPF, 0);
2045 if (load_segment(&e1, &e2, new_cs) != 0)
2046 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2047 cpl = env->hflags & HF_CPL_MASK;
f3f2d9be 2048#ifdef DEBUG_PCALL
e19e89a5 2049 if (loglevel & CPU_LOG_PCALL) {
f3f2d9be
FB		 2050 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2051 }
2052#endif
2c0262af
FB		 2053 if (e2 & DESC_S_MASK) {
2054 if (!(e2 & DESC_CS_MASK))
2055 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2056 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
7e84c249 2057 if (e2 & DESC_C_MASK) {
2c0262af
FB		 2058 /* conforming code segment */
2059 if (dpl > cpl)
2060 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2061 } else {
2062 /* non conforming code segment */
2063 rpl = new_cs & 3;
2064 if (rpl > cpl)
2065 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2066 if (dpl != cpl)
2067 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2068 }
2069 if (!(e2 & DESC_P_MASK))
2070 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2071
f419b321
FB		 2072#ifdef TARGET_X86_64
2073 /* XXX: check 16/32 bit cases in long mode */
2074 if (shift == 2) {
2075 target_ulong rsp;
2076 /* 64 bit case */
2077 rsp = ESP;
2078 PUSHQ(rsp, env->segs[R_CS].selector);
2079 PUSHQ(rsp, next_eip);
2080 /* from this point, not restartable */
2081 ESP = rsp;
2082 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
2083 get_seg_base(e1, e2),
2084 get_seg_limit(e1, e2), e2);
2085 EIP = new_eip;
2086 } else
2087#endif
2088 {
2089 sp = ESP;
2090 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2091 ssp = env->segs[R_SS].base;
2092 if (shift) {
2093 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2094 PUSHL(ssp, sp, sp_mask, next_eip);
2095 } else {
2096 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2097 PUSHW(ssp, sp, sp_mask, next_eip);
2098 }
2099
2100 limit = get_seg_limit(e1, e2);
2101 if (new_eip > limit)
2102 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2103 /* from this point, not restartable */
2104 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2105 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
2106 get_seg_base(e1, e2), limit, e2);
2107 EIP = new_eip;
2c0262af 2108 }
2c0262af
FB		 2109 } else {
2110 /* check gate type */
2111 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
7e84c249
FB		 2112 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2113 rpl = new_cs & 3;
2c0262af
FB		 2114 switch(type) {
2115 case 1: /* available 286 TSS */
2116 case 9: /* available 386 TSS */
2117 case 5: /* task gate */
7e84c249
FB		 2118 if (dpl < cpl || dpl < rpl)
2119 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
883da8e2 2120 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
447c2cef 2121 CC_OP = CC_OP_EFLAGS;
8145122b 2122 return;
2c0262af
FB		 2123 case 4: /* 286 call gate */
2124 case 12: /* 386 call gate */
2125 break;
2126 default:
2127 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2128 break;
2129 }
2130 shift = type >> 3;
2131
2c0262af
FB		 2132 if (dpl < cpl || dpl < rpl)
2133 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2134 /* check valid bit */
2135 if (!(e2 & DESC_P_MASK))
2136 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2137 selector = e1 >> 16;
2138 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
f3f2d9be 2139 param_count = e2 & 0x1f;
2c0262af
FB		 2140 if ((selector & 0xfffc) == 0)
2141 raise_exception_err(EXCP0D_GPF, 0);
2142
2143 if (load_segment(&e1, &e2, selector) != 0)
2144 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2145 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
2146 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2147 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2148 if (dpl > cpl)
2149 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2150 if (!(e2 & DESC_P_MASK))
2151 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2152
2153 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2154 /* to inner priviledge */
2155 get_ss_esp_from_tss(&ss, &sp, dpl);
f3f2d9be 2156#ifdef DEBUG_PCALL
e19e89a5 2157 if (loglevel & CPU_LOG_PCALL)
14ce26e7 2158 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
f3f2d9be
FB		 2159 ss, sp, param_count, ESP);
2160#endif
2c0262af
FB		 2161 if ((ss & 0xfffc) == 0)
2162 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2163 if ((ss & 3) != dpl)
2164 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2165 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2166 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2167 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2168 if (ss_dpl != dpl)
2169 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2170 if (!(ss_e2 & DESC_S_MASK) ||
2171 (ss_e2 & DESC_CS_MASK) ||
2172 !(ss_e2 & DESC_W_MASK))
2173 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2174 if (!(ss_e2 & DESC_P_MASK))
2175 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2176
891b38e4 2177 // push_size = ((param_count * 2) + 8) << shift;
2c0262af 2178
891b38e4
FB		 2179 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2180 old_ssp = env->segs[R_SS].base;
2c0262af 2181
891b38e4
FB		 2182 sp_mask = get_sp_mask(ss_e2);
2183 ssp = get_seg_base(ss_e1, ss_e2);
2c0262af 2184 if (shift) {
891b38e4
FB		 2185 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2186 PUSHL(ssp, sp, sp_mask, ESP);
2187 for(i = param_count - 1; i >= 0; i--) {
2188 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2189 PUSHL(ssp, sp, sp_mask, val);
2c0262af
FB		 2190 }
2191 } else {
891b38e4
FB		 2192 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2193 PUSHW(ssp, sp, sp_mask, ESP);
2194 for(i = param_count - 1; i >= 0; i--) {
2195 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2196 PUSHW(ssp, sp, sp_mask, val);
2c0262af
FB		 2197 }
2198 }
891b38e4 2199 new_stack = 1;
2c0262af
FB		 2200 } else {
2201 /* to same priviledge */
891b38e4
FB		 2202 sp = ESP;
2203 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2204 ssp = env->segs[R_SS].base;
2205 // push_size = (4 << shift);
2206 new_stack = 0;
2c0262af
FB		 2207 }
2208
2209 if (shift) {
891b38e4
FB		 2210 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2211 PUSHL(ssp, sp, sp_mask, next_eip);
2c0262af 2212 } else {
891b38e4
FB		 2213 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2214 PUSHW(ssp, sp, sp_mask, next_eip);
2215 }
2216
2217 /* from this point, not restartable */
2218
2219 if (new_stack) {
2220 ss = (ss & ~3) | dpl;
2221 cpu_x86_load_seg_cache(env, R_SS, ss,
2222 ssp,
2223 get_seg_limit(ss_e1, ss_e2),
2224 ss_e2);
2c0262af
FB		 2225 }
2226
2c0262af
FB		 2227 selector = (selector & ~3) | dpl;
2228 cpu_x86_load_seg_cache(env, R_CS, selector,
2229 get_seg_base(e1, e2),
2230 get_seg_limit(e1, e2),
2231 e2);
2232 cpu_x86_set_cpl(env, dpl);
891b38e4 2233 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2c0262af
FB		 2234 EIP = offset;
2235 }
9df217a3
FB		 2236#ifdef USE_KQEMU
2237 if (kqemu_is_ok(env)) {
2238 env->exception_index = -1;
2239 cpu_loop_exit();
2240 }
2241#endif
2c0262af
FB		 2242}
2243
7e84c249 2244/* real and vm86 mode iret */
2c0262af
FB		 2245void helper_iret_real(int shift)
2246{
891b38e4 2247 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
14ce26e7 2248 target_ulong ssp;
2c0262af 2249 int eflags_mask;
7e84c249 2250
891b38e4
FB		 2251 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2252 sp = ESP;
2253 ssp = env->segs[R_SS].base;
2c0262af
FB		 2254 if (shift == 1) {
2255 /* 32 bits */
891b38e4
FB		 2256 POPL(ssp, sp, sp_mask, new_eip);
2257 POPL(ssp, sp, sp_mask, new_cs);
2258 new_cs &= 0xffff;
2259 POPL(ssp, sp, sp_mask, new_eflags);
2c0262af
FB		 2260 } else {
2261 /* 16 bits */
891b38e4
FB		 2262 POPW(ssp, sp, sp_mask, new_eip);
2263 POPW(ssp, sp, sp_mask, new_cs);
2264 POPW(ssp, sp, sp_mask, new_eflags);
2c0262af 2265 }
4136f33c 2266 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2c0262af
FB		 2267 load_seg_vm(R_CS, new_cs);
2268 env->eip = new_eip;
7e84c249 2269 if (env->eflags & VM_MASK)
8145122b 2270 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
7e84c249 2271 else
8145122b 2272 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
2c0262af
FB		 2273 if (shift == 0)
2274 eflags_mask &= 0xffff;
2275 load_eflags(new_eflags, eflags_mask);
2276}
2277
8e682019
FB		 2278static inline void validate_seg(int seg_reg, int cpl)
2279{
2280 int dpl;
2281 uint32_t e2;
cd072e01
FB		 2282
2283 /* XXX: on x86_64, we do not want to nullify FS and GS because
2284 they may still contain a valid base. I would be interested to
2285 know how a real x86_64 CPU behaves */
2286 if ((seg_reg == R_FS || seg_reg == R_GS) &&
2287 (env->segs[seg_reg].selector & 0xfffc) == 0)
2288 return;
2289
8e682019
FB		 2290 e2 = env->segs[seg_reg].flags;
2291 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2292 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2293 /* data or non conforming code segment */
2294 if (dpl < cpl) {
14ce26e7 2295 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
8e682019
FB		 2296 }
2297 }
2298}
2299
2c0262af
FB		 2300/* protected mode iret */
2301static inline void helper_ret_protected(int shift, int is_iret, int addend)
2302{
14ce26e7 2303 uint32_t new_cs, new_eflags, new_ss;
2c0262af
FB		 2304 uint32_t new_es, new_ds, new_fs, new_gs;
2305 uint32_t e1, e2, ss_e1, ss_e2;
4136f33c 2306 int cpl, dpl, rpl, eflags_mask, iopl;
14ce26e7 2307 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2c0262af 2308
14ce26e7
FB		 2309#ifdef TARGET_X86_64
2310 if (shift == 2)
2311 sp_mask = -1;
2312 else
2313#endif
2314 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2c0262af 2315 sp = ESP;
891b38e4 2316 ssp = env->segs[R_SS].base;
354ff226 2317 new_eflags = 0; /* avoid warning */
14ce26e7
FB		 2318#ifdef TARGET_X86_64
2319 if (shift == 2) {
2320 POPQ(sp, new_eip);
2321 POPQ(sp, new_cs);
2322 new_cs &= 0xffff;
2323 if (is_iret) {
2324 POPQ(sp, new_eflags);
2325 }
2326 } else
2327#endif
2c0262af
FB		 2328 if (shift == 1) {
2329 /* 32 bits */
891b38e4
FB		 2330 POPL(ssp, sp, sp_mask, new_eip);
2331 POPL(ssp, sp, sp_mask, new_cs);
2332 new_cs &= 0xffff;
2333 if (is_iret) {
2334 POPL(ssp, sp, sp_mask, new_eflags);
2335 if (new_eflags & VM_MASK)
2336 goto return_to_vm86;
2337 }
2c0262af
FB		 2338 } else {
2339 /* 16 bits */
891b38e4
FB		 2340 POPW(ssp, sp, sp_mask, new_eip);
2341 POPW(ssp, sp, sp_mask, new_cs);
2c0262af 2342 if (is_iret)
891b38e4 2343 POPW(ssp, sp, sp_mask, new_eflags);
2c0262af 2344 }
891b38e4 2345#ifdef DEBUG_PCALL
e19e89a5 2346 if (loglevel & CPU_LOG_PCALL) {
14ce26e7 2347 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
e19e89a5 2348 new_cs, new_eip, shift, addend);
7fe48483 2349 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
891b38e4
FB		 2350 }
2351#endif
2c0262af
FB		 2352 if ((new_cs & 0xfffc) == 0)
2353 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2354 if (load_segment(&e1, &e2, new_cs) != 0)
2355 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2356 if (!(e2 & DESC_S_MASK) ||
2357 !(e2 & DESC_CS_MASK))
2358 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2359 cpl = env->hflags & HF_CPL_MASK;
2360 rpl = new_cs & 3;
2361 if (rpl < cpl)
2362 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2363 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
7e84c249 2364 if (e2 & DESC_C_MASK) {
2c0262af
FB		 2365 if (dpl > rpl)
2366 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2367 } else {
2368 if (dpl != rpl)
2369 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2370 }
2371 if (!(e2 & DESC_P_MASK))
2372 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2373
891b38e4 2374 sp += addend;
ca954f6d
FB		 2375 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2376 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2c0262af
FB		 2377 /* return to same priledge level */
2378 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2379 get_seg_base(e1, e2),
2380 get_seg_limit(e1, e2),
2381 e2);
2c0262af
FB		 2382 } else {
2383 /* return to different priviledge level */
14ce26e7
FB		 2384#ifdef TARGET_X86_64
2385 if (shift == 2) {
2386 POPQ(sp, new_esp);
2387 POPQ(sp, new_ss);
2388 new_ss &= 0xffff;
2389 } else
2390#endif
2c0262af
FB		 2391 if (shift == 1) {
2392 /* 32 bits */
891b38e4
FB		 2393 POPL(ssp, sp, sp_mask, new_esp);
2394 POPL(ssp, sp, sp_mask, new_ss);
2395 new_ss &= 0xffff;
2c0262af
FB		 2396 } else {
2397 /* 16 bits */
891b38e4
FB		 2398 POPW(ssp, sp, sp_mask, new_esp);
2399 POPW(ssp, sp, sp_mask, new_ss);
2c0262af 2400 }
e19e89a5
FB		 2401#ifdef DEBUG_PCALL
2402 if (loglevel & CPU_LOG_PCALL) {
14ce26e7 2403 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
e19e89a5
FB		 2404 new_ss, new_esp);
2405 }
2406#endif
b359d4e7
FB		 2407 if ((new_ss & 0xfffc) == 0) {
2408#ifdef TARGET_X86_64
2409 /* NULL ss is allowed in long mode if cpl != 3*/
2410 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2411 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2412 0, 0xffffffff,
2413 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2414 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2415 DESC_W_MASK | DESC_A_MASK);
2416 } else
2417#endif
2418 {
2419 raise_exception_err(EXCP0D_GPF, 0);
2420 }
14ce26e7
FB		 2421 } else {
2422 if ((new_ss & 3) != rpl)
2423 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2424 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2425 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2426 if (!(ss_e2 & DESC_S_MASK) ||
2427 (ss_e2 & DESC_CS_MASK) ||
2428 !(ss_e2 & DESC_W_MASK))
2429 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2430 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2431 if (dpl != rpl)
2432 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2433 if (!(ss_e2 & DESC_P_MASK))
2434 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2435 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2436 get_seg_base(ss_e1, ss_e2),
2437 get_seg_limit(ss_e1, ss_e2),
2438 ss_e2);
2439 }
2c0262af
FB		 2440
2441 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2442 get_seg_base(e1, e2),
2443 get_seg_limit(e1, e2),
2444 e2);
2c0262af 2445 cpu_x86_set_cpl(env, rpl);
891b38e4 2446 sp = new_esp;
14ce26e7 2447#ifdef TARGET_X86_64
2c8e0301 2448 if (env->hflags & HF_CS64_MASK)
14ce26e7
FB		 2449 sp_mask = -1;
2450 else
2451#endif
2452 sp_mask = get_sp_mask(ss_e2);
8e682019
FB		 2453
2454 /* validate data segments */
89984cd2
FB		 2455 validate_seg(R_ES, rpl);
2456 validate_seg(R_DS, rpl);
2457 validate_seg(R_FS, rpl);
2458 validate_seg(R_GS, rpl);
4afa6482
FB		 2459
2460 sp += addend;
2c0262af 2461 }
891b38e4 2462 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2c0262af
FB		 2463 env->eip = new_eip;
2464 if (is_iret) {
4136f33c 2465 /* NOTE: 'cpl' is the _old_ CPL */
8145122b 2466 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2c0262af 2467 if (cpl == 0)
4136f33c
FB		 2468 eflags_mask |= IOPL_MASK;
2469 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2470 if (cpl <= iopl)
2471 eflags_mask |= IF_MASK;
2c0262af
FB		 2472 if (shift == 0)
2473 eflags_mask &= 0xffff;
2474 load_eflags(new_eflags, eflags_mask);
2475 }
2476 return;
2477
2478 return_to_vm86:
891b38e4
FB		 2479 POPL(ssp, sp, sp_mask, new_esp);
2480 POPL(ssp, sp, sp_mask, new_ss);
2481 POPL(ssp, sp, sp_mask, new_es);
2482 POPL(ssp, sp, sp_mask, new_ds);
2483 POPL(ssp, sp, sp_mask, new_fs);
2484 POPL(ssp, sp, sp_mask, new_gs);
2c0262af
FB		 2485
2486 /* modify processor state */
4136f33c 2487 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
8145122b 2488 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
891b38e4 2489 load_seg_vm(R_CS, new_cs & 0xffff);
2c0262af 2490 cpu_x86_set_cpl(env, 3);
891b38e4
FB		 2491 load_seg_vm(R_SS, new_ss & 0xffff);
2492 load_seg_vm(R_ES, new_es & 0xffff);
2493 load_seg_vm(R_DS, new_ds & 0xffff);
2494 load_seg_vm(R_FS, new_fs & 0xffff);
2495 load_seg_vm(R_GS, new_gs & 0xffff);
2c0262af 2496
fd836909 2497 env->eip = new_eip & 0xffff;
2c0262af
FB		 2498 ESP = new_esp;
2499}
2500
08cea4ee 2501void helper_iret_protected(int shift, int next_eip)
2c0262af 2502{
7e84c249
FB		 2503 int tss_selector, type;
2504 uint32_t e1, e2;
2505
2506 /* specific case for TSS */
2507 if (env->eflags & NT_MASK) {
14ce26e7
FB		 2508#ifdef TARGET_X86_64
2509 if (env->hflags & HF_LMA_MASK)
2510 raise_exception_err(EXCP0D_GPF, 0);
2511#endif
7e84c249
FB		 2512 tss_selector = lduw_kernel(env->tr.base + 0);
2513 if (tss_selector & 4)
2514 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2515 if (load_segment(&e1, &e2, tss_selector) != 0)
2516 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2517 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2518 /* NOTE: we check both segment and busy TSS */
2519 if (type != 3)
2520 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
08cea4ee 2521 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
7e84c249
FB		 2522 } else {
2523 helper_ret_protected(shift, 1, 0);
2524 }
9df217a3
FB		 2525#ifdef USE_KQEMU
2526 if (kqemu_is_ok(env)) {
2527 CC_OP = CC_OP_EFLAGS;
2528 env->exception_index = -1;
2529 cpu_loop_exit();
2530 }
2531#endif
2c0262af
FB		 2532}
2533
2534void helper_lret_protected(int shift, int addend)
2535{
2536 helper_ret_protected(shift, 0, addend);
9df217a3
FB		 2537#ifdef USE_KQEMU
2538 if (kqemu_is_ok(env)) {
9df217a3
FB		 2539 env->exception_index = -1;
2540 cpu_loop_exit();
2541 }
2542#endif
2c0262af
FB		 2543}
2544
023fe10d
FB		 2545void helper_sysenter(void)
2546{
2547 if (env->sysenter_cs == 0) {
2548 raise_exception_err(EXCP0D_GPF, 0);
2549 }
2550 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2551 cpu_x86_set_cpl(env, 0);
2552 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
14ce26e7 2553 0, 0xffffffff,
023fe10d
FB		 2554 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2555 DESC_S_MASK |
2556 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2557 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
14ce26e7 2558 0, 0xffffffff,
023fe10d
FB		 2559 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2560 DESC_S_MASK |
2561 DESC_W_MASK | DESC_A_MASK);
2562 ESP = env->sysenter_esp;
2563 EIP = env->sysenter_eip;
2564}
2565
2566void helper_sysexit(void)
2567{
2568 int cpl;
2569
2570 cpl = env->hflags & HF_CPL_MASK;
2571 if (env->sysenter_cs == 0 || cpl != 0) {
2572 raise_exception_err(EXCP0D_GPF, 0);
2573 }
2574 cpu_x86_set_cpl(env, 3);
2575 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
14ce26e7 2576 0, 0xffffffff,
023fe10d
FB		 2577 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2578 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2579 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2580 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
14ce26e7 2581 0, 0xffffffff,
023fe10d
FB		 2582 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2583 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2584 DESC_W_MASK | DESC_A_MASK);
2585 ESP = ECX;
2586 EIP = EDX;
9df217a3
FB		 2587#ifdef USE_KQEMU
2588 if (kqemu_is_ok(env)) {
2589 env->exception_index = -1;
2590 cpu_loop_exit();
2591 }
2592#endif
023fe10d
FB		 2593}
2594
2c0262af
FB		 2595void helper_movl_crN_T0(int reg)
2596{
4d6b6c0a 2597#if !defined(CONFIG_USER_ONLY)
2c0262af
FB		 2598 switch(reg) {
2599 case 0:
1ac157da 2600 cpu_x86_update_cr0(env, T0);
2c0262af
FB		 2601 break;
2602 case 3:
1ac157da
FB		 2603 cpu_x86_update_cr3(env, T0);
2604 break;
2605 case 4:
2606 cpu_x86_update_cr4(env, T0);
2607 break;
4d6b6c0a
FB		 2608 case 8:
2609 cpu_set_apic_tpr(env, T0);
2610 break;
1ac157da
FB		 2611 default:
2612 env->cr[reg] = T0;
2c0262af
FB		 2613 break;
2614 }
4d6b6c0a 2615#endif
2c0262af
FB		 2616}
2617
2618/* XXX: do more */
2619void helper_movl_drN_T0(int reg)
2620{
2621 env->dr[reg] = T0;
2622}
2623
8f091a59 2624void helper_invlpg(target_ulong addr)
2c0262af
FB		 2625{
2626 cpu_x86_flush_tlb(env, addr);
2627}
2628
2c0262af
FB		 2629void helper_rdtsc(void)
2630{
2631 uint64_t val;
ecada8a2
FB		 2632
2633 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2634 raise_exception(EXCP0D_GPF);
2635 }
28ab0e2e 2636 val = cpu_get_tsc(env);
14ce26e7
FB		 2637 EAX = (uint32_t)(val);
2638 EDX = (uint32_t)(val >> 32);
2639}
2640
2641#if defined(CONFIG_USER_ONLY)
2642void helper_wrmsr(void)
2643{
2c0262af
FB		 2644}
2645
14ce26e7
FB		 2646void helper_rdmsr(void)
2647{
2648}
2649#else
2c0262af
FB		 2650void helper_wrmsr(void)
2651{
14ce26e7
FB		 2652 uint64_t val;
2653
2654 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2655
2656 switch((uint32_t)ECX) {
2c0262af 2657 case MSR_IA32_SYSENTER_CS:
14ce26e7 2658 env->sysenter_cs = val & 0xffff;
2c0262af
FB		 2659 break;
2660 case MSR_IA32_SYSENTER_ESP:
14ce26e7 2661 env->sysenter_esp = val;
2c0262af
FB		 2662 break;
2663 case MSR_IA32_SYSENTER_EIP:
14ce26e7
FB		 2664 env->sysenter_eip = val;
2665 break;
2666 case MSR_IA32_APICBASE:
2667 cpu_set_apic_base(env, val);
2668 break;
14ce26e7 2669 case MSR_EFER:
f419b321
FB		 2670 {
2671 uint64_t update_mask;
2672 update_mask = 0;
2673 if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
2674 update_mask |= MSR_EFER_SCE;
2675 if (env->cpuid_ext2_features & CPUID_EXT2_LM)
2676 update_mask |= MSR_EFER_LME;
2677 if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
2678 update_mask |= MSR_EFER_FFXSR;
2679 if (env->cpuid_ext2_features & CPUID_EXT2_NX)
2680 update_mask |= MSR_EFER_NXE;
2681 env->efer = (env->efer & ~update_mask) |
2682 (val & update_mask);
2683 }
2c0262af 2684 break;
14ce26e7
FB		 2685 case MSR_STAR:
2686 env->star = val;
2687 break;
8f091a59
FB		 2688 case MSR_PAT:
2689 env->pat = val;
2690 break;
f419b321 2691#ifdef TARGET_X86_64
14ce26e7
FB		 2692 case MSR_LSTAR:
2693 env->lstar = val;
2694 break;
2695 case MSR_CSTAR:
2696 env->cstar = val;
2697 break;
2698 case MSR_FMASK:
2699 env->fmask = val;
2700 break;
2701 case MSR_FSBASE:
2702 env->segs[R_FS].base = val;
2703 break;
2704 case MSR_GSBASE:
2705 env->segs[R_GS].base = val;
2706 break;
2707 case MSR_KERNELGSBASE:
2708 env->kernelgsbase = val;
2709 break;
2710#endif
2c0262af
FB		 2711 default:
2712 /* XXX: exception ? */
2713 break;
2714 }
2715}
2716
2717void helper_rdmsr(void)
2718{
14ce26e7
FB		 2719 uint64_t val;
2720 switch((uint32_t)ECX) {
2c0262af 2721 case MSR_IA32_SYSENTER_CS:
14ce26e7 2722 val = env->sysenter_cs;
2c0262af
FB		 2723 break;
2724 case MSR_IA32_SYSENTER_ESP:
14ce26e7 2725 val = env->sysenter_esp;
2c0262af
FB		 2726 break;
2727 case MSR_IA32_SYSENTER_EIP:
14ce26e7
FB		 2728 val = env->sysenter_eip;
2729 break;
2730 case MSR_IA32_APICBASE:
2731 val = cpu_get_apic_base(env);
2732 break;
14ce26e7
FB		 2733 case MSR_EFER:
2734 val = env->efer;
2735 break;
2736 case MSR_STAR:
2737 val = env->star;
2738 break;
8f091a59
FB		 2739 case MSR_PAT:
2740 val = env->pat;
2741 break;
f419b321 2742#ifdef TARGET_X86_64
14ce26e7
FB		 2743 case MSR_LSTAR:
2744 val = env->lstar;
2745 break;
2746 case MSR_CSTAR:
2747 val = env->cstar;
2748 break;
2749 case MSR_FMASK:
2750 val = env->fmask;
2751 break;
2752 case MSR_FSBASE:
2753 val = env->segs[R_FS].base;
2754 break;
2755 case MSR_GSBASE:
2756 val = env->segs[R_GS].base;
2c0262af 2757 break;
14ce26e7
FB		 2758 case MSR_KERNELGSBASE:
2759 val = env->kernelgsbase;
2760 break;
2761#endif
2c0262af
FB		 2762 default:
2763 /* XXX: exception ? */
14ce26e7 2764 val = 0;
2c0262af
FB		 2765 break;
2766 }
14ce26e7
FB		 2767 EAX = (uint32_t)(val);
2768 EDX = (uint32_t)(val >> 32);
2c0262af 2769}
14ce26e7 2770#endif
2c0262af
FB		 2771
2772void helper_lsl(void)
2773{
2774 unsigned int selector, limit;
5516d670 2775 uint32_t e1, e2, eflags;
3ab493de 2776 int rpl, dpl, cpl, type;
2c0262af 2777
5516d670 2778 eflags = cc_table[CC_OP].compute_all();
2c0262af
FB		 2779 selector = T0 & 0xffff;
2780 if (load_segment(&e1, &e2, selector) != 0)
5516d670 2781 goto fail;
3ab493de
FB		 2782 rpl = selector & 3;
2783 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2784 cpl = env->hflags & HF_CPL_MASK;
2785 if (e2 & DESC_S_MASK) {
2786 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2787 /* conforming */
2788 } else {
2789 if (dpl < cpl || dpl < rpl)
5516d670 2790 goto fail;
3ab493de
FB		 2791 }
2792 } else {
2793 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2794 switch(type) {
2795 case 1:
2796 case 2:
2797 case 3:
2798 case 9:
2799 case 11:
2800 break;
2801 default:
5516d670 2802 goto fail;
3ab493de 2803 }
5516d670
FB		 2804 if (dpl < cpl || dpl < rpl) {
2805 fail:
2806 CC_SRC = eflags & ~CC_Z;
3ab493de 2807 return;
5516d670 2808 }
3ab493de
FB		 2809 }
2810 limit = get_seg_limit(e1, e2);
2c0262af 2811 T1 = limit;
5516d670 2812 CC_SRC = eflags | CC_Z;
2c0262af
FB		 2813}
2814
2815void helper_lar(void)
2816{
2817 unsigned int selector;
5516d670 2818 uint32_t e1, e2, eflags;
3ab493de 2819 int rpl, dpl, cpl, type;
2c0262af 2820
5516d670 2821 eflags = cc_table[CC_OP].compute_all();
2c0262af 2822 selector = T0 & 0xffff;
3ab493de 2823 if ((selector & 0xfffc) == 0)
5516d670 2824 goto fail;
2c0262af 2825 if (load_segment(&e1, &e2, selector) != 0)
5516d670 2826 goto fail;
3ab493de
FB		 2827 rpl = selector & 3;
2828 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2829 cpl = env->hflags & HF_CPL_MASK;
2830 if (e2 & DESC_S_MASK) {
2831 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2832 /* conforming */
2833 } else {
2834 if (dpl < cpl || dpl < rpl)
5516d670 2835 goto fail;
3ab493de
FB		 2836 }
2837 } else {
2838 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2839 switch(type) {
2840 case 1:
2841 case 2:
2842 case 3:
2843 case 4:
2844 case 5:
2845 case 9:
2846 case 11:
2847 case 12:
2848 break;
2849 default:
5516d670 2850 goto fail;
3ab493de 2851 }
5516d670
FB		 2852 if (dpl < cpl || dpl < rpl) {
2853 fail:
2854 CC_SRC = eflags & ~CC_Z;
3ab493de 2855 return;
5516d670 2856 }
3ab493de 2857 }
2c0262af 2858 T1 = e2 & 0x00f0ff00;
5516d670 2859 CC_SRC = eflags | CC_Z;
2c0262af
FB		 2860}
2861
3ab493de
FB		 2862void helper_verr(void)
2863{
2864 unsigned int selector;
5516d670 2865 uint32_t e1, e2, eflags;
3ab493de
FB		 2866 int rpl, dpl, cpl;
2867
5516d670 2868 eflags = cc_table[CC_OP].compute_all();
3ab493de
FB		 2869 selector = T0 & 0xffff;
2870 if ((selector & 0xfffc) == 0)
5516d670 2871 goto fail;
3ab493de 2872 if (load_segment(&e1, &e2, selector) != 0)
5516d670 2873 goto fail;
3ab493de 2874 if (!(e2 & DESC_S_MASK))
5516d670 2875 goto fail;
3ab493de
FB		 2876 rpl = selector & 3;
2877 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2878 cpl = env->hflags & HF_CPL_MASK;
2879 if (e2 & DESC_CS_MASK) {
2880 if (!(e2 & DESC_R_MASK))
5516d670 2881 goto fail;
3ab493de
FB		 2882 if (!(e2 & DESC_C_MASK)) {
2883 if (dpl < cpl || dpl < rpl)
5516d670 2884 goto fail;
3ab493de
FB		 2885 }
2886 } else {
5516d670
FB		 2887 if (dpl < cpl || dpl < rpl) {
2888 fail:
2889 CC_SRC = eflags & ~CC_Z;
3ab493de 2890 return;
5516d670 2891 }
3ab493de 2892 }
5516d670 2893 CC_SRC = eflags | CC_Z;
3ab493de
FB		 2894}
2895
2896void helper_verw(void)
2897{
2898 unsigned int selector;
5516d670 2899 uint32_t e1, e2, eflags;
3ab493de
FB		 2900 int rpl, dpl, cpl;
2901
5516d670 2902 eflags = cc_table[CC_OP].compute_all();
3ab493de
FB		 2903 selector = T0 & 0xffff;
2904 if ((selector & 0xfffc) == 0)
5516d670 2905 goto fail;
3ab493de 2906 if (load_segment(&e1, &e2, selector) != 0)
5516d670 2907 goto fail;
3ab493de 2908 if (!(e2 & DESC_S_MASK))
5516d670 2909 goto fail;
3ab493de
FB		 2910 rpl = selector & 3;
2911 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2912 cpl = env->hflags & HF_CPL_MASK;
2913 if (e2 & DESC_CS_MASK) {
5516d670 2914 goto fail;
3ab493de
FB		 2915 } else {
2916 if (dpl < cpl || dpl < rpl)
5516d670
FB		 2917 goto fail;
2918 if (!(e2 & DESC_W_MASK)) {
2919 fail:
2920 CC_SRC = eflags & ~CC_Z;
3ab493de 2921 return;
5516d670 2922 }
3ab493de 2923 }
5516d670 2924 CC_SRC = eflags | CC_Z;
3ab493de
FB		 2925}
2926
2c0262af
FB		 2927/* FPU helpers */
2928
2c0262af
FB		 2929void helper_fldt_ST0_A0(void)
2930{
2931 int new_fpstt;
2932 new_fpstt = (env->fpstt - 1) & 7;
664e0f19 2933 env->fpregs[new_fpstt].d = helper_fldt(A0);
2c0262af
FB		 2934 env->fpstt = new_fpstt;
2935 env->fptags[new_fpstt] = 0; /* validate stack entry */
2936}
2937
2938void helper_fstt_ST0_A0(void)
2939{
14ce26e7 2940 helper_fstt(ST0, A0);
2c0262af 2941}
2c0262af 2942
2ee73ac3
FB		 2943void fpu_set_exception(int mask)
2944{
2945 env->fpus |= mask;
2946 if (env->fpus & (~env->fpuc & FPUC_EM))
2947 env->fpus |= FPUS_SE | FPUS_B;
2948}
2949
2950CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
2951{
2952 if (b == 0.0)
2953 fpu_set_exception(FPUS_ZE);
2954 return a / b;
2955}
2956
2957void fpu_raise_exception(void)
2958{
2959 if (env->cr[0] & CR0_NE_MASK) {
2960 raise_exception(EXCP10_COPR);
2961 }
2962#if !defined(CONFIG_USER_ONLY)
2963 else {
2964 cpu_set_ferr(env);
2965 }
2966#endif
2967}
2968
2c0262af
FB		 2969/* BCD ops */
2970
2c0262af
FB		 2971void helper_fbld_ST0_A0(void)
2972{
2973 CPU86_LDouble tmp;
2974 uint64_t val;
2975 unsigned int v;
2976 int i;
2977
2978 val = 0;
2979 for(i = 8; i >= 0; i--) {
14ce26e7 2980 v = ldub(A0 + i);
2c0262af
FB		 2981 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
2982 }
2983 tmp = val;
14ce26e7 2984 if (ldub(A0 + 9) & 0x80)
2c0262af
FB		 2985 tmp = -tmp;
2986 fpush();
2987 ST0 = tmp;
2988}
2989
2990void helper_fbst_ST0_A0(void)
2991{
2c0262af 2992 int v;
14ce26e7 2993 target_ulong mem_ref, mem_end;
2c0262af
FB		 2994 int64_t val;
2995
7a0e1f41 2996 val = floatx_to_int64(ST0, &env->fp_status);
14ce26e7 2997 mem_ref = A0;
2c0262af
FB		 2998 mem_end = mem_ref + 9;
2999 if (val < 0) {
3000 stb(mem_end, 0x80);
3001 val = -val;
3002 } else {
3003 stb(mem_end, 0x00);
3004 }
3005 while (mem_ref < mem_end) {
3006 if (val == 0)
3007 break;
3008 v = val % 100;
3009 val = val / 100;
3010 v = ((v / 10) << 4) | (v % 10);
3011 stb(mem_ref++, v);
3012 }
3013 while (mem_ref < mem_end) {
3014 stb(mem_ref++, 0);
3015 }
3016}
3017
3018void helper_f2xm1(void)
3019{
3020 ST0 = pow(2.0,ST0) - 1.0;
3021}
3022
3023void helper_fyl2x(void)
3024{
3025 CPU86_LDouble fptemp;
3026
3027 fptemp = ST0;
3028 if (fptemp>0.0){
3029 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3030 ST1 *= fptemp;
3031 fpop();
3032 } else {
3033 env->fpus &= (~0x4700);
3034 env->fpus |= 0x400;
3035 }
3036}
3037
3038void helper_fptan(void)
3039{
3040 CPU86_LDouble fptemp;
3041
3042 fptemp = ST0;
3043 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3044 env->fpus |= 0x400;
3045 } else {
3046 ST0 = tan(fptemp);
3047 fpush();
3048 ST0 = 1.0;
3049 env->fpus &= (~0x400); /* C2 <-- 0 */
3050 /* the above code is for |arg| < 2**52 only */
3051 }
3052}
3053
3054void helper_fpatan(void)
3055{
3056 CPU86_LDouble fptemp, fpsrcop;
3057
3058 fpsrcop = ST1;
3059 fptemp = ST0;
3060 ST1 = atan2(fpsrcop,fptemp);
3061 fpop();
3062}
3063
3064void helper_fxtract(void)
3065{
3066 CPU86_LDoubleU temp;
3067 unsigned int expdif;
3068
3069 temp.d = ST0;
3070 expdif = EXPD(temp) - EXPBIAS;
3071 /*DP exponent bias*/
3072 ST0 = expdif;
3073 fpush();
3074 BIASEXPONENT(temp);
3075 ST0 = temp.d;
3076}
3077
3078void helper_fprem1(void)
3079{
3080 CPU86_LDouble dblq, fpsrcop, fptemp;
3081 CPU86_LDoubleU fpsrcop1, fptemp1;
3082 int expdif;
3083 int q;
3084
3085 fpsrcop = ST0;
3086 fptemp = ST1;
3087 fpsrcop1.d = fpsrcop;
3088 fptemp1.d = fptemp;
3089 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3090 if (expdif < 53) {
3091 dblq = fpsrcop / fptemp;
3092 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3093 ST0 = fpsrcop - fptemp*dblq;
3094 q = (int)dblq; /* cutting off top bits is assumed here */
3095 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3096 /* (C0,C1,C3) <-- (q2,q1,q0) */
3097 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
3098 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
3099 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
3100 } else {
3101 env->fpus |= 0x400; /* C2 <-- 1 */
3102 fptemp = pow(2.0, expdif-50);
3103 fpsrcop = (ST0 / ST1) / fptemp;
3104 /* fpsrcop = integer obtained by rounding to the nearest */
3105 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3106 floor(fpsrcop): ceil(fpsrcop);
3107 ST0 -= (ST1 * fpsrcop * fptemp);
3108 }
3109}
3110
3111void helper_fprem(void)
3112{
3113 CPU86_LDouble dblq, fpsrcop, fptemp;
3114 CPU86_LDoubleU fpsrcop1, fptemp1;
3115 int expdif;
3116 int q;
3117
3118 fpsrcop = ST0;
3119 fptemp = ST1;
3120 fpsrcop1.d = fpsrcop;
3121 fptemp1.d = fptemp;
3122 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3123 if ( expdif < 53 ) {
3124 dblq = fpsrcop / fptemp;
3125 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3126 ST0 = fpsrcop - fptemp*dblq;
3127 q = (int)dblq; /* cutting off top bits is assumed here */
3128 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3129 /* (C0,C1,C3) <-- (q2,q1,q0) */
3130 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
3131 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
3132 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
3133 } else {
3134 env->fpus |= 0x400; /* C2 <-- 1 */
3135 fptemp = pow(2.0, expdif-50);
3136 fpsrcop = (ST0 / ST1) / fptemp;
3137 /* fpsrcop = integer obtained by chopping */
3138 fpsrcop = (fpsrcop < 0.0)?
3139 -(floor(fabs(fpsrcop))): floor(fpsrcop);
3140 ST0 -= (ST1 * fpsrcop * fptemp);
3141 }
3142}
3143
3144void helper_fyl2xp1(void)
3145{
3146 CPU86_LDouble fptemp;
3147
3148 fptemp = ST0;
3149 if ((fptemp+1.0)>0.0) {
3150 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3151 ST1 *= fptemp;
3152 fpop();
3153 } else {
3154 env->fpus &= (~0x4700);
3155 env->fpus |= 0x400;
3156 }
3157}
3158
3159void helper_fsqrt(void)
3160{
3161 CPU86_LDouble fptemp;
3162
3163 fptemp = ST0;
3164 if (fptemp<0.0) {
3165 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3166 env->fpus |= 0x400;
3167 }
3168 ST0 = sqrt(fptemp);
3169}
3170
3171void helper_fsincos(void)
3172{
3173 CPU86_LDouble fptemp;
3174
3175 fptemp = ST0;
3176 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3177 env->fpus |= 0x400;
3178 } else {
3179 ST0 = sin(fptemp);
3180 fpush();
3181 ST0 = cos(fptemp);
3182 env->fpus &= (~0x400); /* C2 <-- 0 */
3183 /* the above code is for |arg| < 2**63 only */
3184 }
3185}
3186
3187void helper_frndint(void)
3188{
7a0e1f41 3189 ST0 = floatx_round_to_int(ST0, &env->fp_status);
2c0262af
FB		 3190}
3191
3192void helper_fscale(void)
3193{
57e4c06e 3194 ST0 = ldexp (ST0, (int)(ST1));
2c0262af
FB		 3195}
3196
3197void helper_fsin(void)
3198{
3199 CPU86_LDouble fptemp;
3200
3201 fptemp = ST0;
3202 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3203 env->fpus |= 0x400;
3204 } else {
3205 ST0 = sin(fptemp);
3206 env->fpus &= (~0x400); /* C2 <-- 0 */
3207 /* the above code is for |arg| < 2**53 only */
3208 }
3209}
3210
3211void helper_fcos(void)
3212{
3213 CPU86_LDouble fptemp;
3214
3215 fptemp = ST0;
3216 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3217 env->fpus |= 0x400;
3218 } else {
3219 ST0 = cos(fptemp);
3220 env->fpus &= (~0x400); /* C2 <-- 0 */
3221 /* the above code is for |arg5 < 2**63 only */
3222 }
3223}
3224
3225void helper_fxam_ST0(void)
3226{
3227 CPU86_LDoubleU temp;
3228 int expdif;
3229
3230 temp.d = ST0;
3231
3232 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3233 if (SIGND(temp))
3234 env->fpus |= 0x200; /* C1 <-- 1 */
3235
a891c7a1 3236 /* XXX: test fptags too */
2c0262af
FB		 3237 expdif = EXPD(temp);
3238 if (expdif == MAXEXPD) {
a891c7a1
FB		 3239#ifdef USE_X86LDOUBLE
3240 if (MANTD(temp) == 0x8000000000000000ULL)
3241#else
2c0262af 3242 if (MANTD(temp) == 0)
a891c7a1 3243#endif
2c0262af
FB		 3244 env->fpus |= 0x500 /*Infinity*/;
3245 else
3246 env->fpus |= 0x100 /*NaN*/;
3247 } else if (expdif == 0) {
3248 if (MANTD(temp) == 0)
3249 env->fpus |= 0x4000 /*Zero*/;
3250 else
3251 env->fpus |= 0x4400 /*Denormal*/;
3252 } else {
3253 env->fpus |= 0x400;
3254 }
3255}
3256
14ce26e7 3257void helper_fstenv(target_ulong ptr, int data32)
2c0262af
FB		 3258{
3259 int fpus, fptag, exp, i;
3260 uint64_t mant;
3261 CPU86_LDoubleU tmp;
3262
3263 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3264 fptag = 0;
3265 for (i=7; i>=0; i--) {
3266 fptag <<= 2;
3267 if (env->fptags[i]) {
3268 fptag |= 3;
3269 } else {
664e0f19 3270 tmp.d = env->fpregs[i].d;
2c0262af
FB		 3271 exp = EXPD(tmp);
3272 mant = MANTD(tmp);
3273 if (exp == 0 && mant == 0) {
3274 /* zero */
3275 fptag |= 1;
3276 } else if (exp == 0 || exp == MAXEXPD
3277#ifdef USE_X86LDOUBLE
3278 || (mant & (1LL << 63)) == 0
3279#endif
3280 ) {
3281 /* NaNs, infinity, denormal */
3282 fptag |= 2;
3283 }
3284 }
3285 }
3286 if (data32) {
3287 /* 32 bit */
3288 stl(ptr, env->fpuc);
3289 stl(ptr + 4, fpus);
3290 stl(ptr + 8, fptag);
2edcdce3
FB		 3291 stl(ptr + 12, 0); /* fpip */
3292 stl(ptr + 16, 0); /* fpcs */
3293 stl(ptr + 20, 0); /* fpoo */
3294 stl(ptr + 24, 0); /* fpos */
2c0262af
FB		 3295 } else {
3296 /* 16 bit */
3297 stw(ptr, env->fpuc);
3298 stw(ptr + 2, fpus);
3299 stw(ptr + 4, fptag);
3300 stw(ptr + 6, 0);
3301 stw(ptr + 8, 0);
3302 stw(ptr + 10, 0);
3303 stw(ptr + 12, 0);
3304 }
3305}
3306
14ce26e7 3307void helper_fldenv(target_ulong ptr, int data32)
2c0262af
FB		 3308{
3309 int i, fpus, fptag;
3310
3311 if (data32) {
3312 env->fpuc = lduw(ptr);
3313 fpus = lduw(ptr + 4);
3314 fptag = lduw(ptr + 8);
3315 }
3316 else {
3317 env->fpuc = lduw(ptr);
3318 fpus = lduw(ptr + 2);
3319 fptag = lduw(ptr + 4);
3320 }
3321 env->fpstt = (fpus >> 11) & 7;
3322 env->fpus = fpus & ~0x3800;
2edcdce3 3323 for(i = 0;i < 8; i++) {
2c0262af
FB		 3324 env->fptags[i] = ((fptag & 3) == 3);
3325 fptag >>= 2;
3326 }
3327}
3328
14ce26e7 3329void helper_fsave(target_ulong ptr, int data32)
2c0262af
FB		 3330{
3331 CPU86_LDouble tmp;
3332 int i;
3333
3334 helper_fstenv(ptr, data32);
3335
3336 ptr += (14 << data32);
3337 for(i = 0;i < 8; i++) {
3338 tmp = ST(i);
2c0262af 3339 helper_fstt(tmp, ptr);
2c0262af
FB		 3340 ptr += 10;
3341 }
3342
3343 /* fninit */
3344 env->fpus = 0;
3345 env->fpstt = 0;
3346 env->fpuc = 0x37f;
3347 env->fptags[0] = 1;
3348 env->fptags[1] = 1;
3349 env->fptags[2] = 1;
3350 env->fptags[3] = 1;
3351 env->fptags[4] = 1;
3352 env->fptags[5] = 1;
3353 env->fptags[6] = 1;
3354 env->fptags[7] = 1;
3355}
3356
14ce26e7 3357void helper_frstor(target_ulong ptr, int data32)
2c0262af
FB		 3358{
3359 CPU86_LDouble tmp;
3360 int i;
3361
3362 helper_fldenv(ptr, data32);
3363 ptr += (14 << data32);
3364
3365 for(i = 0;i < 8; i++) {
2c0262af 3366 tmp = helper_fldt(ptr);
2c0262af
FB		 3367 ST(i) = tmp;
3368 ptr += 10;
3369 }
3370}
3371
14ce26e7
FB		 3372void helper_fxsave(target_ulong ptr, int data64)
3373{
3374 int fpus, fptag, i, nb_xmm_regs;
3375 CPU86_LDouble tmp;
3376 target_ulong addr;
3377
3378 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3379 fptag = 0;
3380 for(i = 0; i < 8; i++) {
d3c61721 3381 fptag |= (env->fptags[i] << i);
14ce26e7
FB		 3382 }
3383 stw(ptr, env->fpuc);
3384 stw(ptr + 2, fpus);
d3c61721 3385 stw(ptr + 4, fptag ^ 0xff);
14ce26e7
FB		 3386
3387 addr = ptr + 0x20;
3388 for(i = 0;i < 8; i++) {
3389 tmp = ST(i);
3390 helper_fstt(tmp, addr);
3391 addr += 16;
3392 }
3393
3394 if (env->cr[4] & CR4_OSFXSR_MASK) {
a8ede8ba 3395 /* XXX: finish it */
664e0f19 3396 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
d3c61721 3397 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
14ce26e7
FB		 3398 nb_xmm_regs = 8 << data64;
3399 addr = ptr + 0xa0;
3400 for(i = 0; i < nb_xmm_regs; i++) {
a8ede8ba
FB		 3401 stq(addr, env->xmm_regs[i].XMM_Q(0));
3402 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
14ce26e7
FB		 3403 addr += 16;
3404 }
3405 }
3406}
3407
3408void helper_fxrstor(target_ulong ptr, int data64)
3409{
3410 int i, fpus, fptag, nb_xmm_regs;
3411 CPU86_LDouble tmp;
3412 target_ulong addr;
3413
3414 env->fpuc = lduw(ptr);
3415 fpus = lduw(ptr + 2);
d3c61721 3416 fptag = lduw(ptr + 4);
14ce26e7
FB		 3417 env->fpstt = (fpus >> 11) & 7;
3418 env->fpus = fpus & ~0x3800;
3419 fptag ^= 0xff;
3420 for(i = 0;i < 8; i++) {
d3c61721 3421 env->fptags[i] = ((fptag >> i) & 1);
14ce26e7
FB		 3422 }
3423
3424 addr = ptr + 0x20;
3425 for(i = 0;i < 8; i++) {
3426 tmp = helper_fldt(addr);
3427 ST(i) = tmp;
3428 addr += 16;
3429 }
3430
3431 if (env->cr[4] & CR4_OSFXSR_MASK) {
31313213 3432 /* XXX: finish it */
664e0f19 3433 env->mxcsr = ldl(ptr + 0x18);
14ce26e7
FB		 3434 //ldl(ptr + 0x1c);
3435 nb_xmm_regs = 8 << data64;
3436 addr = ptr + 0xa0;
3437 for(i = 0; i < nb_xmm_regs; i++) {
a8ede8ba
FB		 3438 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3439 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
14ce26e7
FB		 3440 addr += 16;
3441 }
3442 }
3443}
1f1af9fd
FB		 3444
3445#ifndef USE_X86LDOUBLE
3446
3447void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3448{
3449 CPU86_LDoubleU temp;
3450 int e;
3451
3452 temp.d = f;
3453 /* mantissa */
3454 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3455 /* exponent + sign */
3456 e = EXPD(temp) - EXPBIAS + 16383;
3457 e |= SIGND(temp) >> 16;
3458 *pexp = e;
3459}
3460
3461CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3462{
3463 CPU86_LDoubleU temp;
3464 int e;
3465 uint64_t ll;
3466
3467 /* XXX: handle overflow ? */
3468 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3469 e |= (upper >> 4) & 0x800; /* sign */
3470 ll = (mant >> 11) & ((1LL << 52) - 1);
3471#ifdef __arm__
3472 temp.l.upper = (e << 20) | (ll >> 32);
3473 temp.l.lower = ll;
3474#else
3475 temp.ll = ll | ((uint64_t)e << 52);
3476#endif
3477 return temp.d;
3478}
3479
3480#else
3481
3482void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3483{
3484 CPU86_LDoubleU temp;
3485
3486 temp.d = f;
3487 *pmant = temp.l.lower;
3488 *pexp = temp.l.upper;
3489}
3490
3491CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3492{
3493 CPU86_LDoubleU temp;
3494
3495 temp.l.upper = upper;
3496 temp.l.lower = mant;
3497 return temp.d;
3498}
3499#endif
3500
14ce26e7
FB		 3501#ifdef TARGET_X86_64
3502
3503//#define DEBUG_MULDIV
3504
3505static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3506{
3507 *plow += a;
3508 /* carry test */
3509 if (*plow < a)
3510 (*phigh)++;
3511 *phigh += b;
3512}
3513
3514static void neg128(uint64_t *plow, uint64_t *phigh)
3515{
3516 *plow = ~ *plow;
3517 *phigh = ~ *phigh;
3518 add128(plow, phigh, 1, 0);
3519}
3520
3521static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3522{
3523 uint32_t a0, a1, b0, b1;
3524 uint64_t v;
3525
3526 a0 = a;
3527 a1 = a >> 32;
3528
3529 b0 = b;
3530 b1 = b >> 32;
3531
3532 v = (uint64_t)a0 * (uint64_t)b0;
3533 *plow = v;
3534 *phigh = 0;
3535
3536 v = (uint64_t)a0 * (uint64_t)b1;
3537 add128(plow, phigh, v << 32, v >> 32);
3538
3539 v = (uint64_t)a1 * (uint64_t)b0;
3540 add128(plow, phigh, v << 32, v >> 32);
3541
3542 v = (uint64_t)a1 * (uint64_t)b1;
3543 *phigh += v;
3544#ifdef DEBUG_MULDIV
26a76461 3545 printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
14ce26e7
FB		 3546 a, b, *phigh, *plow);
3547#endif
3548}
3549
3550static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3551{
3552 int sa, sb;
3553 sa = (a < 0);
3554 if (sa)
3555 a = -a;
3556 sb = (b < 0);
3557 if (sb)
3558 b = -b;
3559 mul64(plow, phigh, a, b);
3560 if (sa ^ sb) {
3561 neg128(plow, phigh);
3562 }
3563}
3564
45bbbb46
FB		 3565/* return TRUE if overflow */
3566static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
14ce26e7
FB		 3567{
3568 uint64_t q, r, a1, a0;
c0b24a1d 3569 int i, qb, ab;
14ce26e7
FB		 3570
3571 a0 = *plow;
3572 a1 = *phigh;
3573 if (a1 == 0) {
3574 q = a0 / b;
3575 r = a0 % b;
3576 *plow = q;
3577 *phigh = r;
3578 } else {
45bbbb46
FB		 3579 if (a1 >= b)
3580 return 1;
14ce26e7
FB		 3581 /* XXX: use a better algorithm */
3582 for(i = 0; i < 64; i++) {
c0b24a1d 3583 ab = a1 >> 63;
a8ede8ba 3584 a1 = (a1 << 1) | (a0 >> 63);
c0b24a1d 3585 if (ab || a1 >= b) {
14ce26e7
FB		 3586 a1 -= b;
3587 qb = 1;
3588 } else {
3589 qb = 0;
3590 }
14ce26e7
FB		 3591 a0 = (a0 << 1) | qb;
3592 }
a8ede8ba 3593#if defined(DEBUG_MULDIV)
26a76461 3594 printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
14ce26e7
FB		 3595 *phigh, *plow, b, a0, a1);
3596#endif
3597 *plow = a0;
3598 *phigh = a1;
3599 }
45bbbb46 3600 return 0;
14ce26e7
FB		 3601}
3602
45bbbb46
FB		 3603/* return TRUE if overflow */
3604static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
14ce26e7
FB		 3605{
3606 int sa, sb;
3607 sa = ((int64_t)*phigh < 0);
3608 if (sa)
3609 neg128(plow, phigh);
3610 sb = (b < 0);
3611 if (sb)
3612 b = -b;
45bbbb46
FB		 3613 if (div64(plow, phigh, b) != 0)
3614 return 1;
3615 if (sa ^ sb) {
3616 if (*plow > (1ULL << 63))
3617 return 1;
14ce26e7 3618 *plow = - *plow;
45bbbb46
FB		 3619 } else {
3620 if (*plow >= (1ULL << 63))
3621 return 1;
3622 }
31313213 3623 if (sa)
14ce26e7 3624 *phigh = - *phigh;
45bbbb46 3625 return 0;
14ce26e7
FB		 3626}
3627
3628void helper_mulq_EAX_T0(void)
3629{
3630 uint64_t r0, r1;
3631
3632 mul64(&r0, &r1, EAX, T0);
3633 EAX = r0;
3634 EDX = r1;
3635 CC_DST = r0;
3636 CC_SRC = r1;
3637}
3638
3639void helper_imulq_EAX_T0(void)
3640{
3641 uint64_t r0, r1;
3642
3643 imul64(&r0, &r1, EAX, T0);
3644 EAX = r0;
3645 EDX = r1;
3646 CC_DST = r0;
a8ede8ba 3647 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
14ce26e7
FB		 3648}
3649
3650void helper_imulq_T0_T1(void)
3651{
3652 uint64_t r0, r1;
3653
3654 imul64(&r0, &r1, T0, T1);
3655 T0 = r0;
3656 CC_DST = r0;
3657 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3658}
3659
3660void helper_divq_EAX_T0(void)
3661{
3662 uint64_t r0, r1;
3663 if (T0 == 0) {
3664 raise_exception(EXCP00_DIVZ);
3665 }
3666 r0 = EAX;
3667 r1 = EDX;
45bbbb46
FB		 3668 if (div64(&r0, &r1, T0))
3669 raise_exception(EXCP00_DIVZ);
14ce26e7
FB		 3670 EAX = r0;
3671 EDX = r1;
3672}
3673
3674void helper_idivq_EAX_T0(void)
3675{
3676 uint64_t r0, r1;
3677 if (T0 == 0) {
3678 raise_exception(EXCP00_DIVZ);
3679 }
3680 r0 = EAX;
3681 r1 = EDX;
45bbbb46
FB		 3682 if (idiv64(&r0, &r1, T0))
3683 raise_exception(EXCP00_DIVZ);
14ce26e7
FB		 3684 EAX = r0;
3685 EDX = r1;
3686}
3687
68cae3d8
FB		 3688void helper_bswapq_T0(void)
3689{
3690 T0 = bswap64(T0);
3691}
14ce26e7
FB		 3692#endif
3693
3d7374c5
FB		 3694void helper_hlt(void)
3695{
3696 env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
3697 env->hflags |= HF_HALTED_MASK;
3698 env->exception_index = EXCP_HLT;
3699 cpu_loop_exit();
3700}
3701
3702void helper_monitor(void)
3703{
3704 if (ECX != 0)
3705 raise_exception(EXCP0D_GPF);
3706 /* XXX: store address ? */
3707}
3708
3709void helper_mwait(void)
3710{
3711 if (ECX != 0)
3712 raise_exception(EXCP0D_GPF);
3713 /* XXX: not complete but not completely erroneous */
3714 if (env->cpu_index != 0 || env->next_cpu != NULL) {
3715 /* more than one CPU: do not sleep because another CPU may
3716 wake this one */
3717 } else {
3718 helper_hlt();
3719 }
3720}
3721
664e0f19
FB		 3722float approx_rsqrt(float a)
3723{
3724 return 1.0 / sqrt(a);
3725}
3726
3727float approx_rcp(float a)
3728{
3729 return 1.0 / a;
3730}
3731
7a0e1f41 3732void update_fp_status(void)
4d6b6c0a 3733{
7a0e1f41 3734 int rnd_type;
4d6b6c0a 3735
7a0e1f41
FB		 3736 /* set rounding mode */
3737 switch(env->fpuc & RC_MASK) {
3738 default:
3739 case RC_NEAR:
3740 rnd_type = float_round_nearest_even;
3741 break;
3742 case RC_DOWN:
3743 rnd_type = float_round_down;
3744 break;
3745 case RC_UP:
3746 rnd_type = float_round_up;
3747 break;
3748 case RC_CHOP:
3749 rnd_type = float_round_to_zero;
3750 break;
3751 }
3752 set_float_rounding_mode(rnd_type, &env->fp_status);
3753#ifdef FLOATX80
3754 switch((env->fpuc >> 8) & 3) {
3755 case 0:
3756 rnd_type = 32;
3757 break;
3758 case 2:
3759 rnd_type = 64;
3760 break;
3761 case 3:
3762 default:
3763 rnd_type = 80;
3764 break;
3765 }
3766 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
4d6b6c0a 3767#endif
7a0e1f41 3768}
664e0f19 3769
61382a50
FB		 3770#if !defined(CONFIG_USER_ONLY)
3771
3772#define MMUSUFFIX _mmu
3773#define GETPC() (__builtin_return_address(0))
3774
2c0262af
FB		 3775#define SHIFT 0
3776#include "softmmu_template.h"
3777
3778#define SHIFT 1
3779#include "softmmu_template.h"
3780
3781#define SHIFT 2
3782#include "softmmu_template.h"
3783
3784#define SHIFT 3
3785#include "softmmu_template.h"
3786
61382a50
FB		 3787#endif
3788
3789/* try to fill the TLB and return an exception if error. If retaddr is
3790 NULL, it means that the function was called in C code (i.e. not
3791 from generated code or from helper.c) */
3792/* XXX: fix it to restore all registers */
14ce26e7 3793void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
2c0262af
FB		 3794{
3795 TranslationBlock *tb;
3796 int ret;
3797 unsigned long pc;
61382a50
FB		 3798 CPUX86State *saved_env;
3799
3800 /* XXX: hack to restore env in all cases, even if not called from
3801 generated code */
3802 saved_env = env;
3803 env = cpu_single_env;
61382a50
FB		 3804
3805 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
2c0262af 3806 if (ret) {
61382a50
FB		 3807 if (retaddr) {
3808 /* now we have a real cpu fault */
3809 pc = (unsigned long)retaddr;
3810 tb = tb_find_pc(pc);
3811 if (tb) {
3812 /* the PC is inside the translated code. It means that we have
3813 a virtual CPU fault */
58fe2f10 3814 cpu_restore_state(tb, env, pc, NULL);
61382a50 3815 }
2c0262af 3816 }
0d1a29f9 3817 if (retaddr)
54ca9095 3818 raise_exception_err(env->exception_index, env->error_code);
0d1a29f9 3819 else
54ca9095 3820 raise_exception_err_norestore(env->exception_index, env->error_code);
2c0262af 3821 }
61382a50 3822 env = saved_env;
2c0262af 3823}
Qemu copy for testing