[qemu.git] / target-i386 / kvm.c

/*
 * QEMU KVM support
 *
 * Copyright (C) 2006-2008 Qumranet Technologies
 * Copyright IBM, Corp. 2008
 *
 * Authors:
 *  Anthony Liguori   <aliguori@us.ibm.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include <sys/types.h>
#include <sys/ioctl.h>
#include <sys/mman.h>

#include <linux/kvm.h>

#include "qemu-common.h"
#include "sysemu.h"
#include "kvm.h"
#include "cpu.h"

//#define DEBUG_KVM

#ifdef DEBUG_KVM
#define dprintf(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
#else
#define dprintf(fmt, ...) \
    do { } while (0)
#endif

int kvm_arch_init_vcpu(CPUState *env)
{
    struct {
        struct kvm_cpuid2 cpuid;
        struct kvm_cpuid_entry2 entries[100];
    } __attribute__((packed)) cpuid_data;
    uint32_t limit, i, j, cpuid_i;
    uint32_t eax, ebx, ecx, edx;

    cpuid_i = 0;

    cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx);
    limit = eax;

    for (i = 0; i <= limit; i++) {
        struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];

        switch (i) {
        case 4:
        case 0xb:
        case 0xd:
            for (j = 0; ; j++) {
                cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx);
                c->function = i;
                c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
                c->index = j;
                c->eax = eax;
                c->ebx = ebx;
                c->ecx = ecx;
                c->edx = edx;
                c = &cpuid_data.entries[++cpuid_i];

                if (i == 4 && eax == 0)
                    break;
                if (i == 0xb && !(ecx & 0xff00))
                    break;
                if (i == 0xd && eax == 0)
                    break;
            }
            break;
        default:
            cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
            c->function = i;
            c->eax = eax;
            c->ebx = ebx;
            c->ecx = ecx;
            c->edx = edx;
            break;
        }
    }
    cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
    limit = eax;

    for (i = 0x80000000; i <= limit; i++) {
        struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];

        cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
        c->function = i;
        c->eax = eax;
        c->ebx = ebx;
        c->ecx = ecx;
        c->edx = edx;
    }

    cpuid_data.cpuid.nent = cpuid_i;

    return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
}

static int kvm_has_msr_star(CPUState *env)
{
    static int has_msr_star;
    int ret;

    /* first time */
    if (has_msr_star == 0) {        
        struct kvm_msr_list msr_list, *kvm_msr_list;

        has_msr_star = -1;

        /* Obtain MSR list from KVM.  These are the MSRs that we must
         * save/restore */
        msr_list.nmsrs = 0;
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
        if (ret < 0)
            return 0;

        kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
                                    msr_list.nmsrs * sizeof(msr_list.indices[0]));

        kvm_msr_list->nmsrs = msr_list.nmsrs;
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
        if (ret >= 0) {
            int i;

            for (i = 0; i < kvm_msr_list->nmsrs; i++) {
                if (kvm_msr_list->indices[i] == MSR_STAR) {
                    has_msr_star = 1;
                    break;
                }
            }
        }

        free(kvm_msr_list);
    }

    if (has_msr_star == 1)
        return 1;
    return 0;
}

int kvm_arch_init(KVMState *s, int smp_cpus)
{
    int ret;

    /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
     * directly.  In order to use vm86 mode, a TSS is needed.  Since this
     * must be part of guest physical memory, we need to allocate it.  Older
     * versions of KVM just assumed that it would be at the end of physical
     * memory but that doesn't work with more than 4GB of memory.  We simply
     * refuse to work with those older versions of KVM. */
    ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
    if (ret <= 0) {
        fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
        return ret;
    }

    /* this address is 3 pages before the bios, and the bios should present
     * as unavaible memory.  FIXME, need to ensure the e820 map deals with
     * this?
     */
    return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
}
                    
static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
{
    lhs->selector = rhs->selector;
    lhs->base = rhs->base;
    lhs->limit = rhs->limit;
    lhs->type = 3;
    lhs->present = 1;
    lhs->dpl = 3;
    lhs->db = 0;
    lhs->s = 1;
    lhs->l = 0;
    lhs->g = 0;
    lhs->avl = 0;
    lhs->unusable = 0;
}

static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
{
    unsigned flags = rhs->flags;
    lhs->selector = rhs->selector;
    lhs->base = rhs->base;
    lhs->limit = rhs->limit;
    lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
    lhs->present = (flags & DESC_P_MASK) != 0;
    lhs->dpl = rhs->selector & 3;
    lhs->db = (flags >> DESC_B_SHIFT) & 1;
    lhs->s = (flags & DESC_S_MASK) != 0;
    lhs->l = (flags >> DESC_L_SHIFT) & 1;
    lhs->g = (flags & DESC_G_MASK) != 0;
    lhs->avl = (flags & DESC_AVL_MASK) != 0;
    lhs->unusable = 0;
}

static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
{
    lhs->selector = rhs->selector;
    lhs->base = rhs->base;
    lhs->limit = rhs->limit;
    lhs->flags =
	(rhs->type << DESC_TYPE_SHIFT)
	| (rhs->present * DESC_P_MASK)
	| (rhs->dpl << DESC_DPL_SHIFT)
	| (rhs->db << DESC_B_SHIFT)
	| (rhs->s * DESC_S_MASK)
	| (rhs->l << DESC_L_SHIFT)
	| (rhs->g * DESC_G_MASK)
	| (rhs->avl * DESC_AVL_MASK);
}

static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
{
    if (set)
        *kvm_reg = *qemu_reg;
    else
        *qemu_reg = *kvm_reg;
}

static int kvm_getput_regs(CPUState *env, int set)
{
    struct kvm_regs regs;
    int ret = 0;

    if (!set) {
        ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
        if (ret < 0)
            return ret;
    }

    kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
    kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
    kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
    kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
    kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
    kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
    kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
    kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
#ifdef TARGET_X86_64
    kvm_getput_reg(&regs.r8, &env->regs[8], set);
    kvm_getput_reg(&regs.r9, &env->regs[9], set);
    kvm_getput_reg(&regs.r10, &env->regs[10], set);
    kvm_getput_reg(&regs.r11, &env->regs[11], set);
    kvm_getput_reg(&regs.r12, &env->regs[12], set);
    kvm_getput_reg(&regs.r13, &env->regs[13], set);
    kvm_getput_reg(&regs.r14, &env->regs[14], set);
    kvm_getput_reg(&regs.r15, &env->regs[15], set);
#endif

    kvm_getput_reg(&regs.rflags, &env->eflags, set);
    kvm_getput_reg(&regs.rip, &env->eip, set);

    if (set)
        ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);

    return ret;
}

static int kvm_put_fpu(CPUState *env)
{
    struct kvm_fpu fpu;
    int i;

    memset(&fpu, 0, sizeof fpu);
    fpu.fsw = env->fpus & ~(7 << 11);
    fpu.fsw |= (env->fpstt & 7) << 11;
    fpu.fcw = env->fpuc;
    for (i = 0; i < 8; ++i)
	fpu.ftwx |= (!env->fptags[i]) << i;
    memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
    memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
    fpu.mxcsr = env->mxcsr;

    return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
}

static int kvm_put_sregs(CPUState *env)
{
    struct kvm_sregs sregs;

    memcpy(sregs.interrupt_bitmap,
           env->interrupt_bitmap,
           sizeof(sregs.interrupt_bitmap));

    if ((env->eflags & VM_MASK)) {
	    set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
	    set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
	    set_v8086_seg(&sregs.es, &env->segs[R_ES]);
	    set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
	    set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
	    set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
    } else {
	    set_seg(&sregs.cs, &env->segs[R_CS]);
	    set_seg(&sregs.ds, &env->segs[R_DS]);
	    set_seg(&sregs.es, &env->segs[R_ES]);
	    set_seg(&sregs.fs, &env->segs[R_FS]);
	    set_seg(&sregs.gs, &env->segs[R_GS]);
	    set_seg(&sregs.ss, &env->segs[R_SS]);

	    if (env->cr[0] & CR0_PE_MASK) {
		/* force ss cpl to cs cpl */
		sregs.ss.selector = (sregs.ss.selector & ~3) |
			(sregs.cs.selector & 3);
		sregs.ss.dpl = sregs.ss.selector & 3;
	    }
    }

    set_seg(&sregs.tr, &env->tr);
    set_seg(&sregs.ldt, &env->ldt);

    sregs.idt.limit = env->idt.limit;
    sregs.idt.base = env->idt.base;
    sregs.gdt.limit = env->gdt.limit;
    sregs.gdt.base = env->gdt.base;

    sregs.cr0 = env->cr[0];
    sregs.cr2 = env->cr[2];
    sregs.cr3 = env->cr[3];
    sregs.cr4 = env->cr[4];

    sregs.cr8 = cpu_get_apic_tpr(env);
    sregs.apic_base = cpu_get_apic_base(env);

    sregs.efer = env->efer;

    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
}

static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
                              uint32_t index, uint64_t value)
{
    entry->index = index;
    entry->data = value;
}

static int kvm_put_msrs(CPUState *env)
{
    struct {
        struct kvm_msrs info;
        struct kvm_msr_entry entries[100];
    } msr_data;
    struct kvm_msr_entry *msrs = msr_data.entries;
    int n = 0;

    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
    if (kvm_has_msr_star(env))
	kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
#ifdef TARGET_X86_64
    /* FIXME if lm capable */
    kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
    kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
    kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
    kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
#endif
    msr_data.info.nmsrs = n;

    return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);

}


static int kvm_get_fpu(CPUState *env)
{
    struct kvm_fpu fpu;
    int i, ret;

    ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
    if (ret < 0)
        return ret;

    env->fpstt = (fpu.fsw >> 11) & 7;
    env->fpus = fpu.fsw;
    env->fpuc = fpu.fcw;
    for (i = 0; i < 8; ++i)
	env->fptags[i] = !((fpu.ftwx >> i) & 1);
    memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
    memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
    env->mxcsr = fpu.mxcsr;

    return 0;
}

static int kvm_get_sregs(CPUState *env)
{
    struct kvm_sregs sregs;
    uint32_t hflags;
    int ret;

    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
    if (ret < 0)
        return ret;

    memcpy(env->interrupt_bitmap, 
           sregs.interrupt_bitmap,
           sizeof(sregs.interrupt_bitmap));

    get_seg(&env->segs[R_CS], &sregs.cs);
    get_seg(&env->segs[R_DS], &sregs.ds);
    get_seg(&env->segs[R_ES], &sregs.es);
    get_seg(&env->segs[R_FS], &sregs.fs);
    get_seg(&env->segs[R_GS], &sregs.gs);
    get_seg(&env->segs[R_SS], &sregs.ss);

    get_seg(&env->tr, &sregs.tr);
    get_seg(&env->ldt, &sregs.ldt);

    env->idt.limit = sregs.idt.limit;
    env->idt.base = sregs.idt.base;
    env->gdt.limit = sregs.gdt.limit;
    env->gdt.base = sregs.gdt.base;

    env->cr[0] = sregs.cr0;
    env->cr[2] = sregs.cr2;
    env->cr[3] = sregs.cr3;
    env->cr[4] = sregs.cr4;

    cpu_set_apic_base(env, sregs.apic_base);

    env->efer = sregs.efer;
    //cpu_set_apic_tpr(env, sregs.cr8);

#define HFLAG_COPY_MASK ~( \
			HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
			HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
			HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
			HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)


    hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
    hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
    hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
	    (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
    hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
    hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
	    (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);

    if (env->efer & MSR_EFER_LMA) {
        hflags |= HF_LMA_MASK;
    }

    if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
        hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
    } else {
        hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
		(DESC_B_SHIFT - HF_CS32_SHIFT);
        hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
		(DESC_B_SHIFT - HF_SS32_SHIFT);
        if (!(env->cr[0] & CR0_PE_MASK) ||
                   (env->eflags & VM_MASK) ||
                   !(hflags & HF_CS32_MASK)) {
                hflags |= HF_ADDSEG_MASK;
            } else {
                hflags |= ((env->segs[R_DS].base |
                                env->segs[R_ES].base |
                                env->segs[R_SS].base) != 0) <<
                    HF_ADDSEG_SHIFT;
            }
    }
    env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;

    return 0;
}

static int kvm_get_msrs(CPUState *env)
{
    struct {
        struct kvm_msrs info;
        struct kvm_msr_entry entries[100];
    } msr_data;
    struct kvm_msr_entry *msrs = msr_data.entries;
    int ret, i, n;

    n = 0;
    msrs[n++].index = MSR_IA32_SYSENTER_CS;
    msrs[n++].index = MSR_IA32_SYSENTER_ESP;
    msrs[n++].index = MSR_IA32_SYSENTER_EIP;
    if (kvm_has_msr_star(env))
	msrs[n++].index = MSR_STAR;
    msrs[n++].index = MSR_IA32_TSC;
#ifdef TARGET_X86_64
    /* FIXME lm_capable_kernel */
    msrs[n++].index = MSR_CSTAR;
    msrs[n++].index = MSR_KERNELGSBASE;
    msrs[n++].index = MSR_FMASK;
    msrs[n++].index = MSR_LSTAR;
#endif
    msr_data.info.nmsrs = n;
    ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
    if (ret < 0)
        return ret;

    for (i = 0; i < ret; i++) {
        switch (msrs[i].index) {
        case MSR_IA32_SYSENTER_CS:
            env->sysenter_cs = msrs[i].data;
            break;
        case MSR_IA32_SYSENTER_ESP:
            env->sysenter_esp = msrs[i].data;
            break;
        case MSR_IA32_SYSENTER_EIP:
            env->sysenter_eip = msrs[i].data;
            break;
        case MSR_STAR:
            env->star = msrs[i].data;
            break;
#ifdef TARGET_X86_64
        case MSR_CSTAR:
            env->cstar = msrs[i].data;
            break;
        case MSR_KERNELGSBASE:
            env->kernelgsbase = msrs[i].data;
            break;
        case MSR_FMASK:
            env->fmask = msrs[i].data;
            break;
        case MSR_LSTAR:
            env->lstar = msrs[i].data;
            break;
#endif
        case MSR_IA32_TSC:
            env->tsc = msrs[i].data;
            break;
        }
    }

    return 0;
}

int kvm_arch_put_registers(CPUState *env)
{
    int ret;

    ret = kvm_getput_regs(env, 1);
    if (ret < 0)
        return ret;

    ret = kvm_put_fpu(env);
    if (ret < 0)
        return ret;

    ret = kvm_put_sregs(env);
    if (ret < 0)
        return ret;

    ret = kvm_put_msrs(env);
    if (ret < 0)
        return ret;

    return 0;
}

int kvm_arch_get_registers(CPUState *env)
{
    int ret;

    ret = kvm_getput_regs(env, 0);
    if (ret < 0)
        return ret;

    ret = kvm_get_fpu(env);
    if (ret < 0)
        return ret;

    ret = kvm_get_sregs(env);
    if (ret < 0)
        return ret;

    ret = kvm_get_msrs(env);
    if (ret < 0)
        return ret;

    return 0;
}

int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
{
    /* Try to inject an interrupt if the guest can accept it */
    if (run->ready_for_interrupt_injection &&
        (env->interrupt_request & CPU_INTERRUPT_HARD) &&
        (env->eflags & IF_MASK)) {
        int irq;

        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
        irq = cpu_get_pic_interrupt(env);
        if (irq >= 0) {
            struct kvm_interrupt intr;
            intr.irq = irq;
            /* FIXME: errors */
            dprintf("injected interrupt %d\n", irq);
            kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
        }
    }

    /* If we have an interrupt but the guest is not ready to receive an
     * interrupt, request an interrupt window exit.  This will
     * cause a return to userspace as soon as the guest is ready to
     * receive interrupts. */
    if ((env->interrupt_request & CPU_INTERRUPT_HARD))
        run->request_interrupt_window = 1;
    else
        run->request_interrupt_window = 0;

    dprintf("setting tpr\n");
    run->cr8 = cpu_get_apic_tpr(env);

    return 0;
}

int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
{
    if (run->if_flag)
        env->eflags |= IF_MASK;
    else
        env->eflags &= ~IF_MASK;
    
    cpu_set_apic_tpr(env, run->cr8);
    cpu_set_apic_base(env, run->apic_base);

    return 0;
}

static int kvm_handle_halt(CPUState *env)
{
    if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
          (env->eflags & IF_MASK)) &&
        !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
        env->halted = 1;
        env->exception_index = EXCP_HLT;
        return 0;
    }

    return 1;
}

int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
{
    int ret = 0;

    switch (run->exit_reason) {
    case KVM_EXIT_HLT:
        dprintf("handle_hlt\n");
        ret = kvm_handle_halt(env);
        break;
    }

    return ret;
}
Commit	Line	Data
05330448 AL	1	/*
	2	* QEMU KVM support
	3	*
	4	* Copyright (C) 2006-2008 Qumranet Technologies
	5	* Copyright IBM, Corp. 2008
	6	*
	7	* Authors:
	8	* Anthony Liguori <aliguori@us.ibm.com>
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	11	* See the COPYING file in the top-level directory.
	12	*
	13	*/
	14
	15	#include <sys/types.h>
	16	#include <sys/ioctl.h>
	17	#include <sys/mman.h>
	18
	19	#include <linux/kvm.h>
	20
	21	#include "qemu-common.h"
	22	#include "sysemu.h"
	23	#include "kvm.h"
	24	#include "cpu.h"
	25
	26	//#define DEBUG_KVM
	27
	28	#ifdef DEBUG_KVM
	29	#define dprintf(fmt, ...) \
	30	do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
	31	#else
	32	#define dprintf(fmt, ...) \
	33	do { } while (0)
	34	#endif
	35
	36	int kvm_arch_init_vcpu(CPUState *env)
	37	{
	38	struct {
486bd5a2 AL	39	struct kvm_cpuid2 cpuid;
486bd5a2 AL	40	struct kvm_cpuid_entry2 entries[100];
05330448	41	} __attribute__((packed)) cpuid_data;
486bd5a2	42	uint32_t limit, i, j, cpuid_i;
05330448 AL	43	uint32_t eax, ebx, ecx, edx;
	44
	45	cpuid_i = 0;
	46
e00b6f80	47	cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx);
05330448 AL	48	limit = eax;
	49
	50	for (i = 0; i <= limit; i++) {
486bd5a2 AL	51	struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
	52
	53	switch (i) {
	54	case 4:
	55	case 0xb:
	56	case 0xd:
	57	for (j = 0; ; j++) {
	58	cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx);
	59	c->function = i;
	60	c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
	61	c->index = j;
	62	c->eax = eax;
	63	c->ebx = ebx;
	64	c->ecx = ecx;
	65	c->edx = edx;
	66	c = &cpuid_data.entries[++cpuid_i];
	67
	68	if (i == 4 && eax == 0)
	69	break;
	70	if (i == 0xb && !(ecx & 0xff00))
	71	break;
	72	if (i == 0xd && eax == 0)
	73	break;
	74	}
	75	break;
	76	default:
	77	cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
	78	c->function = i;
	79	c->eax = eax;
	80	c->ebx = ebx;
	81	c->ecx = ecx;
	82	c->edx = edx;
	83	break;
	84	}
05330448	85	}
e00b6f80	86	cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
05330448 AL	87	limit = eax;
	88
	89	for (i = 0x80000000; i <= limit; i++) {
486bd5a2	90	struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
05330448	91
e00b6f80	92	cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
05330448 AL	93	c->function = i;
	94	c->eax = eax;
	95	c->ebx = ebx;
	96	c->ecx = ecx;
	97	c->edx = edx;
	98	}
	99
	100	cpuid_data.cpuid.nent = cpuid_i;
	101
486bd5a2	102	return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448 AL	103	}
	104
	105	static int kvm_has_msr_star(CPUState *env)
	106	{
	107	static int has_msr_star;
	108	int ret;
	109
	110	/* first time */
	111	if (has_msr_star == 0) {
	112	struct kvm_msr_list msr_list, *kvm_msr_list;
	113
	114	has_msr_star = -1;
	115
	116	/* Obtain MSR list from KVM. These are the MSRs that we must
	117	* save/restore */
4c9f7372	118	msr_list.nmsrs = 0;
05330448 AL	119	ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
	120	if (ret < 0)
	121	return 0;
	122
05330448 AL	123	kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
05330448 AL	124	msr_list.nmsrs * sizeof(msr_list.indices[0]));
05330448	125
55308450	126	kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448 AL	127	ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
	128	if (ret >= 0) {
	129	int i;
	130
	131	for (i = 0; i < kvm_msr_list->nmsrs; i++) {
	132	if (kvm_msr_list->indices[i] == MSR_STAR) {
	133	has_msr_star = 1;
	134	break;
	135	}
	136	}
	137	}
	138
	139	free(kvm_msr_list);
	140	}
	141
	142	if (has_msr_star == 1)
	143	return 1;
	144	return 0;
	145	}
	146
	147	int kvm_arch_init(KVMState *s, int smp_cpus)
	148	{
	149	int ret;
	150
	151	/* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
	152	* directly. In order to use vm86 mode, a TSS is needed. Since this
	153	* must be part of guest physical memory, we need to allocate it. Older
	154	* versions of KVM just assumed that it would be at the end of physical
	155	* memory but that doesn't work with more than 4GB of memory. We simply
	156	* refuse to work with those older versions of KVM. */
984b5181	157	ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448 AL	158	if (ret <= 0) {
	159	fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
	160	return ret;
	161	}
	162
	163	/* this address is 3 pages before the bios, and the bios should present
	164	* as unavaible memory. FIXME, need to ensure the e820 map deals with
	165	* this?
	166	*/
984b5181	167	return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
05330448 AL	168	}
	169
	170	static void set_v8086_seg(struct kvm_segment lhs, const SegmentCache rhs)
	171	{
	172	lhs->selector = rhs->selector;
	173	lhs->base = rhs->base;
	174	lhs->limit = rhs->limit;
	175	lhs->type = 3;
	176	lhs->present = 1;
	177	lhs->dpl = 3;
	178	lhs->db = 0;
	179	lhs->s = 1;
	180	lhs->l = 0;
	181	lhs->g = 0;
	182	lhs->avl = 0;
	183	lhs->unusable = 0;
	184	}
	185
	186	static void set_seg(struct kvm_segment lhs, const SegmentCache rhs)
	187	{
	188	unsigned flags = rhs->flags;
	189	lhs->selector = rhs->selector;
	190	lhs->base = rhs->base;
	191	lhs->limit = rhs->limit;
	192	lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
	193	lhs->present = (flags & DESC_P_MASK) != 0;
	194	lhs->dpl = rhs->selector & 3;
	195	lhs->db = (flags >> DESC_B_SHIFT) & 1;
	196	lhs->s = (flags & DESC_S_MASK) != 0;
	197	lhs->l = (flags >> DESC_L_SHIFT) & 1;
	198	lhs->g = (flags & DESC_G_MASK) != 0;
	199	lhs->avl = (flags & DESC_AVL_MASK) != 0;
	200	lhs->unusable = 0;
	201	}
	202
	203	static void get_seg(SegmentCache lhs, const struct kvm_segment rhs)
	204	{
	205	lhs->selector = rhs->selector;
	206	lhs->base = rhs->base;
	207	lhs->limit = rhs->limit;
	208	lhs->flags =
	209	(rhs->type << DESC_TYPE_SHIFT)
	210	\| (rhs->present * DESC_P_MASK)
	211	\| (rhs->dpl << DESC_DPL_SHIFT)
	212	\| (rhs->db << DESC_B_SHIFT)
	213	\| (rhs->s * DESC_S_MASK)
	214	\| (rhs->l << DESC_L_SHIFT)
	215	\| (rhs->g * DESC_G_MASK)
	216	\| (rhs->avl * DESC_AVL_MASK);
	217	}
	218
	219	static void kvm_getput_reg(__u64 kvm_reg, target_ulong qemu_reg, int set)
	220	{
	221	if (set)
	222	kvm_reg = qemu_reg;
	223	else
	224	qemu_reg = kvm_reg;
	225	}
	226
	227	static int kvm_getput_regs(CPUState *env, int set)
	228	{
	229	struct kvm_regs regs;
	230	int ret = 0;
	231
232	if (!set) {
233	ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
234	if (ret < 0)
235	return ret;
236	}
237
238	kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
239	kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
240	kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
241	kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
242	kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
243	kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
244	kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
245	kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
246	#ifdef TARGET_X86_64
247	kvm_getput_reg(&regs.r8, &env->regs[8], set);
248	kvm_getput_reg(&regs.r9, &env->regs[9], set);
249	kvm_getput_reg(&regs.r10, &env->regs[10], set);
250	kvm_getput_reg(&regs.r11, &env->regs[11], set);
251	kvm_getput_reg(&regs.r12, &env->regs[12], set);
252	kvm_getput_reg(&regs.r13, &env->regs[13], set);
253	kvm_getput_reg(&regs.r14, &env->regs[14], set);
254	kvm_getput_reg(&regs.r15, &env->regs[15], set);
255	#endif
256
257	kvm_getput_reg(&regs.rflags, &env->eflags, set);
258	kvm_getput_reg(&regs.rip, &env->eip, set);
259
260	if (set)
261	ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
262
263	return ret;
264	}
265
266	static int kvm_put_fpu(CPUState *env)
267	{
268	struct kvm_fpu fpu;
269	int i;
270
271	memset(&fpu, 0, sizeof fpu);
272	fpu.fsw = env->fpus & ~(7 << 11);
273	fpu.fsw \|= (env->fpstt & 7) << 11;
274	fpu.fcw = env->fpuc;
275	for (i = 0; i < 8; ++i)
276	fpu.ftwx \|= (!env->fptags[i]) << i;
277	memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
278	memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
279	fpu.mxcsr = env->mxcsr;
280
281	return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
282	}
283
284	static int kvm_put_sregs(CPUState *env)
285	{
286	struct kvm_sregs sregs;
287
288	memcpy(sregs.interrupt_bitmap,
289	env->interrupt_bitmap,
290	sizeof(sregs.interrupt_bitmap));
291
292	if ((env->eflags & VM_MASK)) {
293	set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
294	set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
295	set_v8086_seg(&sregs.es, &env->segs[R_ES]);
296	set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
297	set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
298	set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
299	} else {
300	set_seg(&sregs.cs, &env->segs[R_CS]);
301	set_seg(&sregs.ds, &env->segs[R_DS]);
302	set_seg(&sregs.es, &env->segs[R_ES]);
303	set_seg(&sregs.fs, &env->segs[R_FS]);
304	set_seg(&sregs.gs, &env->segs[R_GS]);
305	set_seg(&sregs.ss, &env->segs[R_SS]);
306
307	if (env->cr[0] & CR0_PE_MASK) {
308	/* force ss cpl to cs cpl */
309	sregs.ss.selector = (sregs.ss.selector & ~3) \|
310	(sregs.cs.selector & 3);
311	sregs.ss.dpl = sregs.ss.selector & 3;
312	}
313	}
314
315	set_seg(&sregs.tr, &env->tr);
316	set_seg(&sregs.ldt, &env->ldt);
317
318	sregs.idt.limit = env->idt.limit;
319	sregs.idt.base = env->idt.base;
320	sregs.gdt.limit = env->gdt.limit;
321	sregs.gdt.base = env->gdt.base;
322
323	sregs.cr0 = env->cr[0];
324	sregs.cr2 = env->cr[2];
325	sregs.cr3 = env->cr[3];
326	sregs.cr4 = env->cr[4];
327
328	sregs.cr8 = cpu_get_apic_tpr(env);
329	sregs.apic_base = cpu_get_apic_base(env);
330
331	sregs.efer = env->efer;
332
333	return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
334	}
335
336	static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
337	uint32_t index, uint64_t value)
338	{
339	entry->index = index;
340	entry->data = value;
341	}
342
343	static int kvm_put_msrs(CPUState *env)
344	{
345	struct {
346	struct kvm_msrs info;
347	struct kvm_msr_entry entries[100];
348	} msr_data;
349	struct kvm_msr_entry *msrs = msr_data.entries;
350	int n = 0;
351
352	kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
353	kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
354	kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
355	if (kvm_has_msr_star(env))
356	kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
357	kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
358	#ifdef TARGET_X86_64
359	/* FIXME if lm capable */
360	kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
361	kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
362	kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
363	kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
364	#endif
365	msr_data.info.nmsrs = n;
366
367	return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
368
369	}
370
371
372	static int kvm_get_fpu(CPUState *env)
373	{
374	struct kvm_fpu fpu;
375	int i, ret;
376
377	ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
378	if (ret < 0)
379	return ret;
380
381	env->fpstt = (fpu.fsw >> 11) & 7;
382	env->fpus = fpu.fsw;
383	env->fpuc = fpu.fcw;
384	for (i = 0; i < 8; ++i)
385	env->fptags[i] = !((fpu.ftwx >> i) & 1);
386	memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
387	memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
388	env->mxcsr = fpu.mxcsr;
389
390	return 0;
391	}
392
393	static int kvm_get_sregs(CPUState *env)
394	{
395	struct kvm_sregs sregs;
396	uint32_t hflags;
397	int ret;
398
399	ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
400	if (ret < 0)
401	return ret;
402
403	memcpy(env->interrupt_bitmap,
404	sregs.interrupt_bitmap,
405	sizeof(sregs.interrupt_bitmap));
406
407	get_seg(&env->segs[R_CS], &sregs.cs);
408	get_seg(&env->segs[R_DS], &sregs.ds);
409	get_seg(&env->segs[R_ES], &sregs.es);
410	get_seg(&env->segs[R_FS], &sregs.fs);
411	get_seg(&env->segs[R_GS], &sregs.gs);
412	get_seg(&env->segs[R_SS], &sregs.ss);
413
414	get_seg(&env->tr, &sregs.tr);
415	get_seg(&env->ldt, &sregs.ldt);
416
417	env->idt.limit = sregs.idt.limit;
418	env->idt.base = sregs.idt.base;
419	env->gdt.limit = sregs.gdt.limit;
420	env->gdt.base = sregs.gdt.base;
421
422	env->cr[0] = sregs.cr0;
423	env->cr[2] = sregs.cr2;
424	env->cr[3] = sregs.cr3;
425	env->cr[4] = sregs.cr4;
426
427	cpu_set_apic_base(env, sregs.apic_base);
428
429	env->efer = sregs.efer;
430	//cpu_set_apic_tpr(env, sregs.cr8);
431
432	#define HFLAG_COPY_MASK ~( \
433	HF_CPL_MASK \| HF_PE_MASK \| HF_MP_MASK \| HF_EM_MASK \| \
434	HF_TS_MASK \| HF_TF_MASK \| HF_VM_MASK \| HF_IOPL_MASK \| \
435	HF_OSFXSR_MASK \| HF_LMA_MASK \| HF_CS32_MASK \| \
436	HF_SS32_MASK \| HF_CS64_MASK \| HF_ADDSEG_MASK)
437
438
439
440	hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
441	hflags \|= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
442	hflags \|= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
443	(HF_MP_MASK \| HF_EM_MASK \| HF_TS_MASK);
444	hflags \|= (env->eflags & (HF_TF_MASK \| HF_VM_MASK \| HF_IOPL_MASK));
445	hflags \|= (env->cr[4] & CR4_OSFXSR_MASK) <<
446	(HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
447
448	if (env->efer & MSR_EFER_LMA) {
449	hflags \|= HF_LMA_MASK;
450	}
451
452	if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
453	hflags \|= HF_CS32_MASK \| HF_SS32_MASK \| HF_CS64_MASK;
454	} else {
455	hflags \|= (env->segs[R_CS].flags & DESC_B_MASK) >>
456	(DESC_B_SHIFT - HF_CS32_SHIFT);
457	hflags \|= (env->segs[R_SS].flags & DESC_B_MASK) >>
458	(DESC_B_SHIFT - HF_SS32_SHIFT);
459	if (!(env->cr[0] & CR0_PE_MASK) \|\|
460	(env->eflags & VM_MASK) \|\|
461	!(hflags & HF_CS32_MASK)) {
462	hflags \|= HF_ADDSEG_MASK;
463	} else {
464	hflags \|= ((env->segs[R_DS].base \|
465	env->segs[R_ES].base \|
466	env->segs[R_SS].base) != 0) <<
467	HF_ADDSEG_SHIFT;
468	}
469	}
470	env->hflags = (env->hflags & HFLAG_COPY_MASK) \| hflags;
05330448 AL	471
	472	return 0;
	473	}
	474
	475	static int kvm_get_msrs(CPUState *env)
	476	{
	477	struct {
	478	struct kvm_msrs info;
	479	struct kvm_msr_entry entries[100];
	480	} msr_data;
	481	struct kvm_msr_entry *msrs = msr_data.entries;
	482	int ret, i, n;
	483
	484	n = 0;
	485	msrs[n++].index = MSR_IA32_SYSENTER_CS;
	486	msrs[n++].index = MSR_IA32_SYSENTER_ESP;
	487	msrs[n++].index = MSR_IA32_SYSENTER_EIP;
	488	if (kvm_has_msr_star(env))
	489	msrs[n++].index = MSR_STAR;
	490	msrs[n++].index = MSR_IA32_TSC;
	491	#ifdef TARGET_X86_64
	492	/* FIXME lm_capable_kernel */
	493	msrs[n++].index = MSR_CSTAR;
	494	msrs[n++].index = MSR_KERNELGSBASE;
	495	msrs[n++].index = MSR_FMASK;
	496	msrs[n++].index = MSR_LSTAR;
	497	#endif
	498	msr_data.info.nmsrs = n;
	499	ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
	500	if (ret < 0)
	501	return ret;
	502
	503	for (i = 0; i < ret; i++) {
	504	switch (msrs[i].index) {
	505	case MSR_IA32_SYSENTER_CS:
	506	env->sysenter_cs = msrs[i].data;
	507	break;
	508	case MSR_IA32_SYSENTER_ESP:
	509	env->sysenter_esp = msrs[i].data;
	510	break;
	511	case MSR_IA32_SYSENTER_EIP:
	512	env->sysenter_eip = msrs[i].data;
	513	break;
	514	case MSR_STAR:
	515	env->star = msrs[i].data;
	516	break;
	517	#ifdef TARGET_X86_64
	518	case MSR_CSTAR:
	519	env->cstar = msrs[i].data;
	520	break;
	521	case MSR_KERNELGSBASE:
	522	env->kernelgsbase = msrs[i].data;
	523	break;
	524	case MSR_FMASK:
	525	env->fmask = msrs[i].data;
	526	break;
	527	case MSR_LSTAR:
	528	env->lstar = msrs[i].data;
	529	break;
	530	#endif
	531	case MSR_IA32_TSC:
	532	env->tsc = msrs[i].data;
	533	break;
	534	}
535	}
536
537	return 0;
538	}
539
540	int kvm_arch_put_registers(CPUState *env)
541	{
542	int ret;
543
544	ret = kvm_getput_regs(env, 1);
545	if (ret < 0)
546	return ret;
547
548	ret = kvm_put_fpu(env);
549	if (ret < 0)
550	return ret;
551
552	ret = kvm_put_sregs(env);
553	if (ret < 0)
554	return ret;
555
556	ret = kvm_put_msrs(env);
557	if (ret < 0)
558	return ret;
559
560	return 0;
561	}
562
563	int kvm_arch_get_registers(CPUState *env)
564	{
565	int ret;
566
567	ret = kvm_getput_regs(env, 0);
568	if (ret < 0)
569	return ret;
570
571	ret = kvm_get_fpu(env);
572	if (ret < 0)
573	return ret;
574
575	ret = kvm_get_sregs(env);
576	if (ret < 0)
577	return ret;
578
579	ret = kvm_get_msrs(env);
580	if (ret < 0)
581	return ret;
582
583	return 0;
584	}
585
586	int kvm_arch_pre_run(CPUState env, struct kvm_run run)
587	{
588	/* Try to inject an interrupt if the guest can accept it */
589	if (run->ready_for_interrupt_injection &&
590	(env->interrupt_request & CPU_INTERRUPT_HARD) &&
591	(env->eflags & IF_MASK)) {
592	int irq;
593
594	env->interrupt_request &= ~CPU_INTERRUPT_HARD;
595	irq = cpu_get_pic_interrupt(env);
596	if (irq >= 0) {
597	struct kvm_interrupt intr;
598	intr.irq = irq;
599	/* FIXME: errors */
600	dprintf("injected interrupt %d\n", irq);
601	kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
602	}
603	}
604
605	/* If we have an interrupt but the guest is not ready to receive an
606	* interrupt, request an interrupt window exit. This will
607	* cause a return to userspace as soon as the guest is ready to
608	* receive interrupts. */
609	if ((env->interrupt_request & CPU_INTERRUPT_HARD))
610	run->request_interrupt_window = 1;
611	else
612	run->request_interrupt_window = 0;
613
614	dprintf("setting tpr\n");
615	run->cr8 = cpu_get_apic_tpr(env);
616
617	return 0;
618	}
619
620	int kvm_arch_post_run(CPUState env, struct kvm_run run)
621	{
622	if (run->if_flag)
623	env->eflags \|= IF_MASK;
624	else
625	env->eflags &= ~IF_MASK;
626
627	cpu_set_apic_tpr(env, run->cr8);
628	cpu_set_apic_base(env, run->apic_base);
629
630	return 0;
631	}
632
633	static int kvm_handle_halt(CPUState *env)
634	{
635	if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
636	(env->eflags & IF_MASK)) &&
637	!(env->interrupt_request & CPU_INTERRUPT_NMI)) {
638	env->halted = 1;
639	env->exception_index = EXCP_HLT;
640	return 0;
641	}
642
643	return 1;
644	}
645
646	int kvm_arch_handle_exit(CPUState env, struct kvm_run run)
647	{
648	int ret = 0;
649
650	switch (run->exit_reason) {
651	case KVM_EXIT_HLT:
652	dprintf("handle_hlt\n");
653	ret = kvm_handle_halt(env);
654	break;
655	}
656
657	return ret;
658	}