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preserve the hypervisor bit while KVM trims the CPUID bits
[qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
05330448
AL		 26
27//#define DEBUG_KVM
28
29#ifdef DEBUG_KVM
30#define dprintf(fmt, ...) \
31 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
32#else
33#define dprintf(fmt, ...) \
34 do { } while (0)
35#endif
36
b827df58
AK		 37#ifdef KVM_CAP_EXT_CPUID
38
39static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
40{
41 struct kvm_cpuid2 *cpuid;
42 int r, size;
43
44 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
45 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
46 cpuid->nent = max;
47 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 48 if (r == 0 && cpuid->nent >= max) {
49 r = -E2BIG;
50 }
b827df58
AK		 51 if (r < 0) {
52 if (r == -E2BIG) {
53 qemu_free(cpuid);
54 return NULL;
55 } else {
56 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
57 strerror(-r));
58 exit(1);
59 }
60 }
61 return cpuid;
62}
63
64uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
65{
66 struct kvm_cpuid2 *cpuid;
67 int i, max;
68 uint32_t ret = 0;
69 uint32_t cpuid_1_edx;
70
71 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
72 return -1U;
73 }
74
75 max = 1;
76 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
77 max *= 2;
78 }
79
80 for (i = 0; i < cpuid->nent; ++i) {
81 if (cpuid->entries[i].function == function) {
82 switch (reg) {
83 case R_EAX:
84 ret = cpuid->entries[i].eax;
85 break;
86 case R_EBX:
87 ret = cpuid->entries[i].ebx;
88 break;
89 case R_ECX:
90 ret = cpuid->entries[i].ecx;
91 break;
92 case R_EDX:
93 ret = cpuid->entries[i].edx;
94 if (function == 0x80000001) {
95 /* On Intel, kvm returns cpuid according to the Intel spec,
96 * so add missing bits according to the AMD spec:
97 */
98 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
99 ret |= cpuid_1_edx & 0xdfeff7ff;
100 }
101 break;
102 }
103 }
104 }
105
106 qemu_free(cpuid);
107
108 return ret;
109}
110
111#else
112
113uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
114{
115 return -1U;
116}
117
118#endif
119
6c1f42fe
AP		 120static void kvm_trim_features(uint32_t *features, uint32_t supported)
121{
122 int i;
123 uint32_t mask;
124
125 for (i = 0; i < 32; ++i) {
126 mask = 1U << i;
127 if ((*features & mask) && !(supported & mask)) {
128 *features &= ~mask;
129 }
130 }
131}
132
05330448
AL		 133int kvm_arch_init_vcpu(CPUState *env)
134{
135 struct {
486bd5a2
AL		 136 struct kvm_cpuid2 cpuid;
137 struct kvm_cpuid_entry2 entries[100];
05330448 138 } __attribute__((packed)) cpuid_data;
486bd5a2 139 uint32_t limit, i, j, cpuid_i;
a33609ca 140 uint32_t unused;
05330448 141
f8d926e9
JK		 142 env->mp_state = KVM_MP_STATE_RUNNABLE;
143
6c1f42fe
AP		 144 kvm_trim_features(&env->cpuid_features,
145 kvm_arch_get_supported_cpuid(env, 1, R_EDX));
6c0d7ee8
AP		 146
147 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
6c1f42fe
AP		 148 kvm_trim_features(&env->cpuid_ext_features,
149 kvm_arch_get_supported_cpuid(env, 1, R_ECX));
6c0d7ee8
AP		 150 env->cpuid_ext_features |= i;
151
6c1f42fe
AP		 152 kvm_trim_features(&env->cpuid_ext2_features,
153 kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
154 kvm_trim_features(&env->cpuid_ext3_features,
155 kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
156
05330448
AL		 157 cpuid_i = 0;
158
a33609ca 159 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 160
161 for (i = 0; i <= limit; i++) {
486bd5a2
AL		 162 struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
163
164 switch (i) {
a36b1029
AL		 165 case 2: {
166 /* Keep reading function 2 till all the input is received */
167 int times;
168
a36b1029 169 c->function = i;
a33609ca
AL		 170 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
171 KVM_CPUID_FLAG_STATE_READ_NEXT;
172 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
173 times = c->eax & 0xff;
a36b1029
AL		 174
175 for (j = 1; j < times; ++j) {
a33609ca 176 c = &cpuid_data.entries[cpuid_i++];
a36b1029 177 c->function = i;
a33609ca
AL		 178 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
179 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 180 }
181 break;
182 }
486bd5a2
AL		 183 case 4:
184 case 0xb:
185 case 0xd:
186 for (j = 0; ; j++) {
486bd5a2
AL		 187 c->function = i;
188 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
189 c->index = j;
a33609ca 190 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 191
a33609ca 192 if (i == 4 && c->eax == 0)
486bd5a2 193 break;
a33609ca 194 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 195 break;
a33609ca 196 if (i == 0xd && c->eax == 0)
486bd5a2 197 break;
a33609ca
AL		 198
199 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 200 }
201 break;
202 default:
486bd5a2 203 c->function = i;
a33609ca
AL		 204 c->flags = 0;
205 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 206 break;
207 }
05330448 208 }
a33609ca 209 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 210
211 for (i = 0x80000000; i <= limit; i++) {
486bd5a2 212 struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
05330448 213
05330448 214 c->function = i;
a33609ca
AL		 215 c->flags = 0;
216 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 217 }
218
219 cpuid_data.cpuid.nent = cpuid_i;
220
486bd5a2 221 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 222}
223
224static int kvm_has_msr_star(CPUState *env)
225{
226 static int has_msr_star;
227 int ret;
228
229 /* first time */
230 if (has_msr_star == 0) {
231 struct kvm_msr_list msr_list, *kvm_msr_list;
232
233 has_msr_star = -1;
234
235 /* Obtain MSR list from KVM. These are the MSRs that we must
236 * save/restore */
4c9f7372 237 msr_list.nmsrs = 0;
05330448
AL		 238 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
239 if (ret < 0)
240 return 0;
241
05330448
AL		 242 kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
243 msr_list.nmsrs * sizeof(msr_list.indices[0]));
05330448 244
55308450 245 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 246 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
247 if (ret >= 0) {
248 int i;
249
250 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
251 if (kvm_msr_list->indices[i] == MSR_STAR) {
252 has_msr_star = 1;
253 break;
254 }
255 }
256 }
257
258 free(kvm_msr_list);
259 }
260
261 if (has_msr_star == 1)
262 return 1;
263 return 0;
264}
265
266int kvm_arch_init(KVMState *s, int smp_cpus)
267{
268 int ret;
269
270 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
271 * directly. In order to use vm86 mode, a TSS is needed. Since this
272 * must be part of guest physical memory, we need to allocate it. Older
273 * versions of KVM just assumed that it would be at the end of physical
274 * memory but that doesn't work with more than 4GB of memory. We simply
275 * refuse to work with those older versions of KVM. */
984b5181 276 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 277 if (ret <= 0) {
278 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
279 return ret;
280 }
281
282 /* this address is 3 pages before the bios, and the bios should present
283 * as unavaible memory. FIXME, need to ensure the e820 map deals with
284 * this?
285 */
984b5181 286 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
05330448
AL		 287}
288
289static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
290{
291 lhs->selector = rhs->selector;
292 lhs->base = rhs->base;
293 lhs->limit = rhs->limit;
294 lhs->type = 3;
295 lhs->present = 1;
296 lhs->dpl = 3;
297 lhs->db = 0;
298 lhs->s = 1;
299 lhs->l = 0;
300 lhs->g = 0;
301 lhs->avl = 0;
302 lhs->unusable = 0;
303}
304
305static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
306{
307 unsigned flags = rhs->flags;
308 lhs->selector = rhs->selector;
309 lhs->base = rhs->base;
310 lhs->limit = rhs->limit;
311 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
312 lhs->present = (flags & DESC_P_MASK) != 0;
313 lhs->dpl = rhs->selector & 3;
314 lhs->db = (flags >> DESC_B_SHIFT) & 1;
315 lhs->s = (flags & DESC_S_MASK) != 0;
316 lhs->l = (flags >> DESC_L_SHIFT) & 1;
317 lhs->g = (flags & DESC_G_MASK) != 0;
318 lhs->avl = (flags & DESC_AVL_MASK) != 0;
319 lhs->unusable = 0;
320}
321
322static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
323{
324 lhs->selector = rhs->selector;
325 lhs->base = rhs->base;
326 lhs->limit = rhs->limit;
327 lhs->flags =
328 (rhs->type << DESC_TYPE_SHIFT)
329 | (rhs->present * DESC_P_MASK)
330 | (rhs->dpl << DESC_DPL_SHIFT)
331 | (rhs->db << DESC_B_SHIFT)
332 | (rhs->s * DESC_S_MASK)
333 | (rhs->l << DESC_L_SHIFT)
334 | (rhs->g * DESC_G_MASK)
335 | (rhs->avl * DESC_AVL_MASK);
336}
337
338static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
339{
340 if (set)
341 *kvm_reg = *qemu_reg;
342 else
343 *qemu_reg = *kvm_reg;
344}
345
346static int kvm_getput_regs(CPUState *env, int set)
347{
348 struct kvm_regs regs;
349 int ret = 0;
350
351 if (!set) {
352 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
353 if (ret < 0)
354 return ret;
355 }
356
357 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
358 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
359 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
360 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
361 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
362 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
363 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
364 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
365#ifdef TARGET_X86_64
366 kvm_getput_reg(&regs.r8, &env->regs[8], set);
367 kvm_getput_reg(&regs.r9, &env->regs[9], set);
368 kvm_getput_reg(&regs.r10, &env->regs[10], set);
369 kvm_getput_reg(&regs.r11, &env->regs[11], set);
370 kvm_getput_reg(&regs.r12, &env->regs[12], set);
371 kvm_getput_reg(&regs.r13, &env->regs[13], set);
372 kvm_getput_reg(&regs.r14, &env->regs[14], set);
373 kvm_getput_reg(&regs.r15, &env->regs[15], set);
374#endif
375
376 kvm_getput_reg(&regs.rflags, &env->eflags, set);
377 kvm_getput_reg(&regs.rip, &env->eip, set);
378
379 if (set)
380 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
381
382 return ret;
383}
384
385static int kvm_put_fpu(CPUState *env)
386{
387 struct kvm_fpu fpu;
388 int i;
389
390 memset(&fpu, 0, sizeof fpu);
391 fpu.fsw = env->fpus & ~(7 << 11);
392 fpu.fsw |= (env->fpstt & 7) << 11;
393 fpu.fcw = env->fpuc;
394 for (i = 0; i < 8; ++i)
395 fpu.ftwx |= (!env->fptags[i]) << i;
396 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
397 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
398 fpu.mxcsr = env->mxcsr;
399
400 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
401}
402
403static int kvm_put_sregs(CPUState *env)
404{
405 struct kvm_sregs sregs;
406
407 memcpy(sregs.interrupt_bitmap,
408 env->interrupt_bitmap,
409 sizeof(sregs.interrupt_bitmap));
410
411 if ((env->eflags & VM_MASK)) {
412 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
413 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
414 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
415 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
416 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
417 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
418 } else {
419 set_seg(&sregs.cs, &env->segs[R_CS]);
420 set_seg(&sregs.ds, &env->segs[R_DS]);
421 set_seg(&sregs.es, &env->segs[R_ES]);
422 set_seg(&sregs.fs, &env->segs[R_FS]);
423 set_seg(&sregs.gs, &env->segs[R_GS]);
424 set_seg(&sregs.ss, &env->segs[R_SS]);
425
426 if (env->cr[0] & CR0_PE_MASK) {
427 /* force ss cpl to cs cpl */
428 sregs.ss.selector = (sregs.ss.selector & ~3) |
429 (sregs.cs.selector & 3);
430 sregs.ss.dpl = sregs.ss.selector & 3;
431 }
432 }
433
434 set_seg(&sregs.tr, &env->tr);
435 set_seg(&sregs.ldt, &env->ldt);
436
437 sregs.idt.limit = env->idt.limit;
438 sregs.idt.base = env->idt.base;
439 sregs.gdt.limit = env->gdt.limit;
440 sregs.gdt.base = env->gdt.base;
441
442 sregs.cr0 = env->cr[0];
443 sregs.cr2 = env->cr[2];
444 sregs.cr3 = env->cr[3];
445 sregs.cr4 = env->cr[4];
446
447 sregs.cr8 = cpu_get_apic_tpr(env);
448 sregs.apic_base = cpu_get_apic_base(env);
449
450 sregs.efer = env->efer;
451
452 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
453}
454
455static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
456 uint32_t index, uint64_t value)
457{
458 entry->index = index;
459 entry->data = value;
460}
461
462static int kvm_put_msrs(CPUState *env)
463{
464 struct {
465 struct kvm_msrs info;
466 struct kvm_msr_entry entries[100];
467 } msr_data;
468 struct kvm_msr_entry *msrs = msr_data.entries;
469 int n = 0;
470
471 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
472 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
473 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
474 if (kvm_has_msr_star(env))
475 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
476 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
477#ifdef TARGET_X86_64
478 /* FIXME if lm capable */
479 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
480 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
481 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
482 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
483#endif
484 msr_data.info.nmsrs = n;
485
486 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
487
488}
489
490
491static int kvm_get_fpu(CPUState *env)
492{
493 struct kvm_fpu fpu;
494 int i, ret;
495
496 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
497 if (ret < 0)
498 return ret;
499
500 env->fpstt = (fpu.fsw >> 11) & 7;
501 env->fpus = fpu.fsw;
502 env->fpuc = fpu.fcw;
503 for (i = 0; i < 8; ++i)
504 env->fptags[i] = !((fpu.ftwx >> i) & 1);
505 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
506 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
507 env->mxcsr = fpu.mxcsr;
508
509 return 0;
510}
511
512static int kvm_get_sregs(CPUState *env)
513{
514 struct kvm_sregs sregs;
515 uint32_t hflags;
516 int ret;
517
518 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
519 if (ret < 0)
520 return ret;
521
522 memcpy(env->interrupt_bitmap,
523 sregs.interrupt_bitmap,
524 sizeof(sregs.interrupt_bitmap));
525
526 get_seg(&env->segs[R_CS], &sregs.cs);
527 get_seg(&env->segs[R_DS], &sregs.ds);
528 get_seg(&env->segs[R_ES], &sregs.es);
529 get_seg(&env->segs[R_FS], &sregs.fs);
530 get_seg(&env->segs[R_GS], &sregs.gs);
531 get_seg(&env->segs[R_SS], &sregs.ss);
532
533 get_seg(&env->tr, &sregs.tr);
534 get_seg(&env->ldt, &sregs.ldt);
535
536 env->idt.limit = sregs.idt.limit;
537 env->idt.base = sregs.idt.base;
538 env->gdt.limit = sregs.gdt.limit;
539 env->gdt.base = sregs.gdt.base;
540
541 env->cr[0] = sregs.cr0;
542 env->cr[2] = sregs.cr2;
543 env->cr[3] = sregs.cr3;
544 env->cr[4] = sregs.cr4;
545
546 cpu_set_apic_base(env, sregs.apic_base);
547
548 env->efer = sregs.efer;
549 //cpu_set_apic_tpr(env, sregs.cr8);
550
551#define HFLAG_COPY_MASK ~( \
552 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
553 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
554 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
555 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
556
557
558
559 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
560 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
561 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
562 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
563 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
564 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
565 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
566
567 if (env->efer & MSR_EFER_LMA) {
568 hflags |= HF_LMA_MASK;
569 }
570
571 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
572 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
573 } else {
574 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
575 (DESC_B_SHIFT - HF_CS32_SHIFT);
576 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
577 (DESC_B_SHIFT - HF_SS32_SHIFT);
578 if (!(env->cr[0] & CR0_PE_MASK) ||
579 (env->eflags & VM_MASK) ||
580 !(hflags & HF_CS32_MASK)) {
581 hflags |= HF_ADDSEG_MASK;
582 } else {
583 hflags |= ((env->segs[R_DS].base |
584 env->segs[R_ES].base |
585 env->segs[R_SS].base) != 0) <<
586 HF_ADDSEG_SHIFT;
587 }
588 }
589 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 590
591 return 0;
592}
593
594static int kvm_get_msrs(CPUState *env)
595{
596 struct {
597 struct kvm_msrs info;
598 struct kvm_msr_entry entries[100];
599 } msr_data;
600 struct kvm_msr_entry *msrs = msr_data.entries;
601 int ret, i, n;
602
603 n = 0;
604 msrs[n++].index = MSR_IA32_SYSENTER_CS;
605 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
606 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
607 if (kvm_has_msr_star(env))
608 msrs[n++].index = MSR_STAR;
609 msrs[n++].index = MSR_IA32_TSC;
610#ifdef TARGET_X86_64
611 /* FIXME lm_capable_kernel */
612 msrs[n++].index = MSR_CSTAR;
613 msrs[n++].index = MSR_KERNELGSBASE;
614 msrs[n++].index = MSR_FMASK;
615 msrs[n++].index = MSR_LSTAR;
616#endif
617 msr_data.info.nmsrs = n;
618 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
619 if (ret < 0)
620 return ret;
621
622 for (i = 0; i < ret; i++) {
623 switch (msrs[i].index) {
624 case MSR_IA32_SYSENTER_CS:
625 env->sysenter_cs = msrs[i].data;
626 break;
627 case MSR_IA32_SYSENTER_ESP:
628 env->sysenter_esp = msrs[i].data;
629 break;
630 case MSR_IA32_SYSENTER_EIP:
631 env->sysenter_eip = msrs[i].data;
632 break;
633 case MSR_STAR:
634 env->star = msrs[i].data;
635 break;
636#ifdef TARGET_X86_64
637 case MSR_CSTAR:
638 env->cstar = msrs[i].data;
639 break;
640 case MSR_KERNELGSBASE:
641 env->kernelgsbase = msrs[i].data;
642 break;
643 case MSR_FMASK:
644 env->fmask = msrs[i].data;
645 break;
646 case MSR_LSTAR:
647 env->lstar = msrs[i].data;
648 break;
649#endif
650 case MSR_IA32_TSC:
651 env->tsc = msrs[i].data;
652 break;
653 }
654 }
655
656 return 0;
657}
658
659int kvm_arch_put_registers(CPUState *env)
660{
661 int ret;
662
663 ret = kvm_getput_regs(env, 1);
664 if (ret < 0)
665 return ret;
666
667 ret = kvm_put_fpu(env);
668 if (ret < 0)
669 return ret;
670
671 ret = kvm_put_sregs(env);
672 if (ret < 0)
673 return ret;
674
675 ret = kvm_put_msrs(env);
676 if (ret < 0)
677 return ret;
678
f8d926e9
JK		 679 ret = kvm_put_mp_state(env);
680 if (ret < 0)
681 return ret;
682
683 ret = kvm_get_mp_state(env);
684 if (ret < 0)
685 return ret;
686
05330448
AL		 687 return 0;
688}
689
690int kvm_arch_get_registers(CPUState *env)
691{
692 int ret;
693
694 ret = kvm_getput_regs(env, 0);
695 if (ret < 0)
696 return ret;
697
698 ret = kvm_get_fpu(env);
699 if (ret < 0)
700 return ret;
701
702 ret = kvm_get_sregs(env);
703 if (ret < 0)
704 return ret;
705
706 ret = kvm_get_msrs(env);
707 if (ret < 0)
708 return ret;
709
710 return 0;
711}
712
713int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
714{
715 /* Try to inject an interrupt if the guest can accept it */
716 if (run->ready_for_interrupt_injection &&
717 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
718 (env->eflags & IF_MASK)) {
719 int irq;
720
721 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
722 irq = cpu_get_pic_interrupt(env);
723 if (irq >= 0) {
724 struct kvm_interrupt intr;
725 intr.irq = irq;
726 /* FIXME: errors */
727 dprintf("injected interrupt %d\n", irq);
728 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
729 }
730 }
731
732 /* If we have an interrupt but the guest is not ready to receive an
733 * interrupt, request an interrupt window exit. This will
734 * cause a return to userspace as soon as the guest is ready to
735 * receive interrupts. */
736 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
737 run->request_interrupt_window = 1;
738 else
739 run->request_interrupt_window = 0;
740
741 dprintf("setting tpr\n");
742 run->cr8 = cpu_get_apic_tpr(env);
743
744 return 0;
745}
746
747int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
748{
749 if (run->if_flag)
750 env->eflags |= IF_MASK;
751 else
752 env->eflags &= ~IF_MASK;
753
754 cpu_set_apic_tpr(env, run->cr8);
755 cpu_set_apic_base(env, run->apic_base);
756
757 return 0;
758}
759
760static int kvm_handle_halt(CPUState *env)
761{
762 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
763 (env->eflags & IF_MASK)) &&
764 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
765 env->halted = 1;
766 env->exception_index = EXCP_HLT;
767 return 0;
768 }
769
770 return 1;
771}
772
773int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
774{
775 int ret = 0;
776
777 switch (run->exit_reason) {
778 case KVM_EXIT_HLT:
779 dprintf("handle_hlt\n");
780 ret = kvm_handle_halt(env);
781 break;
782 }
783
784 return ret;
785}
e22a25c9
AL		 786
787#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 788int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
789{
64bf3f4e
AL		 790 const static uint8_t int3 = 0xcc;
791
e22a25c9 792 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 793 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 794 return -EINVAL;
795 return 0;
796}
797
798int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
799{
800 uint8_t int3;
801
802 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 803 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 804 return -EINVAL;
805 return 0;
806}
807
808static struct {
809 target_ulong addr;
810 int len;
811 int type;
812} hw_breakpoint[4];
813
814static int nb_hw_breakpoint;
815
816static int find_hw_breakpoint(target_ulong addr, int len, int type)
817{
818 int n;
819
820 for (n = 0; n < nb_hw_breakpoint; n++)
821 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
822 (hw_breakpoint[n].len == len || len == -1))
823 return n;
824 return -1;
825}
826
827int kvm_arch_insert_hw_breakpoint(target_ulong addr,
828 target_ulong len, int type)
829{
830 switch (type) {
831 case GDB_BREAKPOINT_HW:
832 len = 1;
833 break;
834 case GDB_WATCHPOINT_WRITE:
835 case GDB_WATCHPOINT_ACCESS:
836 switch (len) {
837 case 1:
838 break;
839 case 2:
840 case 4:
841 case 8:
842 if (addr & (len - 1))
843 return -EINVAL;
844 break;
845 default:
846 return -EINVAL;
847 }
848 break;
849 default:
850 return -ENOSYS;
851 }
852
853 if (nb_hw_breakpoint == 4)
854 return -ENOBUFS;
855
856 if (find_hw_breakpoint(addr, len, type) >= 0)
857 return -EEXIST;
858
859 hw_breakpoint[nb_hw_breakpoint].addr = addr;
860 hw_breakpoint[nb_hw_breakpoint].len = len;
861 hw_breakpoint[nb_hw_breakpoint].type = type;
862 nb_hw_breakpoint++;
863
864 return 0;
865}
866
867int kvm_arch_remove_hw_breakpoint(target_ulong addr,
868 target_ulong len, int type)
869{
870 int n;
871
872 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
873 if (n < 0)
874 return -ENOENT;
875
876 nb_hw_breakpoint--;
877 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
878
879 return 0;
880}
881
882void kvm_arch_remove_all_hw_breakpoints(void)
883{
884 nb_hw_breakpoint = 0;
885}
886
887static CPUWatchpoint hw_watchpoint;
888
889int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
890{
891 int handle = 0;
892 int n;
893
894 if (arch_info->exception == 1) {
895 if (arch_info->dr6 & (1 << 14)) {
896 if (cpu_single_env->singlestep_enabled)
897 handle = 1;
898 } else {
899 for (n = 0; n < 4; n++)
900 if (arch_info->dr6 & (1 << n))
901 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
902 case 0x0:
903 handle = 1;
904 break;
905 case 0x1:
906 handle = 1;
907 cpu_single_env->watchpoint_hit = &hw_watchpoint;
908 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
909 hw_watchpoint.flags = BP_MEM_WRITE;
910 break;
911 case 0x3:
912 handle = 1;
913 cpu_single_env->watchpoint_hit = &hw_watchpoint;
914 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
915 hw_watchpoint.flags = BP_MEM_ACCESS;
916 break;
917 }
918 }
919 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
920 handle = 1;
921
922 if (!handle)
923 kvm_update_guest_debug(cpu_single_env,
924 (arch_info->exception == 1) ?
925 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
926
927 return handle;
928}
929
930void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
931{
932 const uint8_t type_code[] = {
933 [GDB_BREAKPOINT_HW] = 0x0,
934 [GDB_WATCHPOINT_WRITE] = 0x1,
935 [GDB_WATCHPOINT_ACCESS] = 0x3
936 };
937 const uint8_t len_code[] = {
938 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
939 };
940 int n;
941
942 if (kvm_sw_breakpoints_active(env))
943 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
944
945 if (nb_hw_breakpoint > 0) {
946 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
947 dbg->arch.debugreg[7] = 0x0600;
948 for (n = 0; n < nb_hw_breakpoint; n++) {
949 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
950 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
951 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
952 (len_code[hw_breakpoint[n].len] << (18 + n*4));
953 }
954 }
955}
956#endif /* KVM_CAP_SET_GUEST_DEBUG */
Qemu copy for testing