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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
1d31f66b | 26 | #include "kvm_i386.h" |
05330448 | 27 | #include "cpu.h" |
e22a25c9 | 28 | #include "gdbstub.h" |
0e607a80 | 29 | #include "host-utils.h" |
4c5b10b7 | 30 | #include "hw/pc.h" |
408392b3 | 31 | #include "hw/apic.h" |
35bed8ee | 32 | #include "ioport.h" |
eab70139 | 33 | #include "hyperv.h" |
05330448 AL |
34 | |
35 | //#define DEBUG_KVM | |
36 | ||
37 | #ifdef DEBUG_KVM | |
8c0d577e | 38 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
39 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
40 | #else | |
8c0d577e | 41 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
42 | do { } while (0) |
43 | #endif | |
44 | ||
1a03675d GC |
45 | #define MSR_KVM_WALL_CLOCK 0x11 |
46 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
47 | ||
c0532a76 MT |
48 | #ifndef BUS_MCEERR_AR |
49 | #define BUS_MCEERR_AR 4 | |
50 | #endif | |
51 | #ifndef BUS_MCEERR_AO | |
52 | #define BUS_MCEERR_AO 5 | |
53 | #endif | |
54 | ||
94a8d39a JK |
55 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
56 | KVM_CAP_INFO(SET_TSS_ADDR), | |
57 | KVM_CAP_INFO(EXT_CPUID), | |
58 | KVM_CAP_INFO(MP_STATE), | |
59 | KVM_CAP_LAST_INFO | |
60 | }; | |
25d2e361 | 61 | |
c3a3a7d3 JK |
62 | static bool has_msr_star; |
63 | static bool has_msr_hsave_pa; | |
aa82ba54 | 64 | static bool has_msr_tsc_deadline; |
c5999bfc | 65 | static bool has_msr_async_pf_en; |
21e87c46 | 66 | static bool has_msr_misc_enable; |
25d2e361 | 67 | static int lm_capable_kernel; |
b827df58 | 68 | |
1d31f66b PM |
69 | bool kvm_allows_irq0_override(void) |
70 | { | |
71 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
72 | } | |
73 | ||
b827df58 AK |
74 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
75 | { | |
76 | struct kvm_cpuid2 *cpuid; | |
77 | int r, size; | |
78 | ||
79 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
7267c094 | 80 | cpuid = (struct kvm_cpuid2 *)g_malloc0(size); |
b827df58 AK |
81 | cpuid->nent = max; |
82 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
83 | if (r == 0 && cpuid->nent >= max) { |
84 | r = -E2BIG; | |
85 | } | |
b827df58 AK |
86 | if (r < 0) { |
87 | if (r == -E2BIG) { | |
7267c094 | 88 | g_free(cpuid); |
b827df58 AK |
89 | return NULL; |
90 | } else { | |
91 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
92 | strerror(-r)); | |
93 | exit(1); | |
94 | } | |
95 | } | |
96 | return cpuid; | |
97 | } | |
98 | ||
0c31b744 GC |
99 | struct kvm_para_features { |
100 | int cap; | |
101 | int feature; | |
102 | } para_features[] = { | |
103 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
104 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
105 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 106 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
107 | { -1, -1 } |
108 | }; | |
109 | ||
ba9bc59e | 110 | static int get_para_features(KVMState *s) |
0c31b744 GC |
111 | { |
112 | int i, features = 0; | |
113 | ||
114 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
ba9bc59e | 115 | if (kvm_check_extension(s, para_features[i].cap)) { |
0c31b744 GC |
116 | features |= (1 << para_features[i].feature); |
117 | } | |
118 | } | |
119 | ||
120 | return features; | |
121 | } | |
0c31b744 GC |
122 | |
123 | ||
ba9bc59e | 124 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 125 | uint32_t index, int reg) |
b827df58 AK |
126 | { |
127 | struct kvm_cpuid2 *cpuid; | |
128 | int i, max; | |
129 | uint32_t ret = 0; | |
130 | uint32_t cpuid_1_edx; | |
0c31b744 | 131 | int has_kvm_features = 0; |
b827df58 | 132 | |
b827df58 | 133 | max = 1; |
ba9bc59e | 134 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { |
b827df58 AK |
135 | max *= 2; |
136 | } | |
137 | ||
138 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
139 | if (cpuid->entries[i].function == function && |
140 | cpuid->entries[i].index == index) { | |
0c31b744 GC |
141 | if (cpuid->entries[i].function == KVM_CPUID_FEATURES) { |
142 | has_kvm_features = 1; | |
143 | } | |
b827df58 AK |
144 | switch (reg) { |
145 | case R_EAX: | |
146 | ret = cpuid->entries[i].eax; | |
147 | break; | |
148 | case R_EBX: | |
149 | ret = cpuid->entries[i].ebx; | |
150 | break; | |
151 | case R_ECX: | |
152 | ret = cpuid->entries[i].ecx; | |
153 | break; | |
154 | case R_EDX: | |
155 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
156 | switch (function) { |
157 | case 1: | |
158 | /* KVM before 2.6.30 misreports the following features */ | |
159 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
160 | break; | |
161 | case 0x80000001: | |
b827df58 AK |
162 | /* On Intel, kvm returns cpuid according to the Intel spec, |
163 | * so add missing bits according to the AMD spec: | |
164 | */ | |
ba9bc59e | 165 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); |
c1667e40 | 166 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 167 | break; |
b827df58 AK |
168 | } |
169 | break; | |
170 | } | |
171 | } | |
172 | } | |
173 | ||
7267c094 | 174 | g_free(cpuid); |
b827df58 | 175 | |
0c31b744 GC |
176 | /* fallback for older kernels */ |
177 | if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) { | |
ba9bc59e | 178 | ret = get_para_features(s); |
b9bec74b | 179 | } |
0c31b744 GC |
180 | |
181 | return ret; | |
bb0300dc | 182 | } |
bb0300dc | 183 | |
3c85e74f HY |
184 | typedef struct HWPoisonPage { |
185 | ram_addr_t ram_addr; | |
186 | QLIST_ENTRY(HWPoisonPage) list; | |
187 | } HWPoisonPage; | |
188 | ||
189 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
190 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
191 | ||
192 | static void kvm_unpoison_all(void *param) | |
193 | { | |
194 | HWPoisonPage *page, *next_page; | |
195 | ||
196 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
197 | QLIST_REMOVE(page, list); | |
198 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
7267c094 | 199 | g_free(page); |
3c85e74f HY |
200 | } |
201 | } | |
202 | ||
3c85e74f HY |
203 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
204 | { | |
205 | HWPoisonPage *page; | |
206 | ||
207 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
208 | if (page->ram_addr == ram_addr) { | |
209 | return; | |
210 | } | |
211 | } | |
7267c094 | 212 | page = g_malloc(sizeof(HWPoisonPage)); |
3c85e74f HY |
213 | page->ram_addr = ram_addr; |
214 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
215 | } | |
216 | ||
e7701825 MT |
217 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
218 | int *max_banks) | |
219 | { | |
220 | int r; | |
221 | ||
14a09518 | 222 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
223 | if (r > 0) { |
224 | *max_banks = r; | |
225 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
226 | } | |
227 | return -ENOSYS; | |
228 | } | |
229 | ||
317ac620 | 230 | static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, int code) |
e7701825 | 231 | { |
c34d440a JK |
232 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
233 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
234 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 235 | |
c34d440a JK |
236 | if (code == BUS_MCEERR_AR) { |
237 | status |= MCI_STATUS_AR | 0x134; | |
238 | mcg_status |= MCG_STATUS_EIPV; | |
239 | } else { | |
240 | status |= 0xc0; | |
241 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 242 | } |
c34d440a JK |
243 | cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, |
244 | (MCM_ADDR_PHYS << 6) | 0xc, | |
245 | cpu_x86_support_mca_broadcast(env) ? | |
246 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 247 | } |
419fb20a JK |
248 | |
249 | static void hardware_memory_error(void) | |
250 | { | |
251 | fprintf(stderr, "Hardware memory error!\n"); | |
252 | exit(1); | |
253 | } | |
254 | ||
317ac620 | 255 | int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr) |
419fb20a | 256 | { |
419fb20a JK |
257 | ram_addr_t ram_addr; |
258 | target_phys_addr_t paddr; | |
259 | ||
260 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a JK |
261 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
262 | if (qemu_ram_addr_from_host(addr, &ram_addr) || | |
9f213ed9 | 263 | !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) { |
419fb20a JK |
264 | fprintf(stderr, "Hardware memory error for memory used by " |
265 | "QEMU itself instead of guest system!\n"); | |
266 | /* Hope we are lucky for AO MCE */ | |
267 | if (code == BUS_MCEERR_AO) { | |
268 | return 0; | |
269 | } else { | |
270 | hardware_memory_error(); | |
271 | } | |
272 | } | |
3c85e74f | 273 | kvm_hwpoison_page_add(ram_addr); |
c34d440a | 274 | kvm_mce_inject(env, paddr, code); |
e56ff191 | 275 | } else { |
419fb20a JK |
276 | if (code == BUS_MCEERR_AO) { |
277 | return 0; | |
278 | } else if (code == BUS_MCEERR_AR) { | |
279 | hardware_memory_error(); | |
280 | } else { | |
281 | return 1; | |
282 | } | |
283 | } | |
284 | return 0; | |
285 | } | |
286 | ||
287 | int kvm_arch_on_sigbus(int code, void *addr) | |
288 | { | |
419fb20a | 289 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { |
419fb20a JK |
290 | ram_addr_t ram_addr; |
291 | target_phys_addr_t paddr; | |
292 | ||
293 | /* Hope we are lucky for AO MCE */ | |
c34d440a | 294 | if (qemu_ram_addr_from_host(addr, &ram_addr) || |
9f213ed9 AK |
295 | !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr, |
296 | &paddr)) { | |
419fb20a JK |
297 | fprintf(stderr, "Hardware memory error for memory used by " |
298 | "QEMU itself instead of guest system!: %p\n", addr); | |
299 | return 0; | |
300 | } | |
3c85e74f | 301 | kvm_hwpoison_page_add(ram_addr); |
c34d440a | 302 | kvm_mce_inject(first_cpu, paddr, code); |
e56ff191 | 303 | } else { |
419fb20a JK |
304 | if (code == BUS_MCEERR_AO) { |
305 | return 0; | |
306 | } else if (code == BUS_MCEERR_AR) { | |
307 | hardware_memory_error(); | |
308 | } else { | |
309 | return 1; | |
310 | } | |
311 | } | |
312 | return 0; | |
313 | } | |
e7701825 | 314 | |
317ac620 | 315 | static int kvm_inject_mce_oldstyle(CPUX86State *env) |
ab443475 | 316 | { |
ab443475 JK |
317 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
318 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
319 | struct kvm_x86_mce mce; | |
320 | ||
321 | env->exception_injected = -1; | |
322 | ||
323 | /* | |
324 | * There must be at least one bank in use if an MCE is pending. | |
325 | * Find it and use its values for the event injection. | |
326 | */ | |
327 | for (bank = 0; bank < bank_num; bank++) { | |
328 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
329 | break; | |
330 | } | |
331 | } | |
332 | assert(bank < bank_num); | |
333 | ||
334 | mce.bank = bank; | |
335 | mce.status = env->mce_banks[bank * 4 + 1]; | |
336 | mce.mcg_status = env->mcg_status; | |
337 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
338 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
339 | ||
340 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce); | |
341 | } | |
ab443475 JK |
342 | return 0; |
343 | } | |
344 | ||
1dfb4dd9 | 345 | static void cpu_update_state(void *opaque, int running, RunState state) |
b8cc45d6 | 346 | { |
317ac620 | 347 | CPUX86State *env = opaque; |
b8cc45d6 GC |
348 | |
349 | if (running) { | |
350 | env->tsc_valid = false; | |
351 | } | |
352 | } | |
353 | ||
317ac620 | 354 | int kvm_arch_init_vcpu(CPUX86State *env) |
05330448 AL |
355 | { |
356 | struct { | |
486bd5a2 AL |
357 | struct kvm_cpuid2 cpuid; |
358 | struct kvm_cpuid_entry2 entries[100]; | |
541dc0d4 | 359 | } QEMU_PACKED cpuid_data; |
ba9bc59e | 360 | KVMState *s = env->kvm_state; |
486bd5a2 | 361 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 362 | uint32_t unused; |
bb0300dc | 363 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 364 | uint32_t signature[3]; |
e7429073 | 365 | int r; |
05330448 | 366 | |
ba9bc59e | 367 | env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); |
6c0d7ee8 AP |
368 | |
369 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
a75b3e0f | 370 | j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER; |
ba9bc59e | 371 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); |
6c0d7ee8 | 372 | env->cpuid_ext_features |= i; |
a75b3e0f LJ |
373 | if (j && kvm_irqchip_in_kernel() && |
374 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
375 | env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
376 | } | |
6c0d7ee8 | 377 | |
ba9bc59e | 378 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, |
c958a8bd | 379 | 0, R_EDX); |
ba9bc59e | 380 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, |
c958a8bd | 381 | 0, R_ECX); |
ba9bc59e | 382 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, |
296acb64 JR |
383 | 0, R_EDX); |
384 | ||
05330448 AL |
385 | cpuid_i = 0; |
386 | ||
bb0300dc | 387 | /* Paravirtualization CPUIDs */ |
bb0300dc GN |
388 | c = &cpuid_data.entries[cpuid_i++]; |
389 | memset(c, 0, sizeof(*c)); | |
390 | c->function = KVM_CPUID_SIGNATURE; | |
eab70139 VR |
391 | if (!hyperv_enabled()) { |
392 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
393 | c->eax = 0; | |
394 | } else { | |
395 | memcpy(signature, "Microsoft Hv", 12); | |
396 | c->eax = HYPERV_CPUID_MIN; | |
397 | } | |
bb0300dc GN |
398 | c->ebx = signature[0]; |
399 | c->ecx = signature[1]; | |
400 | c->edx = signature[2]; | |
401 | ||
402 | c = &cpuid_data.entries[cpuid_i++]; | |
403 | memset(c, 0, sizeof(*c)); | |
404 | c->function = KVM_CPUID_FEATURES; | |
ba9bc59e JK |
405 | c->eax = env->cpuid_kvm_features & |
406 | kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); | |
0c31b744 | 407 | |
eab70139 VR |
408 | if (hyperv_enabled()) { |
409 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); | |
410 | c->eax = signature[0]; | |
411 | ||
412 | c = &cpuid_data.entries[cpuid_i++]; | |
413 | memset(c, 0, sizeof(*c)); | |
414 | c->function = HYPERV_CPUID_VERSION; | |
415 | c->eax = 0x00001bbc; | |
416 | c->ebx = 0x00060001; | |
417 | ||
418 | c = &cpuid_data.entries[cpuid_i++]; | |
419 | memset(c, 0, sizeof(*c)); | |
420 | c->function = HYPERV_CPUID_FEATURES; | |
421 | if (hyperv_relaxed_timing_enabled()) { | |
422 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
423 | } | |
424 | if (hyperv_vapic_recommended()) { | |
425 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
426 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
427 | } | |
428 | ||
429 | c = &cpuid_data.entries[cpuid_i++]; | |
430 | memset(c, 0, sizeof(*c)); | |
431 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; | |
432 | if (hyperv_relaxed_timing_enabled()) { | |
433 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; | |
434 | } | |
435 | if (hyperv_vapic_recommended()) { | |
436 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; | |
437 | } | |
438 | c->ebx = hyperv_get_spinlock_retries(); | |
439 | ||
440 | c = &cpuid_data.entries[cpuid_i++]; | |
441 | memset(c, 0, sizeof(*c)); | |
442 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; | |
443 | c->eax = 0x40; | |
444 | c->ebx = 0x40; | |
445 | ||
446 | c = &cpuid_data.entries[cpuid_i++]; | |
447 | memset(c, 0, sizeof(*c)); | |
448 | c->function = KVM_CPUID_SIGNATURE_NEXT; | |
449 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
450 | c->eax = 0; | |
451 | c->ebx = signature[0]; | |
452 | c->ecx = signature[1]; | |
453 | c->edx = signature[2]; | |
454 | } | |
455 | ||
0c31b744 | 456 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 457 | |
a33609ca | 458 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
459 | |
460 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 461 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
462 | |
463 | switch (i) { | |
a36b1029 AL |
464 | case 2: { |
465 | /* Keep reading function 2 till all the input is received */ | |
466 | int times; | |
467 | ||
a36b1029 | 468 | c->function = i; |
a33609ca AL |
469 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
470 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
471 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
472 | times = c->eax & 0xff; | |
a36b1029 AL |
473 | |
474 | for (j = 1; j < times; ++j) { | |
a33609ca | 475 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 476 | c->function = i; |
a33609ca AL |
477 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
478 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
479 | } |
480 | break; | |
481 | } | |
486bd5a2 AL |
482 | case 4: |
483 | case 0xb: | |
484 | case 0xd: | |
485 | for (j = 0; ; j++) { | |
31e8c696 AP |
486 | if (i == 0xd && j == 64) { |
487 | break; | |
488 | } | |
486bd5a2 AL |
489 | c->function = i; |
490 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
491 | c->index = j; | |
a33609ca | 492 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 493 | |
b9bec74b | 494 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 495 | break; |
b9bec74b JK |
496 | } |
497 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 498 | break; |
b9bec74b JK |
499 | } |
500 | if (i == 0xd && c->eax == 0) { | |
31e8c696 | 501 | continue; |
b9bec74b | 502 | } |
a33609ca | 503 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
504 | } |
505 | break; | |
506 | default: | |
486bd5a2 | 507 | c->function = i; |
a33609ca AL |
508 | c->flags = 0; |
509 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
510 | break; |
511 | } | |
05330448 | 512 | } |
a33609ca | 513 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
514 | |
515 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 516 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 517 | |
05330448 | 518 | c->function = i; |
a33609ca AL |
519 | c->flags = 0; |
520 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
521 | } |
522 | ||
b3baa152 | 523 | /* Call Centaur's CPUID instructions they are supported. */ |
524 | if (env->cpuid_xlevel2 > 0) { | |
525 | env->cpuid_ext4_features &= | |
ba9bc59e | 526 | kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); |
b3baa152 | 527 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
528 | ||
529 | for (i = 0xC0000000; i <= limit; i++) { | |
530 | c = &cpuid_data.entries[cpuid_i++]; | |
531 | ||
532 | c->function = i; | |
533 | c->flags = 0; | |
534 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
535 | } | |
536 | } | |
537 | ||
05330448 AL |
538 | cpuid_data.cpuid.nent = cpuid_i; |
539 | ||
e7701825 MT |
540 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
541 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
542 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
543 | uint64_t mcg_cap; | |
544 | int banks; | |
32a42024 | 545 | int ret; |
e7701825 | 546 | |
75d49497 JK |
547 | ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks); |
548 | if (ret < 0) { | |
549 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
550 | return ret; | |
e7701825 | 551 | } |
75d49497 JK |
552 | |
553 | if (banks > MCE_BANKS_DEF) { | |
554 | banks = MCE_BANKS_DEF; | |
555 | } | |
556 | mcg_cap &= MCE_CAP_DEF; | |
557 | mcg_cap |= banks; | |
558 | ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap); | |
559 | if (ret < 0) { | |
560 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
561 | return ret; | |
562 | } | |
563 | ||
564 | env->mcg_cap = mcg_cap; | |
e7701825 | 565 | } |
e7701825 | 566 | |
b8cc45d6 GC |
567 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
568 | ||
7e680753 | 569 | cpuid_data.cpuid.padding = 0; |
e7429073 | 570 | r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
fdc9c41a JK |
571 | if (r) { |
572 | return r; | |
573 | } | |
e7429073 | 574 | |
e7429073 JR |
575 | r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL); |
576 | if (r && env->tsc_khz) { | |
577 | r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz); | |
578 | if (r < 0) { | |
579 | fprintf(stderr, "KVM_SET_TSC_KHZ failed\n"); | |
580 | return r; | |
581 | } | |
582 | } | |
e7429073 | 583 | |
fabacc0f JK |
584 | if (kvm_has_xsave()) { |
585 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
586 | } | |
587 | ||
e7429073 | 588 | return 0; |
05330448 AL |
589 | } |
590 | ||
317ac620 | 591 | void kvm_arch_reset_vcpu(CPUX86State *env) |
caa5af0f | 592 | { |
dd673288 IM |
593 | X86CPU *cpu = x86_env_get_cpu(env); |
594 | ||
e73223a5 | 595 | env->exception_injected = -1; |
0e607a80 | 596 | env->interrupt_injected = -1; |
1a5e9d2f | 597 | env->xcr0 = 1; |
ddced198 | 598 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 599 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
600 | KVM_MP_STATE_UNINITIALIZED; |
601 | } else { | |
602 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
603 | } | |
caa5af0f JK |
604 | } |
605 | ||
c3a3a7d3 | 606 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 607 | { |
75b10c43 | 608 | static int kvm_supported_msrs; |
c3a3a7d3 | 609 | int ret = 0; |
05330448 AL |
610 | |
611 | /* first time */ | |
75b10c43 | 612 | if (kvm_supported_msrs == 0) { |
05330448 AL |
613 | struct kvm_msr_list msr_list, *kvm_msr_list; |
614 | ||
75b10c43 | 615 | kvm_supported_msrs = -1; |
05330448 AL |
616 | |
617 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
618 | * save/restore */ | |
4c9f7372 | 619 | msr_list.nmsrs = 0; |
c3a3a7d3 | 620 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 621 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 622 | return ret; |
6fb6d245 | 623 | } |
d9db889f JK |
624 | /* Old kernel modules had a bug and could write beyond the provided |
625 | memory. Allocate at least a safe amount of 1K. */ | |
7267c094 | 626 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
d9db889f JK |
627 | msr_list.nmsrs * |
628 | sizeof(msr_list.indices[0]))); | |
05330448 | 629 | |
55308450 | 630 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 631 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
632 | if (ret >= 0) { |
633 | int i; | |
634 | ||
635 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
636 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 637 | has_msr_star = true; |
75b10c43 MT |
638 | continue; |
639 | } | |
640 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 641 | has_msr_hsave_pa = true; |
75b10c43 | 642 | continue; |
05330448 | 643 | } |
aa82ba54 LJ |
644 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { |
645 | has_msr_tsc_deadline = true; | |
646 | continue; | |
647 | } | |
21e87c46 AK |
648 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { |
649 | has_msr_misc_enable = true; | |
650 | continue; | |
651 | } | |
05330448 AL |
652 | } |
653 | } | |
654 | ||
7267c094 | 655 | g_free(kvm_msr_list); |
05330448 AL |
656 | } |
657 | ||
c3a3a7d3 | 658 | return ret; |
05330448 AL |
659 | } |
660 | ||
cad1e282 | 661 | int kvm_arch_init(KVMState *s) |
20420430 | 662 | { |
39d6960a | 663 | QemuOptsList *list = qemu_find_opts("machine"); |
11076198 | 664 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 665 | uint64_t shadow_mem; |
20420430 | 666 | int ret; |
25d2e361 | 667 | struct utsname utsname; |
20420430 | 668 | |
c3a3a7d3 | 669 | ret = kvm_get_supported_msrs(s); |
20420430 | 670 | if (ret < 0) { |
20420430 SY |
671 | return ret; |
672 | } | |
25d2e361 MT |
673 | |
674 | uname(&utsname); | |
675 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
676 | ||
4c5b10b7 | 677 | /* |
11076198 JK |
678 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
679 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
680 | * Since these must be part of guest physical memory, we need to allocate | |
681 | * them, both by setting their start addresses in the kernel and by | |
682 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
683 | * | |
684 | * Older KVM versions may not support setting the identity map base. In | |
685 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
686 | * size. | |
4c5b10b7 | 687 | */ |
11076198 JK |
688 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
689 | /* Allows up to 16M BIOSes. */ | |
690 | identity_base = 0xfeffc000; | |
691 | ||
692 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
693 | if (ret < 0) { | |
694 | return ret; | |
695 | } | |
4c5b10b7 | 696 | } |
e56ff191 | 697 | |
11076198 JK |
698 | /* Set TSS base one page after EPT identity map. */ |
699 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
700 | if (ret < 0) { |
701 | return ret; | |
702 | } | |
703 | ||
11076198 JK |
704 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
705 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 706 | if (ret < 0) { |
11076198 | 707 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
708 | return ret; |
709 | } | |
3c85e74f | 710 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 711 | |
39d6960a JK |
712 | if (!QTAILQ_EMPTY(&list->head)) { |
713 | shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head), | |
714 | "kvm_shadow_mem", -1); | |
715 | if (shadow_mem != -1) { | |
716 | shadow_mem /= 4096; | |
717 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
718 | if (ret < 0) { | |
719 | return ret; | |
720 | } | |
721 | } | |
722 | } | |
11076198 | 723 | return 0; |
05330448 | 724 | } |
b9bec74b | 725 | |
05330448 AL |
726 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
727 | { | |
728 | lhs->selector = rhs->selector; | |
729 | lhs->base = rhs->base; | |
730 | lhs->limit = rhs->limit; | |
731 | lhs->type = 3; | |
732 | lhs->present = 1; | |
733 | lhs->dpl = 3; | |
734 | lhs->db = 0; | |
735 | lhs->s = 1; | |
736 | lhs->l = 0; | |
737 | lhs->g = 0; | |
738 | lhs->avl = 0; | |
739 | lhs->unusable = 0; | |
740 | } | |
741 | ||
742 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
743 | { | |
744 | unsigned flags = rhs->flags; | |
745 | lhs->selector = rhs->selector; | |
746 | lhs->base = rhs->base; | |
747 | lhs->limit = rhs->limit; | |
748 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
749 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 750 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
751 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
752 | lhs->s = (flags & DESC_S_MASK) != 0; | |
753 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
754 | lhs->g = (flags & DESC_G_MASK) != 0; | |
755 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
756 | lhs->unusable = 0; | |
7e680753 | 757 | lhs->padding = 0; |
05330448 AL |
758 | } |
759 | ||
760 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
761 | { | |
762 | lhs->selector = rhs->selector; | |
763 | lhs->base = rhs->base; | |
764 | lhs->limit = rhs->limit; | |
b9bec74b JK |
765 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
766 | (rhs->present * DESC_P_MASK) | | |
767 | (rhs->dpl << DESC_DPL_SHIFT) | | |
768 | (rhs->db << DESC_B_SHIFT) | | |
769 | (rhs->s * DESC_S_MASK) | | |
770 | (rhs->l << DESC_L_SHIFT) | | |
771 | (rhs->g * DESC_G_MASK) | | |
772 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
773 | } |
774 | ||
775 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
776 | { | |
b9bec74b | 777 | if (set) { |
05330448 | 778 | *kvm_reg = *qemu_reg; |
b9bec74b | 779 | } else { |
05330448 | 780 | *qemu_reg = *kvm_reg; |
b9bec74b | 781 | } |
05330448 AL |
782 | } |
783 | ||
317ac620 | 784 | static int kvm_getput_regs(CPUX86State *env, int set) |
05330448 AL |
785 | { |
786 | struct kvm_regs regs; | |
787 | int ret = 0; | |
788 | ||
789 | if (!set) { | |
790 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
b9bec74b | 791 | if (ret < 0) { |
05330448 | 792 | return ret; |
b9bec74b | 793 | } |
05330448 AL |
794 | } |
795 | ||
796 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
797 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
798 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
799 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
800 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
801 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
802 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
803 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
804 | #ifdef TARGET_X86_64 | |
805 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
806 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
807 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
808 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
809 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
810 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
811 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
812 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
813 | #endif | |
814 | ||
815 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
816 | kvm_getput_reg(®s.rip, &env->eip, set); | |
817 | ||
b9bec74b | 818 | if (set) { |
05330448 | 819 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
b9bec74b | 820 | } |
05330448 AL |
821 | |
822 | return ret; | |
823 | } | |
824 | ||
317ac620 | 825 | static int kvm_put_fpu(CPUX86State *env) |
05330448 AL |
826 | { |
827 | struct kvm_fpu fpu; | |
828 | int i; | |
829 | ||
830 | memset(&fpu, 0, sizeof fpu); | |
831 | fpu.fsw = env->fpus & ~(7 << 11); | |
832 | fpu.fsw |= (env->fpstt & 7) << 11; | |
833 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
834 | fpu.last_opcode = env->fpop; |
835 | fpu.last_ip = env->fpip; | |
836 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
837 | for (i = 0; i < 8; ++i) { |
838 | fpu.ftwx |= (!env->fptags[i]) << i; | |
839 | } | |
05330448 AL |
840 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
841 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
842 | fpu.mxcsr = env->mxcsr; | |
843 | ||
844 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
845 | } | |
846 | ||
6b42494b JK |
847 | #define XSAVE_FCW_FSW 0 |
848 | #define XSAVE_FTW_FOP 1 | |
f1665b21 SY |
849 | #define XSAVE_CWD_RIP 2 |
850 | #define XSAVE_CWD_RDP 4 | |
851 | #define XSAVE_MXCSR 6 | |
852 | #define XSAVE_ST_SPACE 8 | |
853 | #define XSAVE_XMM_SPACE 40 | |
854 | #define XSAVE_XSTATE_BV 128 | |
855 | #define XSAVE_YMMH_SPACE 144 | |
f1665b21 | 856 | |
317ac620 | 857 | static int kvm_put_xsave(CPUX86State *env) |
f1665b21 | 858 | { |
fabacc0f | 859 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
42cc8fa6 | 860 | uint16_t cwd, swd, twd; |
fabacc0f | 861 | int i, r; |
f1665b21 | 862 | |
b9bec74b | 863 | if (!kvm_has_xsave()) { |
f1665b21 | 864 | return kvm_put_fpu(env); |
b9bec74b | 865 | } |
f1665b21 | 866 | |
f1665b21 | 867 | memset(xsave, 0, sizeof(struct kvm_xsave)); |
6115c0a8 | 868 | twd = 0; |
f1665b21 SY |
869 | swd = env->fpus & ~(7 << 11); |
870 | swd |= (env->fpstt & 7) << 11; | |
871 | cwd = env->fpuc; | |
b9bec74b | 872 | for (i = 0; i < 8; ++i) { |
f1665b21 | 873 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 874 | } |
6b42494b JK |
875 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; |
876 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
42cc8fa6 JK |
877 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); |
878 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
879 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
880 | sizeof env->fpregs); | |
881 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
882 | sizeof env->xmm_regs); | |
883 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
884 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
885 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
886 | sizeof env->ymmh_regs); | |
0f53994f | 887 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
0f53994f | 888 | return r; |
f1665b21 SY |
889 | } |
890 | ||
317ac620 | 891 | static int kvm_put_xcrs(CPUX86State *env) |
f1665b21 | 892 | { |
f1665b21 SY |
893 | struct kvm_xcrs xcrs; |
894 | ||
b9bec74b | 895 | if (!kvm_has_xcrs()) { |
f1665b21 | 896 | return 0; |
b9bec74b | 897 | } |
f1665b21 SY |
898 | |
899 | xcrs.nr_xcrs = 1; | |
900 | xcrs.flags = 0; | |
901 | xcrs.xcrs[0].xcr = 0; | |
902 | xcrs.xcrs[0].value = env->xcr0; | |
903 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
f1665b21 SY |
904 | } |
905 | ||
317ac620 | 906 | static int kvm_put_sregs(CPUX86State *env) |
05330448 AL |
907 | { |
908 | struct kvm_sregs sregs; | |
909 | ||
0e607a80 JK |
910 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
911 | if (env->interrupt_injected >= 0) { | |
912 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
913 | (uint64_t)1 << (env->interrupt_injected % 64); | |
914 | } | |
05330448 AL |
915 | |
916 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
917 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
918 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
919 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
920 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
921 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
922 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 923 | } else { |
b9bec74b JK |
924 | set_seg(&sregs.cs, &env->segs[R_CS]); |
925 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
926 | set_seg(&sregs.es, &env->segs[R_ES]); | |
927 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
928 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
929 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
930 | } |
931 | ||
932 | set_seg(&sregs.tr, &env->tr); | |
933 | set_seg(&sregs.ldt, &env->ldt); | |
934 | ||
935 | sregs.idt.limit = env->idt.limit; | |
936 | sregs.idt.base = env->idt.base; | |
7e680753 | 937 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
938 | sregs.gdt.limit = env->gdt.limit; |
939 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 940 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
941 | |
942 | sregs.cr0 = env->cr[0]; | |
943 | sregs.cr2 = env->cr[2]; | |
944 | sregs.cr3 = env->cr[3]; | |
945 | sregs.cr4 = env->cr[4]; | |
946 | ||
4a942cea BS |
947 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
948 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
949 | |
950 | sregs.efer = env->efer; | |
951 | ||
952 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
953 | } | |
954 | ||
955 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
956 | uint32_t index, uint64_t value) | |
957 | { | |
958 | entry->index = index; | |
959 | entry->data = value; | |
960 | } | |
961 | ||
317ac620 | 962 | static int kvm_put_msrs(CPUX86State *env, int level) |
05330448 AL |
963 | { |
964 | struct { | |
965 | struct kvm_msrs info; | |
966 | struct kvm_msr_entry entries[100]; | |
967 | } msr_data; | |
968 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 969 | int n = 0; |
05330448 AL |
970 | |
971 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
972 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
973 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 974 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 975 | if (has_msr_star) { |
b9bec74b JK |
976 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
977 | } | |
c3a3a7d3 | 978 | if (has_msr_hsave_pa) { |
75b10c43 | 979 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 980 | } |
aa82ba54 LJ |
981 | if (has_msr_tsc_deadline) { |
982 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
983 | } | |
21e87c46 AK |
984 | if (has_msr_misc_enable) { |
985 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
986 | env->msr_ia32_misc_enable); | |
987 | } | |
05330448 | 988 | #ifdef TARGET_X86_64 |
25d2e361 MT |
989 | if (lm_capable_kernel) { |
990 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
991 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
992 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
993 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
994 | } | |
05330448 | 995 | #endif |
ea643051 | 996 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
997 | /* |
998 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
999 | * writeback. Until this is fixed, we only write the offset to SMP | |
1000 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
1001 | * huge jump-backs that would occur without any writeback at all. | |
1002 | */ | |
1003 | if (smp_cpus == 1 || env->tsc != 0) { | |
1004 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
1005 | } | |
ff5c186b JK |
1006 | } |
1007 | /* | |
1008 | * The following paravirtual MSRs have side effects on the guest or are | |
1009 | * too heavy for normal writeback. Limit them to reset or full state | |
1010 | * updates. | |
1011 | */ | |
1012 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
1013 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1014 | env->system_time_msr); | |
1015 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
1016 | if (has_msr_async_pf_en) { |
1017 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1018 | env->async_pf_en_msr); | |
1019 | } | |
eab70139 VR |
1020 | if (hyperv_hypercall_available()) { |
1021 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0); | |
1022 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0); | |
1023 | } | |
1024 | if (hyperv_vapic_recommended()) { | |
1025 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0); | |
1026 | } | |
ea643051 | 1027 | } |
57780495 | 1028 | if (env->mcg_cap) { |
d8da8574 | 1029 | int i; |
b9bec74b | 1030 | |
c34d440a JK |
1031 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1032 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1033 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1034 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
1035 | } |
1036 | } | |
1a03675d | 1037 | |
05330448 AL |
1038 | msr_data.info.nmsrs = n; |
1039 | ||
1040 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
1041 | ||
1042 | } | |
1043 | ||
1044 | ||
317ac620 | 1045 | static int kvm_get_fpu(CPUX86State *env) |
05330448 AL |
1046 | { |
1047 | struct kvm_fpu fpu; | |
1048 | int i, ret; | |
1049 | ||
1050 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
b9bec74b | 1051 | if (ret < 0) { |
05330448 | 1052 | return ret; |
b9bec74b | 1053 | } |
05330448 AL |
1054 | |
1055 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1056 | env->fpus = fpu.fsw; | |
1057 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
1058 | env->fpop = fpu.last_opcode; |
1059 | env->fpip = fpu.last_ip; | |
1060 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
1061 | for (i = 0; i < 8; ++i) { |
1062 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1063 | } | |
05330448 AL |
1064 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
1065 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
1066 | env->mxcsr = fpu.mxcsr; | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
317ac620 | 1071 | static int kvm_get_xsave(CPUX86State *env) |
f1665b21 | 1072 | { |
fabacc0f | 1073 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
f1665b21 | 1074 | int ret, i; |
42cc8fa6 | 1075 | uint16_t cwd, swd, twd; |
f1665b21 | 1076 | |
b9bec74b | 1077 | if (!kvm_has_xsave()) { |
f1665b21 | 1078 | return kvm_get_fpu(env); |
b9bec74b | 1079 | } |
f1665b21 | 1080 | |
f1665b21 | 1081 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); |
0f53994f | 1082 | if (ret < 0) { |
f1665b21 | 1083 | return ret; |
0f53994f | 1084 | } |
f1665b21 | 1085 | |
6b42494b JK |
1086 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1087 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1088 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1089 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
f1665b21 SY |
1090 | env->fpstt = (swd >> 11) & 7; |
1091 | env->fpus = swd; | |
1092 | env->fpuc = cwd; | |
b9bec74b | 1093 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1094 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1095 | } |
42cc8fa6 JK |
1096 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1097 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1098 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1099 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1100 | sizeof env->fpregs); | |
1101 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1102 | sizeof env->xmm_regs); | |
1103 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1104 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1105 | sizeof env->ymmh_regs); | |
1106 | return 0; | |
f1665b21 SY |
1107 | } |
1108 | ||
317ac620 | 1109 | static int kvm_get_xcrs(CPUX86State *env) |
f1665b21 | 1110 | { |
f1665b21 SY |
1111 | int i, ret; |
1112 | struct kvm_xcrs xcrs; | |
1113 | ||
b9bec74b | 1114 | if (!kvm_has_xcrs()) { |
f1665b21 | 1115 | return 0; |
b9bec74b | 1116 | } |
f1665b21 SY |
1117 | |
1118 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
b9bec74b | 1119 | if (ret < 0) { |
f1665b21 | 1120 | return ret; |
b9bec74b | 1121 | } |
f1665b21 | 1122 | |
b9bec74b | 1123 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
1124 | /* Only support xcr0 now */ |
1125 | if (xcrs.xcrs[0].xcr == 0) { | |
1126 | env->xcr0 = xcrs.xcrs[0].value; | |
1127 | break; | |
1128 | } | |
b9bec74b | 1129 | } |
f1665b21 | 1130 | return 0; |
f1665b21 SY |
1131 | } |
1132 | ||
317ac620 | 1133 | static int kvm_get_sregs(CPUX86State *env) |
05330448 AL |
1134 | { |
1135 | struct kvm_sregs sregs; | |
1136 | uint32_t hflags; | |
0e607a80 | 1137 | int bit, i, ret; |
05330448 AL |
1138 | |
1139 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
b9bec74b | 1140 | if (ret < 0) { |
05330448 | 1141 | return ret; |
b9bec74b | 1142 | } |
05330448 | 1143 | |
0e607a80 JK |
1144 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1145 | to find it and save its number instead (-1 for none). */ | |
1146 | env->interrupt_injected = -1; | |
1147 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1148 | if (sregs.interrupt_bitmap[i]) { | |
1149 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1150 | env->interrupt_injected = i * 64 + bit; | |
1151 | break; | |
1152 | } | |
1153 | } | |
05330448 AL |
1154 | |
1155 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1156 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1157 | get_seg(&env->segs[R_ES], &sregs.es); | |
1158 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1159 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1160 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1161 | ||
1162 | get_seg(&env->tr, &sregs.tr); | |
1163 | get_seg(&env->ldt, &sregs.ldt); | |
1164 | ||
1165 | env->idt.limit = sregs.idt.limit; | |
1166 | env->idt.base = sregs.idt.base; | |
1167 | env->gdt.limit = sregs.gdt.limit; | |
1168 | env->gdt.base = sregs.gdt.base; | |
1169 | ||
1170 | env->cr[0] = sregs.cr0; | |
1171 | env->cr[2] = sregs.cr2; | |
1172 | env->cr[3] = sregs.cr3; | |
1173 | env->cr[4] = sregs.cr4; | |
1174 | ||
05330448 | 1175 | env->efer = sregs.efer; |
cce47516 JK |
1176 | |
1177 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
05330448 | 1178 | |
b9bec74b JK |
1179 | #define HFLAG_COPY_MASK \ |
1180 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1181 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1182 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1183 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1184 | |
1185 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1186 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1187 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1188 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1189 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1190 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1191 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1192 | |
1193 | if (env->efer & MSR_EFER_LMA) { | |
1194 | hflags |= HF_LMA_MASK; | |
1195 | } | |
1196 | ||
1197 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1198 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1199 | } else { | |
1200 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1201 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1202 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1203 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1204 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1205 | !(hflags & HF_CS32_MASK)) { | |
1206 | hflags |= HF_ADDSEG_MASK; | |
1207 | } else { | |
1208 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1209 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1210 | } | |
05330448 AL |
1211 | } |
1212 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1213 | |
1214 | return 0; | |
1215 | } | |
1216 | ||
317ac620 | 1217 | static int kvm_get_msrs(CPUX86State *env) |
05330448 AL |
1218 | { |
1219 | struct { | |
1220 | struct kvm_msrs info; | |
1221 | struct kvm_msr_entry entries[100]; | |
1222 | } msr_data; | |
1223 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1224 | int ret, i, n; | |
1225 | ||
1226 | n = 0; | |
1227 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1228 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1229 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1230 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1231 | if (has_msr_star) { |
b9bec74b JK |
1232 | msrs[n++].index = MSR_STAR; |
1233 | } | |
c3a3a7d3 | 1234 | if (has_msr_hsave_pa) { |
75b10c43 | 1235 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1236 | } |
aa82ba54 LJ |
1237 | if (has_msr_tsc_deadline) { |
1238 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1239 | } | |
21e87c46 AK |
1240 | if (has_msr_misc_enable) { |
1241 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1242 | } | |
b8cc45d6 GC |
1243 | |
1244 | if (!env->tsc_valid) { | |
1245 | msrs[n++].index = MSR_IA32_TSC; | |
1354869c | 1246 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
1247 | } |
1248 | ||
05330448 | 1249 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1250 | if (lm_capable_kernel) { |
1251 | msrs[n++].index = MSR_CSTAR; | |
1252 | msrs[n++].index = MSR_KERNELGSBASE; | |
1253 | msrs[n++].index = MSR_FMASK; | |
1254 | msrs[n++].index = MSR_LSTAR; | |
1255 | } | |
05330448 | 1256 | #endif |
1a03675d GC |
1257 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1258 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1259 | if (has_msr_async_pf_en) { |
1260 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1261 | } | |
1a03675d | 1262 | |
57780495 MT |
1263 | if (env->mcg_cap) { |
1264 | msrs[n++].index = MSR_MCG_STATUS; | |
1265 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1266 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1267 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1268 | } |
57780495 | 1269 | } |
57780495 | 1270 | |
05330448 AL |
1271 | msr_data.info.nmsrs = n; |
1272 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
b9bec74b | 1273 | if (ret < 0) { |
05330448 | 1274 | return ret; |
b9bec74b | 1275 | } |
05330448 AL |
1276 | |
1277 | for (i = 0; i < ret; i++) { | |
1278 | switch (msrs[i].index) { | |
1279 | case MSR_IA32_SYSENTER_CS: | |
1280 | env->sysenter_cs = msrs[i].data; | |
1281 | break; | |
1282 | case MSR_IA32_SYSENTER_ESP: | |
1283 | env->sysenter_esp = msrs[i].data; | |
1284 | break; | |
1285 | case MSR_IA32_SYSENTER_EIP: | |
1286 | env->sysenter_eip = msrs[i].data; | |
1287 | break; | |
0c03266a JK |
1288 | case MSR_PAT: |
1289 | env->pat = msrs[i].data; | |
1290 | break; | |
05330448 AL |
1291 | case MSR_STAR: |
1292 | env->star = msrs[i].data; | |
1293 | break; | |
1294 | #ifdef TARGET_X86_64 | |
1295 | case MSR_CSTAR: | |
1296 | env->cstar = msrs[i].data; | |
1297 | break; | |
1298 | case MSR_KERNELGSBASE: | |
1299 | env->kernelgsbase = msrs[i].data; | |
1300 | break; | |
1301 | case MSR_FMASK: | |
1302 | env->fmask = msrs[i].data; | |
1303 | break; | |
1304 | case MSR_LSTAR: | |
1305 | env->lstar = msrs[i].data; | |
1306 | break; | |
1307 | #endif | |
1308 | case MSR_IA32_TSC: | |
1309 | env->tsc = msrs[i].data; | |
1310 | break; | |
aa82ba54 LJ |
1311 | case MSR_IA32_TSCDEADLINE: |
1312 | env->tsc_deadline = msrs[i].data; | |
1313 | break; | |
aa851e36 MT |
1314 | case MSR_VM_HSAVE_PA: |
1315 | env->vm_hsave = msrs[i].data; | |
1316 | break; | |
1a03675d GC |
1317 | case MSR_KVM_SYSTEM_TIME: |
1318 | env->system_time_msr = msrs[i].data; | |
1319 | break; | |
1320 | case MSR_KVM_WALL_CLOCK: | |
1321 | env->wall_clock_msr = msrs[i].data; | |
1322 | break; | |
57780495 MT |
1323 | case MSR_MCG_STATUS: |
1324 | env->mcg_status = msrs[i].data; | |
1325 | break; | |
1326 | case MSR_MCG_CTL: | |
1327 | env->mcg_ctl = msrs[i].data; | |
1328 | break; | |
21e87c46 AK |
1329 | case MSR_IA32_MISC_ENABLE: |
1330 | env->msr_ia32_misc_enable = msrs[i].data; | |
1331 | break; | |
57780495 | 1332 | default: |
57780495 MT |
1333 | if (msrs[i].index >= MSR_MC0_CTL && |
1334 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1335 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 1336 | } |
d8da8574 | 1337 | break; |
f6584ee2 GN |
1338 | case MSR_KVM_ASYNC_PF_EN: |
1339 | env->async_pf_en_msr = msrs[i].data; | |
1340 | break; | |
05330448 AL |
1341 | } |
1342 | } | |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
317ac620 | 1347 | static int kvm_put_mp_state(CPUX86State *env) |
9bdbe550 HB |
1348 | { |
1349 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1350 | ||
1351 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1352 | } | |
1353 | ||
317ac620 | 1354 | static int kvm_get_mp_state(CPUX86State *env) |
9bdbe550 HB |
1355 | { |
1356 | struct kvm_mp_state mp_state; | |
1357 | int ret; | |
1358 | ||
1359 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1360 | if (ret < 0) { | |
1361 | return ret; | |
1362 | } | |
1363 | env->mp_state = mp_state.mp_state; | |
c14750e8 JK |
1364 | if (kvm_irqchip_in_kernel()) { |
1365 | env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); | |
1366 | } | |
9bdbe550 HB |
1367 | return 0; |
1368 | } | |
1369 | ||
317ac620 | 1370 | static int kvm_get_apic(CPUX86State *env) |
680c1c6f JK |
1371 | { |
1372 | DeviceState *apic = env->apic_state; | |
1373 | struct kvm_lapic_state kapic; | |
1374 | int ret; | |
1375 | ||
3d4b2649 | 1376 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
1377 | ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic); |
1378 | if (ret < 0) { | |
1379 | return ret; | |
1380 | } | |
1381 | ||
1382 | kvm_get_apic_state(apic, &kapic); | |
1383 | } | |
1384 | return 0; | |
1385 | } | |
1386 | ||
317ac620 | 1387 | static int kvm_put_apic(CPUX86State *env) |
680c1c6f JK |
1388 | { |
1389 | DeviceState *apic = env->apic_state; | |
1390 | struct kvm_lapic_state kapic; | |
1391 | ||
3d4b2649 | 1392 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
1393 | kvm_put_apic_state(apic, &kapic); |
1394 | ||
1395 | return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic); | |
1396 | } | |
1397 | return 0; | |
1398 | } | |
1399 | ||
317ac620 | 1400 | static int kvm_put_vcpu_events(CPUX86State *env, int level) |
a0fb002c | 1401 | { |
a0fb002c JK |
1402 | struct kvm_vcpu_events events; |
1403 | ||
1404 | if (!kvm_has_vcpu_events()) { | |
1405 | return 0; | |
1406 | } | |
1407 | ||
31827373 JK |
1408 | events.exception.injected = (env->exception_injected >= 0); |
1409 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1410 | events.exception.has_error_code = env->has_error_code; |
1411 | events.exception.error_code = env->error_code; | |
7e680753 | 1412 | events.exception.pad = 0; |
a0fb002c JK |
1413 | |
1414 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1415 | events.interrupt.nr = env->interrupt_injected; | |
1416 | events.interrupt.soft = env->soft_interrupt; | |
1417 | ||
1418 | events.nmi.injected = env->nmi_injected; | |
1419 | events.nmi.pending = env->nmi_pending; | |
1420 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
7e680753 | 1421 | events.nmi.pad = 0; |
a0fb002c JK |
1422 | |
1423 | events.sipi_vector = env->sipi_vector; | |
1424 | ||
ea643051 JK |
1425 | events.flags = 0; |
1426 | if (level >= KVM_PUT_RESET_STATE) { | |
1427 | events.flags |= | |
1428 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1429 | } | |
aee028b9 | 1430 | |
a0fb002c | 1431 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
1432 | } |
1433 | ||
317ac620 | 1434 | static int kvm_get_vcpu_events(CPUX86State *env) |
a0fb002c | 1435 | { |
a0fb002c JK |
1436 | struct kvm_vcpu_events events; |
1437 | int ret; | |
1438 | ||
1439 | if (!kvm_has_vcpu_events()) { | |
1440 | return 0; | |
1441 | } | |
1442 | ||
1443 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1444 | if (ret < 0) { | |
1445 | return ret; | |
1446 | } | |
31827373 | 1447 | env->exception_injected = |
a0fb002c JK |
1448 | events.exception.injected ? events.exception.nr : -1; |
1449 | env->has_error_code = events.exception.has_error_code; | |
1450 | env->error_code = events.exception.error_code; | |
1451 | ||
1452 | env->interrupt_injected = | |
1453 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1454 | env->soft_interrupt = events.interrupt.soft; | |
1455 | ||
1456 | env->nmi_injected = events.nmi.injected; | |
1457 | env->nmi_pending = events.nmi.pending; | |
1458 | if (events.nmi.masked) { | |
1459 | env->hflags2 |= HF2_NMI_MASK; | |
1460 | } else { | |
1461 | env->hflags2 &= ~HF2_NMI_MASK; | |
1462 | } | |
1463 | ||
1464 | env->sipi_vector = events.sipi_vector; | |
a0fb002c JK |
1465 | |
1466 | return 0; | |
1467 | } | |
1468 | ||
317ac620 | 1469 | static int kvm_guest_debug_workarounds(CPUX86State *env) |
b0b1d690 JK |
1470 | { |
1471 | int ret = 0; | |
b0b1d690 JK |
1472 | unsigned long reinject_trap = 0; |
1473 | ||
1474 | if (!kvm_has_vcpu_events()) { | |
1475 | if (env->exception_injected == 1) { | |
1476 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1477 | } else if (env->exception_injected == 3) { | |
1478 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1479 | } | |
1480 | env->exception_injected = -1; | |
1481 | } | |
1482 | ||
1483 | /* | |
1484 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1485 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1486 | * by updating the debug state once again if single-stepping is on. | |
1487 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1488 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1489 | * reinject them via SET_GUEST_DEBUG. | |
1490 | */ | |
1491 | if (reinject_trap || | |
1492 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1493 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1494 | } | |
b0b1d690 JK |
1495 | return ret; |
1496 | } | |
1497 | ||
317ac620 | 1498 | static int kvm_put_debugregs(CPUX86State *env) |
ff44f1a3 | 1499 | { |
ff44f1a3 JK |
1500 | struct kvm_debugregs dbgregs; |
1501 | int i; | |
1502 | ||
1503 | if (!kvm_has_debugregs()) { | |
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | for (i = 0; i < 4; i++) { | |
1508 | dbgregs.db[i] = env->dr[i]; | |
1509 | } | |
1510 | dbgregs.dr6 = env->dr[6]; | |
1511 | dbgregs.dr7 = env->dr[7]; | |
1512 | dbgregs.flags = 0; | |
1513 | ||
1514 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
ff44f1a3 JK |
1515 | } |
1516 | ||
317ac620 | 1517 | static int kvm_get_debugregs(CPUX86State *env) |
ff44f1a3 | 1518 | { |
ff44f1a3 JK |
1519 | struct kvm_debugregs dbgregs; |
1520 | int i, ret; | |
1521 | ||
1522 | if (!kvm_has_debugregs()) { | |
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1527 | if (ret < 0) { | |
b9bec74b | 1528 | return ret; |
ff44f1a3 JK |
1529 | } |
1530 | for (i = 0; i < 4; i++) { | |
1531 | env->dr[i] = dbgregs.db[i]; | |
1532 | } | |
1533 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1534 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
1535 | |
1536 | return 0; | |
1537 | } | |
1538 | ||
317ac620 | 1539 | int kvm_arch_put_registers(CPUX86State *env, int level) |
05330448 AL |
1540 | { |
1541 | int ret; | |
1542 | ||
b7680cb6 | 1543 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1544 | |
05330448 | 1545 | ret = kvm_getput_regs(env, 1); |
b9bec74b | 1546 | if (ret < 0) { |
05330448 | 1547 | return ret; |
b9bec74b | 1548 | } |
f1665b21 | 1549 | ret = kvm_put_xsave(env); |
b9bec74b | 1550 | if (ret < 0) { |
f1665b21 | 1551 | return ret; |
b9bec74b | 1552 | } |
f1665b21 | 1553 | ret = kvm_put_xcrs(env); |
b9bec74b | 1554 | if (ret < 0) { |
05330448 | 1555 | return ret; |
b9bec74b | 1556 | } |
05330448 | 1557 | ret = kvm_put_sregs(env); |
b9bec74b | 1558 | if (ret < 0) { |
05330448 | 1559 | return ret; |
b9bec74b | 1560 | } |
ab443475 JK |
1561 | /* must be before kvm_put_msrs */ |
1562 | ret = kvm_inject_mce_oldstyle(env); | |
1563 | if (ret < 0) { | |
1564 | return ret; | |
1565 | } | |
ea643051 | 1566 | ret = kvm_put_msrs(env, level); |
b9bec74b | 1567 | if (ret < 0) { |
05330448 | 1568 | return ret; |
b9bec74b | 1569 | } |
ea643051 JK |
1570 | if (level >= KVM_PUT_RESET_STATE) { |
1571 | ret = kvm_put_mp_state(env); | |
b9bec74b | 1572 | if (ret < 0) { |
ea643051 | 1573 | return ret; |
b9bec74b | 1574 | } |
680c1c6f JK |
1575 | ret = kvm_put_apic(env); |
1576 | if (ret < 0) { | |
1577 | return ret; | |
1578 | } | |
ea643051 | 1579 | } |
ea643051 | 1580 | ret = kvm_put_vcpu_events(env, level); |
b9bec74b | 1581 | if (ret < 0) { |
a0fb002c | 1582 | return ret; |
b9bec74b | 1583 | } |
0d75a9ec | 1584 | ret = kvm_put_debugregs(env); |
b9bec74b | 1585 | if (ret < 0) { |
b0b1d690 | 1586 | return ret; |
b9bec74b | 1587 | } |
b0b1d690 JK |
1588 | /* must be last */ |
1589 | ret = kvm_guest_debug_workarounds(env); | |
b9bec74b | 1590 | if (ret < 0) { |
ff44f1a3 | 1591 | return ret; |
b9bec74b | 1592 | } |
05330448 AL |
1593 | return 0; |
1594 | } | |
1595 | ||
317ac620 | 1596 | int kvm_arch_get_registers(CPUX86State *env) |
05330448 AL |
1597 | { |
1598 | int ret; | |
1599 | ||
b7680cb6 | 1600 | assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
dbaa07c4 | 1601 | |
05330448 | 1602 | ret = kvm_getput_regs(env, 0); |
b9bec74b | 1603 | if (ret < 0) { |
05330448 | 1604 | return ret; |
b9bec74b | 1605 | } |
f1665b21 | 1606 | ret = kvm_get_xsave(env); |
b9bec74b | 1607 | if (ret < 0) { |
f1665b21 | 1608 | return ret; |
b9bec74b | 1609 | } |
f1665b21 | 1610 | ret = kvm_get_xcrs(env); |
b9bec74b | 1611 | if (ret < 0) { |
05330448 | 1612 | return ret; |
b9bec74b | 1613 | } |
05330448 | 1614 | ret = kvm_get_sregs(env); |
b9bec74b | 1615 | if (ret < 0) { |
05330448 | 1616 | return ret; |
b9bec74b | 1617 | } |
05330448 | 1618 | ret = kvm_get_msrs(env); |
b9bec74b | 1619 | if (ret < 0) { |
05330448 | 1620 | return ret; |
b9bec74b | 1621 | } |
5a2e3c2e | 1622 | ret = kvm_get_mp_state(env); |
b9bec74b | 1623 | if (ret < 0) { |
5a2e3c2e | 1624 | return ret; |
b9bec74b | 1625 | } |
680c1c6f JK |
1626 | ret = kvm_get_apic(env); |
1627 | if (ret < 0) { | |
1628 | return ret; | |
1629 | } | |
a0fb002c | 1630 | ret = kvm_get_vcpu_events(env); |
b9bec74b | 1631 | if (ret < 0) { |
a0fb002c | 1632 | return ret; |
b9bec74b | 1633 | } |
ff44f1a3 | 1634 | ret = kvm_get_debugregs(env); |
b9bec74b | 1635 | if (ret < 0) { |
ff44f1a3 | 1636 | return ret; |
b9bec74b | 1637 | } |
05330448 AL |
1638 | return 0; |
1639 | } | |
1640 | ||
317ac620 | 1641 | void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run) |
05330448 | 1642 | { |
ce377af3 JK |
1643 | int ret; |
1644 | ||
276ce815 LJ |
1645 | /* Inject NMI */ |
1646 | if (env->interrupt_request & CPU_INTERRUPT_NMI) { | |
1647 | env->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
1648 | DPRINTF("injected NMI\n"); | |
ce377af3 JK |
1649 | ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1650 | if (ret < 0) { | |
1651 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1652 | strerror(-ret)); | |
1653 | } | |
276ce815 LJ |
1654 | } |
1655 | ||
db1669bc | 1656 | if (!kvm_irqchip_in_kernel()) { |
d362e757 JK |
1657 | /* Force the VCPU out of its inner loop to process any INIT requests |
1658 | * or pending TPR access reports. */ | |
1659 | if (env->interrupt_request & | |
1660 | (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { | |
db1669bc | 1661 | env->exit_request = 1; |
05330448 | 1662 | } |
05330448 | 1663 | |
db1669bc JK |
1664 | /* Try to inject an interrupt if the guest can accept it */ |
1665 | if (run->ready_for_interrupt_injection && | |
1666 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1667 | (env->eflags & IF_MASK)) { | |
1668 | int irq; | |
1669 | ||
1670 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1671 | irq = cpu_get_pic_interrupt(env); | |
1672 | if (irq >= 0) { | |
1673 | struct kvm_interrupt intr; | |
1674 | ||
1675 | intr.irq = irq; | |
db1669bc | 1676 | DPRINTF("injected interrupt %d\n", irq); |
ce377af3 JK |
1677 | ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1678 | if (ret < 0) { | |
1679 | fprintf(stderr, | |
1680 | "KVM: injection failed, interrupt lost (%s)\n", | |
1681 | strerror(-ret)); | |
1682 | } | |
db1669bc JK |
1683 | } |
1684 | } | |
05330448 | 1685 | |
db1669bc JK |
1686 | /* If we have an interrupt but the guest is not ready to receive an |
1687 | * interrupt, request an interrupt window exit. This will | |
1688 | * cause a return to userspace as soon as the guest is ready to | |
1689 | * receive interrupts. */ | |
1690 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) { | |
1691 | run->request_interrupt_window = 1; | |
1692 | } else { | |
1693 | run->request_interrupt_window = 0; | |
1694 | } | |
1695 | ||
1696 | DPRINTF("setting tpr\n"); | |
1697 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1698 | } | |
05330448 AL |
1699 | } |
1700 | ||
317ac620 | 1701 | void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run) |
05330448 | 1702 | { |
b9bec74b | 1703 | if (run->if_flag) { |
05330448 | 1704 | env->eflags |= IF_MASK; |
b9bec74b | 1705 | } else { |
05330448 | 1706 | env->eflags &= ~IF_MASK; |
b9bec74b | 1707 | } |
4a942cea BS |
1708 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1709 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1710 | } |
1711 | ||
317ac620 | 1712 | int kvm_arch_process_async_events(CPUX86State *env) |
0af691d7 | 1713 | { |
232fc23b AF |
1714 | X86CPU *cpu = x86_env_get_cpu(env); |
1715 | ||
ab443475 JK |
1716 | if (env->interrupt_request & CPU_INTERRUPT_MCE) { |
1717 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ | |
1718 | assert(env->mcg_cap); | |
1719 | ||
1720 | env->interrupt_request &= ~CPU_INTERRUPT_MCE; | |
1721 | ||
1722 | kvm_cpu_synchronize_state(env); | |
1723 | ||
1724 | if (env->exception_injected == EXCP08_DBLE) { | |
1725 | /* this means triple fault */ | |
1726 | qemu_system_reset_request(); | |
1727 | env->exit_request = 1; | |
1728 | return 0; | |
1729 | } | |
1730 | env->exception_injected = EXCP12_MCHK; | |
1731 | env->has_error_code = 0; | |
1732 | ||
1733 | env->halted = 0; | |
1734 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { | |
1735 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1736 | } | |
1737 | } | |
1738 | ||
db1669bc JK |
1739 | if (kvm_irqchip_in_kernel()) { |
1740 | return 0; | |
1741 | } | |
1742 | ||
5d62c43a JK |
1743 | if (env->interrupt_request & CPU_INTERRUPT_POLL) { |
1744 | env->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
1745 | apic_poll_irq(env->apic_state); | |
1746 | } | |
4601f7b0 JK |
1747 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) && |
1748 | (env->eflags & IF_MASK)) || | |
1749 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
6792a57b JK |
1750 | env->halted = 0; |
1751 | } | |
0af691d7 MT |
1752 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { |
1753 | kvm_cpu_synchronize_state(env); | |
232fc23b | 1754 | do_cpu_init(cpu); |
0af691d7 | 1755 | } |
0af691d7 MT |
1756 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { |
1757 | kvm_cpu_synchronize_state(env); | |
232fc23b | 1758 | do_cpu_sipi(cpu); |
0af691d7 | 1759 | } |
d362e757 JK |
1760 | if (env->interrupt_request & CPU_INTERRUPT_TPR) { |
1761 | env->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
1762 | kvm_cpu_synchronize_state(env); | |
1763 | apic_handle_tpr_access_report(env->apic_state, env->eip, | |
1764 | env->tpr_access_type); | |
1765 | } | |
0af691d7 MT |
1766 | |
1767 | return env->halted; | |
1768 | } | |
1769 | ||
317ac620 | 1770 | static int kvm_handle_halt(CPUX86State *env) |
05330448 AL |
1771 | { |
1772 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1773 | (env->eflags & IF_MASK)) && | |
1774 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1775 | env->halted = 1; | |
bb4ea393 | 1776 | return EXCP_HLT; |
05330448 AL |
1777 | } |
1778 | ||
bb4ea393 | 1779 | return 0; |
05330448 AL |
1780 | } |
1781 | ||
317ac620 | 1782 | static int kvm_handle_tpr_access(CPUX86State *env) |
d362e757 JK |
1783 | { |
1784 | struct kvm_run *run = env->kvm_run; | |
1785 | ||
1786 | apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip, | |
1787 | run->tpr_access.is_write ? TPR_ACCESS_WRITE | |
1788 | : TPR_ACCESS_READ); | |
1789 | return 1; | |
1790 | } | |
1791 | ||
317ac620 | 1792 | int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 1793 | { |
38972938 | 1794 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1795 | |
e22a25c9 | 1796 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
b9bec74b | 1797 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
e22a25c9 | 1798 | return -EINVAL; |
b9bec74b | 1799 | } |
e22a25c9 AL |
1800 | return 0; |
1801 | } | |
1802 | ||
317ac620 | 1803 | int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp) |
e22a25c9 AL |
1804 | { |
1805 | uint8_t int3; | |
1806 | ||
1807 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
b9bec74b | 1808 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
e22a25c9 | 1809 | return -EINVAL; |
b9bec74b | 1810 | } |
e22a25c9 AL |
1811 | return 0; |
1812 | } | |
1813 | ||
1814 | static struct { | |
1815 | target_ulong addr; | |
1816 | int len; | |
1817 | int type; | |
1818 | } hw_breakpoint[4]; | |
1819 | ||
1820 | static int nb_hw_breakpoint; | |
1821 | ||
1822 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1823 | { | |
1824 | int n; | |
1825 | ||
b9bec74b | 1826 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1827 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1828 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1829 | return n; |
b9bec74b JK |
1830 | } |
1831 | } | |
e22a25c9 AL |
1832 | return -1; |
1833 | } | |
1834 | ||
1835 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1836 | target_ulong len, int type) | |
1837 | { | |
1838 | switch (type) { | |
1839 | case GDB_BREAKPOINT_HW: | |
1840 | len = 1; | |
1841 | break; | |
1842 | case GDB_WATCHPOINT_WRITE: | |
1843 | case GDB_WATCHPOINT_ACCESS: | |
1844 | switch (len) { | |
1845 | case 1: | |
1846 | break; | |
1847 | case 2: | |
1848 | case 4: | |
1849 | case 8: | |
b9bec74b | 1850 | if (addr & (len - 1)) { |
e22a25c9 | 1851 | return -EINVAL; |
b9bec74b | 1852 | } |
e22a25c9 AL |
1853 | break; |
1854 | default: | |
1855 | return -EINVAL; | |
1856 | } | |
1857 | break; | |
1858 | default: | |
1859 | return -ENOSYS; | |
1860 | } | |
1861 | ||
b9bec74b | 1862 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 1863 | return -ENOBUFS; |
b9bec74b JK |
1864 | } |
1865 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 1866 | return -EEXIST; |
b9bec74b | 1867 | } |
e22a25c9 AL |
1868 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1869 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1870 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1871 | nb_hw_breakpoint++; | |
1872 | ||
1873 | return 0; | |
1874 | } | |
1875 | ||
1876 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1877 | target_ulong len, int type) | |
1878 | { | |
1879 | int n; | |
1880 | ||
1881 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 1882 | if (n < 0) { |
e22a25c9 | 1883 | return -ENOENT; |
b9bec74b | 1884 | } |
e22a25c9 AL |
1885 | nb_hw_breakpoint--; |
1886 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1887 | ||
1888 | return 0; | |
1889 | } | |
1890 | ||
1891 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1892 | { | |
1893 | nb_hw_breakpoint = 0; | |
1894 | } | |
1895 | ||
1896 | static CPUWatchpoint hw_watchpoint; | |
1897 | ||
f2574737 | 1898 | static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 1899 | { |
f2574737 | 1900 | int ret = 0; |
e22a25c9 AL |
1901 | int n; |
1902 | ||
1903 | if (arch_info->exception == 1) { | |
1904 | if (arch_info->dr6 & (1 << 14)) { | |
b9bec74b | 1905 | if (cpu_single_env->singlestep_enabled) { |
f2574737 | 1906 | ret = EXCP_DEBUG; |
b9bec74b | 1907 | } |
e22a25c9 | 1908 | } else { |
b9bec74b JK |
1909 | for (n = 0; n < 4; n++) { |
1910 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
1911 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1912 | case 0x0: | |
f2574737 | 1913 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1914 | break; |
1915 | case 0x1: | |
f2574737 | 1916 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1917 | cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1918 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1919 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1920 | break; | |
1921 | case 0x3: | |
f2574737 | 1922 | ret = EXCP_DEBUG; |
e22a25c9 AL |
1923 | cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1924 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1925 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1926 | break; | |
1927 | } | |
b9bec74b JK |
1928 | } |
1929 | } | |
e22a25c9 | 1930 | } |
b9bec74b | 1931 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
f2574737 | 1932 | ret = EXCP_DEBUG; |
b9bec74b | 1933 | } |
f2574737 | 1934 | if (ret == 0) { |
b0b1d690 JK |
1935 | cpu_synchronize_state(cpu_single_env); |
1936 | assert(cpu_single_env->exception_injected == -1); | |
1937 | ||
f2574737 | 1938 | /* pass to guest */ |
b0b1d690 JK |
1939 | cpu_single_env->exception_injected = arch_info->exception; |
1940 | cpu_single_env->has_error_code = 0; | |
1941 | } | |
e22a25c9 | 1942 | |
f2574737 | 1943 | return ret; |
e22a25c9 AL |
1944 | } |
1945 | ||
317ac620 | 1946 | void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
1947 | { |
1948 | const uint8_t type_code[] = { | |
1949 | [GDB_BREAKPOINT_HW] = 0x0, | |
1950 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1951 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1952 | }; | |
1953 | const uint8_t len_code[] = { | |
1954 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1955 | }; | |
1956 | int n; | |
1957 | ||
b9bec74b | 1958 | if (kvm_sw_breakpoints_active(env)) { |
e22a25c9 | 1959 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 1960 | } |
e22a25c9 AL |
1961 | if (nb_hw_breakpoint > 0) { |
1962 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1963 | dbg->arch.debugreg[7] = 0x0600; | |
1964 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1965 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1966 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1967 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 1968 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
1969 | } |
1970 | } | |
1971 | } | |
4513d923 | 1972 | |
2a4dac83 JK |
1973 | static bool host_supports_vmx(void) |
1974 | { | |
1975 | uint32_t ecx, unused; | |
1976 | ||
1977 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
1978 | return ecx & CPUID_EXT_VMX; | |
1979 | } | |
1980 | ||
1981 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
1982 | ||
317ac620 | 1983 | int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run) |
2a4dac83 JK |
1984 | { |
1985 | uint64_t code; | |
1986 | int ret; | |
1987 | ||
1988 | switch (run->exit_reason) { | |
1989 | case KVM_EXIT_HLT: | |
1990 | DPRINTF("handle_hlt\n"); | |
1991 | ret = kvm_handle_halt(env); | |
1992 | break; | |
1993 | case KVM_EXIT_SET_TPR: | |
1994 | ret = 0; | |
1995 | break; | |
d362e757 JK |
1996 | case KVM_EXIT_TPR_ACCESS: |
1997 | ret = kvm_handle_tpr_access(env); | |
1998 | break; | |
2a4dac83 JK |
1999 | case KVM_EXIT_FAIL_ENTRY: |
2000 | code = run->fail_entry.hardware_entry_failure_reason; | |
2001 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
2002 | code); | |
2003 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
2004 | fprintf(stderr, | |
12619721 | 2005 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
2006 | "unrestricted mode\n" |
2007 | "support, the failure can be most likely due to the guest " | |
2008 | "entering an invalid\n" | |
2009 | "state for Intel VT. For example, the guest maybe running " | |
2010 | "in big real mode\n" | |
2011 | "which is not supported on less recent Intel processors." | |
2012 | "\n\n"); | |
2013 | } | |
2014 | ret = -1; | |
2015 | break; | |
2016 | case KVM_EXIT_EXCEPTION: | |
2017 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
2018 | run->ex.exception, run->ex.error_code); | |
2019 | ret = -1; | |
2020 | break; | |
f2574737 JK |
2021 | case KVM_EXIT_DEBUG: |
2022 | DPRINTF("kvm_exit_debug\n"); | |
2023 | ret = kvm_handle_debug(&run->debug.arch); | |
2024 | break; | |
2a4dac83 JK |
2025 | default: |
2026 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
2027 | ret = -1; | |
2028 | break; | |
2029 | } | |
2030 | ||
2031 | return ret; | |
2032 | } | |
2033 | ||
317ac620 | 2034 | bool kvm_arch_stop_on_emulation_error(CPUX86State *env) |
4513d923 | 2035 | { |
d1f86636 | 2036 | kvm_cpu_synchronize_state(env); |
b9bec74b JK |
2037 | return !(env->cr[0] & CR0_PE_MASK) || |
2038 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2039 | } |
84b058d7 JK |
2040 | |
2041 | void kvm_arch_init_irq_routing(KVMState *s) | |
2042 | { | |
2043 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
2044 | /* If kernel can't do irq routing, interrupt source | |
2045 | * override 0->2 cannot be set up as required by HPET. | |
2046 | * So we have to disable it. | |
2047 | */ | |
2048 | no_hpet = 1; | |
2049 | } | |
cc7e0ddf | 2050 | /* We know at this point that we're using the in-kernel |
614e41bc | 2051 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 2052 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf PM |
2053 | */ |
2054 | kvm_irqfds_allowed = true; | |
614e41bc | 2055 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 2056 | kvm_gsi_routing_allowed = true; |
84b058d7 | 2057 | } |