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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
9c17d615 PB |
24 | #include "sysemu/sysemu.h" |
25 | #include "sysemu/kvm.h" | |
1d31f66b | 26 | #include "kvm_i386.h" |
05330448 | 27 | #include "cpu.h" |
022c62cb | 28 | #include "exec/gdbstub.h" |
1de7afc9 PB |
29 | #include "qemu/host-utils.h" |
30 | #include "qemu/config-file.h" | |
0d09e41a PB |
31 | #include "hw/i386/pc.h" |
32 | #include "hw/i386/apic.h" | |
022c62cb | 33 | #include "exec/ioport.h" |
92067bf4 | 34 | #include <asm/hyperv.h> |
a2cb15b0 | 35 | #include "hw/pci/pci.h" |
05330448 AL |
36 | |
37 | //#define DEBUG_KVM | |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_INFO(SET_TSS_ADDR), | |
59 | KVM_CAP_INFO(EXT_CPUID), | |
60 | KVM_CAP_INFO(MP_STATE), | |
61 | KVM_CAP_LAST_INFO | |
62 | }; | |
25d2e361 | 63 | |
c3a3a7d3 JK |
64 | static bool has_msr_star; |
65 | static bool has_msr_hsave_pa; | |
f28558d3 | 66 | static bool has_msr_tsc_adjust; |
aa82ba54 | 67 | static bool has_msr_tsc_deadline; |
c5999bfc | 68 | static bool has_msr_async_pf_en; |
bc9a839d | 69 | static bool has_msr_pv_eoi_en; |
21e87c46 | 70 | static bool has_msr_misc_enable; |
917367aa | 71 | static bool has_msr_kvm_steal_time; |
25d2e361 | 72 | static int lm_capable_kernel; |
b827df58 | 73 | |
1d31f66b PM |
74 | bool kvm_allows_irq0_override(void) |
75 | { | |
76 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
77 | } | |
78 | ||
b827df58 AK |
79 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
80 | { | |
81 | struct kvm_cpuid2 *cpuid; | |
82 | int r, size; | |
83 | ||
84 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
7267c094 | 85 | cpuid = (struct kvm_cpuid2 *)g_malloc0(size); |
b827df58 AK |
86 | cpuid->nent = max; |
87 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
88 | if (r == 0 && cpuid->nent >= max) { |
89 | r = -E2BIG; | |
90 | } | |
b827df58 AK |
91 | if (r < 0) { |
92 | if (r == -E2BIG) { | |
7267c094 | 93 | g_free(cpuid); |
b827df58 AK |
94 | return NULL; |
95 | } else { | |
96 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
97 | strerror(-r)); | |
98 | exit(1); | |
99 | } | |
100 | } | |
101 | return cpuid; | |
102 | } | |
103 | ||
dd87f8a6 EH |
104 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough |
105 | * for all entries. | |
106 | */ | |
107 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
108 | { | |
109 | struct kvm_cpuid2 *cpuid; | |
110 | int max = 1; | |
111 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
112 | max *= 2; | |
113 | } | |
114 | return cpuid; | |
115 | } | |
116 | ||
0c31b744 GC |
117 | struct kvm_para_features { |
118 | int cap; | |
119 | int feature; | |
120 | } para_features[] = { | |
121 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
122 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
123 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 124 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
125 | { -1, -1 } |
126 | }; | |
127 | ||
ba9bc59e | 128 | static int get_para_features(KVMState *s) |
0c31b744 GC |
129 | { |
130 | int i, features = 0; | |
131 | ||
132 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
ba9bc59e | 133 | if (kvm_check_extension(s, para_features[i].cap)) { |
0c31b744 GC |
134 | features |= (1 << para_features[i].feature); |
135 | } | |
136 | } | |
137 | ||
138 | return features; | |
139 | } | |
0c31b744 GC |
140 | |
141 | ||
829ae2f9 EH |
142 | /* Returns the value for a specific register on the cpuid entry |
143 | */ | |
144 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
145 | { | |
146 | uint32_t ret = 0; | |
147 | switch (reg) { | |
148 | case R_EAX: | |
149 | ret = entry->eax; | |
150 | break; | |
151 | case R_EBX: | |
152 | ret = entry->ebx; | |
153 | break; | |
154 | case R_ECX: | |
155 | ret = entry->ecx; | |
156 | break; | |
157 | case R_EDX: | |
158 | ret = entry->edx; | |
159 | break; | |
160 | } | |
161 | return ret; | |
162 | } | |
163 | ||
4fb73f1d EH |
164 | /* Find matching entry for function/index on kvm_cpuid2 struct |
165 | */ | |
166 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
167 | uint32_t function, | |
168 | uint32_t index) | |
169 | { | |
170 | int i; | |
171 | for (i = 0; i < cpuid->nent; ++i) { | |
172 | if (cpuid->entries[i].function == function && | |
173 | cpuid->entries[i].index == index) { | |
174 | return &cpuid->entries[i]; | |
175 | } | |
176 | } | |
177 | /* not found: */ | |
178 | return NULL; | |
179 | } | |
180 | ||
ba9bc59e | 181 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 182 | uint32_t index, int reg) |
b827df58 AK |
183 | { |
184 | struct kvm_cpuid2 *cpuid; | |
b827df58 AK |
185 | uint32_t ret = 0; |
186 | uint32_t cpuid_1_edx; | |
8c723b79 | 187 | bool found = false; |
b827df58 | 188 | |
dd87f8a6 | 189 | cpuid = get_supported_cpuid(s); |
b827df58 | 190 | |
4fb73f1d EH |
191 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); |
192 | if (entry) { | |
193 | found = true; | |
194 | ret = cpuid_entry_get_reg(entry, reg); | |
b827df58 AK |
195 | } |
196 | ||
7b46e5ce EH |
197 | /* Fixups for the data returned by KVM, below */ |
198 | ||
c2acb022 EH |
199 | if (function == 1 && reg == R_EDX) { |
200 | /* KVM before 2.6.30 misreports the following features */ | |
201 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
84bd945c EH |
202 | } else if (function == 1 && reg == R_ECX) { |
203 | /* We can set the hypervisor flag, even if KVM does not return it on | |
204 | * GET_SUPPORTED_CPUID | |
205 | */ | |
206 | ret |= CPUID_EXT_HYPERVISOR; | |
ac67ee26 EH |
207 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it |
208 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
209 | * and the irqchip is in the kernel. | |
210 | */ | |
211 | if (kvm_irqchip_in_kernel() && | |
212 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
213 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
214 | } | |
41e5e76d EH |
215 | |
216 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
217 | * without the in-kernel irqchip | |
218 | */ | |
219 | if (!kvm_irqchip_in_kernel()) { | |
220 | ret &= ~CPUID_EXT_X2APIC; | |
b827df58 | 221 | } |
c2acb022 EH |
222 | } else if (function == 0x80000001 && reg == R_EDX) { |
223 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
224 | * so add missing bits according to the AMD spec: | |
225 | */ | |
226 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
227 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
b827df58 AK |
228 | } |
229 | ||
7267c094 | 230 | g_free(cpuid); |
b827df58 | 231 | |
0c31b744 | 232 | /* fallback for older kernels */ |
8c723b79 | 233 | if ((function == KVM_CPUID_FEATURES) && !found) { |
ba9bc59e | 234 | ret = get_para_features(s); |
b9bec74b | 235 | } |
0c31b744 GC |
236 | |
237 | return ret; | |
bb0300dc | 238 | } |
bb0300dc | 239 | |
3c85e74f HY |
240 | typedef struct HWPoisonPage { |
241 | ram_addr_t ram_addr; | |
242 | QLIST_ENTRY(HWPoisonPage) list; | |
243 | } HWPoisonPage; | |
244 | ||
245 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
246 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
247 | ||
248 | static void kvm_unpoison_all(void *param) | |
249 | { | |
250 | HWPoisonPage *page, *next_page; | |
251 | ||
252 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
253 | QLIST_REMOVE(page, list); | |
254 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
7267c094 | 255 | g_free(page); |
3c85e74f HY |
256 | } |
257 | } | |
258 | ||
3c85e74f HY |
259 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
260 | { | |
261 | HWPoisonPage *page; | |
262 | ||
263 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
264 | if (page->ram_addr == ram_addr) { | |
265 | return; | |
266 | } | |
267 | } | |
7267c094 | 268 | page = g_malloc(sizeof(HWPoisonPage)); |
3c85e74f HY |
269 | page->ram_addr = ram_addr; |
270 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
271 | } | |
272 | ||
e7701825 MT |
273 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
274 | int *max_banks) | |
275 | { | |
276 | int r; | |
277 | ||
14a09518 | 278 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
279 | if (r > 0) { |
280 | *max_banks = r; | |
281 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
282 | } | |
283 | return -ENOSYS; | |
284 | } | |
285 | ||
bee615d4 | 286 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) |
e7701825 | 287 | { |
bee615d4 | 288 | CPUX86State *env = &cpu->env; |
c34d440a JK |
289 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
290 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
291 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 292 | |
c34d440a JK |
293 | if (code == BUS_MCEERR_AR) { |
294 | status |= MCI_STATUS_AR | 0x134; | |
295 | mcg_status |= MCG_STATUS_EIPV; | |
296 | } else { | |
297 | status |= 0xc0; | |
298 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 299 | } |
8c5cf3b6 | 300 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, |
c34d440a JK |
301 | (MCM_ADDR_PHYS << 6) | 0xc, |
302 | cpu_x86_support_mca_broadcast(env) ? | |
303 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 304 | } |
419fb20a JK |
305 | |
306 | static void hardware_memory_error(void) | |
307 | { | |
308 | fprintf(stderr, "Hardware memory error!\n"); | |
309 | exit(1); | |
310 | } | |
311 | ||
20d695a9 | 312 | int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) |
419fb20a | 313 | { |
20d695a9 AF |
314 | X86CPU *cpu = X86_CPU(c); |
315 | CPUX86State *env = &cpu->env; | |
419fb20a | 316 | ram_addr_t ram_addr; |
a8170e5e | 317 | hwaddr paddr; |
419fb20a JK |
318 | |
319 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a | 320 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
1b5ec234 | 321 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
a60f24b5 | 322 | !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { |
419fb20a JK |
323 | fprintf(stderr, "Hardware memory error for memory used by " |
324 | "QEMU itself instead of guest system!\n"); | |
325 | /* Hope we are lucky for AO MCE */ | |
326 | if (code == BUS_MCEERR_AO) { | |
327 | return 0; | |
328 | } else { | |
329 | hardware_memory_error(); | |
330 | } | |
331 | } | |
3c85e74f | 332 | kvm_hwpoison_page_add(ram_addr); |
bee615d4 | 333 | kvm_mce_inject(cpu, paddr, code); |
e56ff191 | 334 | } else { |
419fb20a JK |
335 | if (code == BUS_MCEERR_AO) { |
336 | return 0; | |
337 | } else if (code == BUS_MCEERR_AR) { | |
338 | hardware_memory_error(); | |
339 | } else { | |
340 | return 1; | |
341 | } | |
342 | } | |
343 | return 0; | |
344 | } | |
345 | ||
346 | int kvm_arch_on_sigbus(int code, void *addr) | |
347 | { | |
182735ef AF |
348 | X86CPU *cpu = X86_CPU(first_cpu); |
349 | ||
350 | if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
419fb20a | 351 | ram_addr_t ram_addr; |
a8170e5e | 352 | hwaddr paddr; |
419fb20a JK |
353 | |
354 | /* Hope we are lucky for AO MCE */ | |
1b5ec234 | 355 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
182735ef | 356 | !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, |
a60f24b5 | 357 | addr, &paddr)) { |
419fb20a JK |
358 | fprintf(stderr, "Hardware memory error for memory used by " |
359 | "QEMU itself instead of guest system!: %p\n", addr); | |
360 | return 0; | |
361 | } | |
3c85e74f | 362 | kvm_hwpoison_page_add(ram_addr); |
182735ef | 363 | kvm_mce_inject(X86_CPU(first_cpu), paddr, code); |
e56ff191 | 364 | } else { |
419fb20a JK |
365 | if (code == BUS_MCEERR_AO) { |
366 | return 0; | |
367 | } else if (code == BUS_MCEERR_AR) { | |
368 | hardware_memory_error(); | |
369 | } else { | |
370 | return 1; | |
371 | } | |
372 | } | |
373 | return 0; | |
374 | } | |
e7701825 | 375 | |
1bc22652 | 376 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) |
ab443475 | 377 | { |
1bc22652 AF |
378 | CPUX86State *env = &cpu->env; |
379 | ||
ab443475 JK |
380 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
381 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
382 | struct kvm_x86_mce mce; | |
383 | ||
384 | env->exception_injected = -1; | |
385 | ||
386 | /* | |
387 | * There must be at least one bank in use if an MCE is pending. | |
388 | * Find it and use its values for the event injection. | |
389 | */ | |
390 | for (bank = 0; bank < bank_num; bank++) { | |
391 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
392 | break; | |
393 | } | |
394 | } | |
395 | assert(bank < bank_num); | |
396 | ||
397 | mce.bank = bank; | |
398 | mce.status = env->mce_banks[bank * 4 + 1]; | |
399 | mce.mcg_status = env->mcg_status; | |
400 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
401 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
402 | ||
1bc22652 | 403 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); |
ab443475 | 404 | } |
ab443475 JK |
405 | return 0; |
406 | } | |
407 | ||
1dfb4dd9 | 408 | static void cpu_update_state(void *opaque, int running, RunState state) |
b8cc45d6 | 409 | { |
317ac620 | 410 | CPUX86State *env = opaque; |
b8cc45d6 GC |
411 | |
412 | if (running) { | |
413 | env->tsc_valid = false; | |
414 | } | |
415 | } | |
416 | ||
83b17af5 | 417 | unsigned long kvm_arch_vcpu_id(CPUState *cs) |
b164e48e | 418 | { |
83b17af5 EH |
419 | X86CPU *cpu = X86_CPU(cs); |
420 | return cpu->env.cpuid_apic_id; | |
b164e48e EH |
421 | } |
422 | ||
92067bf4 IM |
423 | #ifndef KVM_CPUID_SIGNATURE_NEXT |
424 | #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 | |
425 | #endif | |
426 | ||
427 | static bool hyperv_hypercall_available(X86CPU *cpu) | |
428 | { | |
429 | return cpu->hyperv_vapic || | |
430 | (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY); | |
431 | } | |
432 | ||
433 | static bool hyperv_enabled(X86CPU *cpu) | |
434 | { | |
435 | return hyperv_hypercall_available(cpu) || | |
436 | cpu->hyperv_relaxed_timing; | |
437 | } | |
438 | ||
f8bb0565 | 439 | #define KVM_MAX_CPUID_ENTRIES 100 |
0893d460 | 440 | |
20d695a9 | 441 | int kvm_arch_init_vcpu(CPUState *cs) |
05330448 AL |
442 | { |
443 | struct { | |
486bd5a2 | 444 | struct kvm_cpuid2 cpuid; |
f8bb0565 | 445 | struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; |
541dc0d4 | 446 | } QEMU_PACKED cpuid_data; |
20d695a9 AF |
447 | X86CPU *cpu = X86_CPU(cs); |
448 | CPUX86State *env = &cpu->env; | |
486bd5a2 | 449 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 450 | uint32_t unused; |
bb0300dc | 451 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 452 | uint32_t signature[3]; |
e7429073 | 453 | int r; |
05330448 AL |
454 | |
455 | cpuid_i = 0; | |
456 | ||
bb0300dc | 457 | /* Paravirtualization CPUIDs */ |
bb0300dc GN |
458 | c = &cpuid_data.entries[cpuid_i++]; |
459 | memset(c, 0, sizeof(*c)); | |
460 | c->function = KVM_CPUID_SIGNATURE; | |
92067bf4 | 461 | if (!hyperv_enabled(cpu)) { |
eab70139 VR |
462 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); |
463 | c->eax = 0; | |
464 | } else { | |
465 | memcpy(signature, "Microsoft Hv", 12); | |
466 | c->eax = HYPERV_CPUID_MIN; | |
467 | } | |
bb0300dc GN |
468 | c->ebx = signature[0]; |
469 | c->ecx = signature[1]; | |
470 | c->edx = signature[2]; | |
471 | ||
472 | c = &cpuid_data.entries[cpuid_i++]; | |
473 | memset(c, 0, sizeof(*c)); | |
474 | c->function = KVM_CPUID_FEATURES; | |
0514ef2f | 475 | c->eax = env->features[FEAT_KVM]; |
0c31b744 | 476 | |
92067bf4 | 477 | if (hyperv_enabled(cpu)) { |
eab70139 VR |
478 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); |
479 | c->eax = signature[0]; | |
480 | ||
481 | c = &cpuid_data.entries[cpuid_i++]; | |
482 | memset(c, 0, sizeof(*c)); | |
483 | c->function = HYPERV_CPUID_VERSION; | |
484 | c->eax = 0x00001bbc; | |
485 | c->ebx = 0x00060001; | |
486 | ||
487 | c = &cpuid_data.entries[cpuid_i++]; | |
488 | memset(c, 0, sizeof(*c)); | |
489 | c->function = HYPERV_CPUID_FEATURES; | |
92067bf4 | 490 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
491 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
492 | } | |
92067bf4 | 493 | if (cpu->hyperv_vapic) { |
eab70139 VR |
494 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
495 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
496 | } | |
497 | ||
498 | c = &cpuid_data.entries[cpuid_i++]; | |
499 | memset(c, 0, sizeof(*c)); | |
500 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; | |
92067bf4 | 501 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
502 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; |
503 | } | |
92067bf4 | 504 | if (cpu->hyperv_vapic) { |
eab70139 VR |
505 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; |
506 | } | |
92067bf4 | 507 | c->ebx = cpu->hyperv_spinlock_attempts; |
eab70139 VR |
508 | |
509 | c = &cpuid_data.entries[cpuid_i++]; | |
510 | memset(c, 0, sizeof(*c)); | |
511 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; | |
512 | c->eax = 0x40; | |
513 | c->ebx = 0x40; | |
514 | ||
515 | c = &cpuid_data.entries[cpuid_i++]; | |
516 | memset(c, 0, sizeof(*c)); | |
517 | c->function = KVM_CPUID_SIGNATURE_NEXT; | |
518 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
519 | c->eax = 0; | |
520 | c->ebx = signature[0]; | |
521 | c->ecx = signature[1]; | |
522 | c->edx = signature[2]; | |
523 | } | |
524 | ||
0c31b744 | 525 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 526 | |
bc9a839d MT |
527 | has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI); |
528 | ||
917367aa MT |
529 | has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME); |
530 | ||
a33609ca | 531 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
532 | |
533 | for (i = 0; i <= limit; i++) { | |
f8bb0565 IM |
534 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
535 | fprintf(stderr, "unsupported level value: 0x%x\n", limit); | |
536 | abort(); | |
537 | } | |
bb0300dc | 538 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
539 | |
540 | switch (i) { | |
a36b1029 AL |
541 | case 2: { |
542 | /* Keep reading function 2 till all the input is received */ | |
543 | int times; | |
544 | ||
a36b1029 | 545 | c->function = i; |
a33609ca AL |
546 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
547 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
548 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
549 | times = c->eax & 0xff; | |
a36b1029 AL |
550 | |
551 | for (j = 1; j < times; ++j) { | |
f8bb0565 IM |
552 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
553 | fprintf(stderr, "cpuid_data is full, no space for " | |
554 | "cpuid(eax:2):eax & 0xf = 0x%x\n", times); | |
555 | abort(); | |
556 | } | |
a33609ca | 557 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 558 | c->function = i; |
a33609ca AL |
559 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
560 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
561 | } |
562 | break; | |
563 | } | |
486bd5a2 AL |
564 | case 4: |
565 | case 0xb: | |
566 | case 0xd: | |
567 | for (j = 0; ; j++) { | |
31e8c696 AP |
568 | if (i == 0xd && j == 64) { |
569 | break; | |
570 | } | |
486bd5a2 AL |
571 | c->function = i; |
572 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
573 | c->index = j; | |
a33609ca | 574 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 575 | |
b9bec74b | 576 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 577 | break; |
b9bec74b JK |
578 | } |
579 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 580 | break; |
b9bec74b JK |
581 | } |
582 | if (i == 0xd && c->eax == 0) { | |
31e8c696 | 583 | continue; |
b9bec74b | 584 | } |
f8bb0565 IM |
585 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
586 | fprintf(stderr, "cpuid_data is full, no space for " | |
587 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
588 | abort(); | |
589 | } | |
a33609ca | 590 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
591 | } |
592 | break; | |
593 | default: | |
486bd5a2 | 594 | c->function = i; |
a33609ca AL |
595 | c->flags = 0; |
596 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
597 | break; |
598 | } | |
05330448 | 599 | } |
a33609ca | 600 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
601 | |
602 | for (i = 0x80000000; i <= limit; i++) { | |
f8bb0565 IM |
603 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
604 | fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); | |
605 | abort(); | |
606 | } | |
bb0300dc | 607 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 608 | |
05330448 | 609 | c->function = i; |
a33609ca AL |
610 | c->flags = 0; |
611 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
612 | } |
613 | ||
b3baa152 | 614 | /* Call Centaur's CPUID instructions they are supported. */ |
615 | if (env->cpuid_xlevel2 > 0) { | |
b3baa152 | 616 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
617 | ||
618 | for (i = 0xC0000000; i <= limit; i++) { | |
f8bb0565 IM |
619 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
620 | fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); | |
621 | abort(); | |
622 | } | |
b3baa152 | 623 | c = &cpuid_data.entries[cpuid_i++]; |
624 | ||
625 | c->function = i; | |
626 | c->flags = 0; | |
627 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
628 | } | |
629 | } | |
630 | ||
05330448 AL |
631 | cpuid_data.cpuid.nent = cpuid_i; |
632 | ||
e7701825 | 633 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
0514ef2f | 634 | && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == |
fc7a504c | 635 | (CPUID_MCE | CPUID_MCA) |
a60f24b5 | 636 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { |
e7701825 MT |
637 | uint64_t mcg_cap; |
638 | int banks; | |
32a42024 | 639 | int ret; |
e7701825 | 640 | |
a60f24b5 | 641 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); |
75d49497 JK |
642 | if (ret < 0) { |
643 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
644 | return ret; | |
e7701825 | 645 | } |
75d49497 JK |
646 | |
647 | if (banks > MCE_BANKS_DEF) { | |
648 | banks = MCE_BANKS_DEF; | |
649 | } | |
650 | mcg_cap &= MCE_CAP_DEF; | |
651 | mcg_cap |= banks; | |
1bc22652 | 652 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap); |
75d49497 JK |
653 | if (ret < 0) { |
654 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
655 | return ret; | |
656 | } | |
657 | ||
658 | env->mcg_cap = mcg_cap; | |
e7701825 | 659 | } |
e7701825 | 660 | |
b8cc45d6 GC |
661 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
662 | ||
7e680753 | 663 | cpuid_data.cpuid.padding = 0; |
1bc22652 | 664 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); |
fdc9c41a JK |
665 | if (r) { |
666 | return r; | |
667 | } | |
e7429073 | 668 | |
a60f24b5 | 669 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL); |
e7429073 | 670 | if (r && env->tsc_khz) { |
1bc22652 | 671 | r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz); |
e7429073 JR |
672 | if (r < 0) { |
673 | fprintf(stderr, "KVM_SET_TSC_KHZ failed\n"); | |
674 | return r; | |
675 | } | |
676 | } | |
e7429073 | 677 | |
fabacc0f JK |
678 | if (kvm_has_xsave()) { |
679 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
680 | } | |
681 | ||
e7429073 | 682 | return 0; |
05330448 AL |
683 | } |
684 | ||
20d695a9 | 685 | void kvm_arch_reset_vcpu(CPUState *cs) |
caa5af0f | 686 | { |
20d695a9 AF |
687 | X86CPU *cpu = X86_CPU(cs); |
688 | CPUX86State *env = &cpu->env; | |
dd673288 | 689 | |
e73223a5 | 690 | env->exception_injected = -1; |
0e607a80 | 691 | env->interrupt_injected = -1; |
1a5e9d2f | 692 | env->xcr0 = 1; |
ddced198 | 693 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 694 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
695 | KVM_MP_STATE_UNINITIALIZED; |
696 | } else { | |
697 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
698 | } | |
caa5af0f JK |
699 | } |
700 | ||
c3a3a7d3 | 701 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 702 | { |
75b10c43 | 703 | static int kvm_supported_msrs; |
c3a3a7d3 | 704 | int ret = 0; |
05330448 AL |
705 | |
706 | /* first time */ | |
75b10c43 | 707 | if (kvm_supported_msrs == 0) { |
05330448 AL |
708 | struct kvm_msr_list msr_list, *kvm_msr_list; |
709 | ||
75b10c43 | 710 | kvm_supported_msrs = -1; |
05330448 AL |
711 | |
712 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
713 | * save/restore */ | |
4c9f7372 | 714 | msr_list.nmsrs = 0; |
c3a3a7d3 | 715 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 716 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 717 | return ret; |
6fb6d245 | 718 | } |
d9db889f JK |
719 | /* Old kernel modules had a bug and could write beyond the provided |
720 | memory. Allocate at least a safe amount of 1K. */ | |
7267c094 | 721 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
d9db889f JK |
722 | msr_list.nmsrs * |
723 | sizeof(msr_list.indices[0]))); | |
05330448 | 724 | |
55308450 | 725 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 726 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
727 | if (ret >= 0) { |
728 | int i; | |
729 | ||
730 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
731 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 732 | has_msr_star = true; |
75b10c43 MT |
733 | continue; |
734 | } | |
735 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 736 | has_msr_hsave_pa = true; |
75b10c43 | 737 | continue; |
05330448 | 738 | } |
f28558d3 WA |
739 | if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { |
740 | has_msr_tsc_adjust = true; | |
741 | continue; | |
742 | } | |
aa82ba54 LJ |
743 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { |
744 | has_msr_tsc_deadline = true; | |
745 | continue; | |
746 | } | |
21e87c46 AK |
747 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { |
748 | has_msr_misc_enable = true; | |
749 | continue; | |
750 | } | |
05330448 AL |
751 | } |
752 | } | |
753 | ||
7267c094 | 754 | g_free(kvm_msr_list); |
05330448 AL |
755 | } |
756 | ||
c3a3a7d3 | 757 | return ret; |
05330448 AL |
758 | } |
759 | ||
cad1e282 | 760 | int kvm_arch_init(KVMState *s) |
20420430 | 761 | { |
11076198 | 762 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 763 | uint64_t shadow_mem; |
20420430 | 764 | int ret; |
25d2e361 | 765 | struct utsname utsname; |
20420430 | 766 | |
c3a3a7d3 | 767 | ret = kvm_get_supported_msrs(s); |
20420430 | 768 | if (ret < 0) { |
20420430 SY |
769 | return ret; |
770 | } | |
25d2e361 MT |
771 | |
772 | uname(&utsname); | |
773 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
774 | ||
4c5b10b7 | 775 | /* |
11076198 JK |
776 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
777 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
778 | * Since these must be part of guest physical memory, we need to allocate | |
779 | * them, both by setting their start addresses in the kernel and by | |
780 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
781 | * | |
782 | * Older KVM versions may not support setting the identity map base. In | |
783 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
784 | * size. | |
4c5b10b7 | 785 | */ |
11076198 JK |
786 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
787 | /* Allows up to 16M BIOSes. */ | |
788 | identity_base = 0xfeffc000; | |
789 | ||
790 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
791 | if (ret < 0) { | |
792 | return ret; | |
793 | } | |
4c5b10b7 | 794 | } |
e56ff191 | 795 | |
11076198 JK |
796 | /* Set TSS base one page after EPT identity map. */ |
797 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
798 | if (ret < 0) { |
799 | return ret; | |
800 | } | |
801 | ||
11076198 JK |
802 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
803 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 804 | if (ret < 0) { |
11076198 | 805 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
806 | return ret; |
807 | } | |
3c85e74f | 808 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 809 | |
36ad0e94 MA |
810 | shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(), |
811 | "kvm_shadow_mem", -1); | |
812 | if (shadow_mem != -1) { | |
813 | shadow_mem /= 4096; | |
814 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
815 | if (ret < 0) { | |
816 | return ret; | |
39d6960a JK |
817 | } |
818 | } | |
11076198 | 819 | return 0; |
05330448 | 820 | } |
b9bec74b | 821 | |
05330448 AL |
822 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
823 | { | |
824 | lhs->selector = rhs->selector; | |
825 | lhs->base = rhs->base; | |
826 | lhs->limit = rhs->limit; | |
827 | lhs->type = 3; | |
828 | lhs->present = 1; | |
829 | lhs->dpl = 3; | |
830 | lhs->db = 0; | |
831 | lhs->s = 1; | |
832 | lhs->l = 0; | |
833 | lhs->g = 0; | |
834 | lhs->avl = 0; | |
835 | lhs->unusable = 0; | |
836 | } | |
837 | ||
838 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
839 | { | |
840 | unsigned flags = rhs->flags; | |
841 | lhs->selector = rhs->selector; | |
842 | lhs->base = rhs->base; | |
843 | lhs->limit = rhs->limit; | |
844 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
845 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 846 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
847 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
848 | lhs->s = (flags & DESC_S_MASK) != 0; | |
849 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
850 | lhs->g = (flags & DESC_G_MASK) != 0; | |
851 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
852 | lhs->unusable = 0; | |
7e680753 | 853 | lhs->padding = 0; |
05330448 AL |
854 | } |
855 | ||
856 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
857 | { | |
858 | lhs->selector = rhs->selector; | |
859 | lhs->base = rhs->base; | |
860 | lhs->limit = rhs->limit; | |
b9bec74b JK |
861 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
862 | (rhs->present * DESC_P_MASK) | | |
863 | (rhs->dpl << DESC_DPL_SHIFT) | | |
864 | (rhs->db << DESC_B_SHIFT) | | |
865 | (rhs->s * DESC_S_MASK) | | |
866 | (rhs->l << DESC_L_SHIFT) | | |
867 | (rhs->g * DESC_G_MASK) | | |
868 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
869 | } |
870 | ||
871 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
872 | { | |
b9bec74b | 873 | if (set) { |
05330448 | 874 | *kvm_reg = *qemu_reg; |
b9bec74b | 875 | } else { |
05330448 | 876 | *qemu_reg = *kvm_reg; |
b9bec74b | 877 | } |
05330448 AL |
878 | } |
879 | ||
1bc22652 | 880 | static int kvm_getput_regs(X86CPU *cpu, int set) |
05330448 | 881 | { |
1bc22652 | 882 | CPUX86State *env = &cpu->env; |
05330448 AL |
883 | struct kvm_regs regs; |
884 | int ret = 0; | |
885 | ||
886 | if (!set) { | |
1bc22652 | 887 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); |
b9bec74b | 888 | if (ret < 0) { |
05330448 | 889 | return ret; |
b9bec74b | 890 | } |
05330448 AL |
891 | } |
892 | ||
893 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
894 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
895 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
896 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
897 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
898 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
899 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
900 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
901 | #ifdef TARGET_X86_64 | |
902 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
903 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
904 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
905 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
906 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
907 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
908 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
909 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
910 | #endif | |
911 | ||
912 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
913 | kvm_getput_reg(®s.rip, &env->eip, set); | |
914 | ||
b9bec74b | 915 | if (set) { |
1bc22652 | 916 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); |
b9bec74b | 917 | } |
05330448 AL |
918 | |
919 | return ret; | |
920 | } | |
921 | ||
1bc22652 | 922 | static int kvm_put_fpu(X86CPU *cpu) |
05330448 | 923 | { |
1bc22652 | 924 | CPUX86State *env = &cpu->env; |
05330448 AL |
925 | struct kvm_fpu fpu; |
926 | int i; | |
927 | ||
928 | memset(&fpu, 0, sizeof fpu); | |
929 | fpu.fsw = env->fpus & ~(7 << 11); | |
930 | fpu.fsw |= (env->fpstt & 7) << 11; | |
931 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
932 | fpu.last_opcode = env->fpop; |
933 | fpu.last_ip = env->fpip; | |
934 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
935 | for (i = 0; i < 8; ++i) { |
936 | fpu.ftwx |= (!env->fptags[i]) << i; | |
937 | } | |
05330448 AL |
938 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
939 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
940 | fpu.mxcsr = env->mxcsr; | |
941 | ||
1bc22652 | 942 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); |
05330448 AL |
943 | } |
944 | ||
6b42494b JK |
945 | #define XSAVE_FCW_FSW 0 |
946 | #define XSAVE_FTW_FOP 1 | |
f1665b21 SY |
947 | #define XSAVE_CWD_RIP 2 |
948 | #define XSAVE_CWD_RDP 4 | |
949 | #define XSAVE_MXCSR 6 | |
950 | #define XSAVE_ST_SPACE 8 | |
951 | #define XSAVE_XMM_SPACE 40 | |
952 | #define XSAVE_XSTATE_BV 128 | |
953 | #define XSAVE_YMMH_SPACE 144 | |
f1665b21 | 954 | |
1bc22652 | 955 | static int kvm_put_xsave(X86CPU *cpu) |
f1665b21 | 956 | { |
1bc22652 | 957 | CPUX86State *env = &cpu->env; |
fabacc0f | 958 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
42cc8fa6 | 959 | uint16_t cwd, swd, twd; |
fabacc0f | 960 | int i, r; |
f1665b21 | 961 | |
b9bec74b | 962 | if (!kvm_has_xsave()) { |
1bc22652 | 963 | return kvm_put_fpu(cpu); |
b9bec74b | 964 | } |
f1665b21 | 965 | |
f1665b21 | 966 | memset(xsave, 0, sizeof(struct kvm_xsave)); |
6115c0a8 | 967 | twd = 0; |
f1665b21 SY |
968 | swd = env->fpus & ~(7 << 11); |
969 | swd |= (env->fpstt & 7) << 11; | |
970 | cwd = env->fpuc; | |
b9bec74b | 971 | for (i = 0; i < 8; ++i) { |
f1665b21 | 972 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 973 | } |
6b42494b JK |
974 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; |
975 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
42cc8fa6 JK |
976 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); |
977 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
978 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
979 | sizeof env->fpregs); | |
980 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
981 | sizeof env->xmm_regs); | |
982 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
983 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
984 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
985 | sizeof env->ymmh_regs); | |
1bc22652 | 986 | r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); |
0f53994f | 987 | return r; |
f1665b21 SY |
988 | } |
989 | ||
1bc22652 | 990 | static int kvm_put_xcrs(X86CPU *cpu) |
f1665b21 | 991 | { |
1bc22652 | 992 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
993 | struct kvm_xcrs xcrs; |
994 | ||
b9bec74b | 995 | if (!kvm_has_xcrs()) { |
f1665b21 | 996 | return 0; |
b9bec74b | 997 | } |
f1665b21 SY |
998 | |
999 | xcrs.nr_xcrs = 1; | |
1000 | xcrs.flags = 0; | |
1001 | xcrs.xcrs[0].xcr = 0; | |
1002 | xcrs.xcrs[0].value = env->xcr0; | |
1bc22652 | 1003 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); |
f1665b21 SY |
1004 | } |
1005 | ||
1bc22652 | 1006 | static int kvm_put_sregs(X86CPU *cpu) |
05330448 | 1007 | { |
1bc22652 | 1008 | CPUX86State *env = &cpu->env; |
05330448 AL |
1009 | struct kvm_sregs sregs; |
1010 | ||
0e607a80 JK |
1011 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
1012 | if (env->interrupt_injected >= 0) { | |
1013 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
1014 | (uint64_t)1 << (env->interrupt_injected % 64); | |
1015 | } | |
05330448 AL |
1016 | |
1017 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
1018 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
1019 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
1020 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
1021 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
1022 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
1023 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 1024 | } else { |
b9bec74b JK |
1025 | set_seg(&sregs.cs, &env->segs[R_CS]); |
1026 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
1027 | set_seg(&sregs.es, &env->segs[R_ES]); | |
1028 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
1029 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
1030 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
1031 | } |
1032 | ||
1033 | set_seg(&sregs.tr, &env->tr); | |
1034 | set_seg(&sregs.ldt, &env->ldt); | |
1035 | ||
1036 | sregs.idt.limit = env->idt.limit; | |
1037 | sregs.idt.base = env->idt.base; | |
7e680753 | 1038 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
1039 | sregs.gdt.limit = env->gdt.limit; |
1040 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 1041 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
1042 | |
1043 | sregs.cr0 = env->cr[0]; | |
1044 | sregs.cr2 = env->cr[2]; | |
1045 | sregs.cr3 = env->cr[3]; | |
1046 | sregs.cr4 = env->cr[4]; | |
1047 | ||
4a942cea BS |
1048 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
1049 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
1050 | |
1051 | sregs.efer = env->efer; | |
1052 | ||
1bc22652 | 1053 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); |
05330448 AL |
1054 | } |
1055 | ||
1056 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
1057 | uint32_t index, uint64_t value) | |
1058 | { | |
1059 | entry->index = index; | |
1060 | entry->data = value; | |
1061 | } | |
1062 | ||
1bc22652 | 1063 | static int kvm_put_msrs(X86CPU *cpu, int level) |
05330448 | 1064 | { |
1bc22652 | 1065 | CPUX86State *env = &cpu->env; |
05330448 AL |
1066 | struct { |
1067 | struct kvm_msrs info; | |
1068 | struct kvm_msr_entry entries[100]; | |
1069 | } msr_data; | |
1070 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 1071 | int n = 0; |
05330448 AL |
1072 | |
1073 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1074 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1075 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 1076 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 1077 | if (has_msr_star) { |
b9bec74b JK |
1078 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
1079 | } | |
c3a3a7d3 | 1080 | if (has_msr_hsave_pa) { |
75b10c43 | 1081 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 1082 | } |
f28558d3 WA |
1083 | if (has_msr_tsc_adjust) { |
1084 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); | |
1085 | } | |
aa82ba54 LJ |
1086 | if (has_msr_tsc_deadline) { |
1087 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
1088 | } | |
21e87c46 AK |
1089 | if (has_msr_misc_enable) { |
1090 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
1091 | env->msr_ia32_misc_enable); | |
1092 | } | |
05330448 | 1093 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1094 | if (lm_capable_kernel) { |
1095 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1096 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1097 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1098 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1099 | } | |
05330448 | 1100 | #endif |
ea643051 | 1101 | if (level == KVM_PUT_FULL_STATE) { |
384331a6 MT |
1102 | /* |
1103 | * KVM is yet unable to synchronize TSC values of multiple VCPUs on | |
1104 | * writeback. Until this is fixed, we only write the offset to SMP | |
1105 | * guests after migration, desynchronizing the VCPUs, but avoiding | |
1106 | * huge jump-backs that would occur without any writeback at all. | |
1107 | */ | |
1108 | if (smp_cpus == 1 || env->tsc != 0) { | |
1109 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
1110 | } | |
ff5c186b JK |
1111 | } |
1112 | /* | |
1113 | * The following paravirtual MSRs have side effects on the guest or are | |
1114 | * too heavy for normal writeback. Limit them to reset or full state | |
1115 | * updates. | |
1116 | */ | |
1117 | if (level >= KVM_PUT_RESET_STATE) { | |
ea643051 JK |
1118 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1119 | env->system_time_msr); | |
1120 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
1121 | if (has_msr_async_pf_en) { |
1122 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1123 | env->async_pf_en_msr); | |
1124 | } | |
bc9a839d MT |
1125 | if (has_msr_pv_eoi_en) { |
1126 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN, | |
1127 | env->pv_eoi_en_msr); | |
1128 | } | |
917367aa MT |
1129 | if (has_msr_kvm_steal_time) { |
1130 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME, | |
1131 | env->steal_time_msr); | |
1132 | } | |
92067bf4 | 1133 | if (hyperv_hypercall_available(cpu)) { |
eab70139 VR |
1134 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0); |
1135 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0); | |
1136 | } | |
92067bf4 | 1137 | if (cpu->hyperv_vapic) { |
eab70139 VR |
1138 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0); |
1139 | } | |
ea643051 | 1140 | } |
57780495 | 1141 | if (env->mcg_cap) { |
d8da8574 | 1142 | int i; |
b9bec74b | 1143 | |
c34d440a JK |
1144 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1145 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1146 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1147 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
1148 | } |
1149 | } | |
1a03675d | 1150 | |
05330448 AL |
1151 | msr_data.info.nmsrs = n; |
1152 | ||
1bc22652 | 1153 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); |
05330448 AL |
1154 | |
1155 | } | |
1156 | ||
1157 | ||
1bc22652 | 1158 | static int kvm_get_fpu(X86CPU *cpu) |
05330448 | 1159 | { |
1bc22652 | 1160 | CPUX86State *env = &cpu->env; |
05330448 AL |
1161 | struct kvm_fpu fpu; |
1162 | int i, ret; | |
1163 | ||
1bc22652 | 1164 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); |
b9bec74b | 1165 | if (ret < 0) { |
05330448 | 1166 | return ret; |
b9bec74b | 1167 | } |
05330448 AL |
1168 | |
1169 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1170 | env->fpus = fpu.fsw; | |
1171 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
1172 | env->fpop = fpu.last_opcode; |
1173 | env->fpip = fpu.last_ip; | |
1174 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
1175 | for (i = 0; i < 8; ++i) { |
1176 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1177 | } | |
05330448 AL |
1178 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
1179 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
1180 | env->mxcsr = fpu.mxcsr; | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
1bc22652 | 1185 | static int kvm_get_xsave(X86CPU *cpu) |
f1665b21 | 1186 | { |
1bc22652 | 1187 | CPUX86State *env = &cpu->env; |
fabacc0f | 1188 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
f1665b21 | 1189 | int ret, i; |
42cc8fa6 | 1190 | uint16_t cwd, swd, twd; |
f1665b21 | 1191 | |
b9bec74b | 1192 | if (!kvm_has_xsave()) { |
1bc22652 | 1193 | return kvm_get_fpu(cpu); |
b9bec74b | 1194 | } |
f1665b21 | 1195 | |
1bc22652 | 1196 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); |
0f53994f | 1197 | if (ret < 0) { |
f1665b21 | 1198 | return ret; |
0f53994f | 1199 | } |
f1665b21 | 1200 | |
6b42494b JK |
1201 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1202 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1203 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1204 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
f1665b21 SY |
1205 | env->fpstt = (swd >> 11) & 7; |
1206 | env->fpus = swd; | |
1207 | env->fpuc = cwd; | |
b9bec74b | 1208 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1209 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1210 | } |
42cc8fa6 JK |
1211 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1212 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1213 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1214 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1215 | sizeof env->fpregs); | |
1216 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1217 | sizeof env->xmm_regs); | |
1218 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1219 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1220 | sizeof env->ymmh_regs); | |
1221 | return 0; | |
f1665b21 SY |
1222 | } |
1223 | ||
1bc22652 | 1224 | static int kvm_get_xcrs(X86CPU *cpu) |
f1665b21 | 1225 | { |
1bc22652 | 1226 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1227 | int i, ret; |
1228 | struct kvm_xcrs xcrs; | |
1229 | ||
b9bec74b | 1230 | if (!kvm_has_xcrs()) { |
f1665b21 | 1231 | return 0; |
b9bec74b | 1232 | } |
f1665b21 | 1233 | |
1bc22652 | 1234 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); |
b9bec74b | 1235 | if (ret < 0) { |
f1665b21 | 1236 | return ret; |
b9bec74b | 1237 | } |
f1665b21 | 1238 | |
b9bec74b | 1239 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 SY |
1240 | /* Only support xcr0 now */ |
1241 | if (xcrs.xcrs[0].xcr == 0) { | |
1242 | env->xcr0 = xcrs.xcrs[0].value; | |
1243 | break; | |
1244 | } | |
b9bec74b | 1245 | } |
f1665b21 | 1246 | return 0; |
f1665b21 SY |
1247 | } |
1248 | ||
1bc22652 | 1249 | static int kvm_get_sregs(X86CPU *cpu) |
05330448 | 1250 | { |
1bc22652 | 1251 | CPUX86State *env = &cpu->env; |
05330448 AL |
1252 | struct kvm_sregs sregs; |
1253 | uint32_t hflags; | |
0e607a80 | 1254 | int bit, i, ret; |
05330448 | 1255 | |
1bc22652 | 1256 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); |
b9bec74b | 1257 | if (ret < 0) { |
05330448 | 1258 | return ret; |
b9bec74b | 1259 | } |
05330448 | 1260 | |
0e607a80 JK |
1261 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1262 | to find it and save its number instead (-1 for none). */ | |
1263 | env->interrupt_injected = -1; | |
1264 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1265 | if (sregs.interrupt_bitmap[i]) { | |
1266 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1267 | env->interrupt_injected = i * 64 + bit; | |
1268 | break; | |
1269 | } | |
1270 | } | |
05330448 AL |
1271 | |
1272 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1273 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1274 | get_seg(&env->segs[R_ES], &sregs.es); | |
1275 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1276 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1277 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1278 | ||
1279 | get_seg(&env->tr, &sregs.tr); | |
1280 | get_seg(&env->ldt, &sregs.ldt); | |
1281 | ||
1282 | env->idt.limit = sregs.idt.limit; | |
1283 | env->idt.base = sregs.idt.base; | |
1284 | env->gdt.limit = sregs.gdt.limit; | |
1285 | env->gdt.base = sregs.gdt.base; | |
1286 | ||
1287 | env->cr[0] = sregs.cr0; | |
1288 | env->cr[2] = sregs.cr2; | |
1289 | env->cr[3] = sregs.cr3; | |
1290 | env->cr[4] = sregs.cr4; | |
1291 | ||
05330448 | 1292 | env->efer = sregs.efer; |
cce47516 JK |
1293 | |
1294 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
05330448 | 1295 | |
b9bec74b JK |
1296 | #define HFLAG_COPY_MASK \ |
1297 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1298 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1299 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1300 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1301 | |
1302 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1303 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1304 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1305 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1306 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1307 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1308 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1309 | |
1310 | if (env->efer & MSR_EFER_LMA) { | |
1311 | hflags |= HF_LMA_MASK; | |
1312 | } | |
1313 | ||
1314 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1315 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1316 | } else { | |
1317 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1318 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1319 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1320 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1321 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1322 | !(hflags & HF_CS32_MASK)) { | |
1323 | hflags |= HF_ADDSEG_MASK; | |
1324 | } else { | |
1325 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1326 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1327 | } | |
05330448 AL |
1328 | } |
1329 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1330 | |
1331 | return 0; | |
1332 | } | |
1333 | ||
1bc22652 | 1334 | static int kvm_get_msrs(X86CPU *cpu) |
05330448 | 1335 | { |
1bc22652 | 1336 | CPUX86State *env = &cpu->env; |
05330448 AL |
1337 | struct { |
1338 | struct kvm_msrs info; | |
1339 | struct kvm_msr_entry entries[100]; | |
1340 | } msr_data; | |
1341 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1342 | int ret, i, n; | |
1343 | ||
1344 | n = 0; | |
1345 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1346 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1347 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1348 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1349 | if (has_msr_star) { |
b9bec74b JK |
1350 | msrs[n++].index = MSR_STAR; |
1351 | } | |
c3a3a7d3 | 1352 | if (has_msr_hsave_pa) { |
75b10c43 | 1353 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1354 | } |
f28558d3 WA |
1355 | if (has_msr_tsc_adjust) { |
1356 | msrs[n++].index = MSR_TSC_ADJUST; | |
1357 | } | |
aa82ba54 LJ |
1358 | if (has_msr_tsc_deadline) { |
1359 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1360 | } | |
21e87c46 AK |
1361 | if (has_msr_misc_enable) { |
1362 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1363 | } | |
b8cc45d6 GC |
1364 | |
1365 | if (!env->tsc_valid) { | |
1366 | msrs[n++].index = MSR_IA32_TSC; | |
1354869c | 1367 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
1368 | } |
1369 | ||
05330448 | 1370 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1371 | if (lm_capable_kernel) { |
1372 | msrs[n++].index = MSR_CSTAR; | |
1373 | msrs[n++].index = MSR_KERNELGSBASE; | |
1374 | msrs[n++].index = MSR_FMASK; | |
1375 | msrs[n++].index = MSR_LSTAR; | |
1376 | } | |
05330448 | 1377 | #endif |
1a03675d GC |
1378 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1379 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1380 | if (has_msr_async_pf_en) { |
1381 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1382 | } | |
bc9a839d MT |
1383 | if (has_msr_pv_eoi_en) { |
1384 | msrs[n++].index = MSR_KVM_PV_EOI_EN; | |
1385 | } | |
917367aa MT |
1386 | if (has_msr_kvm_steal_time) { |
1387 | msrs[n++].index = MSR_KVM_STEAL_TIME; | |
1388 | } | |
1a03675d | 1389 | |
57780495 MT |
1390 | if (env->mcg_cap) { |
1391 | msrs[n++].index = MSR_MCG_STATUS; | |
1392 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1393 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1394 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1395 | } |
57780495 | 1396 | } |
57780495 | 1397 | |
05330448 | 1398 | msr_data.info.nmsrs = n; |
1bc22652 | 1399 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); |
b9bec74b | 1400 | if (ret < 0) { |
05330448 | 1401 | return ret; |
b9bec74b | 1402 | } |
05330448 AL |
1403 | |
1404 | for (i = 0; i < ret; i++) { | |
1405 | switch (msrs[i].index) { | |
1406 | case MSR_IA32_SYSENTER_CS: | |
1407 | env->sysenter_cs = msrs[i].data; | |
1408 | break; | |
1409 | case MSR_IA32_SYSENTER_ESP: | |
1410 | env->sysenter_esp = msrs[i].data; | |
1411 | break; | |
1412 | case MSR_IA32_SYSENTER_EIP: | |
1413 | env->sysenter_eip = msrs[i].data; | |
1414 | break; | |
0c03266a JK |
1415 | case MSR_PAT: |
1416 | env->pat = msrs[i].data; | |
1417 | break; | |
05330448 AL |
1418 | case MSR_STAR: |
1419 | env->star = msrs[i].data; | |
1420 | break; | |
1421 | #ifdef TARGET_X86_64 | |
1422 | case MSR_CSTAR: | |
1423 | env->cstar = msrs[i].data; | |
1424 | break; | |
1425 | case MSR_KERNELGSBASE: | |
1426 | env->kernelgsbase = msrs[i].data; | |
1427 | break; | |
1428 | case MSR_FMASK: | |
1429 | env->fmask = msrs[i].data; | |
1430 | break; | |
1431 | case MSR_LSTAR: | |
1432 | env->lstar = msrs[i].data; | |
1433 | break; | |
1434 | #endif | |
1435 | case MSR_IA32_TSC: | |
1436 | env->tsc = msrs[i].data; | |
1437 | break; | |
f28558d3 WA |
1438 | case MSR_TSC_ADJUST: |
1439 | env->tsc_adjust = msrs[i].data; | |
1440 | break; | |
aa82ba54 LJ |
1441 | case MSR_IA32_TSCDEADLINE: |
1442 | env->tsc_deadline = msrs[i].data; | |
1443 | break; | |
aa851e36 MT |
1444 | case MSR_VM_HSAVE_PA: |
1445 | env->vm_hsave = msrs[i].data; | |
1446 | break; | |
1a03675d GC |
1447 | case MSR_KVM_SYSTEM_TIME: |
1448 | env->system_time_msr = msrs[i].data; | |
1449 | break; | |
1450 | case MSR_KVM_WALL_CLOCK: | |
1451 | env->wall_clock_msr = msrs[i].data; | |
1452 | break; | |
57780495 MT |
1453 | case MSR_MCG_STATUS: |
1454 | env->mcg_status = msrs[i].data; | |
1455 | break; | |
1456 | case MSR_MCG_CTL: | |
1457 | env->mcg_ctl = msrs[i].data; | |
1458 | break; | |
21e87c46 AK |
1459 | case MSR_IA32_MISC_ENABLE: |
1460 | env->msr_ia32_misc_enable = msrs[i].data; | |
1461 | break; | |
57780495 | 1462 | default: |
57780495 MT |
1463 | if (msrs[i].index >= MSR_MC0_CTL && |
1464 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1465 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 1466 | } |
d8da8574 | 1467 | break; |
f6584ee2 GN |
1468 | case MSR_KVM_ASYNC_PF_EN: |
1469 | env->async_pf_en_msr = msrs[i].data; | |
1470 | break; | |
bc9a839d MT |
1471 | case MSR_KVM_PV_EOI_EN: |
1472 | env->pv_eoi_en_msr = msrs[i].data; | |
1473 | break; | |
917367aa MT |
1474 | case MSR_KVM_STEAL_TIME: |
1475 | env->steal_time_msr = msrs[i].data; | |
1476 | break; | |
05330448 AL |
1477 | } |
1478 | } | |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | ||
1bc22652 | 1483 | static int kvm_put_mp_state(X86CPU *cpu) |
9bdbe550 | 1484 | { |
1bc22652 | 1485 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; |
9bdbe550 | 1486 | |
1bc22652 | 1487 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); |
9bdbe550 HB |
1488 | } |
1489 | ||
23d02d9b | 1490 | static int kvm_get_mp_state(X86CPU *cpu) |
9bdbe550 | 1491 | { |
259186a7 | 1492 | CPUState *cs = CPU(cpu); |
23d02d9b | 1493 | CPUX86State *env = &cpu->env; |
9bdbe550 HB |
1494 | struct kvm_mp_state mp_state; |
1495 | int ret; | |
1496 | ||
259186a7 | 1497 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); |
9bdbe550 HB |
1498 | if (ret < 0) { |
1499 | return ret; | |
1500 | } | |
1501 | env->mp_state = mp_state.mp_state; | |
c14750e8 | 1502 | if (kvm_irqchip_in_kernel()) { |
259186a7 | 1503 | cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
c14750e8 | 1504 | } |
9bdbe550 HB |
1505 | return 0; |
1506 | } | |
1507 | ||
1bc22652 | 1508 | static int kvm_get_apic(X86CPU *cpu) |
680c1c6f | 1509 | { |
1bc22652 | 1510 | CPUX86State *env = &cpu->env; |
680c1c6f JK |
1511 | DeviceState *apic = env->apic_state; |
1512 | struct kvm_lapic_state kapic; | |
1513 | int ret; | |
1514 | ||
3d4b2649 | 1515 | if (apic && kvm_irqchip_in_kernel()) { |
1bc22652 | 1516 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); |
680c1c6f JK |
1517 | if (ret < 0) { |
1518 | return ret; | |
1519 | } | |
1520 | ||
1521 | kvm_get_apic_state(apic, &kapic); | |
1522 | } | |
1523 | return 0; | |
1524 | } | |
1525 | ||
1bc22652 | 1526 | static int kvm_put_apic(X86CPU *cpu) |
680c1c6f | 1527 | { |
1bc22652 | 1528 | CPUX86State *env = &cpu->env; |
680c1c6f JK |
1529 | DeviceState *apic = env->apic_state; |
1530 | struct kvm_lapic_state kapic; | |
1531 | ||
3d4b2649 | 1532 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
1533 | kvm_put_apic_state(apic, &kapic); |
1534 | ||
1bc22652 | 1535 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic); |
680c1c6f JK |
1536 | } |
1537 | return 0; | |
1538 | } | |
1539 | ||
1bc22652 | 1540 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) |
a0fb002c | 1541 | { |
1bc22652 | 1542 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1543 | struct kvm_vcpu_events events; |
1544 | ||
1545 | if (!kvm_has_vcpu_events()) { | |
1546 | return 0; | |
1547 | } | |
1548 | ||
31827373 JK |
1549 | events.exception.injected = (env->exception_injected >= 0); |
1550 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1551 | events.exception.has_error_code = env->has_error_code; |
1552 | events.exception.error_code = env->error_code; | |
7e680753 | 1553 | events.exception.pad = 0; |
a0fb002c JK |
1554 | |
1555 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1556 | events.interrupt.nr = env->interrupt_injected; | |
1557 | events.interrupt.soft = env->soft_interrupt; | |
1558 | ||
1559 | events.nmi.injected = env->nmi_injected; | |
1560 | events.nmi.pending = env->nmi_pending; | |
1561 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
7e680753 | 1562 | events.nmi.pad = 0; |
a0fb002c JK |
1563 | |
1564 | events.sipi_vector = env->sipi_vector; | |
1565 | ||
ea643051 JK |
1566 | events.flags = 0; |
1567 | if (level >= KVM_PUT_RESET_STATE) { | |
1568 | events.flags |= | |
1569 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1570 | } | |
aee028b9 | 1571 | |
1bc22652 | 1572 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
1573 | } |
1574 | ||
1bc22652 | 1575 | static int kvm_get_vcpu_events(X86CPU *cpu) |
a0fb002c | 1576 | { |
1bc22652 | 1577 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1578 | struct kvm_vcpu_events events; |
1579 | int ret; | |
1580 | ||
1581 | if (!kvm_has_vcpu_events()) { | |
1582 | return 0; | |
1583 | } | |
1584 | ||
1bc22652 | 1585 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); |
a0fb002c JK |
1586 | if (ret < 0) { |
1587 | return ret; | |
1588 | } | |
31827373 | 1589 | env->exception_injected = |
a0fb002c JK |
1590 | events.exception.injected ? events.exception.nr : -1; |
1591 | env->has_error_code = events.exception.has_error_code; | |
1592 | env->error_code = events.exception.error_code; | |
1593 | ||
1594 | env->interrupt_injected = | |
1595 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1596 | env->soft_interrupt = events.interrupt.soft; | |
1597 | ||
1598 | env->nmi_injected = events.nmi.injected; | |
1599 | env->nmi_pending = events.nmi.pending; | |
1600 | if (events.nmi.masked) { | |
1601 | env->hflags2 |= HF2_NMI_MASK; | |
1602 | } else { | |
1603 | env->hflags2 &= ~HF2_NMI_MASK; | |
1604 | } | |
1605 | ||
1606 | env->sipi_vector = events.sipi_vector; | |
a0fb002c JK |
1607 | |
1608 | return 0; | |
1609 | } | |
1610 | ||
1bc22652 | 1611 | static int kvm_guest_debug_workarounds(X86CPU *cpu) |
b0b1d690 | 1612 | { |
ed2803da | 1613 | CPUState *cs = CPU(cpu); |
1bc22652 | 1614 | CPUX86State *env = &cpu->env; |
b0b1d690 | 1615 | int ret = 0; |
b0b1d690 JK |
1616 | unsigned long reinject_trap = 0; |
1617 | ||
1618 | if (!kvm_has_vcpu_events()) { | |
1619 | if (env->exception_injected == 1) { | |
1620 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1621 | } else if (env->exception_injected == 3) { | |
1622 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1623 | } | |
1624 | env->exception_injected = -1; | |
1625 | } | |
1626 | ||
1627 | /* | |
1628 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1629 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1630 | * by updating the debug state once again if single-stepping is on. | |
1631 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1632 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1633 | * reinject them via SET_GUEST_DEBUG. | |
1634 | */ | |
1635 | if (reinject_trap || | |
ed2803da | 1636 | (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { |
38e478ec | 1637 | ret = kvm_update_guest_debug(cs, reinject_trap); |
b0b1d690 | 1638 | } |
b0b1d690 JK |
1639 | return ret; |
1640 | } | |
1641 | ||
1bc22652 | 1642 | static int kvm_put_debugregs(X86CPU *cpu) |
ff44f1a3 | 1643 | { |
1bc22652 | 1644 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1645 | struct kvm_debugregs dbgregs; |
1646 | int i; | |
1647 | ||
1648 | if (!kvm_has_debugregs()) { | |
1649 | return 0; | |
1650 | } | |
1651 | ||
1652 | for (i = 0; i < 4; i++) { | |
1653 | dbgregs.db[i] = env->dr[i]; | |
1654 | } | |
1655 | dbgregs.dr6 = env->dr[6]; | |
1656 | dbgregs.dr7 = env->dr[7]; | |
1657 | dbgregs.flags = 0; | |
1658 | ||
1bc22652 | 1659 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); |
ff44f1a3 JK |
1660 | } |
1661 | ||
1bc22652 | 1662 | static int kvm_get_debugregs(X86CPU *cpu) |
ff44f1a3 | 1663 | { |
1bc22652 | 1664 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1665 | struct kvm_debugregs dbgregs; |
1666 | int i, ret; | |
1667 | ||
1668 | if (!kvm_has_debugregs()) { | |
1669 | return 0; | |
1670 | } | |
1671 | ||
1bc22652 | 1672 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); |
ff44f1a3 | 1673 | if (ret < 0) { |
b9bec74b | 1674 | return ret; |
ff44f1a3 JK |
1675 | } |
1676 | for (i = 0; i < 4; i++) { | |
1677 | env->dr[i] = dbgregs.db[i]; | |
1678 | } | |
1679 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1680 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
1681 | |
1682 | return 0; | |
1683 | } | |
1684 | ||
20d695a9 | 1685 | int kvm_arch_put_registers(CPUState *cpu, int level) |
05330448 | 1686 | { |
20d695a9 | 1687 | X86CPU *x86_cpu = X86_CPU(cpu); |
05330448 AL |
1688 | int ret; |
1689 | ||
2fa45344 | 1690 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); |
dbaa07c4 | 1691 | |
1bc22652 | 1692 | ret = kvm_getput_regs(x86_cpu, 1); |
b9bec74b | 1693 | if (ret < 0) { |
05330448 | 1694 | return ret; |
b9bec74b | 1695 | } |
1bc22652 | 1696 | ret = kvm_put_xsave(x86_cpu); |
b9bec74b | 1697 | if (ret < 0) { |
f1665b21 | 1698 | return ret; |
b9bec74b | 1699 | } |
1bc22652 | 1700 | ret = kvm_put_xcrs(x86_cpu); |
b9bec74b | 1701 | if (ret < 0) { |
05330448 | 1702 | return ret; |
b9bec74b | 1703 | } |
1bc22652 | 1704 | ret = kvm_put_sregs(x86_cpu); |
b9bec74b | 1705 | if (ret < 0) { |
05330448 | 1706 | return ret; |
b9bec74b | 1707 | } |
ab443475 | 1708 | /* must be before kvm_put_msrs */ |
1bc22652 | 1709 | ret = kvm_inject_mce_oldstyle(x86_cpu); |
ab443475 JK |
1710 | if (ret < 0) { |
1711 | return ret; | |
1712 | } | |
1bc22652 | 1713 | ret = kvm_put_msrs(x86_cpu, level); |
b9bec74b | 1714 | if (ret < 0) { |
05330448 | 1715 | return ret; |
b9bec74b | 1716 | } |
ea643051 | 1717 | if (level >= KVM_PUT_RESET_STATE) { |
1bc22652 | 1718 | ret = kvm_put_mp_state(x86_cpu); |
b9bec74b | 1719 | if (ret < 0) { |
ea643051 | 1720 | return ret; |
b9bec74b | 1721 | } |
1bc22652 | 1722 | ret = kvm_put_apic(x86_cpu); |
680c1c6f JK |
1723 | if (ret < 0) { |
1724 | return ret; | |
1725 | } | |
ea643051 | 1726 | } |
1bc22652 | 1727 | ret = kvm_put_vcpu_events(x86_cpu, level); |
b9bec74b | 1728 | if (ret < 0) { |
a0fb002c | 1729 | return ret; |
b9bec74b | 1730 | } |
1bc22652 | 1731 | ret = kvm_put_debugregs(x86_cpu); |
b9bec74b | 1732 | if (ret < 0) { |
b0b1d690 | 1733 | return ret; |
b9bec74b | 1734 | } |
b0b1d690 | 1735 | /* must be last */ |
1bc22652 | 1736 | ret = kvm_guest_debug_workarounds(x86_cpu); |
b9bec74b | 1737 | if (ret < 0) { |
ff44f1a3 | 1738 | return ret; |
b9bec74b | 1739 | } |
05330448 AL |
1740 | return 0; |
1741 | } | |
1742 | ||
20d695a9 | 1743 | int kvm_arch_get_registers(CPUState *cs) |
05330448 | 1744 | { |
20d695a9 | 1745 | X86CPU *cpu = X86_CPU(cs); |
05330448 AL |
1746 | int ret; |
1747 | ||
20d695a9 | 1748 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); |
dbaa07c4 | 1749 | |
1bc22652 | 1750 | ret = kvm_getput_regs(cpu, 0); |
b9bec74b | 1751 | if (ret < 0) { |
05330448 | 1752 | return ret; |
b9bec74b | 1753 | } |
1bc22652 | 1754 | ret = kvm_get_xsave(cpu); |
b9bec74b | 1755 | if (ret < 0) { |
f1665b21 | 1756 | return ret; |
b9bec74b | 1757 | } |
1bc22652 | 1758 | ret = kvm_get_xcrs(cpu); |
b9bec74b | 1759 | if (ret < 0) { |
05330448 | 1760 | return ret; |
b9bec74b | 1761 | } |
1bc22652 | 1762 | ret = kvm_get_sregs(cpu); |
b9bec74b | 1763 | if (ret < 0) { |
05330448 | 1764 | return ret; |
b9bec74b | 1765 | } |
1bc22652 | 1766 | ret = kvm_get_msrs(cpu); |
b9bec74b | 1767 | if (ret < 0) { |
05330448 | 1768 | return ret; |
b9bec74b | 1769 | } |
23d02d9b | 1770 | ret = kvm_get_mp_state(cpu); |
b9bec74b | 1771 | if (ret < 0) { |
5a2e3c2e | 1772 | return ret; |
b9bec74b | 1773 | } |
1bc22652 | 1774 | ret = kvm_get_apic(cpu); |
680c1c6f JK |
1775 | if (ret < 0) { |
1776 | return ret; | |
1777 | } | |
1bc22652 | 1778 | ret = kvm_get_vcpu_events(cpu); |
b9bec74b | 1779 | if (ret < 0) { |
a0fb002c | 1780 | return ret; |
b9bec74b | 1781 | } |
1bc22652 | 1782 | ret = kvm_get_debugregs(cpu); |
b9bec74b | 1783 | if (ret < 0) { |
ff44f1a3 | 1784 | return ret; |
b9bec74b | 1785 | } |
05330448 AL |
1786 | return 0; |
1787 | } | |
1788 | ||
20d695a9 | 1789 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 1790 | { |
20d695a9 AF |
1791 | X86CPU *x86_cpu = X86_CPU(cpu); |
1792 | CPUX86State *env = &x86_cpu->env; | |
ce377af3 JK |
1793 | int ret; |
1794 | ||
276ce815 | 1795 | /* Inject NMI */ |
259186a7 AF |
1796 | if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { |
1797 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
276ce815 | 1798 | DPRINTF("injected NMI\n"); |
1bc22652 | 1799 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); |
ce377af3 JK |
1800 | if (ret < 0) { |
1801 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
1802 | strerror(-ret)); | |
1803 | } | |
276ce815 LJ |
1804 | } |
1805 | ||
db1669bc | 1806 | if (!kvm_irqchip_in_kernel()) { |
d362e757 JK |
1807 | /* Force the VCPU out of its inner loop to process any INIT requests |
1808 | * or pending TPR access reports. */ | |
259186a7 | 1809 | if (cpu->interrupt_request & |
d362e757 | 1810 | (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { |
fcd7d003 | 1811 | cpu->exit_request = 1; |
05330448 | 1812 | } |
05330448 | 1813 | |
db1669bc JK |
1814 | /* Try to inject an interrupt if the guest can accept it */ |
1815 | if (run->ready_for_interrupt_injection && | |
259186a7 | 1816 | (cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
db1669bc JK |
1817 | (env->eflags & IF_MASK)) { |
1818 | int irq; | |
1819 | ||
259186a7 | 1820 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; |
db1669bc JK |
1821 | irq = cpu_get_pic_interrupt(env); |
1822 | if (irq >= 0) { | |
1823 | struct kvm_interrupt intr; | |
1824 | ||
1825 | intr.irq = irq; | |
db1669bc | 1826 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 1827 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); |
ce377af3 JK |
1828 | if (ret < 0) { |
1829 | fprintf(stderr, | |
1830 | "KVM: injection failed, interrupt lost (%s)\n", | |
1831 | strerror(-ret)); | |
1832 | } | |
db1669bc JK |
1833 | } |
1834 | } | |
05330448 | 1835 | |
db1669bc JK |
1836 | /* If we have an interrupt but the guest is not ready to receive an |
1837 | * interrupt, request an interrupt window exit. This will | |
1838 | * cause a return to userspace as soon as the guest is ready to | |
1839 | * receive interrupts. */ | |
259186a7 | 1840 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { |
db1669bc JK |
1841 | run->request_interrupt_window = 1; |
1842 | } else { | |
1843 | run->request_interrupt_window = 0; | |
1844 | } | |
1845 | ||
1846 | DPRINTF("setting tpr\n"); | |
1847 | run->cr8 = cpu_get_apic_tpr(env->apic_state); | |
1848 | } | |
05330448 AL |
1849 | } |
1850 | ||
20d695a9 | 1851 | void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 1852 | { |
20d695a9 AF |
1853 | X86CPU *x86_cpu = X86_CPU(cpu); |
1854 | CPUX86State *env = &x86_cpu->env; | |
1855 | ||
b9bec74b | 1856 | if (run->if_flag) { |
05330448 | 1857 | env->eflags |= IF_MASK; |
b9bec74b | 1858 | } else { |
05330448 | 1859 | env->eflags &= ~IF_MASK; |
b9bec74b | 1860 | } |
4a942cea BS |
1861 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1862 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1863 | } |
1864 | ||
20d695a9 | 1865 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 1866 | { |
20d695a9 AF |
1867 | X86CPU *cpu = X86_CPU(cs); |
1868 | CPUX86State *env = &cpu->env; | |
232fc23b | 1869 | |
259186a7 | 1870 | if (cs->interrupt_request & CPU_INTERRUPT_MCE) { |
ab443475 JK |
1871 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ |
1872 | assert(env->mcg_cap); | |
1873 | ||
259186a7 | 1874 | cs->interrupt_request &= ~CPU_INTERRUPT_MCE; |
ab443475 | 1875 | |
dd1750d7 | 1876 | kvm_cpu_synchronize_state(cs); |
ab443475 JK |
1877 | |
1878 | if (env->exception_injected == EXCP08_DBLE) { | |
1879 | /* this means triple fault */ | |
1880 | qemu_system_reset_request(); | |
fcd7d003 | 1881 | cs->exit_request = 1; |
ab443475 JK |
1882 | return 0; |
1883 | } | |
1884 | env->exception_injected = EXCP12_MCHK; | |
1885 | env->has_error_code = 0; | |
1886 | ||
259186a7 | 1887 | cs->halted = 0; |
ab443475 JK |
1888 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { |
1889 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
1890 | } | |
1891 | } | |
1892 | ||
db1669bc JK |
1893 | if (kvm_irqchip_in_kernel()) { |
1894 | return 0; | |
1895 | } | |
1896 | ||
259186a7 AF |
1897 | if (cs->interrupt_request & CPU_INTERRUPT_POLL) { |
1898 | cs->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
5d62c43a JK |
1899 | apic_poll_irq(env->apic_state); |
1900 | } | |
259186a7 | 1901 | if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
4601f7b0 | 1902 | (env->eflags & IF_MASK)) || |
259186a7 AF |
1903 | (cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
1904 | cs->halted = 0; | |
6792a57b | 1905 | } |
259186a7 | 1906 | if (cs->interrupt_request & CPU_INTERRUPT_INIT) { |
dd1750d7 | 1907 | kvm_cpu_synchronize_state(cs); |
232fc23b | 1908 | do_cpu_init(cpu); |
0af691d7 | 1909 | } |
259186a7 | 1910 | if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { |
dd1750d7 | 1911 | kvm_cpu_synchronize_state(cs); |
232fc23b | 1912 | do_cpu_sipi(cpu); |
0af691d7 | 1913 | } |
259186a7 AF |
1914 | if (cs->interrupt_request & CPU_INTERRUPT_TPR) { |
1915 | cs->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
dd1750d7 | 1916 | kvm_cpu_synchronize_state(cs); |
d362e757 JK |
1917 | apic_handle_tpr_access_report(env->apic_state, env->eip, |
1918 | env->tpr_access_type); | |
1919 | } | |
0af691d7 | 1920 | |
259186a7 | 1921 | return cs->halted; |
0af691d7 MT |
1922 | } |
1923 | ||
839b5630 | 1924 | static int kvm_handle_halt(X86CPU *cpu) |
05330448 | 1925 | { |
259186a7 | 1926 | CPUState *cs = CPU(cpu); |
839b5630 AF |
1927 | CPUX86State *env = &cpu->env; |
1928 | ||
259186a7 | 1929 | if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
05330448 | 1930 | (env->eflags & IF_MASK)) && |
259186a7 AF |
1931 | !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
1932 | cs->halted = 1; | |
bb4ea393 | 1933 | return EXCP_HLT; |
05330448 AL |
1934 | } |
1935 | ||
bb4ea393 | 1936 | return 0; |
05330448 AL |
1937 | } |
1938 | ||
f7575c96 | 1939 | static int kvm_handle_tpr_access(X86CPU *cpu) |
d362e757 | 1940 | { |
f7575c96 AF |
1941 | CPUX86State *env = &cpu->env; |
1942 | CPUState *cs = CPU(cpu); | |
1943 | struct kvm_run *run = cs->kvm_run; | |
d362e757 JK |
1944 | |
1945 | apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip, | |
1946 | run->tpr_access.is_write ? TPR_ACCESS_WRITE | |
1947 | : TPR_ACCESS_READ); | |
1948 | return 1; | |
1949 | } | |
1950 | ||
f17ec444 | 1951 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 1952 | { |
38972938 | 1953 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1954 | |
f17ec444 AF |
1955 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
1956 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
e22a25c9 | 1957 | return -EINVAL; |
b9bec74b | 1958 | } |
e22a25c9 AL |
1959 | return 0; |
1960 | } | |
1961 | ||
f17ec444 | 1962 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 AL |
1963 | { |
1964 | uint8_t int3; | |
1965 | ||
f17ec444 AF |
1966 | if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
1967 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
e22a25c9 | 1968 | return -EINVAL; |
b9bec74b | 1969 | } |
e22a25c9 AL |
1970 | return 0; |
1971 | } | |
1972 | ||
1973 | static struct { | |
1974 | target_ulong addr; | |
1975 | int len; | |
1976 | int type; | |
1977 | } hw_breakpoint[4]; | |
1978 | ||
1979 | static int nb_hw_breakpoint; | |
1980 | ||
1981 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1982 | { | |
1983 | int n; | |
1984 | ||
b9bec74b | 1985 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 1986 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 1987 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 1988 | return n; |
b9bec74b JK |
1989 | } |
1990 | } | |
e22a25c9 AL |
1991 | return -1; |
1992 | } | |
1993 | ||
1994 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1995 | target_ulong len, int type) | |
1996 | { | |
1997 | switch (type) { | |
1998 | case GDB_BREAKPOINT_HW: | |
1999 | len = 1; | |
2000 | break; | |
2001 | case GDB_WATCHPOINT_WRITE: | |
2002 | case GDB_WATCHPOINT_ACCESS: | |
2003 | switch (len) { | |
2004 | case 1: | |
2005 | break; | |
2006 | case 2: | |
2007 | case 4: | |
2008 | case 8: | |
b9bec74b | 2009 | if (addr & (len - 1)) { |
e22a25c9 | 2010 | return -EINVAL; |
b9bec74b | 2011 | } |
e22a25c9 AL |
2012 | break; |
2013 | default: | |
2014 | return -EINVAL; | |
2015 | } | |
2016 | break; | |
2017 | default: | |
2018 | return -ENOSYS; | |
2019 | } | |
2020 | ||
b9bec74b | 2021 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 2022 | return -ENOBUFS; |
b9bec74b JK |
2023 | } |
2024 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 2025 | return -EEXIST; |
b9bec74b | 2026 | } |
e22a25c9 AL |
2027 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
2028 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
2029 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
2030 | nb_hw_breakpoint++; | |
2031 | ||
2032 | return 0; | |
2033 | } | |
2034 | ||
2035 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
2036 | target_ulong len, int type) | |
2037 | { | |
2038 | int n; | |
2039 | ||
2040 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 2041 | if (n < 0) { |
e22a25c9 | 2042 | return -ENOENT; |
b9bec74b | 2043 | } |
e22a25c9 AL |
2044 | nb_hw_breakpoint--; |
2045 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
2046 | ||
2047 | return 0; | |
2048 | } | |
2049 | ||
2050 | void kvm_arch_remove_all_hw_breakpoints(void) | |
2051 | { | |
2052 | nb_hw_breakpoint = 0; | |
2053 | } | |
2054 | ||
2055 | static CPUWatchpoint hw_watchpoint; | |
2056 | ||
a60f24b5 | 2057 | static int kvm_handle_debug(X86CPU *cpu, |
48405526 | 2058 | struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 2059 | { |
ed2803da | 2060 | CPUState *cs = CPU(cpu); |
a60f24b5 | 2061 | CPUX86State *env = &cpu->env; |
f2574737 | 2062 | int ret = 0; |
e22a25c9 AL |
2063 | int n; |
2064 | ||
2065 | if (arch_info->exception == 1) { | |
2066 | if (arch_info->dr6 & (1 << 14)) { | |
ed2803da | 2067 | if (cs->singlestep_enabled) { |
f2574737 | 2068 | ret = EXCP_DEBUG; |
b9bec74b | 2069 | } |
e22a25c9 | 2070 | } else { |
b9bec74b JK |
2071 | for (n = 0; n < 4; n++) { |
2072 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
2073 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
2074 | case 0x0: | |
f2574737 | 2075 | ret = EXCP_DEBUG; |
e22a25c9 AL |
2076 | break; |
2077 | case 0x1: | |
f2574737 | 2078 | ret = EXCP_DEBUG; |
48405526 | 2079 | env->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2080 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2081 | hw_watchpoint.flags = BP_MEM_WRITE; | |
2082 | break; | |
2083 | case 0x3: | |
f2574737 | 2084 | ret = EXCP_DEBUG; |
48405526 | 2085 | env->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2086 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2087 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
2088 | break; | |
2089 | } | |
b9bec74b JK |
2090 | } |
2091 | } | |
e22a25c9 | 2092 | } |
a60f24b5 | 2093 | } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) { |
f2574737 | 2094 | ret = EXCP_DEBUG; |
b9bec74b | 2095 | } |
f2574737 | 2096 | if (ret == 0) { |
cb446eca | 2097 | cpu_synchronize_state(CPU(cpu)); |
48405526 | 2098 | assert(env->exception_injected == -1); |
b0b1d690 | 2099 | |
f2574737 | 2100 | /* pass to guest */ |
48405526 BS |
2101 | env->exception_injected = arch_info->exception; |
2102 | env->has_error_code = 0; | |
b0b1d690 | 2103 | } |
e22a25c9 | 2104 | |
f2574737 | 2105 | return ret; |
e22a25c9 AL |
2106 | } |
2107 | ||
20d695a9 | 2108 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
2109 | { |
2110 | const uint8_t type_code[] = { | |
2111 | [GDB_BREAKPOINT_HW] = 0x0, | |
2112 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
2113 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
2114 | }; | |
2115 | const uint8_t len_code[] = { | |
2116 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
2117 | }; | |
2118 | int n; | |
2119 | ||
a60f24b5 | 2120 | if (kvm_sw_breakpoints_active(cpu)) { |
e22a25c9 | 2121 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 2122 | } |
e22a25c9 AL |
2123 | if (nb_hw_breakpoint > 0) { |
2124 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
2125 | dbg->arch.debugreg[7] = 0x0600; | |
2126 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
2127 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
2128 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
2129 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 2130 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
2131 | } |
2132 | } | |
2133 | } | |
4513d923 | 2134 | |
2a4dac83 JK |
2135 | static bool host_supports_vmx(void) |
2136 | { | |
2137 | uint32_t ecx, unused; | |
2138 | ||
2139 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
2140 | return ecx & CPUID_EXT_VMX; | |
2141 | } | |
2142 | ||
2143 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
2144 | ||
20d695a9 | 2145 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
2a4dac83 | 2146 | { |
20d695a9 | 2147 | X86CPU *cpu = X86_CPU(cs); |
2a4dac83 JK |
2148 | uint64_t code; |
2149 | int ret; | |
2150 | ||
2151 | switch (run->exit_reason) { | |
2152 | case KVM_EXIT_HLT: | |
2153 | DPRINTF("handle_hlt\n"); | |
839b5630 | 2154 | ret = kvm_handle_halt(cpu); |
2a4dac83 JK |
2155 | break; |
2156 | case KVM_EXIT_SET_TPR: | |
2157 | ret = 0; | |
2158 | break; | |
d362e757 | 2159 | case KVM_EXIT_TPR_ACCESS: |
f7575c96 | 2160 | ret = kvm_handle_tpr_access(cpu); |
d362e757 | 2161 | break; |
2a4dac83 JK |
2162 | case KVM_EXIT_FAIL_ENTRY: |
2163 | code = run->fail_entry.hardware_entry_failure_reason; | |
2164 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
2165 | code); | |
2166 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
2167 | fprintf(stderr, | |
12619721 | 2168 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
2169 | "unrestricted mode\n" |
2170 | "support, the failure can be most likely due to the guest " | |
2171 | "entering an invalid\n" | |
2172 | "state for Intel VT. For example, the guest maybe running " | |
2173 | "in big real mode\n" | |
2174 | "which is not supported on less recent Intel processors." | |
2175 | "\n\n"); | |
2176 | } | |
2177 | ret = -1; | |
2178 | break; | |
2179 | case KVM_EXIT_EXCEPTION: | |
2180 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
2181 | run->ex.exception, run->ex.error_code); | |
2182 | ret = -1; | |
2183 | break; | |
f2574737 JK |
2184 | case KVM_EXIT_DEBUG: |
2185 | DPRINTF("kvm_exit_debug\n"); | |
a60f24b5 | 2186 | ret = kvm_handle_debug(cpu, &run->debug.arch); |
f2574737 | 2187 | break; |
2a4dac83 JK |
2188 | default: |
2189 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
2190 | ret = -1; | |
2191 | break; | |
2192 | } | |
2193 | ||
2194 | return ret; | |
2195 | } | |
2196 | ||
20d695a9 | 2197 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
4513d923 | 2198 | { |
20d695a9 AF |
2199 | X86CPU *cpu = X86_CPU(cs); |
2200 | CPUX86State *env = &cpu->env; | |
2201 | ||
dd1750d7 | 2202 | kvm_cpu_synchronize_state(cs); |
b9bec74b JK |
2203 | return !(env->cr[0] & CR0_PE_MASK) || |
2204 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2205 | } |
84b058d7 JK |
2206 | |
2207 | void kvm_arch_init_irq_routing(KVMState *s) | |
2208 | { | |
2209 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
2210 | /* If kernel can't do irq routing, interrupt source | |
2211 | * override 0->2 cannot be set up as required by HPET. | |
2212 | * So we have to disable it. | |
2213 | */ | |
2214 | no_hpet = 1; | |
2215 | } | |
cc7e0ddf | 2216 | /* We know at this point that we're using the in-kernel |
614e41bc | 2217 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 2218 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf PM |
2219 | */ |
2220 | kvm_irqfds_allowed = true; | |
614e41bc | 2221 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 2222 | kvm_gsi_routing_allowed = true; |
84b058d7 | 2223 | } |
b139bd30 JK |
2224 | |
2225 | /* Classic KVM device assignment interface. Will remain x86 only. */ | |
2226 | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, | |
2227 | uint32_t flags, uint32_t *dev_id) | |
2228 | { | |
2229 | struct kvm_assigned_pci_dev dev_data = { | |
2230 | .segnr = dev_addr->domain, | |
2231 | .busnr = dev_addr->bus, | |
2232 | .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function), | |
2233 | .flags = flags, | |
2234 | }; | |
2235 | int ret; | |
2236 | ||
2237 | dev_data.assigned_dev_id = | |
2238 | (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn; | |
2239 | ||
2240 | ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data); | |
2241 | if (ret < 0) { | |
2242 | return ret; | |
2243 | } | |
2244 | ||
2245 | *dev_id = dev_data.assigned_dev_id; | |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | ||
2250 | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id) | |
2251 | { | |
2252 | struct kvm_assigned_pci_dev dev_data = { | |
2253 | .assigned_dev_id = dev_id, | |
2254 | }; | |
2255 | ||
2256 | return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data); | |
2257 | } | |
2258 | ||
2259 | static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id, | |
2260 | uint32_t irq_type, uint32_t guest_irq) | |
2261 | { | |
2262 | struct kvm_assigned_irq assigned_irq = { | |
2263 | .assigned_dev_id = dev_id, | |
2264 | .guest_irq = guest_irq, | |
2265 | .flags = irq_type, | |
2266 | }; | |
2267 | ||
2268 | if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) { | |
2269 | return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq); | |
2270 | } else { | |
2271 | return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq); | |
2272 | } | |
2273 | } | |
2274 | ||
2275 | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi, | |
2276 | uint32_t guest_irq) | |
2277 | { | |
2278 | uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX | | |
2279 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX); | |
2280 | ||
2281 | return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq); | |
2282 | } | |
2283 | ||
2284 | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked) | |
2285 | { | |
2286 | struct kvm_assigned_pci_dev dev_data = { | |
2287 | .assigned_dev_id = dev_id, | |
2288 | .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0, | |
2289 | }; | |
2290 | ||
2291 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data); | |
2292 | } | |
2293 | ||
2294 | static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id, | |
2295 | uint32_t type) | |
2296 | { | |
2297 | struct kvm_assigned_irq assigned_irq = { | |
2298 | .assigned_dev_id = dev_id, | |
2299 | .flags = type, | |
2300 | }; | |
2301 | ||
2302 | return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq); | |
2303 | } | |
2304 | ||
2305 | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi) | |
2306 | { | |
2307 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX | | |
2308 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX)); | |
2309 | } | |
2310 | ||
2311 | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq) | |
2312 | { | |
2313 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI | | |
2314 | KVM_DEV_IRQ_GUEST_MSI, virq); | |
2315 | } | |
2316 | ||
2317 | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id) | |
2318 | { | |
2319 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI | | |
2320 | KVM_DEV_IRQ_HOST_MSI); | |
2321 | } | |
2322 | ||
2323 | bool kvm_device_msix_supported(KVMState *s) | |
2324 | { | |
2325 | /* The kernel lacks a corresponding KVM_CAP, so we probe by calling | |
2326 | * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */ | |
2327 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT; | |
2328 | } | |
2329 | ||
2330 | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id, | |
2331 | uint32_t nr_vectors) | |
2332 | { | |
2333 | struct kvm_assigned_msix_nr msix_nr = { | |
2334 | .assigned_dev_id = dev_id, | |
2335 | .entry_nr = nr_vectors, | |
2336 | }; | |
2337 | ||
2338 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr); | |
2339 | } | |
2340 | ||
2341 | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector, | |
2342 | int virq) | |
2343 | { | |
2344 | struct kvm_assigned_msix_entry msix_entry = { | |
2345 | .assigned_dev_id = dev_id, | |
2346 | .gsi = virq, | |
2347 | .entry = vector, | |
2348 | }; | |
2349 | ||
2350 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry); | |
2351 | } | |
2352 | ||
2353 | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id) | |
2354 | { | |
2355 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX | | |
2356 | KVM_DEV_IRQ_GUEST_MSIX, 0); | |
2357 | } | |
2358 | ||
2359 | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id) | |
2360 | { | |
2361 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX | | |
2362 | KVM_DEV_IRQ_HOST_MSIX); | |
2363 | } |