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kvm: x86: Prevent sign extension of DR7 in guest debugging mode
[qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
21
22#include "qemu-common.h"
23#include "sysemu.h"
24#include "kvm.h"
25#include "cpu.h"
e22a25c9 26#include "gdbstub.h"
0e607a80 27#include "host-utils.h"
4c5b10b7 28#include "hw/pc.h"
408392b3 29#include "hw/apic.h"
35bed8ee 30#include "ioport.h"
e7701825 31#include "kvm_x86.h"
05330448 32
bb0300dc
GN		 33#ifdef CONFIG_KVM_PARA
34#include <linux/kvm_para.h>
35#endif
36//
05330448
AL		 37//#define DEBUG_KVM
38
39#ifdef DEBUG_KVM
8c0d577e 40#define DPRINTF(fmt, ...) \
05330448
AL		 41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42#else
8c0d577e 43#define DPRINTF(fmt, ...) \
05330448
AL		 44 do { } while (0)
45#endif
46
1a03675d
GC		 47#define MSR_KVM_WALL_CLOCK 0x11
48#define MSR_KVM_SYSTEM_TIME 0x12
49
c0532a76
MT		 50#ifndef BUS_MCEERR_AR
51#define BUS_MCEERR_AR 4
52#endif
53#ifndef BUS_MCEERR_AO
54#define BUS_MCEERR_AO 5
55#endif
56
25d2e361
MT		 57static int lm_capable_kernel;
58
b827df58
AK		 59#ifdef KVM_CAP_EXT_CPUID
60
61static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
62{
63 struct kvm_cpuid2 *cpuid;
64 int r, size;
65
66 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
67 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
68 cpuid->nent = max;
69 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 70 if (r == 0 && cpuid->nent >= max) {
71 r = -E2BIG;
72 }
b827df58
AK		 73 if (r < 0) {
74 if (r == -E2BIG) {
75 qemu_free(cpuid);
76 return NULL;
77 } else {
78 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
79 strerror(-r));
80 exit(1);
81 }
82 }
83 return cpuid;
84}
85
c958a8bd
SY		 86uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
87 uint32_t index, int reg)
b827df58
AK		 88{
89 struct kvm_cpuid2 *cpuid;
90 int i, max;
91 uint32_t ret = 0;
92 uint32_t cpuid_1_edx;
93
94 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
95 return -1U;
96 }
97
98 max = 1;
99 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
100 max *= 2;
101 }
102
103 for (i = 0; i < cpuid->nent; ++i) {
c958a8bd
SY		 104 if (cpuid->entries[i].function == function &&
105 cpuid->entries[i].index == index) {
b827df58
AK		 106 switch (reg) {
107 case R_EAX:
108 ret = cpuid->entries[i].eax;
109 break;
110 case R_EBX:
111 ret = cpuid->entries[i].ebx;
112 break;
113 case R_ECX:
114 ret = cpuid->entries[i].ecx;
115 break;
116 case R_EDX:
117 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 118 switch (function) {
119 case 1:
120 /* KVM before 2.6.30 misreports the following features */
121 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
122 break;
123 case 0x80000001:
b827df58
AK		 124 /* On Intel, kvm returns cpuid according to the Intel spec,
125 * so add missing bits according to the AMD spec:
126 */
c958a8bd 127 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
c1667e40 128 ret |= cpuid_1_edx & 0x183f7ff;
19ccb8ea 129 break;
b827df58
AK		 130 }
131 break;
132 }
133 }
134 }
135
136 qemu_free(cpuid);
137
138 return ret;
139}
140
141#else
142
c958a8bd
SY		 143uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
144 uint32_t index, int reg)
b827df58
AK		 145{
146 return -1U;
147}
148
149#endif
150
bb0300dc
GN		 151#ifdef CONFIG_KVM_PARA
152struct kvm_para_features {
153 int cap;
154 int feature;
155} para_features[] = {
156#ifdef KVM_CAP_CLOCKSOURCE
157 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
158#endif
159#ifdef KVM_CAP_NOP_IO_DELAY
160 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
161#endif
162#ifdef KVM_CAP_PV_MMU
163 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
f6584ee2
GN		 164#endif
165#ifdef KVM_CAP_ASYNC_PF
166 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
bb0300dc
GN		 167#endif
168 { -1, -1 }
169};
170
171static int get_para_features(CPUState *env)
172{
173 int i, features = 0;
174
175 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
176 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
177 features |= (1 << para_features[i].feature);
178 }
179
180 return features;
181}
182#endif
183
e7701825
MT		 184#ifdef KVM_CAP_MCE
185static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
186 int *max_banks)
187{
188 int r;
189
14a09518 190 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 191 if (r > 0) {
192 *max_banks = r;
193 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
194 }
195 return -ENOSYS;
196}
197
198static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
199{
200 return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
201}
202
203static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
204{
205 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
206}
207
c0532a76
MT		 208static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
209{
210 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
211 int r;
212
213 kmsrs->nmsrs = n;
214 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
215 r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
216 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
217 free(kmsrs);
218 return r;
219}
220
221/* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
6643e2f0 222static int kvm_mce_in_progress(CPUState *env)
c0532a76
MT		 223{
224 struct kvm_msr_entry msr_mcg_status = {
225 .index = MSR_MCG_STATUS,
226 };
227 int r;
228
229 r = kvm_get_msr(env, &msr_mcg_status, 1);
230 if (r == -1 || r == 0) {
6643e2f0
JD		 231 fprintf(stderr, "Failed to get MCE status\n");
232 return 0;
c0532a76
MT		 233 }
234 return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
235}
236
e7701825
MT		 237struct kvm_x86_mce_data
238{
239 CPUState *env;
240 struct kvm_x86_mce *mce;
c0532a76 241 int abort_on_error;
e7701825
MT		 242};
243
244static void kvm_do_inject_x86_mce(void *_data)
245{
246 struct kvm_x86_mce_data *data = _data;
247 int r;
248
f8502cfb
HS		 249 /* If there is an MCE exception being processed, ignore this SRAO MCE */
250 if ((data->env->mcg_cap & MCG_SER_P) &&
251 !(data->mce->status & MCI_STATUS_AR)) {
6643e2f0 252 if (kvm_mce_in_progress(data->env)) {
f8502cfb
HS		 253 return;
254 }
255 }
c0532a76 256
e7701825 257 r = kvm_set_mce(data->env, data->mce);
c0532a76 258 if (r < 0) {
e7701825 259 perror("kvm_set_mce FAILED");
c0532a76
MT		 260 if (data->abort_on_error) {
261 abort();
262 }
263 }
e7701825 264}
31ce5e0c 265
7cc2cc3e
JD		 266static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce,
267 int flag)
268{
269 struct kvm_x86_mce_data data = {
270 .env = env,
271 .mce = mce,
272 .abort_on_error = (flag & ABORT_ON_ERROR),
273 };
274
275 if (!env->mcg_cap) {
276 fprintf(stderr, "MCE support is not enabled!\n");
277 return;
278 }
279
280 run_on_cpu(env, kvm_do_inject_x86_mce, &data);
281}
282
31ce5e0c 283static void kvm_mce_broadcast_rest(CPUState *env);
e7701825
MT		 284#endif
285
286void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
c0532a76 287 uint64_t mcg_status, uint64_t addr, uint64_t misc,
31ce5e0c 288 int flag)
e7701825
MT		 289{
290#ifdef KVM_CAP_MCE
291 struct kvm_x86_mce mce = {
292 .bank = bank,
293 .status = status,
294 .mcg_status = mcg_status,
295 .addr = addr,
296 .misc = misc,
297 };
c0532a76 298
31ce5e0c
JD		 299 if (flag & MCE_BROADCAST) {
300 kvm_mce_broadcast_rest(cenv);
301 }
302
7cc2cc3e 303 kvm_inject_x86_mce_on(cenv, &mce, flag);
c0532a76 304#else
31ce5e0c 305 if (flag & ABORT_ON_ERROR) {
c0532a76 306 abort();
31ce5e0c 307 }
e7701825
MT		 308#endif
309}
310
05330448
AL		 311int kvm_arch_init_vcpu(CPUState *env)
312{
313 struct {
486bd5a2
AL		 314 struct kvm_cpuid2 cpuid;
315 struct kvm_cpuid_entry2 entries[100];
05330448 316 } __attribute__((packed)) cpuid_data;
486bd5a2 317 uint32_t limit, i, j, cpuid_i;
a33609ca 318 uint32_t unused;
bb0300dc
GN		 319 struct kvm_cpuid_entry2 *c;
320#ifdef KVM_CPUID_SIGNATURE
321 uint32_t signature[3];
322#endif
05330448 323
f8d926e9
JK		 324 env->mp_state = KVM_MP_STATE_RUNNABLE;
325
c958a8bd 326 env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
6c0d7ee8
AP		 327
328 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
c958a8bd 329 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
6c0d7ee8
AP		 330 env->cpuid_ext_features |= i;
331
457dfed6 332 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 333 0, R_EDX);
457dfed6 334 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
c958a8bd 335 0, R_ECX);
296acb64
JR		 336 env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
337 0, R_EDX);
338
6c1f42fe 339
05330448
AL		 340 cpuid_i = 0;
341
bb0300dc
GN		 342#ifdef CONFIG_KVM_PARA
343 /* Paravirtualization CPUIDs */
344 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
345 c = &cpuid_data.entries[cpuid_i++];
346 memset(c, 0, sizeof(*c));
347 c->function = KVM_CPUID_SIGNATURE;
348 c->eax = 0;
349 c->ebx = signature[0];
350 c->ecx = signature[1];
351 c->edx = signature[2];
352
353 c = &cpuid_data.entries[cpuid_i++];
354 memset(c, 0, sizeof(*c));
355 c->function = KVM_CPUID_FEATURES;
356 c->eax = env->cpuid_kvm_features & get_para_features(env);
357#endif
358
a33609ca 359 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 360
361 for (i = 0; i <= limit; i++) {
bb0300dc 362 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 363
364 switch (i) {
a36b1029
AL		 365 case 2: {
366 /* Keep reading function 2 till all the input is received */
367 int times;
368
a36b1029 369 c->function = i;
a33609ca
AL		 370 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
371 KVM_CPUID_FLAG_STATE_READ_NEXT;
372 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
373 times = c->eax & 0xff;
a36b1029
AL		 374
375 for (j = 1; j < times; ++j) {
a33609ca 376 c = &cpuid_data.entries[cpuid_i++];
a36b1029 377 c->function = i;
a33609ca
AL		 378 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
379 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 380 }
381 break;
382 }
486bd5a2
AL		 383 case 4:
384 case 0xb:
385 case 0xd:
386 for (j = 0; ; j++) {
486bd5a2
AL		 387 c->function = i;
388 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
389 c->index = j;
a33609ca 390 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 391
a33609ca 392 if (i == 4 && c->eax == 0)
486bd5a2 393 break;
a33609ca 394 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 395 break;
a33609ca 396 if (i == 0xd && c->eax == 0)
486bd5a2 397 break;
a33609ca
AL		 398
399 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 400 }
401 break;
402 default:
486bd5a2 403 c->function = i;
a33609ca
AL		 404 c->flags = 0;
405 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 406 break;
407 }
05330448 408 }
a33609ca 409 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 410
411 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 412 c = &cpuid_data.entries[cpuid_i++];
05330448 413
05330448 414 c->function = i;
a33609ca
AL		 415 c->flags = 0;
416 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 417 }
418
419 cpuid_data.cpuid.nent = cpuid_i;
420
e7701825
MT		 421#ifdef KVM_CAP_MCE
422 if (((env->cpuid_version >> 8)&0xF) >= 6
423 && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
424 && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
425 uint64_t mcg_cap;
426 int banks;
427
428 if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks))
429 perror("kvm_get_mce_cap_supported FAILED");
430 else {
431 if (banks > MCE_BANKS_DEF)
432 banks = MCE_BANKS_DEF;
433 mcg_cap &= MCE_CAP_DEF;
434 mcg_cap |= banks;
435 if (kvm_setup_mce(env, &mcg_cap))
436 perror("kvm_setup_mce FAILED");
437 else
438 env->mcg_cap = mcg_cap;
439 }
440 }
441#endif
442
486bd5a2 443 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 444}
445
caa5af0f
JK		 446void kvm_arch_reset_vcpu(CPUState *env)
447{
e73223a5 448 env->exception_injected = -1;
0e607a80 449 env->interrupt_injected = -1;
a0fb002c
JK		 450 env->nmi_injected = 0;
451 env->nmi_pending = 0;
ddced198
MT		 452 if (kvm_irqchip_in_kernel()) {
453 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
454 KVM_MP_STATE_UNINITIALIZED;
455 } else {
456 env->mp_state = KVM_MP_STATE_RUNNABLE;
457 }
caa5af0f
JK		 458}
459
75b10c43
MT		 460int has_msr_star;
461int has_msr_hsave_pa;
462
463static void kvm_supported_msrs(CPUState *env)
05330448 464{
75b10c43 465 static int kvm_supported_msrs;
05330448
AL		 466 int ret;
467
468 /* first time */
75b10c43 469 if (kvm_supported_msrs == 0) {
05330448
AL		 470 struct kvm_msr_list msr_list, *kvm_msr_list;
471
75b10c43 472 kvm_supported_msrs = -1;
05330448
AL		 473
474 /* Obtain MSR list from KVM. These are the MSRs that we must
475 * save/restore */
4c9f7372 476 msr_list.nmsrs = 0;
05330448 477 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 478 if (ret < 0 && ret != -E2BIG) {
75b10c43 479 return;
6fb6d245 480 }
d9db889f
JK		 481 /* Old kernel modules had a bug and could write beyond the provided
482 memory. Allocate at least a safe amount of 1K. */
483 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
484 msr_list.nmsrs *
485 sizeof(msr_list.indices[0])));
05330448 486
55308450 487 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 488 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
489 if (ret >= 0) {
490 int i;
491
492 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
493 if (kvm_msr_list->indices[i] == MSR_STAR) {
494 has_msr_star = 1;
75b10c43
MT		 495 continue;
496 }
497 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
498 has_msr_hsave_pa = 1;
499 continue;
05330448
AL		 500 }
501 }
502 }
503
504 free(kvm_msr_list);
505 }
506
75b10c43
MT		 507 return;
508}
509
510static int kvm_has_msr_hsave_pa(CPUState *env)
511{
512 kvm_supported_msrs(env);
513 return has_msr_hsave_pa;
514}
515
516static int kvm_has_msr_star(CPUState *env)
517{
518 kvm_supported_msrs(env);
519 return has_msr_star;
05330448
AL		 520}
521
20420430
SY		 522static int kvm_init_identity_map_page(KVMState *s)
523{
524#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
525 int ret;
526 uint64_t addr = 0xfffbc000;
527
528 if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
529 return 0;
530 }
531
532 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
533 if (ret < 0) {
534 fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
535 return ret;
536 }
537#endif
538 return 0;
539}
540
05330448
AL		 541int kvm_arch_init(KVMState *s, int smp_cpus)
542{
543 int ret;
544
25d2e361
MT		 545 struct utsname utsname;
546
547 uname(&utsname);
548 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
549
05330448
AL		 550 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
551 * directly. In order to use vm86 mode, a TSS is needed. Since this
552 * must be part of guest physical memory, we need to allocate it. Older
553 * versions of KVM just assumed that it would be at the end of physical
554 * memory but that doesn't work with more than 4GB of memory. We simply
555 * refuse to work with those older versions of KVM. */
14a09518 556 ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 557 if (ret <= 0) {
558 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
559 return ret;
560 }
561
562 /* this address is 3 pages before the bios, and the bios should present
563 * as unavaible memory. FIXME, need to ensure the e820 map deals with
564 * this?
565 */
4c5b10b7
JS		 566 /*
567 * Tell fw_cfg to notify the BIOS to reserve the range.
568 */
569 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
570 perror("e820_add_entry() table is full");
571 exit(1);
572 }
20420430
SY		 573 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
574 if (ret < 0) {
575 return ret;
576 }
577
578 return kvm_init_identity_map_page(s);
05330448
AL		 579}
580
581static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
582{
583 lhs->selector = rhs->selector;
584 lhs->base = rhs->base;
585 lhs->limit = rhs->limit;
586 lhs->type = 3;
587 lhs->present = 1;
588 lhs->dpl = 3;
589 lhs->db = 0;
590 lhs->s = 1;
591 lhs->l = 0;
592 lhs->g = 0;
593 lhs->avl = 0;
594 lhs->unusable = 0;
595}
596
597static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
598{
599 unsigned flags = rhs->flags;
600 lhs->selector = rhs->selector;
601 lhs->base = rhs->base;
602 lhs->limit = rhs->limit;
603 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
604 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 605 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 606 lhs->db = (flags >> DESC_B_SHIFT) & 1;
607 lhs->s = (flags & DESC_S_MASK) != 0;
608 lhs->l = (flags >> DESC_L_SHIFT) & 1;
609 lhs->g = (flags & DESC_G_MASK) != 0;
610 lhs->avl = (flags & DESC_AVL_MASK) != 0;
611 lhs->unusable = 0;
612}
613
614static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
615{
616 lhs->selector = rhs->selector;
617 lhs->base = rhs->base;
618 lhs->limit = rhs->limit;
619 lhs->flags =
620 (rhs->type << DESC_TYPE_SHIFT)
621 | (rhs->present * DESC_P_MASK)
622 | (rhs->dpl << DESC_DPL_SHIFT)
623 | (rhs->db << DESC_B_SHIFT)
624 | (rhs->s * DESC_S_MASK)
625 | (rhs->l << DESC_L_SHIFT)
626 | (rhs->g * DESC_G_MASK)
627 | (rhs->avl * DESC_AVL_MASK);
628}
629
630static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
631{
632 if (set)
633 *kvm_reg = *qemu_reg;
634 else
635 *qemu_reg = *kvm_reg;
636}
637
638static int kvm_getput_regs(CPUState *env, int set)
639{
640 struct kvm_regs regs;
641 int ret = 0;
642
643 if (!set) {
644 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
645 if (ret < 0)
646 return ret;
647 }
648
649 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
650 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
651 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
652 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
653 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
654 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
655 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
656 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
657#ifdef TARGET_X86_64
658 kvm_getput_reg(&regs.r8, &env->regs[8], set);
659 kvm_getput_reg(&regs.r9, &env->regs[9], set);
660 kvm_getput_reg(&regs.r10, &env->regs[10], set);
661 kvm_getput_reg(&regs.r11, &env->regs[11], set);
662 kvm_getput_reg(&regs.r12, &env->regs[12], set);
663 kvm_getput_reg(&regs.r13, &env->regs[13], set);
664 kvm_getput_reg(&regs.r14, &env->regs[14], set);
665 kvm_getput_reg(&regs.r15, &env->regs[15], set);
666#endif
667
668 kvm_getput_reg(&regs.rflags, &env->eflags, set);
669 kvm_getput_reg(&regs.rip, &env->eip, set);
670
671 if (set)
672 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
673
674 return ret;
675}
676
677static int kvm_put_fpu(CPUState *env)
678{
679 struct kvm_fpu fpu;
680 int i;
681
682 memset(&fpu, 0, sizeof fpu);
683 fpu.fsw = env->fpus & ~(7 << 11);
684 fpu.fsw |= (env->fpstt & 7) << 11;
685 fpu.fcw = env->fpuc;
686 for (i = 0; i < 8; ++i)
687 fpu.ftwx |= (!env->fptags[i]) << i;
688 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
689 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
690 fpu.mxcsr = env->mxcsr;
691
692 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
693}
694
f1665b21
SY		 695#ifdef KVM_CAP_XSAVE
696#define XSAVE_CWD_RIP 2
697#define XSAVE_CWD_RDP 4
698#define XSAVE_MXCSR 6
699#define XSAVE_ST_SPACE 8
700#define XSAVE_XMM_SPACE 40
701#define XSAVE_XSTATE_BV 128
702#define XSAVE_YMMH_SPACE 144
703#endif
704
705static int kvm_put_xsave(CPUState *env)
706{
707#ifdef KVM_CAP_XSAVE
0f53994f 708 int i, r;
f1665b21
SY		 709 struct kvm_xsave* xsave;
710 uint16_t cwd, swd, twd, fop;
711
712 if (!kvm_has_xsave())
713 return kvm_put_fpu(env);
714
715 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
716 memset(xsave, 0, sizeof(struct kvm_xsave));
717 cwd = swd = twd = fop = 0;
718 swd = env->fpus & ~(7 << 11);
719 swd |= (env->fpstt & 7) << 11;
720 cwd = env->fpuc;
721 for (i = 0; i < 8; ++i)
722 twd |= (!env->fptags[i]) << i;
723 xsave->region[0] = (uint32_t)(swd << 16) + cwd;
724 xsave->region[1] = (uint32_t)(fop << 16) + twd;
725 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
726 sizeof env->fpregs);
727 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
728 sizeof env->xmm_regs);
729 xsave->region[XSAVE_MXCSR] = env->mxcsr;
730 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
731 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
732 sizeof env->ymmh_regs);
0f53994f
MT		 733 r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
734 qemu_free(xsave);
735 return r;
f1665b21
SY		 736#else
737 return kvm_put_fpu(env);
738#endif
739}
740
741static int kvm_put_xcrs(CPUState *env)
742{
743#ifdef KVM_CAP_XCRS
744 struct kvm_xcrs xcrs;
745
746 if (!kvm_has_xcrs())
747 return 0;
748
749 xcrs.nr_xcrs = 1;
750 xcrs.flags = 0;
751 xcrs.xcrs[0].xcr = 0;
752 xcrs.xcrs[0].value = env->xcr0;
753 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
754#else
755 return 0;
756#endif
757}
758
05330448
AL		 759static int kvm_put_sregs(CPUState *env)
760{
761 struct kvm_sregs sregs;
762
0e607a80
JK		 763 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
764 if (env->interrupt_injected >= 0) {
765 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
766 (uint64_t)1 << (env->interrupt_injected % 64);
767 }
05330448
AL		 768
769 if ((env->eflags & VM_MASK)) {
770 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
771 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
772 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
773 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
774 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
775 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
776 } else {
777 set_seg(&sregs.cs, &env->segs[R_CS]);
778 set_seg(&sregs.ds, &env->segs[R_DS]);
779 set_seg(&sregs.es, &env->segs[R_ES]);
780 set_seg(&sregs.fs, &env->segs[R_FS]);
781 set_seg(&sregs.gs, &env->segs[R_GS]);
782 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 783 }
784
785 set_seg(&sregs.tr, &env->tr);
786 set_seg(&sregs.ldt, &env->ldt);
787
788 sregs.idt.limit = env->idt.limit;
789 sregs.idt.base = env->idt.base;
790 sregs.gdt.limit = env->gdt.limit;
791 sregs.gdt.base = env->gdt.base;
792
793 sregs.cr0 = env->cr[0];
794 sregs.cr2 = env->cr[2];
795 sregs.cr3 = env->cr[3];
796 sregs.cr4 = env->cr[4];
797
4a942cea
BS		 798 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
799 sregs.apic_base = cpu_get_apic_base(env->apic_state);
05330448
AL		 800
801 sregs.efer = env->efer;
802
803 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
804}
805
806static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
807 uint32_t index, uint64_t value)
808{
809 entry->index = index;
810 entry->data = value;
811}
812
ea643051 813static int kvm_put_msrs(CPUState *env, int level)
05330448
AL		 814{
815 struct {
816 struct kvm_msrs info;
817 struct kvm_msr_entry entries[100];
818 } msr_data;
819 struct kvm_msr_entry *msrs = msr_data.entries;
d8da8574 820 int n = 0;
05330448
AL		 821
822 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
823 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
824 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
825 if (kvm_has_msr_star(env))
826 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
75b10c43
MT		 827 if (kvm_has_msr_hsave_pa(env))
828 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
05330448 829#ifdef TARGET_X86_64
25d2e361
MT		 830 if (lm_capable_kernel) {
831 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
832 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
833 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
834 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
835 }
05330448 836#endif
ea643051 837 if (level == KVM_PUT_FULL_STATE) {
384331a6
MT		 838 /*
839 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
840 * writeback. Until this is fixed, we only write the offset to SMP
841 * guests after migration, desynchronizing the VCPUs, but avoiding
842 * huge jump-backs that would occur without any writeback at all.
843 */
844 if (smp_cpus == 1 || env->tsc != 0) {
845 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
846 }
ea643051
JK		 847 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
848 env->system_time_msr);
849 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
f6584ee2
GN		 850#ifdef KVM_CAP_ASYNC_PF
851 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
852#endif
ea643051 853 }
57780495
MT		 854#ifdef KVM_CAP_MCE
855 if (env->mcg_cap) {
d8da8574 856 int i;
57780495
MT		 857 if (level == KVM_PUT_RESET_STATE)
858 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
859 else if (level == KVM_PUT_FULL_STATE) {
860 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
861 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
862 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
863 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
864 }
865 }
866#endif
1a03675d 867
05330448
AL		 868 msr_data.info.nmsrs = n;
869
870 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
871
872}
873
874
875static int kvm_get_fpu(CPUState *env)
876{
877 struct kvm_fpu fpu;
878 int i, ret;
879
880 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
881 if (ret < 0)
882 return ret;
883
884 env->fpstt = (fpu.fsw >> 11) & 7;
885 env->fpus = fpu.fsw;
886 env->fpuc = fpu.fcw;
887 for (i = 0; i < 8; ++i)
888 env->fptags[i] = !((fpu.ftwx >> i) & 1);
889 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
890 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
891 env->mxcsr = fpu.mxcsr;
892
893 return 0;
894}
895
f1665b21
SY		 896static int kvm_get_xsave(CPUState *env)
897{
898#ifdef KVM_CAP_XSAVE
899 struct kvm_xsave* xsave;
900 int ret, i;
901 uint16_t cwd, swd, twd, fop;
902
903 if (!kvm_has_xsave())
904 return kvm_get_fpu(env);
905
906 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
907 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
0f53994f
MT		 908 if (ret < 0) {
909 qemu_free(xsave);
f1665b21 910 return ret;
0f53994f 911 }
f1665b21
SY		 912
913 cwd = (uint16_t)xsave->region[0];
914 swd = (uint16_t)(xsave->region[0] >> 16);
915 twd = (uint16_t)xsave->region[1];
916 fop = (uint16_t)(xsave->region[1] >> 16);
917 env->fpstt = (swd >> 11) & 7;
918 env->fpus = swd;
919 env->fpuc = cwd;
920 for (i = 0; i < 8; ++i)
921 env->fptags[i] = !((twd >> i) & 1);
922 env->mxcsr = xsave->region[XSAVE_MXCSR];
923 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
924 sizeof env->fpregs);
925 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
926 sizeof env->xmm_regs);
927 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
928 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
929 sizeof env->ymmh_regs);
0f53994f 930 qemu_free(xsave);
f1665b21
SY		 931 return 0;
932#else
933 return kvm_get_fpu(env);
934#endif
935}
936
937static int kvm_get_xcrs(CPUState *env)
938{
939#ifdef KVM_CAP_XCRS
940 int i, ret;
941 struct kvm_xcrs xcrs;
942
943 if (!kvm_has_xcrs())
944 return 0;
945
946 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
947 if (ret < 0)
948 return ret;
949
950 for (i = 0; i < xcrs.nr_xcrs; i++)
951 /* Only support xcr0 now */
952 if (xcrs.xcrs[0].xcr == 0) {
953 env->xcr0 = xcrs.xcrs[0].value;
954 break;
955 }
956 return 0;
957#else
958 return 0;
959#endif
960}
961
05330448
AL		 962static int kvm_get_sregs(CPUState *env)
963{
964 struct kvm_sregs sregs;
965 uint32_t hflags;
0e607a80 966 int bit, i, ret;
05330448
AL		 967
968 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
969 if (ret < 0)
970 return ret;
971
0e607a80
JK		 972 /* There can only be one pending IRQ set in the bitmap at a time, so try
973 to find it and save its number instead (-1 for none). */
974 env->interrupt_injected = -1;
975 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
976 if (sregs.interrupt_bitmap[i]) {
977 bit = ctz64(sregs.interrupt_bitmap[i]);
978 env->interrupt_injected = i * 64 + bit;
979 break;
980 }
981 }
05330448
AL		 982
983 get_seg(&env->segs[R_CS], &sregs.cs);
984 get_seg(&env->segs[R_DS], &sregs.ds);
985 get_seg(&env->segs[R_ES], &sregs.es);
986 get_seg(&env->segs[R_FS], &sregs.fs);
987 get_seg(&env->segs[R_GS], &sregs.gs);
988 get_seg(&env->segs[R_SS], &sregs.ss);
989
990 get_seg(&env->tr, &sregs.tr);
991 get_seg(&env->ldt, &sregs.ldt);
992
993 env->idt.limit = sregs.idt.limit;
994 env->idt.base = sregs.idt.base;
995 env->gdt.limit = sregs.gdt.limit;
996 env->gdt.base = sregs.gdt.base;
997
998 env->cr[0] = sregs.cr0;
999 env->cr[2] = sregs.cr2;
1000 env->cr[3] = sregs.cr3;
1001 env->cr[4] = sregs.cr4;
1002
4a942cea 1003 cpu_set_apic_base(env->apic_state, sregs.apic_base);
05330448
AL		 1004
1005 env->efer = sregs.efer;
4a942cea 1006 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
05330448
AL		 1007
1008#define HFLAG_COPY_MASK ~( \
1009 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1010 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1011 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1012 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1013
1014
1015
1016 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1017 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1018 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1019 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1020 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1021 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1022 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1023
1024 if (env->efer & MSR_EFER_LMA) {
1025 hflags |= HF_LMA_MASK;
1026 }
1027
1028 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1029 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1030 } else {
1031 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1032 (DESC_B_SHIFT - HF_CS32_SHIFT);
1033 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1034 (DESC_B_SHIFT - HF_SS32_SHIFT);
1035 if (!(env->cr[0] & CR0_PE_MASK) ||
1036 (env->eflags & VM_MASK) ||
1037 !(hflags & HF_CS32_MASK)) {
1038 hflags |= HF_ADDSEG_MASK;
1039 } else {
1040 hflags |= ((env->segs[R_DS].base |
1041 env->segs[R_ES].base |
1042 env->segs[R_SS].base) != 0) <<
1043 HF_ADDSEG_SHIFT;
1044 }
1045 }
1046 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 1047
1048 return 0;
1049}
1050
1051static int kvm_get_msrs(CPUState *env)
1052{
1053 struct {
1054 struct kvm_msrs info;
1055 struct kvm_msr_entry entries[100];
1056 } msr_data;
1057 struct kvm_msr_entry *msrs = msr_data.entries;
1058 int ret, i, n;
1059
1060 n = 0;
1061 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1062 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1063 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1064 if (kvm_has_msr_star(env))
1065 msrs[n++].index = MSR_STAR;
75b10c43
MT		 1066 if (kvm_has_msr_hsave_pa(env))
1067 msrs[n++].index = MSR_VM_HSAVE_PA;
05330448
AL		 1068 msrs[n++].index = MSR_IA32_TSC;
1069#ifdef TARGET_X86_64
25d2e361
MT		 1070 if (lm_capable_kernel) {
1071 msrs[n++].index = MSR_CSTAR;
1072 msrs[n++].index = MSR_KERNELGSBASE;
1073 msrs[n++].index = MSR_FMASK;
1074 msrs[n++].index = MSR_LSTAR;
1075 }
05330448 1076#endif
1a03675d
GC		 1077 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1078 msrs[n++].index = MSR_KVM_WALL_CLOCK;
f6584ee2
GN		 1079#ifdef KVM_CAP_ASYNC_PF
1080 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1081#endif
1a03675d 1082
57780495
MT		 1083#ifdef KVM_CAP_MCE
1084 if (env->mcg_cap) {
1085 msrs[n++].index = MSR_MCG_STATUS;
1086 msrs[n++].index = MSR_MCG_CTL;
1087 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
1088 msrs[n++].index = MSR_MC0_CTL + i;
1089 }
1090#endif
1091
05330448
AL		 1092 msr_data.info.nmsrs = n;
1093 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1094 if (ret < 0)
1095 return ret;
1096
1097 for (i = 0; i < ret; i++) {
1098 switch (msrs[i].index) {
1099 case MSR_IA32_SYSENTER_CS:
1100 env->sysenter_cs = msrs[i].data;
1101 break;
1102 case MSR_IA32_SYSENTER_ESP:
1103 env->sysenter_esp = msrs[i].data;
1104 break;
1105 case MSR_IA32_SYSENTER_EIP:
1106 env->sysenter_eip = msrs[i].data;
1107 break;
1108 case MSR_STAR:
1109 env->star = msrs[i].data;
1110 break;
1111#ifdef TARGET_X86_64
1112 case MSR_CSTAR:
1113 env->cstar = msrs[i].data;
1114 break;
1115 case MSR_KERNELGSBASE:
1116 env->kernelgsbase = msrs[i].data;
1117 break;
1118 case MSR_FMASK:
1119 env->fmask = msrs[i].data;
1120 break;
1121 case MSR_LSTAR:
1122 env->lstar = msrs[i].data;
1123 break;
1124#endif
1125 case MSR_IA32_TSC:
1126 env->tsc = msrs[i].data;
1127 break;
aa851e36
MT		 1128 case MSR_VM_HSAVE_PA:
1129 env->vm_hsave = msrs[i].data;
1130 break;
1a03675d
GC		 1131 case MSR_KVM_SYSTEM_TIME:
1132 env->system_time_msr = msrs[i].data;
1133 break;
1134 case MSR_KVM_WALL_CLOCK:
1135 env->wall_clock_msr = msrs[i].data;
1136 break;
57780495
MT		 1137#ifdef KVM_CAP_MCE
1138 case MSR_MCG_STATUS:
1139 env->mcg_status = msrs[i].data;
1140 break;
1141 case MSR_MCG_CTL:
1142 env->mcg_ctl = msrs[i].data;
1143 break;
1144#endif
1145 default:
1146#ifdef KVM_CAP_MCE
1147 if (msrs[i].index >= MSR_MC0_CTL &&
1148 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1149 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495
MT		 1150 }
1151#endif
d8da8574 1152 break;
f6584ee2
GN		 1153#ifdef KVM_CAP_ASYNC_PF
1154 case MSR_KVM_ASYNC_PF_EN:
1155 env->async_pf_en_msr = msrs[i].data;
1156 break;
1157#endif
05330448
AL		 1158 }
1159 }
1160
1161 return 0;
1162}
1163
9bdbe550
HB		 1164static int kvm_put_mp_state(CPUState *env)
1165{
1166 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1167
1168 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1169}
1170
1171static int kvm_get_mp_state(CPUState *env)
1172{
1173 struct kvm_mp_state mp_state;
1174 int ret;
1175
1176 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1177 if (ret < 0) {
1178 return ret;
1179 }
1180 env->mp_state = mp_state.mp_state;
1181 return 0;
1182}
1183
ea643051 1184static int kvm_put_vcpu_events(CPUState *env, int level)
a0fb002c
JK		 1185{
1186#ifdef KVM_CAP_VCPU_EVENTS
1187 struct kvm_vcpu_events events;
1188
1189 if (!kvm_has_vcpu_events()) {
1190 return 0;
1191 }
1192
31827373
JK		 1193 events.exception.injected = (env->exception_injected >= 0);
1194 events.exception.nr = env->exception_injected;
a0fb002c
JK		 1195 events.exception.has_error_code = env->has_error_code;
1196 events.exception.error_code = env->error_code;
1197
1198 events.interrupt.injected = (env->interrupt_injected >= 0);
1199 events.interrupt.nr = env->interrupt_injected;
1200 events.interrupt.soft = env->soft_interrupt;
1201
1202 events.nmi.injected = env->nmi_injected;
1203 events.nmi.pending = env->nmi_pending;
1204 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1205
1206 events.sipi_vector = env->sipi_vector;
1207
ea643051
JK		 1208 events.flags = 0;
1209 if (level >= KVM_PUT_RESET_STATE) {
1210 events.flags |=
1211 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1212 }
aee028b9 1213
a0fb002c
JK		 1214 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1215#else
1216 return 0;
1217#endif
1218}
1219
1220static int kvm_get_vcpu_events(CPUState *env)
1221{
1222#ifdef KVM_CAP_VCPU_EVENTS
1223 struct kvm_vcpu_events events;
1224 int ret;
1225
1226 if (!kvm_has_vcpu_events()) {
1227 return 0;
1228 }
1229
1230 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1231 if (ret < 0) {
1232 return ret;
1233 }
31827373 1234 env->exception_injected =
a0fb002c
JK		 1235 events.exception.injected ? events.exception.nr : -1;
1236 env->has_error_code = events.exception.has_error_code;
1237 env->error_code = events.exception.error_code;
1238
1239 env->interrupt_injected =
1240 events.interrupt.injected ? events.interrupt.nr : -1;
1241 env->soft_interrupt = events.interrupt.soft;
1242
1243 env->nmi_injected = events.nmi.injected;
1244 env->nmi_pending = events.nmi.pending;
1245 if (events.nmi.masked) {
1246 env->hflags2 |= HF2_NMI_MASK;
1247 } else {
1248 env->hflags2 &= ~HF2_NMI_MASK;
1249 }
1250
1251 env->sipi_vector = events.sipi_vector;
1252#endif
1253
1254 return 0;
1255}
1256
b0b1d690
JK		 1257static int kvm_guest_debug_workarounds(CPUState *env)
1258{
1259 int ret = 0;
1260#ifdef KVM_CAP_SET_GUEST_DEBUG
1261 unsigned long reinject_trap = 0;
1262
1263 if (!kvm_has_vcpu_events()) {
1264 if (env->exception_injected == 1) {
1265 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1266 } else if (env->exception_injected == 3) {
1267 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1268 }
1269 env->exception_injected = -1;
1270 }
1271
1272 /*
1273 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1274 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1275 * by updating the debug state once again if single-stepping is on.
1276 * Another reason to call kvm_update_guest_debug here is a pending debug
1277 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1278 * reinject them via SET_GUEST_DEBUG.
1279 */
1280 if (reinject_trap ||
1281 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1282 ret = kvm_update_guest_debug(env, reinject_trap);
1283 }
1284#endif /* KVM_CAP_SET_GUEST_DEBUG */
1285 return ret;
1286}
1287
ff44f1a3
JK		 1288static int kvm_put_debugregs(CPUState *env)
1289{
1290#ifdef KVM_CAP_DEBUGREGS
1291 struct kvm_debugregs dbgregs;
1292 int i;
1293
1294 if (!kvm_has_debugregs()) {
1295 return 0;
1296 }
1297
1298 for (i = 0; i < 4; i++) {
1299 dbgregs.db[i] = env->dr[i];
1300 }
1301 dbgregs.dr6 = env->dr[6];
1302 dbgregs.dr7 = env->dr[7];
1303 dbgregs.flags = 0;
1304
1305 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1306#else
1307 return 0;
1308#endif
1309}
1310
1311static int kvm_get_debugregs(CPUState *env)
1312{
1313#ifdef KVM_CAP_DEBUGREGS
1314 struct kvm_debugregs dbgregs;
1315 int i, ret;
1316
1317 if (!kvm_has_debugregs()) {
1318 return 0;
1319 }
1320
1321 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1322 if (ret < 0) {
1323 return ret;
1324 }
1325 for (i = 0; i < 4; i++) {
1326 env->dr[i] = dbgregs.db[i];
1327 }
1328 env->dr[4] = env->dr[6] = dbgregs.dr6;
1329 env->dr[5] = env->dr[7] = dbgregs.dr7;
1330#endif
1331
1332 return 0;
1333}
1334
ea375f9a 1335int kvm_arch_put_registers(CPUState *env, int level)
05330448
AL		 1336{
1337 int ret;
1338
dbaa07c4
JK		 1339 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1340
05330448
AL		 1341 ret = kvm_getput_regs(env, 1);
1342 if (ret < 0)
1343 return ret;
1344
f1665b21
SY		 1345 ret = kvm_put_xsave(env);
1346 if (ret < 0)
1347 return ret;
1348
1349 ret = kvm_put_xcrs(env);
05330448
AL		 1350 if (ret < 0)
1351 return ret;
1352
1353 ret = kvm_put_sregs(env);
1354 if (ret < 0)
1355 return ret;
1356
ea643051 1357 ret = kvm_put_msrs(env, level);
05330448
AL		 1358 if (ret < 0)
1359 return ret;
1360
ea643051
JK		 1361 if (level >= KVM_PUT_RESET_STATE) {
1362 ret = kvm_put_mp_state(env);
1363 if (ret < 0)
1364 return ret;
1365 }
f8d926e9 1366
ea643051 1367 ret = kvm_put_vcpu_events(env, level);
a0fb002c
JK		 1368 if (ret < 0)
1369 return ret;
1370
b0b1d690
JK		 1371 /* must be last */
1372 ret = kvm_guest_debug_workarounds(env);
1373 if (ret < 0)
1374 return ret;
1375
ff44f1a3
JK		 1376 ret = kvm_put_debugregs(env);
1377 if (ret < 0)
1378 return ret;
1379
05330448
AL		 1380 return 0;
1381}
1382
1383int kvm_arch_get_registers(CPUState *env)
1384{
1385 int ret;
1386
dbaa07c4
JK		 1387 assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1388
05330448
AL		 1389 ret = kvm_getput_regs(env, 0);
1390 if (ret < 0)
1391 return ret;
1392
f1665b21
SY		 1393 ret = kvm_get_xsave(env);
1394 if (ret < 0)
1395 return ret;
1396
1397 ret = kvm_get_xcrs(env);
05330448
AL		 1398 if (ret < 0)
1399 return ret;
1400
1401 ret = kvm_get_sregs(env);
1402 if (ret < 0)
1403 return ret;
1404
1405 ret = kvm_get_msrs(env);
1406 if (ret < 0)
1407 return ret;
1408
5a2e3c2e
JK		 1409 ret = kvm_get_mp_state(env);
1410 if (ret < 0)
1411 return ret;
1412
a0fb002c
JK		 1413 ret = kvm_get_vcpu_events(env);
1414 if (ret < 0)
1415 return ret;
1416
ff44f1a3
JK		 1417 ret = kvm_get_debugregs(env);
1418 if (ret < 0)
1419 return ret;
1420
05330448
AL		 1421 return 0;
1422}
1423
1424int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1425{
276ce815
LJ		 1426 /* Inject NMI */
1427 if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1428 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1429 DPRINTF("injected NMI\n");
1430 kvm_vcpu_ioctl(env, KVM_NMI);
1431 }
1432
05330448
AL		 1433 /* Try to inject an interrupt if the guest can accept it */
1434 if (run->ready_for_interrupt_injection &&
1435 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1436 (env->eflags & IF_MASK)) {
1437 int irq;
1438
1439 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1440 irq = cpu_get_pic_interrupt(env);
1441 if (irq >= 0) {
1442 struct kvm_interrupt intr;
1443 intr.irq = irq;
1444 /* FIXME: errors */
8c0d577e 1445 DPRINTF("injected interrupt %d\n", irq);
05330448
AL		 1446 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1447 }
1448 }
1449
1450 /* If we have an interrupt but the guest is not ready to receive an
1451 * interrupt, request an interrupt window exit. This will
1452 * cause a return to userspace as soon as the guest is ready to
1453 * receive interrupts. */
1454 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1455 run->request_interrupt_window = 1;
1456 else
1457 run->request_interrupt_window = 0;
1458
8c0d577e 1459 DPRINTF("setting tpr\n");
4a942cea 1460 run->cr8 = cpu_get_apic_tpr(env->apic_state);
05330448
AL		 1461
1462 return 0;
1463}
1464
1465int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1466{
1467 if (run->if_flag)
1468 env->eflags |= IF_MASK;
1469 else
1470 env->eflags &= ~IF_MASK;
1471
4a942cea
BS		 1472 cpu_set_apic_tpr(env->apic_state, run->cr8);
1473 cpu_set_apic_base(env->apic_state, run->apic_base);
05330448
AL		 1474
1475 return 0;
1476}
1477
0af691d7
MT		 1478int kvm_arch_process_irqchip_events(CPUState *env)
1479{
1480 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1481 kvm_cpu_synchronize_state(env);
1482 do_cpu_init(env);
1483 env->exception_index = EXCP_HALTED;
1484 }
1485
1486 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1487 kvm_cpu_synchronize_state(env);
1488 do_cpu_sipi(env);
1489 }
1490
1491 return env->halted;
1492}
1493
05330448
AL		 1494static int kvm_handle_halt(CPUState *env)
1495{
1496 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1497 (env->eflags & IF_MASK)) &&
1498 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1499 env->halted = 1;
1500 env->exception_index = EXCP_HLT;
1501 return 0;
1502 }
1503
1504 return 1;
1505}
1506
1507int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1508{
1509 int ret = 0;
1510
1511 switch (run->exit_reason) {
1512 case KVM_EXIT_HLT:
8c0d577e 1513 DPRINTF("handle_hlt\n");
05330448
AL		 1514 ret = kvm_handle_halt(env);
1515 break;
1516 }
1517
1518 return ret;
1519}
e22a25c9
AL		 1520
1521#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 1522int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1523{
38972938 1524 static const uint8_t int3 = 0xcc;
64bf3f4e 1525
e22a25c9 1526 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 1527 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 1528 return -EINVAL;
1529 return 0;
1530}
1531
1532int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1533{
1534 uint8_t int3;
1535
1536 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1537 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1538 return -EINVAL;
1539 return 0;
1540}
1541
1542static struct {
1543 target_ulong addr;
1544 int len;
1545 int type;
1546} hw_breakpoint[4];
1547
1548static int nb_hw_breakpoint;
1549
1550static int find_hw_breakpoint(target_ulong addr, int len, int type)
1551{
1552 int n;
1553
1554 for (n = 0; n < nb_hw_breakpoint; n++)
1555 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1556 (hw_breakpoint[n].len == len || len == -1))
1557 return n;
1558 return -1;
1559}
1560
1561int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1562 target_ulong len, int type)
1563{
1564 switch (type) {
1565 case GDB_BREAKPOINT_HW:
1566 len = 1;
1567 break;
1568 case GDB_WATCHPOINT_WRITE:
1569 case GDB_WATCHPOINT_ACCESS:
1570 switch (len) {
1571 case 1:
1572 break;
1573 case 2:
1574 case 4:
1575 case 8:
1576 if (addr & (len - 1))
1577 return -EINVAL;
1578 break;
1579 default:
1580 return -EINVAL;
1581 }
1582 break;
1583 default:
1584 return -ENOSYS;
1585 }
1586
1587 if (nb_hw_breakpoint == 4)
1588 return -ENOBUFS;
1589
1590 if (find_hw_breakpoint(addr, len, type) >= 0)
1591 return -EEXIST;
1592
1593 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1594 hw_breakpoint[nb_hw_breakpoint].len = len;
1595 hw_breakpoint[nb_hw_breakpoint].type = type;
1596 nb_hw_breakpoint++;
1597
1598 return 0;
1599}
1600
1601int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1602 target_ulong len, int type)
1603{
1604 int n;
1605
1606 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1607 if (n < 0)
1608 return -ENOENT;
1609
1610 nb_hw_breakpoint--;
1611 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1612
1613 return 0;
1614}
1615
1616void kvm_arch_remove_all_hw_breakpoints(void)
1617{
1618 nb_hw_breakpoint = 0;
1619}
1620
1621static CPUWatchpoint hw_watchpoint;
1622
1623int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1624{
1625 int handle = 0;
1626 int n;
1627
1628 if (arch_info->exception == 1) {
1629 if (arch_info->dr6 & (1 << 14)) {
1630 if (cpu_single_env->singlestep_enabled)
1631 handle = 1;
1632 } else {
1633 for (n = 0; n < 4; n++)
1634 if (arch_info->dr6 & (1 << n))
1635 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1636 case 0x0:
1637 handle = 1;
1638 break;
1639 case 0x1:
1640 handle = 1;
1641 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1642 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1643 hw_watchpoint.flags = BP_MEM_WRITE;
1644 break;
1645 case 0x3:
1646 handle = 1;
1647 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1648 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1649 hw_watchpoint.flags = BP_MEM_ACCESS;
1650 break;
1651 }
1652 }
1653 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1654 handle = 1;
1655
b0b1d690
JK		 1656 if (!handle) {
1657 cpu_synchronize_state(cpu_single_env);
1658 assert(cpu_single_env->exception_injected == -1);
1659
1660 cpu_single_env->exception_injected = arch_info->exception;
1661 cpu_single_env->has_error_code = 0;
1662 }
e22a25c9
AL		 1663
1664 return handle;
1665}
1666
1667void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1668{
1669 const uint8_t type_code[] = {
1670 [GDB_BREAKPOINT_HW] = 0x0,
1671 [GDB_WATCHPOINT_WRITE] = 0x1,
1672 [GDB_WATCHPOINT_ACCESS] = 0x3
1673 };
1674 const uint8_t len_code[] = {
1675 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1676 };
1677 int n;
1678
1679 if (kvm_sw_breakpoints_active(env))
1680 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1681
1682 if (nb_hw_breakpoint > 0) {
1683 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1684 dbg->arch.debugreg[7] = 0x0600;
1685 for (n = 0; n < nb_hw_breakpoint; n++) {
1686 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1687 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1688 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 1689 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 1690 }
1691 }
f1665b21
SY		 1692 /* Legal xcr0 for loading */
1693 env->xcr0 = 1;
e22a25c9
AL		 1694}
1695#endif /* KVM_CAP_SET_GUEST_DEBUG */
4513d923
GN		 1696
1697bool kvm_arch_stop_on_emulation_error(CPUState *env)
1698{
1699 return !(env->cr[0] & CR0_PE_MASK) ||
1700 ((env->segs[R_CS].selector & 3) != 3);
1701}
1702
c0532a76
MT		 1703static void hardware_memory_error(void)
1704{
1705 fprintf(stderr, "Hardware memory error!\n");
1706 exit(1);
1707}
1708
f71ac88f
HS		 1709#ifdef KVM_CAP_MCE
1710static void kvm_mce_broadcast_rest(CPUState *env)
1711{
7cc2cc3e
JD		 1712 struct kvm_x86_mce mce = {
1713 .bank = 1,
1714 .status = MCI_STATUS_VAL | MCI_STATUS_UC,
1715 .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1716 .addr = 0,
1717 .misc = 0,
1718 };
f71ac88f 1719 CPUState *cenv;
f71ac88f
HS		 1720
1721 /* Broadcast MCA signal for processor version 06H_EH and above */
2bd3e04c 1722 if (cpu_x86_support_mca_broadcast(env)) {
f71ac88f
HS		 1723 for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1724 if (cenv == env) {
1725 continue;
1726 }
7cc2cc3e 1727 kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR);
f71ac88f
HS		 1728 }
1729 }
1730}
e387c338
JD		 1731
1732static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1733{
1734 struct kvm_x86_mce mce = {
1735 .bank = 9,
1736 .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1737 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1738 | MCI_STATUS_AR | 0x134,
1739 .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1740 .addr = paddr,
1741 .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1742 };
1743 int r;
1744
1745 r = kvm_set_mce(env, &mce);
1746 if (r < 0) {
1747 fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1748 abort();
1749 }
1750 kvm_mce_broadcast_rest(env);
1751}
1752
1753static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1754{
1755 struct kvm_x86_mce mce = {
1756 .bank = 9,
1757 .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1758 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1759 | 0xc0,
1760 .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1761 .addr = paddr,
1762 .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1763 };
1764 int r;
1765
1766 r = kvm_set_mce(env, &mce);
1767 if (r < 0) {
1768 fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1769 abort();
1770 }
1771 kvm_mce_broadcast_rest(env);
1772}
1773
1774static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1775{
7cc2cc3e
JD		 1776 struct kvm_x86_mce mce = {
1777 .bank = 9,
1778 .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1779 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1780 | 0xc0,
1781 .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1782 .addr = paddr,
1783 .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1784 };
e387c338 1785
7cc2cc3e 1786 kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR);
e387c338
JD		 1787 kvm_mce_broadcast_rest(env);
1788}
1789
f71ac88f
HS		 1790#endif
1791
c0532a76
MT		 1792int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1793{
1794#if defined(KVM_CAP_MCE)
c0532a76
MT		 1795 void *vaddr;
1796 ram_addr_t ram_addr;
1797 target_phys_addr_t paddr;
c0532a76
MT		 1798
1799 if ((env->mcg_cap & MCG_SER_P) && addr
1800 && (code == BUS_MCEERR_AR
1801 || code == BUS_MCEERR_AO)) {
c0532a76
MT		 1802 vaddr = (void *)addr;
1803 if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1804 !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1805 fprintf(stderr, "Hardware memory error for memory used by "
1806 "QEMU itself instead of guest system!\n");
1807 /* Hope we are lucky for AO MCE */
1808 if (code == BUS_MCEERR_AO) {
1809 return 0;
1810 } else {
1811 hardware_memory_error();
1812 }
1813 }
e387c338
JD		 1814
1815 if (code == BUS_MCEERR_AR) {
1816 /* Fake an Intel architectural Data Load SRAR UCR */
1817 kvm_mce_inj_srar_dataload(env, paddr);
1818 } else {
1819 /*
1820 * If there is an MCE excpetion being processed, ignore
1821 * this SRAO MCE
1822 */
1823 if (!kvm_mce_in_progress(env)) {
1824 /* Fake an Intel architectural Memory scrubbing UCR */
1825 kvm_mce_inj_srao_memscrub(env, paddr);
1826 }
c0532a76
MT		 1827 }
1828 } else
1829#endif
1830 {
1831 if (code == BUS_MCEERR_AO) {
1832 return 0;
1833 } else if (code == BUS_MCEERR_AR) {
1834 hardware_memory_error();
1835 } else {
1836 return 1;
1837 }
1838 }
1839 return 0;
1840}
1841
1842int kvm_on_sigbus(int code, void *addr)
1843{
1844#if defined(KVM_CAP_MCE)
1845 if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
c0532a76
MT		 1846 void *vaddr;
1847 ram_addr_t ram_addr;
1848 target_phys_addr_t paddr;
c0532a76
MT		 1849
1850 /* Hope we are lucky for AO MCE */
1851 vaddr = addr;
1852 if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1853 !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1854 fprintf(stderr, "Hardware memory error for memory used by "
1855 "QEMU itself instead of guest system!: %p\n", addr);
1856 return 0;
1857 }
e387c338 1858 kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
c0532a76
MT		 1859 } else
1860#endif
1861 {
1862 if (code == BUS_MCEERR_AO) {
1863 return 0;
1864 } else if (code == BUS_MCEERR_AR) {
1865 hardware_memory_error();
1866 } else {
1867 return 1;
1868 }
1869 }
1870 return 0;
1871}
Qemu copy for testing