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Remove bogus cpu_physical_memory_rw
[qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
18
19#include <linux/kvm.h>
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "kvm.h"
24#include "cpu.h"
e22a25c9 25#include "gdbstub.h"
0e607a80 26#include "host-utils.h"
4c5b10b7 27#include "hw/pc.h"
05330448 28
bb0300dc
GN		 29#ifdef CONFIG_KVM_PARA
30#include <linux/kvm_para.h>
31#endif
32//
05330448
AL		 33//#define DEBUG_KVM
34
35#ifdef DEBUG_KVM
36#define dprintf(fmt, ...) \
37 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
38#else
39#define dprintf(fmt, ...) \
40 do { } while (0)
41#endif
42
1a03675d
GC		 43#define MSR_KVM_WALL_CLOCK 0x11
44#define MSR_KVM_SYSTEM_TIME 0x12
45
b827df58
AK		 46#ifdef KVM_CAP_EXT_CPUID
47
48static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
49{
50 struct kvm_cpuid2 *cpuid;
51 int r, size;
52
53 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
54 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
55 cpuid->nent = max;
56 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 57 if (r == 0 && cpuid->nent >= max) {
58 r = -E2BIG;
59 }
b827df58
AK		 60 if (r < 0) {
61 if (r == -E2BIG) {
62 qemu_free(cpuid);
63 return NULL;
64 } else {
65 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
66 strerror(-r));
67 exit(1);
68 }
69 }
70 return cpuid;
71}
72
73uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
74{
75 struct kvm_cpuid2 *cpuid;
76 int i, max;
77 uint32_t ret = 0;
78 uint32_t cpuid_1_edx;
79
80 if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
81 return -1U;
82 }
83
84 max = 1;
85 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
86 max *= 2;
87 }
88
89 for (i = 0; i < cpuid->nent; ++i) {
90 if (cpuid->entries[i].function == function) {
91 switch (reg) {
92 case R_EAX:
93 ret = cpuid->entries[i].eax;
94 break;
95 case R_EBX:
96 ret = cpuid->entries[i].ebx;
97 break;
98 case R_ECX:
99 ret = cpuid->entries[i].ecx;
100 break;
101 case R_EDX:
102 ret = cpuid->entries[i].edx;
19ccb8ea
JK		 103 switch (function) {
104 case 1:
105 /* KVM before 2.6.30 misreports the following features */
106 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
107 break;
108 case 0x80000001:
b827df58
AK		 109 /* On Intel, kvm returns cpuid according to the Intel spec,
110 * so add missing bits according to the AMD spec:
111 */
112 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
113 ret |= cpuid_1_edx & 0xdfeff7ff;
19ccb8ea 114 break;
b827df58
AK		 115 }
116 break;
117 }
118 }
119 }
120
121 qemu_free(cpuid);
122
123 return ret;
124}
125
126#else
127
128uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
129{
130 return -1U;
131}
132
133#endif
134
6c1f42fe
AP		 135static void kvm_trim_features(uint32_t *features, uint32_t supported)
136{
137 int i;
138 uint32_t mask;
139
140 for (i = 0; i < 32; ++i) {
141 mask = 1U << i;
142 if ((*features & mask) && !(supported & mask)) {
143 *features &= ~mask;
144 }
145 }
146}
147
bb0300dc
GN		 148#ifdef CONFIG_KVM_PARA
149struct kvm_para_features {
150 int cap;
151 int feature;
152} para_features[] = {
153#ifdef KVM_CAP_CLOCKSOURCE
154 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
155#endif
156#ifdef KVM_CAP_NOP_IO_DELAY
157 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
158#endif
159#ifdef KVM_CAP_PV_MMU
160 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
bb0300dc
GN		 161#endif
162 { -1, -1 }
163};
164
165static int get_para_features(CPUState *env)
166{
167 int i, features = 0;
168
169 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
170 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
171 features |= (1 << para_features[i].feature);
172 }
173
174 return features;
175}
176#endif
177
05330448
AL		 178int kvm_arch_init_vcpu(CPUState *env)
179{
180 struct {
486bd5a2
AL		 181 struct kvm_cpuid2 cpuid;
182 struct kvm_cpuid_entry2 entries[100];
05330448 183 } __attribute__((packed)) cpuid_data;
486bd5a2 184 uint32_t limit, i, j, cpuid_i;
a33609ca 185 uint32_t unused;
bb0300dc
GN		 186 struct kvm_cpuid_entry2 *c;
187#ifdef KVM_CPUID_SIGNATURE
188 uint32_t signature[3];
189#endif
05330448 190
f8d926e9
JK		 191 env->mp_state = KVM_MP_STATE_RUNNABLE;
192
6c1f42fe
AP		 193 kvm_trim_features(&env->cpuid_features,
194 kvm_arch_get_supported_cpuid(env, 1, R_EDX));
6c0d7ee8
AP		 195
196 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
6c1f42fe
AP		 197 kvm_trim_features(&env->cpuid_ext_features,
198 kvm_arch_get_supported_cpuid(env, 1, R_ECX));
6c0d7ee8
AP		 199 env->cpuid_ext_features |= i;
200
6c1f42fe
AP		 201 kvm_trim_features(&env->cpuid_ext2_features,
202 kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
203 kvm_trim_features(&env->cpuid_ext3_features,
204 kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
205
05330448
AL		 206 cpuid_i = 0;
207
bb0300dc
GN		 208#ifdef CONFIG_KVM_PARA
209 /* Paravirtualization CPUIDs */
210 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
211 c = &cpuid_data.entries[cpuid_i++];
212 memset(c, 0, sizeof(*c));
213 c->function = KVM_CPUID_SIGNATURE;
214 c->eax = 0;
215 c->ebx = signature[0];
216 c->ecx = signature[1];
217 c->edx = signature[2];
218
219 c = &cpuid_data.entries[cpuid_i++];
220 memset(c, 0, sizeof(*c));
221 c->function = KVM_CPUID_FEATURES;
222 c->eax = env->cpuid_kvm_features & get_para_features(env);
223#endif
224
a33609ca 225 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 226
227 for (i = 0; i <= limit; i++) {
bb0300dc 228 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 229
230 switch (i) {
a36b1029
AL		 231 case 2: {
232 /* Keep reading function 2 till all the input is received */
233 int times;
234
a36b1029 235 c->function = i;
a33609ca
AL		 236 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
237 KVM_CPUID_FLAG_STATE_READ_NEXT;
238 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
239 times = c->eax & 0xff;
a36b1029
AL		 240
241 for (j = 1; j < times; ++j) {
a33609ca 242 c = &cpuid_data.entries[cpuid_i++];
a36b1029 243 c->function = i;
a33609ca
AL		 244 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
245 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 246 }
247 break;
248 }
486bd5a2
AL		 249 case 4:
250 case 0xb:
251 case 0xd:
252 for (j = 0; ; j++) {
486bd5a2
AL		 253 c->function = i;
254 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
255 c->index = j;
a33609ca 256 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 257
a33609ca 258 if (i == 4 && c->eax == 0)
486bd5a2 259 break;
a33609ca 260 if (i == 0xb && !(c->ecx & 0xff00))
486bd5a2 261 break;
a33609ca 262 if (i == 0xd && c->eax == 0)
486bd5a2 263 break;
a33609ca
AL		 264
265 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 266 }
267 break;
268 default:
486bd5a2 269 c->function = i;
a33609ca
AL		 270 c->flags = 0;
271 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 272 break;
273 }
05330448 274 }
a33609ca 275 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 276
277 for (i = 0x80000000; i <= limit; i++) {
bb0300dc 278 c = &cpuid_data.entries[cpuid_i++];
05330448 279
05330448 280 c->function = i;
a33609ca
AL		 281 c->flags = 0;
282 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 283 }
284
285 cpuid_data.cpuid.nent = cpuid_i;
286
486bd5a2 287 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
05330448
AL		 288}
289
caa5af0f
JK		 290void kvm_arch_reset_vcpu(CPUState *env)
291{
e73223a5 292 env->exception_injected = -1;
0e607a80 293 env->interrupt_injected = -1;
a0fb002c
JK		 294 env->nmi_injected = 0;
295 env->nmi_pending = 0;
caa5af0f
JK		 296}
297
05330448
AL		 298static int kvm_has_msr_star(CPUState *env)
299{
300 static int has_msr_star;
301 int ret;
302
303 /* first time */
304 if (has_msr_star == 0) {
305 struct kvm_msr_list msr_list, *kvm_msr_list;
306
307 has_msr_star = -1;
308
309 /* Obtain MSR list from KVM. These are the MSRs that we must
310 * save/restore */
4c9f7372 311 msr_list.nmsrs = 0;
05330448 312 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 313 if (ret < 0 && ret != -E2BIG) {
05330448 314 return 0;
6fb6d245 315 }
d9db889f
JK		 316 /* Old kernel modules had a bug and could write beyond the provided
317 memory. Allocate at least a safe amount of 1K. */
318 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
319 msr_list.nmsrs *
320 sizeof(msr_list.indices[0])));
05330448 321
55308450 322 kvm_msr_list->nmsrs = msr_list.nmsrs;
05330448
AL		 323 ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
324 if (ret >= 0) {
325 int i;
326
327 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
328 if (kvm_msr_list->indices[i] == MSR_STAR) {
329 has_msr_star = 1;
330 break;
331 }
332 }
333 }
334
335 free(kvm_msr_list);
336 }
337
338 if (has_msr_star == 1)
339 return 1;
340 return 0;
341}
342
343int kvm_arch_init(KVMState *s, int smp_cpus)
344{
345 int ret;
346
347 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
348 * directly. In order to use vm86 mode, a TSS is needed. Since this
349 * must be part of guest physical memory, we need to allocate it. Older
350 * versions of KVM just assumed that it would be at the end of physical
351 * memory but that doesn't work with more than 4GB of memory. We simply
352 * refuse to work with those older versions of KVM. */
984b5181 353 ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
05330448
AL		 354 if (ret <= 0) {
355 fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
356 return ret;
357 }
358
359 /* this address is 3 pages before the bios, and the bios should present
360 * as unavaible memory. FIXME, need to ensure the e820 map deals with
361 * this?
362 */
4c5b10b7
JS		 363 /*
364 * Tell fw_cfg to notify the BIOS to reserve the range.
365 */
366 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
367 perror("e820_add_entry() table is full");
368 exit(1);
369 }
984b5181 370 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
05330448
AL		 371}
372
373static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
374{
375 lhs->selector = rhs->selector;
376 lhs->base = rhs->base;
377 lhs->limit = rhs->limit;
378 lhs->type = 3;
379 lhs->present = 1;
380 lhs->dpl = 3;
381 lhs->db = 0;
382 lhs->s = 1;
383 lhs->l = 0;
384 lhs->g = 0;
385 lhs->avl = 0;
386 lhs->unusable = 0;
387}
388
389static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
390{
391 unsigned flags = rhs->flags;
392 lhs->selector = rhs->selector;
393 lhs->base = rhs->base;
394 lhs->limit = rhs->limit;
395 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
396 lhs->present = (flags & DESC_P_MASK) != 0;
397 lhs->dpl = rhs->selector & 3;
398 lhs->db = (flags >> DESC_B_SHIFT) & 1;
399 lhs->s = (flags & DESC_S_MASK) != 0;
400 lhs->l = (flags >> DESC_L_SHIFT) & 1;
401 lhs->g = (flags & DESC_G_MASK) != 0;
402 lhs->avl = (flags & DESC_AVL_MASK) != 0;
403 lhs->unusable = 0;
404}
405
406static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
407{
408 lhs->selector = rhs->selector;
409 lhs->base = rhs->base;
410 lhs->limit = rhs->limit;
411 lhs->flags =
412 (rhs->type << DESC_TYPE_SHIFT)
413 | (rhs->present * DESC_P_MASK)
414 | (rhs->dpl << DESC_DPL_SHIFT)
415 | (rhs->db << DESC_B_SHIFT)
416 | (rhs->s * DESC_S_MASK)
417 | (rhs->l << DESC_L_SHIFT)
418 | (rhs->g * DESC_G_MASK)
419 | (rhs->avl * DESC_AVL_MASK);
420}
421
422static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
423{
424 if (set)
425 *kvm_reg = *qemu_reg;
426 else
427 *qemu_reg = *kvm_reg;
428}
429
430static int kvm_getput_regs(CPUState *env, int set)
431{
432 struct kvm_regs regs;
433 int ret = 0;
434
435 if (!set) {
436 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
437 if (ret < 0)
438 return ret;
439 }
440
441 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
442 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
443 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
444 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
445 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
446 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
447 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
448 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
449#ifdef TARGET_X86_64
450 kvm_getput_reg(&regs.r8, &env->regs[8], set);
451 kvm_getput_reg(&regs.r9, &env->regs[9], set);
452 kvm_getput_reg(&regs.r10, &env->regs[10], set);
453 kvm_getput_reg(&regs.r11, &env->regs[11], set);
454 kvm_getput_reg(&regs.r12, &env->regs[12], set);
455 kvm_getput_reg(&regs.r13, &env->regs[13], set);
456 kvm_getput_reg(&regs.r14, &env->regs[14], set);
457 kvm_getput_reg(&regs.r15, &env->regs[15], set);
458#endif
459
460 kvm_getput_reg(&regs.rflags, &env->eflags, set);
461 kvm_getput_reg(&regs.rip, &env->eip, set);
462
463 if (set)
464 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
465
466 return ret;
467}
468
469static int kvm_put_fpu(CPUState *env)
470{
471 struct kvm_fpu fpu;
472 int i;
473
474 memset(&fpu, 0, sizeof fpu);
475 fpu.fsw = env->fpus & ~(7 << 11);
476 fpu.fsw |= (env->fpstt & 7) << 11;
477 fpu.fcw = env->fpuc;
478 for (i = 0; i < 8; ++i)
479 fpu.ftwx |= (!env->fptags[i]) << i;
480 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
481 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
482 fpu.mxcsr = env->mxcsr;
483
484 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
485}
486
487static int kvm_put_sregs(CPUState *env)
488{
489 struct kvm_sregs sregs;
490
0e607a80
JK		 491 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
492 if (env->interrupt_injected >= 0) {
493 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
494 (uint64_t)1 << (env->interrupt_injected % 64);
495 }
05330448
AL		 496
497 if ((env->eflags & VM_MASK)) {
498 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
499 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
500 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
501 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
502 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
503 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
504 } else {
505 set_seg(&sregs.cs, &env->segs[R_CS]);
506 set_seg(&sregs.ds, &env->segs[R_DS]);
507 set_seg(&sregs.es, &env->segs[R_ES]);
508 set_seg(&sregs.fs, &env->segs[R_FS]);
509 set_seg(&sregs.gs, &env->segs[R_GS]);
510 set_seg(&sregs.ss, &env->segs[R_SS]);
511
512 if (env->cr[0] & CR0_PE_MASK) {
513 /* force ss cpl to cs cpl */
514 sregs.ss.selector = (sregs.ss.selector & ~3) |
515 (sregs.cs.selector & 3);
516 sregs.ss.dpl = sregs.ss.selector & 3;
517 }
518 }
519
520 set_seg(&sregs.tr, &env->tr);
521 set_seg(&sregs.ldt, &env->ldt);
522
523 sregs.idt.limit = env->idt.limit;
524 sregs.idt.base = env->idt.base;
525 sregs.gdt.limit = env->gdt.limit;
526 sregs.gdt.base = env->gdt.base;
527
528 sregs.cr0 = env->cr[0];
529 sregs.cr2 = env->cr[2];
530 sregs.cr3 = env->cr[3];
531 sregs.cr4 = env->cr[4];
532
533 sregs.cr8 = cpu_get_apic_tpr(env);
534 sregs.apic_base = cpu_get_apic_base(env);
535
536 sregs.efer = env->efer;
537
538 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
539}
540
541static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
542 uint32_t index, uint64_t value)
543{
544 entry->index = index;
545 entry->data = value;
546}
547
548static int kvm_put_msrs(CPUState *env)
549{
550 struct {
551 struct kvm_msrs info;
552 struct kvm_msr_entry entries[100];
553 } msr_data;
554 struct kvm_msr_entry *msrs = msr_data.entries;
555 int n = 0;
556
557 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
558 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
559 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
560 if (kvm_has_msr_star(env))
561 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
562 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
563#ifdef TARGET_X86_64
564 /* FIXME if lm capable */
565 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
566 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
567 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
568 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
569#endif
1a03675d
GC		 570 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
571 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
572
05330448
AL		 573 msr_data.info.nmsrs = n;
574
575 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
576
577}
578
579
580static int kvm_get_fpu(CPUState *env)
581{
582 struct kvm_fpu fpu;
583 int i, ret;
584
585 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
586 if (ret < 0)
587 return ret;
588
589 env->fpstt = (fpu.fsw >> 11) & 7;
590 env->fpus = fpu.fsw;
591 env->fpuc = fpu.fcw;
592 for (i = 0; i < 8; ++i)
593 env->fptags[i] = !((fpu.ftwx >> i) & 1);
594 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
595 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
596 env->mxcsr = fpu.mxcsr;
597
598 return 0;
599}
600
601static int kvm_get_sregs(CPUState *env)
602{
603 struct kvm_sregs sregs;
604 uint32_t hflags;
0e607a80 605 int bit, i, ret;
05330448
AL		 606
607 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
608 if (ret < 0)
609 return ret;
610
0e607a80
JK		 611 /* There can only be one pending IRQ set in the bitmap at a time, so try
612 to find it and save its number instead (-1 for none). */
613 env->interrupt_injected = -1;
614 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
615 if (sregs.interrupt_bitmap[i]) {
616 bit = ctz64(sregs.interrupt_bitmap[i]);
617 env->interrupt_injected = i * 64 + bit;
618 break;
619 }
620 }
05330448
AL		 621
622 get_seg(&env->segs[R_CS], &sregs.cs);
623 get_seg(&env->segs[R_DS], &sregs.ds);
624 get_seg(&env->segs[R_ES], &sregs.es);
625 get_seg(&env->segs[R_FS], &sregs.fs);
626 get_seg(&env->segs[R_GS], &sregs.gs);
627 get_seg(&env->segs[R_SS], &sregs.ss);
628
629 get_seg(&env->tr, &sregs.tr);
630 get_seg(&env->ldt, &sregs.ldt);
631
632 env->idt.limit = sregs.idt.limit;
633 env->idt.base = sregs.idt.base;
634 env->gdt.limit = sregs.gdt.limit;
635 env->gdt.base = sregs.gdt.base;
636
637 env->cr[0] = sregs.cr0;
638 env->cr[2] = sregs.cr2;
639 env->cr[3] = sregs.cr3;
640 env->cr[4] = sregs.cr4;
641
642 cpu_set_apic_base(env, sregs.apic_base);
643
644 env->efer = sregs.efer;
645 //cpu_set_apic_tpr(env, sregs.cr8);
646
647#define HFLAG_COPY_MASK ~( \
648 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
649 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
650 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
651 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
652
653
654
655 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
656 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
657 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
658 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
659 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
660 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
661 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
662
663 if (env->efer & MSR_EFER_LMA) {
664 hflags |= HF_LMA_MASK;
665 }
666
667 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
668 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
669 } else {
670 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
671 (DESC_B_SHIFT - HF_CS32_SHIFT);
672 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
673 (DESC_B_SHIFT - HF_SS32_SHIFT);
674 if (!(env->cr[0] & CR0_PE_MASK) ||
675 (env->eflags & VM_MASK) ||
676 !(hflags & HF_CS32_MASK)) {
677 hflags |= HF_ADDSEG_MASK;
678 } else {
679 hflags |= ((env->segs[R_DS].base |
680 env->segs[R_ES].base |
681 env->segs[R_SS].base) != 0) <<
682 HF_ADDSEG_SHIFT;
683 }
684 }
685 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 686
687 return 0;
688}
689
690static int kvm_get_msrs(CPUState *env)
691{
692 struct {
693 struct kvm_msrs info;
694 struct kvm_msr_entry entries[100];
695 } msr_data;
696 struct kvm_msr_entry *msrs = msr_data.entries;
697 int ret, i, n;
698
699 n = 0;
700 msrs[n++].index = MSR_IA32_SYSENTER_CS;
701 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
702 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
703 if (kvm_has_msr_star(env))
704 msrs[n++].index = MSR_STAR;
705 msrs[n++].index = MSR_IA32_TSC;
706#ifdef TARGET_X86_64
707 /* FIXME lm_capable_kernel */
708 msrs[n++].index = MSR_CSTAR;
709 msrs[n++].index = MSR_KERNELGSBASE;
710 msrs[n++].index = MSR_FMASK;
711 msrs[n++].index = MSR_LSTAR;
712#endif
1a03675d
GC		 713 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
714 msrs[n++].index = MSR_KVM_WALL_CLOCK;
715
05330448
AL		 716 msr_data.info.nmsrs = n;
717 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
718 if (ret < 0)
719 return ret;
720
721 for (i = 0; i < ret; i++) {
722 switch (msrs[i].index) {
723 case MSR_IA32_SYSENTER_CS:
724 env->sysenter_cs = msrs[i].data;
725 break;
726 case MSR_IA32_SYSENTER_ESP:
727 env->sysenter_esp = msrs[i].data;
728 break;
729 case MSR_IA32_SYSENTER_EIP:
730 env->sysenter_eip = msrs[i].data;
731 break;
732 case MSR_STAR:
733 env->star = msrs[i].data;
734 break;
735#ifdef TARGET_X86_64
736 case MSR_CSTAR:
737 env->cstar = msrs[i].data;
738 break;
739 case MSR_KERNELGSBASE:
740 env->kernelgsbase = msrs[i].data;
741 break;
742 case MSR_FMASK:
743 env->fmask = msrs[i].data;
744 break;
745 case MSR_LSTAR:
746 env->lstar = msrs[i].data;
747 break;
748#endif
749 case MSR_IA32_TSC:
750 env->tsc = msrs[i].data;
751 break;
1a03675d
GC		 752 case MSR_KVM_SYSTEM_TIME:
753 env->system_time_msr = msrs[i].data;
754 break;
755 case MSR_KVM_WALL_CLOCK:
756 env->wall_clock_msr = msrs[i].data;
757 break;
05330448
AL		 758 }
759 }
760
761 return 0;
762}
763
9bdbe550
HB		 764static int kvm_put_mp_state(CPUState *env)
765{
766 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
767
768 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
769}
770
771static int kvm_get_mp_state(CPUState *env)
772{
773 struct kvm_mp_state mp_state;
774 int ret;
775
776 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
777 if (ret < 0) {
778 return ret;
779 }
780 env->mp_state = mp_state.mp_state;
781 return 0;
782}
783
a0fb002c
JK		 784static int kvm_put_vcpu_events(CPUState *env)
785{
786#ifdef KVM_CAP_VCPU_EVENTS
787 struct kvm_vcpu_events events;
788
789 if (!kvm_has_vcpu_events()) {
790 return 0;
791 }
792
31827373
JK		 793 events.exception.injected = (env->exception_injected >= 0);
794 events.exception.nr = env->exception_injected;
a0fb002c
JK		 795 events.exception.has_error_code = env->has_error_code;
796 events.exception.error_code = env->error_code;
797
798 events.interrupt.injected = (env->interrupt_injected >= 0);
799 events.interrupt.nr = env->interrupt_injected;
800 events.interrupt.soft = env->soft_interrupt;
801
802 events.nmi.injected = env->nmi_injected;
803 events.nmi.pending = env->nmi_pending;
804 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
805
806 events.sipi_vector = env->sipi_vector;
807
aee028b9
JK		 808 events.flags =
809 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
810
a0fb002c
JK		 811 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
812#else
813 return 0;
814#endif
815}
816
817static int kvm_get_vcpu_events(CPUState *env)
818{
819#ifdef KVM_CAP_VCPU_EVENTS
820 struct kvm_vcpu_events events;
821 int ret;
822
823 if (!kvm_has_vcpu_events()) {
824 return 0;
825 }
826
827 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
828 if (ret < 0) {
829 return ret;
830 }
31827373 831 env->exception_injected =
a0fb002c
JK		 832 events.exception.injected ? events.exception.nr : -1;
833 env->has_error_code = events.exception.has_error_code;
834 env->error_code = events.exception.error_code;
835
836 env->interrupt_injected =
837 events.interrupt.injected ? events.interrupt.nr : -1;
838 env->soft_interrupt = events.interrupt.soft;
839
840 env->nmi_injected = events.nmi.injected;
841 env->nmi_pending = events.nmi.pending;
842 if (events.nmi.masked) {
843 env->hflags2 |= HF2_NMI_MASK;
844 } else {
845 env->hflags2 &= ~HF2_NMI_MASK;
846 }
847
848 env->sipi_vector = events.sipi_vector;
849#endif
850
851 return 0;
852}
853
05330448
AL		 854int kvm_arch_put_registers(CPUState *env)
855{
856 int ret;
857
858 ret = kvm_getput_regs(env, 1);
859 if (ret < 0)
860 return ret;
861
862 ret = kvm_put_fpu(env);
863 if (ret < 0)
864 return ret;
865
866 ret = kvm_put_sregs(env);
867 if (ret < 0)
868 return ret;
869
870 ret = kvm_put_msrs(env);
871 if (ret < 0)
872 return ret;
873
f8d926e9
JK		 874 ret = kvm_put_mp_state(env);
875 if (ret < 0)
876 return ret;
877
a0fb002c
JK		 878 ret = kvm_put_vcpu_events(env);
879 if (ret < 0)
880 return ret;
881
05330448
AL		 882 return 0;
883}
884
885int kvm_arch_get_registers(CPUState *env)
886{
887 int ret;
888
889 ret = kvm_getput_regs(env, 0);
890 if (ret < 0)
891 return ret;
892
893 ret = kvm_get_fpu(env);
894 if (ret < 0)
895 return ret;
896
897 ret = kvm_get_sregs(env);
898 if (ret < 0)
899 return ret;
900
901 ret = kvm_get_msrs(env);
902 if (ret < 0)
903 return ret;
904
5a2e3c2e
JK		 905 ret = kvm_get_mp_state(env);
906 if (ret < 0)
907 return ret;
908
a0fb002c
JK		 909 ret = kvm_get_vcpu_events(env);
910 if (ret < 0)
911 return ret;
912
05330448
AL		 913 return 0;
914}
915
916int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
917{
918 /* Try to inject an interrupt if the guest can accept it */
919 if (run->ready_for_interrupt_injection &&
920 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
921 (env->eflags & IF_MASK)) {
922 int irq;
923
924 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
925 irq = cpu_get_pic_interrupt(env);
926 if (irq >= 0) {
927 struct kvm_interrupt intr;
928 intr.irq = irq;
929 /* FIXME: errors */
930 dprintf("injected interrupt %d\n", irq);
931 kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
932 }
933 }
934
935 /* If we have an interrupt but the guest is not ready to receive an
936 * interrupt, request an interrupt window exit. This will
937 * cause a return to userspace as soon as the guest is ready to
938 * receive interrupts. */
939 if ((env->interrupt_request & CPU_INTERRUPT_HARD))
940 run->request_interrupt_window = 1;
941 else
942 run->request_interrupt_window = 0;
943
944 dprintf("setting tpr\n");
945 run->cr8 = cpu_get_apic_tpr(env);
946
947 return 0;
948}
949
950int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
951{
952 if (run->if_flag)
953 env->eflags |= IF_MASK;
954 else
955 env->eflags &= ~IF_MASK;
956
957 cpu_set_apic_tpr(env, run->cr8);
958 cpu_set_apic_base(env, run->apic_base);
959
960 return 0;
961}
962
963static int kvm_handle_halt(CPUState *env)
964{
965 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
966 (env->eflags & IF_MASK)) &&
967 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
968 env->halted = 1;
969 env->exception_index = EXCP_HLT;
970 return 0;
971 }
972
973 return 1;
974}
975
976int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
977{
978 int ret = 0;
979
980 switch (run->exit_reason) {
981 case KVM_EXIT_HLT:
982 dprintf("handle_hlt\n");
983 ret = kvm_handle_halt(env);
984 break;
985 }
986
987 return ret;
988}
e22a25c9
AL		 989
990#ifdef KVM_CAP_SET_GUEST_DEBUG
e22a25c9
AL		 991int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
992{
38972938 993 static const uint8_t int3 = 0xcc;
64bf3f4e 994
e22a25c9 995 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
64bf3f4e 996 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
e22a25c9
AL		 997 return -EINVAL;
998 return 0;
999}
1000
1001int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1002{
1003 uint8_t int3;
1004
1005 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
64bf3f4e 1006 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
e22a25c9
AL		 1007 return -EINVAL;
1008 return 0;
1009}
1010
1011static struct {
1012 target_ulong addr;
1013 int len;
1014 int type;
1015} hw_breakpoint[4];
1016
1017static int nb_hw_breakpoint;
1018
1019static int find_hw_breakpoint(target_ulong addr, int len, int type)
1020{
1021 int n;
1022
1023 for (n = 0; n < nb_hw_breakpoint; n++)
1024 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1025 (hw_breakpoint[n].len == len || len == -1))
1026 return n;
1027 return -1;
1028}
1029
1030int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1031 target_ulong len, int type)
1032{
1033 switch (type) {
1034 case GDB_BREAKPOINT_HW:
1035 len = 1;
1036 break;
1037 case GDB_WATCHPOINT_WRITE:
1038 case GDB_WATCHPOINT_ACCESS:
1039 switch (len) {
1040 case 1:
1041 break;
1042 case 2:
1043 case 4:
1044 case 8:
1045 if (addr & (len - 1))
1046 return -EINVAL;
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
1051 break;
1052 default:
1053 return -ENOSYS;
1054 }
1055
1056 if (nb_hw_breakpoint == 4)
1057 return -ENOBUFS;
1058
1059 if (find_hw_breakpoint(addr, len, type) >= 0)
1060 return -EEXIST;
1061
1062 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1063 hw_breakpoint[nb_hw_breakpoint].len = len;
1064 hw_breakpoint[nb_hw_breakpoint].type = type;
1065 nb_hw_breakpoint++;
1066
1067 return 0;
1068}
1069
1070int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1071 target_ulong len, int type)
1072{
1073 int n;
1074
1075 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1076 if (n < 0)
1077 return -ENOENT;
1078
1079 nb_hw_breakpoint--;
1080 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1081
1082 return 0;
1083}
1084
1085void kvm_arch_remove_all_hw_breakpoints(void)
1086{
1087 nb_hw_breakpoint = 0;
1088}
1089
1090static CPUWatchpoint hw_watchpoint;
1091
1092int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1093{
1094 int handle = 0;
1095 int n;
1096
1097 if (arch_info->exception == 1) {
1098 if (arch_info->dr6 & (1 << 14)) {
1099 if (cpu_single_env->singlestep_enabled)
1100 handle = 1;
1101 } else {
1102 for (n = 0; n < 4; n++)
1103 if (arch_info->dr6 & (1 << n))
1104 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1105 case 0x0:
1106 handle = 1;
1107 break;
1108 case 0x1:
1109 handle = 1;
1110 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1111 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1112 hw_watchpoint.flags = BP_MEM_WRITE;
1113 break;
1114 case 0x3:
1115 handle = 1;
1116 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1117 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1118 hw_watchpoint.flags = BP_MEM_ACCESS;
1119 break;
1120 }
1121 }
1122 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1123 handle = 1;
1124
1125 if (!handle)
1126 kvm_update_guest_debug(cpu_single_env,
1127 (arch_info->exception == 1) ?
1128 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1129
1130 return handle;
1131}
1132
1133void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1134{
1135 const uint8_t type_code[] = {
1136 [GDB_BREAKPOINT_HW] = 0x0,
1137 [GDB_WATCHPOINT_WRITE] = 0x1,
1138 [GDB_WATCHPOINT_ACCESS] = 0x3
1139 };
1140 const uint8_t len_code[] = {
1141 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1142 };
1143 int n;
1144
1145 if (kvm_sw_breakpoints_active(env))
1146 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1147
1148 if (nb_hw_breakpoint > 0) {
1149 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1150 dbg->arch.debugreg[7] = 0x0600;
1151 for (n = 0; n < nb_hw_breakpoint; n++) {
1152 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1153 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1154 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1155 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1156 }
1157 }
1158}
1159#endif /* KVM_CAP_SET_GUEST_DEBUG */
Qemu copy for testing