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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
18 | ||
19 | #include <linux/kvm.h> | |
20 | ||
21 | #include "qemu-common.h" | |
22 | #include "sysemu.h" | |
23 | #include "kvm.h" | |
24 | #include "cpu.h" | |
e22a25c9 | 25 | #include "gdbstub.h" |
0e607a80 | 26 | #include "host-utils.h" |
4c5b10b7 | 27 | #include "hw/pc.h" |
408392b3 | 28 | #include "hw/apic.h" |
35bed8ee | 29 | #include "ioport.h" |
e7701825 | 30 | #include "kvm_x86.h" |
05330448 | 31 | |
bb0300dc GN |
32 | #ifdef CONFIG_KVM_PARA |
33 | #include <linux/kvm_para.h> | |
34 | #endif | |
35 | // | |
05330448 AL |
36 | //#define DEBUG_KVM |
37 | ||
38 | #ifdef DEBUG_KVM | |
8c0d577e | 39 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
40 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
41 | #else | |
8c0d577e | 42 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
43 | do { } while (0) |
44 | #endif | |
45 | ||
1a03675d GC |
46 | #define MSR_KVM_WALL_CLOCK 0x11 |
47 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
48 | ||
c0532a76 MT |
49 | #ifndef BUS_MCEERR_AR |
50 | #define BUS_MCEERR_AR 4 | |
51 | #endif | |
52 | #ifndef BUS_MCEERR_AO | |
53 | #define BUS_MCEERR_AO 5 | |
54 | #endif | |
55 | ||
b827df58 AK |
56 | #ifdef KVM_CAP_EXT_CPUID |
57 | ||
58 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
59 | { | |
60 | struct kvm_cpuid2 *cpuid; | |
61 | int r, size; | |
62 | ||
63 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
64 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
65 | cpuid->nent = max; | |
66 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
67 | if (r == 0 && cpuid->nent >= max) { |
68 | r = -E2BIG; | |
69 | } | |
b827df58 AK |
70 | if (r < 0) { |
71 | if (r == -E2BIG) { | |
72 | qemu_free(cpuid); | |
73 | return NULL; | |
74 | } else { | |
75 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
76 | strerror(-r)); | |
77 | exit(1); | |
78 | } | |
79 | } | |
80 | return cpuid; | |
81 | } | |
82 | ||
c958a8bd SY |
83 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
84 | uint32_t index, int reg) | |
b827df58 AK |
85 | { |
86 | struct kvm_cpuid2 *cpuid; | |
87 | int i, max; | |
88 | uint32_t ret = 0; | |
89 | uint32_t cpuid_1_edx; | |
90 | ||
91 | if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) { | |
92 | return -1U; | |
93 | } | |
94 | ||
95 | max = 1; | |
96 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
97 | max *= 2; | |
98 | } | |
99 | ||
100 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
101 | if (cpuid->entries[i].function == function && |
102 | cpuid->entries[i].index == index) { | |
b827df58 AK |
103 | switch (reg) { |
104 | case R_EAX: | |
105 | ret = cpuid->entries[i].eax; | |
106 | break; | |
107 | case R_EBX: | |
108 | ret = cpuid->entries[i].ebx; | |
109 | break; | |
110 | case R_ECX: | |
111 | ret = cpuid->entries[i].ecx; | |
112 | break; | |
113 | case R_EDX: | |
114 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
115 | switch (function) { |
116 | case 1: | |
117 | /* KVM before 2.6.30 misreports the following features */ | |
118 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
119 | break; | |
120 | case 0x80000001: | |
b827df58 AK |
121 | /* On Intel, kvm returns cpuid according to the Intel spec, |
122 | * so add missing bits according to the AMD spec: | |
123 | */ | |
c958a8bd | 124 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 125 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 126 | break; |
b827df58 AK |
127 | } |
128 | break; | |
129 | } | |
130 | } | |
131 | } | |
132 | ||
133 | qemu_free(cpuid); | |
134 | ||
135 | return ret; | |
136 | } | |
137 | ||
138 | #else | |
139 | ||
c958a8bd SY |
140 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
141 | uint32_t index, int reg) | |
b827df58 AK |
142 | { |
143 | return -1U; | |
144 | } | |
145 | ||
146 | #endif | |
147 | ||
bb0300dc GN |
148 | #ifdef CONFIG_KVM_PARA |
149 | struct kvm_para_features { | |
150 | int cap; | |
151 | int feature; | |
152 | } para_features[] = { | |
153 | #ifdef KVM_CAP_CLOCKSOURCE | |
154 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
155 | #endif | |
156 | #ifdef KVM_CAP_NOP_IO_DELAY | |
157 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
158 | #endif | |
159 | #ifdef KVM_CAP_PV_MMU | |
160 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
bb0300dc GN |
161 | #endif |
162 | { -1, -1 } | |
163 | }; | |
164 | ||
165 | static int get_para_features(CPUState *env) | |
166 | { | |
167 | int i, features = 0; | |
168 | ||
169 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
170 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) | |
171 | features |= (1 << para_features[i].feature); | |
172 | } | |
173 | ||
174 | return features; | |
175 | } | |
176 | #endif | |
177 | ||
e7701825 MT |
178 | #ifdef KVM_CAP_MCE |
179 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, | |
180 | int *max_banks) | |
181 | { | |
182 | int r; | |
183 | ||
184 | r = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_MCE); | |
185 | if (r > 0) { | |
186 | *max_banks = r; | |
187 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
188 | } | |
189 | return -ENOSYS; | |
190 | } | |
191 | ||
192 | static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap) | |
193 | { | |
194 | return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap); | |
195 | } | |
196 | ||
197 | static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m) | |
198 | { | |
199 | return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m); | |
200 | } | |
201 | ||
c0532a76 MT |
202 | static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n) |
203 | { | |
204 | struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs); | |
205 | int r; | |
206 | ||
207 | kmsrs->nmsrs = n; | |
208 | memcpy(kmsrs->entries, msrs, n * sizeof *msrs); | |
209 | r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs); | |
210 | memcpy(msrs, kmsrs->entries, n * sizeof *msrs); | |
211 | free(kmsrs); | |
212 | return r; | |
213 | } | |
214 | ||
215 | /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */ | |
216 | static int kvm_mce_in_exception(CPUState *env) | |
217 | { | |
218 | struct kvm_msr_entry msr_mcg_status = { | |
219 | .index = MSR_MCG_STATUS, | |
220 | }; | |
221 | int r; | |
222 | ||
223 | r = kvm_get_msr(env, &msr_mcg_status, 1); | |
224 | if (r == -1 || r == 0) { | |
225 | return -1; | |
226 | } | |
227 | return !!(msr_mcg_status.data & MCG_STATUS_MCIP); | |
228 | } | |
229 | ||
e7701825 MT |
230 | struct kvm_x86_mce_data |
231 | { | |
232 | CPUState *env; | |
233 | struct kvm_x86_mce *mce; | |
c0532a76 | 234 | int abort_on_error; |
e7701825 MT |
235 | }; |
236 | ||
237 | static void kvm_do_inject_x86_mce(void *_data) | |
238 | { | |
239 | struct kvm_x86_mce_data *data = _data; | |
240 | int r; | |
241 | ||
f8502cfb HS |
242 | /* If there is an MCE exception being processed, ignore this SRAO MCE */ |
243 | if ((data->env->mcg_cap & MCG_SER_P) && | |
244 | !(data->mce->status & MCI_STATUS_AR)) { | |
245 | r = kvm_mce_in_exception(data->env); | |
246 | if (r == -1) { | |
247 | fprintf(stderr, "Failed to get MCE status\n"); | |
248 | } else if (r) { | |
249 | return; | |
250 | } | |
251 | } | |
c0532a76 | 252 | |
e7701825 | 253 | r = kvm_set_mce(data->env, data->mce); |
c0532a76 | 254 | if (r < 0) { |
e7701825 | 255 | perror("kvm_set_mce FAILED"); |
c0532a76 MT |
256 | if (data->abort_on_error) { |
257 | abort(); | |
258 | } | |
259 | } | |
e7701825 MT |
260 | } |
261 | #endif | |
262 | ||
263 | void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, | |
c0532a76 MT |
264 | uint64_t mcg_status, uint64_t addr, uint64_t misc, |
265 | int abort_on_error) | |
e7701825 MT |
266 | { |
267 | #ifdef KVM_CAP_MCE | |
268 | struct kvm_x86_mce mce = { | |
269 | .bank = bank, | |
270 | .status = status, | |
271 | .mcg_status = mcg_status, | |
272 | .addr = addr, | |
273 | .misc = misc, | |
274 | }; | |
275 | struct kvm_x86_mce_data data = { | |
276 | .env = cenv, | |
277 | .mce = &mce, | |
278 | }; | |
279 | ||
c0532a76 MT |
280 | if (!cenv->mcg_cap) { |
281 | fprintf(stderr, "MCE support is not enabled!\n"); | |
282 | return; | |
283 | } | |
284 | ||
e7701825 | 285 | run_on_cpu(cenv, kvm_do_inject_x86_mce, &data); |
c0532a76 MT |
286 | #else |
287 | if (abort_on_error) | |
288 | abort(); | |
e7701825 MT |
289 | #endif |
290 | } | |
291 | ||
05330448 AL |
292 | int kvm_arch_init_vcpu(CPUState *env) |
293 | { | |
294 | struct { | |
486bd5a2 AL |
295 | struct kvm_cpuid2 cpuid; |
296 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 297 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 298 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 299 | uint32_t unused; |
bb0300dc GN |
300 | struct kvm_cpuid_entry2 *c; |
301 | #ifdef KVM_CPUID_SIGNATURE | |
302 | uint32_t signature[3]; | |
303 | #endif | |
05330448 | 304 | |
f8d926e9 JK |
305 | env->mp_state = KVM_MP_STATE_RUNNABLE; |
306 | ||
c958a8bd | 307 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
308 | |
309 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 310 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
311 | env->cpuid_ext_features |= i; |
312 | ||
457dfed6 | 313 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 314 | 0, R_EDX); |
457dfed6 | 315 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 316 | 0, R_ECX); |
296acb64 JR |
317 | env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A, |
318 | 0, R_EDX); | |
319 | ||
6c1f42fe | 320 | |
05330448 AL |
321 | cpuid_i = 0; |
322 | ||
bb0300dc GN |
323 | #ifdef CONFIG_KVM_PARA |
324 | /* Paravirtualization CPUIDs */ | |
325 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
326 | c = &cpuid_data.entries[cpuid_i++]; | |
327 | memset(c, 0, sizeof(*c)); | |
328 | c->function = KVM_CPUID_SIGNATURE; | |
329 | c->eax = 0; | |
330 | c->ebx = signature[0]; | |
331 | c->ecx = signature[1]; | |
332 | c->edx = signature[2]; | |
333 | ||
334 | c = &cpuid_data.entries[cpuid_i++]; | |
335 | memset(c, 0, sizeof(*c)); | |
336 | c->function = KVM_CPUID_FEATURES; | |
337 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
338 | #endif | |
339 | ||
a33609ca | 340 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
341 | |
342 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 343 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
344 | |
345 | switch (i) { | |
a36b1029 AL |
346 | case 2: { |
347 | /* Keep reading function 2 till all the input is received */ | |
348 | int times; | |
349 | ||
a36b1029 | 350 | c->function = i; |
a33609ca AL |
351 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
352 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
353 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
354 | times = c->eax & 0xff; | |
a36b1029 AL |
355 | |
356 | for (j = 1; j < times; ++j) { | |
a33609ca | 357 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 358 | c->function = i; |
a33609ca AL |
359 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
360 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
361 | } |
362 | break; | |
363 | } | |
486bd5a2 AL |
364 | case 4: |
365 | case 0xb: | |
366 | case 0xd: | |
367 | for (j = 0; ; j++) { | |
486bd5a2 AL |
368 | c->function = i; |
369 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
370 | c->index = j; | |
a33609ca | 371 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 372 | |
a33609ca | 373 | if (i == 4 && c->eax == 0) |
486bd5a2 | 374 | break; |
a33609ca | 375 | if (i == 0xb && !(c->ecx & 0xff00)) |
486bd5a2 | 376 | break; |
a33609ca | 377 | if (i == 0xd && c->eax == 0) |
486bd5a2 | 378 | break; |
a33609ca AL |
379 | |
380 | c = &cpuid_data.entries[cpuid_i++]; | |
486bd5a2 AL |
381 | } |
382 | break; | |
383 | default: | |
486bd5a2 | 384 | c->function = i; |
a33609ca AL |
385 | c->flags = 0; |
386 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
387 | break; |
388 | } | |
05330448 | 389 | } |
a33609ca | 390 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
391 | |
392 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 393 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 394 | |
05330448 | 395 | c->function = i; |
a33609ca AL |
396 | c->flags = 0; |
397 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
398 | } |
399 | ||
400 | cpuid_data.cpuid.nent = cpuid_i; | |
401 | ||
e7701825 MT |
402 | #ifdef KVM_CAP_MCE |
403 | if (((env->cpuid_version >> 8)&0xF) >= 6 | |
404 | && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) | |
405 | && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) { | |
406 | uint64_t mcg_cap; | |
407 | int banks; | |
408 | ||
409 | if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) | |
410 | perror("kvm_get_mce_cap_supported FAILED"); | |
411 | else { | |
412 | if (banks > MCE_BANKS_DEF) | |
413 | banks = MCE_BANKS_DEF; | |
414 | mcg_cap &= MCE_CAP_DEF; | |
415 | mcg_cap |= banks; | |
416 | if (kvm_setup_mce(env, &mcg_cap)) | |
417 | perror("kvm_setup_mce FAILED"); | |
418 | else | |
419 | env->mcg_cap = mcg_cap; | |
420 | } | |
421 | } | |
422 | #endif | |
423 | ||
486bd5a2 | 424 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
425 | } |
426 | ||
caa5af0f JK |
427 | void kvm_arch_reset_vcpu(CPUState *env) |
428 | { | |
e73223a5 | 429 | env->exception_injected = -1; |
0e607a80 | 430 | env->interrupt_injected = -1; |
a0fb002c JK |
431 | env->nmi_injected = 0; |
432 | env->nmi_pending = 0; | |
ddced198 MT |
433 | if (kvm_irqchip_in_kernel()) { |
434 | env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : | |
435 | KVM_MP_STATE_UNINITIALIZED; | |
436 | } else { | |
437 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
438 | } | |
caa5af0f JK |
439 | } |
440 | ||
05330448 AL |
441 | static int kvm_has_msr_star(CPUState *env) |
442 | { | |
443 | static int has_msr_star; | |
444 | int ret; | |
445 | ||
446 | /* first time */ | |
447 | if (has_msr_star == 0) { | |
448 | struct kvm_msr_list msr_list, *kvm_msr_list; | |
449 | ||
450 | has_msr_star = -1; | |
451 | ||
452 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
453 | * save/restore */ | |
4c9f7372 | 454 | msr_list.nmsrs = 0; |
05330448 | 455 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 456 | if (ret < 0 && ret != -E2BIG) { |
05330448 | 457 | return 0; |
6fb6d245 | 458 | } |
d9db889f JK |
459 | /* Old kernel modules had a bug and could write beyond the provided |
460 | memory. Allocate at least a safe amount of 1K. */ | |
461 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
462 | msr_list.nmsrs * | |
463 | sizeof(msr_list.indices[0]))); | |
05330448 | 464 | |
55308450 | 465 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
05330448 AL |
466 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
467 | if (ret >= 0) { | |
468 | int i; | |
469 | ||
470 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
471 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
472 | has_msr_star = 1; | |
473 | break; | |
474 | } | |
475 | } | |
476 | } | |
477 | ||
478 | free(kvm_msr_list); | |
479 | } | |
480 | ||
481 | if (has_msr_star == 1) | |
482 | return 1; | |
483 | return 0; | |
484 | } | |
485 | ||
20420430 SY |
486 | static int kvm_init_identity_map_page(KVMState *s) |
487 | { | |
488 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR | |
489 | int ret; | |
490 | uint64_t addr = 0xfffbc000; | |
491 | ||
492 | if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
493 | return 0; | |
494 | } | |
495 | ||
496 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr); | |
497 | if (ret < 0) { | |
498 | fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret)); | |
499 | return ret; | |
500 | } | |
501 | #endif | |
502 | return 0; | |
503 | } | |
504 | ||
05330448 AL |
505 | int kvm_arch_init(KVMState *s, int smp_cpus) |
506 | { | |
507 | int ret; | |
508 | ||
509 | /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code | |
510 | * directly. In order to use vm86 mode, a TSS is needed. Since this | |
511 | * must be part of guest physical memory, we need to allocate it. Older | |
512 | * versions of KVM just assumed that it would be at the end of physical | |
513 | * memory but that doesn't work with more than 4GB of memory. We simply | |
514 | * refuse to work with those older versions of KVM. */ | |
984b5181 | 515 | ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR); |
05330448 AL |
516 | if (ret <= 0) { |
517 | fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n"); | |
518 | return ret; | |
519 | } | |
520 | ||
521 | /* this address is 3 pages before the bios, and the bios should present | |
522 | * as unavaible memory. FIXME, need to ensure the e820 map deals with | |
523 | * this? | |
524 | */ | |
4c5b10b7 JS |
525 | /* |
526 | * Tell fw_cfg to notify the BIOS to reserve the range. | |
527 | */ | |
528 | if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) { | |
529 | perror("e820_add_entry() table is full"); | |
530 | exit(1); | |
531 | } | |
20420430 SY |
532 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000); |
533 | if (ret < 0) { | |
534 | return ret; | |
535 | } | |
536 | ||
537 | return kvm_init_identity_map_page(s); | |
05330448 AL |
538 | } |
539 | ||
540 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
541 | { | |
542 | lhs->selector = rhs->selector; | |
543 | lhs->base = rhs->base; | |
544 | lhs->limit = rhs->limit; | |
545 | lhs->type = 3; | |
546 | lhs->present = 1; | |
547 | lhs->dpl = 3; | |
548 | lhs->db = 0; | |
549 | lhs->s = 1; | |
550 | lhs->l = 0; | |
551 | lhs->g = 0; | |
552 | lhs->avl = 0; | |
553 | lhs->unusable = 0; | |
554 | } | |
555 | ||
556 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
557 | { | |
558 | unsigned flags = rhs->flags; | |
559 | lhs->selector = rhs->selector; | |
560 | lhs->base = rhs->base; | |
561 | lhs->limit = rhs->limit; | |
562 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
563 | lhs->present = (flags & DESC_P_MASK) != 0; | |
564 | lhs->dpl = rhs->selector & 3; | |
565 | lhs->db = (flags >> DESC_B_SHIFT) & 1; | |
566 | lhs->s = (flags & DESC_S_MASK) != 0; | |
567 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
568 | lhs->g = (flags & DESC_G_MASK) != 0; | |
569 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
570 | lhs->unusable = 0; | |
571 | } | |
572 | ||
573 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
574 | { | |
575 | lhs->selector = rhs->selector; | |
576 | lhs->base = rhs->base; | |
577 | lhs->limit = rhs->limit; | |
578 | lhs->flags = | |
579 | (rhs->type << DESC_TYPE_SHIFT) | |
580 | | (rhs->present * DESC_P_MASK) | |
581 | | (rhs->dpl << DESC_DPL_SHIFT) | |
582 | | (rhs->db << DESC_B_SHIFT) | |
583 | | (rhs->s * DESC_S_MASK) | |
584 | | (rhs->l << DESC_L_SHIFT) | |
585 | | (rhs->g * DESC_G_MASK) | |
586 | | (rhs->avl * DESC_AVL_MASK); | |
587 | } | |
588 | ||
589 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
590 | { | |
591 | if (set) | |
592 | *kvm_reg = *qemu_reg; | |
593 | else | |
594 | *qemu_reg = *kvm_reg; | |
595 | } | |
596 | ||
597 | static int kvm_getput_regs(CPUState *env, int set) | |
598 | { | |
599 | struct kvm_regs regs; | |
600 | int ret = 0; | |
601 | ||
602 | if (!set) { | |
603 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
604 | if (ret < 0) | |
605 | return ret; | |
606 | } | |
607 | ||
608 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
609 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
610 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
611 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
612 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
613 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
614 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
615 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
616 | #ifdef TARGET_X86_64 | |
617 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
618 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
619 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
620 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
621 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
622 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
623 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
624 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
625 | #endif | |
626 | ||
627 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
628 | kvm_getput_reg(®s.rip, &env->eip, set); | |
629 | ||
630 | if (set) | |
631 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
632 | ||
633 | return ret; | |
634 | } | |
635 | ||
636 | static int kvm_put_fpu(CPUState *env) | |
637 | { | |
638 | struct kvm_fpu fpu; | |
639 | int i; | |
640 | ||
641 | memset(&fpu, 0, sizeof fpu); | |
642 | fpu.fsw = env->fpus & ~(7 << 11); | |
643 | fpu.fsw |= (env->fpstt & 7) << 11; | |
644 | fpu.fcw = env->fpuc; | |
645 | for (i = 0; i < 8; ++i) | |
646 | fpu.ftwx |= (!env->fptags[i]) << i; | |
647 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); | |
648 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
649 | fpu.mxcsr = env->mxcsr; | |
650 | ||
651 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
652 | } | |
653 | ||
f1665b21 SY |
654 | #ifdef KVM_CAP_XSAVE |
655 | #define XSAVE_CWD_RIP 2 | |
656 | #define XSAVE_CWD_RDP 4 | |
657 | #define XSAVE_MXCSR 6 | |
658 | #define XSAVE_ST_SPACE 8 | |
659 | #define XSAVE_XMM_SPACE 40 | |
660 | #define XSAVE_XSTATE_BV 128 | |
661 | #define XSAVE_YMMH_SPACE 144 | |
662 | #endif | |
663 | ||
664 | static int kvm_put_xsave(CPUState *env) | |
665 | { | |
666 | #ifdef KVM_CAP_XSAVE | |
0f53994f | 667 | int i, r; |
f1665b21 SY |
668 | struct kvm_xsave* xsave; |
669 | uint16_t cwd, swd, twd, fop; | |
670 | ||
671 | if (!kvm_has_xsave()) | |
672 | return kvm_put_fpu(env); | |
673 | ||
674 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
675 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
676 | cwd = swd = twd = fop = 0; | |
677 | swd = env->fpus & ~(7 << 11); | |
678 | swd |= (env->fpstt & 7) << 11; | |
679 | cwd = env->fpuc; | |
680 | for (i = 0; i < 8; ++i) | |
681 | twd |= (!env->fptags[i]) << i; | |
682 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; | |
683 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
684 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
685 | sizeof env->fpregs); | |
686 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
687 | sizeof env->xmm_regs); | |
688 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
689 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
690 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
691 | sizeof env->ymmh_regs); | |
0f53994f MT |
692 | r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
693 | qemu_free(xsave); | |
694 | return r; | |
f1665b21 SY |
695 | #else |
696 | return kvm_put_fpu(env); | |
697 | #endif | |
698 | } | |
699 | ||
700 | static int kvm_put_xcrs(CPUState *env) | |
701 | { | |
702 | #ifdef KVM_CAP_XCRS | |
703 | struct kvm_xcrs xcrs; | |
704 | ||
705 | if (!kvm_has_xcrs()) | |
706 | return 0; | |
707 | ||
708 | xcrs.nr_xcrs = 1; | |
709 | xcrs.flags = 0; | |
710 | xcrs.xcrs[0].xcr = 0; | |
711 | xcrs.xcrs[0].value = env->xcr0; | |
712 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
713 | #else | |
714 | return 0; | |
715 | #endif | |
716 | } | |
717 | ||
05330448 AL |
718 | static int kvm_put_sregs(CPUState *env) |
719 | { | |
720 | struct kvm_sregs sregs; | |
721 | ||
0e607a80 JK |
722 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
723 | if (env->interrupt_injected >= 0) { | |
724 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
725 | (uint64_t)1 << (env->interrupt_injected % 64); | |
726 | } | |
05330448 AL |
727 | |
728 | if ((env->eflags & VM_MASK)) { | |
729 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); | |
730 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
731 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
732 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
733 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
734 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
735 | } else { | |
736 | set_seg(&sregs.cs, &env->segs[R_CS]); | |
737 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
738 | set_seg(&sregs.es, &env->segs[R_ES]); | |
739 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
740 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
741 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
742 | ||
743 | if (env->cr[0] & CR0_PE_MASK) { | |
744 | /* force ss cpl to cs cpl */ | |
745 | sregs.ss.selector = (sregs.ss.selector & ~3) | | |
746 | (sregs.cs.selector & 3); | |
747 | sregs.ss.dpl = sregs.ss.selector & 3; | |
748 | } | |
749 | } | |
750 | ||
751 | set_seg(&sregs.tr, &env->tr); | |
752 | set_seg(&sregs.ldt, &env->ldt); | |
753 | ||
754 | sregs.idt.limit = env->idt.limit; | |
755 | sregs.idt.base = env->idt.base; | |
756 | sregs.gdt.limit = env->gdt.limit; | |
757 | sregs.gdt.base = env->gdt.base; | |
758 | ||
759 | sregs.cr0 = env->cr[0]; | |
760 | sregs.cr2 = env->cr[2]; | |
761 | sregs.cr3 = env->cr[3]; | |
762 | sregs.cr4 = env->cr[4]; | |
763 | ||
4a942cea BS |
764 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
765 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
766 | |
767 | sregs.efer = env->efer; | |
768 | ||
769 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
770 | } | |
771 | ||
772 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
773 | uint32_t index, uint64_t value) | |
774 | { | |
775 | entry->index = index; | |
776 | entry->data = value; | |
777 | } | |
778 | ||
ea643051 | 779 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
780 | { |
781 | struct { | |
782 | struct kvm_msrs info; | |
783 | struct kvm_msr_entry entries[100]; | |
784 | } msr_data; | |
785 | struct kvm_msr_entry *msrs = msr_data.entries; | |
d8da8574 | 786 | int n = 0; |
05330448 AL |
787 | |
788 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
789 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
790 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
791 | if (kvm_has_msr_star(env)) | |
792 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); | |
05330448 AL |
793 | #ifdef TARGET_X86_64 |
794 | /* FIXME if lm capable */ | |
795 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
796 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
797 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
798 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
799 | #endif | |
ea643051 JK |
800 | if (level == KVM_PUT_FULL_STATE) { |
801 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
802 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, | |
803 | env->system_time_msr); | |
804 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
805 | } | |
57780495 MT |
806 | #ifdef KVM_CAP_MCE |
807 | if (env->mcg_cap) { | |
d8da8574 | 808 | int i; |
57780495 MT |
809 | if (level == KVM_PUT_RESET_STATE) |
810 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); | |
811 | else if (level == KVM_PUT_FULL_STATE) { | |
812 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); | |
813 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
814 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) | |
815 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
816 | } | |
817 | } | |
818 | #endif | |
1a03675d | 819 | |
05330448 AL |
820 | msr_data.info.nmsrs = n; |
821 | ||
822 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
823 | ||
824 | } | |
825 | ||
826 | ||
827 | static int kvm_get_fpu(CPUState *env) | |
828 | { | |
829 | struct kvm_fpu fpu; | |
830 | int i, ret; | |
831 | ||
832 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
833 | if (ret < 0) | |
834 | return ret; | |
835 | ||
836 | env->fpstt = (fpu.fsw >> 11) & 7; | |
837 | env->fpus = fpu.fsw; | |
838 | env->fpuc = fpu.fcw; | |
839 | for (i = 0; i < 8; ++i) | |
840 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
841 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); | |
842 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
843 | env->mxcsr = fpu.mxcsr; | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
f1665b21 SY |
848 | static int kvm_get_xsave(CPUState *env) |
849 | { | |
850 | #ifdef KVM_CAP_XSAVE | |
851 | struct kvm_xsave* xsave; | |
852 | int ret, i; | |
853 | uint16_t cwd, swd, twd, fop; | |
854 | ||
855 | if (!kvm_has_xsave()) | |
856 | return kvm_get_fpu(env); | |
857 | ||
858 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
859 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
0f53994f MT |
860 | if (ret < 0) { |
861 | qemu_free(xsave); | |
f1665b21 | 862 | return ret; |
0f53994f | 863 | } |
f1665b21 SY |
864 | |
865 | cwd = (uint16_t)xsave->region[0]; | |
866 | swd = (uint16_t)(xsave->region[0] >> 16); | |
867 | twd = (uint16_t)xsave->region[1]; | |
868 | fop = (uint16_t)(xsave->region[1] >> 16); | |
869 | env->fpstt = (swd >> 11) & 7; | |
870 | env->fpus = swd; | |
871 | env->fpuc = cwd; | |
872 | for (i = 0; i < 8; ++i) | |
873 | env->fptags[i] = !((twd >> i) & 1); | |
874 | env->mxcsr = xsave->region[XSAVE_MXCSR]; | |
875 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
876 | sizeof env->fpregs); | |
877 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
878 | sizeof env->xmm_regs); | |
879 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
880 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
881 | sizeof env->ymmh_regs); | |
0f53994f | 882 | qemu_free(xsave); |
f1665b21 SY |
883 | return 0; |
884 | #else | |
885 | return kvm_get_fpu(env); | |
886 | #endif | |
887 | } | |
888 | ||
889 | static int kvm_get_xcrs(CPUState *env) | |
890 | { | |
891 | #ifdef KVM_CAP_XCRS | |
892 | int i, ret; | |
893 | struct kvm_xcrs xcrs; | |
894 | ||
895 | if (!kvm_has_xcrs()) | |
896 | return 0; | |
897 | ||
898 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
899 | if (ret < 0) | |
900 | return ret; | |
901 | ||
902 | for (i = 0; i < xcrs.nr_xcrs; i++) | |
903 | /* Only support xcr0 now */ | |
904 | if (xcrs.xcrs[0].xcr == 0) { | |
905 | env->xcr0 = xcrs.xcrs[0].value; | |
906 | break; | |
907 | } | |
908 | return 0; | |
909 | #else | |
910 | return 0; | |
911 | #endif | |
912 | } | |
913 | ||
05330448 AL |
914 | static int kvm_get_sregs(CPUState *env) |
915 | { | |
916 | struct kvm_sregs sregs; | |
917 | uint32_t hflags; | |
0e607a80 | 918 | int bit, i, ret; |
05330448 AL |
919 | |
920 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
921 | if (ret < 0) | |
922 | return ret; | |
923 | ||
0e607a80 JK |
924 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
925 | to find it and save its number instead (-1 for none). */ | |
926 | env->interrupt_injected = -1; | |
927 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
928 | if (sregs.interrupt_bitmap[i]) { | |
929 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
930 | env->interrupt_injected = i * 64 + bit; | |
931 | break; | |
932 | } | |
933 | } | |
05330448 AL |
934 | |
935 | get_seg(&env->segs[R_CS], &sregs.cs); | |
936 | get_seg(&env->segs[R_DS], &sregs.ds); | |
937 | get_seg(&env->segs[R_ES], &sregs.es); | |
938 | get_seg(&env->segs[R_FS], &sregs.fs); | |
939 | get_seg(&env->segs[R_GS], &sregs.gs); | |
940 | get_seg(&env->segs[R_SS], &sregs.ss); | |
941 | ||
942 | get_seg(&env->tr, &sregs.tr); | |
943 | get_seg(&env->ldt, &sregs.ldt); | |
944 | ||
945 | env->idt.limit = sregs.idt.limit; | |
946 | env->idt.base = sregs.idt.base; | |
947 | env->gdt.limit = sregs.gdt.limit; | |
948 | env->gdt.base = sregs.gdt.base; | |
949 | ||
950 | env->cr[0] = sregs.cr0; | |
951 | env->cr[2] = sregs.cr2; | |
952 | env->cr[3] = sregs.cr3; | |
953 | env->cr[4] = sregs.cr4; | |
954 | ||
4a942cea | 955 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
956 | |
957 | env->efer = sregs.efer; | |
4a942cea | 958 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 AL |
959 | |
960 | #define HFLAG_COPY_MASK ~( \ | |
961 | HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
962 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
963 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
964 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
965 | ||
966 | ||
967 | ||
968 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
969 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
970 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
971 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); | |
972 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); | |
973 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
974 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); | |
975 | ||
976 | if (env->efer & MSR_EFER_LMA) { | |
977 | hflags |= HF_LMA_MASK; | |
978 | } | |
979 | ||
980 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
981 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
982 | } else { | |
983 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
984 | (DESC_B_SHIFT - HF_CS32_SHIFT); | |
985 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> | |
986 | (DESC_B_SHIFT - HF_SS32_SHIFT); | |
987 | if (!(env->cr[0] & CR0_PE_MASK) || | |
988 | (env->eflags & VM_MASK) || | |
989 | !(hflags & HF_CS32_MASK)) { | |
990 | hflags |= HF_ADDSEG_MASK; | |
991 | } else { | |
992 | hflags |= ((env->segs[R_DS].base | | |
993 | env->segs[R_ES].base | | |
994 | env->segs[R_SS].base) != 0) << | |
995 | HF_ADDSEG_SHIFT; | |
996 | } | |
997 | } | |
998 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
999 | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static int kvm_get_msrs(CPUState *env) | |
1004 | { | |
1005 | struct { | |
1006 | struct kvm_msrs info; | |
1007 | struct kvm_msr_entry entries[100]; | |
1008 | } msr_data; | |
1009 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1010 | int ret, i, n; | |
1011 | ||
1012 | n = 0; | |
1013 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1014 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1015 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
1016 | if (kvm_has_msr_star(env)) | |
1017 | msrs[n++].index = MSR_STAR; | |
1018 | msrs[n++].index = MSR_IA32_TSC; | |
1019 | #ifdef TARGET_X86_64 | |
1020 | /* FIXME lm_capable_kernel */ | |
1021 | msrs[n++].index = MSR_CSTAR; | |
1022 | msrs[n++].index = MSR_KERNELGSBASE; | |
1023 | msrs[n++].index = MSR_FMASK; | |
1024 | msrs[n++].index = MSR_LSTAR; | |
1025 | #endif | |
1a03675d GC |
1026 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1027 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
1028 | ||
57780495 MT |
1029 | #ifdef KVM_CAP_MCE |
1030 | if (env->mcg_cap) { | |
1031 | msrs[n++].index = MSR_MCG_STATUS; | |
1032 | msrs[n++].index = MSR_MCG_CTL; | |
1033 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) | |
1034 | msrs[n++].index = MSR_MC0_CTL + i; | |
1035 | } | |
1036 | #endif | |
1037 | ||
05330448 AL |
1038 | msr_data.info.nmsrs = n; |
1039 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
1040 | if (ret < 0) | |
1041 | return ret; | |
1042 | ||
1043 | for (i = 0; i < ret; i++) { | |
1044 | switch (msrs[i].index) { | |
1045 | case MSR_IA32_SYSENTER_CS: | |
1046 | env->sysenter_cs = msrs[i].data; | |
1047 | break; | |
1048 | case MSR_IA32_SYSENTER_ESP: | |
1049 | env->sysenter_esp = msrs[i].data; | |
1050 | break; | |
1051 | case MSR_IA32_SYSENTER_EIP: | |
1052 | env->sysenter_eip = msrs[i].data; | |
1053 | break; | |
1054 | case MSR_STAR: | |
1055 | env->star = msrs[i].data; | |
1056 | break; | |
1057 | #ifdef TARGET_X86_64 | |
1058 | case MSR_CSTAR: | |
1059 | env->cstar = msrs[i].data; | |
1060 | break; | |
1061 | case MSR_KERNELGSBASE: | |
1062 | env->kernelgsbase = msrs[i].data; | |
1063 | break; | |
1064 | case MSR_FMASK: | |
1065 | env->fmask = msrs[i].data; | |
1066 | break; | |
1067 | case MSR_LSTAR: | |
1068 | env->lstar = msrs[i].data; | |
1069 | break; | |
1070 | #endif | |
1071 | case MSR_IA32_TSC: | |
1072 | env->tsc = msrs[i].data; | |
1073 | break; | |
1a03675d GC |
1074 | case MSR_KVM_SYSTEM_TIME: |
1075 | env->system_time_msr = msrs[i].data; | |
1076 | break; | |
1077 | case MSR_KVM_WALL_CLOCK: | |
1078 | env->wall_clock_msr = msrs[i].data; | |
1079 | break; | |
57780495 MT |
1080 | #ifdef KVM_CAP_MCE |
1081 | case MSR_MCG_STATUS: | |
1082 | env->mcg_status = msrs[i].data; | |
1083 | break; | |
1084 | case MSR_MCG_CTL: | |
1085 | env->mcg_ctl = msrs[i].data; | |
1086 | break; | |
1087 | #endif | |
1088 | default: | |
1089 | #ifdef KVM_CAP_MCE | |
1090 | if (msrs[i].index >= MSR_MC0_CTL && | |
1091 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1092 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 MT |
1093 | } |
1094 | #endif | |
d8da8574 | 1095 | break; |
05330448 AL |
1096 | } |
1097 | } | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
9bdbe550 HB |
1102 | static int kvm_put_mp_state(CPUState *env) |
1103 | { | |
1104 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
1105 | ||
1106 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
1107 | } | |
1108 | ||
1109 | static int kvm_get_mp_state(CPUState *env) | |
1110 | { | |
1111 | struct kvm_mp_state mp_state; | |
1112 | int ret; | |
1113 | ||
1114 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
1115 | if (ret < 0) { | |
1116 | return ret; | |
1117 | } | |
1118 | env->mp_state = mp_state.mp_state; | |
1119 | return 0; | |
1120 | } | |
1121 | ||
ea643051 | 1122 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
1123 | { |
1124 | #ifdef KVM_CAP_VCPU_EVENTS | |
1125 | struct kvm_vcpu_events events; | |
1126 | ||
1127 | if (!kvm_has_vcpu_events()) { | |
1128 | return 0; | |
1129 | } | |
1130 | ||
31827373 JK |
1131 | events.exception.injected = (env->exception_injected >= 0); |
1132 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1133 | events.exception.has_error_code = env->has_error_code; |
1134 | events.exception.error_code = env->error_code; | |
1135 | ||
1136 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1137 | events.interrupt.nr = env->interrupt_injected; | |
1138 | events.interrupt.soft = env->soft_interrupt; | |
1139 | ||
1140 | events.nmi.injected = env->nmi_injected; | |
1141 | events.nmi.pending = env->nmi_pending; | |
1142 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
1143 | ||
1144 | events.sipi_vector = env->sipi_vector; | |
1145 | ||
ea643051 JK |
1146 | events.flags = 0; |
1147 | if (level >= KVM_PUT_RESET_STATE) { | |
1148 | events.flags |= | |
1149 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1150 | } | |
aee028b9 | 1151 | |
a0fb002c JK |
1152 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
1153 | #else | |
1154 | return 0; | |
1155 | #endif | |
1156 | } | |
1157 | ||
1158 | static int kvm_get_vcpu_events(CPUState *env) | |
1159 | { | |
1160 | #ifdef KVM_CAP_VCPU_EVENTS | |
1161 | struct kvm_vcpu_events events; | |
1162 | int ret; | |
1163 | ||
1164 | if (!kvm_has_vcpu_events()) { | |
1165 | return 0; | |
1166 | } | |
1167 | ||
1168 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
1169 | if (ret < 0) { | |
1170 | return ret; | |
1171 | } | |
31827373 | 1172 | env->exception_injected = |
a0fb002c JK |
1173 | events.exception.injected ? events.exception.nr : -1; |
1174 | env->has_error_code = events.exception.has_error_code; | |
1175 | env->error_code = events.exception.error_code; | |
1176 | ||
1177 | env->interrupt_injected = | |
1178 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1179 | env->soft_interrupt = events.interrupt.soft; | |
1180 | ||
1181 | env->nmi_injected = events.nmi.injected; | |
1182 | env->nmi_pending = events.nmi.pending; | |
1183 | if (events.nmi.masked) { | |
1184 | env->hflags2 |= HF2_NMI_MASK; | |
1185 | } else { | |
1186 | env->hflags2 &= ~HF2_NMI_MASK; | |
1187 | } | |
1188 | ||
1189 | env->sipi_vector = events.sipi_vector; | |
1190 | #endif | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
b0b1d690 JK |
1195 | static int kvm_guest_debug_workarounds(CPUState *env) |
1196 | { | |
1197 | int ret = 0; | |
1198 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1199 | unsigned long reinject_trap = 0; | |
1200 | ||
1201 | if (!kvm_has_vcpu_events()) { | |
1202 | if (env->exception_injected == 1) { | |
1203 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1204 | } else if (env->exception_injected == 3) { | |
1205 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1206 | } | |
1207 | env->exception_injected = -1; | |
1208 | } | |
1209 | ||
1210 | /* | |
1211 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1212 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1213 | * by updating the debug state once again if single-stepping is on. | |
1214 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1215 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1216 | * reinject them via SET_GUEST_DEBUG. | |
1217 | */ | |
1218 | if (reinject_trap || | |
1219 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1220 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1221 | } | |
1222 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1223 | return ret; | |
1224 | } | |
1225 | ||
ff44f1a3 JK |
1226 | static int kvm_put_debugregs(CPUState *env) |
1227 | { | |
1228 | #ifdef KVM_CAP_DEBUGREGS | |
1229 | struct kvm_debugregs dbgregs; | |
1230 | int i; | |
1231 | ||
1232 | if (!kvm_has_debugregs()) { | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | for (i = 0; i < 4; i++) { | |
1237 | dbgregs.db[i] = env->dr[i]; | |
1238 | } | |
1239 | dbgregs.dr6 = env->dr[6]; | |
1240 | dbgregs.dr7 = env->dr[7]; | |
1241 | dbgregs.flags = 0; | |
1242 | ||
1243 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1244 | #else | |
1245 | return 0; | |
1246 | #endif | |
1247 | } | |
1248 | ||
1249 | static int kvm_get_debugregs(CPUState *env) | |
1250 | { | |
1251 | #ifdef KVM_CAP_DEBUGREGS | |
1252 | struct kvm_debugregs dbgregs; | |
1253 | int i, ret; | |
1254 | ||
1255 | if (!kvm_has_debugregs()) { | |
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1260 | if (ret < 0) { | |
1261 | return ret; | |
1262 | } | |
1263 | for (i = 0; i < 4; i++) { | |
1264 | env->dr[i] = dbgregs.db[i]; | |
1265 | } | |
1266 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1267 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1268 | #endif | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
ea375f9a | 1273 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1274 | { |
1275 | int ret; | |
1276 | ||
dbaa07c4 JK |
1277 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1278 | ||
05330448 AL |
1279 | ret = kvm_getput_regs(env, 1); |
1280 | if (ret < 0) | |
1281 | return ret; | |
1282 | ||
f1665b21 SY |
1283 | ret = kvm_put_xsave(env); |
1284 | if (ret < 0) | |
1285 | return ret; | |
1286 | ||
1287 | ret = kvm_put_xcrs(env); | |
05330448 AL |
1288 | if (ret < 0) |
1289 | return ret; | |
1290 | ||
1291 | ret = kvm_put_sregs(env); | |
1292 | if (ret < 0) | |
1293 | return ret; | |
1294 | ||
ea643051 | 1295 | ret = kvm_put_msrs(env, level); |
05330448 AL |
1296 | if (ret < 0) |
1297 | return ret; | |
1298 | ||
ea643051 JK |
1299 | if (level >= KVM_PUT_RESET_STATE) { |
1300 | ret = kvm_put_mp_state(env); | |
1301 | if (ret < 0) | |
1302 | return ret; | |
1303 | } | |
f8d926e9 | 1304 | |
ea643051 | 1305 | ret = kvm_put_vcpu_events(env, level); |
a0fb002c JK |
1306 | if (ret < 0) |
1307 | return ret; | |
1308 | ||
b0b1d690 JK |
1309 | /* must be last */ |
1310 | ret = kvm_guest_debug_workarounds(env); | |
1311 | if (ret < 0) | |
1312 | return ret; | |
1313 | ||
ff44f1a3 JK |
1314 | ret = kvm_put_debugregs(env); |
1315 | if (ret < 0) | |
1316 | return ret; | |
1317 | ||
05330448 AL |
1318 | return 0; |
1319 | } | |
1320 | ||
1321 | int kvm_arch_get_registers(CPUState *env) | |
1322 | { | |
1323 | int ret; | |
1324 | ||
dbaa07c4 JK |
1325 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1326 | ||
05330448 AL |
1327 | ret = kvm_getput_regs(env, 0); |
1328 | if (ret < 0) | |
1329 | return ret; | |
1330 | ||
f1665b21 SY |
1331 | ret = kvm_get_xsave(env); |
1332 | if (ret < 0) | |
1333 | return ret; | |
1334 | ||
1335 | ret = kvm_get_xcrs(env); | |
05330448 AL |
1336 | if (ret < 0) |
1337 | return ret; | |
1338 | ||
1339 | ret = kvm_get_sregs(env); | |
1340 | if (ret < 0) | |
1341 | return ret; | |
1342 | ||
1343 | ret = kvm_get_msrs(env); | |
1344 | if (ret < 0) | |
1345 | return ret; | |
1346 | ||
5a2e3c2e JK |
1347 | ret = kvm_get_mp_state(env); |
1348 | if (ret < 0) | |
1349 | return ret; | |
1350 | ||
a0fb002c JK |
1351 | ret = kvm_get_vcpu_events(env); |
1352 | if (ret < 0) | |
1353 | return ret; | |
1354 | ||
ff44f1a3 JK |
1355 | ret = kvm_get_debugregs(env); |
1356 | if (ret < 0) | |
1357 | return ret; | |
1358 | ||
05330448 AL |
1359 | return 0; |
1360 | } | |
1361 | ||
1362 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) | |
1363 | { | |
1364 | /* Try to inject an interrupt if the guest can accept it */ | |
1365 | if (run->ready_for_interrupt_injection && | |
1366 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1367 | (env->eflags & IF_MASK)) { | |
1368 | int irq; | |
1369 | ||
1370 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1371 | irq = cpu_get_pic_interrupt(env); | |
1372 | if (irq >= 0) { | |
1373 | struct kvm_interrupt intr; | |
1374 | intr.irq = irq; | |
1375 | /* FIXME: errors */ | |
8c0d577e | 1376 | DPRINTF("injected interrupt %d\n", irq); |
05330448 AL |
1377 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1378 | } | |
1379 | } | |
1380 | ||
1381 | /* If we have an interrupt but the guest is not ready to receive an | |
1382 | * interrupt, request an interrupt window exit. This will | |
1383 | * cause a return to userspace as soon as the guest is ready to | |
1384 | * receive interrupts. */ | |
1385 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) | |
1386 | run->request_interrupt_window = 1; | |
1387 | else | |
1388 | run->request_interrupt_window = 0; | |
1389 | ||
8c0d577e | 1390 | DPRINTF("setting tpr\n"); |
4a942cea | 1391 | run->cr8 = cpu_get_apic_tpr(env->apic_state); |
05330448 AL |
1392 | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
1397 | { | |
1398 | if (run->if_flag) | |
1399 | env->eflags |= IF_MASK; | |
1400 | else | |
1401 | env->eflags &= ~IF_MASK; | |
1402 | ||
4a942cea BS |
1403 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1404 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1405 | |
1406 | return 0; | |
1407 | } | |
1408 | ||
0af691d7 MT |
1409 | int kvm_arch_process_irqchip_events(CPUState *env) |
1410 | { | |
1411 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1412 | kvm_cpu_synchronize_state(env); | |
1413 | do_cpu_init(env); | |
1414 | env->exception_index = EXCP_HALTED; | |
1415 | } | |
1416 | ||
1417 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { | |
1418 | kvm_cpu_synchronize_state(env); | |
1419 | do_cpu_sipi(env); | |
1420 | } | |
1421 | ||
1422 | return env->halted; | |
1423 | } | |
1424 | ||
05330448 AL |
1425 | static int kvm_handle_halt(CPUState *env) |
1426 | { | |
1427 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1428 | (env->eflags & IF_MASK)) && | |
1429 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1430 | env->halted = 1; | |
1431 | env->exception_index = EXCP_HLT; | |
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | return 1; | |
1436 | } | |
1437 | ||
1438 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1439 | { | |
1440 | int ret = 0; | |
1441 | ||
1442 | switch (run->exit_reason) { | |
1443 | case KVM_EXIT_HLT: | |
8c0d577e | 1444 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1445 | ret = kvm_handle_halt(env); |
1446 | break; | |
1447 | } | |
1448 | ||
1449 | return ret; | |
1450 | } | |
e22a25c9 AL |
1451 | |
1452 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1453 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1454 | { | |
38972938 | 1455 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1456 | |
e22a25c9 | 1457 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
64bf3f4e | 1458 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) |
e22a25c9 AL |
1459 | return -EINVAL; |
1460 | return 0; | |
1461 | } | |
1462 | ||
1463 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1464 | { | |
1465 | uint8_t int3; | |
1466 | ||
1467 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
64bf3f4e | 1468 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) |
e22a25c9 AL |
1469 | return -EINVAL; |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static struct { | |
1474 | target_ulong addr; | |
1475 | int len; | |
1476 | int type; | |
1477 | } hw_breakpoint[4]; | |
1478 | ||
1479 | static int nb_hw_breakpoint; | |
1480 | ||
1481 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1482 | { | |
1483 | int n; | |
1484 | ||
1485 | for (n = 0; n < nb_hw_breakpoint; n++) | |
1486 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && | |
1487 | (hw_breakpoint[n].len == len || len == -1)) | |
1488 | return n; | |
1489 | return -1; | |
1490 | } | |
1491 | ||
1492 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1493 | target_ulong len, int type) | |
1494 | { | |
1495 | switch (type) { | |
1496 | case GDB_BREAKPOINT_HW: | |
1497 | len = 1; | |
1498 | break; | |
1499 | case GDB_WATCHPOINT_WRITE: | |
1500 | case GDB_WATCHPOINT_ACCESS: | |
1501 | switch (len) { | |
1502 | case 1: | |
1503 | break; | |
1504 | case 2: | |
1505 | case 4: | |
1506 | case 8: | |
1507 | if (addr & (len - 1)) | |
1508 | return -EINVAL; | |
1509 | break; | |
1510 | default: | |
1511 | return -EINVAL; | |
1512 | } | |
1513 | break; | |
1514 | default: | |
1515 | return -ENOSYS; | |
1516 | } | |
1517 | ||
1518 | if (nb_hw_breakpoint == 4) | |
1519 | return -ENOBUFS; | |
1520 | ||
1521 | if (find_hw_breakpoint(addr, len, type) >= 0) | |
1522 | return -EEXIST; | |
1523 | ||
1524 | hw_breakpoint[nb_hw_breakpoint].addr = addr; | |
1525 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1526 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1527 | nb_hw_breakpoint++; | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1533 | target_ulong len, int type) | |
1534 | { | |
1535 | int n; | |
1536 | ||
1537 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
1538 | if (n < 0) | |
1539 | return -ENOENT; | |
1540 | ||
1541 | nb_hw_breakpoint--; | |
1542 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1548 | { | |
1549 | nb_hw_breakpoint = 0; | |
1550 | } | |
1551 | ||
1552 | static CPUWatchpoint hw_watchpoint; | |
1553 | ||
1554 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1555 | { | |
1556 | int handle = 0; | |
1557 | int n; | |
1558 | ||
1559 | if (arch_info->exception == 1) { | |
1560 | if (arch_info->dr6 & (1 << 14)) { | |
1561 | if (cpu_single_env->singlestep_enabled) | |
1562 | handle = 1; | |
1563 | } else { | |
1564 | for (n = 0; n < 4; n++) | |
1565 | if (arch_info->dr6 & (1 << n)) | |
1566 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { | |
1567 | case 0x0: | |
1568 | handle = 1; | |
1569 | break; | |
1570 | case 0x1: | |
1571 | handle = 1; | |
1572 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1573 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1574 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1575 | break; | |
1576 | case 0x3: | |
1577 | handle = 1; | |
1578 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1579 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1580 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1581 | break; | |
1582 | } | |
1583 | } | |
1584 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) | |
1585 | handle = 1; | |
1586 | ||
b0b1d690 JK |
1587 | if (!handle) { |
1588 | cpu_synchronize_state(cpu_single_env); | |
1589 | assert(cpu_single_env->exception_injected == -1); | |
1590 | ||
1591 | cpu_single_env->exception_injected = arch_info->exception; | |
1592 | cpu_single_env->has_error_code = 0; | |
1593 | } | |
e22a25c9 AL |
1594 | |
1595 | return handle; | |
1596 | } | |
1597 | ||
1598 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1599 | { | |
1600 | const uint8_t type_code[] = { | |
1601 | [GDB_BREAKPOINT_HW] = 0x0, | |
1602 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1603 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1604 | }; | |
1605 | const uint8_t len_code[] = { | |
1606 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1607 | }; | |
1608 | int n; | |
1609 | ||
1610 | if (kvm_sw_breakpoints_active(env)) | |
1611 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; | |
1612 | ||
1613 | if (nb_hw_breakpoint > 0) { | |
1614 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1615 | dbg->arch.debugreg[7] = 0x0600; | |
1616 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1617 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1618 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1619 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
1620 | (len_code[hw_breakpoint[n].len] << (18 + n*4)); | |
1621 | } | |
1622 | } | |
f1665b21 SY |
1623 | /* Legal xcr0 for loading */ |
1624 | env->xcr0 = 1; | |
e22a25c9 AL |
1625 | } |
1626 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1627 | |
1628 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1629 | { | |
1630 | return !(env->cr[0] & CR0_PE_MASK) || | |
1631 | ((env->segs[R_CS].selector & 3) != 3); | |
1632 | } | |
1633 | ||
c0532a76 MT |
1634 | static void hardware_memory_error(void) |
1635 | { | |
1636 | fprintf(stderr, "Hardware memory error!\n"); | |
1637 | exit(1); | |
1638 | } | |
1639 | ||
f71ac88f HS |
1640 | #ifdef KVM_CAP_MCE |
1641 | static void kvm_mce_broadcast_rest(CPUState *env) | |
1642 | { | |
1643 | CPUState *cenv; | |
1644 | int family, model, cpuver = env->cpuid_version; | |
1645 | ||
1646 | family = (cpuver >> 8) & 0xf; | |
1647 | model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0xf); | |
1648 | ||
1649 | /* Broadcast MCA signal for processor version 06H_EH and above */ | |
1650 | if ((family == 6 && model >= 14) || family > 6) { | |
1651 | for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { | |
1652 | if (cenv == env) { | |
1653 | continue; | |
1654 | } | |
1655 | kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC, | |
1656 | MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1); | |
1657 | } | |
1658 | } | |
1659 | } | |
1660 | #endif | |
1661 | ||
c0532a76 MT |
1662 | int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
1663 | { | |
1664 | #if defined(KVM_CAP_MCE) | |
1665 | struct kvm_x86_mce mce = { | |
1666 | .bank = 9, | |
1667 | }; | |
1668 | void *vaddr; | |
1669 | ram_addr_t ram_addr; | |
1670 | target_phys_addr_t paddr; | |
1671 | int r; | |
1672 | ||
1673 | if ((env->mcg_cap & MCG_SER_P) && addr | |
1674 | && (code == BUS_MCEERR_AR | |
1675 | || code == BUS_MCEERR_AO)) { | |
1676 | if (code == BUS_MCEERR_AR) { | |
1677 | /* Fake an Intel architectural Data Load SRAR UCR */ | |
1678 | mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1679 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1680 | | MCI_STATUS_AR | 0x134; | |
1681 | mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; | |
1682 | mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; | |
1683 | } else { | |
1684 | /* | |
1685 | * If there is an MCE excpetion being processed, ignore | |
1686 | * this SRAO MCE | |
1687 | */ | |
1688 | r = kvm_mce_in_exception(env); | |
1689 | if (r == -1) { | |
1690 | fprintf(stderr, "Failed to get MCE status\n"); | |
1691 | } else if (r) { | |
1692 | return 0; | |
1693 | } | |
1694 | /* Fake an Intel architectural Memory scrubbing UCR */ | |
1695 | mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1696 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1697 | | 0xc0; | |
1698 | mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; | |
1699 | mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV; | |
1700 | } | |
1701 | vaddr = (void *)addr; | |
1702 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1703 | !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) { | |
1704 | fprintf(stderr, "Hardware memory error for memory used by " | |
1705 | "QEMU itself instead of guest system!\n"); | |
1706 | /* Hope we are lucky for AO MCE */ | |
1707 | if (code == BUS_MCEERR_AO) { | |
1708 | return 0; | |
1709 | } else { | |
1710 | hardware_memory_error(); | |
1711 | } | |
1712 | } | |
1713 | mce.addr = paddr; | |
1714 | r = kvm_set_mce(env, &mce); | |
1715 | if (r < 0) { | |
1716 | fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno)); | |
1717 | abort(); | |
1718 | } | |
f71ac88f | 1719 | kvm_mce_broadcast_rest(env); |
c0532a76 MT |
1720 | } else |
1721 | #endif | |
1722 | { | |
1723 | if (code == BUS_MCEERR_AO) { | |
1724 | return 0; | |
1725 | } else if (code == BUS_MCEERR_AR) { | |
1726 | hardware_memory_error(); | |
1727 | } else { | |
1728 | return 1; | |
1729 | } | |
1730 | } | |
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | int kvm_on_sigbus(int code, void *addr) | |
1735 | { | |
1736 | #if defined(KVM_CAP_MCE) | |
1737 | if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
1738 | uint64_t status; | |
1739 | void *vaddr; | |
1740 | ram_addr_t ram_addr; | |
1741 | target_phys_addr_t paddr; | |
c0532a76 MT |
1742 | |
1743 | /* Hope we are lucky for AO MCE */ | |
1744 | vaddr = addr; | |
1745 | if (qemu_ram_addr_from_host(vaddr, &ram_addr) || | |
1746 | !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) { | |
1747 | fprintf(stderr, "Hardware memory error for memory used by " | |
1748 | "QEMU itself instead of guest system!: %p\n", addr); | |
1749 | return 0; | |
1750 | } | |
1751 | status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
1752 | | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S | |
1753 | | 0xc0; | |
1754 | kvm_inject_x86_mce(first_cpu, 9, status, | |
1755 | MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr, | |
1756 | (MCM_ADDR_PHYS << 6) | 0xc, 1); | |
f71ac88f | 1757 | kvm_mce_broadcast_rest(first_cpu); |
c0532a76 MT |
1758 | } else |
1759 | #endif | |
1760 | { | |
1761 | if (code == BUS_MCEERR_AO) { | |
1762 | return 0; | |
1763 | } else if (code == BUS_MCEERR_AR) { | |
1764 | hardware_memory_error(); | |
1765 | } else { | |
1766 | return 1; | |
1767 | } | |
1768 | } | |
1769 | return 0; | |
1770 | } |