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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
18 | ||
19 | #include <linux/kvm.h> | |
20 | ||
21 | #include "qemu-common.h" | |
22 | #include "sysemu.h" | |
23 | #include "kvm.h" | |
24 | #include "cpu.h" | |
e22a25c9 | 25 | #include "gdbstub.h" |
0e607a80 | 26 | #include "host-utils.h" |
4c5b10b7 | 27 | #include "hw/pc.h" |
35bed8ee | 28 | #include "ioport.h" |
05330448 | 29 | |
bb0300dc GN |
30 | #ifdef CONFIG_KVM_PARA |
31 | #include <linux/kvm_para.h> | |
32 | #endif | |
33 | // | |
05330448 AL |
34 | //#define DEBUG_KVM |
35 | ||
36 | #ifdef DEBUG_KVM | |
8c0d577e | 37 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
38 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
39 | #else | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { } while (0) |
42 | #endif | |
43 | ||
1a03675d GC |
44 | #define MSR_KVM_WALL_CLOCK 0x11 |
45 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
46 | ||
b827df58 AK |
47 | #ifdef KVM_CAP_EXT_CPUID |
48 | ||
49 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) | |
50 | { | |
51 | struct kvm_cpuid2 *cpuid; | |
52 | int r, size; | |
53 | ||
54 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
55 | cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size); | |
56 | cpuid->nent = max; | |
57 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
58 | if (r == 0 && cpuid->nent >= max) { |
59 | r = -E2BIG; | |
60 | } | |
b827df58 AK |
61 | if (r < 0) { |
62 | if (r == -E2BIG) { | |
63 | qemu_free(cpuid); | |
64 | return NULL; | |
65 | } else { | |
66 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
67 | strerror(-r)); | |
68 | exit(1); | |
69 | } | |
70 | } | |
71 | return cpuid; | |
72 | } | |
73 | ||
c958a8bd SY |
74 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
75 | uint32_t index, int reg) | |
b827df58 AK |
76 | { |
77 | struct kvm_cpuid2 *cpuid; | |
78 | int i, max; | |
79 | uint32_t ret = 0; | |
80 | uint32_t cpuid_1_edx; | |
81 | ||
82 | if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) { | |
83 | return -1U; | |
84 | } | |
85 | ||
86 | max = 1; | |
87 | while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) { | |
88 | max *= 2; | |
89 | } | |
90 | ||
91 | for (i = 0; i < cpuid->nent; ++i) { | |
c958a8bd SY |
92 | if (cpuid->entries[i].function == function && |
93 | cpuid->entries[i].index == index) { | |
b827df58 AK |
94 | switch (reg) { |
95 | case R_EAX: | |
96 | ret = cpuid->entries[i].eax; | |
97 | break; | |
98 | case R_EBX: | |
99 | ret = cpuid->entries[i].ebx; | |
100 | break; | |
101 | case R_ECX: | |
102 | ret = cpuid->entries[i].ecx; | |
103 | break; | |
104 | case R_EDX: | |
105 | ret = cpuid->entries[i].edx; | |
19ccb8ea JK |
106 | switch (function) { |
107 | case 1: | |
108 | /* KVM before 2.6.30 misreports the following features */ | |
109 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
110 | break; | |
111 | case 0x80000001: | |
b827df58 AK |
112 | /* On Intel, kvm returns cpuid according to the Intel spec, |
113 | * so add missing bits according to the AMD spec: | |
114 | */ | |
c958a8bd | 115 | cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
c1667e40 | 116 | ret |= cpuid_1_edx & 0x183f7ff; |
19ccb8ea | 117 | break; |
b827df58 AK |
118 | } |
119 | break; | |
120 | } | |
121 | } | |
122 | } | |
123 | ||
124 | qemu_free(cpuid); | |
125 | ||
126 | return ret; | |
127 | } | |
128 | ||
129 | #else | |
130 | ||
c958a8bd SY |
131 | uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, |
132 | uint32_t index, int reg) | |
b827df58 AK |
133 | { |
134 | return -1U; | |
135 | } | |
136 | ||
137 | #endif | |
138 | ||
bb0300dc GN |
139 | #ifdef CONFIG_KVM_PARA |
140 | struct kvm_para_features { | |
141 | int cap; | |
142 | int feature; | |
143 | } para_features[] = { | |
144 | #ifdef KVM_CAP_CLOCKSOURCE | |
145 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
146 | #endif | |
147 | #ifdef KVM_CAP_NOP_IO_DELAY | |
148 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
149 | #endif | |
150 | #ifdef KVM_CAP_PV_MMU | |
151 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
bb0300dc GN |
152 | #endif |
153 | { -1, -1 } | |
154 | }; | |
155 | ||
156 | static int get_para_features(CPUState *env) | |
157 | { | |
158 | int i, features = 0; | |
159 | ||
160 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
161 | if (kvm_check_extension(env->kvm_state, para_features[i].cap)) | |
162 | features |= (1 << para_features[i].feature); | |
163 | } | |
164 | ||
165 | return features; | |
166 | } | |
167 | #endif | |
168 | ||
05330448 AL |
169 | int kvm_arch_init_vcpu(CPUState *env) |
170 | { | |
171 | struct { | |
486bd5a2 AL |
172 | struct kvm_cpuid2 cpuid; |
173 | struct kvm_cpuid_entry2 entries[100]; | |
05330448 | 174 | } __attribute__((packed)) cpuid_data; |
486bd5a2 | 175 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 176 | uint32_t unused; |
bb0300dc GN |
177 | struct kvm_cpuid_entry2 *c; |
178 | #ifdef KVM_CPUID_SIGNATURE | |
179 | uint32_t signature[3]; | |
180 | #endif | |
05330448 | 181 | |
f8d926e9 JK |
182 | env->mp_state = KVM_MP_STATE_RUNNABLE; |
183 | ||
c958a8bd | 184 | env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX); |
6c0d7ee8 AP |
185 | |
186 | i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; | |
c958a8bd | 187 | env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX); |
6c0d7ee8 AP |
188 | env->cpuid_ext_features |= i; |
189 | ||
457dfed6 | 190 | env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 191 | 0, R_EDX); |
457dfed6 | 192 | env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001, |
c958a8bd | 193 | 0, R_ECX); |
6c1f42fe | 194 | |
05330448 AL |
195 | cpuid_i = 0; |
196 | ||
bb0300dc GN |
197 | #ifdef CONFIG_KVM_PARA |
198 | /* Paravirtualization CPUIDs */ | |
199 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
200 | c = &cpuid_data.entries[cpuid_i++]; | |
201 | memset(c, 0, sizeof(*c)); | |
202 | c->function = KVM_CPUID_SIGNATURE; | |
203 | c->eax = 0; | |
204 | c->ebx = signature[0]; | |
205 | c->ecx = signature[1]; | |
206 | c->edx = signature[2]; | |
207 | ||
208 | c = &cpuid_data.entries[cpuid_i++]; | |
209 | memset(c, 0, sizeof(*c)); | |
210 | c->function = KVM_CPUID_FEATURES; | |
211 | c->eax = env->cpuid_kvm_features & get_para_features(env); | |
212 | #endif | |
213 | ||
a33609ca | 214 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
215 | |
216 | for (i = 0; i <= limit; i++) { | |
bb0300dc | 217 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
218 | |
219 | switch (i) { | |
a36b1029 AL |
220 | case 2: { |
221 | /* Keep reading function 2 till all the input is received */ | |
222 | int times; | |
223 | ||
a36b1029 | 224 | c->function = i; |
a33609ca AL |
225 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
226 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
227 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
228 | times = c->eax & 0xff; | |
a36b1029 AL |
229 | |
230 | for (j = 1; j < times; ++j) { | |
a33609ca | 231 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 232 | c->function = i; |
a33609ca AL |
233 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
234 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
235 | } |
236 | break; | |
237 | } | |
486bd5a2 AL |
238 | case 4: |
239 | case 0xb: | |
240 | case 0xd: | |
241 | for (j = 0; ; j++) { | |
486bd5a2 AL |
242 | c->function = i; |
243 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
244 | c->index = j; | |
a33609ca | 245 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 246 | |
a33609ca | 247 | if (i == 4 && c->eax == 0) |
486bd5a2 | 248 | break; |
a33609ca | 249 | if (i == 0xb && !(c->ecx & 0xff00)) |
486bd5a2 | 250 | break; |
a33609ca | 251 | if (i == 0xd && c->eax == 0) |
486bd5a2 | 252 | break; |
a33609ca AL |
253 | |
254 | c = &cpuid_data.entries[cpuid_i++]; | |
486bd5a2 AL |
255 | } |
256 | break; | |
257 | default: | |
486bd5a2 | 258 | c->function = i; |
a33609ca AL |
259 | c->flags = 0; |
260 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
261 | break; |
262 | } | |
05330448 | 263 | } |
a33609ca | 264 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
265 | |
266 | for (i = 0x80000000; i <= limit; i++) { | |
bb0300dc | 267 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 268 | |
05330448 | 269 | c->function = i; |
a33609ca AL |
270 | c->flags = 0; |
271 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
272 | } |
273 | ||
274 | cpuid_data.cpuid.nent = cpuid_i; | |
275 | ||
486bd5a2 | 276 | return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
05330448 AL |
277 | } |
278 | ||
caa5af0f JK |
279 | void kvm_arch_reset_vcpu(CPUState *env) |
280 | { | |
e73223a5 | 281 | env->exception_injected = -1; |
0e607a80 | 282 | env->interrupt_injected = -1; |
a0fb002c JK |
283 | env->nmi_injected = 0; |
284 | env->nmi_pending = 0; | |
caa5af0f JK |
285 | } |
286 | ||
05330448 AL |
287 | static int kvm_has_msr_star(CPUState *env) |
288 | { | |
289 | static int has_msr_star; | |
290 | int ret; | |
291 | ||
292 | /* first time */ | |
293 | if (has_msr_star == 0) { | |
294 | struct kvm_msr_list msr_list, *kvm_msr_list; | |
295 | ||
296 | has_msr_star = -1; | |
297 | ||
298 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
299 | * save/restore */ | |
4c9f7372 | 300 | msr_list.nmsrs = 0; |
05330448 | 301 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 302 | if (ret < 0 && ret != -E2BIG) { |
05330448 | 303 | return 0; |
6fb6d245 | 304 | } |
d9db889f JK |
305 | /* Old kernel modules had a bug and could write beyond the provided |
306 | memory. Allocate at least a safe amount of 1K. */ | |
307 | kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) + | |
308 | msr_list.nmsrs * | |
309 | sizeof(msr_list.indices[0]))); | |
05330448 | 310 | |
55308450 | 311 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
05330448 AL |
312 | ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
313 | if (ret >= 0) { | |
314 | int i; | |
315 | ||
316 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
317 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
318 | has_msr_star = 1; | |
319 | break; | |
320 | } | |
321 | } | |
322 | } | |
323 | ||
324 | free(kvm_msr_list); | |
325 | } | |
326 | ||
327 | if (has_msr_star == 1) | |
328 | return 1; | |
329 | return 0; | |
330 | } | |
331 | ||
20420430 SY |
332 | static int kvm_init_identity_map_page(KVMState *s) |
333 | { | |
334 | #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR | |
335 | int ret; | |
336 | uint64_t addr = 0xfffbc000; | |
337 | ||
338 | if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { | |
339 | return 0; | |
340 | } | |
341 | ||
342 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr); | |
343 | if (ret < 0) { | |
344 | fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret)); | |
345 | return ret; | |
346 | } | |
347 | #endif | |
348 | return 0; | |
349 | } | |
350 | ||
05330448 AL |
351 | int kvm_arch_init(KVMState *s, int smp_cpus) |
352 | { | |
353 | int ret; | |
354 | ||
355 | /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code | |
356 | * directly. In order to use vm86 mode, a TSS is needed. Since this | |
357 | * must be part of guest physical memory, we need to allocate it. Older | |
358 | * versions of KVM just assumed that it would be at the end of physical | |
359 | * memory but that doesn't work with more than 4GB of memory. We simply | |
360 | * refuse to work with those older versions of KVM. */ | |
984b5181 | 361 | ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR); |
05330448 AL |
362 | if (ret <= 0) { |
363 | fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n"); | |
364 | return ret; | |
365 | } | |
366 | ||
367 | /* this address is 3 pages before the bios, and the bios should present | |
368 | * as unavaible memory. FIXME, need to ensure the e820 map deals with | |
369 | * this? | |
370 | */ | |
4c5b10b7 JS |
371 | /* |
372 | * Tell fw_cfg to notify the BIOS to reserve the range. | |
373 | */ | |
374 | if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) { | |
375 | perror("e820_add_entry() table is full"); | |
376 | exit(1); | |
377 | } | |
20420430 SY |
378 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000); |
379 | if (ret < 0) { | |
380 | return ret; | |
381 | } | |
382 | ||
383 | return kvm_init_identity_map_page(s); | |
05330448 AL |
384 | } |
385 | ||
386 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
387 | { | |
388 | lhs->selector = rhs->selector; | |
389 | lhs->base = rhs->base; | |
390 | lhs->limit = rhs->limit; | |
391 | lhs->type = 3; | |
392 | lhs->present = 1; | |
393 | lhs->dpl = 3; | |
394 | lhs->db = 0; | |
395 | lhs->s = 1; | |
396 | lhs->l = 0; | |
397 | lhs->g = 0; | |
398 | lhs->avl = 0; | |
399 | lhs->unusable = 0; | |
400 | } | |
401 | ||
402 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
403 | { | |
404 | unsigned flags = rhs->flags; | |
405 | lhs->selector = rhs->selector; | |
406 | lhs->base = rhs->base; | |
407 | lhs->limit = rhs->limit; | |
408 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
409 | lhs->present = (flags & DESC_P_MASK) != 0; | |
410 | lhs->dpl = rhs->selector & 3; | |
411 | lhs->db = (flags >> DESC_B_SHIFT) & 1; | |
412 | lhs->s = (flags & DESC_S_MASK) != 0; | |
413 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
414 | lhs->g = (flags & DESC_G_MASK) != 0; | |
415 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
416 | lhs->unusable = 0; | |
417 | } | |
418 | ||
419 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
420 | { | |
421 | lhs->selector = rhs->selector; | |
422 | lhs->base = rhs->base; | |
423 | lhs->limit = rhs->limit; | |
424 | lhs->flags = | |
425 | (rhs->type << DESC_TYPE_SHIFT) | |
426 | | (rhs->present * DESC_P_MASK) | |
427 | | (rhs->dpl << DESC_DPL_SHIFT) | |
428 | | (rhs->db << DESC_B_SHIFT) | |
429 | | (rhs->s * DESC_S_MASK) | |
430 | | (rhs->l << DESC_L_SHIFT) | |
431 | | (rhs->g * DESC_G_MASK) | |
432 | | (rhs->avl * DESC_AVL_MASK); | |
433 | } | |
434 | ||
435 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
436 | { | |
437 | if (set) | |
438 | *kvm_reg = *qemu_reg; | |
439 | else | |
440 | *qemu_reg = *kvm_reg; | |
441 | } | |
442 | ||
443 | static int kvm_getput_regs(CPUState *env, int set) | |
444 | { | |
445 | struct kvm_regs regs; | |
446 | int ret = 0; | |
447 | ||
448 | if (!set) { | |
449 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
450 | if (ret < 0) | |
451 | return ret; | |
452 | } | |
453 | ||
454 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
455 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
456 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
457 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
458 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
459 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
460 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
461 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
462 | #ifdef TARGET_X86_64 | |
463 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
464 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
465 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
466 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
467 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
468 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
469 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
470 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
471 | #endif | |
472 | ||
473 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
474 | kvm_getput_reg(®s.rip, &env->eip, set); | |
475 | ||
476 | if (set) | |
477 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
478 | ||
479 | return ret; | |
480 | } | |
481 | ||
482 | static int kvm_put_fpu(CPUState *env) | |
483 | { | |
484 | struct kvm_fpu fpu; | |
485 | int i; | |
486 | ||
487 | memset(&fpu, 0, sizeof fpu); | |
488 | fpu.fsw = env->fpus & ~(7 << 11); | |
489 | fpu.fsw |= (env->fpstt & 7) << 11; | |
490 | fpu.fcw = env->fpuc; | |
491 | for (i = 0; i < 8; ++i) | |
492 | fpu.ftwx |= (!env->fptags[i]) << i; | |
493 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); | |
494 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
495 | fpu.mxcsr = env->mxcsr; | |
496 | ||
497 | return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu); | |
498 | } | |
499 | ||
f1665b21 SY |
500 | #ifdef KVM_CAP_XSAVE |
501 | #define XSAVE_CWD_RIP 2 | |
502 | #define XSAVE_CWD_RDP 4 | |
503 | #define XSAVE_MXCSR 6 | |
504 | #define XSAVE_ST_SPACE 8 | |
505 | #define XSAVE_XMM_SPACE 40 | |
506 | #define XSAVE_XSTATE_BV 128 | |
507 | #define XSAVE_YMMH_SPACE 144 | |
508 | #endif | |
509 | ||
510 | static int kvm_put_xsave(CPUState *env) | |
511 | { | |
512 | #ifdef KVM_CAP_XSAVE | |
513 | int i; | |
514 | struct kvm_xsave* xsave; | |
515 | uint16_t cwd, swd, twd, fop; | |
516 | ||
517 | if (!kvm_has_xsave()) | |
518 | return kvm_put_fpu(env); | |
519 | ||
520 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
521 | memset(xsave, 0, sizeof(struct kvm_xsave)); | |
522 | cwd = swd = twd = fop = 0; | |
523 | swd = env->fpus & ~(7 << 11); | |
524 | swd |= (env->fpstt & 7) << 11; | |
525 | cwd = env->fpuc; | |
526 | for (i = 0; i < 8; ++i) | |
527 | twd |= (!env->fptags[i]) << i; | |
528 | xsave->region[0] = (uint32_t)(swd << 16) + cwd; | |
529 | xsave->region[1] = (uint32_t)(fop << 16) + twd; | |
530 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, | |
531 | sizeof env->fpregs); | |
532 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
533 | sizeof env->xmm_regs); | |
534 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
535 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
536 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
537 | sizeof env->ymmh_regs); | |
538 | return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); | |
539 | #else | |
540 | return kvm_put_fpu(env); | |
541 | #endif | |
542 | } | |
543 | ||
544 | static int kvm_put_xcrs(CPUState *env) | |
545 | { | |
546 | #ifdef KVM_CAP_XCRS | |
547 | struct kvm_xcrs xcrs; | |
548 | ||
549 | if (!kvm_has_xcrs()) | |
550 | return 0; | |
551 | ||
552 | xcrs.nr_xcrs = 1; | |
553 | xcrs.flags = 0; | |
554 | xcrs.xcrs[0].xcr = 0; | |
555 | xcrs.xcrs[0].value = env->xcr0; | |
556 | return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs); | |
557 | #else | |
558 | return 0; | |
559 | #endif | |
560 | } | |
561 | ||
05330448 AL |
562 | static int kvm_put_sregs(CPUState *env) |
563 | { | |
564 | struct kvm_sregs sregs; | |
565 | ||
0e607a80 JK |
566 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
567 | if (env->interrupt_injected >= 0) { | |
568 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
569 | (uint64_t)1 << (env->interrupt_injected % 64); | |
570 | } | |
05330448 AL |
571 | |
572 | if ((env->eflags & VM_MASK)) { | |
573 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); | |
574 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
575 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
576 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
577 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
578 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
579 | } else { | |
580 | set_seg(&sregs.cs, &env->segs[R_CS]); | |
581 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
582 | set_seg(&sregs.es, &env->segs[R_ES]); | |
583 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
584 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
585 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
586 | ||
587 | if (env->cr[0] & CR0_PE_MASK) { | |
588 | /* force ss cpl to cs cpl */ | |
589 | sregs.ss.selector = (sregs.ss.selector & ~3) | | |
590 | (sregs.cs.selector & 3); | |
591 | sregs.ss.dpl = sregs.ss.selector & 3; | |
592 | } | |
593 | } | |
594 | ||
595 | set_seg(&sregs.tr, &env->tr); | |
596 | set_seg(&sregs.ldt, &env->ldt); | |
597 | ||
598 | sregs.idt.limit = env->idt.limit; | |
599 | sregs.idt.base = env->idt.base; | |
600 | sregs.gdt.limit = env->gdt.limit; | |
601 | sregs.gdt.base = env->gdt.base; | |
602 | ||
603 | sregs.cr0 = env->cr[0]; | |
604 | sregs.cr2 = env->cr[2]; | |
605 | sregs.cr3 = env->cr[3]; | |
606 | sregs.cr4 = env->cr[4]; | |
607 | ||
4a942cea BS |
608 | sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
609 | sregs.apic_base = cpu_get_apic_base(env->apic_state); | |
05330448 AL |
610 | |
611 | sregs.efer = env->efer; | |
612 | ||
613 | return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
614 | } | |
615 | ||
616 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
617 | uint32_t index, uint64_t value) | |
618 | { | |
619 | entry->index = index; | |
620 | entry->data = value; | |
621 | } | |
622 | ||
ea643051 | 623 | static int kvm_put_msrs(CPUState *env, int level) |
05330448 AL |
624 | { |
625 | struct { | |
626 | struct kvm_msrs info; | |
627 | struct kvm_msr_entry entries[100]; | |
628 | } msr_data; | |
629 | struct kvm_msr_entry *msrs = msr_data.entries; | |
630 | int n = 0; | |
631 | ||
632 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
633 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
634 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
635 | if (kvm_has_msr_star(env)) | |
636 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); | |
05330448 AL |
637 | #ifdef TARGET_X86_64 |
638 | /* FIXME if lm capable */ | |
639 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
640 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
641 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
642 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
643 | #endif | |
ea643051 JK |
644 | if (level == KVM_PUT_FULL_STATE) { |
645 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); | |
646 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, | |
647 | env->system_time_msr); | |
648 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
649 | } | |
1a03675d | 650 | |
05330448 AL |
651 | msr_data.info.nmsrs = n; |
652 | ||
653 | return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data); | |
654 | ||
655 | } | |
656 | ||
657 | ||
658 | static int kvm_get_fpu(CPUState *env) | |
659 | { | |
660 | struct kvm_fpu fpu; | |
661 | int i, ret; | |
662 | ||
663 | ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); | |
664 | if (ret < 0) | |
665 | return ret; | |
666 | ||
667 | env->fpstt = (fpu.fsw >> 11) & 7; | |
668 | env->fpus = fpu.fsw; | |
669 | env->fpuc = fpu.fcw; | |
670 | for (i = 0; i < 8; ++i) | |
671 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
672 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); | |
673 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
674 | env->mxcsr = fpu.mxcsr; | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
f1665b21 SY |
679 | static int kvm_get_xsave(CPUState *env) |
680 | { | |
681 | #ifdef KVM_CAP_XSAVE | |
682 | struct kvm_xsave* xsave; | |
683 | int ret, i; | |
684 | uint16_t cwd, swd, twd, fop; | |
685 | ||
686 | if (!kvm_has_xsave()) | |
687 | return kvm_get_fpu(env); | |
688 | ||
689 | xsave = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
690 | ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); | |
691 | if (ret < 0) | |
692 | return ret; | |
693 | ||
694 | cwd = (uint16_t)xsave->region[0]; | |
695 | swd = (uint16_t)(xsave->region[0] >> 16); | |
696 | twd = (uint16_t)xsave->region[1]; | |
697 | fop = (uint16_t)(xsave->region[1] >> 16); | |
698 | env->fpstt = (swd >> 11) & 7; | |
699 | env->fpus = swd; | |
700 | env->fpuc = cwd; | |
701 | for (i = 0; i < 8; ++i) | |
702 | env->fptags[i] = !((twd >> i) & 1); | |
703 | env->mxcsr = xsave->region[XSAVE_MXCSR]; | |
704 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
705 | sizeof env->fpregs); | |
706 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
707 | sizeof env->xmm_regs); | |
708 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
709 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
710 | sizeof env->ymmh_regs); | |
711 | return 0; | |
712 | #else | |
713 | return kvm_get_fpu(env); | |
714 | #endif | |
715 | } | |
716 | ||
717 | static int kvm_get_xcrs(CPUState *env) | |
718 | { | |
719 | #ifdef KVM_CAP_XCRS | |
720 | int i, ret; | |
721 | struct kvm_xcrs xcrs; | |
722 | ||
723 | if (!kvm_has_xcrs()) | |
724 | return 0; | |
725 | ||
726 | ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); | |
727 | if (ret < 0) | |
728 | return ret; | |
729 | ||
730 | for (i = 0; i < xcrs.nr_xcrs; i++) | |
731 | /* Only support xcr0 now */ | |
732 | if (xcrs.xcrs[0].xcr == 0) { | |
733 | env->xcr0 = xcrs.xcrs[0].value; | |
734 | break; | |
735 | } | |
736 | return 0; | |
737 | #else | |
738 | return 0; | |
739 | #endif | |
740 | } | |
741 | ||
05330448 AL |
742 | static int kvm_get_sregs(CPUState *env) |
743 | { | |
744 | struct kvm_sregs sregs; | |
745 | uint32_t hflags; | |
0e607a80 | 746 | int bit, i, ret; |
05330448 AL |
747 | |
748 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
749 | if (ret < 0) | |
750 | return ret; | |
751 | ||
0e607a80 JK |
752 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
753 | to find it and save its number instead (-1 for none). */ | |
754 | env->interrupt_injected = -1; | |
755 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
756 | if (sregs.interrupt_bitmap[i]) { | |
757 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
758 | env->interrupt_injected = i * 64 + bit; | |
759 | break; | |
760 | } | |
761 | } | |
05330448 AL |
762 | |
763 | get_seg(&env->segs[R_CS], &sregs.cs); | |
764 | get_seg(&env->segs[R_DS], &sregs.ds); | |
765 | get_seg(&env->segs[R_ES], &sregs.es); | |
766 | get_seg(&env->segs[R_FS], &sregs.fs); | |
767 | get_seg(&env->segs[R_GS], &sregs.gs); | |
768 | get_seg(&env->segs[R_SS], &sregs.ss); | |
769 | ||
770 | get_seg(&env->tr, &sregs.tr); | |
771 | get_seg(&env->ldt, &sregs.ldt); | |
772 | ||
773 | env->idt.limit = sregs.idt.limit; | |
774 | env->idt.base = sregs.idt.base; | |
775 | env->gdt.limit = sregs.gdt.limit; | |
776 | env->gdt.base = sregs.gdt.base; | |
777 | ||
778 | env->cr[0] = sregs.cr0; | |
779 | env->cr[2] = sregs.cr2; | |
780 | env->cr[3] = sregs.cr3; | |
781 | env->cr[4] = sregs.cr4; | |
782 | ||
4a942cea | 783 | cpu_set_apic_base(env->apic_state, sregs.apic_base); |
05330448 AL |
784 | |
785 | env->efer = sregs.efer; | |
4a942cea | 786 | //cpu_set_apic_tpr(env->apic_state, sregs.cr8); |
05330448 AL |
787 | |
788 | #define HFLAG_COPY_MASK ~( \ | |
789 | HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
790 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
791 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
792 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
793 | ||
794 | ||
795 | ||
796 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
797 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
798 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
799 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); | |
800 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); | |
801 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
802 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); | |
803 | ||
804 | if (env->efer & MSR_EFER_LMA) { | |
805 | hflags |= HF_LMA_MASK; | |
806 | } | |
807 | ||
808 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
809 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
810 | } else { | |
811 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
812 | (DESC_B_SHIFT - HF_CS32_SHIFT); | |
813 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> | |
814 | (DESC_B_SHIFT - HF_SS32_SHIFT); | |
815 | if (!(env->cr[0] & CR0_PE_MASK) || | |
816 | (env->eflags & VM_MASK) || | |
817 | !(hflags & HF_CS32_MASK)) { | |
818 | hflags |= HF_ADDSEG_MASK; | |
819 | } else { | |
820 | hflags |= ((env->segs[R_DS].base | | |
821 | env->segs[R_ES].base | | |
822 | env->segs[R_SS].base) != 0) << | |
823 | HF_ADDSEG_SHIFT; | |
824 | } | |
825 | } | |
826 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
827 | |
828 | return 0; | |
829 | } | |
830 | ||
831 | static int kvm_get_msrs(CPUState *env) | |
832 | { | |
833 | struct { | |
834 | struct kvm_msrs info; | |
835 | struct kvm_msr_entry entries[100]; | |
836 | } msr_data; | |
837 | struct kvm_msr_entry *msrs = msr_data.entries; | |
838 | int ret, i, n; | |
839 | ||
840 | n = 0; | |
841 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
842 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
843 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
844 | if (kvm_has_msr_star(env)) | |
845 | msrs[n++].index = MSR_STAR; | |
846 | msrs[n++].index = MSR_IA32_TSC; | |
847 | #ifdef TARGET_X86_64 | |
848 | /* FIXME lm_capable_kernel */ | |
849 | msrs[n++].index = MSR_CSTAR; | |
850 | msrs[n++].index = MSR_KERNELGSBASE; | |
851 | msrs[n++].index = MSR_FMASK; | |
852 | msrs[n++].index = MSR_LSTAR; | |
853 | #endif | |
1a03675d GC |
854 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
855 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
856 | ||
05330448 AL |
857 | msr_data.info.nmsrs = n; |
858 | ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); | |
859 | if (ret < 0) | |
860 | return ret; | |
861 | ||
862 | for (i = 0; i < ret; i++) { | |
863 | switch (msrs[i].index) { | |
864 | case MSR_IA32_SYSENTER_CS: | |
865 | env->sysenter_cs = msrs[i].data; | |
866 | break; | |
867 | case MSR_IA32_SYSENTER_ESP: | |
868 | env->sysenter_esp = msrs[i].data; | |
869 | break; | |
870 | case MSR_IA32_SYSENTER_EIP: | |
871 | env->sysenter_eip = msrs[i].data; | |
872 | break; | |
873 | case MSR_STAR: | |
874 | env->star = msrs[i].data; | |
875 | break; | |
876 | #ifdef TARGET_X86_64 | |
877 | case MSR_CSTAR: | |
878 | env->cstar = msrs[i].data; | |
879 | break; | |
880 | case MSR_KERNELGSBASE: | |
881 | env->kernelgsbase = msrs[i].data; | |
882 | break; | |
883 | case MSR_FMASK: | |
884 | env->fmask = msrs[i].data; | |
885 | break; | |
886 | case MSR_LSTAR: | |
887 | env->lstar = msrs[i].data; | |
888 | break; | |
889 | #endif | |
890 | case MSR_IA32_TSC: | |
891 | env->tsc = msrs[i].data; | |
892 | break; | |
1a03675d GC |
893 | case MSR_KVM_SYSTEM_TIME: |
894 | env->system_time_msr = msrs[i].data; | |
895 | break; | |
896 | case MSR_KVM_WALL_CLOCK: | |
897 | env->wall_clock_msr = msrs[i].data; | |
898 | break; | |
05330448 AL |
899 | } |
900 | } | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
9bdbe550 HB |
905 | static int kvm_put_mp_state(CPUState *env) |
906 | { | |
907 | struct kvm_mp_state mp_state = { .mp_state = env->mp_state }; | |
908 | ||
909 | return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); | |
910 | } | |
911 | ||
912 | static int kvm_get_mp_state(CPUState *env) | |
913 | { | |
914 | struct kvm_mp_state mp_state; | |
915 | int ret; | |
916 | ||
917 | ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); | |
918 | if (ret < 0) { | |
919 | return ret; | |
920 | } | |
921 | env->mp_state = mp_state.mp_state; | |
922 | return 0; | |
923 | } | |
924 | ||
ea643051 | 925 | static int kvm_put_vcpu_events(CPUState *env, int level) |
a0fb002c JK |
926 | { |
927 | #ifdef KVM_CAP_VCPU_EVENTS | |
928 | struct kvm_vcpu_events events; | |
929 | ||
930 | if (!kvm_has_vcpu_events()) { | |
931 | return 0; | |
932 | } | |
933 | ||
31827373 JK |
934 | events.exception.injected = (env->exception_injected >= 0); |
935 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
936 | events.exception.has_error_code = env->has_error_code; |
937 | events.exception.error_code = env->error_code; | |
938 | ||
939 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
940 | events.interrupt.nr = env->interrupt_injected; | |
941 | events.interrupt.soft = env->soft_interrupt; | |
942 | ||
943 | events.nmi.injected = env->nmi_injected; | |
944 | events.nmi.pending = env->nmi_pending; | |
945 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
946 | ||
947 | events.sipi_vector = env->sipi_vector; | |
948 | ||
ea643051 JK |
949 | events.flags = 0; |
950 | if (level >= KVM_PUT_RESET_STATE) { | |
951 | events.flags |= | |
952 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
953 | } | |
aee028b9 | 954 | |
a0fb002c JK |
955 | return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events); |
956 | #else | |
957 | return 0; | |
958 | #endif | |
959 | } | |
960 | ||
961 | static int kvm_get_vcpu_events(CPUState *env) | |
962 | { | |
963 | #ifdef KVM_CAP_VCPU_EVENTS | |
964 | struct kvm_vcpu_events events; | |
965 | int ret; | |
966 | ||
967 | if (!kvm_has_vcpu_events()) { | |
968 | return 0; | |
969 | } | |
970 | ||
971 | ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); | |
972 | if (ret < 0) { | |
973 | return ret; | |
974 | } | |
31827373 | 975 | env->exception_injected = |
a0fb002c JK |
976 | events.exception.injected ? events.exception.nr : -1; |
977 | env->has_error_code = events.exception.has_error_code; | |
978 | env->error_code = events.exception.error_code; | |
979 | ||
980 | env->interrupt_injected = | |
981 | events.interrupt.injected ? events.interrupt.nr : -1; | |
982 | env->soft_interrupt = events.interrupt.soft; | |
983 | ||
984 | env->nmi_injected = events.nmi.injected; | |
985 | env->nmi_pending = events.nmi.pending; | |
986 | if (events.nmi.masked) { | |
987 | env->hflags2 |= HF2_NMI_MASK; | |
988 | } else { | |
989 | env->hflags2 &= ~HF2_NMI_MASK; | |
990 | } | |
991 | ||
992 | env->sipi_vector = events.sipi_vector; | |
993 | #endif | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
b0b1d690 JK |
998 | static int kvm_guest_debug_workarounds(CPUState *env) |
999 | { | |
1000 | int ret = 0; | |
1001 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
1002 | unsigned long reinject_trap = 0; | |
1003 | ||
1004 | if (!kvm_has_vcpu_events()) { | |
1005 | if (env->exception_injected == 1) { | |
1006 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1007 | } else if (env->exception_injected == 3) { | |
1008 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1009 | } | |
1010 | env->exception_injected = -1; | |
1011 | } | |
1012 | ||
1013 | /* | |
1014 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1015 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1016 | * by updating the debug state once again if single-stepping is on. | |
1017 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1018 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1019 | * reinject them via SET_GUEST_DEBUG. | |
1020 | */ | |
1021 | if (reinject_trap || | |
1022 | (!kvm_has_robust_singlestep() && env->singlestep_enabled)) { | |
1023 | ret = kvm_update_guest_debug(env, reinject_trap); | |
1024 | } | |
1025 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
1026 | return ret; | |
1027 | } | |
1028 | ||
ff44f1a3 JK |
1029 | static int kvm_put_debugregs(CPUState *env) |
1030 | { | |
1031 | #ifdef KVM_CAP_DEBUGREGS | |
1032 | struct kvm_debugregs dbgregs; | |
1033 | int i; | |
1034 | ||
1035 | if (!kvm_has_debugregs()) { | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | for (i = 0; i < 4; i++) { | |
1040 | dbgregs.db[i] = env->dr[i]; | |
1041 | } | |
1042 | dbgregs.dr6 = env->dr[6]; | |
1043 | dbgregs.dr7 = env->dr[7]; | |
1044 | dbgregs.flags = 0; | |
1045 | ||
1046 | return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs); | |
1047 | #else | |
1048 | return 0; | |
1049 | #endif | |
1050 | } | |
1051 | ||
1052 | static int kvm_get_debugregs(CPUState *env) | |
1053 | { | |
1054 | #ifdef KVM_CAP_DEBUGREGS | |
1055 | struct kvm_debugregs dbgregs; | |
1056 | int i, ret; | |
1057 | ||
1058 | if (!kvm_has_debugregs()) { | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); | |
1063 | if (ret < 0) { | |
1064 | return ret; | |
1065 | } | |
1066 | for (i = 0; i < 4; i++) { | |
1067 | env->dr[i] = dbgregs.db[i]; | |
1068 | } | |
1069 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1070 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
1071 | #endif | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
ea375f9a | 1076 | int kvm_arch_put_registers(CPUState *env, int level) |
05330448 AL |
1077 | { |
1078 | int ret; | |
1079 | ||
dbaa07c4 JK |
1080 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1081 | ||
05330448 AL |
1082 | ret = kvm_getput_regs(env, 1); |
1083 | if (ret < 0) | |
1084 | return ret; | |
1085 | ||
f1665b21 SY |
1086 | ret = kvm_put_xsave(env); |
1087 | if (ret < 0) | |
1088 | return ret; | |
1089 | ||
1090 | ret = kvm_put_xcrs(env); | |
05330448 AL |
1091 | if (ret < 0) |
1092 | return ret; | |
1093 | ||
1094 | ret = kvm_put_sregs(env); | |
1095 | if (ret < 0) | |
1096 | return ret; | |
1097 | ||
ea643051 | 1098 | ret = kvm_put_msrs(env, level); |
05330448 AL |
1099 | if (ret < 0) |
1100 | return ret; | |
1101 | ||
ea643051 JK |
1102 | if (level >= KVM_PUT_RESET_STATE) { |
1103 | ret = kvm_put_mp_state(env); | |
1104 | if (ret < 0) | |
1105 | return ret; | |
1106 | } | |
f8d926e9 | 1107 | |
ea643051 | 1108 | ret = kvm_put_vcpu_events(env, level); |
a0fb002c JK |
1109 | if (ret < 0) |
1110 | return ret; | |
1111 | ||
b0b1d690 JK |
1112 | /* must be last */ |
1113 | ret = kvm_guest_debug_workarounds(env); | |
1114 | if (ret < 0) | |
1115 | return ret; | |
1116 | ||
ff44f1a3 JK |
1117 | ret = kvm_put_debugregs(env); |
1118 | if (ret < 0) | |
1119 | return ret; | |
1120 | ||
05330448 AL |
1121 | return 0; |
1122 | } | |
1123 | ||
1124 | int kvm_arch_get_registers(CPUState *env) | |
1125 | { | |
1126 | int ret; | |
1127 | ||
dbaa07c4 JK |
1128 | assert(cpu_is_stopped(env) || qemu_cpu_self(env)); |
1129 | ||
05330448 AL |
1130 | ret = kvm_getput_regs(env, 0); |
1131 | if (ret < 0) | |
1132 | return ret; | |
1133 | ||
f1665b21 SY |
1134 | ret = kvm_get_xsave(env); |
1135 | if (ret < 0) | |
1136 | return ret; | |
1137 | ||
1138 | ret = kvm_get_xcrs(env); | |
05330448 AL |
1139 | if (ret < 0) |
1140 | return ret; | |
1141 | ||
1142 | ret = kvm_get_sregs(env); | |
1143 | if (ret < 0) | |
1144 | return ret; | |
1145 | ||
1146 | ret = kvm_get_msrs(env); | |
1147 | if (ret < 0) | |
1148 | return ret; | |
1149 | ||
5a2e3c2e JK |
1150 | ret = kvm_get_mp_state(env); |
1151 | if (ret < 0) | |
1152 | return ret; | |
1153 | ||
a0fb002c JK |
1154 | ret = kvm_get_vcpu_events(env); |
1155 | if (ret < 0) | |
1156 | return ret; | |
1157 | ||
ff44f1a3 JK |
1158 | ret = kvm_get_debugregs(env); |
1159 | if (ret < 0) | |
1160 | return ret; | |
1161 | ||
05330448 AL |
1162 | return 0; |
1163 | } | |
1164 | ||
1165 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) | |
1166 | { | |
1167 | /* Try to inject an interrupt if the guest can accept it */ | |
1168 | if (run->ready_for_interrupt_injection && | |
1169 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1170 | (env->eflags & IF_MASK)) { | |
1171 | int irq; | |
1172 | ||
1173 | env->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1174 | irq = cpu_get_pic_interrupt(env); | |
1175 | if (irq >= 0) { | |
1176 | struct kvm_interrupt intr; | |
1177 | intr.irq = irq; | |
1178 | /* FIXME: errors */ | |
8c0d577e | 1179 | DPRINTF("injected interrupt %d\n", irq); |
05330448 AL |
1180 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1181 | } | |
1182 | } | |
1183 | ||
1184 | /* If we have an interrupt but the guest is not ready to receive an | |
1185 | * interrupt, request an interrupt window exit. This will | |
1186 | * cause a return to userspace as soon as the guest is ready to | |
1187 | * receive interrupts. */ | |
1188 | if ((env->interrupt_request & CPU_INTERRUPT_HARD)) | |
1189 | run->request_interrupt_window = 1; | |
1190 | else | |
1191 | run->request_interrupt_window = 0; | |
1192 | ||
8c0d577e | 1193 | DPRINTF("setting tpr\n"); |
4a942cea | 1194 | run->cr8 = cpu_get_apic_tpr(env->apic_state); |
05330448 AL |
1195 | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
1200 | { | |
1201 | if (run->if_flag) | |
1202 | env->eflags |= IF_MASK; | |
1203 | else | |
1204 | env->eflags &= ~IF_MASK; | |
1205 | ||
4a942cea BS |
1206 | cpu_set_apic_tpr(env->apic_state, run->cr8); |
1207 | cpu_set_apic_base(env->apic_state, run->apic_base); | |
05330448 AL |
1208 | |
1209 | return 0; | |
1210 | } | |
1211 | ||
0af691d7 MT |
1212 | int kvm_arch_process_irqchip_events(CPUState *env) |
1213 | { | |
1214 | if (env->interrupt_request & CPU_INTERRUPT_INIT) { | |
1215 | kvm_cpu_synchronize_state(env); | |
1216 | do_cpu_init(env); | |
1217 | env->exception_index = EXCP_HALTED; | |
1218 | } | |
1219 | ||
1220 | if (env->interrupt_request & CPU_INTERRUPT_SIPI) { | |
1221 | kvm_cpu_synchronize_state(env); | |
1222 | do_cpu_sipi(env); | |
1223 | } | |
1224 | ||
1225 | return env->halted; | |
1226 | } | |
1227 | ||
05330448 AL |
1228 | static int kvm_handle_halt(CPUState *env) |
1229 | { | |
1230 | if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && | |
1231 | (env->eflags & IF_MASK)) && | |
1232 | !(env->interrupt_request & CPU_INTERRUPT_NMI)) { | |
1233 | env->halted = 1; | |
1234 | env->exception_index = EXCP_HLT; | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | return 1; | |
1239 | } | |
1240 | ||
1241 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
1242 | { | |
1243 | int ret = 0; | |
1244 | ||
1245 | switch (run->exit_reason) { | |
1246 | case KVM_EXIT_HLT: | |
8c0d577e | 1247 | DPRINTF("handle_hlt\n"); |
05330448 AL |
1248 | ret = kvm_handle_halt(env); |
1249 | break; | |
1250 | } | |
1251 | ||
1252 | return ret; | |
1253 | } | |
e22a25c9 AL |
1254 | |
1255 | #ifdef KVM_CAP_SET_GUEST_DEBUG | |
e22a25c9 AL |
1256 | int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1257 | { | |
38972938 | 1258 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 1259 | |
e22a25c9 | 1260 | if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
64bf3f4e | 1261 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) |
e22a25c9 AL |
1262 | return -EINVAL; |
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) | |
1267 | { | |
1268 | uint8_t int3; | |
1269 | ||
1270 | if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || | |
64bf3f4e | 1271 | cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) |
e22a25c9 AL |
1272 | return -EINVAL; |
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static struct { | |
1277 | target_ulong addr; | |
1278 | int len; | |
1279 | int type; | |
1280 | } hw_breakpoint[4]; | |
1281 | ||
1282 | static int nb_hw_breakpoint; | |
1283 | ||
1284 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
1285 | { | |
1286 | int n; | |
1287 | ||
1288 | for (n = 0; n < nb_hw_breakpoint; n++) | |
1289 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && | |
1290 | (hw_breakpoint[n].len == len || len == -1)) | |
1291 | return n; | |
1292 | return -1; | |
1293 | } | |
1294 | ||
1295 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1296 | target_ulong len, int type) | |
1297 | { | |
1298 | switch (type) { | |
1299 | case GDB_BREAKPOINT_HW: | |
1300 | len = 1; | |
1301 | break; | |
1302 | case GDB_WATCHPOINT_WRITE: | |
1303 | case GDB_WATCHPOINT_ACCESS: | |
1304 | switch (len) { | |
1305 | case 1: | |
1306 | break; | |
1307 | case 2: | |
1308 | case 4: | |
1309 | case 8: | |
1310 | if (addr & (len - 1)) | |
1311 | return -EINVAL; | |
1312 | break; | |
1313 | default: | |
1314 | return -EINVAL; | |
1315 | } | |
1316 | break; | |
1317 | default: | |
1318 | return -ENOSYS; | |
1319 | } | |
1320 | ||
1321 | if (nb_hw_breakpoint == 4) | |
1322 | return -ENOBUFS; | |
1323 | ||
1324 | if (find_hw_breakpoint(addr, len, type) >= 0) | |
1325 | return -EEXIST; | |
1326 | ||
1327 | hw_breakpoint[nb_hw_breakpoint].addr = addr; | |
1328 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
1329 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
1330 | nb_hw_breakpoint++; | |
1331 | ||
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1336 | target_ulong len, int type) | |
1337 | { | |
1338 | int n; | |
1339 | ||
1340 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
1341 | if (n < 0) | |
1342 | return -ENOENT; | |
1343 | ||
1344 | nb_hw_breakpoint--; | |
1345 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1351 | { | |
1352 | nb_hw_breakpoint = 0; | |
1353 | } | |
1354 | ||
1355 | static CPUWatchpoint hw_watchpoint; | |
1356 | ||
1357 | int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) | |
1358 | { | |
1359 | int handle = 0; | |
1360 | int n; | |
1361 | ||
1362 | if (arch_info->exception == 1) { | |
1363 | if (arch_info->dr6 & (1 << 14)) { | |
1364 | if (cpu_single_env->singlestep_enabled) | |
1365 | handle = 1; | |
1366 | } else { | |
1367 | for (n = 0; n < 4; n++) | |
1368 | if (arch_info->dr6 & (1 << n)) | |
1369 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { | |
1370 | case 0x0: | |
1371 | handle = 1; | |
1372 | break; | |
1373 | case 0x1: | |
1374 | handle = 1; | |
1375 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1376 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1377 | hw_watchpoint.flags = BP_MEM_WRITE; | |
1378 | break; | |
1379 | case 0x3: | |
1380 | handle = 1; | |
1381 | cpu_single_env->watchpoint_hit = &hw_watchpoint; | |
1382 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; | |
1383 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
1384 | break; | |
1385 | } | |
1386 | } | |
1387 | } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) | |
1388 | handle = 1; | |
1389 | ||
b0b1d690 JK |
1390 | if (!handle) { |
1391 | cpu_synchronize_state(cpu_single_env); | |
1392 | assert(cpu_single_env->exception_injected == -1); | |
1393 | ||
1394 | cpu_single_env->exception_injected = arch_info->exception; | |
1395 | cpu_single_env->has_error_code = 0; | |
1396 | } | |
e22a25c9 AL |
1397 | |
1398 | return handle; | |
1399 | } | |
1400 | ||
1401 | void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) | |
1402 | { | |
1403 | const uint8_t type_code[] = { | |
1404 | [GDB_BREAKPOINT_HW] = 0x0, | |
1405 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
1406 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
1407 | }; | |
1408 | const uint8_t len_code[] = { | |
1409 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
1410 | }; | |
1411 | int n; | |
1412 | ||
1413 | if (kvm_sw_breakpoints_active(env)) | |
1414 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; | |
1415 | ||
1416 | if (nb_hw_breakpoint > 0) { | |
1417 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1418 | dbg->arch.debugreg[7] = 0x0600; | |
1419 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
1420 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
1421 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
1422 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
1423 | (len_code[hw_breakpoint[n].len] << (18 + n*4)); | |
1424 | } | |
1425 | } | |
f1665b21 SY |
1426 | /* Legal xcr0 for loading */ |
1427 | env->xcr0 = 1; | |
e22a25c9 AL |
1428 | } |
1429 | #endif /* KVM_CAP_SET_GUEST_DEBUG */ | |
4513d923 GN |
1430 | |
1431 | bool kvm_arch_stop_on_emulation_error(CPUState *env) | |
1432 | { | |
1433 | return !(env->cr[0] & CR0_PE_MASK) || | |
1434 | ((env->segs[R_CS].selector & 3) != 3); | |
1435 | } | |
1436 |