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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
9c17d615 PB |
24 | #include "sysemu/sysemu.h" |
25 | #include "sysemu/kvm.h" | |
1d31f66b | 26 | #include "kvm_i386.h" |
05330448 | 27 | #include "cpu.h" |
022c62cb | 28 | #include "exec/gdbstub.h" |
1de7afc9 PB |
29 | #include "qemu/host-utils.h" |
30 | #include "qemu/config-file.h" | |
0d09e41a PB |
31 | #include "hw/i386/pc.h" |
32 | #include "hw/i386/apic.h" | |
022c62cb | 33 | #include "exec/ioport.h" |
92067bf4 | 34 | #include <asm/hyperv.h> |
a2cb15b0 | 35 | #include "hw/pci/pci.h" |
05330448 AL |
36 | |
37 | //#define DEBUG_KVM | |
38 | ||
39 | #ifdef DEBUG_KVM | |
8c0d577e | 40 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
42 | #else | |
8c0d577e | 43 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
44 | do { } while (0) |
45 | #endif | |
46 | ||
1a03675d GC |
47 | #define MSR_KVM_WALL_CLOCK 0x11 |
48 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
49 | ||
c0532a76 MT |
50 | #ifndef BUS_MCEERR_AR |
51 | #define BUS_MCEERR_AR 4 | |
52 | #endif | |
53 | #ifndef BUS_MCEERR_AO | |
54 | #define BUS_MCEERR_AO 5 | |
55 | #endif | |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_INFO(SET_TSS_ADDR), | |
59 | KVM_CAP_INFO(EXT_CPUID), | |
60 | KVM_CAP_INFO(MP_STATE), | |
61 | KVM_CAP_LAST_INFO | |
62 | }; | |
25d2e361 | 63 | |
c3a3a7d3 JK |
64 | static bool has_msr_star; |
65 | static bool has_msr_hsave_pa; | |
f28558d3 | 66 | static bool has_msr_tsc_adjust; |
aa82ba54 | 67 | static bool has_msr_tsc_deadline; |
df67696e | 68 | static bool has_msr_feature_control; |
c5999bfc | 69 | static bool has_msr_async_pf_en; |
bc9a839d | 70 | static bool has_msr_pv_eoi_en; |
21e87c46 | 71 | static bool has_msr_misc_enable; |
79e9ebeb | 72 | static bool has_msr_bndcfgs; |
917367aa | 73 | static bool has_msr_kvm_steal_time; |
25d2e361 | 74 | static int lm_capable_kernel; |
7bc3d711 PB |
75 | static bool has_msr_hv_hypercall; |
76 | static bool has_msr_hv_vapic; | |
48a5f3bc | 77 | static bool has_msr_hv_tsc; |
b827df58 | 78 | |
0d894367 PB |
79 | static bool has_msr_architectural_pmu; |
80 | static uint32_t num_architectural_pmu_counters; | |
81 | ||
1d31f66b PM |
82 | bool kvm_allows_irq0_override(void) |
83 | { | |
84 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
85 | } | |
86 | ||
b827df58 AK |
87 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
88 | { | |
89 | struct kvm_cpuid2 *cpuid; | |
90 | int r, size; | |
91 | ||
92 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
7267c094 | 93 | cpuid = (struct kvm_cpuid2 *)g_malloc0(size); |
b827df58 AK |
94 | cpuid->nent = max; |
95 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
96 | if (r == 0 && cpuid->nent >= max) { |
97 | r = -E2BIG; | |
98 | } | |
b827df58 AK |
99 | if (r < 0) { |
100 | if (r == -E2BIG) { | |
7267c094 | 101 | g_free(cpuid); |
b827df58 AK |
102 | return NULL; |
103 | } else { | |
104 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
105 | strerror(-r)); | |
106 | exit(1); | |
107 | } | |
108 | } | |
109 | return cpuid; | |
110 | } | |
111 | ||
dd87f8a6 EH |
112 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough |
113 | * for all entries. | |
114 | */ | |
115 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
116 | { | |
117 | struct kvm_cpuid2 *cpuid; | |
118 | int max = 1; | |
119 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
120 | max *= 2; | |
121 | } | |
122 | return cpuid; | |
123 | } | |
124 | ||
0c31b744 GC |
125 | struct kvm_para_features { |
126 | int cap; | |
127 | int feature; | |
128 | } para_features[] = { | |
129 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
130 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
131 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 132 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
133 | { -1, -1 } |
134 | }; | |
135 | ||
ba9bc59e | 136 | static int get_para_features(KVMState *s) |
0c31b744 GC |
137 | { |
138 | int i, features = 0; | |
139 | ||
140 | for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { | |
ba9bc59e | 141 | if (kvm_check_extension(s, para_features[i].cap)) { |
0c31b744 GC |
142 | features |= (1 << para_features[i].feature); |
143 | } | |
144 | } | |
145 | ||
146 | return features; | |
147 | } | |
0c31b744 GC |
148 | |
149 | ||
829ae2f9 EH |
150 | /* Returns the value for a specific register on the cpuid entry |
151 | */ | |
152 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
153 | { | |
154 | uint32_t ret = 0; | |
155 | switch (reg) { | |
156 | case R_EAX: | |
157 | ret = entry->eax; | |
158 | break; | |
159 | case R_EBX: | |
160 | ret = entry->ebx; | |
161 | break; | |
162 | case R_ECX: | |
163 | ret = entry->ecx; | |
164 | break; | |
165 | case R_EDX: | |
166 | ret = entry->edx; | |
167 | break; | |
168 | } | |
169 | return ret; | |
170 | } | |
171 | ||
4fb73f1d EH |
172 | /* Find matching entry for function/index on kvm_cpuid2 struct |
173 | */ | |
174 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
175 | uint32_t function, | |
176 | uint32_t index) | |
177 | { | |
178 | int i; | |
179 | for (i = 0; i < cpuid->nent; ++i) { | |
180 | if (cpuid->entries[i].function == function && | |
181 | cpuid->entries[i].index == index) { | |
182 | return &cpuid->entries[i]; | |
183 | } | |
184 | } | |
185 | /* not found: */ | |
186 | return NULL; | |
187 | } | |
188 | ||
ba9bc59e | 189 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 190 | uint32_t index, int reg) |
b827df58 AK |
191 | { |
192 | struct kvm_cpuid2 *cpuid; | |
b827df58 AK |
193 | uint32_t ret = 0; |
194 | uint32_t cpuid_1_edx; | |
8c723b79 | 195 | bool found = false; |
b827df58 | 196 | |
dd87f8a6 | 197 | cpuid = get_supported_cpuid(s); |
b827df58 | 198 | |
4fb73f1d EH |
199 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); |
200 | if (entry) { | |
201 | found = true; | |
202 | ret = cpuid_entry_get_reg(entry, reg); | |
b827df58 AK |
203 | } |
204 | ||
7b46e5ce EH |
205 | /* Fixups for the data returned by KVM, below */ |
206 | ||
c2acb022 EH |
207 | if (function == 1 && reg == R_EDX) { |
208 | /* KVM before 2.6.30 misreports the following features */ | |
209 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
84bd945c EH |
210 | } else if (function == 1 && reg == R_ECX) { |
211 | /* We can set the hypervisor flag, even if KVM does not return it on | |
212 | * GET_SUPPORTED_CPUID | |
213 | */ | |
214 | ret |= CPUID_EXT_HYPERVISOR; | |
ac67ee26 EH |
215 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it |
216 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
217 | * and the irqchip is in the kernel. | |
218 | */ | |
219 | if (kvm_irqchip_in_kernel() && | |
220 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
221 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
222 | } | |
41e5e76d EH |
223 | |
224 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
225 | * without the in-kernel irqchip | |
226 | */ | |
227 | if (!kvm_irqchip_in_kernel()) { | |
228 | ret &= ~CPUID_EXT_X2APIC; | |
b827df58 | 229 | } |
c2acb022 EH |
230 | } else if (function == 0x80000001 && reg == R_EDX) { |
231 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
232 | * so add missing bits according to the AMD spec: | |
233 | */ | |
234 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
235 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
b827df58 AK |
236 | } |
237 | ||
7267c094 | 238 | g_free(cpuid); |
b827df58 | 239 | |
0c31b744 | 240 | /* fallback for older kernels */ |
8c723b79 | 241 | if ((function == KVM_CPUID_FEATURES) && !found) { |
ba9bc59e | 242 | ret = get_para_features(s); |
b9bec74b | 243 | } |
0c31b744 GC |
244 | |
245 | return ret; | |
bb0300dc | 246 | } |
bb0300dc | 247 | |
3c85e74f HY |
248 | typedef struct HWPoisonPage { |
249 | ram_addr_t ram_addr; | |
250 | QLIST_ENTRY(HWPoisonPage) list; | |
251 | } HWPoisonPage; | |
252 | ||
253 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
254 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
255 | ||
256 | static void kvm_unpoison_all(void *param) | |
257 | { | |
258 | HWPoisonPage *page, *next_page; | |
259 | ||
260 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
261 | QLIST_REMOVE(page, list); | |
262 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
7267c094 | 263 | g_free(page); |
3c85e74f HY |
264 | } |
265 | } | |
266 | ||
3c85e74f HY |
267 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
268 | { | |
269 | HWPoisonPage *page; | |
270 | ||
271 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
272 | if (page->ram_addr == ram_addr) { | |
273 | return; | |
274 | } | |
275 | } | |
7267c094 | 276 | page = g_malloc(sizeof(HWPoisonPage)); |
3c85e74f HY |
277 | page->ram_addr = ram_addr; |
278 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
279 | } | |
280 | ||
e7701825 MT |
281 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
282 | int *max_banks) | |
283 | { | |
284 | int r; | |
285 | ||
14a09518 | 286 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
287 | if (r > 0) { |
288 | *max_banks = r; | |
289 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
290 | } | |
291 | return -ENOSYS; | |
292 | } | |
293 | ||
bee615d4 | 294 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) |
e7701825 | 295 | { |
bee615d4 | 296 | CPUX86State *env = &cpu->env; |
c34d440a JK |
297 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
298 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
299 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 300 | |
c34d440a JK |
301 | if (code == BUS_MCEERR_AR) { |
302 | status |= MCI_STATUS_AR | 0x134; | |
303 | mcg_status |= MCG_STATUS_EIPV; | |
304 | } else { | |
305 | status |= 0xc0; | |
306 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 307 | } |
8c5cf3b6 | 308 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, |
c34d440a JK |
309 | (MCM_ADDR_PHYS << 6) | 0xc, |
310 | cpu_x86_support_mca_broadcast(env) ? | |
311 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 312 | } |
419fb20a JK |
313 | |
314 | static void hardware_memory_error(void) | |
315 | { | |
316 | fprintf(stderr, "Hardware memory error!\n"); | |
317 | exit(1); | |
318 | } | |
319 | ||
20d695a9 | 320 | int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) |
419fb20a | 321 | { |
20d695a9 AF |
322 | X86CPU *cpu = X86_CPU(c); |
323 | CPUX86State *env = &cpu->env; | |
419fb20a | 324 | ram_addr_t ram_addr; |
a8170e5e | 325 | hwaddr paddr; |
419fb20a JK |
326 | |
327 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a | 328 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
1b5ec234 | 329 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
a60f24b5 | 330 | !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { |
419fb20a JK |
331 | fprintf(stderr, "Hardware memory error for memory used by " |
332 | "QEMU itself instead of guest system!\n"); | |
333 | /* Hope we are lucky for AO MCE */ | |
334 | if (code == BUS_MCEERR_AO) { | |
335 | return 0; | |
336 | } else { | |
337 | hardware_memory_error(); | |
338 | } | |
339 | } | |
3c85e74f | 340 | kvm_hwpoison_page_add(ram_addr); |
bee615d4 | 341 | kvm_mce_inject(cpu, paddr, code); |
e56ff191 | 342 | } else { |
419fb20a JK |
343 | if (code == BUS_MCEERR_AO) { |
344 | return 0; | |
345 | } else if (code == BUS_MCEERR_AR) { | |
346 | hardware_memory_error(); | |
347 | } else { | |
348 | return 1; | |
349 | } | |
350 | } | |
351 | return 0; | |
352 | } | |
353 | ||
354 | int kvm_arch_on_sigbus(int code, void *addr) | |
355 | { | |
182735ef AF |
356 | X86CPU *cpu = X86_CPU(first_cpu); |
357 | ||
358 | if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
419fb20a | 359 | ram_addr_t ram_addr; |
a8170e5e | 360 | hwaddr paddr; |
419fb20a JK |
361 | |
362 | /* Hope we are lucky for AO MCE */ | |
1b5ec234 | 363 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
182735ef | 364 | !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, |
a60f24b5 | 365 | addr, &paddr)) { |
419fb20a JK |
366 | fprintf(stderr, "Hardware memory error for memory used by " |
367 | "QEMU itself instead of guest system!: %p\n", addr); | |
368 | return 0; | |
369 | } | |
3c85e74f | 370 | kvm_hwpoison_page_add(ram_addr); |
182735ef | 371 | kvm_mce_inject(X86_CPU(first_cpu), paddr, code); |
e56ff191 | 372 | } else { |
419fb20a JK |
373 | if (code == BUS_MCEERR_AO) { |
374 | return 0; | |
375 | } else if (code == BUS_MCEERR_AR) { | |
376 | hardware_memory_error(); | |
377 | } else { | |
378 | return 1; | |
379 | } | |
380 | } | |
381 | return 0; | |
382 | } | |
e7701825 | 383 | |
1bc22652 | 384 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) |
ab443475 | 385 | { |
1bc22652 AF |
386 | CPUX86State *env = &cpu->env; |
387 | ||
ab443475 JK |
388 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
389 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
390 | struct kvm_x86_mce mce; | |
391 | ||
392 | env->exception_injected = -1; | |
393 | ||
394 | /* | |
395 | * There must be at least one bank in use if an MCE is pending. | |
396 | * Find it and use its values for the event injection. | |
397 | */ | |
398 | for (bank = 0; bank < bank_num; bank++) { | |
399 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
400 | break; | |
401 | } | |
402 | } | |
403 | assert(bank < bank_num); | |
404 | ||
405 | mce.bank = bank; | |
406 | mce.status = env->mce_banks[bank * 4 + 1]; | |
407 | mce.mcg_status = env->mcg_status; | |
408 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
409 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
410 | ||
1bc22652 | 411 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); |
ab443475 | 412 | } |
ab443475 JK |
413 | return 0; |
414 | } | |
415 | ||
1dfb4dd9 | 416 | static void cpu_update_state(void *opaque, int running, RunState state) |
b8cc45d6 | 417 | { |
317ac620 | 418 | CPUX86State *env = opaque; |
b8cc45d6 GC |
419 | |
420 | if (running) { | |
421 | env->tsc_valid = false; | |
422 | } | |
423 | } | |
424 | ||
83b17af5 | 425 | unsigned long kvm_arch_vcpu_id(CPUState *cs) |
b164e48e | 426 | { |
83b17af5 EH |
427 | X86CPU *cpu = X86_CPU(cs); |
428 | return cpu->env.cpuid_apic_id; | |
b164e48e EH |
429 | } |
430 | ||
92067bf4 IM |
431 | #ifndef KVM_CPUID_SIGNATURE_NEXT |
432 | #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 | |
433 | #endif | |
434 | ||
435 | static bool hyperv_hypercall_available(X86CPU *cpu) | |
436 | { | |
437 | return cpu->hyperv_vapic || | |
438 | (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY); | |
439 | } | |
440 | ||
441 | static bool hyperv_enabled(X86CPU *cpu) | |
442 | { | |
7bc3d711 PB |
443 | CPUState *cs = CPU(cpu); |
444 | return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 && | |
445 | (hyperv_hypercall_available(cpu) || | |
48a5f3bc | 446 | cpu->hyperv_time || |
7bc3d711 | 447 | cpu->hyperv_relaxed_timing); |
92067bf4 IM |
448 | } |
449 | ||
f8bb0565 | 450 | #define KVM_MAX_CPUID_ENTRIES 100 |
0893d460 | 451 | |
20d695a9 | 452 | int kvm_arch_init_vcpu(CPUState *cs) |
05330448 AL |
453 | { |
454 | struct { | |
486bd5a2 | 455 | struct kvm_cpuid2 cpuid; |
f8bb0565 | 456 | struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; |
541dc0d4 | 457 | } QEMU_PACKED cpuid_data; |
20d695a9 AF |
458 | X86CPU *cpu = X86_CPU(cs); |
459 | CPUX86State *env = &cpu->env; | |
486bd5a2 | 460 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 461 | uint32_t unused; |
bb0300dc | 462 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 463 | uint32_t signature[3]; |
234cc647 | 464 | int kvm_base = KVM_CPUID_SIGNATURE; |
e7429073 | 465 | int r; |
05330448 | 466 | |
ef4cbe14 SW |
467 | memset(&cpuid_data, 0, sizeof(cpuid_data)); |
468 | ||
05330448 AL |
469 | cpuid_i = 0; |
470 | ||
bb0300dc | 471 | /* Paravirtualization CPUIDs */ |
234cc647 PB |
472 | if (hyperv_enabled(cpu)) { |
473 | c = &cpuid_data.entries[cpuid_i++]; | |
474 | c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; | |
eab70139 VR |
475 | memcpy(signature, "Microsoft Hv", 12); |
476 | c->eax = HYPERV_CPUID_MIN; | |
234cc647 PB |
477 | c->ebx = signature[0]; |
478 | c->ecx = signature[1]; | |
479 | c->edx = signature[2]; | |
0c31b744 | 480 | |
234cc647 PB |
481 | c = &cpuid_data.entries[cpuid_i++]; |
482 | c->function = HYPERV_CPUID_INTERFACE; | |
eab70139 VR |
483 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); |
484 | c->eax = signature[0]; | |
234cc647 PB |
485 | c->ebx = 0; |
486 | c->ecx = 0; | |
487 | c->edx = 0; | |
eab70139 VR |
488 | |
489 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 VR |
490 | c->function = HYPERV_CPUID_VERSION; |
491 | c->eax = 0x00001bbc; | |
492 | c->ebx = 0x00060001; | |
493 | ||
494 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 | 495 | c->function = HYPERV_CPUID_FEATURES; |
92067bf4 | 496 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
497 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
498 | } | |
92067bf4 | 499 | if (cpu->hyperv_vapic) { |
eab70139 VR |
500 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
501 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
7bc3d711 | 502 | has_msr_hv_vapic = true; |
eab70139 | 503 | } |
48a5f3bc VR |
504 | if (cpu->hyperv_time && |
505 | kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { | |
506 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
507 | c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE; | |
508 | c->eax |= 0x200; | |
509 | has_msr_hv_tsc = true; | |
510 | } | |
eab70139 | 511 | c = &cpuid_data.entries[cpuid_i++]; |
eab70139 | 512 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; |
92067bf4 | 513 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
514 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; |
515 | } | |
7bc3d711 | 516 | if (has_msr_hv_vapic) { |
eab70139 VR |
517 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; |
518 | } | |
92067bf4 | 519 | c->ebx = cpu->hyperv_spinlock_attempts; |
eab70139 VR |
520 | |
521 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 VR |
522 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; |
523 | c->eax = 0x40; | |
524 | c->ebx = 0x40; | |
525 | ||
234cc647 | 526 | kvm_base = KVM_CPUID_SIGNATURE_NEXT; |
7bc3d711 | 527 | has_msr_hv_hypercall = true; |
eab70139 VR |
528 | } |
529 | ||
234cc647 PB |
530 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); |
531 | c = &cpuid_data.entries[cpuid_i++]; | |
532 | c->function = KVM_CPUID_SIGNATURE | kvm_base; | |
533 | c->eax = 0; | |
534 | c->ebx = signature[0]; | |
535 | c->ecx = signature[1]; | |
536 | c->edx = signature[2]; | |
537 | ||
538 | c = &cpuid_data.entries[cpuid_i++]; | |
539 | c->function = KVM_CPUID_FEATURES | kvm_base; | |
540 | c->eax = env->features[FEAT_KVM]; | |
541 | ||
0c31b744 | 542 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 543 | |
bc9a839d MT |
544 | has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI); |
545 | ||
917367aa MT |
546 | has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME); |
547 | ||
a33609ca | 548 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
549 | |
550 | for (i = 0; i <= limit; i++) { | |
f8bb0565 IM |
551 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
552 | fprintf(stderr, "unsupported level value: 0x%x\n", limit); | |
553 | abort(); | |
554 | } | |
bb0300dc | 555 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
556 | |
557 | switch (i) { | |
a36b1029 AL |
558 | case 2: { |
559 | /* Keep reading function 2 till all the input is received */ | |
560 | int times; | |
561 | ||
a36b1029 | 562 | c->function = i; |
a33609ca AL |
563 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
564 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
565 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
566 | times = c->eax & 0xff; | |
a36b1029 AL |
567 | |
568 | for (j = 1; j < times; ++j) { | |
f8bb0565 IM |
569 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
570 | fprintf(stderr, "cpuid_data is full, no space for " | |
571 | "cpuid(eax:2):eax & 0xf = 0x%x\n", times); | |
572 | abort(); | |
573 | } | |
a33609ca | 574 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 575 | c->function = i; |
a33609ca AL |
576 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
577 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
578 | } |
579 | break; | |
580 | } | |
486bd5a2 AL |
581 | case 4: |
582 | case 0xb: | |
583 | case 0xd: | |
584 | for (j = 0; ; j++) { | |
31e8c696 AP |
585 | if (i == 0xd && j == 64) { |
586 | break; | |
587 | } | |
486bd5a2 AL |
588 | c->function = i; |
589 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
590 | c->index = j; | |
a33609ca | 591 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 592 | |
b9bec74b | 593 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 594 | break; |
b9bec74b JK |
595 | } |
596 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 597 | break; |
b9bec74b JK |
598 | } |
599 | if (i == 0xd && c->eax == 0) { | |
31e8c696 | 600 | continue; |
b9bec74b | 601 | } |
f8bb0565 IM |
602 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
603 | fprintf(stderr, "cpuid_data is full, no space for " | |
604 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
605 | abort(); | |
606 | } | |
a33609ca | 607 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
608 | } |
609 | break; | |
610 | default: | |
486bd5a2 | 611 | c->function = i; |
a33609ca AL |
612 | c->flags = 0; |
613 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
614 | break; |
615 | } | |
05330448 | 616 | } |
0d894367 PB |
617 | |
618 | if (limit >= 0x0a) { | |
619 | uint32_t ver; | |
620 | ||
621 | cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused); | |
622 | if ((ver & 0xff) > 0) { | |
623 | has_msr_architectural_pmu = true; | |
624 | num_architectural_pmu_counters = (ver & 0xff00) >> 8; | |
625 | ||
626 | /* Shouldn't be more than 32, since that's the number of bits | |
627 | * available in EBX to tell us _which_ counters are available. | |
628 | * Play it safe. | |
629 | */ | |
630 | if (num_architectural_pmu_counters > MAX_GP_COUNTERS) { | |
631 | num_architectural_pmu_counters = MAX_GP_COUNTERS; | |
632 | } | |
633 | } | |
634 | } | |
635 | ||
a33609ca | 636 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
637 | |
638 | for (i = 0x80000000; i <= limit; i++) { | |
f8bb0565 IM |
639 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
640 | fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); | |
641 | abort(); | |
642 | } | |
bb0300dc | 643 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 644 | |
05330448 | 645 | c->function = i; |
a33609ca AL |
646 | c->flags = 0; |
647 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
648 | } |
649 | ||
b3baa152 BW |
650 | /* Call Centaur's CPUID instructions they are supported. */ |
651 | if (env->cpuid_xlevel2 > 0) { | |
b3baa152 BW |
652 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
653 | ||
654 | for (i = 0xC0000000; i <= limit; i++) { | |
f8bb0565 IM |
655 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
656 | fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); | |
657 | abort(); | |
658 | } | |
b3baa152 BW |
659 | c = &cpuid_data.entries[cpuid_i++]; |
660 | ||
661 | c->function = i; | |
662 | c->flags = 0; | |
663 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
664 | } | |
665 | } | |
666 | ||
05330448 AL |
667 | cpuid_data.cpuid.nent = cpuid_i; |
668 | ||
e7701825 | 669 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
0514ef2f | 670 | && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == |
fc7a504c | 671 | (CPUID_MCE | CPUID_MCA) |
a60f24b5 | 672 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { |
e7701825 MT |
673 | uint64_t mcg_cap; |
674 | int banks; | |
32a42024 | 675 | int ret; |
e7701825 | 676 | |
a60f24b5 | 677 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); |
75d49497 JK |
678 | if (ret < 0) { |
679 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
680 | return ret; | |
e7701825 | 681 | } |
75d49497 JK |
682 | |
683 | if (banks > MCE_BANKS_DEF) { | |
684 | banks = MCE_BANKS_DEF; | |
685 | } | |
686 | mcg_cap &= MCE_CAP_DEF; | |
687 | mcg_cap |= banks; | |
1bc22652 | 688 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap); |
75d49497 JK |
689 | if (ret < 0) { |
690 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
691 | return ret; | |
692 | } | |
693 | ||
694 | env->mcg_cap = mcg_cap; | |
e7701825 | 695 | } |
e7701825 | 696 | |
b8cc45d6 GC |
697 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
698 | ||
df67696e LJ |
699 | c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); |
700 | if (c) { | |
701 | has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || | |
702 | !!(c->ecx & CPUID_EXT_SMX); | |
703 | } | |
704 | ||
7e680753 | 705 | cpuid_data.cpuid.padding = 0; |
1bc22652 | 706 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); |
fdc9c41a JK |
707 | if (r) { |
708 | return r; | |
709 | } | |
e7429073 | 710 | |
a60f24b5 | 711 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL); |
e7429073 | 712 | if (r && env->tsc_khz) { |
1bc22652 | 713 | r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz); |
e7429073 JR |
714 | if (r < 0) { |
715 | fprintf(stderr, "KVM_SET_TSC_KHZ failed\n"); | |
716 | return r; | |
717 | } | |
718 | } | |
e7429073 | 719 | |
fabacc0f JK |
720 | if (kvm_has_xsave()) { |
721 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); | |
722 | } | |
723 | ||
e7429073 | 724 | return 0; |
05330448 AL |
725 | } |
726 | ||
20d695a9 | 727 | void kvm_arch_reset_vcpu(CPUState *cs) |
caa5af0f | 728 | { |
20d695a9 AF |
729 | X86CPU *cpu = X86_CPU(cs); |
730 | CPUX86State *env = &cpu->env; | |
dd673288 | 731 | |
e73223a5 | 732 | env->exception_injected = -1; |
0e607a80 | 733 | env->interrupt_injected = -1; |
1a5e9d2f | 734 | env->xcr0 = 1; |
ddced198 | 735 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 736 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
737 | KVM_MP_STATE_UNINITIALIZED; |
738 | } else { | |
739 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
740 | } | |
caa5af0f JK |
741 | } |
742 | ||
c3a3a7d3 | 743 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 744 | { |
75b10c43 | 745 | static int kvm_supported_msrs; |
c3a3a7d3 | 746 | int ret = 0; |
05330448 AL |
747 | |
748 | /* first time */ | |
75b10c43 | 749 | if (kvm_supported_msrs == 0) { |
05330448 AL |
750 | struct kvm_msr_list msr_list, *kvm_msr_list; |
751 | ||
75b10c43 | 752 | kvm_supported_msrs = -1; |
05330448 AL |
753 | |
754 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
755 | * save/restore */ | |
4c9f7372 | 756 | msr_list.nmsrs = 0; |
c3a3a7d3 | 757 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 758 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 759 | return ret; |
6fb6d245 | 760 | } |
d9db889f JK |
761 | /* Old kernel modules had a bug and could write beyond the provided |
762 | memory. Allocate at least a safe amount of 1K. */ | |
7267c094 | 763 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
d9db889f JK |
764 | msr_list.nmsrs * |
765 | sizeof(msr_list.indices[0]))); | |
05330448 | 766 | |
55308450 | 767 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 768 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
769 | if (ret >= 0) { |
770 | int i; | |
771 | ||
772 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
773 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 774 | has_msr_star = true; |
75b10c43 MT |
775 | continue; |
776 | } | |
777 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 778 | has_msr_hsave_pa = true; |
75b10c43 | 779 | continue; |
05330448 | 780 | } |
f28558d3 WA |
781 | if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { |
782 | has_msr_tsc_adjust = true; | |
783 | continue; | |
784 | } | |
aa82ba54 LJ |
785 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { |
786 | has_msr_tsc_deadline = true; | |
787 | continue; | |
788 | } | |
21e87c46 AK |
789 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { |
790 | has_msr_misc_enable = true; | |
791 | continue; | |
792 | } | |
79e9ebeb LJ |
793 | if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) { |
794 | has_msr_bndcfgs = true; | |
795 | continue; | |
796 | } | |
05330448 AL |
797 | } |
798 | } | |
799 | ||
7267c094 | 800 | g_free(kvm_msr_list); |
05330448 AL |
801 | } |
802 | ||
c3a3a7d3 | 803 | return ret; |
05330448 AL |
804 | } |
805 | ||
cad1e282 | 806 | int kvm_arch_init(KVMState *s) |
20420430 | 807 | { |
11076198 | 808 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 809 | uint64_t shadow_mem; |
20420430 | 810 | int ret; |
25d2e361 | 811 | struct utsname utsname; |
20420430 | 812 | |
c3a3a7d3 | 813 | ret = kvm_get_supported_msrs(s); |
20420430 | 814 | if (ret < 0) { |
20420430 SY |
815 | return ret; |
816 | } | |
25d2e361 MT |
817 | |
818 | uname(&utsname); | |
819 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
820 | ||
4c5b10b7 | 821 | /* |
11076198 JK |
822 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
823 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
824 | * Since these must be part of guest physical memory, we need to allocate | |
825 | * them, both by setting their start addresses in the kernel and by | |
826 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
827 | * | |
828 | * Older KVM versions may not support setting the identity map base. In | |
829 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
830 | * size. | |
4c5b10b7 | 831 | */ |
11076198 JK |
832 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
833 | /* Allows up to 16M BIOSes. */ | |
834 | identity_base = 0xfeffc000; | |
835 | ||
836 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
837 | if (ret < 0) { | |
838 | return ret; | |
839 | } | |
4c5b10b7 | 840 | } |
e56ff191 | 841 | |
11076198 JK |
842 | /* Set TSS base one page after EPT identity map. */ |
843 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
844 | if (ret < 0) { |
845 | return ret; | |
846 | } | |
847 | ||
11076198 JK |
848 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
849 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 850 | if (ret < 0) { |
11076198 | 851 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
852 | return ret; |
853 | } | |
3c85e74f | 854 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 855 | |
36ad0e94 MA |
856 | shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(), |
857 | "kvm_shadow_mem", -1); | |
858 | if (shadow_mem != -1) { | |
859 | shadow_mem /= 4096; | |
860 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
861 | if (ret < 0) { | |
862 | return ret; | |
39d6960a JK |
863 | } |
864 | } | |
11076198 | 865 | return 0; |
05330448 | 866 | } |
b9bec74b | 867 | |
05330448 AL |
868 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
869 | { | |
870 | lhs->selector = rhs->selector; | |
871 | lhs->base = rhs->base; | |
872 | lhs->limit = rhs->limit; | |
873 | lhs->type = 3; | |
874 | lhs->present = 1; | |
875 | lhs->dpl = 3; | |
876 | lhs->db = 0; | |
877 | lhs->s = 1; | |
878 | lhs->l = 0; | |
879 | lhs->g = 0; | |
880 | lhs->avl = 0; | |
881 | lhs->unusable = 0; | |
882 | } | |
883 | ||
884 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
885 | { | |
886 | unsigned flags = rhs->flags; | |
887 | lhs->selector = rhs->selector; | |
888 | lhs->base = rhs->base; | |
889 | lhs->limit = rhs->limit; | |
890 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
891 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 892 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
893 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
894 | lhs->s = (flags & DESC_S_MASK) != 0; | |
895 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
896 | lhs->g = (flags & DESC_G_MASK) != 0; | |
897 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
898 | lhs->unusable = 0; | |
7e680753 | 899 | lhs->padding = 0; |
05330448 AL |
900 | } |
901 | ||
902 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
903 | { | |
904 | lhs->selector = rhs->selector; | |
905 | lhs->base = rhs->base; | |
906 | lhs->limit = rhs->limit; | |
b9bec74b JK |
907 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
908 | (rhs->present * DESC_P_MASK) | | |
909 | (rhs->dpl << DESC_DPL_SHIFT) | | |
910 | (rhs->db << DESC_B_SHIFT) | | |
911 | (rhs->s * DESC_S_MASK) | | |
912 | (rhs->l << DESC_L_SHIFT) | | |
913 | (rhs->g * DESC_G_MASK) | | |
914 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
915 | } |
916 | ||
917 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
918 | { | |
b9bec74b | 919 | if (set) { |
05330448 | 920 | *kvm_reg = *qemu_reg; |
b9bec74b | 921 | } else { |
05330448 | 922 | *qemu_reg = *kvm_reg; |
b9bec74b | 923 | } |
05330448 AL |
924 | } |
925 | ||
1bc22652 | 926 | static int kvm_getput_regs(X86CPU *cpu, int set) |
05330448 | 927 | { |
1bc22652 | 928 | CPUX86State *env = &cpu->env; |
05330448 AL |
929 | struct kvm_regs regs; |
930 | int ret = 0; | |
931 | ||
932 | if (!set) { | |
1bc22652 | 933 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); |
b9bec74b | 934 | if (ret < 0) { |
05330448 | 935 | return ret; |
b9bec74b | 936 | } |
05330448 AL |
937 | } |
938 | ||
939 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
940 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
941 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
942 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
943 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
944 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
945 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
946 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
947 | #ifdef TARGET_X86_64 | |
948 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
949 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
950 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
951 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
952 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
953 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
954 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
955 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
956 | #endif | |
957 | ||
958 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
959 | kvm_getput_reg(®s.rip, &env->eip, set); | |
960 | ||
b9bec74b | 961 | if (set) { |
1bc22652 | 962 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); |
b9bec74b | 963 | } |
05330448 AL |
964 | |
965 | return ret; | |
966 | } | |
967 | ||
1bc22652 | 968 | static int kvm_put_fpu(X86CPU *cpu) |
05330448 | 969 | { |
1bc22652 | 970 | CPUX86State *env = &cpu->env; |
05330448 AL |
971 | struct kvm_fpu fpu; |
972 | int i; | |
973 | ||
974 | memset(&fpu, 0, sizeof fpu); | |
975 | fpu.fsw = env->fpus & ~(7 << 11); | |
976 | fpu.fsw |= (env->fpstt & 7) << 11; | |
977 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
978 | fpu.last_opcode = env->fpop; |
979 | fpu.last_ip = env->fpip; | |
980 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
981 | for (i = 0; i < 8; ++i) { |
982 | fpu.ftwx |= (!env->fptags[i]) << i; | |
983 | } | |
05330448 AL |
984 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
985 | memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs); | |
986 | fpu.mxcsr = env->mxcsr; | |
987 | ||
1bc22652 | 988 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); |
05330448 AL |
989 | } |
990 | ||
6b42494b JK |
991 | #define XSAVE_FCW_FSW 0 |
992 | #define XSAVE_FTW_FOP 1 | |
f1665b21 SY |
993 | #define XSAVE_CWD_RIP 2 |
994 | #define XSAVE_CWD_RDP 4 | |
995 | #define XSAVE_MXCSR 6 | |
996 | #define XSAVE_ST_SPACE 8 | |
997 | #define XSAVE_XMM_SPACE 40 | |
998 | #define XSAVE_XSTATE_BV 128 | |
999 | #define XSAVE_YMMH_SPACE 144 | |
79e9ebeb LJ |
1000 | #define XSAVE_BNDREGS 240 |
1001 | #define XSAVE_BNDCSR 256 | |
f1665b21 | 1002 | |
1bc22652 | 1003 | static int kvm_put_xsave(X86CPU *cpu) |
f1665b21 | 1004 | { |
1bc22652 | 1005 | CPUX86State *env = &cpu->env; |
fabacc0f | 1006 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
42cc8fa6 | 1007 | uint16_t cwd, swd, twd; |
fabacc0f | 1008 | int i, r; |
f1665b21 | 1009 | |
b9bec74b | 1010 | if (!kvm_has_xsave()) { |
1bc22652 | 1011 | return kvm_put_fpu(cpu); |
b9bec74b | 1012 | } |
f1665b21 | 1013 | |
f1665b21 | 1014 | memset(xsave, 0, sizeof(struct kvm_xsave)); |
6115c0a8 | 1015 | twd = 0; |
f1665b21 SY |
1016 | swd = env->fpus & ~(7 << 11); |
1017 | swd |= (env->fpstt & 7) << 11; | |
1018 | cwd = env->fpuc; | |
b9bec74b | 1019 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1020 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 1021 | } |
6b42494b JK |
1022 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; |
1023 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
42cc8fa6 JK |
1024 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); |
1025 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
1026 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
1027 | sizeof env->fpregs); | |
1028 | memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, | |
1029 | sizeof env->xmm_regs); | |
1030 | xsave->region[XSAVE_MXCSR] = env->mxcsr; | |
1031 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
1032 | memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, | |
1033 | sizeof env->ymmh_regs); | |
79e9ebeb LJ |
1034 | memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs, |
1035 | sizeof env->bnd_regs); | |
1036 | memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs, | |
1037 | sizeof(env->bndcs_regs)); | |
1bc22652 | 1038 | r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); |
0f53994f | 1039 | return r; |
f1665b21 SY |
1040 | } |
1041 | ||
1bc22652 | 1042 | static int kvm_put_xcrs(X86CPU *cpu) |
f1665b21 | 1043 | { |
1bc22652 | 1044 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1045 | struct kvm_xcrs xcrs; |
1046 | ||
b9bec74b | 1047 | if (!kvm_has_xcrs()) { |
f1665b21 | 1048 | return 0; |
b9bec74b | 1049 | } |
f1665b21 SY |
1050 | |
1051 | xcrs.nr_xcrs = 1; | |
1052 | xcrs.flags = 0; | |
1053 | xcrs.xcrs[0].xcr = 0; | |
1054 | xcrs.xcrs[0].value = env->xcr0; | |
1bc22652 | 1055 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); |
f1665b21 SY |
1056 | } |
1057 | ||
1bc22652 | 1058 | static int kvm_put_sregs(X86CPU *cpu) |
05330448 | 1059 | { |
1bc22652 | 1060 | CPUX86State *env = &cpu->env; |
05330448 AL |
1061 | struct kvm_sregs sregs; |
1062 | ||
0e607a80 JK |
1063 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
1064 | if (env->interrupt_injected >= 0) { | |
1065 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
1066 | (uint64_t)1 << (env->interrupt_injected % 64); | |
1067 | } | |
05330448 AL |
1068 | |
1069 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
1070 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
1071 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
1072 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
1073 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
1074 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
1075 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 1076 | } else { |
b9bec74b JK |
1077 | set_seg(&sregs.cs, &env->segs[R_CS]); |
1078 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
1079 | set_seg(&sregs.es, &env->segs[R_ES]); | |
1080 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
1081 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
1082 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
1083 | } |
1084 | ||
1085 | set_seg(&sregs.tr, &env->tr); | |
1086 | set_seg(&sregs.ldt, &env->ldt); | |
1087 | ||
1088 | sregs.idt.limit = env->idt.limit; | |
1089 | sregs.idt.base = env->idt.base; | |
7e680753 | 1090 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
1091 | sregs.gdt.limit = env->gdt.limit; |
1092 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 1093 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
1094 | |
1095 | sregs.cr0 = env->cr[0]; | |
1096 | sregs.cr2 = env->cr[2]; | |
1097 | sregs.cr3 = env->cr[3]; | |
1098 | sregs.cr4 = env->cr[4]; | |
1099 | ||
02e51483 CF |
1100 | sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); |
1101 | sregs.apic_base = cpu_get_apic_base(cpu->apic_state); | |
05330448 AL |
1102 | |
1103 | sregs.efer = env->efer; | |
1104 | ||
1bc22652 | 1105 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); |
05330448 AL |
1106 | } |
1107 | ||
1108 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
1109 | uint32_t index, uint64_t value) | |
1110 | { | |
1111 | entry->index = index; | |
1112 | entry->data = value; | |
1113 | } | |
1114 | ||
7477cd38 MT |
1115 | static int kvm_put_tscdeadline_msr(X86CPU *cpu) |
1116 | { | |
1117 | CPUX86State *env = &cpu->env; | |
1118 | struct { | |
1119 | struct kvm_msrs info; | |
1120 | struct kvm_msr_entry entries[1]; | |
1121 | } msr_data; | |
1122 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1123 | ||
1124 | if (!has_msr_tsc_deadline) { | |
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
1129 | ||
1130 | msr_data.info.nmsrs = 1; | |
1131 | ||
1132 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1133 | } | |
1134 | ||
6bdf863d JK |
1135 | /* |
1136 | * Provide a separate write service for the feature control MSR in order to | |
1137 | * kick the VCPU out of VMXON or even guest mode on reset. This has to be done | |
1138 | * before writing any other state because forcibly leaving nested mode | |
1139 | * invalidates the VCPU state. | |
1140 | */ | |
1141 | static int kvm_put_msr_feature_control(X86CPU *cpu) | |
1142 | { | |
1143 | struct { | |
1144 | struct kvm_msrs info; | |
1145 | struct kvm_msr_entry entry; | |
1146 | } msr_data; | |
1147 | ||
1148 | kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, | |
1149 | cpu->env.msr_ia32_feature_control); | |
1150 | msr_data.info.nmsrs = 1; | |
1151 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1152 | } | |
1153 | ||
1bc22652 | 1154 | static int kvm_put_msrs(X86CPU *cpu, int level) |
05330448 | 1155 | { |
1bc22652 | 1156 | CPUX86State *env = &cpu->env; |
05330448 AL |
1157 | struct { |
1158 | struct kvm_msrs info; | |
1159 | struct kvm_msr_entry entries[100]; | |
1160 | } msr_data; | |
1161 | struct kvm_msr_entry *msrs = msr_data.entries; | |
0d894367 | 1162 | int n = 0, i; |
05330448 AL |
1163 | |
1164 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1165 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1166 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 1167 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 1168 | if (has_msr_star) { |
b9bec74b JK |
1169 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
1170 | } | |
c3a3a7d3 | 1171 | if (has_msr_hsave_pa) { |
75b10c43 | 1172 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 1173 | } |
f28558d3 WA |
1174 | if (has_msr_tsc_adjust) { |
1175 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); | |
1176 | } | |
21e87c46 AK |
1177 | if (has_msr_misc_enable) { |
1178 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
1179 | env->msr_ia32_misc_enable); | |
1180 | } | |
439d19f2 PB |
1181 | if (has_msr_bndcfgs) { |
1182 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs); | |
1183 | } | |
05330448 | 1184 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1185 | if (lm_capable_kernel) { |
1186 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1187 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1188 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1189 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1190 | } | |
05330448 | 1191 | #endif |
ff5c186b | 1192 | /* |
0d894367 PB |
1193 | * The following MSRs have side effects on the guest or are too heavy |
1194 | * for normal writeback. Limit them to reset or full state updates. | |
ff5c186b JK |
1195 | */ |
1196 | if (level >= KVM_PUT_RESET_STATE) { | |
0522604b | 1197 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); |
ea643051 JK |
1198 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1199 | env->system_time_msr); | |
1200 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
1201 | if (has_msr_async_pf_en) { |
1202 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1203 | env->async_pf_en_msr); | |
1204 | } | |
bc9a839d MT |
1205 | if (has_msr_pv_eoi_en) { |
1206 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN, | |
1207 | env->pv_eoi_en_msr); | |
1208 | } | |
917367aa MT |
1209 | if (has_msr_kvm_steal_time) { |
1210 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME, | |
1211 | env->steal_time_msr); | |
1212 | } | |
0d894367 PB |
1213 | if (has_msr_architectural_pmu) { |
1214 | /* Stop the counter. */ | |
1215 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0); | |
1216 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
1217 | ||
1218 | /* Set the counter values. */ | |
1219 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1220 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i, | |
1221 | env->msr_fixed_counters[i]); | |
1222 | } | |
1223 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1224 | kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i, | |
1225 | env->msr_gp_counters[i]); | |
1226 | kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i, | |
1227 | env->msr_gp_evtsel[i]); | |
1228 | } | |
1229 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS, | |
1230 | env->msr_global_status); | |
1231 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1232 | env->msr_global_ovf_ctrl); | |
1233 | ||
1234 | /* Now start the PMU. */ | |
1235 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, | |
1236 | env->msr_fixed_ctr_ctrl); | |
1237 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, | |
1238 | env->msr_global_ctrl); | |
1239 | } | |
7bc3d711 | 1240 | if (has_msr_hv_hypercall) { |
1c90ef26 VR |
1241 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, |
1242 | env->msr_hv_guest_os_id); | |
1243 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, | |
1244 | env->msr_hv_hypercall); | |
eab70139 | 1245 | } |
7bc3d711 | 1246 | if (has_msr_hv_vapic) { |
5ef68987 VR |
1247 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, |
1248 | env->msr_hv_vapic); | |
eab70139 | 1249 | } |
48a5f3bc VR |
1250 | if (has_msr_hv_tsc) { |
1251 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC, | |
1252 | env->msr_hv_tsc); | |
1253 | } | |
6bdf863d JK |
1254 | |
1255 | /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see | |
1256 | * kvm_put_msr_feature_control. */ | |
ea643051 | 1257 | } |
57780495 | 1258 | if (env->mcg_cap) { |
d8da8574 | 1259 | int i; |
b9bec74b | 1260 | |
c34d440a JK |
1261 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1262 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1263 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1264 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
1265 | } |
1266 | } | |
1a03675d | 1267 | |
05330448 AL |
1268 | msr_data.info.nmsrs = n; |
1269 | ||
1bc22652 | 1270 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); |
05330448 AL |
1271 | |
1272 | } | |
1273 | ||
1274 | ||
1bc22652 | 1275 | static int kvm_get_fpu(X86CPU *cpu) |
05330448 | 1276 | { |
1bc22652 | 1277 | CPUX86State *env = &cpu->env; |
05330448 AL |
1278 | struct kvm_fpu fpu; |
1279 | int i, ret; | |
1280 | ||
1bc22652 | 1281 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); |
b9bec74b | 1282 | if (ret < 0) { |
05330448 | 1283 | return ret; |
b9bec74b | 1284 | } |
05330448 AL |
1285 | |
1286 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1287 | env->fpus = fpu.fsw; | |
1288 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
1289 | env->fpop = fpu.last_opcode; |
1290 | env->fpip = fpu.last_ip; | |
1291 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
1292 | for (i = 0; i < 8; ++i) { |
1293 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1294 | } | |
05330448 AL |
1295 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
1296 | memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs); | |
1297 | env->mxcsr = fpu.mxcsr; | |
1298 | ||
1299 | return 0; | |
1300 | } | |
1301 | ||
1bc22652 | 1302 | static int kvm_get_xsave(X86CPU *cpu) |
f1665b21 | 1303 | { |
1bc22652 | 1304 | CPUX86State *env = &cpu->env; |
fabacc0f | 1305 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
f1665b21 | 1306 | int ret, i; |
42cc8fa6 | 1307 | uint16_t cwd, swd, twd; |
f1665b21 | 1308 | |
b9bec74b | 1309 | if (!kvm_has_xsave()) { |
1bc22652 | 1310 | return kvm_get_fpu(cpu); |
b9bec74b | 1311 | } |
f1665b21 | 1312 | |
1bc22652 | 1313 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); |
0f53994f | 1314 | if (ret < 0) { |
f1665b21 | 1315 | return ret; |
0f53994f | 1316 | } |
f1665b21 | 1317 | |
6b42494b JK |
1318 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1319 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1320 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1321 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
f1665b21 SY |
1322 | env->fpstt = (swd >> 11) & 7; |
1323 | env->fpus = swd; | |
1324 | env->fpuc = cwd; | |
b9bec74b | 1325 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1326 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1327 | } |
42cc8fa6 JK |
1328 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1329 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1330 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1331 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1332 | sizeof env->fpregs); | |
1333 | memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], | |
1334 | sizeof env->xmm_regs); | |
1335 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; | |
1336 | memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], | |
1337 | sizeof env->ymmh_regs); | |
79e9ebeb LJ |
1338 | memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS], |
1339 | sizeof env->bnd_regs); | |
1340 | memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR], | |
1341 | sizeof(env->bndcs_regs)); | |
f1665b21 | 1342 | return 0; |
f1665b21 SY |
1343 | } |
1344 | ||
1bc22652 | 1345 | static int kvm_get_xcrs(X86CPU *cpu) |
f1665b21 | 1346 | { |
1bc22652 | 1347 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1348 | int i, ret; |
1349 | struct kvm_xcrs xcrs; | |
1350 | ||
b9bec74b | 1351 | if (!kvm_has_xcrs()) { |
f1665b21 | 1352 | return 0; |
b9bec74b | 1353 | } |
f1665b21 | 1354 | |
1bc22652 | 1355 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); |
b9bec74b | 1356 | if (ret < 0) { |
f1665b21 | 1357 | return ret; |
b9bec74b | 1358 | } |
f1665b21 | 1359 | |
b9bec74b | 1360 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 | 1361 | /* Only support xcr0 now */ |
0fd53fec PB |
1362 | if (xcrs.xcrs[i].xcr == 0) { |
1363 | env->xcr0 = xcrs.xcrs[i].value; | |
f1665b21 SY |
1364 | break; |
1365 | } | |
b9bec74b | 1366 | } |
f1665b21 | 1367 | return 0; |
f1665b21 SY |
1368 | } |
1369 | ||
1bc22652 | 1370 | static int kvm_get_sregs(X86CPU *cpu) |
05330448 | 1371 | { |
1bc22652 | 1372 | CPUX86State *env = &cpu->env; |
05330448 AL |
1373 | struct kvm_sregs sregs; |
1374 | uint32_t hflags; | |
0e607a80 | 1375 | int bit, i, ret; |
05330448 | 1376 | |
1bc22652 | 1377 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); |
b9bec74b | 1378 | if (ret < 0) { |
05330448 | 1379 | return ret; |
b9bec74b | 1380 | } |
05330448 | 1381 | |
0e607a80 JK |
1382 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1383 | to find it and save its number instead (-1 for none). */ | |
1384 | env->interrupt_injected = -1; | |
1385 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1386 | if (sregs.interrupt_bitmap[i]) { | |
1387 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1388 | env->interrupt_injected = i * 64 + bit; | |
1389 | break; | |
1390 | } | |
1391 | } | |
05330448 AL |
1392 | |
1393 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1394 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1395 | get_seg(&env->segs[R_ES], &sregs.es); | |
1396 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1397 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1398 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1399 | ||
1400 | get_seg(&env->tr, &sregs.tr); | |
1401 | get_seg(&env->ldt, &sregs.ldt); | |
1402 | ||
1403 | env->idt.limit = sregs.idt.limit; | |
1404 | env->idt.base = sregs.idt.base; | |
1405 | env->gdt.limit = sregs.gdt.limit; | |
1406 | env->gdt.base = sregs.gdt.base; | |
1407 | ||
1408 | env->cr[0] = sregs.cr0; | |
1409 | env->cr[2] = sregs.cr2; | |
1410 | env->cr[3] = sregs.cr3; | |
1411 | env->cr[4] = sregs.cr4; | |
1412 | ||
05330448 | 1413 | env->efer = sregs.efer; |
cce47516 JK |
1414 | |
1415 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
05330448 | 1416 | |
b9bec74b JK |
1417 | #define HFLAG_COPY_MASK \ |
1418 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1419 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1420 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1421 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 AL |
1422 | |
1423 | hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; | |
1424 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); | |
1425 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1426 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1427 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1428 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1429 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1430 | |
1431 | if (env->efer & MSR_EFER_LMA) { | |
1432 | hflags |= HF_LMA_MASK; | |
1433 | } | |
1434 | ||
1435 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1436 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1437 | } else { | |
1438 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1439 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1440 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1441 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1442 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1443 | !(hflags & HF_CS32_MASK)) { | |
1444 | hflags |= HF_ADDSEG_MASK; | |
1445 | } else { | |
1446 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1447 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1448 | } | |
05330448 AL |
1449 | } |
1450 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1451 | |
1452 | return 0; | |
1453 | } | |
1454 | ||
1bc22652 | 1455 | static int kvm_get_msrs(X86CPU *cpu) |
05330448 | 1456 | { |
1bc22652 | 1457 | CPUX86State *env = &cpu->env; |
05330448 AL |
1458 | struct { |
1459 | struct kvm_msrs info; | |
1460 | struct kvm_msr_entry entries[100]; | |
1461 | } msr_data; | |
1462 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1463 | int ret, i, n; | |
1464 | ||
1465 | n = 0; | |
1466 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1467 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1468 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1469 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1470 | if (has_msr_star) { |
b9bec74b JK |
1471 | msrs[n++].index = MSR_STAR; |
1472 | } | |
c3a3a7d3 | 1473 | if (has_msr_hsave_pa) { |
75b10c43 | 1474 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1475 | } |
f28558d3 WA |
1476 | if (has_msr_tsc_adjust) { |
1477 | msrs[n++].index = MSR_TSC_ADJUST; | |
1478 | } | |
aa82ba54 LJ |
1479 | if (has_msr_tsc_deadline) { |
1480 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1481 | } | |
21e87c46 AK |
1482 | if (has_msr_misc_enable) { |
1483 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1484 | } | |
df67696e LJ |
1485 | if (has_msr_feature_control) { |
1486 | msrs[n++].index = MSR_IA32_FEATURE_CONTROL; | |
1487 | } | |
79e9ebeb LJ |
1488 | if (has_msr_bndcfgs) { |
1489 | msrs[n++].index = MSR_IA32_BNDCFGS; | |
1490 | } | |
b8cc45d6 GC |
1491 | |
1492 | if (!env->tsc_valid) { | |
1493 | msrs[n++].index = MSR_IA32_TSC; | |
1354869c | 1494 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
1495 | } |
1496 | ||
05330448 | 1497 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1498 | if (lm_capable_kernel) { |
1499 | msrs[n++].index = MSR_CSTAR; | |
1500 | msrs[n++].index = MSR_KERNELGSBASE; | |
1501 | msrs[n++].index = MSR_FMASK; | |
1502 | msrs[n++].index = MSR_LSTAR; | |
1503 | } | |
05330448 | 1504 | #endif |
1a03675d GC |
1505 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1506 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1507 | if (has_msr_async_pf_en) { |
1508 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1509 | } | |
bc9a839d MT |
1510 | if (has_msr_pv_eoi_en) { |
1511 | msrs[n++].index = MSR_KVM_PV_EOI_EN; | |
1512 | } | |
917367aa MT |
1513 | if (has_msr_kvm_steal_time) { |
1514 | msrs[n++].index = MSR_KVM_STEAL_TIME; | |
1515 | } | |
0d894367 PB |
1516 | if (has_msr_architectural_pmu) { |
1517 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL; | |
1518 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL; | |
1519 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS; | |
1520 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL; | |
1521 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1522 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i; | |
1523 | } | |
1524 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1525 | msrs[n++].index = MSR_P6_PERFCTR0 + i; | |
1526 | msrs[n++].index = MSR_P6_EVNTSEL0 + i; | |
1527 | } | |
1528 | } | |
1a03675d | 1529 | |
57780495 MT |
1530 | if (env->mcg_cap) { |
1531 | msrs[n++].index = MSR_MCG_STATUS; | |
1532 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1533 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1534 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1535 | } |
57780495 | 1536 | } |
57780495 | 1537 | |
1c90ef26 VR |
1538 | if (has_msr_hv_hypercall) { |
1539 | msrs[n++].index = HV_X64_MSR_HYPERCALL; | |
1540 | msrs[n++].index = HV_X64_MSR_GUEST_OS_ID; | |
1541 | } | |
5ef68987 VR |
1542 | if (has_msr_hv_vapic) { |
1543 | msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE; | |
1544 | } | |
48a5f3bc VR |
1545 | if (has_msr_hv_tsc) { |
1546 | msrs[n++].index = HV_X64_MSR_REFERENCE_TSC; | |
1547 | } | |
5ef68987 | 1548 | |
05330448 | 1549 | msr_data.info.nmsrs = n; |
1bc22652 | 1550 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); |
b9bec74b | 1551 | if (ret < 0) { |
05330448 | 1552 | return ret; |
b9bec74b | 1553 | } |
05330448 AL |
1554 | |
1555 | for (i = 0; i < ret; i++) { | |
0d894367 PB |
1556 | uint32_t index = msrs[i].index; |
1557 | switch (index) { | |
05330448 AL |
1558 | case MSR_IA32_SYSENTER_CS: |
1559 | env->sysenter_cs = msrs[i].data; | |
1560 | break; | |
1561 | case MSR_IA32_SYSENTER_ESP: | |
1562 | env->sysenter_esp = msrs[i].data; | |
1563 | break; | |
1564 | case MSR_IA32_SYSENTER_EIP: | |
1565 | env->sysenter_eip = msrs[i].data; | |
1566 | break; | |
0c03266a JK |
1567 | case MSR_PAT: |
1568 | env->pat = msrs[i].data; | |
1569 | break; | |
05330448 AL |
1570 | case MSR_STAR: |
1571 | env->star = msrs[i].data; | |
1572 | break; | |
1573 | #ifdef TARGET_X86_64 | |
1574 | case MSR_CSTAR: | |
1575 | env->cstar = msrs[i].data; | |
1576 | break; | |
1577 | case MSR_KERNELGSBASE: | |
1578 | env->kernelgsbase = msrs[i].data; | |
1579 | break; | |
1580 | case MSR_FMASK: | |
1581 | env->fmask = msrs[i].data; | |
1582 | break; | |
1583 | case MSR_LSTAR: | |
1584 | env->lstar = msrs[i].data; | |
1585 | break; | |
1586 | #endif | |
1587 | case MSR_IA32_TSC: | |
1588 | env->tsc = msrs[i].data; | |
1589 | break; | |
f28558d3 WA |
1590 | case MSR_TSC_ADJUST: |
1591 | env->tsc_adjust = msrs[i].data; | |
1592 | break; | |
aa82ba54 LJ |
1593 | case MSR_IA32_TSCDEADLINE: |
1594 | env->tsc_deadline = msrs[i].data; | |
1595 | break; | |
aa851e36 MT |
1596 | case MSR_VM_HSAVE_PA: |
1597 | env->vm_hsave = msrs[i].data; | |
1598 | break; | |
1a03675d GC |
1599 | case MSR_KVM_SYSTEM_TIME: |
1600 | env->system_time_msr = msrs[i].data; | |
1601 | break; | |
1602 | case MSR_KVM_WALL_CLOCK: | |
1603 | env->wall_clock_msr = msrs[i].data; | |
1604 | break; | |
57780495 MT |
1605 | case MSR_MCG_STATUS: |
1606 | env->mcg_status = msrs[i].data; | |
1607 | break; | |
1608 | case MSR_MCG_CTL: | |
1609 | env->mcg_ctl = msrs[i].data; | |
1610 | break; | |
21e87c46 AK |
1611 | case MSR_IA32_MISC_ENABLE: |
1612 | env->msr_ia32_misc_enable = msrs[i].data; | |
1613 | break; | |
0779caeb ACL |
1614 | case MSR_IA32_FEATURE_CONTROL: |
1615 | env->msr_ia32_feature_control = msrs[i].data; | |
df67696e | 1616 | break; |
79e9ebeb LJ |
1617 | case MSR_IA32_BNDCFGS: |
1618 | env->msr_bndcfgs = msrs[i].data; | |
1619 | break; | |
57780495 | 1620 | default: |
57780495 MT |
1621 | if (msrs[i].index >= MSR_MC0_CTL && |
1622 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
1623 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 1624 | } |
d8da8574 | 1625 | break; |
f6584ee2 GN |
1626 | case MSR_KVM_ASYNC_PF_EN: |
1627 | env->async_pf_en_msr = msrs[i].data; | |
1628 | break; | |
bc9a839d MT |
1629 | case MSR_KVM_PV_EOI_EN: |
1630 | env->pv_eoi_en_msr = msrs[i].data; | |
1631 | break; | |
917367aa MT |
1632 | case MSR_KVM_STEAL_TIME: |
1633 | env->steal_time_msr = msrs[i].data; | |
1634 | break; | |
0d894367 PB |
1635 | case MSR_CORE_PERF_FIXED_CTR_CTRL: |
1636 | env->msr_fixed_ctr_ctrl = msrs[i].data; | |
1637 | break; | |
1638 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1639 | env->msr_global_ctrl = msrs[i].data; | |
1640 | break; | |
1641 | case MSR_CORE_PERF_GLOBAL_STATUS: | |
1642 | env->msr_global_status = msrs[i].data; | |
1643 | break; | |
1644 | case MSR_CORE_PERF_GLOBAL_OVF_CTRL: | |
1645 | env->msr_global_ovf_ctrl = msrs[i].data; | |
1646 | break; | |
1647 | case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: | |
1648 | env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; | |
1649 | break; | |
1650 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: | |
1651 | env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; | |
1652 | break; | |
1653 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: | |
1654 | env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; | |
1655 | break; | |
1c90ef26 VR |
1656 | case HV_X64_MSR_HYPERCALL: |
1657 | env->msr_hv_hypercall = msrs[i].data; | |
1658 | break; | |
1659 | case HV_X64_MSR_GUEST_OS_ID: | |
1660 | env->msr_hv_guest_os_id = msrs[i].data; | |
1661 | break; | |
5ef68987 VR |
1662 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
1663 | env->msr_hv_vapic = msrs[i].data; | |
1664 | break; | |
48a5f3bc VR |
1665 | case HV_X64_MSR_REFERENCE_TSC: |
1666 | env->msr_hv_tsc = msrs[i].data; | |
1667 | break; | |
05330448 AL |
1668 | } |
1669 | } | |
1670 | ||
1671 | return 0; | |
1672 | } | |
1673 | ||
1bc22652 | 1674 | static int kvm_put_mp_state(X86CPU *cpu) |
9bdbe550 | 1675 | { |
1bc22652 | 1676 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; |
9bdbe550 | 1677 | |
1bc22652 | 1678 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); |
9bdbe550 HB |
1679 | } |
1680 | ||
23d02d9b | 1681 | static int kvm_get_mp_state(X86CPU *cpu) |
9bdbe550 | 1682 | { |
259186a7 | 1683 | CPUState *cs = CPU(cpu); |
23d02d9b | 1684 | CPUX86State *env = &cpu->env; |
9bdbe550 HB |
1685 | struct kvm_mp_state mp_state; |
1686 | int ret; | |
1687 | ||
259186a7 | 1688 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); |
9bdbe550 HB |
1689 | if (ret < 0) { |
1690 | return ret; | |
1691 | } | |
1692 | env->mp_state = mp_state.mp_state; | |
c14750e8 | 1693 | if (kvm_irqchip_in_kernel()) { |
259186a7 | 1694 | cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
c14750e8 | 1695 | } |
9bdbe550 HB |
1696 | return 0; |
1697 | } | |
1698 | ||
1bc22652 | 1699 | static int kvm_get_apic(X86CPU *cpu) |
680c1c6f | 1700 | { |
02e51483 | 1701 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
1702 | struct kvm_lapic_state kapic; |
1703 | int ret; | |
1704 | ||
3d4b2649 | 1705 | if (apic && kvm_irqchip_in_kernel()) { |
1bc22652 | 1706 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); |
680c1c6f JK |
1707 | if (ret < 0) { |
1708 | return ret; | |
1709 | } | |
1710 | ||
1711 | kvm_get_apic_state(apic, &kapic); | |
1712 | } | |
1713 | return 0; | |
1714 | } | |
1715 | ||
1bc22652 | 1716 | static int kvm_put_apic(X86CPU *cpu) |
680c1c6f | 1717 | { |
02e51483 | 1718 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
1719 | struct kvm_lapic_state kapic; |
1720 | ||
3d4b2649 | 1721 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
1722 | kvm_put_apic_state(apic, &kapic); |
1723 | ||
1bc22652 | 1724 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic); |
680c1c6f JK |
1725 | } |
1726 | return 0; | |
1727 | } | |
1728 | ||
1bc22652 | 1729 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) |
a0fb002c | 1730 | { |
1bc22652 | 1731 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1732 | struct kvm_vcpu_events events; |
1733 | ||
1734 | if (!kvm_has_vcpu_events()) { | |
1735 | return 0; | |
1736 | } | |
1737 | ||
31827373 JK |
1738 | events.exception.injected = (env->exception_injected >= 0); |
1739 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
1740 | events.exception.has_error_code = env->has_error_code; |
1741 | events.exception.error_code = env->error_code; | |
7e680753 | 1742 | events.exception.pad = 0; |
a0fb002c JK |
1743 | |
1744 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
1745 | events.interrupt.nr = env->interrupt_injected; | |
1746 | events.interrupt.soft = env->soft_interrupt; | |
1747 | ||
1748 | events.nmi.injected = env->nmi_injected; | |
1749 | events.nmi.pending = env->nmi_pending; | |
1750 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
7e680753 | 1751 | events.nmi.pad = 0; |
a0fb002c JK |
1752 | |
1753 | events.sipi_vector = env->sipi_vector; | |
1754 | ||
ea643051 JK |
1755 | events.flags = 0; |
1756 | if (level >= KVM_PUT_RESET_STATE) { | |
1757 | events.flags |= | |
1758 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
1759 | } | |
aee028b9 | 1760 | |
1bc22652 | 1761 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
1762 | } |
1763 | ||
1bc22652 | 1764 | static int kvm_get_vcpu_events(X86CPU *cpu) |
a0fb002c | 1765 | { |
1bc22652 | 1766 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
1767 | struct kvm_vcpu_events events; |
1768 | int ret; | |
1769 | ||
1770 | if (!kvm_has_vcpu_events()) { | |
1771 | return 0; | |
1772 | } | |
1773 | ||
1bc22652 | 1774 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); |
a0fb002c JK |
1775 | if (ret < 0) { |
1776 | return ret; | |
1777 | } | |
31827373 | 1778 | env->exception_injected = |
a0fb002c JK |
1779 | events.exception.injected ? events.exception.nr : -1; |
1780 | env->has_error_code = events.exception.has_error_code; | |
1781 | env->error_code = events.exception.error_code; | |
1782 | ||
1783 | env->interrupt_injected = | |
1784 | events.interrupt.injected ? events.interrupt.nr : -1; | |
1785 | env->soft_interrupt = events.interrupt.soft; | |
1786 | ||
1787 | env->nmi_injected = events.nmi.injected; | |
1788 | env->nmi_pending = events.nmi.pending; | |
1789 | if (events.nmi.masked) { | |
1790 | env->hflags2 |= HF2_NMI_MASK; | |
1791 | } else { | |
1792 | env->hflags2 &= ~HF2_NMI_MASK; | |
1793 | } | |
1794 | ||
1795 | env->sipi_vector = events.sipi_vector; | |
a0fb002c JK |
1796 | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1bc22652 | 1800 | static int kvm_guest_debug_workarounds(X86CPU *cpu) |
b0b1d690 | 1801 | { |
ed2803da | 1802 | CPUState *cs = CPU(cpu); |
1bc22652 | 1803 | CPUX86State *env = &cpu->env; |
b0b1d690 | 1804 | int ret = 0; |
b0b1d690 JK |
1805 | unsigned long reinject_trap = 0; |
1806 | ||
1807 | if (!kvm_has_vcpu_events()) { | |
1808 | if (env->exception_injected == 1) { | |
1809 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
1810 | } else if (env->exception_injected == 3) { | |
1811 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
1812 | } | |
1813 | env->exception_injected = -1; | |
1814 | } | |
1815 | ||
1816 | /* | |
1817 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
1818 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
1819 | * by updating the debug state once again if single-stepping is on. | |
1820 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
1821 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
1822 | * reinject them via SET_GUEST_DEBUG. | |
1823 | */ | |
1824 | if (reinject_trap || | |
ed2803da | 1825 | (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { |
38e478ec | 1826 | ret = kvm_update_guest_debug(cs, reinject_trap); |
b0b1d690 | 1827 | } |
b0b1d690 JK |
1828 | return ret; |
1829 | } | |
1830 | ||
1bc22652 | 1831 | static int kvm_put_debugregs(X86CPU *cpu) |
ff44f1a3 | 1832 | { |
1bc22652 | 1833 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1834 | struct kvm_debugregs dbgregs; |
1835 | int i; | |
1836 | ||
1837 | if (!kvm_has_debugregs()) { | |
1838 | return 0; | |
1839 | } | |
1840 | ||
1841 | for (i = 0; i < 4; i++) { | |
1842 | dbgregs.db[i] = env->dr[i]; | |
1843 | } | |
1844 | dbgregs.dr6 = env->dr[6]; | |
1845 | dbgregs.dr7 = env->dr[7]; | |
1846 | dbgregs.flags = 0; | |
1847 | ||
1bc22652 | 1848 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); |
ff44f1a3 JK |
1849 | } |
1850 | ||
1bc22652 | 1851 | static int kvm_get_debugregs(X86CPU *cpu) |
ff44f1a3 | 1852 | { |
1bc22652 | 1853 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
1854 | struct kvm_debugregs dbgregs; |
1855 | int i, ret; | |
1856 | ||
1857 | if (!kvm_has_debugregs()) { | |
1858 | return 0; | |
1859 | } | |
1860 | ||
1bc22652 | 1861 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); |
ff44f1a3 | 1862 | if (ret < 0) { |
b9bec74b | 1863 | return ret; |
ff44f1a3 JK |
1864 | } |
1865 | for (i = 0; i < 4; i++) { | |
1866 | env->dr[i] = dbgregs.db[i]; | |
1867 | } | |
1868 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
1869 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
1870 | |
1871 | return 0; | |
1872 | } | |
1873 | ||
20d695a9 | 1874 | int kvm_arch_put_registers(CPUState *cpu, int level) |
05330448 | 1875 | { |
20d695a9 | 1876 | X86CPU *x86_cpu = X86_CPU(cpu); |
05330448 AL |
1877 | int ret; |
1878 | ||
2fa45344 | 1879 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); |
dbaa07c4 | 1880 | |
6bdf863d JK |
1881 | if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) { |
1882 | ret = kvm_put_msr_feature_control(x86_cpu); | |
1883 | if (ret < 0) { | |
1884 | return ret; | |
1885 | } | |
1886 | } | |
1887 | ||
1bc22652 | 1888 | ret = kvm_getput_regs(x86_cpu, 1); |
b9bec74b | 1889 | if (ret < 0) { |
05330448 | 1890 | return ret; |
b9bec74b | 1891 | } |
1bc22652 | 1892 | ret = kvm_put_xsave(x86_cpu); |
b9bec74b | 1893 | if (ret < 0) { |
f1665b21 | 1894 | return ret; |
b9bec74b | 1895 | } |
1bc22652 | 1896 | ret = kvm_put_xcrs(x86_cpu); |
b9bec74b | 1897 | if (ret < 0) { |
05330448 | 1898 | return ret; |
b9bec74b | 1899 | } |
1bc22652 | 1900 | ret = kvm_put_sregs(x86_cpu); |
b9bec74b | 1901 | if (ret < 0) { |
05330448 | 1902 | return ret; |
b9bec74b | 1903 | } |
ab443475 | 1904 | /* must be before kvm_put_msrs */ |
1bc22652 | 1905 | ret = kvm_inject_mce_oldstyle(x86_cpu); |
ab443475 JK |
1906 | if (ret < 0) { |
1907 | return ret; | |
1908 | } | |
1bc22652 | 1909 | ret = kvm_put_msrs(x86_cpu, level); |
b9bec74b | 1910 | if (ret < 0) { |
05330448 | 1911 | return ret; |
b9bec74b | 1912 | } |
ea643051 | 1913 | if (level >= KVM_PUT_RESET_STATE) { |
1bc22652 | 1914 | ret = kvm_put_mp_state(x86_cpu); |
b9bec74b | 1915 | if (ret < 0) { |
ea643051 | 1916 | return ret; |
b9bec74b | 1917 | } |
1bc22652 | 1918 | ret = kvm_put_apic(x86_cpu); |
680c1c6f JK |
1919 | if (ret < 0) { |
1920 | return ret; | |
1921 | } | |
ea643051 | 1922 | } |
7477cd38 MT |
1923 | |
1924 | ret = kvm_put_tscdeadline_msr(x86_cpu); | |
1925 | if (ret < 0) { | |
1926 | return ret; | |
1927 | } | |
1928 | ||
1bc22652 | 1929 | ret = kvm_put_vcpu_events(x86_cpu, level); |
b9bec74b | 1930 | if (ret < 0) { |
a0fb002c | 1931 | return ret; |
b9bec74b | 1932 | } |
1bc22652 | 1933 | ret = kvm_put_debugregs(x86_cpu); |
b9bec74b | 1934 | if (ret < 0) { |
b0b1d690 | 1935 | return ret; |
b9bec74b | 1936 | } |
b0b1d690 | 1937 | /* must be last */ |
1bc22652 | 1938 | ret = kvm_guest_debug_workarounds(x86_cpu); |
b9bec74b | 1939 | if (ret < 0) { |
ff44f1a3 | 1940 | return ret; |
b9bec74b | 1941 | } |
05330448 AL |
1942 | return 0; |
1943 | } | |
1944 | ||
20d695a9 | 1945 | int kvm_arch_get_registers(CPUState *cs) |
05330448 | 1946 | { |
20d695a9 | 1947 | X86CPU *cpu = X86_CPU(cs); |
05330448 AL |
1948 | int ret; |
1949 | ||
20d695a9 | 1950 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); |
dbaa07c4 | 1951 | |
1bc22652 | 1952 | ret = kvm_getput_regs(cpu, 0); |
b9bec74b | 1953 | if (ret < 0) { |
05330448 | 1954 | return ret; |
b9bec74b | 1955 | } |
1bc22652 | 1956 | ret = kvm_get_xsave(cpu); |
b9bec74b | 1957 | if (ret < 0) { |
f1665b21 | 1958 | return ret; |
b9bec74b | 1959 | } |
1bc22652 | 1960 | ret = kvm_get_xcrs(cpu); |
b9bec74b | 1961 | if (ret < 0) { |
05330448 | 1962 | return ret; |
b9bec74b | 1963 | } |
1bc22652 | 1964 | ret = kvm_get_sregs(cpu); |
b9bec74b | 1965 | if (ret < 0) { |
05330448 | 1966 | return ret; |
b9bec74b | 1967 | } |
1bc22652 | 1968 | ret = kvm_get_msrs(cpu); |
b9bec74b | 1969 | if (ret < 0) { |
05330448 | 1970 | return ret; |
b9bec74b | 1971 | } |
23d02d9b | 1972 | ret = kvm_get_mp_state(cpu); |
b9bec74b | 1973 | if (ret < 0) { |
5a2e3c2e | 1974 | return ret; |
b9bec74b | 1975 | } |
1bc22652 | 1976 | ret = kvm_get_apic(cpu); |
680c1c6f JK |
1977 | if (ret < 0) { |
1978 | return ret; | |
1979 | } | |
1bc22652 | 1980 | ret = kvm_get_vcpu_events(cpu); |
b9bec74b | 1981 | if (ret < 0) { |
a0fb002c | 1982 | return ret; |
b9bec74b | 1983 | } |
1bc22652 | 1984 | ret = kvm_get_debugregs(cpu); |
b9bec74b | 1985 | if (ret < 0) { |
ff44f1a3 | 1986 | return ret; |
b9bec74b | 1987 | } |
05330448 AL |
1988 | return 0; |
1989 | } | |
1990 | ||
20d695a9 | 1991 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 1992 | { |
20d695a9 AF |
1993 | X86CPU *x86_cpu = X86_CPU(cpu); |
1994 | CPUX86State *env = &x86_cpu->env; | |
ce377af3 JK |
1995 | int ret; |
1996 | ||
276ce815 | 1997 | /* Inject NMI */ |
259186a7 AF |
1998 | if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { |
1999 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
276ce815 | 2000 | DPRINTF("injected NMI\n"); |
1bc22652 | 2001 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); |
ce377af3 JK |
2002 | if (ret < 0) { |
2003 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
2004 | strerror(-ret)); | |
2005 | } | |
276ce815 LJ |
2006 | } |
2007 | ||
db1669bc | 2008 | if (!kvm_irqchip_in_kernel()) { |
d362e757 JK |
2009 | /* Force the VCPU out of its inner loop to process any INIT requests |
2010 | * or pending TPR access reports. */ | |
259186a7 | 2011 | if (cpu->interrupt_request & |
d362e757 | 2012 | (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { |
fcd7d003 | 2013 | cpu->exit_request = 1; |
05330448 | 2014 | } |
05330448 | 2015 | |
db1669bc JK |
2016 | /* Try to inject an interrupt if the guest can accept it */ |
2017 | if (run->ready_for_interrupt_injection && | |
259186a7 | 2018 | (cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
db1669bc JK |
2019 | (env->eflags & IF_MASK)) { |
2020 | int irq; | |
2021 | ||
259186a7 | 2022 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; |
db1669bc JK |
2023 | irq = cpu_get_pic_interrupt(env); |
2024 | if (irq >= 0) { | |
2025 | struct kvm_interrupt intr; | |
2026 | ||
2027 | intr.irq = irq; | |
db1669bc | 2028 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 2029 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); |
ce377af3 JK |
2030 | if (ret < 0) { |
2031 | fprintf(stderr, | |
2032 | "KVM: injection failed, interrupt lost (%s)\n", | |
2033 | strerror(-ret)); | |
2034 | } | |
db1669bc JK |
2035 | } |
2036 | } | |
05330448 | 2037 | |
db1669bc JK |
2038 | /* If we have an interrupt but the guest is not ready to receive an |
2039 | * interrupt, request an interrupt window exit. This will | |
2040 | * cause a return to userspace as soon as the guest is ready to | |
2041 | * receive interrupts. */ | |
259186a7 | 2042 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { |
db1669bc JK |
2043 | run->request_interrupt_window = 1; |
2044 | } else { | |
2045 | run->request_interrupt_window = 0; | |
2046 | } | |
2047 | ||
2048 | DPRINTF("setting tpr\n"); | |
02e51483 | 2049 | run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); |
db1669bc | 2050 | } |
05330448 AL |
2051 | } |
2052 | ||
20d695a9 | 2053 | void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 2054 | { |
20d695a9 AF |
2055 | X86CPU *x86_cpu = X86_CPU(cpu); |
2056 | CPUX86State *env = &x86_cpu->env; | |
2057 | ||
b9bec74b | 2058 | if (run->if_flag) { |
05330448 | 2059 | env->eflags |= IF_MASK; |
b9bec74b | 2060 | } else { |
05330448 | 2061 | env->eflags &= ~IF_MASK; |
b9bec74b | 2062 | } |
02e51483 CF |
2063 | cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); |
2064 | cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); | |
05330448 AL |
2065 | } |
2066 | ||
20d695a9 | 2067 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 2068 | { |
20d695a9 AF |
2069 | X86CPU *cpu = X86_CPU(cs); |
2070 | CPUX86State *env = &cpu->env; | |
232fc23b | 2071 | |
259186a7 | 2072 | if (cs->interrupt_request & CPU_INTERRUPT_MCE) { |
ab443475 JK |
2073 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ |
2074 | assert(env->mcg_cap); | |
2075 | ||
259186a7 | 2076 | cs->interrupt_request &= ~CPU_INTERRUPT_MCE; |
ab443475 | 2077 | |
dd1750d7 | 2078 | kvm_cpu_synchronize_state(cs); |
ab443475 JK |
2079 | |
2080 | if (env->exception_injected == EXCP08_DBLE) { | |
2081 | /* this means triple fault */ | |
2082 | qemu_system_reset_request(); | |
fcd7d003 | 2083 | cs->exit_request = 1; |
ab443475 JK |
2084 | return 0; |
2085 | } | |
2086 | env->exception_injected = EXCP12_MCHK; | |
2087 | env->has_error_code = 0; | |
2088 | ||
259186a7 | 2089 | cs->halted = 0; |
ab443475 JK |
2090 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { |
2091 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
2092 | } | |
2093 | } | |
2094 | ||
db1669bc JK |
2095 | if (kvm_irqchip_in_kernel()) { |
2096 | return 0; | |
2097 | } | |
2098 | ||
259186a7 AF |
2099 | if (cs->interrupt_request & CPU_INTERRUPT_POLL) { |
2100 | cs->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
02e51483 | 2101 | apic_poll_irq(cpu->apic_state); |
5d62c43a | 2102 | } |
259186a7 | 2103 | if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
4601f7b0 | 2104 | (env->eflags & IF_MASK)) || |
259186a7 AF |
2105 | (cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
2106 | cs->halted = 0; | |
6792a57b | 2107 | } |
259186a7 | 2108 | if (cs->interrupt_request & CPU_INTERRUPT_INIT) { |
dd1750d7 | 2109 | kvm_cpu_synchronize_state(cs); |
232fc23b | 2110 | do_cpu_init(cpu); |
0af691d7 | 2111 | } |
259186a7 | 2112 | if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { |
dd1750d7 | 2113 | kvm_cpu_synchronize_state(cs); |
232fc23b | 2114 | do_cpu_sipi(cpu); |
0af691d7 | 2115 | } |
259186a7 AF |
2116 | if (cs->interrupt_request & CPU_INTERRUPT_TPR) { |
2117 | cs->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
dd1750d7 | 2118 | kvm_cpu_synchronize_state(cs); |
02e51483 | 2119 | apic_handle_tpr_access_report(cpu->apic_state, env->eip, |
d362e757 JK |
2120 | env->tpr_access_type); |
2121 | } | |
0af691d7 | 2122 | |
259186a7 | 2123 | return cs->halted; |
0af691d7 MT |
2124 | } |
2125 | ||
839b5630 | 2126 | static int kvm_handle_halt(X86CPU *cpu) |
05330448 | 2127 | { |
259186a7 | 2128 | CPUState *cs = CPU(cpu); |
839b5630 AF |
2129 | CPUX86State *env = &cpu->env; |
2130 | ||
259186a7 | 2131 | if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
05330448 | 2132 | (env->eflags & IF_MASK)) && |
259186a7 AF |
2133 | !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
2134 | cs->halted = 1; | |
bb4ea393 | 2135 | return EXCP_HLT; |
05330448 AL |
2136 | } |
2137 | ||
bb4ea393 | 2138 | return 0; |
05330448 AL |
2139 | } |
2140 | ||
f7575c96 | 2141 | static int kvm_handle_tpr_access(X86CPU *cpu) |
d362e757 | 2142 | { |
f7575c96 AF |
2143 | CPUState *cs = CPU(cpu); |
2144 | struct kvm_run *run = cs->kvm_run; | |
d362e757 | 2145 | |
02e51483 | 2146 | apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, |
d362e757 JK |
2147 | run->tpr_access.is_write ? TPR_ACCESS_WRITE |
2148 | : TPR_ACCESS_READ); | |
2149 | return 1; | |
2150 | } | |
2151 | ||
f17ec444 | 2152 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 2153 | { |
38972938 | 2154 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 2155 | |
f17ec444 AF |
2156 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
2157 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
e22a25c9 | 2158 | return -EINVAL; |
b9bec74b | 2159 | } |
e22a25c9 AL |
2160 | return 0; |
2161 | } | |
2162 | ||
f17ec444 | 2163 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 AL |
2164 | { |
2165 | uint8_t int3; | |
2166 | ||
f17ec444 AF |
2167 | if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
2168 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
e22a25c9 | 2169 | return -EINVAL; |
b9bec74b | 2170 | } |
e22a25c9 AL |
2171 | return 0; |
2172 | } | |
2173 | ||
2174 | static struct { | |
2175 | target_ulong addr; | |
2176 | int len; | |
2177 | int type; | |
2178 | } hw_breakpoint[4]; | |
2179 | ||
2180 | static int nb_hw_breakpoint; | |
2181 | ||
2182 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
2183 | { | |
2184 | int n; | |
2185 | ||
b9bec74b | 2186 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 2187 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 2188 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 2189 | return n; |
b9bec74b JK |
2190 | } |
2191 | } | |
e22a25c9 AL |
2192 | return -1; |
2193 | } | |
2194 | ||
2195 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
2196 | target_ulong len, int type) | |
2197 | { | |
2198 | switch (type) { | |
2199 | case GDB_BREAKPOINT_HW: | |
2200 | len = 1; | |
2201 | break; | |
2202 | case GDB_WATCHPOINT_WRITE: | |
2203 | case GDB_WATCHPOINT_ACCESS: | |
2204 | switch (len) { | |
2205 | case 1: | |
2206 | break; | |
2207 | case 2: | |
2208 | case 4: | |
2209 | case 8: | |
b9bec74b | 2210 | if (addr & (len - 1)) { |
e22a25c9 | 2211 | return -EINVAL; |
b9bec74b | 2212 | } |
e22a25c9 AL |
2213 | break; |
2214 | default: | |
2215 | return -EINVAL; | |
2216 | } | |
2217 | break; | |
2218 | default: | |
2219 | return -ENOSYS; | |
2220 | } | |
2221 | ||
b9bec74b | 2222 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 2223 | return -ENOBUFS; |
b9bec74b JK |
2224 | } |
2225 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 2226 | return -EEXIST; |
b9bec74b | 2227 | } |
e22a25c9 AL |
2228 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
2229 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
2230 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
2231 | nb_hw_breakpoint++; | |
2232 | ||
2233 | return 0; | |
2234 | } | |
2235 | ||
2236 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
2237 | target_ulong len, int type) | |
2238 | { | |
2239 | int n; | |
2240 | ||
2241 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 2242 | if (n < 0) { |
e22a25c9 | 2243 | return -ENOENT; |
b9bec74b | 2244 | } |
e22a25c9 AL |
2245 | nb_hw_breakpoint--; |
2246 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
2251 | void kvm_arch_remove_all_hw_breakpoints(void) | |
2252 | { | |
2253 | nb_hw_breakpoint = 0; | |
2254 | } | |
2255 | ||
2256 | static CPUWatchpoint hw_watchpoint; | |
2257 | ||
a60f24b5 | 2258 | static int kvm_handle_debug(X86CPU *cpu, |
48405526 | 2259 | struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 2260 | { |
ed2803da | 2261 | CPUState *cs = CPU(cpu); |
a60f24b5 | 2262 | CPUX86State *env = &cpu->env; |
f2574737 | 2263 | int ret = 0; |
e22a25c9 AL |
2264 | int n; |
2265 | ||
2266 | if (arch_info->exception == 1) { | |
2267 | if (arch_info->dr6 & (1 << 14)) { | |
ed2803da | 2268 | if (cs->singlestep_enabled) { |
f2574737 | 2269 | ret = EXCP_DEBUG; |
b9bec74b | 2270 | } |
e22a25c9 | 2271 | } else { |
b9bec74b JK |
2272 | for (n = 0; n < 4; n++) { |
2273 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
2274 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
2275 | case 0x0: | |
f2574737 | 2276 | ret = EXCP_DEBUG; |
e22a25c9 AL |
2277 | break; |
2278 | case 0x1: | |
f2574737 | 2279 | ret = EXCP_DEBUG; |
ff4700b0 | 2280 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2281 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2282 | hw_watchpoint.flags = BP_MEM_WRITE; | |
2283 | break; | |
2284 | case 0x3: | |
f2574737 | 2285 | ret = EXCP_DEBUG; |
ff4700b0 | 2286 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2287 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2288 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
2289 | break; | |
2290 | } | |
b9bec74b JK |
2291 | } |
2292 | } | |
e22a25c9 | 2293 | } |
ff4700b0 | 2294 | } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { |
f2574737 | 2295 | ret = EXCP_DEBUG; |
b9bec74b | 2296 | } |
f2574737 | 2297 | if (ret == 0) { |
ff4700b0 | 2298 | cpu_synchronize_state(cs); |
48405526 | 2299 | assert(env->exception_injected == -1); |
b0b1d690 | 2300 | |
f2574737 | 2301 | /* pass to guest */ |
48405526 BS |
2302 | env->exception_injected = arch_info->exception; |
2303 | env->has_error_code = 0; | |
b0b1d690 | 2304 | } |
e22a25c9 | 2305 | |
f2574737 | 2306 | return ret; |
e22a25c9 AL |
2307 | } |
2308 | ||
20d695a9 | 2309 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
2310 | { |
2311 | const uint8_t type_code[] = { | |
2312 | [GDB_BREAKPOINT_HW] = 0x0, | |
2313 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
2314 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
2315 | }; | |
2316 | const uint8_t len_code[] = { | |
2317 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
2318 | }; | |
2319 | int n; | |
2320 | ||
a60f24b5 | 2321 | if (kvm_sw_breakpoints_active(cpu)) { |
e22a25c9 | 2322 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 2323 | } |
e22a25c9 AL |
2324 | if (nb_hw_breakpoint > 0) { |
2325 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
2326 | dbg->arch.debugreg[7] = 0x0600; | |
2327 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
2328 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
2329 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
2330 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 2331 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
2332 | } |
2333 | } | |
2334 | } | |
4513d923 | 2335 | |
2a4dac83 JK |
2336 | static bool host_supports_vmx(void) |
2337 | { | |
2338 | uint32_t ecx, unused; | |
2339 | ||
2340 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
2341 | return ecx & CPUID_EXT_VMX; | |
2342 | } | |
2343 | ||
2344 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
2345 | ||
20d695a9 | 2346 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
2a4dac83 | 2347 | { |
20d695a9 | 2348 | X86CPU *cpu = X86_CPU(cs); |
2a4dac83 JK |
2349 | uint64_t code; |
2350 | int ret; | |
2351 | ||
2352 | switch (run->exit_reason) { | |
2353 | case KVM_EXIT_HLT: | |
2354 | DPRINTF("handle_hlt\n"); | |
839b5630 | 2355 | ret = kvm_handle_halt(cpu); |
2a4dac83 JK |
2356 | break; |
2357 | case KVM_EXIT_SET_TPR: | |
2358 | ret = 0; | |
2359 | break; | |
d362e757 | 2360 | case KVM_EXIT_TPR_ACCESS: |
f7575c96 | 2361 | ret = kvm_handle_tpr_access(cpu); |
d362e757 | 2362 | break; |
2a4dac83 JK |
2363 | case KVM_EXIT_FAIL_ENTRY: |
2364 | code = run->fail_entry.hardware_entry_failure_reason; | |
2365 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
2366 | code); | |
2367 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
2368 | fprintf(stderr, | |
12619721 | 2369 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
2370 | "unrestricted mode\n" |
2371 | "support, the failure can be most likely due to the guest " | |
2372 | "entering an invalid\n" | |
2373 | "state for Intel VT. For example, the guest maybe running " | |
2374 | "in big real mode\n" | |
2375 | "which is not supported on less recent Intel processors." | |
2376 | "\n\n"); | |
2377 | } | |
2378 | ret = -1; | |
2379 | break; | |
2380 | case KVM_EXIT_EXCEPTION: | |
2381 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
2382 | run->ex.exception, run->ex.error_code); | |
2383 | ret = -1; | |
2384 | break; | |
f2574737 JK |
2385 | case KVM_EXIT_DEBUG: |
2386 | DPRINTF("kvm_exit_debug\n"); | |
a60f24b5 | 2387 | ret = kvm_handle_debug(cpu, &run->debug.arch); |
f2574737 | 2388 | break; |
2a4dac83 JK |
2389 | default: |
2390 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
2391 | ret = -1; | |
2392 | break; | |
2393 | } | |
2394 | ||
2395 | return ret; | |
2396 | } | |
2397 | ||
20d695a9 | 2398 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
4513d923 | 2399 | { |
20d695a9 AF |
2400 | X86CPU *cpu = X86_CPU(cs); |
2401 | CPUX86State *env = &cpu->env; | |
2402 | ||
dd1750d7 | 2403 | kvm_cpu_synchronize_state(cs); |
b9bec74b JK |
2404 | return !(env->cr[0] & CR0_PE_MASK) || |
2405 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2406 | } |
84b058d7 JK |
2407 | |
2408 | void kvm_arch_init_irq_routing(KVMState *s) | |
2409 | { | |
2410 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
2411 | /* If kernel can't do irq routing, interrupt source | |
2412 | * override 0->2 cannot be set up as required by HPET. | |
2413 | * So we have to disable it. | |
2414 | */ | |
2415 | no_hpet = 1; | |
2416 | } | |
cc7e0ddf | 2417 | /* We know at this point that we're using the in-kernel |
614e41bc | 2418 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 2419 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf PM |
2420 | */ |
2421 | kvm_irqfds_allowed = true; | |
614e41bc | 2422 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 2423 | kvm_gsi_routing_allowed = true; |
84b058d7 | 2424 | } |
b139bd30 JK |
2425 | |
2426 | /* Classic KVM device assignment interface. Will remain x86 only. */ | |
2427 | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, | |
2428 | uint32_t flags, uint32_t *dev_id) | |
2429 | { | |
2430 | struct kvm_assigned_pci_dev dev_data = { | |
2431 | .segnr = dev_addr->domain, | |
2432 | .busnr = dev_addr->bus, | |
2433 | .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function), | |
2434 | .flags = flags, | |
2435 | }; | |
2436 | int ret; | |
2437 | ||
2438 | dev_data.assigned_dev_id = | |
2439 | (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn; | |
2440 | ||
2441 | ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data); | |
2442 | if (ret < 0) { | |
2443 | return ret; | |
2444 | } | |
2445 | ||
2446 | *dev_id = dev_data.assigned_dev_id; | |
2447 | ||
2448 | return 0; | |
2449 | } | |
2450 | ||
2451 | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id) | |
2452 | { | |
2453 | struct kvm_assigned_pci_dev dev_data = { | |
2454 | .assigned_dev_id = dev_id, | |
2455 | }; | |
2456 | ||
2457 | return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data); | |
2458 | } | |
2459 | ||
2460 | static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id, | |
2461 | uint32_t irq_type, uint32_t guest_irq) | |
2462 | { | |
2463 | struct kvm_assigned_irq assigned_irq = { | |
2464 | .assigned_dev_id = dev_id, | |
2465 | .guest_irq = guest_irq, | |
2466 | .flags = irq_type, | |
2467 | }; | |
2468 | ||
2469 | if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) { | |
2470 | return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq); | |
2471 | } else { | |
2472 | return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq); | |
2473 | } | |
2474 | } | |
2475 | ||
2476 | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi, | |
2477 | uint32_t guest_irq) | |
2478 | { | |
2479 | uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX | | |
2480 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX); | |
2481 | ||
2482 | return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq); | |
2483 | } | |
2484 | ||
2485 | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked) | |
2486 | { | |
2487 | struct kvm_assigned_pci_dev dev_data = { | |
2488 | .assigned_dev_id = dev_id, | |
2489 | .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0, | |
2490 | }; | |
2491 | ||
2492 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data); | |
2493 | } | |
2494 | ||
2495 | static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id, | |
2496 | uint32_t type) | |
2497 | { | |
2498 | struct kvm_assigned_irq assigned_irq = { | |
2499 | .assigned_dev_id = dev_id, | |
2500 | .flags = type, | |
2501 | }; | |
2502 | ||
2503 | return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq); | |
2504 | } | |
2505 | ||
2506 | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi) | |
2507 | { | |
2508 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX | | |
2509 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX)); | |
2510 | } | |
2511 | ||
2512 | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq) | |
2513 | { | |
2514 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI | | |
2515 | KVM_DEV_IRQ_GUEST_MSI, virq); | |
2516 | } | |
2517 | ||
2518 | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id) | |
2519 | { | |
2520 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI | | |
2521 | KVM_DEV_IRQ_HOST_MSI); | |
2522 | } | |
2523 | ||
2524 | bool kvm_device_msix_supported(KVMState *s) | |
2525 | { | |
2526 | /* The kernel lacks a corresponding KVM_CAP, so we probe by calling | |
2527 | * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */ | |
2528 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT; | |
2529 | } | |
2530 | ||
2531 | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id, | |
2532 | uint32_t nr_vectors) | |
2533 | { | |
2534 | struct kvm_assigned_msix_nr msix_nr = { | |
2535 | .assigned_dev_id = dev_id, | |
2536 | .entry_nr = nr_vectors, | |
2537 | }; | |
2538 | ||
2539 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr); | |
2540 | } | |
2541 | ||
2542 | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector, | |
2543 | int virq) | |
2544 | { | |
2545 | struct kvm_assigned_msix_entry msix_entry = { | |
2546 | .assigned_dev_id = dev_id, | |
2547 | .gsi = virq, | |
2548 | .entry = vector, | |
2549 | }; | |
2550 | ||
2551 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry); | |
2552 | } | |
2553 | ||
2554 | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id) | |
2555 | { | |
2556 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX | | |
2557 | KVM_DEV_IRQ_GUEST_MSIX, 0); | |
2558 | } | |
2559 | ||
2560 | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id) | |
2561 | { | |
2562 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX | | |
2563 | KVM_DEV_IRQ_HOST_MSIX); | |
2564 | } |