[qemu.git] / target-i386 / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/pc.h"
#include "hw/isa.h"

#include "exec-all.h"
#include "kvm.h"

static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
{
    qemu_put_be32(f, dt->selector);
    qemu_put_betl(f, dt->base);
    qemu_put_be32(f, dt->limit);
    qemu_put_be32(f, dt->flags);
}

static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
{
    dt->selector = qemu_get_be32(f);
    dt->base = qemu_get_betl(f);
    dt->limit = qemu_get_be32(f);
    dt->flags = qemu_get_be32(f);
}

void cpu_save(QEMUFile *f, void *opaque)
{
    CPUState *env = opaque;
    uint16_t fptag, fpus, fpuc, fpregs_format;
    uint32_t hflags;
    int32_t a20_mask;
    int i;

    cpu_synchronize_state(env, 0);

    for(i = 0; i < CPU_NB_REGS; i++)
        qemu_put_betls(f, &env->regs[i]);
    qemu_put_betls(f, &env->eip);
    qemu_put_betls(f, &env->eflags);
    hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
    qemu_put_be32s(f, &hflags);

    /* FPU */
    fpuc = env->fpuc;
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
    fptag = 0;
    for(i = 0; i < 8; i++) {
        fptag |= ((!env->fptags[i]) << i);
    }

    qemu_put_be16s(f, &fpuc);
    qemu_put_be16s(f, &fpus);
    qemu_put_be16s(f, &fptag);

#ifdef USE_X86LDOUBLE
    fpregs_format = 0;
#else
    fpregs_format = 1;
#endif
    qemu_put_be16s(f, &fpregs_format);

    for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
        {
            uint64_t mant;
            uint16_t exp;
            /* we save the real CPU data (in case of MMX usage only 'mant'
               contains the MMX register */
            cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
            qemu_put_be64(f, mant);
            qemu_put_be16(f, exp);
        }
#else
        /* if we use doubles for float emulation, we save the doubles to
           avoid losing information in case of MMX usage. It can give
           problems if the image is restored on a CPU where long
           doubles are used instead. */
        qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
    }

    for(i = 0; i < 6; i++)
        cpu_put_seg(f, &env->segs[i]);
    cpu_put_seg(f, &env->ldt);
    cpu_put_seg(f, &env->tr);
    cpu_put_seg(f, &env->gdt);
    cpu_put_seg(f, &env->idt);

    qemu_put_be32s(f, &env->sysenter_cs);
    qemu_put_betls(f, &env->sysenter_esp);
    qemu_put_betls(f, &env->sysenter_eip);

    qemu_put_betls(f, &env->cr[0]);
    qemu_put_betls(f, &env->cr[2]);
    qemu_put_betls(f, &env->cr[3]);
    qemu_put_betls(f, &env->cr[4]);

    for(i = 0; i < 8; i++)
        qemu_put_betls(f, &env->dr[i]);

    /* MMU */
    a20_mask = (int32_t) env->a20_mask;
    qemu_put_sbe32s(f, &a20_mask);

    /* XMM */
    qemu_put_be32s(f, &env->mxcsr);
    for(i = 0; i < CPU_NB_REGS; i++) {
        qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
        qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
    }

#ifdef TARGET_X86_64
    qemu_put_be64s(f, &env->efer);
    qemu_put_be64s(f, &env->star);
    qemu_put_be64s(f, &env->lstar);
    qemu_put_be64s(f, &env->cstar);
    qemu_put_be64s(f, &env->fmask);
    qemu_put_be64s(f, &env->kernelgsbase);
#endif
    qemu_put_be32s(f, &env->smbase);

    qemu_put_be64s(f, &env->pat);
    qemu_put_be32s(f, &env->hflags2);
    
    qemu_put_be64s(f, &env->vm_hsave);
    qemu_put_be64s(f, &env->vm_vmcb);
    qemu_put_be64s(f, &env->tsc_offset);
    qemu_put_be64s(f, &env->intercept);
    qemu_put_be16s(f, &env->intercept_cr_read);
    qemu_put_be16s(f, &env->intercept_cr_write);
    qemu_put_be16s(f, &env->intercept_dr_read);
    qemu_put_be16s(f, &env->intercept_dr_write);
    qemu_put_be32s(f, &env->intercept_exceptions);
    qemu_put_8s(f, &env->v_tpr);

    /* MTRRs */
    for(i = 0; i < 11; i++)
        qemu_put_be64s(f, &env->mtrr_fixed[i]);
    qemu_put_be64s(f, &env->mtrr_deftype);
    for(i = 0; i < 8; i++) {
        qemu_put_be64s(f, &env->mtrr_var[i].base);
        qemu_put_be64s(f, &env->mtrr_var[i].mask);
    }

    for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
        qemu_put_be64s(f, &env->interrupt_bitmap[i]);
    }
    qemu_put_be64s(f, &env->tsc);
    qemu_put_be32s(f, &env->mp_state);
}

#ifdef USE_X86LDOUBLE
/* XXX: add that in a FPU generic layer */
union x86_longdouble {
    uint64_t mant;
    uint16_t exp;
};

#define MANTD1(fp)	(fp & ((1LL << 52) - 1))
#define EXPBIAS1 1023
#define EXPD1(fp)	((fp >> 52) & 0x7FF)
#define SIGND1(fp)	((fp >> 32) & 0x80000000)

static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
{
    int e;
    /* mantissa */
    p->mant = (MANTD1(temp) << 11) | (1LL << 63);
    /* exponent + sign */
    e = EXPD1(temp) - EXPBIAS1 + 16383;
    e |= SIGND1(temp) >> 16;
    p->exp = e;
}
#endif

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUState *env = opaque;
    int i, guess_mmx;
    uint32_t hflags;
    uint16_t fpus, fpuc, fptag, fpregs_format;
    int32_t a20_mask;

    if (version_id < 3 || version_id > CPU_SAVE_VERSION)
        return -EINVAL;
    for(i = 0; i < CPU_NB_REGS; i++)
        qemu_get_betls(f, &env->regs[i]);
    qemu_get_betls(f, &env->eip);
    qemu_get_betls(f, &env->eflags);
    qemu_get_be32s(f, &hflags);

    qemu_get_be16s(f, &fpuc);
    qemu_get_be16s(f, &fpus);
    qemu_get_be16s(f, &fptag);
    qemu_get_be16s(f, &fpregs_format);

    /* NOTE: we cannot always restore the FPU state if the image come
       from a host with a different 'USE_X86LDOUBLE' define. We guess
       if we are in an MMX state to restore correctly in that case. */
    guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
    for(i = 0; i < 8; i++) {
        uint64_t mant;
        uint16_t exp;

        switch(fpregs_format) {
        case 0:
            mant = qemu_get_be64(f);
            exp = qemu_get_be16(f);
#ifdef USE_X86LDOUBLE
            env->fpregs[i].d = cpu_set_fp80(mant, exp);
#else
            /* difficult case */
            if (guess_mmx)
                env->fpregs[i].mmx.MMX_Q(0) = mant;
            else
                env->fpregs[i].d = cpu_set_fp80(mant, exp);
#endif
            break;
        case 1:
            mant = qemu_get_be64(f);
#ifdef USE_X86LDOUBLE
            {
                union x86_longdouble *p;
                /* difficult case */
                p = (void *)&env->fpregs[i];
                if (guess_mmx) {
                    p->mant = mant;
                    p->exp = 0xffff;
                } else {
                    fp64_to_fp80(p, mant);
                }
            }
#else
            env->fpregs[i].mmx.MMX_Q(0) = mant;
#endif
            break;
        default:
            return -EINVAL;
        }
    }

    env->fpuc = fpuc;
    /* XXX: restore FPU round state */
    env->fpstt = (fpus >> 11) & 7;
    env->fpus = fpus & ~0x3800;
    fptag ^= 0xff;
    for(i = 0; i < 8; i++) {
        env->fptags[i] = (fptag >> i) & 1;
    }

    for(i = 0; i < 6; i++)
        cpu_get_seg(f, &env->segs[i]);
    cpu_get_seg(f, &env->ldt);
    cpu_get_seg(f, &env->tr);
    cpu_get_seg(f, &env->gdt);
    cpu_get_seg(f, &env->idt);

    qemu_get_be32s(f, &env->sysenter_cs);
    if (version_id >= 7) {
        qemu_get_betls(f, &env->sysenter_esp);
        qemu_get_betls(f, &env->sysenter_eip);
    } else {
        env->sysenter_esp = qemu_get_be32(f);
        env->sysenter_eip = qemu_get_be32(f);
    }

    qemu_get_betls(f, &env->cr[0]);
    qemu_get_betls(f, &env->cr[2]);
    qemu_get_betls(f, &env->cr[3]);
    qemu_get_betls(f, &env->cr[4]);

    for(i = 0; i < 8; i++)
        qemu_get_betls(f, &env->dr[i]);
    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
    for (i = 0; i < 4; i++)
        hw_breakpoint_insert(env, i);

    /* MMU */
    qemu_get_sbe32s(f, &a20_mask);
    env->a20_mask = a20_mask;

    qemu_get_be32s(f, &env->mxcsr);
    for(i = 0; i < CPU_NB_REGS; i++) {
        qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
        qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
    }

#ifdef TARGET_X86_64
    qemu_get_be64s(f, &env->efer);
    qemu_get_be64s(f, &env->star);
    qemu_get_be64s(f, &env->lstar);
    qemu_get_be64s(f, &env->cstar);
    qemu_get_be64s(f, &env->fmask);
    qemu_get_be64s(f, &env->kernelgsbase);
#endif
    if (version_id >= 4) {
        qemu_get_be32s(f, &env->smbase);
    }
    if (version_id >= 5) {
        qemu_get_be64s(f, &env->pat);
        qemu_get_be32s(f, &env->hflags2);
        if (version_id < 6)
            qemu_get_be32s(f, &env->halted);

        qemu_get_be64s(f, &env->vm_hsave);
        qemu_get_be64s(f, &env->vm_vmcb);
        qemu_get_be64s(f, &env->tsc_offset);
        qemu_get_be64s(f, &env->intercept);
        qemu_get_be16s(f, &env->intercept_cr_read);
        qemu_get_be16s(f, &env->intercept_cr_write);
        qemu_get_be16s(f, &env->intercept_dr_read);
        qemu_get_be16s(f, &env->intercept_dr_write);
        qemu_get_be32s(f, &env->intercept_exceptions);
        qemu_get_8s(f, &env->v_tpr);
    }

    if (version_id >= 8) {
        /* MTRRs */
        for(i = 0; i < 11; i++)
            qemu_get_be64s(f, &env->mtrr_fixed[i]);
        qemu_get_be64s(f, &env->mtrr_deftype);
        for(i = 0; i < 8; i++) {
            qemu_get_be64s(f, &env->mtrr_var[i].base);
            qemu_get_be64s(f, &env->mtrr_var[i].mask);
        }
    }
    if (version_id >= 9) {
        for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
            qemu_get_be64s(f, &env->interrupt_bitmap[i]);
        }
        qemu_get_be64s(f, &env->tsc);
        qemu_get_be32s(f, &env->mp_state);
    }

    /* XXX: ensure compatiblity for halted bit ? */
    /* XXX: compute redundant hflags bits */
    env->hflags = hflags;
    tlb_flush(env, 1);
    cpu_synchronize_state(env, 1);
    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3	#include "hw/pc.h"
	4	#include "hw/isa.h"
	5
	6	#include "exec-all.h"
b0a46a33	7	#include "kvm.h"
8dd3dca3	8
8dd3dca3 AJ	9	static void cpu_put_seg(QEMUFile f, SegmentCache dt)
	10	{
	11	qemu_put_be32(f, dt->selector);
	12	qemu_put_betl(f, dt->base);
	13	qemu_put_be32(f, dt->limit);
	14	qemu_put_be32(f, dt->flags);
	15	}
	16
	17	static void cpu_get_seg(QEMUFile f, SegmentCache dt)
	18	{
	19	dt->selector = qemu_get_be32(f);
	20	dt->base = qemu_get_betl(f);
	21	dt->limit = qemu_get_be32(f);
	22	dt->flags = qemu_get_be32(f);
	23	}
	24
	25	void cpu_save(QEMUFile f, void opaque)
	26	{
	27	CPUState *env = opaque;
	28	uint16_t fptag, fpus, fpuc, fpregs_format;
	29	uint32_t hflags;
7caa33f7	30	int32_t a20_mask;
8dd3dca3 AJ	31	int i;
8dd3dca3 AJ	32
b0a46a33 JK	33	cpu_synchronize_state(env, 0);
b0a46a33 JK	34
8dd3dca3 AJ	35	for(i = 0; i < CPU_NB_REGS; i++)
	36	qemu_put_betls(f, &env->regs[i]);
	37	qemu_put_betls(f, &env->eip);
	38	qemu_put_betls(f, &env->eflags);
	39	hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
	40	qemu_put_be32s(f, &hflags);
	41
	42	/* FPU */
	43	fpuc = env->fpuc;
	44	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
	45	fptag = 0;
	46	for(i = 0; i < 8; i++) {
	47	fptag \|= ((!env->fptags[i]) << i);
	48	}
	49
	50	qemu_put_be16s(f, &fpuc);
	51	qemu_put_be16s(f, &fpus);
	52	qemu_put_be16s(f, &fptag);
	53
	54	#ifdef USE_X86LDOUBLE
	55	fpregs_format = 0;
	56	#else
	57	fpregs_format = 1;
	58	#endif
	59	qemu_put_be16s(f, &fpregs_format);
	60
	61	for(i = 0; i < 8; i++) {
	62	#ifdef USE_X86LDOUBLE
	63	{
	64	uint64_t mant;
	65	uint16_t exp;
	66	/* we save the real CPU data (in case of MMX usage only 'mant'
	67	contains the MMX register */
	68	cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
	69	qemu_put_be64(f, mant);
	70	qemu_put_be16(f, exp);
	71	}
	72	#else
	73	/* if we use doubles for float emulation, we save the doubles to
	74	avoid losing information in case of MMX usage. It can give
	75	problems if the image is restored on a CPU where long
	76	doubles are used instead. */
	77	qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
	78	#endif
	79	}
	80
	81	for(i = 0; i < 6; i++)
	82	cpu_put_seg(f, &env->segs[i]);
	83	cpu_put_seg(f, &env->ldt);
	84	cpu_put_seg(f, &env->tr);
	85	cpu_put_seg(f, &env->gdt);
	86	cpu_put_seg(f, &env->idt);
	87
f5049756	88	qemu_put_be32s(f, &env->sysenter_cs);
2436b61a AZ	89	qemu_put_betls(f, &env->sysenter_esp);
2436b61a AZ	90	qemu_put_betls(f, &env->sysenter_eip);
8dd3dca3 AJ	91
	92	qemu_put_betls(f, &env->cr[0]);
	93	qemu_put_betls(f, &env->cr[2]);
	94	qemu_put_betls(f, &env->cr[3]);
	95	qemu_put_betls(f, &env->cr[4]);
	96
	97	for(i = 0; i < 8; i++)
	98	qemu_put_betls(f, &env->dr[i]);
	99
	100	/* MMU */
7caa33f7	101	a20_mask = (int32_t) env->a20_mask;
b6c4f71f	102	qemu_put_sbe32s(f, &a20_mask);
8dd3dca3 AJ	103
	104	/* XMM */
	105	qemu_put_be32s(f, &env->mxcsr);
	106	for(i = 0; i < CPU_NB_REGS; i++) {
	107	qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
	108	qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
	109	}
	110
	111	#ifdef TARGET_X86_64
	112	qemu_put_be64s(f, &env->efer);
	113	qemu_put_be64s(f, &env->star);
	114	qemu_put_be64s(f, &env->lstar);
	115	qemu_put_be64s(f, &env->cstar);
	116	qemu_put_be64s(f, &env->fmask);
	117	qemu_put_be64s(f, &env->kernelgsbase);
	118	#endif
	119	qemu_put_be32s(f, &env->smbase);
5cc1d1e6 FB	120
	121	qemu_put_be64s(f, &env->pat);
	122	qemu_put_be32s(f, &env->hflags2);
5cc1d1e6 FB	123
	124	qemu_put_be64s(f, &env->vm_hsave);
	125	qemu_put_be64s(f, &env->vm_vmcb);
	126	qemu_put_be64s(f, &env->tsc_offset);
	127	qemu_put_be64s(f, &env->intercept);
	128	qemu_put_be16s(f, &env->intercept_cr_read);
	129	qemu_put_be16s(f, &env->intercept_cr_write);
	130	qemu_put_be16s(f, &env->intercept_dr_read);
	131	qemu_put_be16s(f, &env->intercept_dr_write);
	132	qemu_put_be32s(f, &env->intercept_exceptions);
	133	qemu_put_8s(f, &env->v_tpr);
dd5e3b17 AL	134
	135	/* MTRRs */
	136	for(i = 0; i < 11; i++)
	137	qemu_put_be64s(f, &env->mtrr_fixed[i]);
	138	qemu_put_be64s(f, &env->mtrr_deftype);
	139	for(i = 0; i < 8; i++) {
	140	qemu_put_be64s(f, &env->mtrr_var[i].base);
	141	qemu_put_be64s(f, &env->mtrr_var[i].mask);
	142	}
f8d926e9 JK	143
	144	for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
	145	qemu_put_be64s(f, &env->interrupt_bitmap[i]);
	146	}
	147	qemu_put_be64s(f, &env->tsc);
	148	qemu_put_be32s(f, &env->mp_state);
8dd3dca3 AJ	149	}
	150
	151	#ifdef USE_X86LDOUBLE
	152	/* XXX: add that in a FPU generic layer */
	153	union x86_longdouble {
	154	uint64_t mant;
	155	uint16_t exp;
	156	};
	157
	158	#define MANTD1(fp) (fp & ((1LL << 52) - 1))
	159	#define EXPBIAS1 1023
	160	#define EXPD1(fp) ((fp >> 52) & 0x7FF)
	161	#define SIGND1(fp) ((fp >> 32) & 0x80000000)
	162
	163	static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
	164	{
	165	int e;
	166	/* mantissa */
	167	p->mant = (MANTD1(temp) << 11) \| (1LL << 63);
	168	/* exponent + sign */
	169	e = EXPD1(temp) - EXPBIAS1 + 16383;
	170	e \|= SIGND1(temp) >> 16;
	171	p->exp = e;
	172	}
	173	#endif
	174
	175	int cpu_load(QEMUFile f, void opaque, int version_id)
	176	{
	177	CPUState *env = opaque;
	178	int i, guess_mmx;
	179	uint32_t hflags;
	180	uint16_t fpus, fpuc, fptag, fpregs_format;
7caa33f7	181	int32_t a20_mask;
8dd3dca3	182
f8d926e9	183	if (version_id < 3 \|\| version_id > CPU_SAVE_VERSION)
8dd3dca3 AJ	184	return -EINVAL;
	185	for(i = 0; i < CPU_NB_REGS; i++)
	186	qemu_get_betls(f, &env->regs[i]);
	187	qemu_get_betls(f, &env->eip);
	188	qemu_get_betls(f, &env->eflags);
	189	qemu_get_be32s(f, &hflags);
	190
	191	qemu_get_be16s(f, &fpuc);
	192	qemu_get_be16s(f, &fpus);
	193	qemu_get_be16s(f, &fptag);
	194	qemu_get_be16s(f, &fpregs_format);
	195
	196	/* NOTE: we cannot always restore the FPU state if the image come
	197	from a host with a different 'USE_X86LDOUBLE' define. We guess
	198	if we are in an MMX state to restore correctly in that case. */
	199	guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
	200	for(i = 0; i < 8; i++) {
	201	uint64_t mant;
	202	uint16_t exp;
	203
	204	switch(fpregs_format) {
	205	case 0:
	206	mant = qemu_get_be64(f);
	207	exp = qemu_get_be16(f);
	208	#ifdef USE_X86LDOUBLE
	209	env->fpregs[i].d = cpu_set_fp80(mant, exp);
	210	#else
	211	/* difficult case */
	212	if (guess_mmx)
	213	env->fpregs[i].mmx.MMX_Q(0) = mant;
	214	else
	215	env->fpregs[i].d = cpu_set_fp80(mant, exp);
	216	#endif
	217	break;
	218	case 1:
	219	mant = qemu_get_be64(f);
	220	#ifdef USE_X86LDOUBLE
	221	{
	222	union x86_longdouble *p;
	223	/* difficult case */
	224	p = (void *)&env->fpregs[i];
	225	if (guess_mmx) {
	226	p->mant = mant;
	227	p->exp = 0xffff;
	228	} else {
	229	fp64_to_fp80(p, mant);
	230	}
	231	}
	232	#else
	233	env->fpregs[i].mmx.MMX_Q(0) = mant;
	234	#endif
	235	break;
	236	default:
	237	return -EINVAL;
	238	}
	239	}
	240
	241	env->fpuc = fpuc;
	242	/* XXX: restore FPU round state */
	243	env->fpstt = (fpus >> 11) & 7;
	244	env->fpus = fpus & ~0x3800;
	245	fptag ^= 0xff;
	246	for(i = 0; i < 8; i++) {
	247	env->fptags[i] = (fptag >> i) & 1;
248	}
249
250	for(i = 0; i < 6; i++)
251	cpu_get_seg(f, &env->segs[i]);
252	cpu_get_seg(f, &env->ldt);
253	cpu_get_seg(f, &env->tr);
254	cpu_get_seg(f, &env->gdt);
255	cpu_get_seg(f, &env->idt);
256
257	qemu_get_be32s(f, &env->sysenter_cs);
2436b61a AZ	258	if (version_id >= 7) {
	259	qemu_get_betls(f, &env->sysenter_esp);
	260	qemu_get_betls(f, &env->sysenter_eip);
	261	} else {
e5ceb244 AL	262	env->sysenter_esp = qemu_get_be32(f);
e5ceb244 AL	263	env->sysenter_eip = qemu_get_be32(f);
2436b61a	264	}
8dd3dca3 AJ	265
	266	qemu_get_betls(f, &env->cr[0]);
	267	qemu_get_betls(f, &env->cr[2]);
	268	qemu_get_betls(f, &env->cr[3]);
	269	qemu_get_betls(f, &env->cr[4]);
	270
	271	for(i = 0; i < 8; i++)
	272	qemu_get_betls(f, &env->dr[i]);
01df040b AL	273	cpu_breakpoint_remove_all(env, BP_CPU);
	274	cpu_watchpoint_remove_all(env, BP_CPU);
	275	for (i = 0; i < 4; i++)
	276	hw_breakpoint_insert(env, i);
8dd3dca3 AJ	277
8dd3dca3 AJ	278	/* MMU */
b6c4f71f	279	qemu_get_sbe32s(f, &a20_mask);
7caa33f7	280	env->a20_mask = a20_mask;
8dd3dca3 AJ	281
	282	qemu_get_be32s(f, &env->mxcsr);
	283	for(i = 0; i < CPU_NB_REGS; i++) {
	284	qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
	285	qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
	286	}
	287
	288	#ifdef TARGET_X86_64
	289	qemu_get_be64s(f, &env->efer);
	290	qemu_get_be64s(f, &env->star);
	291	qemu_get_be64s(f, &env->lstar);
	292	qemu_get_be64s(f, &env->cstar);
	293	qemu_get_be64s(f, &env->fmask);
	294	qemu_get_be64s(f, &env->kernelgsbase);
	295	#endif
5cc1d1e6	296	if (version_id >= 4) {
8dd3dca3	297	qemu_get_be32s(f, &env->smbase);
5cc1d1e6 FB	298	}
	299	if (version_id >= 5) {
	300	qemu_get_be64s(f, &env->pat);
	301	qemu_get_be32s(f, &env->hflags2);
9656f324 PB	302	if (version_id < 6)
9656f324 PB	303	qemu_get_be32s(f, &env->halted);
5cc1d1e6 FB	304
	305	qemu_get_be64s(f, &env->vm_hsave);
	306	qemu_get_be64s(f, &env->vm_vmcb);
	307	qemu_get_be64s(f, &env->tsc_offset);
	308	qemu_get_be64s(f, &env->intercept);
	309	qemu_get_be16s(f, &env->intercept_cr_read);
	310	qemu_get_be16s(f, &env->intercept_cr_write);
	311	qemu_get_be16s(f, &env->intercept_dr_read);
	312	qemu_get_be16s(f, &env->intercept_dr_write);
	313	qemu_get_be32s(f, &env->intercept_exceptions);
	314	qemu_get_8s(f, &env->v_tpr);
	315	}
dd5e3b17 AL	316
	317	if (version_id >= 8) {
	318	/* MTRRs */
	319	for(i = 0; i < 11; i++)
	320	qemu_get_be64s(f, &env->mtrr_fixed[i]);
	321	qemu_get_be64s(f, &env->mtrr_deftype);
	322	for(i = 0; i < 8; i++) {
	323	qemu_get_be64s(f, &env->mtrr_var[i].base);
	324	qemu_get_be64s(f, &env->mtrr_var[i].mask);
	325	}
	326	}
f8d926e9 JK	327	if (version_id >= 9) {
	328	for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
	329	qemu_get_be64s(f, &env->interrupt_bitmap[i]);
	330	}
	331	qemu_get_be64s(f, &env->tsc);
	332	qemu_get_be32s(f, &env->mp_state);
	333	}
dd5e3b17	334
5cc1d1e6 FB	335	/* XXX: ensure compatiblity for halted bit ? */
5cc1d1e6 FB	336	/* XXX: compute redundant hflags bits */
8dd3dca3 AJ	337	env->hflags = hflags;
8dd3dca3 AJ	338	tlb_flush(env, 1);
b0a46a33	339	cpu_synchronize_state(env, 1);
8dd3dca3 AJ	340	return 0;
8dd3dca3 AJ	341	}