[qemu.git] / target-i386 / misc_helper.c

/*
 *  x86 misc helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "ioport.h"
#include "helper.h"

/* check if Port I/O is allowed in TSS */
static inline void check_io(CPUX86State *env, int addr, int size)
{
    int io_offset, val, mask;

    /* TSS must be a valid 32 bit one */
    if (!(env->tr.flags & DESC_P_MASK) ||
        ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
        env->tr.limit < 103) {
        goto fail;
    }
    io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
    io_offset += (addr >> 3);
    /* Note: the check needs two bytes */
    if ((io_offset + 1) > env->tr.limit) {
        goto fail;
    }
    val = cpu_lduw_kernel(env, env->tr.base + io_offset);
    val >>= (addr & 7);
    mask = (1 << size) - 1;
    /* all bits must be zero to allow the I/O */
    if ((val & mask) != 0) {
    fail:
        raise_exception_err(env, EXCP0D_GPF, 0);
    }
}

void helper_check_iob(CPUX86State *env, uint32_t t0)
{
    check_io(env, t0, 1);
}

void helper_check_iow(CPUX86State *env, uint32_t t0)
{
    check_io(env, t0, 2);
}

void helper_check_iol(CPUX86State *env, uint32_t t0)
{
    check_io(env, t0, 4);
}

void helper_outb(uint32_t port, uint32_t data)
{
    cpu_outb(port, data & 0xff);
}

target_ulong helper_inb(uint32_t port)
{
    return cpu_inb(port);
}

void helper_outw(uint32_t port, uint32_t data)
{
    cpu_outw(port, data & 0xffff);
}

target_ulong helper_inw(uint32_t port)
{
    return cpu_inw(port);
}

void helper_outl(uint32_t port, uint32_t data)
{
    cpu_outl(port, data);
}

target_ulong helper_inl(uint32_t port)
{
    return cpu_inl(port);
}

void helper_into(CPUX86State *env, int next_eip_addend)
{
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    if (eflags & CC_O) {
        raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
    }
}

void helper_single_step(CPUX86State *env)
{
#ifndef CONFIG_USER_ONLY
    check_hw_breakpoints(env, 1);
    env->dr[6] |= DR6_BS;
#endif
    raise_exception(env, EXCP01_DB);
}

void helper_cpuid(CPUX86State *env)
{
    uint32_t eax, ebx, ecx, edx;

    cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);

    cpu_x86_cpuid(env, (uint32_t)EAX, (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
    EAX = eax;
    EBX = ebx;
    ECX = ecx;
    EDX = edx;
}

#if defined(CONFIG_USER_ONLY)
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    return 0;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
}

void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
}
#else
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    target_ulong val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
    switch (reg) {
    default:
        val = env->cr[reg];
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            val = cpu_get_apic_tpr(env->apic_state);
        } else {
            val = env->v_tpr;
        }
        break;
    }
    return val;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
    switch (reg) {
    case 0:
        cpu_x86_update_cr0(env, t0);
        break;
    case 3:
        cpu_x86_update_cr3(env, t0);
        break;
    case 4:
        cpu_x86_update_cr4(env, t0);
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            cpu_set_apic_tpr(env->apic_state, t0);
        }
        env->v_tpr = t0 & 0x0f;
        break;
    default:
        env->cr[reg] = t0;
        break;
    }
}

void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
    int i;

    if (reg < 4) {
        hw_breakpoint_remove(env, reg);
        env->dr[reg] = t0;
        hw_breakpoint_insert(env, reg);
    } else if (reg == 7) {
        for (i = 0; i < 4; i++) {
            hw_breakpoint_remove(env, i);
        }
        env->dr[7] = t0;
        for (i = 0; i < 4; i++) {
            hw_breakpoint_insert(env, i);
        }
    } else {
        env->dr[reg] = t0;
    }
}
#endif

void helper_lmsw(CPUX86State *env, target_ulong t0)
{
    /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
       if already set to one. */
    t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
    helper_write_crN(env, 0, t0);
}

void helper_invlpg(CPUX86State *env, target_ulong addr)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
    tlb_flush_page(env, addr);
}

void helper_rdtsc(CPUX86State *env)
{
    uint64_t val;

    if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception(env, EXCP0D_GPF);
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);

    val = cpu_get_tsc(env) + env->tsc_offset;
    EAX = (uint32_t)(val);
    EDX = (uint32_t)(val >> 32);
}

void helper_rdtscp(CPUX86State *env)
{
    helper_rdtsc(env);
    ECX = (uint32_t)(env->tsc_aux);
}

void helper_rdpmc(CPUX86State *env)
{
    if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception(env, EXCP0D_GPF);
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);

    /* currently unimplemented */
    qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
    raise_exception_err(env, EXCP06_ILLOP, 0);
}

#if defined(CONFIG_USER_ONLY)
void helper_wrmsr(CPUX86State *env)
{
}

void helper_rdmsr(CPUX86State *env)
{
}
#else
void helper_wrmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);

    val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);

    switch ((uint32_t)ECX) {
    case MSR_IA32_SYSENTER_CS:
        env->sysenter_cs = val & 0xffff;
        break;
    case MSR_IA32_SYSENTER_ESP:
        env->sysenter_esp = val;
        break;
    case MSR_IA32_SYSENTER_EIP:
        env->sysenter_eip = val;
        break;
    case MSR_IA32_APICBASE:
        cpu_set_apic_base(env->apic_state, val);
        break;
    case MSR_EFER:
        {
            uint64_t update_mask;

            update_mask = 0;
            if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL) {
                update_mask |= MSR_EFER_SCE;
            }
            if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
                update_mask |= MSR_EFER_LME;
            }
            if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            if (env->cpuid_ext2_features & CPUID_EXT2_NX) {
                update_mask |= MSR_EFER_NXE;
            }
            if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
                update_mask |= MSR_EFER_SVME;
            }
            if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            cpu_load_efer(env, (env->efer & ~update_mask) |
                          (val & update_mask));
        }
        break;
    case MSR_STAR:
        env->star = val;
        break;
    case MSR_PAT:
        env->pat = val;
        break;
    case MSR_VM_HSAVE_PA:
        env->vm_hsave = val;
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        env->lstar = val;
        break;
    case MSR_CSTAR:
        env->cstar = val;
        break;
    case MSR_FMASK:
        env->fmask = val;
        break;
    case MSR_FSBASE:
        env->segs[R_FS].base = val;
        break;
    case MSR_GSBASE:
        env->segs[R_GS].base = val;
        break;
    case MSR_KERNELGSBASE:
        env->kernelgsbase = val;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base = val;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val;
        break;
    case MSR_MTRRfix64K_00000:
        env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix64K_00000] = val;
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1] = val;
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3] = val;
        break;
    case MSR_MTRRdefType:
        env->mtrr_deftype = val;
        break;
    case MSR_MCG_STATUS:
        env->mcg_status = val;
        break;
    case MSR_MCG_CTL:
        if ((env->mcg_cap & MCG_CTL_P)
            && (val == 0 || val == ~(uint64_t)0)) {
            env->mcg_ctl = val;
        }
        break;
    case MSR_TSC_AUX:
        env->tsc_aux = val;
        break;
    case MSR_IA32_MISC_ENABLE:
        env->msr_ia32_misc_enable = val;
        break;
    default:
        if ((uint32_t)ECX >= MSR_MC0_CTL
            && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
            if ((offset & 0x3) != 0
                || (val == 0 || val == ~(uint64_t)0)) {
                env->mce_banks[offset] = val;
            }
            break;
        }
        /* XXX: exception? */
        break;
    }
}

void helper_rdmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);

    switch ((uint32_t)ECX) {
    case MSR_IA32_SYSENTER_CS:
        val = env->sysenter_cs;
        break;
    case MSR_IA32_SYSENTER_ESP:
        val = env->sysenter_esp;
        break;
    case MSR_IA32_SYSENTER_EIP:
        val = env->sysenter_eip;
        break;
    case MSR_IA32_APICBASE:
        val = cpu_get_apic_base(env->apic_state);
        break;
    case MSR_EFER:
        val = env->efer;
        break;
    case MSR_STAR:
        val = env->star;
        break;
    case MSR_PAT:
        val = env->pat;
        break;
    case MSR_VM_HSAVE_PA:
        val = env->vm_hsave;
        break;
    case MSR_IA32_PERF_STATUS:
        /* tsc_increment_by_tick */
        val = 1000ULL;
        /* CPU multiplier */
        val |= (((uint64_t)4ULL) << 40);
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        val = env->lstar;
        break;
    case MSR_CSTAR:
        val = env->cstar;
        break;
    case MSR_FMASK:
        val = env->fmask;
        break;
    case MSR_FSBASE:
        val = env->segs[R_FS].base;
        break;
    case MSR_GSBASE:
        val = env->segs[R_GS].base;
        break;
    case MSR_KERNELGSBASE:
        val = env->kernelgsbase;
        break;
    case MSR_TSC_AUX:
        val = env->tsc_aux;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask;
        break;
    case MSR_MTRRfix64K_00000:
        val = env->mtrr_fixed[0];
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1];
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3];
        break;
    case MSR_MTRRdefType:
        val = env->mtrr_deftype;
        break;
    case MSR_MTRRcap:
        if (env->cpuid_features & CPUID_MTRR) {
            val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
                MSR_MTRRcap_WC_SUPPORTED;
        } else {
            /* XXX: exception? */
            val = 0;
        }
        break;
    case MSR_MCG_CAP:
        val = env->mcg_cap;
        break;
    case MSR_MCG_CTL:
        if (env->mcg_cap & MCG_CTL_P) {
            val = env->mcg_ctl;
        } else {
            val = 0;
        }
        break;
    case MSR_MCG_STATUS:
        val = env->mcg_status;
        break;
    case MSR_IA32_MISC_ENABLE:
        val = env->msr_ia32_misc_enable;
        break;
    default:
        if ((uint32_t)ECX >= MSR_MC0_CTL
            && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
            val = env->mce_banks[offset];
            break;
        }
        /* XXX: exception? */
        val = 0;
        break;
    }
    EAX = (uint32_t)(val);
    EDX = (uint32_t)(val >> 32);
}
#endif

static void do_hlt(CPUX86State *env)
{
    env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
    env->halted = 1;
    env->exception_index = EXCP_HLT;
    cpu_loop_exit(env);
}

void helper_hlt(CPUX86State *env, int next_eip_addend)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
    EIP += next_eip_addend;

    do_hlt(env);
}

void helper_monitor(CPUX86State *env, target_ulong ptr)
{
    if ((uint32_t)ECX != 0) {
        raise_exception(env, EXCP0D_GPF);
    }
    /* XXX: store address? */
    cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
}

void helper_mwait(CPUX86State *env, int next_eip_addend)
{
    if ((uint32_t)ECX != 0) {
        raise_exception(env, EXCP0D_GPF);
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
    EIP += next_eip_addend;

    /* XXX: not complete but not completely erroneous */
    if (env->cpu_index != 0 || env->next_cpu != NULL) {
        /* more than one CPU: do not sleep because another CPU may
           wake this one */
    } else {
        do_hlt(env);
    }
}

void helper_debug(CPUX86State *env)
{
    env->exception_index = EXCP_DEBUG;
    cpu_loop_exit(env);
}
Commit	Line	Data
f7b2429f BS	1	/*
	2	* x86 misc helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
f7b2429f BS	21	#include "ioport.h"
	22	#include "helper.h"
	23
f7b2429f	24	/* check if Port I/O is allowed in TSS */
4a7443be	25	static inline void check_io(CPUX86State *env, int addr, int size)
f7b2429f BS	26	{
	27	int io_offset, val, mask;
	28
	29	/* TSS must be a valid 32 bit one */
	30	if (!(env->tr.flags & DESC_P_MASK) \|\|
	31	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
	32	env->tr.limit < 103) {
	33	goto fail;
	34	}
4a7443be	35	io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
f7b2429f BS	36	io_offset += (addr >> 3);
	37	/* Note: the check needs two bytes */
	38	if ((io_offset + 1) > env->tr.limit) {
	39	goto fail;
	40	}
4a7443be	41	val = cpu_lduw_kernel(env, env->tr.base + io_offset);
f7b2429f BS	42	val >>= (addr & 7);
	43	mask = (1 << size) - 1;
	44	/* all bits must be zero to allow the I/O */
	45	if ((val & mask) != 0) {
	46	fail:
	47	raise_exception_err(env, EXCP0D_GPF, 0);
	48	}
	49	}
	50
4a7443be	51	void helper_check_iob(CPUX86State *env, uint32_t t0)
f7b2429f	52	{
4a7443be	53	check_io(env, t0, 1);
f7b2429f BS	54	}
f7b2429f BS	55
4a7443be	56	void helper_check_iow(CPUX86State *env, uint32_t t0)
f7b2429f	57	{
4a7443be	58	check_io(env, t0, 2);
f7b2429f BS	59	}
f7b2429f BS	60
4a7443be	61	void helper_check_iol(CPUX86State *env, uint32_t t0)
f7b2429f	62	{
4a7443be	63	check_io(env, t0, 4);
f7b2429f BS	64	}
	65
	66	void helper_outb(uint32_t port, uint32_t data)
	67	{
	68	cpu_outb(port, data & 0xff);
	69	}
	70
	71	target_ulong helper_inb(uint32_t port)
	72	{
	73	return cpu_inb(port);
	74	}
	75
	76	void helper_outw(uint32_t port, uint32_t data)
	77	{
	78	cpu_outw(port, data & 0xffff);
	79	}
	80
	81	target_ulong helper_inw(uint32_t port)
	82	{
	83	return cpu_inw(port);
	84	}
	85
	86	void helper_outl(uint32_t port, uint32_t data)
	87	{
	88	cpu_outl(port, data);
	89	}
	90
	91	target_ulong helper_inl(uint32_t port)
	92	{
	93	return cpu_inl(port);
	94	}
	95
4a7443be	96	void helper_into(CPUX86State *env, int next_eip_addend)
f7b2429f BS	97	{
	98	int eflags;
	99
f0967a1a	100	eflags = cpu_cc_compute_all(env, CC_OP);
f7b2429f BS	101	if (eflags & CC_O) {
	102	raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
	103	}
	104	}
	105
4a7443be	106	void helper_single_step(CPUX86State *env)
f7b2429f BS	107	{
	108	#ifndef CONFIG_USER_ONLY
	109	check_hw_breakpoints(env, 1);
	110	env->dr[6] \|= DR6_BS;
	111	#endif
	112	raise_exception(env, EXCP01_DB);
	113	}
	114
4a7443be	115	void helper_cpuid(CPUX86State *env)
f7b2429f BS	116	{
	117	uint32_t eax, ebx, ecx, edx;
	118
	119	cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
	120
	121	cpu_x86_cpuid(env, (uint32_t)EAX, (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
	122	EAX = eax;
	123	EBX = ebx;
	124	ECX = ecx;
	125	EDX = edx;
	126	}
	127
	128	#if defined(CONFIG_USER_ONLY)
4a7443be	129	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	130	{
	131	return 0;
	132	}
	133
4a7443be	134	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	135	{
	136	}
	137
4a7443be	138	void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	139	{
	140	}
	141	#else
4a7443be	142	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	143	{
	144	target_ulong val;
	145
	146	cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
	147	switch (reg) {
	148	default:
	149	val = env->cr[reg];
	150	break;
	151	case 8:
	152	if (!(env->hflags2 & HF2_VINTR_MASK)) {
	153	val = cpu_get_apic_tpr(env->apic_state);
	154	} else {
	155	val = env->v_tpr;
	156	}
	157	break;
	158	}
	159	return val;
	160	}
	161
4a7443be	162	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	163	{
	164	cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
	165	switch (reg) {
	166	case 0:
	167	cpu_x86_update_cr0(env, t0);
	168	break;
	169	case 3:
	170	cpu_x86_update_cr3(env, t0);
	171	break;
	172	case 4:
	173	cpu_x86_update_cr4(env, t0);
	174	break;
	175	case 8:
	176	if (!(env->hflags2 & HF2_VINTR_MASK)) {
	177	cpu_set_apic_tpr(env->apic_state, t0);
	178	}
	179	env->v_tpr = t0 & 0x0f;
	180	break;
	181	default:
	182	env->cr[reg] = t0;
	183	break;
	184	}
	185	}
	186
4a7443be	187	void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	188	{
	189	int i;
	190
	191	if (reg < 4) {
	192	hw_breakpoint_remove(env, reg);
	193	env->dr[reg] = t0;
	194	hw_breakpoint_insert(env, reg);
	195	} else if (reg == 7) {
	196	for (i = 0; i < 4; i++) {
	197	hw_breakpoint_remove(env, i);
	198	}
	199	env->dr[7] = t0;
	200	for (i = 0; i < 4; i++) {
	201	hw_breakpoint_insert(env, i);
	202	}
	203	} else {
	204	env->dr[reg] = t0;
	205	}
	206	}
	207	#endif
	208
4a7443be	209	void helper_lmsw(CPUX86State *env, target_ulong t0)
f7b2429f BS	210	{
	211	/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
	212	if already set to one. */
	213	t0 = (env->cr[0] & ~0xe) \| (t0 & 0xf);
4a7443be	214	helper_write_crN(env, 0, t0);
f7b2429f BS	215	}
f7b2429f BS	216
4a7443be	217	void helper_invlpg(CPUX86State *env, target_ulong addr)
f7b2429f BS	218	{
	219	cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
	220	tlb_flush_page(env, addr);
	221	}
	222
4a7443be	223	void helper_rdtsc(CPUX86State *env)
f7b2429f BS	224	{
	225	uint64_t val;
	226
	227	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
	228	raise_exception(env, EXCP0D_GPF);
	229	}
	230	cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
	231
	232	val = cpu_get_tsc(env) + env->tsc_offset;
	233	EAX = (uint32_t)(val);
	234	EDX = (uint32_t)(val >> 32);
	235	}
	236
4a7443be	237	void helper_rdtscp(CPUX86State *env)
f7b2429f	238	{
4a7443be	239	helper_rdtsc(env);
f7b2429f BS	240	ECX = (uint32_t)(env->tsc_aux);
	241	}
	242
4a7443be	243	void helper_rdpmc(CPUX86State *env)
f7b2429f BS	244	{
	245	if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
	246	raise_exception(env, EXCP0D_GPF);
	247	}
	248	cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
	249
	250	/* currently unimplemented */
	251	qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
	252	raise_exception_err(env, EXCP06_ILLOP, 0);
	253	}
	254
	255	#if defined(CONFIG_USER_ONLY)
4a7443be	256	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	257	{
	258	}
	259
4a7443be	260	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	261	{
	262	}
	263	#else
4a7443be	264	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	265	{
	266	uint64_t val;
	267
	268	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
	269
	270	val = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
	271
	272	switch ((uint32_t)ECX) {
	273	case MSR_IA32_SYSENTER_CS:
	274	env->sysenter_cs = val & 0xffff;
	275	break;
	276	case MSR_IA32_SYSENTER_ESP:
	277	env->sysenter_esp = val;
	278	break;
	279	case MSR_IA32_SYSENTER_EIP:
	280	env->sysenter_eip = val;
	281	break;
	282	case MSR_IA32_APICBASE:
	283	cpu_set_apic_base(env->apic_state, val);
	284	break;
	285	case MSR_EFER:
	286	{
	287	uint64_t update_mask;
	288
	289	update_mask = 0;
	290	if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL) {
	291	update_mask \|= MSR_EFER_SCE;
	292	}
	293	if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
	294	update_mask \|= MSR_EFER_LME;
	295	}
	296	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
	297	update_mask \|= MSR_EFER_FFXSR;
	298	}
	299	if (env->cpuid_ext2_features & CPUID_EXT2_NX) {
	300	update_mask \|= MSR_EFER_NXE;
	301	}
	302	if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
	303	update_mask \|= MSR_EFER_SVME;
	304	}
	305	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
	306	update_mask \|= MSR_EFER_FFXSR;
	307	}
	308	cpu_load_efer(env, (env->efer & ~update_mask) \|
	309	(val & update_mask));
	310	}
	311	break;
	312	case MSR_STAR:
	313	env->star = val;
	314	break;
	315	case MSR_PAT:
	316	env->pat = val;
	317	break;
	318	case MSR_VM_HSAVE_PA:
	319	env->vm_hsave = val;
	320	break;
	321	#ifdef TARGET_X86_64
	322	case MSR_LSTAR:
	323	env->lstar = val;
	324	break;
	325	case MSR_CSTAR:
	326	env->cstar = val;
	327	break;
	328	case MSR_FMASK:
329	env->fmask = val;
330	break;
331	case MSR_FSBASE:
332	env->segs[R_FS].base = val;
333	break;
334	case MSR_GSBASE:
335	env->segs[R_GS].base = val;
336	break;
337	case MSR_KERNELGSBASE:
338	env->kernelgsbase = val;
339	break;
340	#endif
341	case MSR_MTRRphysBase(0):
342	case MSR_MTRRphysBase(1):
343	case MSR_MTRRphysBase(2):
344	case MSR_MTRRphysBase(3):
345	case MSR_MTRRphysBase(4):
346	case MSR_MTRRphysBase(5):
347	case MSR_MTRRphysBase(6):
348	case MSR_MTRRphysBase(7):
349	env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base = val;
350	break;
351	case MSR_MTRRphysMask(0):
352	case MSR_MTRRphysMask(1):
353	case MSR_MTRRphysMask(2):
354	case MSR_MTRRphysMask(3):
355	case MSR_MTRRphysMask(4):
356	case MSR_MTRRphysMask(5):
357	case MSR_MTRRphysMask(6):
358	case MSR_MTRRphysMask(7):
359	env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val;
360	break;
361	case MSR_MTRRfix64K_00000:
362	env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix64K_00000] = val;
363	break;
364	case MSR_MTRRfix16K_80000:
365	case MSR_MTRRfix16K_A0000:
366	env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1] = val;
367	break;
368	case MSR_MTRRfix4K_C0000:
369	case MSR_MTRRfix4K_C8000:
370	case MSR_MTRRfix4K_D0000:
371	case MSR_MTRRfix4K_D8000:
372	case MSR_MTRRfix4K_E0000:
373	case MSR_MTRRfix4K_E8000:
374	case MSR_MTRRfix4K_F0000:
375	case MSR_MTRRfix4K_F8000:
376	env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3] = val;
377	break;
378	case MSR_MTRRdefType:
379	env->mtrr_deftype = val;
380	break;
381	case MSR_MCG_STATUS:
382	env->mcg_status = val;
383	break;
384	case MSR_MCG_CTL:
385	if ((env->mcg_cap & MCG_CTL_P)
386	&& (val == 0 \|\| val == ~(uint64_t)0)) {
387	env->mcg_ctl = val;
388	}
389	break;
390	case MSR_TSC_AUX:
391	env->tsc_aux = val;
392	break;
393	case MSR_IA32_MISC_ENABLE:
394	env->msr_ia32_misc_enable = val;
395	break;
396	default:
397	if ((uint32_t)ECX >= MSR_MC0_CTL
398	&& (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
399	uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
400	if ((offset & 0x3) != 0
401	\|\| (val == 0 \|\| val == ~(uint64_t)0)) {
402	env->mce_banks[offset] = val;
403	}
404	break;
405	}
406	/* XXX: exception? */
407	break;
408	}
409	}
410
4a7443be	411	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	412	{
	413	uint64_t val;
	414
	415	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
	416
	417	switch ((uint32_t)ECX) {
	418	case MSR_IA32_SYSENTER_CS:
	419	val = env->sysenter_cs;
	420	break;
	421	case MSR_IA32_SYSENTER_ESP:
	422	val = env->sysenter_esp;
	423	break;
	424	case MSR_IA32_SYSENTER_EIP:
	425	val = env->sysenter_eip;
	426	break;
	427	case MSR_IA32_APICBASE:
	428	val = cpu_get_apic_base(env->apic_state);
	429	break;
	430	case MSR_EFER:
	431	val = env->efer;
	432	break;
	433	case MSR_STAR:
	434	val = env->star;
	435	break;
	436	case MSR_PAT:
	437	val = env->pat;
	438	break;
	439	case MSR_VM_HSAVE_PA:
	440	val = env->vm_hsave;
	441	break;
	442	case MSR_IA32_PERF_STATUS:
	443	/* tsc_increment_by_tick */
	444	val = 1000ULL;
	445	/* CPU multiplier */
	446	val \|= (((uint64_t)4ULL) << 40);
	447	break;
	448	#ifdef TARGET_X86_64
	449	case MSR_LSTAR:
	450	val = env->lstar;
	451	break;
	452	case MSR_CSTAR:
	453	val = env->cstar;
	454	break;
	455	case MSR_FMASK:
	456	val = env->fmask;
	457	break;
	458	case MSR_FSBASE:
	459	val = env->segs[R_FS].base;
	460	break;
	461	case MSR_GSBASE:
	462	val = env->segs[R_GS].base;
	463	break;
	464	case MSR_KERNELGSBASE:
	465	val = env->kernelgsbase;
	466	break;
	467	case MSR_TSC_AUX:
	468	val = env->tsc_aux;
	469	break;
	470	#endif
	471	case MSR_MTRRphysBase(0):
	472	case MSR_MTRRphysBase(1):
	473	case MSR_MTRRphysBase(2):
	474	case MSR_MTRRphysBase(3):
	475	case MSR_MTRRphysBase(4):
476	case MSR_MTRRphysBase(5):
477	case MSR_MTRRphysBase(6):
478	case MSR_MTRRphysBase(7):
479	val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base;
480	break;
481	case MSR_MTRRphysMask(0):
482	case MSR_MTRRphysMask(1):
483	case MSR_MTRRphysMask(2):
484	case MSR_MTRRphysMask(3):
485	case MSR_MTRRphysMask(4):
486	case MSR_MTRRphysMask(5):
487	case MSR_MTRRphysMask(6):
488	case MSR_MTRRphysMask(7):
489	val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask;
490	break;
491	case MSR_MTRRfix64K_00000:
492	val = env->mtrr_fixed[0];
493	break;
494	case MSR_MTRRfix16K_80000:
495	case MSR_MTRRfix16K_A0000:
496	val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1];
497	break;
498	case MSR_MTRRfix4K_C0000:
499	case MSR_MTRRfix4K_C8000:
500	case MSR_MTRRfix4K_D0000:
501	case MSR_MTRRfix4K_D8000:
502	case MSR_MTRRfix4K_E0000:
503	case MSR_MTRRfix4K_E8000:
504	case MSR_MTRRfix4K_F0000:
505	case MSR_MTRRfix4K_F8000:
506	val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3];
507	break;
508	case MSR_MTRRdefType:
509	val = env->mtrr_deftype;
510	break;
511	case MSR_MTRRcap:
512	if (env->cpuid_features & CPUID_MTRR) {
513	val = MSR_MTRRcap_VCNT \| MSR_MTRRcap_FIXRANGE_SUPPORT \|
514	MSR_MTRRcap_WC_SUPPORTED;
515	} else {
516	/* XXX: exception? */
517	val = 0;
518	}
519	break;
520	case MSR_MCG_CAP:
521	val = env->mcg_cap;
522	break;
523	case MSR_MCG_CTL:
524	if (env->mcg_cap & MCG_CTL_P) {
525	val = env->mcg_ctl;
526	} else {
527	val = 0;
528	}
529	break;
530	case MSR_MCG_STATUS:
531	val = env->mcg_status;
532	break;
533	case MSR_IA32_MISC_ENABLE:
534	val = env->msr_ia32_misc_enable;
535	break;
536	default:
537	if ((uint32_t)ECX >= MSR_MC0_CTL
538	&& (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
539	uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
540	val = env->mce_banks[offset];
541	break;
542	}
543	/* XXX: exception? */
544	val = 0;
545	break;
546	}
547	EAX = (uint32_t)(val);
548	EDX = (uint32_t)(val >> 32);
549	}
550	#endif
551
4a7443be	552	static void do_hlt(CPUX86State *env)
f7b2429f BS	553	{
	554	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
	555	env->halted = 1;
	556	env->exception_index = EXCP_HLT;
	557	cpu_loop_exit(env);
	558	}
	559
4a7443be	560	void helper_hlt(CPUX86State *env, int next_eip_addend)
f7b2429f BS	561	{
	562	cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
	563	EIP += next_eip_addend;
	564
4a7443be	565	do_hlt(env);
f7b2429f BS	566	}
f7b2429f BS	567
4a7443be	568	void helper_monitor(CPUX86State *env, target_ulong ptr)
f7b2429f BS	569	{
	570	if ((uint32_t)ECX != 0) {
	571	raise_exception(env, EXCP0D_GPF);
	572	}
	573	/* XXX: store address? */
	574	cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
	575	}
	576
4a7443be	577	void helper_mwait(CPUX86State *env, int next_eip_addend)
f7b2429f BS	578	{
	579	if ((uint32_t)ECX != 0) {
	580	raise_exception(env, EXCP0D_GPF);
	581	}
	582	cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
	583	EIP += next_eip_addend;
	584
	585	/* XXX: not complete but not completely erroneous */
	586	if (env->cpu_index != 0 \|\| env->next_cpu != NULL) {
	587	/* more than one CPU: do not sleep because another CPU may
	588	wake this one */
	589	} else {
4a7443be	590	do_hlt(env);
f7b2429f BS	591	}
	592	}
	593
4a7443be	594	void helper_debug(CPUX86State *env)
f7b2429f BS	595	{
	596	env->exception_index = EXCP_DEBUG;
	597	cpu_loop_exit(env);
	598	}