[qemu.git] / target-i386 / smm_helper.c

/*
 *  x86 SMM helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "dyngen-exec.h"
#include "helper.h"

/* SMM support */

#if defined(CONFIG_USER_ONLY)

void do_smm_enter(CPUX86State *env1)
{
}

void helper_rsm(void)
{
}

#else

#ifdef TARGET_X86_64
#define SMM_REVISION_ID 0x00020064
#else
#define SMM_REVISION_ID 0x00020000
#endif

void do_smm_enter(CPUX86State *env1)
{
    target_ulong sm_state;
    SegmentCache *dt;
    int i, offset;
    CPUX86State *saved_env;

    saved_env = env;
    env = env1;

    qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
    log_cpu_state_mask(CPU_LOG_INT, env, X86_DUMP_CCOP);

    env->hflags |= HF_SMM_MASK;
    cpu_smm_update(env);

    sm_state = env->smbase + 0x8000;

#ifdef TARGET_X86_64
    for (i = 0; i < 6; i++) {
        dt = &env->segs[i];
        offset = 0x7e00 + i * 16;
        stw_phys(sm_state + offset, dt->selector);
        stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
        stl_phys(sm_state + offset + 4, dt->limit);
        stq_phys(sm_state + offset + 8, dt->base);
    }

    stq_phys(sm_state + 0x7e68, env->gdt.base);
    stl_phys(sm_state + 0x7e64, env->gdt.limit);

    stw_phys(sm_state + 0x7e70, env->ldt.selector);
    stq_phys(sm_state + 0x7e78, env->ldt.base);
    stl_phys(sm_state + 0x7e74, env->ldt.limit);
    stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);

    stq_phys(sm_state + 0x7e88, env->idt.base);
    stl_phys(sm_state + 0x7e84, env->idt.limit);

    stw_phys(sm_state + 0x7e90, env->tr.selector);
    stq_phys(sm_state + 0x7e98, env->tr.base);
    stl_phys(sm_state + 0x7e94, env->tr.limit);
    stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);

    stq_phys(sm_state + 0x7ed0, env->efer);

    stq_phys(sm_state + 0x7ff8, EAX);
    stq_phys(sm_state + 0x7ff0, ECX);
    stq_phys(sm_state + 0x7fe8, EDX);
    stq_phys(sm_state + 0x7fe0, EBX);
    stq_phys(sm_state + 0x7fd8, ESP);
    stq_phys(sm_state + 0x7fd0, EBP);
    stq_phys(sm_state + 0x7fc8, ESI);
    stq_phys(sm_state + 0x7fc0, EDI);
    for (i = 8; i < 16; i++) {
        stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
    }
    stq_phys(sm_state + 0x7f78, env->eip);
    stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
    stl_phys(sm_state + 0x7f68, env->dr[6]);
    stl_phys(sm_state + 0x7f60, env->dr[7]);

    stl_phys(sm_state + 0x7f48, env->cr[4]);
    stl_phys(sm_state + 0x7f50, env->cr[3]);
    stl_phys(sm_state + 0x7f58, env->cr[0]);

    stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
    stl_phys(sm_state + 0x7f00, env->smbase);
#else
    stl_phys(sm_state + 0x7ffc, env->cr[0]);
    stl_phys(sm_state + 0x7ff8, env->cr[3]);
    stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
    stl_phys(sm_state + 0x7ff0, env->eip);
    stl_phys(sm_state + 0x7fec, EDI);
    stl_phys(sm_state + 0x7fe8, ESI);
    stl_phys(sm_state + 0x7fe4, EBP);
    stl_phys(sm_state + 0x7fe0, ESP);
    stl_phys(sm_state + 0x7fdc, EBX);
    stl_phys(sm_state + 0x7fd8, EDX);
    stl_phys(sm_state + 0x7fd4, ECX);
    stl_phys(sm_state + 0x7fd0, EAX);
    stl_phys(sm_state + 0x7fcc, env->dr[6]);
    stl_phys(sm_state + 0x7fc8, env->dr[7]);

    stl_phys(sm_state + 0x7fc4, env->tr.selector);
    stl_phys(sm_state + 0x7f64, env->tr.base);
    stl_phys(sm_state + 0x7f60, env->tr.limit);
    stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);

    stl_phys(sm_state + 0x7fc0, env->ldt.selector);
    stl_phys(sm_state + 0x7f80, env->ldt.base);
    stl_phys(sm_state + 0x7f7c, env->ldt.limit);
    stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);

    stl_phys(sm_state + 0x7f74, env->gdt.base);
    stl_phys(sm_state + 0x7f70, env->gdt.limit);

    stl_phys(sm_state + 0x7f58, env->idt.base);
    stl_phys(sm_state + 0x7f54, env->idt.limit);

    for (i = 0; i < 6; i++) {
        dt = &env->segs[i];
        if (i < 3) {
            offset = 0x7f84 + i * 12;
        } else {
            offset = 0x7f2c + (i - 3) * 12;
        }
        stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
        stl_phys(sm_state + offset + 8, dt->base);
        stl_phys(sm_state + offset + 4, dt->limit);
        stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
    }
    stl_phys(sm_state + 0x7f14, env->cr[4]);

    stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
    stl_phys(sm_state + 0x7ef8, env->smbase);
#endif
    /* init SMM cpu state */

#ifdef TARGET_X86_64
    cpu_load_efer(env, 0);
#endif
    cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
                              DF_MASK));
    env->eip = 0x00008000;
    cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
                           0xffffffff, 0);
    cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
    cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
    cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
    cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
    cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);

    cpu_x86_update_cr0(env,
                       env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
                                      CR0_PG_MASK));
    cpu_x86_update_cr4(env, 0);
    env->dr[7] = 0x00000400;
    CC_OP = CC_OP_EFLAGS;
    env = saved_env;
}

void helper_rsm(void)
{
    target_ulong sm_state;
    int i, offset;
    uint32_t val;

    sm_state = env->smbase + 0x8000;
#ifdef TARGET_X86_64
    cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));

    for (i = 0; i < 6; i++) {
        offset = 0x7e00 + i * 16;
        cpu_x86_load_seg_cache(env, i,
                               lduw_phys(sm_state + offset),
                               ldq_phys(sm_state + offset + 8),
                               ldl_phys(sm_state + offset + 4),
                               (lduw_phys(sm_state + offset + 2) &
                                0xf0ff) << 8);
    }

    env->gdt.base = ldq_phys(sm_state + 0x7e68);
    env->gdt.limit = ldl_phys(sm_state + 0x7e64);

    env->ldt.selector = lduw_phys(sm_state + 0x7e70);
    env->ldt.base = ldq_phys(sm_state + 0x7e78);
    env->ldt.limit = ldl_phys(sm_state + 0x7e74);
    env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;

    env->idt.base = ldq_phys(sm_state + 0x7e88);
    env->idt.limit = ldl_phys(sm_state + 0x7e84);

    env->tr.selector = lduw_phys(sm_state + 0x7e90);
    env->tr.base = ldq_phys(sm_state + 0x7e98);
    env->tr.limit = ldl_phys(sm_state + 0x7e94);
    env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;

    EAX = ldq_phys(sm_state + 0x7ff8);
    ECX = ldq_phys(sm_state + 0x7ff0);
    EDX = ldq_phys(sm_state + 0x7fe8);
    EBX = ldq_phys(sm_state + 0x7fe0);
    ESP = ldq_phys(sm_state + 0x7fd8);
    EBP = ldq_phys(sm_state + 0x7fd0);
    ESI = ldq_phys(sm_state + 0x7fc8);
    EDI = ldq_phys(sm_state + 0x7fc0);
    for (i = 8; i < 16; i++) {
        env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
    }
    env->eip = ldq_phys(sm_state + 0x7f78);
    cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
    env->dr[6] = ldl_phys(sm_state + 0x7f68);
    env->dr[7] = ldl_phys(sm_state + 0x7f60);

    cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
    cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
    cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));

    val = ldl_phys(sm_state + 0x7efc); /* revision ID */
    if (val & 0x20000) {
        env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
    }
#else
    cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
    cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
    cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
                    ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
    env->eip = ldl_phys(sm_state + 0x7ff0);
    EDI = ldl_phys(sm_state + 0x7fec);
    ESI = ldl_phys(sm_state + 0x7fe8);
    EBP = ldl_phys(sm_state + 0x7fe4);
    ESP = ldl_phys(sm_state + 0x7fe0);
    EBX = ldl_phys(sm_state + 0x7fdc);
    EDX = ldl_phys(sm_state + 0x7fd8);
    ECX = ldl_phys(sm_state + 0x7fd4);
    EAX = ldl_phys(sm_state + 0x7fd0);
    env->dr[6] = ldl_phys(sm_state + 0x7fcc);
    env->dr[7] = ldl_phys(sm_state + 0x7fc8);

    env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
    env->tr.base = ldl_phys(sm_state + 0x7f64);
    env->tr.limit = ldl_phys(sm_state + 0x7f60);
    env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;

    env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
    env->ldt.base = ldl_phys(sm_state + 0x7f80);
    env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
    env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;

    env->gdt.base = ldl_phys(sm_state + 0x7f74);
    env->gdt.limit = ldl_phys(sm_state + 0x7f70);

    env->idt.base = ldl_phys(sm_state + 0x7f58);
    env->idt.limit = ldl_phys(sm_state + 0x7f54);

    for (i = 0; i < 6; i++) {
        if (i < 3) {
            offset = 0x7f84 + i * 12;
        } else {
            offset = 0x7f2c + (i - 3) * 12;
        }
        cpu_x86_load_seg_cache(env, i,
                               ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
                               ldl_phys(sm_state + offset + 8),
                               ldl_phys(sm_state + offset + 4),
                               (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
    }
    cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));

    val = ldl_phys(sm_state + 0x7efc); /* revision ID */
    if (val & 0x20000) {
        env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
    }
#endif
    CC_OP = CC_OP_EFLAGS;
    env->hflags &= ~HF_SMM_MASK;
    cpu_smm_update(env);

    qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
    log_cpu_state_mask(CPU_LOG_INT, env, X86_DUMP_CCOP);
}

#endif /* !CONFIG_USER_ONLY */
Commit	Line	Data
ab109e59 BS	1	/*
	2	* x86 SMM helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
	21	#include "dyngen-exec.h"
	22	#include "helper.h"
	23
	24	/* SMM support */
	25
	26	#if defined(CONFIG_USER_ONLY)
	27
	28	void do_smm_enter(CPUX86State *env1)
	29	{
	30	}
	31
	32	void helper_rsm(void)
	33	{
	34	}
	35
	36	#else
	37
	38	#ifdef TARGET_X86_64
	39	#define SMM_REVISION_ID 0x00020064
	40	#else
	41	#define SMM_REVISION_ID 0x00020000
	42	#endif
	43
	44	void do_smm_enter(CPUX86State *env1)
	45	{
	46	target_ulong sm_state;
	47	SegmentCache *dt;
	48	int i, offset;
	49	CPUX86State *saved_env;
	50
	51	saved_env = env;
	52	env = env1;
	53
	54	qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
	55	log_cpu_state_mask(CPU_LOG_INT, env, X86_DUMP_CCOP);
	56
	57	env->hflags \|= HF_SMM_MASK;
	58	cpu_smm_update(env);
	59
	60	sm_state = env->smbase + 0x8000;
	61
	62	#ifdef TARGET_X86_64
	63	for (i = 0; i < 6; i++) {
	64	dt = &env->segs[i];
65	offset = 0x7e00 + i * 16;
66	stw_phys(sm_state + offset, dt->selector);
67	stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
68	stl_phys(sm_state + offset + 4, dt->limit);
69	stq_phys(sm_state + offset + 8, dt->base);
70	}
71
72	stq_phys(sm_state + 0x7e68, env->gdt.base);
73	stl_phys(sm_state + 0x7e64, env->gdt.limit);
74
75	stw_phys(sm_state + 0x7e70, env->ldt.selector);
76	stq_phys(sm_state + 0x7e78, env->ldt.base);
77	stl_phys(sm_state + 0x7e74, env->ldt.limit);
78	stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
79
80	stq_phys(sm_state + 0x7e88, env->idt.base);
81	stl_phys(sm_state + 0x7e84, env->idt.limit);
82
83	stw_phys(sm_state + 0x7e90, env->tr.selector);
84	stq_phys(sm_state + 0x7e98, env->tr.base);
85	stl_phys(sm_state + 0x7e94, env->tr.limit);
86	stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
87
88	stq_phys(sm_state + 0x7ed0, env->efer);
89
90	stq_phys(sm_state + 0x7ff8, EAX);
91	stq_phys(sm_state + 0x7ff0, ECX);
92	stq_phys(sm_state + 0x7fe8, EDX);
93	stq_phys(sm_state + 0x7fe0, EBX);
94	stq_phys(sm_state + 0x7fd8, ESP);
95	stq_phys(sm_state + 0x7fd0, EBP);
96	stq_phys(sm_state + 0x7fc8, ESI);
97	stq_phys(sm_state + 0x7fc0, EDI);
98	for (i = 8; i < 16; i++) {
99	stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
100	}
101	stq_phys(sm_state + 0x7f78, env->eip);
102	stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
103	stl_phys(sm_state + 0x7f68, env->dr[6]);
104	stl_phys(sm_state + 0x7f60, env->dr[7]);
105
106	stl_phys(sm_state + 0x7f48, env->cr[4]);
107	stl_phys(sm_state + 0x7f50, env->cr[3]);
108	stl_phys(sm_state + 0x7f58, env->cr[0]);
109
110	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
111	stl_phys(sm_state + 0x7f00, env->smbase);
112	#else
113	stl_phys(sm_state + 0x7ffc, env->cr[0]);
114	stl_phys(sm_state + 0x7ff8, env->cr[3]);
115	stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
116	stl_phys(sm_state + 0x7ff0, env->eip);
117	stl_phys(sm_state + 0x7fec, EDI);
118	stl_phys(sm_state + 0x7fe8, ESI);
119	stl_phys(sm_state + 0x7fe4, EBP);
120	stl_phys(sm_state + 0x7fe0, ESP);
121	stl_phys(sm_state + 0x7fdc, EBX);
122	stl_phys(sm_state + 0x7fd8, EDX);
123	stl_phys(sm_state + 0x7fd4, ECX);
124	stl_phys(sm_state + 0x7fd0, EAX);
125	stl_phys(sm_state + 0x7fcc, env->dr[6]);
126	stl_phys(sm_state + 0x7fc8, env->dr[7]);
127
128	stl_phys(sm_state + 0x7fc4, env->tr.selector);
129	stl_phys(sm_state + 0x7f64, env->tr.base);
130	stl_phys(sm_state + 0x7f60, env->tr.limit);
131	stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
132
133	stl_phys(sm_state + 0x7fc0, env->ldt.selector);
134	stl_phys(sm_state + 0x7f80, env->ldt.base);
135	stl_phys(sm_state + 0x7f7c, env->ldt.limit);
136	stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
137
138	stl_phys(sm_state + 0x7f74, env->gdt.base);
139	stl_phys(sm_state + 0x7f70, env->gdt.limit);
140
141	stl_phys(sm_state + 0x7f58, env->idt.base);
142	stl_phys(sm_state + 0x7f54, env->idt.limit);
143
144	for (i = 0; i < 6; i++) {
145	dt = &env->segs[i];
146	if (i < 3) {
147	offset = 0x7f84 + i * 12;
148	} else {
149	offset = 0x7f2c + (i - 3) * 12;
150	}
151	stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
152	stl_phys(sm_state + offset + 8, dt->base);
153	stl_phys(sm_state + offset + 4, dt->limit);
154	stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
155	}
156	stl_phys(sm_state + 0x7f14, env->cr[4]);
157
158	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
159	stl_phys(sm_state + 0x7ef8, env->smbase);
160	#endif
161	/* init SMM cpu state */
162
163	#ifdef TARGET_X86_64
164	cpu_load_efer(env, 0);
165	#endif
166	cpu_load_eflags(env, 0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \|
167	DF_MASK));
168	env->eip = 0x00008000;
169	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
170	0xffffffff, 0);
171	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
172	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
173	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
174	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
175	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
176
177	cpu_x86_update_cr0(env,
178	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \|
179	CR0_PG_MASK));
180	cpu_x86_update_cr4(env, 0);
181	env->dr[7] = 0x00000400;
182	CC_OP = CC_OP_EFLAGS;
183	env = saved_env;
184	}
185
186	void helper_rsm(void)
187	{
188	target_ulong sm_state;
189	int i, offset;
190	uint32_t val;
191
192	sm_state = env->smbase + 0x8000;
193	#ifdef TARGET_X86_64
194	cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));
195
196	for (i = 0; i < 6; i++) {
197	offset = 0x7e00 + i * 16;
198	cpu_x86_load_seg_cache(env, i,
199	lduw_phys(sm_state + offset),
200	ldq_phys(sm_state + offset + 8),
201	ldl_phys(sm_state + offset + 4),
202	(lduw_phys(sm_state + offset + 2) &
203	0xf0ff) << 8);
204	}
205
206	env->gdt.base = ldq_phys(sm_state + 0x7e68);
207	env->gdt.limit = ldl_phys(sm_state + 0x7e64);
208
209	env->ldt.selector = lduw_phys(sm_state + 0x7e70);
210	env->ldt.base = ldq_phys(sm_state + 0x7e78);
211	env->ldt.limit = ldl_phys(sm_state + 0x7e74);
212	env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
213
214	env->idt.base = ldq_phys(sm_state + 0x7e88);
215	env->idt.limit = ldl_phys(sm_state + 0x7e84);
216
217	env->tr.selector = lduw_phys(sm_state + 0x7e90);
218	env->tr.base = ldq_phys(sm_state + 0x7e98);
219	env->tr.limit = ldl_phys(sm_state + 0x7e94);
220	env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
221
222	EAX = ldq_phys(sm_state + 0x7ff8);
223	ECX = ldq_phys(sm_state + 0x7ff0);
224	EDX = ldq_phys(sm_state + 0x7fe8);
225	EBX = ldq_phys(sm_state + 0x7fe0);
226	ESP = ldq_phys(sm_state + 0x7fd8);
227	EBP = ldq_phys(sm_state + 0x7fd0);
228	ESI = ldq_phys(sm_state + 0x7fc8);
229	EDI = ldq_phys(sm_state + 0x7fc0);
230	for (i = 8; i < 16; i++) {
231	env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
232	}
233	env->eip = ldq_phys(sm_state + 0x7f78);
234	cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
235	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
236	env->dr[6] = ldl_phys(sm_state + 0x7f68);
237	env->dr[7] = ldl_phys(sm_state + 0x7f60);
238
239	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
240	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
241	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
242
243	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
244	if (val & 0x20000) {
245	env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
246	}
247	#else
248	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
249	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
250	cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
251	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
252	env->eip = ldl_phys(sm_state + 0x7ff0);
253	EDI = ldl_phys(sm_state + 0x7fec);
254	ESI = ldl_phys(sm_state + 0x7fe8);
255	EBP = ldl_phys(sm_state + 0x7fe4);
256	ESP = ldl_phys(sm_state + 0x7fe0);
257	EBX = ldl_phys(sm_state + 0x7fdc);
258	EDX = ldl_phys(sm_state + 0x7fd8);
259	ECX = ldl_phys(sm_state + 0x7fd4);
260	EAX = ldl_phys(sm_state + 0x7fd0);
261	env->dr[6] = ldl_phys(sm_state + 0x7fcc);
262	env->dr[7] = ldl_phys(sm_state + 0x7fc8);
263
264	env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
265	env->tr.base = ldl_phys(sm_state + 0x7f64);
266	env->tr.limit = ldl_phys(sm_state + 0x7f60);
267	env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
268
269	env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
270	env->ldt.base = ldl_phys(sm_state + 0x7f80);
271	env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
272	env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
273
274	env->gdt.base = ldl_phys(sm_state + 0x7f74);
275	env->gdt.limit = ldl_phys(sm_state + 0x7f70);
276
277	env->idt.base = ldl_phys(sm_state + 0x7f58);
278	env->idt.limit = ldl_phys(sm_state + 0x7f54);
279
280	for (i = 0; i < 6; i++) {
281	if (i < 3) {
282	offset = 0x7f84 + i * 12;
283	} else {
284	offset = 0x7f2c + (i - 3) * 12;
285	}
286	cpu_x86_load_seg_cache(env, i,
287	ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
288	ldl_phys(sm_state + offset + 8),
289	ldl_phys(sm_state + offset + 4),
290	(ldl_phys(sm_state + offset) & 0xf0ff) << 8);
291	}
292	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
293
294	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
295	if (val & 0x20000) {
296	env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
297	}
298	#endif
299	CC_OP = CC_OP_EFLAGS;
300	env->hflags &= ~HF_SMM_MASK;
301	cpu_smm_update(env);
302
303	qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
304	log_cpu_state_mask(CPU_LOG_INT, env, X86_DUMP_CCOP);
305	}
306
307	#endif /* !CONFIG_USER_ONLY */