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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 translation | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af FB |
18 | */ |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
2c0262af FB |
25 | |
26 | #include "cpu.h" | |
2c0262af | 27 | #include "disas.h" |
57fec1fe | 28 | #include "tcg-op.h" |
2c0262af | 29 | |
a7812ae4 PB |
30 | #include "helper.h" |
31 | #define GEN_HELPER 1 | |
32 | #include "helper.h" | |
33 | ||
2c0262af FB |
34 | #define PREFIX_REPZ 0x01 |
35 | #define PREFIX_REPNZ 0x02 | |
36 | #define PREFIX_LOCK 0x04 | |
37 | #define PREFIX_DATA 0x08 | |
38 | #define PREFIX_ADR 0x10 | |
39 | ||
14ce26e7 | 40 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
41 | #define CODE64(s) ((s)->code64) |
42 | #define REX_X(s) ((s)->rex_x) | |
43 | #define REX_B(s) ((s)->rex_b) | |
14ce26e7 | 44 | #else |
14ce26e7 FB |
45 | #define CODE64(s) 0 |
46 | #define REX_X(s) 0 | |
47 | #define REX_B(s) 0 | |
48 | #endif | |
49 | ||
57fec1fe FB |
50 | //#define MACRO_TEST 1 |
51 | ||
57fec1fe | 52 | /* global register indexes */ |
a7812ae4 PB |
53 | static TCGv_ptr cpu_env; |
54 | static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp; | |
55 | static TCGv_i32 cpu_cc_op; | |
cc739bb0 | 56 | static TCGv cpu_regs[CPU_NB_REGS]; |
1e4840bf FB |
57 | /* local temps */ |
58 | static TCGv cpu_T[2], cpu_T3; | |
57fec1fe | 59 | /* local register indexes (only used inside old micro ops) */ |
a7812ae4 PB |
60 | static TCGv cpu_tmp0, cpu_tmp4; |
61 | static TCGv_ptr cpu_ptr0, cpu_ptr1; | |
62 | static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; | |
63 | static TCGv_i64 cpu_tmp1_i64; | |
bedda79c | 64 | static TCGv cpu_tmp5; |
57fec1fe | 65 | |
1a7ff922 PB |
66 | static uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; |
67 | ||
2e70f6ef PB |
68 | #include "gen-icount.h" |
69 | ||
57fec1fe FB |
70 | #ifdef TARGET_X86_64 |
71 | static int x86_64_hregs; | |
ae063a68 FB |
72 | #endif |
73 | ||
2c0262af FB |
74 | typedef struct DisasContext { |
75 | /* current insn context */ | |
76 | int override; /* -1 if no override */ | |
77 | int prefix; | |
78 | int aflag, dflag; | |
14ce26e7 | 79 | target_ulong pc; /* pc = eip + cs_base */ |
2c0262af FB |
80 | int is_jmp; /* 1 = means jump (stop translation), 2 means CPU |
81 | static state change (stop translation) */ | |
82 | /* current block context */ | |
14ce26e7 | 83 | target_ulong cs_base; /* base of CS segment */ |
2c0262af FB |
84 | int pe; /* protected mode */ |
85 | int code32; /* 32 bit code segment */ | |
14ce26e7 FB |
86 | #ifdef TARGET_X86_64 |
87 | int lma; /* long mode active */ | |
88 | int code64; /* 64 bit code segment */ | |
89 | int rex_x, rex_b; | |
90 | #endif | |
2c0262af FB |
91 | int ss32; /* 32 bit stack segment */ |
92 | int cc_op; /* current CC operation */ | |
93 | int addseg; /* non zero if either DS/ES/SS have a non zero base */ | |
94 | int f_st; /* currently unused */ | |
95 | int vm86; /* vm86 mode */ | |
96 | int cpl; | |
97 | int iopl; | |
98 | int tf; /* TF cpu flag */ | |
34865134 | 99 | int singlestep_enabled; /* "hardware" single step enabled */ |
2c0262af FB |
100 | int jmp_opt; /* use direct block chaining for direct jumps */ |
101 | int mem_index; /* select memory access functions */ | |
c068688b | 102 | uint64_t flags; /* all execution flags */ |
2c0262af FB |
103 | struct TranslationBlock *tb; |
104 | int popl_esp_hack; /* for correct popl with esp base handling */ | |
14ce26e7 FB |
105 | int rip_offset; /* only used in x86_64, but left for simplicity */ |
106 | int cpuid_features; | |
3d7374c5 | 107 | int cpuid_ext_features; |
e771edab | 108 | int cpuid_ext2_features; |
12e26b75 | 109 | int cpuid_ext3_features; |
a9321a4d | 110 | int cpuid_7_0_ebx_features; |
2c0262af FB |
111 | } DisasContext; |
112 | ||
113 | static void gen_eob(DisasContext *s); | |
14ce26e7 FB |
114 | static void gen_jmp(DisasContext *s, target_ulong eip); |
115 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); | |
2c0262af FB |
116 | |
117 | /* i386 arith/logic operations */ | |
118 | enum { | |
5fafdf24 TS |
119 | OP_ADDL, |
120 | OP_ORL, | |
121 | OP_ADCL, | |
2c0262af | 122 | OP_SBBL, |
5fafdf24 TS |
123 | OP_ANDL, |
124 | OP_SUBL, | |
125 | OP_XORL, | |
2c0262af FB |
126 | OP_CMPL, |
127 | }; | |
128 | ||
129 | /* i386 shift ops */ | |
130 | enum { | |
5fafdf24 TS |
131 | OP_ROL, |
132 | OP_ROR, | |
133 | OP_RCL, | |
134 | OP_RCR, | |
135 | OP_SHL, | |
136 | OP_SHR, | |
2c0262af FB |
137 | OP_SHL1, /* undocumented */ |
138 | OP_SAR = 7, | |
139 | }; | |
140 | ||
8e1c85e3 FB |
141 | enum { |
142 | JCC_O, | |
143 | JCC_B, | |
144 | JCC_Z, | |
145 | JCC_BE, | |
146 | JCC_S, | |
147 | JCC_P, | |
148 | JCC_L, | |
149 | JCC_LE, | |
150 | }; | |
151 | ||
2c0262af FB |
152 | /* operand size */ |
153 | enum { | |
154 | OT_BYTE = 0, | |
155 | OT_WORD, | |
5fafdf24 | 156 | OT_LONG, |
2c0262af FB |
157 | OT_QUAD, |
158 | }; | |
159 | ||
160 | enum { | |
161 | /* I386 int registers */ | |
162 | OR_EAX, /* MUST be even numbered */ | |
163 | OR_ECX, | |
164 | OR_EDX, | |
165 | OR_EBX, | |
166 | OR_ESP, | |
167 | OR_EBP, | |
168 | OR_ESI, | |
169 | OR_EDI, | |
14ce26e7 FB |
170 | |
171 | OR_TMP0 = 16, /* temporary operand register */ | |
2c0262af FB |
172 | OR_TMP1, |
173 | OR_A0, /* temporary register used when doing address evaluation */ | |
2c0262af FB |
174 | }; |
175 | ||
57fec1fe FB |
176 | static inline void gen_op_movl_T0_0(void) |
177 | { | |
178 | tcg_gen_movi_tl(cpu_T[0], 0); | |
179 | } | |
180 | ||
181 | static inline void gen_op_movl_T0_im(int32_t val) | |
182 | { | |
183 | tcg_gen_movi_tl(cpu_T[0], val); | |
184 | } | |
185 | ||
186 | static inline void gen_op_movl_T0_imu(uint32_t val) | |
187 | { | |
188 | tcg_gen_movi_tl(cpu_T[0], val); | |
189 | } | |
190 | ||
191 | static inline void gen_op_movl_T1_im(int32_t val) | |
192 | { | |
193 | tcg_gen_movi_tl(cpu_T[1], val); | |
194 | } | |
195 | ||
196 | static inline void gen_op_movl_T1_imu(uint32_t val) | |
197 | { | |
198 | tcg_gen_movi_tl(cpu_T[1], val); | |
199 | } | |
200 | ||
201 | static inline void gen_op_movl_A0_im(uint32_t val) | |
202 | { | |
203 | tcg_gen_movi_tl(cpu_A0, val); | |
204 | } | |
205 | ||
206 | #ifdef TARGET_X86_64 | |
207 | static inline void gen_op_movq_A0_im(int64_t val) | |
208 | { | |
209 | tcg_gen_movi_tl(cpu_A0, val); | |
210 | } | |
211 | #endif | |
212 | ||
213 | static inline void gen_movtl_T0_im(target_ulong val) | |
214 | { | |
215 | tcg_gen_movi_tl(cpu_T[0], val); | |
216 | } | |
217 | ||
218 | static inline void gen_movtl_T1_im(target_ulong val) | |
219 | { | |
220 | tcg_gen_movi_tl(cpu_T[1], val); | |
221 | } | |
222 | ||
223 | static inline void gen_op_andl_T0_ffff(void) | |
224 | { | |
225 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
226 | } | |
227 | ||
228 | static inline void gen_op_andl_T0_im(uint32_t val) | |
229 | { | |
230 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); | |
231 | } | |
232 | ||
233 | static inline void gen_op_movl_T0_T1(void) | |
234 | { | |
235 | tcg_gen_mov_tl(cpu_T[0], cpu_T[1]); | |
236 | } | |
237 | ||
238 | static inline void gen_op_andl_A0_ffff(void) | |
239 | { | |
240 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff); | |
241 | } | |
242 | ||
14ce26e7 FB |
243 | #ifdef TARGET_X86_64 |
244 | ||
245 | #define NB_OP_SIZES 4 | |
246 | ||
14ce26e7 FB |
247 | #else /* !TARGET_X86_64 */ |
248 | ||
249 | #define NB_OP_SIZES 3 | |
250 | ||
14ce26e7 FB |
251 | #endif /* !TARGET_X86_64 */ |
252 | ||
e2542fe2 | 253 | #if defined(HOST_WORDS_BIGENDIAN) |
57fec1fe FB |
254 | #define REG_B_OFFSET (sizeof(target_ulong) - 1) |
255 | #define REG_H_OFFSET (sizeof(target_ulong) - 2) | |
256 | #define REG_W_OFFSET (sizeof(target_ulong) - 2) | |
257 | #define REG_L_OFFSET (sizeof(target_ulong) - 4) | |
258 | #define REG_LH_OFFSET (sizeof(target_ulong) - 8) | |
14ce26e7 | 259 | #else |
57fec1fe FB |
260 | #define REG_B_OFFSET 0 |
261 | #define REG_H_OFFSET 1 | |
262 | #define REG_W_OFFSET 0 | |
263 | #define REG_L_OFFSET 0 | |
264 | #define REG_LH_OFFSET 4 | |
14ce26e7 | 265 | #endif |
57fec1fe | 266 | |
96d7073f PM |
267 | /* In instruction encodings for byte register accesses the |
268 | * register number usually indicates "low 8 bits of register N"; | |
269 | * however there are some special cases where N 4..7 indicates | |
270 | * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return | |
271 | * true for this special case, false otherwise. | |
272 | */ | |
273 | static inline bool byte_reg_is_xH(int reg) | |
274 | { | |
275 | if (reg < 4) { | |
276 | return false; | |
277 | } | |
278 | #ifdef TARGET_X86_64 | |
279 | if (reg >= 8 || x86_64_hregs) { | |
280 | return false; | |
281 | } | |
282 | #endif | |
283 | return true; | |
284 | } | |
285 | ||
1e4840bf | 286 | static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) |
57fec1fe FB |
287 | { |
288 | switch(ot) { | |
289 | case OT_BYTE: | |
96d7073f | 290 | if (!byte_reg_is_xH(reg)) { |
c832e3de | 291 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); |
57fec1fe | 292 | } else { |
c832e3de | 293 | tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); |
57fec1fe FB |
294 | } |
295 | break; | |
296 | case OT_WORD: | |
c832e3de | 297 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16); |
57fec1fe | 298 | break; |
cc739bb0 | 299 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 300 | case OT_LONG: |
cc739bb0 LD |
301 | /* For x86_64, this sets the higher half of register to zero. |
302 | For i386, this is equivalent to a mov. */ | |
303 | tcg_gen_ext32u_tl(cpu_regs[reg], t0); | |
57fec1fe | 304 | break; |
cc739bb0 | 305 | #ifdef TARGET_X86_64 |
57fec1fe | 306 | case OT_QUAD: |
cc739bb0 | 307 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
57fec1fe | 308 | break; |
14ce26e7 | 309 | #endif |
57fec1fe FB |
310 | } |
311 | } | |
2c0262af | 312 | |
57fec1fe FB |
313 | static inline void gen_op_mov_reg_T0(int ot, int reg) |
314 | { | |
1e4840bf | 315 | gen_op_mov_reg_v(ot, reg, cpu_T[0]); |
57fec1fe FB |
316 | } |
317 | ||
318 | static inline void gen_op_mov_reg_T1(int ot, int reg) | |
319 | { | |
1e4840bf | 320 | gen_op_mov_reg_v(ot, reg, cpu_T[1]); |
57fec1fe FB |
321 | } |
322 | ||
323 | static inline void gen_op_mov_reg_A0(int size, int reg) | |
324 | { | |
325 | switch(size) { | |
326 | case 0: | |
c832e3de | 327 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); |
57fec1fe | 328 | break; |
cc739bb0 | 329 | default: /* XXX this shouldn't be reached; abort? */ |
57fec1fe | 330 | case 1: |
cc739bb0 LD |
331 | /* For x86_64, this sets the higher half of register to zero. |
332 | For i386, this is equivalent to a mov. */ | |
333 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); | |
57fec1fe | 334 | break; |
cc739bb0 | 335 | #ifdef TARGET_X86_64 |
57fec1fe | 336 | case 2: |
cc739bb0 | 337 | tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); |
57fec1fe | 338 | break; |
14ce26e7 | 339 | #endif |
57fec1fe FB |
340 | } |
341 | } | |
342 | ||
1e4840bf | 343 | static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) |
57fec1fe | 344 | { |
96d7073f PM |
345 | if (ot == OT_BYTE && byte_reg_is_xH(reg)) { |
346 | tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); | |
347 | tcg_gen_ext8u_tl(t0, t0); | |
348 | } else { | |
cc739bb0 | 349 | tcg_gen_mov_tl(t0, cpu_regs[reg]); |
57fec1fe FB |
350 | } |
351 | } | |
352 | ||
1e4840bf FB |
353 | static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) |
354 | { | |
355 | gen_op_mov_v_reg(ot, cpu_T[t_index], reg); | |
356 | } | |
357 | ||
57fec1fe FB |
358 | static inline void gen_op_movl_A0_reg(int reg) |
359 | { | |
cc739bb0 | 360 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
361 | } |
362 | ||
363 | static inline void gen_op_addl_A0_im(int32_t val) | |
364 | { | |
365 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
14ce26e7 | 366 | #ifdef TARGET_X86_64 |
57fec1fe | 367 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); |
14ce26e7 | 368 | #endif |
57fec1fe | 369 | } |
2c0262af | 370 | |
14ce26e7 | 371 | #ifdef TARGET_X86_64 |
57fec1fe FB |
372 | static inline void gen_op_addq_A0_im(int64_t val) |
373 | { | |
374 | tcg_gen_addi_tl(cpu_A0, cpu_A0, val); | |
375 | } | |
14ce26e7 | 376 | #endif |
57fec1fe FB |
377 | |
378 | static void gen_add_A0_im(DisasContext *s, int val) | |
379 | { | |
380 | #ifdef TARGET_X86_64 | |
381 | if (CODE64(s)) | |
382 | gen_op_addq_A0_im(val); | |
383 | else | |
384 | #endif | |
385 | gen_op_addl_A0_im(val); | |
386 | } | |
2c0262af | 387 | |
57fec1fe | 388 | static inline void gen_op_addl_T0_T1(void) |
2c0262af | 389 | { |
57fec1fe FB |
390 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
391 | } | |
392 | ||
393 | static inline void gen_op_jmp_T0(void) | |
394 | { | |
317ac620 | 395 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip)); |
57fec1fe FB |
396 | } |
397 | ||
6e0d8677 | 398 | static inline void gen_op_add_reg_im(int size, int reg, int32_t val) |
57fec1fe | 399 | { |
6e0d8677 FB |
400 | switch(size) { |
401 | case 0: | |
cc739bb0 | 402 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
c832e3de | 403 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 FB |
404 | break; |
405 | case 1: | |
cc739bb0 LD |
406 | tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val); |
407 | /* For x86_64, this sets the higher half of register to zero. | |
408 | For i386, this is equivalent to a nop. */ | |
409 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
410 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 FB |
411 | break; |
412 | #ifdef TARGET_X86_64 | |
413 | case 2: | |
cc739bb0 | 414 | tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val); |
6e0d8677 FB |
415 | break; |
416 | #endif | |
417 | } | |
57fec1fe FB |
418 | } |
419 | ||
6e0d8677 | 420 | static inline void gen_op_add_reg_T0(int size, int reg) |
57fec1fe | 421 | { |
6e0d8677 FB |
422 | switch(size) { |
423 | case 0: | |
cc739bb0 | 424 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
c832e3de | 425 | tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16); |
6e0d8677 FB |
426 | break; |
427 | case 1: | |
cc739bb0 LD |
428 | tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]); |
429 | /* For x86_64, this sets the higher half of register to zero. | |
430 | For i386, this is equivalent to a nop. */ | |
431 | tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0); | |
432 | tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0); | |
6e0d8677 | 433 | break; |
14ce26e7 | 434 | #ifdef TARGET_X86_64 |
6e0d8677 | 435 | case 2: |
cc739bb0 | 436 | tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]); |
6e0d8677 | 437 | break; |
14ce26e7 | 438 | #endif |
6e0d8677 FB |
439 | } |
440 | } | |
57fec1fe FB |
441 | |
442 | static inline void gen_op_set_cc_op(int32_t val) | |
443 | { | |
b6abf97d | 444 | tcg_gen_movi_i32(cpu_cc_op, val); |
57fec1fe FB |
445 | } |
446 | ||
447 | static inline void gen_op_addl_A0_reg_sN(int shift, int reg) | |
448 | { | |
cc739bb0 LD |
449 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
450 | if (shift != 0) | |
57fec1fe FB |
451 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
452 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
cc739bb0 LD |
453 | /* For x86_64, this sets the higher half of register to zero. |
454 | For i386, this is equivalent to a nop. */ | |
455 | tcg_gen_ext32u_tl(cpu_A0, cpu_A0); | |
57fec1fe | 456 | } |
2c0262af | 457 | |
57fec1fe FB |
458 | static inline void gen_op_movl_A0_seg(int reg) |
459 | { | |
317ac620 | 460 | tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET); |
57fec1fe | 461 | } |
2c0262af | 462 | |
7162ab21 | 463 | static inline void gen_op_addl_A0_seg(DisasContext *s, int reg) |
57fec1fe | 464 | { |
317ac620 | 465 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 466 | #ifdef TARGET_X86_64 |
7162ab21 VC |
467 | if (CODE64(s)) { |
468 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
469 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
470 | } else { | |
471 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
472 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
473 | } | |
474 | #else | |
475 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe FB |
476 | #endif |
477 | } | |
2c0262af | 478 | |
14ce26e7 | 479 | #ifdef TARGET_X86_64 |
57fec1fe FB |
480 | static inline void gen_op_movq_A0_seg(int reg) |
481 | { | |
317ac620 | 482 | tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe | 483 | } |
14ce26e7 | 484 | |
57fec1fe FB |
485 | static inline void gen_op_addq_A0_seg(int reg) |
486 | { | |
317ac620 | 487 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base)); |
57fec1fe FB |
488 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); |
489 | } | |
490 | ||
491 | static inline void gen_op_movq_A0_reg(int reg) | |
492 | { | |
cc739bb0 | 493 | tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]); |
57fec1fe FB |
494 | } |
495 | ||
496 | static inline void gen_op_addq_A0_reg_sN(int shift, int reg) | |
497 | { | |
cc739bb0 LD |
498 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]); |
499 | if (shift != 0) | |
57fec1fe FB |
500 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); |
501 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
502 | } | |
14ce26e7 FB |
503 | #endif |
504 | ||
57fec1fe FB |
505 | static inline void gen_op_lds_T0_A0(int idx) |
506 | { | |
507 | int mem_index = (idx >> 2) - 1; | |
508 | switch(idx & 3) { | |
509 | case 0: | |
510 | tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); | |
511 | break; | |
512 | case 1: | |
513 | tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index); | |
514 | break; | |
515 | default: | |
516 | case 2: | |
517 | tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index); | |
518 | break; | |
519 | } | |
520 | } | |
2c0262af | 521 | |
1e4840bf | 522 | static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) |
57fec1fe FB |
523 | { |
524 | int mem_index = (idx >> 2) - 1; | |
525 | switch(idx & 3) { | |
526 | case 0: | |
1e4840bf | 527 | tcg_gen_qemu_ld8u(t0, a0, mem_index); |
57fec1fe FB |
528 | break; |
529 | case 1: | |
1e4840bf | 530 | tcg_gen_qemu_ld16u(t0, a0, mem_index); |
57fec1fe FB |
531 | break; |
532 | case 2: | |
1e4840bf | 533 | tcg_gen_qemu_ld32u(t0, a0, mem_index); |
57fec1fe FB |
534 | break; |
535 | default: | |
536 | case 3: | |
a7812ae4 PB |
537 | /* Should never happen on 32-bit targets. */ |
538 | #ifdef TARGET_X86_64 | |
1e4840bf | 539 | tcg_gen_qemu_ld64(t0, a0, mem_index); |
a7812ae4 | 540 | #endif |
57fec1fe FB |
541 | break; |
542 | } | |
543 | } | |
2c0262af | 544 | |
1e4840bf FB |
545 | /* XXX: always use ldu or lds */ |
546 | static inline void gen_op_ld_T0_A0(int idx) | |
547 | { | |
548 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); | |
549 | } | |
550 | ||
57fec1fe FB |
551 | static inline void gen_op_ldu_T0_A0(int idx) |
552 | { | |
1e4840bf | 553 | gen_op_ld_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 554 | } |
2c0262af | 555 | |
57fec1fe | 556 | static inline void gen_op_ld_T1_A0(int idx) |
1e4840bf FB |
557 | { |
558 | gen_op_ld_v(idx, cpu_T[1], cpu_A0); | |
559 | } | |
560 | ||
561 | static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) | |
57fec1fe FB |
562 | { |
563 | int mem_index = (idx >> 2) - 1; | |
564 | switch(idx & 3) { | |
565 | case 0: | |
1e4840bf | 566 | tcg_gen_qemu_st8(t0, a0, mem_index); |
57fec1fe FB |
567 | break; |
568 | case 1: | |
1e4840bf | 569 | tcg_gen_qemu_st16(t0, a0, mem_index); |
57fec1fe FB |
570 | break; |
571 | case 2: | |
1e4840bf | 572 | tcg_gen_qemu_st32(t0, a0, mem_index); |
57fec1fe FB |
573 | break; |
574 | default: | |
575 | case 3: | |
a7812ae4 PB |
576 | /* Should never happen on 32-bit targets. */ |
577 | #ifdef TARGET_X86_64 | |
1e4840bf | 578 | tcg_gen_qemu_st64(t0, a0, mem_index); |
a7812ae4 | 579 | #endif |
57fec1fe FB |
580 | break; |
581 | } | |
582 | } | |
4f31916f | 583 | |
57fec1fe FB |
584 | static inline void gen_op_st_T0_A0(int idx) |
585 | { | |
1e4840bf | 586 | gen_op_st_v(idx, cpu_T[0], cpu_A0); |
57fec1fe | 587 | } |
4f31916f | 588 | |
57fec1fe FB |
589 | static inline void gen_op_st_T1_A0(int idx) |
590 | { | |
1e4840bf | 591 | gen_op_st_v(idx, cpu_T[1], cpu_A0); |
57fec1fe | 592 | } |
4f31916f | 593 | |
14ce26e7 FB |
594 | static inline void gen_jmp_im(target_ulong pc) |
595 | { | |
57fec1fe | 596 | tcg_gen_movi_tl(cpu_tmp0, pc); |
317ac620 | 597 | tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip)); |
14ce26e7 FB |
598 | } |
599 | ||
2c0262af FB |
600 | static inline void gen_string_movl_A0_ESI(DisasContext *s) |
601 | { | |
602 | int override; | |
603 | ||
604 | override = s->override; | |
14ce26e7 FB |
605 | #ifdef TARGET_X86_64 |
606 | if (s->aflag == 2) { | |
607 | if (override >= 0) { | |
57fec1fe FB |
608 | gen_op_movq_A0_seg(override); |
609 | gen_op_addq_A0_reg_sN(0, R_ESI); | |
14ce26e7 | 610 | } else { |
57fec1fe | 611 | gen_op_movq_A0_reg(R_ESI); |
14ce26e7 FB |
612 | } |
613 | } else | |
614 | #endif | |
2c0262af FB |
615 | if (s->aflag) { |
616 | /* 32 bit address */ | |
617 | if (s->addseg && override < 0) | |
618 | override = R_DS; | |
619 | if (override >= 0) { | |
57fec1fe FB |
620 | gen_op_movl_A0_seg(override); |
621 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af | 622 | } else { |
57fec1fe | 623 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
624 | } |
625 | } else { | |
626 | /* 16 address, always override */ | |
627 | if (override < 0) | |
628 | override = R_DS; | |
57fec1fe | 629 | gen_op_movl_A0_reg(R_ESI); |
2c0262af | 630 | gen_op_andl_A0_ffff(); |
7162ab21 | 631 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
632 | } |
633 | } | |
634 | ||
635 | static inline void gen_string_movl_A0_EDI(DisasContext *s) | |
636 | { | |
14ce26e7 FB |
637 | #ifdef TARGET_X86_64 |
638 | if (s->aflag == 2) { | |
57fec1fe | 639 | gen_op_movq_A0_reg(R_EDI); |
14ce26e7 FB |
640 | } else |
641 | #endif | |
2c0262af FB |
642 | if (s->aflag) { |
643 | if (s->addseg) { | |
57fec1fe FB |
644 | gen_op_movl_A0_seg(R_ES); |
645 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af | 646 | } else { |
57fec1fe | 647 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
648 | } |
649 | } else { | |
57fec1fe | 650 | gen_op_movl_A0_reg(R_EDI); |
2c0262af | 651 | gen_op_andl_A0_ffff(); |
7162ab21 | 652 | gen_op_addl_A0_seg(s, R_ES); |
2c0262af FB |
653 | } |
654 | } | |
655 | ||
6e0d8677 FB |
656 | static inline void gen_op_movl_T0_Dshift(int ot) |
657 | { | |
317ac620 | 658 | tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df)); |
6e0d8677 | 659 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); |
2c0262af FB |
660 | }; |
661 | ||
6e0d8677 FB |
662 | static void gen_extu(int ot, TCGv reg) |
663 | { | |
664 | switch(ot) { | |
665 | case OT_BYTE: | |
666 | tcg_gen_ext8u_tl(reg, reg); | |
667 | break; | |
668 | case OT_WORD: | |
669 | tcg_gen_ext16u_tl(reg, reg); | |
670 | break; | |
671 | case OT_LONG: | |
672 | tcg_gen_ext32u_tl(reg, reg); | |
673 | break; | |
674 | default: | |
675 | break; | |
676 | } | |
677 | } | |
3b46e624 | 678 | |
6e0d8677 FB |
679 | static void gen_exts(int ot, TCGv reg) |
680 | { | |
681 | switch(ot) { | |
682 | case OT_BYTE: | |
683 | tcg_gen_ext8s_tl(reg, reg); | |
684 | break; | |
685 | case OT_WORD: | |
686 | tcg_gen_ext16s_tl(reg, reg); | |
687 | break; | |
688 | case OT_LONG: | |
689 | tcg_gen_ext32s_tl(reg, reg); | |
690 | break; | |
691 | default: | |
692 | break; | |
693 | } | |
694 | } | |
2c0262af | 695 | |
6e0d8677 FB |
696 | static inline void gen_op_jnz_ecx(int size, int label1) |
697 | { | |
cc739bb0 | 698 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 699 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 700 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); |
6e0d8677 FB |
701 | } |
702 | ||
703 | static inline void gen_op_jz_ecx(int size, int label1) | |
704 | { | |
cc739bb0 | 705 | tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]); |
6e0d8677 | 706 | gen_extu(size + 1, cpu_tmp0); |
cb63669a | 707 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
6e0d8677 | 708 | } |
2c0262af | 709 | |
a7812ae4 PB |
710 | static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) |
711 | { | |
712 | switch (ot) { | |
713 | case 0: gen_helper_inb(v, n); break; | |
714 | case 1: gen_helper_inw(v, n); break; | |
715 | case 2: gen_helper_inl(v, n); break; | |
716 | } | |
2c0262af | 717 | |
a7812ae4 | 718 | } |
2c0262af | 719 | |
a7812ae4 PB |
720 | static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) |
721 | { | |
722 | switch (ot) { | |
723 | case 0: gen_helper_outb(v, n); break; | |
724 | case 1: gen_helper_outw(v, n); break; | |
725 | case 2: gen_helper_outl(v, n); break; | |
726 | } | |
727 | ||
728 | } | |
f115e911 | 729 | |
b8b6a50b FB |
730 | static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, |
731 | uint32_t svm_flags) | |
f115e911 | 732 | { |
b8b6a50b FB |
733 | int state_saved; |
734 | target_ulong next_eip; | |
735 | ||
736 | state_saved = 0; | |
f115e911 FB |
737 | if (s->pe && (s->cpl > s->iopl || s->vm86)) { |
738 | if (s->cc_op != CC_OP_DYNAMIC) | |
739 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 740 | gen_jmp_im(cur_eip); |
b8b6a50b | 741 | state_saved = 1; |
b6abf97d | 742 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 743 | switch (ot) { |
4a7443be BS |
744 | case 0: |
745 | gen_helper_check_iob(cpu_env, cpu_tmp2_i32); | |
746 | break; | |
747 | case 1: | |
748 | gen_helper_check_iow(cpu_env, cpu_tmp2_i32); | |
749 | break; | |
750 | case 2: | |
751 | gen_helper_check_iol(cpu_env, cpu_tmp2_i32); | |
752 | break; | |
a7812ae4 | 753 | } |
b8b6a50b | 754 | } |
872929aa | 755 | if(s->flags & HF_SVMI_MASK) { |
b8b6a50b FB |
756 | if (!state_saved) { |
757 | if (s->cc_op != CC_OP_DYNAMIC) | |
758 | gen_op_set_cc_op(s->cc_op); | |
759 | gen_jmp_im(cur_eip); | |
b8b6a50b FB |
760 | } |
761 | svm_flags |= (1 << (4 + ot)); | |
762 | next_eip = s->pc - s->cs_base; | |
b6abf97d | 763 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
052e80d5 BS |
764 | gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32, |
765 | tcg_const_i32(svm_flags), | |
a7812ae4 | 766 | tcg_const_i32(next_eip - cur_eip)); |
f115e911 FB |
767 | } |
768 | } | |
769 | ||
2c0262af FB |
770 | static inline void gen_movs(DisasContext *s, int ot) |
771 | { | |
772 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 773 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 774 | gen_string_movl_A0_EDI(s); |
57fec1fe | 775 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
776 | gen_op_movl_T0_Dshift(ot); |
777 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
778 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
779 | } |
780 | ||
781 | static inline void gen_update_cc_op(DisasContext *s) | |
782 | { | |
783 | if (s->cc_op != CC_OP_DYNAMIC) { | |
784 | gen_op_set_cc_op(s->cc_op); | |
785 | s->cc_op = CC_OP_DYNAMIC; | |
786 | } | |
787 | } | |
788 | ||
b6abf97d FB |
789 | static void gen_op_update1_cc(void) |
790 | { | |
791 | tcg_gen_discard_tl(cpu_cc_src); | |
792 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
793 | } | |
794 | ||
795 | static void gen_op_update2_cc(void) | |
796 | { | |
797 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
798 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
799 | } | |
800 | ||
801 | static inline void gen_op_cmpl_T0_T1_cc(void) | |
802 | { | |
803 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
804 | tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
805 | } | |
806 | ||
807 | static inline void gen_op_testl_T0_T1_cc(void) | |
808 | { | |
809 | tcg_gen_discard_tl(cpu_cc_src); | |
810 | tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); | |
811 | } | |
812 | ||
813 | static void gen_op_update_neg_cc(void) | |
814 | { | |
815 | tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); | |
816 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
817 | } | |
818 | ||
8e1c85e3 FB |
819 | /* compute eflags.C to reg */ |
820 | static void gen_compute_eflags_c(TCGv reg) | |
821 | { | |
f0967a1a | 822 | gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
8e1c85e3 FB |
823 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
824 | } | |
825 | ||
826 | /* compute all eflags to cc_src */ | |
827 | static void gen_compute_eflags(TCGv reg) | |
828 | { | |
f0967a1a | 829 | gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op); |
8e1c85e3 FB |
830 | tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
831 | } | |
832 | ||
1e4840bf | 833 | static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |
8e1c85e3 | 834 | { |
1e4840bf FB |
835 | if (s->cc_op != CC_OP_DYNAMIC) |
836 | gen_op_set_cc_op(s->cc_op); | |
837 | switch(jcc_op) { | |
8e1c85e3 FB |
838 | case JCC_O: |
839 | gen_compute_eflags(cpu_T[0]); | |
840 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); | |
841 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
842 | break; | |
843 | case JCC_B: | |
844 | gen_compute_eflags_c(cpu_T[0]); | |
845 | break; | |
846 | case JCC_Z: | |
847 | gen_compute_eflags(cpu_T[0]); | |
848 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); | |
849 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
850 | break; | |
851 | case JCC_BE: | |
852 | gen_compute_eflags(cpu_tmp0); | |
853 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); | |
854 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
855 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
856 | break; | |
857 | case JCC_S: | |
858 | gen_compute_eflags(cpu_T[0]); | |
859 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); | |
860 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
861 | break; | |
862 | case JCC_P: | |
863 | gen_compute_eflags(cpu_T[0]); | |
864 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); | |
865 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
866 | break; | |
867 | case JCC_L: | |
868 | gen_compute_eflags(cpu_tmp0); | |
869 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ | |
870 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ | |
871 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
872 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
873 | break; | |
874 | default: | |
875 | case JCC_LE: | |
876 | gen_compute_eflags(cpu_tmp0); | |
877 | tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ | |
878 | tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ | |
879 | tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ | |
880 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
881 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
882 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); | |
883 | break; | |
884 | } | |
885 | } | |
886 | ||
887 | /* return true if setcc_slow is not needed (WARNING: must be kept in | |
888 | sync with gen_jcc1) */ | |
889 | static int is_fast_jcc_case(DisasContext *s, int b) | |
890 | { | |
891 | int jcc_op; | |
892 | jcc_op = (b >> 1) & 7; | |
893 | switch(s->cc_op) { | |
894 | /* we optimize the cmp/jcc case */ | |
895 | case CC_OP_SUBB: | |
896 | case CC_OP_SUBW: | |
897 | case CC_OP_SUBL: | |
898 | case CC_OP_SUBQ: | |
899 | if (jcc_op == JCC_O || jcc_op == JCC_P) | |
900 | goto slow_jcc; | |
901 | break; | |
902 | ||
903 | /* some jumps are easy to compute */ | |
904 | case CC_OP_ADDB: | |
905 | case CC_OP_ADDW: | |
906 | case CC_OP_ADDL: | |
907 | case CC_OP_ADDQ: | |
908 | ||
909 | case CC_OP_LOGICB: | |
910 | case CC_OP_LOGICW: | |
911 | case CC_OP_LOGICL: | |
912 | case CC_OP_LOGICQ: | |
913 | ||
914 | case CC_OP_INCB: | |
915 | case CC_OP_INCW: | |
916 | case CC_OP_INCL: | |
917 | case CC_OP_INCQ: | |
918 | ||
919 | case CC_OP_DECB: | |
920 | case CC_OP_DECW: | |
921 | case CC_OP_DECL: | |
922 | case CC_OP_DECQ: | |
923 | ||
924 | case CC_OP_SHLB: | |
925 | case CC_OP_SHLW: | |
926 | case CC_OP_SHLL: | |
927 | case CC_OP_SHLQ: | |
928 | if (jcc_op != JCC_Z && jcc_op != JCC_S) | |
929 | goto slow_jcc; | |
930 | break; | |
931 | default: | |
932 | slow_jcc: | |
933 | return 0; | |
934 | } | |
935 | return 1; | |
936 | } | |
937 | ||
938 | /* generate a conditional jump to label 'l1' according to jump opcode | |
939 | value 'b'. In the fast case, T0 is guaranted not to be used. */ | |
940 | static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) | |
941 | { | |
942 | int inv, jcc_op, size, cond; | |
943 | TCGv t0; | |
944 | ||
945 | inv = b & 1; | |
946 | jcc_op = (b >> 1) & 7; | |
947 | ||
948 | switch(cc_op) { | |
949 | /* we optimize the cmp/jcc case */ | |
950 | case CC_OP_SUBB: | |
951 | case CC_OP_SUBW: | |
952 | case CC_OP_SUBL: | |
953 | case CC_OP_SUBQ: | |
954 | ||
955 | size = cc_op - CC_OP_SUBB; | |
956 | switch(jcc_op) { | |
957 | case JCC_Z: | |
958 | fast_jcc_z: | |
959 | switch(size) { | |
960 | case 0: | |
961 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff); | |
962 | t0 = cpu_tmp0; | |
963 | break; | |
964 | case 1: | |
965 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff); | |
966 | t0 = cpu_tmp0; | |
967 | break; | |
968 | #ifdef TARGET_X86_64 | |
969 | case 2: | |
970 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff); | |
971 | t0 = cpu_tmp0; | |
972 | break; | |
973 | #endif | |
974 | default: | |
975 | t0 = cpu_cc_dst; | |
976 | break; | |
977 | } | |
cb63669a | 978 | tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); |
8e1c85e3 FB |
979 | break; |
980 | case JCC_S: | |
981 | fast_jcc_s: | |
982 | switch(size) { | |
983 | case 0: | |
984 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); | |
cb63669a PB |
985 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
986 | 0, l1); | |
8e1c85e3 FB |
987 | break; |
988 | case 1: | |
989 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); | |
cb63669a PB |
990 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
991 | 0, l1); | |
8e1c85e3 FB |
992 | break; |
993 | #ifdef TARGET_X86_64 | |
994 | case 2: | |
995 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); | |
cb63669a PB |
996 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, |
997 | 0, l1); | |
8e1c85e3 FB |
998 | break; |
999 | #endif | |
1000 | default: | |
cb63669a PB |
1001 | tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, |
1002 | 0, l1); | |
8e1c85e3 FB |
1003 | break; |
1004 | } | |
1005 | break; | |
1006 | ||
1007 | case JCC_B: | |
1008 | cond = inv ? TCG_COND_GEU : TCG_COND_LTU; | |
1009 | goto fast_jcc_b; | |
1010 | case JCC_BE: | |
1011 | cond = inv ? TCG_COND_GTU : TCG_COND_LEU; | |
1012 | fast_jcc_b: | |
1013 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
1014 | switch(size) { | |
1015 | case 0: | |
1016 | t0 = cpu_tmp0; | |
1017 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff); | |
1018 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xff); | |
1019 | break; | |
1020 | case 1: | |
1021 | t0 = cpu_tmp0; | |
1022 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff); | |
1023 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff); | |
1024 | break; | |
1025 | #ifdef TARGET_X86_64 | |
1026 | case 2: | |
1027 | t0 = cpu_tmp0; | |
1028 | tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff); | |
1029 | tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff); | |
1030 | break; | |
1031 | #endif | |
1032 | default: | |
1033 | t0 = cpu_cc_src; | |
1034 | break; | |
1035 | } | |
1036 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); | |
1037 | break; | |
1038 | ||
1039 | case JCC_L: | |
1040 | cond = inv ? TCG_COND_GE : TCG_COND_LT; | |
1041 | goto fast_jcc_l; | |
1042 | case JCC_LE: | |
1043 | cond = inv ? TCG_COND_GT : TCG_COND_LE; | |
1044 | fast_jcc_l: | |
1045 | tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); | |
1046 | switch(size) { | |
1047 | case 0: | |
1048 | t0 = cpu_tmp0; | |
1049 | tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4); | |
1050 | tcg_gen_ext8s_tl(t0, cpu_cc_src); | |
1051 | break; | |
1052 | case 1: | |
1053 | t0 = cpu_tmp0; | |
1054 | tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4); | |
1055 | tcg_gen_ext16s_tl(t0, cpu_cc_src); | |
1056 | break; | |
1057 | #ifdef TARGET_X86_64 | |
1058 | case 2: | |
1059 | t0 = cpu_tmp0; | |
1060 | tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4); | |
1061 | tcg_gen_ext32s_tl(t0, cpu_cc_src); | |
1062 | break; | |
1063 | #endif | |
1064 | default: | |
1065 | t0 = cpu_cc_src; | |
1066 | break; | |
1067 | } | |
1068 | tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); | |
1069 | break; | |
1070 | ||
1071 | default: | |
1072 | goto slow_jcc; | |
1073 | } | |
1074 | break; | |
1075 | ||
1076 | /* some jumps are easy to compute */ | |
1077 | case CC_OP_ADDB: | |
1078 | case CC_OP_ADDW: | |
1079 | case CC_OP_ADDL: | |
1080 | case CC_OP_ADDQ: | |
1081 | ||
1082 | case CC_OP_ADCB: | |
1083 | case CC_OP_ADCW: | |
1084 | case CC_OP_ADCL: | |
1085 | case CC_OP_ADCQ: | |
1086 | ||
1087 | case CC_OP_SBBB: | |
1088 | case CC_OP_SBBW: | |
1089 | case CC_OP_SBBL: | |
1090 | case CC_OP_SBBQ: | |
1091 | ||
1092 | case CC_OP_LOGICB: | |
1093 | case CC_OP_LOGICW: | |
1094 | case CC_OP_LOGICL: | |
1095 | case CC_OP_LOGICQ: | |
1096 | ||
1097 | case CC_OP_INCB: | |
1098 | case CC_OP_INCW: | |
1099 | case CC_OP_INCL: | |
1100 | case CC_OP_INCQ: | |
1101 | ||
1102 | case CC_OP_DECB: | |
1103 | case CC_OP_DECW: | |
1104 | case CC_OP_DECL: | |
1105 | case CC_OP_DECQ: | |
1106 | ||
1107 | case CC_OP_SHLB: | |
1108 | case CC_OP_SHLW: | |
1109 | case CC_OP_SHLL: | |
1110 | case CC_OP_SHLQ: | |
1111 | ||
1112 | case CC_OP_SARB: | |
1113 | case CC_OP_SARW: | |
1114 | case CC_OP_SARL: | |
1115 | case CC_OP_SARQ: | |
1116 | switch(jcc_op) { | |
1117 | case JCC_Z: | |
1118 | size = (cc_op - CC_OP_ADDB) & 3; | |
1119 | goto fast_jcc_z; | |
1120 | case JCC_S: | |
1121 | size = (cc_op - CC_OP_ADDB) & 3; | |
1122 | goto fast_jcc_s; | |
1123 | default: | |
1124 | goto slow_jcc; | |
1125 | } | |
1126 | break; | |
1127 | default: | |
1128 | slow_jcc: | |
1e4840bf | 1129 | gen_setcc_slow_T0(s, jcc_op); |
cb63669a PB |
1130 | tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, |
1131 | cpu_T[0], 0, l1); | |
8e1c85e3 FB |
1132 | break; |
1133 | } | |
1134 | } | |
1135 | ||
14ce26e7 FB |
1136 | /* XXX: does not work with gdbstub "ice" single step - not a |
1137 | serious problem */ | |
1138 | static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) | |
2c0262af | 1139 | { |
14ce26e7 FB |
1140 | int l1, l2; |
1141 | ||
1142 | l1 = gen_new_label(); | |
1143 | l2 = gen_new_label(); | |
6e0d8677 | 1144 | gen_op_jnz_ecx(s->aflag, l1); |
14ce26e7 FB |
1145 | gen_set_label(l2); |
1146 | gen_jmp_tb(s, next_eip, 1); | |
1147 | gen_set_label(l1); | |
1148 | return l2; | |
2c0262af FB |
1149 | } |
1150 | ||
1151 | static inline void gen_stos(DisasContext *s, int ot) | |
1152 | { | |
57fec1fe | 1153 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1154 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1155 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1156 | gen_op_movl_T0_Dshift(ot); |
1157 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1158 | } |
1159 | ||
1160 | static inline void gen_lods(DisasContext *s, int ot) | |
1161 | { | |
1162 | gen_string_movl_A0_ESI(s); | |
57fec1fe FB |
1163 | gen_op_ld_T0_A0(ot + s->mem_index); |
1164 | gen_op_mov_reg_T0(ot, R_EAX); | |
6e0d8677 FB |
1165 | gen_op_movl_T0_Dshift(ot); |
1166 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2c0262af FB |
1167 | } |
1168 | ||
1169 | static inline void gen_scas(DisasContext *s, int ot) | |
1170 | { | |
57fec1fe | 1171 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
2c0262af | 1172 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1173 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1174 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1175 | gen_op_movl_T0_Dshift(ot); |
1176 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1177 | } |
1178 | ||
1179 | static inline void gen_cmps(DisasContext *s, int ot) | |
1180 | { | |
1181 | gen_string_movl_A0_ESI(s); | |
57fec1fe | 1182 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 1183 | gen_string_movl_A0_EDI(s); |
57fec1fe | 1184 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af | 1185 | gen_op_cmpl_T0_T1_cc(); |
6e0d8677 FB |
1186 | gen_op_movl_T0_Dshift(ot); |
1187 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
1188 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2c0262af FB |
1189 | } |
1190 | ||
1191 | static inline void gen_ins(DisasContext *s, int ot) | |
1192 | { | |
2e70f6ef PB |
1193 | if (use_icount) |
1194 | gen_io_start(); | |
2c0262af | 1195 | gen_string_movl_A0_EDI(s); |
6e0d8677 FB |
1196 | /* Note: we must do this dummy write first to be restartable in |
1197 | case of page fault. */ | |
9772c73b | 1198 | gen_op_movl_T0_0(); |
57fec1fe | 1199 | gen_op_st_T0_A0(ot + s->mem_index); |
b8b6a50b | 1200 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
b6abf97d FB |
1201 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1202 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
a7812ae4 | 1203 | gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 1204 | gen_op_st_T0_A0(ot + s->mem_index); |
6e0d8677 FB |
1205 | gen_op_movl_T0_Dshift(ot); |
1206 | gen_op_add_reg_T0(s->aflag, R_EDI); | |
2e70f6ef PB |
1207 | if (use_icount) |
1208 | gen_io_end(); | |
2c0262af FB |
1209 | } |
1210 | ||
1211 | static inline void gen_outs(DisasContext *s, int ot) | |
1212 | { | |
2e70f6ef PB |
1213 | if (use_icount) |
1214 | gen_io_start(); | |
2c0262af | 1215 | gen_string_movl_A0_ESI(s); |
57fec1fe | 1216 | gen_op_ld_T0_A0(ot + s->mem_index); |
b8b6a50b FB |
1217 | |
1218 | gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); | |
b6abf97d FB |
1219 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); |
1220 | tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); | |
1221 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); | |
a7812ae4 | 1222 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
b8b6a50b | 1223 | |
6e0d8677 FB |
1224 | gen_op_movl_T0_Dshift(ot); |
1225 | gen_op_add_reg_T0(s->aflag, R_ESI); | |
2e70f6ef PB |
1226 | if (use_icount) |
1227 | gen_io_end(); | |
2c0262af FB |
1228 | } |
1229 | ||
1230 | /* same method as Valgrind : we generate jumps to current or next | |
1231 | instruction */ | |
1232 | #define GEN_REPZ(op) \ | |
1233 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 | 1234 | target_ulong cur_eip, target_ulong next_eip) \ |
2c0262af | 1235 | { \ |
14ce26e7 | 1236 | int l2;\ |
2c0262af | 1237 | gen_update_cc_op(s); \ |
14ce26e7 | 1238 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1239 | gen_ ## op(s, ot); \ |
6e0d8677 | 1240 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af FB |
1241 | /* a loop would cause two single step exceptions if ECX = 1 \ |
1242 | before rep string_insn */ \ | |
1243 | if (!s->jmp_opt) \ | |
6e0d8677 | 1244 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1245 | gen_jmp(s, cur_eip); \ |
1246 | } | |
1247 | ||
1248 | #define GEN_REPZ2(op) \ | |
1249 | static inline void gen_repz_ ## op(DisasContext *s, int ot, \ | |
14ce26e7 FB |
1250 | target_ulong cur_eip, \ |
1251 | target_ulong next_eip, \ | |
2c0262af FB |
1252 | int nz) \ |
1253 | { \ | |
14ce26e7 | 1254 | int l2;\ |
2c0262af | 1255 | gen_update_cc_op(s); \ |
14ce26e7 | 1256 | l2 = gen_jz_ecx_string(s, next_eip); \ |
2c0262af | 1257 | gen_ ## op(s, ot); \ |
6e0d8677 | 1258 | gen_op_add_reg_im(s->aflag, R_ECX, -1); \ |
2c0262af | 1259 | gen_op_set_cc_op(CC_OP_SUBB + ot); \ |
8e1c85e3 | 1260 | gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \ |
2c0262af | 1261 | if (!s->jmp_opt) \ |
6e0d8677 | 1262 | gen_op_jz_ecx(s->aflag, l2); \ |
2c0262af FB |
1263 | gen_jmp(s, cur_eip); \ |
1264 | } | |
1265 | ||
1266 | GEN_REPZ(movs) | |
1267 | GEN_REPZ(stos) | |
1268 | GEN_REPZ(lods) | |
1269 | GEN_REPZ(ins) | |
1270 | GEN_REPZ(outs) | |
1271 | GEN_REPZ2(scas) | |
1272 | GEN_REPZ2(cmps) | |
1273 | ||
a7812ae4 PB |
1274 | static void gen_helper_fp_arith_ST0_FT0(int op) |
1275 | { | |
1276 | switch (op) { | |
d3eb5eae BS |
1277 | case 0: |
1278 | gen_helper_fadd_ST0_FT0(cpu_env); | |
1279 | break; | |
1280 | case 1: | |
1281 | gen_helper_fmul_ST0_FT0(cpu_env); | |
1282 | break; | |
1283 | case 2: | |
1284 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1285 | break; | |
1286 | case 3: | |
1287 | gen_helper_fcom_ST0_FT0(cpu_env); | |
1288 | break; | |
1289 | case 4: | |
1290 | gen_helper_fsub_ST0_FT0(cpu_env); | |
1291 | break; | |
1292 | case 5: | |
1293 | gen_helper_fsubr_ST0_FT0(cpu_env); | |
1294 | break; | |
1295 | case 6: | |
1296 | gen_helper_fdiv_ST0_FT0(cpu_env); | |
1297 | break; | |
1298 | case 7: | |
1299 | gen_helper_fdivr_ST0_FT0(cpu_env); | |
1300 | break; | |
a7812ae4 PB |
1301 | } |
1302 | } | |
2c0262af FB |
1303 | |
1304 | /* NOTE the exception in "r" op ordering */ | |
a7812ae4 PB |
1305 | static void gen_helper_fp_arith_STN_ST0(int op, int opreg) |
1306 | { | |
1307 | TCGv_i32 tmp = tcg_const_i32(opreg); | |
1308 | switch (op) { | |
d3eb5eae BS |
1309 | case 0: |
1310 | gen_helper_fadd_STN_ST0(cpu_env, tmp); | |
1311 | break; | |
1312 | case 1: | |
1313 | gen_helper_fmul_STN_ST0(cpu_env, tmp); | |
1314 | break; | |
1315 | case 4: | |
1316 | gen_helper_fsubr_STN_ST0(cpu_env, tmp); | |
1317 | break; | |
1318 | case 5: | |
1319 | gen_helper_fsub_STN_ST0(cpu_env, tmp); | |
1320 | break; | |
1321 | case 6: | |
1322 | gen_helper_fdivr_STN_ST0(cpu_env, tmp); | |
1323 | break; | |
1324 | case 7: | |
1325 | gen_helper_fdiv_STN_ST0(cpu_env, tmp); | |
1326 | break; | |
a7812ae4 PB |
1327 | } |
1328 | } | |
2c0262af FB |
1329 | |
1330 | /* if d == OR_TMP0, it means memory operand (address in A0) */ | |
1331 | static void gen_op(DisasContext *s1, int op, int ot, int d) | |
1332 | { | |
2c0262af | 1333 | if (d != OR_TMP0) { |
57fec1fe | 1334 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1335 | } else { |
57fec1fe | 1336 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1337 | } |
1338 | switch(op) { | |
1339 | case OP_ADCL: | |
cad3a37d FB |
1340 | if (s1->cc_op != CC_OP_DYNAMIC) |
1341 | gen_op_set_cc_op(s1->cc_op); | |
1342 | gen_compute_eflags_c(cpu_tmp4); | |
1343 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1344 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1345 | if (d != OR_TMP0) | |
1346 | gen_op_mov_reg_T0(ot, d); | |
1347 | else | |
1348 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1349 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1350 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1351 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1352 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1353 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot); | |
1354 | s1->cc_op = CC_OP_DYNAMIC; | |
1355 | break; | |
2c0262af FB |
1356 | case OP_SBBL: |
1357 | if (s1->cc_op != CC_OP_DYNAMIC) | |
1358 | gen_op_set_cc_op(s1->cc_op); | |
cad3a37d FB |
1359 | gen_compute_eflags_c(cpu_tmp4); |
1360 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
1361 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4); | |
1362 | if (d != OR_TMP0) | |
57fec1fe | 1363 | gen_op_mov_reg_T0(ot, d); |
cad3a37d FB |
1364 | else |
1365 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1366 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); | |
1367 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
1368 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4); | |
1369 | tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2); | |
1370 | tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot); | |
2c0262af | 1371 | s1->cc_op = CC_OP_DYNAMIC; |
cad3a37d | 1372 | break; |
2c0262af FB |
1373 | case OP_ADDL: |
1374 | gen_op_addl_T0_T1(); | |
cad3a37d FB |
1375 | if (d != OR_TMP0) |
1376 | gen_op_mov_reg_T0(ot, d); | |
1377 | else | |
1378 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1379 | gen_op_update2_cc(); | |
2c0262af | 1380 | s1->cc_op = CC_OP_ADDB + ot; |
2c0262af FB |
1381 | break; |
1382 | case OP_SUBL: | |
57fec1fe | 1383 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1384 | if (d != OR_TMP0) |
1385 | gen_op_mov_reg_T0(ot, d); | |
1386 | else | |
1387 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1388 | gen_op_update2_cc(); | |
2c0262af | 1389 | s1->cc_op = CC_OP_SUBB + ot; |
2c0262af FB |
1390 | break; |
1391 | default: | |
1392 | case OP_ANDL: | |
57fec1fe | 1393 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1394 | if (d != OR_TMP0) |
1395 | gen_op_mov_reg_T0(ot, d); | |
1396 | else | |
1397 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1398 | gen_op_update1_cc(); | |
57fec1fe | 1399 | s1->cc_op = CC_OP_LOGICB + ot; |
57fec1fe | 1400 | break; |
2c0262af | 1401 | case OP_ORL: |
57fec1fe | 1402 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1403 | if (d != OR_TMP0) |
1404 | gen_op_mov_reg_T0(ot, d); | |
1405 | else | |
1406 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1407 | gen_op_update1_cc(); | |
57fec1fe | 1408 | s1->cc_op = CC_OP_LOGICB + ot; |
57fec1fe | 1409 | break; |
2c0262af | 1410 | case OP_XORL: |
57fec1fe | 1411 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
cad3a37d FB |
1412 | if (d != OR_TMP0) |
1413 | gen_op_mov_reg_T0(ot, d); | |
1414 | else | |
1415 | gen_op_st_T0_A0(ot + s1->mem_index); | |
1416 | gen_op_update1_cc(); | |
2c0262af | 1417 | s1->cc_op = CC_OP_LOGICB + ot; |
2c0262af FB |
1418 | break; |
1419 | case OP_CMPL: | |
1420 | gen_op_cmpl_T0_T1_cc(); | |
1421 | s1->cc_op = CC_OP_SUBB + ot; | |
2c0262af FB |
1422 | break; |
1423 | } | |
b6abf97d FB |
1424 | } |
1425 | ||
2c0262af FB |
1426 | /* if d == OR_TMP0, it means memory operand (address in A0) */ |
1427 | static void gen_inc(DisasContext *s1, int ot, int d, int c) | |
1428 | { | |
1429 | if (d != OR_TMP0) | |
57fec1fe | 1430 | gen_op_mov_TN_reg(ot, 0, d); |
2c0262af | 1431 | else |
57fec1fe | 1432 | gen_op_ld_T0_A0(ot + s1->mem_index); |
2c0262af FB |
1433 | if (s1->cc_op != CC_OP_DYNAMIC) |
1434 | gen_op_set_cc_op(s1->cc_op); | |
1435 | if (c > 0) { | |
b6abf97d | 1436 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); |
2c0262af FB |
1437 | s1->cc_op = CC_OP_INCB + ot; |
1438 | } else { | |
b6abf97d | 1439 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1); |
2c0262af FB |
1440 | s1->cc_op = CC_OP_DECB + ot; |
1441 | } | |
1442 | if (d != OR_TMP0) | |
57fec1fe | 1443 | gen_op_mov_reg_T0(ot, d); |
2c0262af | 1444 | else |
57fec1fe | 1445 | gen_op_st_T0_A0(ot + s1->mem_index); |
b6abf97d | 1446 | gen_compute_eflags_c(cpu_cc_src); |
cd31fefa | 1447 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
2c0262af FB |
1448 | } |
1449 | ||
b6abf97d FB |
1450 | static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
1451 | int is_right, int is_arith) | |
2c0262af | 1452 | { |
b6abf97d FB |
1453 | target_ulong mask; |
1454 | int shift_label; | |
82786041 | 1455 | TCGv t0, t1, t2; |
1e4840bf | 1456 | |
82786041 | 1457 | if (ot == OT_QUAD) { |
b6abf97d | 1458 | mask = 0x3f; |
82786041 | 1459 | } else { |
b6abf97d | 1460 | mask = 0x1f; |
82786041 | 1461 | } |
3b46e624 | 1462 | |
b6abf97d | 1463 | /* load */ |
82786041 | 1464 | if (op1 == OR_TMP0) { |
b6abf97d | 1465 | gen_op_ld_T0_A0(ot + s->mem_index); |
82786041 | 1466 | } else { |
b6abf97d | 1467 | gen_op_mov_TN_reg(ot, 0, op1); |
82786041 | 1468 | } |
b6abf97d | 1469 | |
82786041 RH |
1470 | t0 = tcg_temp_local_new(); |
1471 | t1 = tcg_temp_local_new(); | |
1472 | t2 = tcg_temp_local_new(); | |
b6abf97d | 1473 | |
82786041 | 1474 | tcg_gen_andi_tl(t2, cpu_T[1], mask); |
b6abf97d FB |
1475 | |
1476 | if (is_right) { | |
1477 | if (is_arith) { | |
f484d386 | 1478 | gen_exts(ot, cpu_T[0]); |
82786041 RH |
1479 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1480 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d | 1481 | } else { |
cad3a37d | 1482 | gen_extu(ot, cpu_T[0]); |
82786041 RH |
1483 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1484 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1485 | } |
1486 | } else { | |
82786041 RH |
1487 | tcg_gen_mov_tl(t0, cpu_T[0]); |
1488 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2); | |
b6abf97d FB |
1489 | } |
1490 | ||
1491 | /* store */ | |
82786041 | 1492 | if (op1 == OR_TMP0) { |
b6abf97d | 1493 | gen_op_st_T0_A0(ot + s->mem_index); |
82786041 | 1494 | } else { |
b6abf97d | 1495 | gen_op_mov_reg_T0(ot, op1); |
82786041 RH |
1496 | } |
1497 | ||
b6abf97d | 1498 | /* update eflags if non zero shift */ |
82786041 | 1499 | if (s->cc_op != CC_OP_DYNAMIC) { |
b6abf97d | 1500 | gen_op_set_cc_op(s->cc_op); |
82786041 | 1501 | } |
b6abf97d | 1502 | |
82786041 | 1503 | tcg_gen_mov_tl(t1, cpu_T[0]); |
1e4840bf | 1504 | |
b6abf97d | 1505 | shift_label = gen_new_label(); |
82786041 RH |
1506 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label); |
1507 | ||
1508 | tcg_gen_addi_tl(t2, t2, -1); | |
1509 | tcg_gen_mov_tl(cpu_cc_dst, t1); | |
1510 | ||
1511 | if (is_right) { | |
1512 | if (is_arith) { | |
1513 | tcg_gen_sar_tl(cpu_cc_src, t0, t2); | |
1514 | } else { | |
1515 | tcg_gen_shr_tl(cpu_cc_src, t0, t2); | |
1516 | } | |
1517 | } else { | |
1518 | tcg_gen_shl_tl(cpu_cc_src, t0, t2); | |
1519 | } | |
b6abf97d | 1520 | |
82786041 | 1521 | if (is_right) { |
b6abf97d | 1522 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
82786041 | 1523 | } else { |
b6abf97d | 1524 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
82786041 RH |
1525 | } |
1526 | ||
b6abf97d FB |
1527 | gen_set_label(shift_label); |
1528 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1529 | |
1530 | tcg_temp_free(t0); | |
1531 | tcg_temp_free(t1); | |
82786041 | 1532 | tcg_temp_free(t2); |
b6abf97d FB |
1533 | } |
1534 | ||
c1c37968 FB |
1535 | static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, |
1536 | int is_right, int is_arith) | |
1537 | { | |
1538 | int mask; | |
1539 | ||
1540 | if (ot == OT_QUAD) | |
1541 | mask = 0x3f; | |
1542 | else | |
1543 | mask = 0x1f; | |
1544 | ||
1545 | /* load */ | |
1546 | if (op1 == OR_TMP0) | |
1547 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1548 | else | |
1549 | gen_op_mov_TN_reg(ot, 0, op1); | |
1550 | ||
1551 | op2 &= mask; | |
1552 | if (op2 != 0) { | |
1553 | if (is_right) { | |
1554 | if (is_arith) { | |
1555 | gen_exts(ot, cpu_T[0]); | |
2a449d14 | 1556 | tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1557 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); |
1558 | } else { | |
1559 | gen_extu(ot, cpu_T[0]); | |
2a449d14 | 1560 | tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1561 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); |
1562 | } | |
1563 | } else { | |
2a449d14 | 1564 | tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); |
c1c37968 FB |
1565 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); |
1566 | } | |
1567 | } | |
1568 | ||
1569 | /* store */ | |
1570 | if (op1 == OR_TMP0) | |
1571 | gen_op_st_T0_A0(ot + s->mem_index); | |
1572 | else | |
1573 | gen_op_mov_reg_T0(ot, op1); | |
1574 | ||
1575 | /* update eflags if non zero shift */ | |
1576 | if (op2 != 0) { | |
2a449d14 | 1577 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
c1c37968 FB |
1578 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
1579 | if (is_right) | |
1580 | s->cc_op = CC_OP_SARB + ot; | |
1581 | else | |
1582 | s->cc_op = CC_OP_SHLB + ot; | |
1583 | } | |
1584 | } | |
1585 | ||
b6abf97d FB |
1586 | static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
1587 | { | |
1588 | if (arg2 >= 0) | |
1589 | tcg_gen_shli_tl(ret, arg1, arg2); | |
1590 | else | |
1591 | tcg_gen_shri_tl(ret, arg1, -arg2); | |
1592 | } | |
1593 | ||
b6abf97d FB |
1594 | static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
1595 | int is_right) | |
1596 | { | |
1597 | target_ulong mask; | |
1598 | int label1, label2, data_bits; | |
1e4840bf FB |
1599 | TCGv t0, t1, t2, a0; |
1600 | ||
1601 | /* XXX: inefficient, but we must use local temps */ | |
a7812ae4 PB |
1602 | t0 = tcg_temp_local_new(); |
1603 | t1 = tcg_temp_local_new(); | |
1604 | t2 = tcg_temp_local_new(); | |
1605 | a0 = tcg_temp_local_new(); | |
1e4840bf | 1606 | |
b6abf97d FB |
1607 | if (ot == OT_QUAD) |
1608 | mask = 0x3f; | |
1609 | else | |
1610 | mask = 0x1f; | |
1611 | ||
1612 | /* load */ | |
1e4840bf FB |
1613 | if (op1 == OR_TMP0) { |
1614 | tcg_gen_mov_tl(a0, cpu_A0); | |
1615 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1616 | } else { | |
1617 | gen_op_mov_v_reg(ot, t0, op1); | |
1618 | } | |
b6abf97d | 1619 | |
1e4840bf FB |
1620 | tcg_gen_mov_tl(t1, cpu_T[1]); |
1621 | ||
1622 | tcg_gen_andi_tl(t1, t1, mask); | |
b6abf97d FB |
1623 | |
1624 | /* Must test zero case to avoid using undefined behaviour in TCG | |
1625 | shifts. */ | |
1626 | label1 = gen_new_label(); | |
1e4840bf | 1627 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); |
b6abf97d FB |
1628 | |
1629 | if (ot <= OT_WORD) | |
1e4840bf | 1630 | tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); |
b6abf97d | 1631 | else |
1e4840bf | 1632 | tcg_gen_mov_tl(cpu_tmp0, t1); |
b6abf97d | 1633 | |
1e4840bf FB |
1634 | gen_extu(ot, t0); |
1635 | tcg_gen_mov_tl(t2, t0); | |
b6abf97d FB |
1636 | |
1637 | data_bits = 8 << ot; | |
1638 | /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: | |
1639 | fix TCG definition) */ | |
1640 | if (is_right) { | |
1e4840bf | 1641 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1642 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1643 | tcg_gen_shl_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1644 | } else { |
1e4840bf | 1645 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); |
5b207c00 | 1646 | tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0); |
1e4840bf | 1647 | tcg_gen_shr_tl(t0, t0, cpu_tmp0); |
b6abf97d | 1648 | } |
1e4840bf | 1649 | tcg_gen_or_tl(t0, t0, cpu_tmp4); |
b6abf97d FB |
1650 | |
1651 | gen_set_label(label1); | |
1652 | /* store */ | |
1e4840bf FB |
1653 | if (op1 == OR_TMP0) { |
1654 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1655 | } else { | |
1656 | gen_op_mov_reg_v(ot, op1, t0); | |
1657 | } | |
b6abf97d FB |
1658 | |
1659 | /* update eflags */ | |
1660 | if (s->cc_op != CC_OP_DYNAMIC) | |
1661 | gen_op_set_cc_op(s->cc_op); | |
1662 | ||
1663 | label2 = gen_new_label(); | |
1e4840bf | 1664 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); |
b6abf97d FB |
1665 | |
1666 | gen_compute_eflags(cpu_cc_src); | |
1667 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); | |
1e4840bf | 1668 | tcg_gen_xor_tl(cpu_tmp0, t2, t0); |
b6abf97d FB |
1669 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
1670 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1671 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1672 | if (is_right) { | |
1e4840bf | 1673 | tcg_gen_shri_tl(t0, t0, data_bits - 1); |
b6abf97d | 1674 | } |
1e4840bf FB |
1675 | tcg_gen_andi_tl(t0, t0, CC_C); |
1676 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
b6abf97d FB |
1677 | |
1678 | tcg_gen_discard_tl(cpu_cc_dst); | |
1679 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1680 | ||
1681 | gen_set_label(label2); | |
1682 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1683 | |
1684 | tcg_temp_free(t0); | |
1685 | tcg_temp_free(t1); | |
1686 | tcg_temp_free(t2); | |
1687 | tcg_temp_free(a0); | |
b6abf97d FB |
1688 | } |
1689 | ||
8cd6345d | 1690 | static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, |
1691 | int is_right) | |
1692 | { | |
1693 | int mask; | |
1694 | int data_bits; | |
1695 | TCGv t0, t1, a0; | |
1696 | ||
1697 | /* XXX: inefficient, but we must use local temps */ | |
1698 | t0 = tcg_temp_local_new(); | |
1699 | t1 = tcg_temp_local_new(); | |
1700 | a0 = tcg_temp_local_new(); | |
1701 | ||
1702 | if (ot == OT_QUAD) | |
1703 | mask = 0x3f; | |
1704 | else | |
1705 | mask = 0x1f; | |
1706 | ||
1707 | /* load */ | |
1708 | if (op1 == OR_TMP0) { | |
1709 | tcg_gen_mov_tl(a0, cpu_A0); | |
1710 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1711 | } else { | |
1712 | gen_op_mov_v_reg(ot, t0, op1); | |
1713 | } | |
1714 | ||
1715 | gen_extu(ot, t0); | |
1716 | tcg_gen_mov_tl(t1, t0); | |
1717 | ||
1718 | op2 &= mask; | |
1719 | data_bits = 8 << ot; | |
1720 | if (op2 != 0) { | |
1721 | int shift = op2 & ((1 << (3 + ot)) - 1); | |
1722 | if (is_right) { | |
1723 | tcg_gen_shri_tl(cpu_tmp4, t0, shift); | |
1724 | tcg_gen_shli_tl(t0, t0, data_bits - shift); | |
1725 | } | |
1726 | else { | |
1727 | tcg_gen_shli_tl(cpu_tmp4, t0, shift); | |
1728 | tcg_gen_shri_tl(t0, t0, data_bits - shift); | |
1729 | } | |
1730 | tcg_gen_or_tl(t0, t0, cpu_tmp4); | |
1731 | } | |
1732 | ||
1733 | /* store */ | |
1734 | if (op1 == OR_TMP0) { | |
1735 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1736 | } else { | |
1737 | gen_op_mov_reg_v(ot, op1, t0); | |
1738 | } | |
1739 | ||
1740 | if (op2 != 0) { | |
1741 | /* update eflags */ | |
1742 | if (s->cc_op != CC_OP_DYNAMIC) | |
1743 | gen_op_set_cc_op(s->cc_op); | |
1744 | ||
1745 | gen_compute_eflags(cpu_cc_src); | |
1746 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); | |
1747 | tcg_gen_xor_tl(cpu_tmp0, t1, t0); | |
1748 | tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); | |
1749 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); | |
1750 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); | |
1751 | if (is_right) { | |
1752 | tcg_gen_shri_tl(t0, t0, data_bits - 1); | |
1753 | } | |
1754 | tcg_gen_andi_tl(t0, t0, CC_C); | |
1755 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); | |
1756 | ||
1757 | tcg_gen_discard_tl(cpu_cc_dst); | |
1758 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1759 | s->cc_op = CC_OP_EFLAGS; | |
1760 | } | |
1761 | ||
1762 | tcg_temp_free(t0); | |
1763 | tcg_temp_free(t1); | |
1764 | tcg_temp_free(a0); | |
1765 | } | |
1766 | ||
b6abf97d FB |
1767 | /* XXX: add faster immediate = 1 case */ |
1768 | static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, | |
1769 | int is_right) | |
1770 | { | |
1771 | int label1; | |
1772 | ||
1773 | if (s->cc_op != CC_OP_DYNAMIC) | |
1774 | gen_op_set_cc_op(s->cc_op); | |
1775 | ||
1776 | /* load */ | |
1777 | if (op1 == OR_TMP0) | |
1778 | gen_op_ld_T0_A0(ot + s->mem_index); | |
1779 | else | |
1780 | gen_op_mov_TN_reg(ot, 0, op1); | |
1781 | ||
a7812ae4 PB |
1782 | if (is_right) { |
1783 | switch (ot) { | |
7923057b BS |
1784 | case 0: |
1785 | gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1786 | break; | |
1787 | case 1: | |
1788 | gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1789 | break; | |
1790 | case 2: | |
1791 | gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1792 | break; | |
a7812ae4 | 1793 | #ifdef TARGET_X86_64 |
7923057b BS |
1794 | case 3: |
1795 | gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1796 | break; | |
a7812ae4 PB |
1797 | #endif |
1798 | } | |
1799 | } else { | |
1800 | switch (ot) { | |
7923057b BS |
1801 | case 0: |
1802 | gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1803 | break; | |
1804 | case 1: | |
1805 | gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1806 | break; | |
1807 | case 2: | |
1808 | gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1809 | break; | |
a7812ae4 | 1810 | #ifdef TARGET_X86_64 |
7923057b BS |
1811 | case 3: |
1812 | gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); | |
1813 | break; | |
a7812ae4 PB |
1814 | #endif |
1815 | } | |
1816 | } | |
b6abf97d FB |
1817 | /* store */ |
1818 | if (op1 == OR_TMP0) | |
1819 | gen_op_st_T0_A0(ot + s->mem_index); | |
1820 | else | |
1821 | gen_op_mov_reg_T0(ot, op1); | |
1822 | ||
1823 | /* update eflags */ | |
1824 | label1 = gen_new_label(); | |
1e4840bf | 1825 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1); |
b6abf97d | 1826 | |
1e4840bf | 1827 | tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp); |
b6abf97d FB |
1828 | tcg_gen_discard_tl(cpu_cc_dst); |
1829 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); | |
1830 | ||
1831 | gen_set_label(label1); | |
1832 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1833 | } | |
1834 | ||
1835 | /* XXX: add faster immediate case */ | |
1836 | static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, | |
1837 | int is_right) | |
1838 | { | |
1839 | int label1, label2, data_bits; | |
1840 | target_ulong mask; | |
1e4840bf FB |
1841 | TCGv t0, t1, t2, a0; |
1842 | ||
a7812ae4 PB |
1843 | t0 = tcg_temp_local_new(); |
1844 | t1 = tcg_temp_local_new(); | |
1845 | t2 = tcg_temp_local_new(); | |
1846 | a0 = tcg_temp_local_new(); | |
b6abf97d FB |
1847 | |
1848 | if (ot == OT_QUAD) | |
1849 | mask = 0x3f; | |
1850 | else | |
1851 | mask = 0x1f; | |
1852 | ||
1853 | /* load */ | |
1e4840bf FB |
1854 | if (op1 == OR_TMP0) { |
1855 | tcg_gen_mov_tl(a0, cpu_A0); | |
1856 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
1857 | } else { | |
1858 | gen_op_mov_v_reg(ot, t0, op1); | |
1859 | } | |
b6abf97d FB |
1860 | |
1861 | tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); | |
1e4840bf FB |
1862 | |
1863 | tcg_gen_mov_tl(t1, cpu_T[1]); | |
1864 | tcg_gen_mov_tl(t2, cpu_T3); | |
1865 | ||
b6abf97d FB |
1866 | /* Must test zero case to avoid using undefined behaviour in TCG |
1867 | shifts. */ | |
1868 | label1 = gen_new_label(); | |
1e4840bf | 1869 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); |
b6abf97d | 1870 | |
1e4840bf | 1871 | tcg_gen_addi_tl(cpu_tmp5, t2, -1); |
b6abf97d FB |
1872 | if (ot == OT_WORD) { |
1873 | /* Note: we implement the Intel behaviour for shift count > 16 */ | |
1874 | if (is_right) { | |
1e4840bf FB |
1875 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1876 | tcg_gen_shli_tl(cpu_tmp0, t1, 16); | |
1877 | tcg_gen_or_tl(t0, t0, cpu_tmp0); | |
1878 | tcg_gen_ext32u_tl(t0, t0); | |
b6abf97d | 1879 | |
1e4840bf | 1880 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d FB |
1881 | |
1882 | /* only needed if count > 16, but a test would complicate */ | |
5b207c00 | 1883 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf | 1884 | tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); |
b6abf97d | 1885 | |
1e4840bf | 1886 | tcg_gen_shr_tl(t0, t0, t2); |
b6abf97d | 1887 | |
1e4840bf | 1888 | tcg_gen_or_tl(t0, t0, cpu_tmp0); |
b6abf97d FB |
1889 | } else { |
1890 | /* XXX: not optimal */ | |
1e4840bf FB |
1891 | tcg_gen_andi_tl(t0, t0, 0xffff); |
1892 | tcg_gen_shli_tl(t1, t1, 16); | |
1893 | tcg_gen_or_tl(t1, t1, t0); | |
1894 | tcg_gen_ext32u_tl(t1, t1); | |
b6abf97d | 1895 | |
1e4840bf | 1896 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
5b207c00 | 1897 | tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); |
bedda79c AJ |
1898 | tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); |
1899 | tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); | |
b6abf97d | 1900 | |
1e4840bf | 1901 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1902 | tcg_gen_subfi_tl(cpu_tmp5, 32, t2); |
1e4840bf FB |
1903 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1904 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1905 | } |
1906 | } else { | |
1907 | data_bits = 8 << ot; | |
1908 | if (is_right) { | |
1909 | if (ot == OT_LONG) | |
1e4840bf | 1910 | tcg_gen_ext32u_tl(t0, t0); |
b6abf97d | 1911 | |
1e4840bf | 1912 | tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1913 | |
1e4840bf | 1914 | tcg_gen_shr_tl(t0, t0, t2); |
5b207c00 | 1915 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1916 | tcg_gen_shl_tl(t1, t1, cpu_tmp5); |
1917 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1918 | |
1919 | } else { | |
1920 | if (ot == OT_LONG) | |
1e4840bf | 1921 | tcg_gen_ext32u_tl(t1, t1); |
b6abf97d | 1922 | |
1e4840bf | 1923 | tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); |
b6abf97d | 1924 | |
1e4840bf | 1925 | tcg_gen_shl_tl(t0, t0, t2); |
5b207c00 | 1926 | tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2); |
1e4840bf FB |
1927 | tcg_gen_shr_tl(t1, t1, cpu_tmp5); |
1928 | tcg_gen_or_tl(t0, t0, t1); | |
b6abf97d FB |
1929 | } |
1930 | } | |
1e4840bf | 1931 | tcg_gen_mov_tl(t1, cpu_tmp4); |
b6abf97d FB |
1932 | |
1933 | gen_set_label(label1); | |
1934 | /* store */ | |
1e4840bf FB |
1935 | if (op1 == OR_TMP0) { |
1936 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1937 | } else { | |
1938 | gen_op_mov_reg_v(ot, op1, t0); | |
1939 | } | |
b6abf97d FB |
1940 | |
1941 | /* update eflags */ | |
1942 | if (s->cc_op != CC_OP_DYNAMIC) | |
1943 | gen_op_set_cc_op(s->cc_op); | |
1944 | ||
1945 | label2 = gen_new_label(); | |
1e4840bf | 1946 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); |
b6abf97d | 1947 | |
1e4840bf FB |
1948 | tcg_gen_mov_tl(cpu_cc_src, t1); |
1949 | tcg_gen_mov_tl(cpu_cc_dst, t0); | |
b6abf97d FB |
1950 | if (is_right) { |
1951 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); | |
1952 | } else { | |
1953 | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); | |
1954 | } | |
1955 | gen_set_label(label2); | |
1956 | s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ | |
1e4840bf FB |
1957 | |
1958 | tcg_temp_free(t0); | |
1959 | tcg_temp_free(t1); | |
1960 | tcg_temp_free(t2); | |
1961 | tcg_temp_free(a0); | |
b6abf97d FB |
1962 | } |
1963 | ||
1964 | static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) | |
1965 | { | |
1966 | if (s != OR_TMP1) | |
1967 | gen_op_mov_TN_reg(ot, 1, s); | |
1968 | switch(op) { | |
1969 | case OP_ROL: | |
1970 | gen_rot_rm_T1(s1, ot, d, 0); | |
1971 | break; | |
1972 | case OP_ROR: | |
1973 | gen_rot_rm_T1(s1, ot, d, 1); | |
1974 | break; | |
1975 | case OP_SHL: | |
1976 | case OP_SHL1: | |
1977 | gen_shift_rm_T1(s1, ot, d, 0, 0); | |
1978 | break; | |
1979 | case OP_SHR: | |
1980 | gen_shift_rm_T1(s1, ot, d, 1, 0); | |
1981 | break; | |
1982 | case OP_SAR: | |
1983 | gen_shift_rm_T1(s1, ot, d, 1, 1); | |
1984 | break; | |
1985 | case OP_RCL: | |
1986 | gen_rotc_rm_T1(s1, ot, d, 0); | |
1987 | break; | |
1988 | case OP_RCR: | |
1989 | gen_rotc_rm_T1(s1, ot, d, 1); | |
1990 | break; | |
1991 | } | |
2c0262af FB |
1992 | } |
1993 | ||
1994 | static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) | |
1995 | { | |
c1c37968 | 1996 | switch(op) { |
8cd6345d | 1997 | case OP_ROL: |
1998 | gen_rot_rm_im(s1, ot, d, c, 0); | |
1999 | break; | |
2000 | case OP_ROR: | |
2001 | gen_rot_rm_im(s1, ot, d, c, 1); | |
2002 | break; | |
c1c37968 FB |
2003 | case OP_SHL: |
2004 | case OP_SHL1: | |
2005 | gen_shift_rm_im(s1, ot, d, c, 0, 0); | |
2006 | break; | |
2007 | case OP_SHR: | |
2008 | gen_shift_rm_im(s1, ot, d, c, 1, 0); | |
2009 | break; | |
2010 | case OP_SAR: | |
2011 | gen_shift_rm_im(s1, ot, d, c, 1, 1); | |
2012 | break; | |
2013 | default: | |
2014 | /* currently not optimized */ | |
2015 | gen_op_movl_T1_im(c); | |
2016 | gen_shift(s1, op, ot, d, OR_TMP1); | |
2017 | break; | |
2018 | } | |
2c0262af FB |
2019 | } |
2020 | ||
2021 | static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) | |
2022 | { | |
14ce26e7 | 2023 | target_long disp; |
2c0262af | 2024 | int havesib; |
14ce26e7 | 2025 | int base; |
2c0262af FB |
2026 | int index; |
2027 | int scale; | |
2028 | int opreg; | |
2029 | int mod, rm, code, override, must_add_seg; | |
2030 | ||
2031 | override = s->override; | |
2032 | must_add_seg = s->addseg; | |
2033 | if (override >= 0) | |
2034 | must_add_seg = 1; | |
2035 | mod = (modrm >> 6) & 3; | |
2036 | rm = modrm & 7; | |
2037 | ||
2038 | if (s->aflag) { | |
2039 | ||
2040 | havesib = 0; | |
2041 | base = rm; | |
2042 | index = 0; | |
2043 | scale = 0; | |
3b46e624 | 2044 | |
2c0262af FB |
2045 | if (base == 4) { |
2046 | havesib = 1; | |
92fc4b58 | 2047 | code = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 2048 | scale = (code >> 6) & 3; |
14ce26e7 FB |
2049 | index = ((code >> 3) & 7) | REX_X(s); |
2050 | base = (code & 7); | |
2c0262af | 2051 | } |
14ce26e7 | 2052 | base |= REX_B(s); |
2c0262af FB |
2053 | |
2054 | switch (mod) { | |
2055 | case 0: | |
14ce26e7 | 2056 | if ((base & 7) == 5) { |
2c0262af | 2057 | base = -1; |
92fc4b58 | 2058 | disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc); |
2c0262af | 2059 | s->pc += 4; |
14ce26e7 FB |
2060 | if (CODE64(s) && !havesib) { |
2061 | disp += s->pc + s->rip_offset; | |
2062 | } | |
2c0262af FB |
2063 | } else { |
2064 | disp = 0; | |
2065 | } | |
2066 | break; | |
2067 | case 1: | |
92fc4b58 | 2068 | disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
2069 | break; |
2070 | default: | |
2071 | case 2: | |
92fc4b58 | 2072 | disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc); |
2c0262af FB |
2073 | s->pc += 4; |
2074 | break; | |
2075 | } | |
3b46e624 | 2076 | |
2c0262af FB |
2077 | if (base >= 0) { |
2078 | /* for correct popl handling with esp */ | |
2079 | if (base == 4 && s->popl_esp_hack) | |
2080 | disp += s->popl_esp_hack; | |
14ce26e7 FB |
2081 | #ifdef TARGET_X86_64 |
2082 | if (s->aflag == 2) { | |
57fec1fe | 2083 | gen_op_movq_A0_reg(base); |
14ce26e7 | 2084 | if (disp != 0) { |
57fec1fe | 2085 | gen_op_addq_A0_im(disp); |
14ce26e7 | 2086 | } |
5fafdf24 | 2087 | } else |
14ce26e7 FB |
2088 | #endif |
2089 | { | |
57fec1fe | 2090 | gen_op_movl_A0_reg(base); |
14ce26e7 FB |
2091 | if (disp != 0) |
2092 | gen_op_addl_A0_im(disp); | |
2093 | } | |
2c0262af | 2094 | } else { |
14ce26e7 FB |
2095 | #ifdef TARGET_X86_64 |
2096 | if (s->aflag == 2) { | |
57fec1fe | 2097 | gen_op_movq_A0_im(disp); |
5fafdf24 | 2098 | } else |
14ce26e7 FB |
2099 | #endif |
2100 | { | |
2101 | gen_op_movl_A0_im(disp); | |
2102 | } | |
2c0262af | 2103 | } |
b16f827b AJ |
2104 | /* index == 4 means no index */ |
2105 | if (havesib && (index != 4)) { | |
14ce26e7 FB |
2106 | #ifdef TARGET_X86_64 |
2107 | if (s->aflag == 2) { | |
57fec1fe | 2108 | gen_op_addq_A0_reg_sN(scale, index); |
5fafdf24 | 2109 | } else |
14ce26e7 FB |
2110 | #endif |
2111 | { | |
57fec1fe | 2112 | gen_op_addl_A0_reg_sN(scale, index); |
14ce26e7 | 2113 | } |
2c0262af FB |
2114 | } |
2115 | if (must_add_seg) { | |
2116 | if (override < 0) { | |
2117 | if (base == R_EBP || base == R_ESP) | |
2118 | override = R_SS; | |
2119 | else | |
2120 | override = R_DS; | |
2121 | } | |
14ce26e7 FB |
2122 | #ifdef TARGET_X86_64 |
2123 | if (s->aflag == 2) { | |
57fec1fe | 2124 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2125 | } else |
14ce26e7 FB |
2126 | #endif |
2127 | { | |
7162ab21 | 2128 | gen_op_addl_A0_seg(s, override); |
14ce26e7 | 2129 | } |
2c0262af FB |
2130 | } |
2131 | } else { | |
2132 | switch (mod) { | |
2133 | case 0: | |
2134 | if (rm == 6) { | |
92fc4b58 | 2135 | disp = cpu_lduw_code(cpu_single_env, s->pc); |
2c0262af FB |
2136 | s->pc += 2; |
2137 | gen_op_movl_A0_im(disp); | |
2138 | rm = 0; /* avoid SS override */ | |
2139 | goto no_rm; | |
2140 | } else { | |
2141 | disp = 0; | |
2142 | } | |
2143 | break; | |
2144 | case 1: | |
92fc4b58 | 2145 | disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
2146 | break; |
2147 | default: | |
2148 | case 2: | |
92fc4b58 | 2149 | disp = cpu_lduw_code(cpu_single_env, s->pc); |
2c0262af FB |
2150 | s->pc += 2; |
2151 | break; | |
2152 | } | |
2153 | switch(rm) { | |
2154 | case 0: | |
57fec1fe FB |
2155 | gen_op_movl_A0_reg(R_EBX); |
2156 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2157 | break; |
2158 | case 1: | |
57fec1fe FB |
2159 | gen_op_movl_A0_reg(R_EBX); |
2160 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2161 | break; |
2162 | case 2: | |
57fec1fe FB |
2163 | gen_op_movl_A0_reg(R_EBP); |
2164 | gen_op_addl_A0_reg_sN(0, R_ESI); | |
2c0262af FB |
2165 | break; |
2166 | case 3: | |
57fec1fe FB |
2167 | gen_op_movl_A0_reg(R_EBP); |
2168 | gen_op_addl_A0_reg_sN(0, R_EDI); | |
2c0262af FB |
2169 | break; |
2170 | case 4: | |
57fec1fe | 2171 | gen_op_movl_A0_reg(R_ESI); |
2c0262af FB |
2172 | break; |
2173 | case 5: | |
57fec1fe | 2174 | gen_op_movl_A0_reg(R_EDI); |
2c0262af FB |
2175 | break; |
2176 | case 6: | |
57fec1fe | 2177 | gen_op_movl_A0_reg(R_EBP); |
2c0262af FB |
2178 | break; |
2179 | default: | |
2180 | case 7: | |
57fec1fe | 2181 | gen_op_movl_A0_reg(R_EBX); |
2c0262af FB |
2182 | break; |
2183 | } | |
2184 | if (disp != 0) | |
2185 | gen_op_addl_A0_im(disp); | |
2186 | gen_op_andl_A0_ffff(); | |
2187 | no_rm: | |
2188 | if (must_add_seg) { | |
2189 | if (override < 0) { | |
2190 | if (rm == 2 || rm == 3 || rm == 6) | |
2191 | override = R_SS; | |
2192 | else | |
2193 | override = R_DS; | |
2194 | } | |
7162ab21 | 2195 | gen_op_addl_A0_seg(s, override); |
2c0262af FB |
2196 | } |
2197 | } | |
2198 | ||
2199 | opreg = OR_A0; | |
2200 | disp = 0; | |
2201 | *reg_ptr = opreg; | |
2202 | *offset_ptr = disp; | |
2203 | } | |
2204 | ||
e17a36ce FB |
2205 | static void gen_nop_modrm(DisasContext *s, int modrm) |
2206 | { | |
2207 | int mod, rm, base, code; | |
2208 | ||
2209 | mod = (modrm >> 6) & 3; | |
2210 | if (mod == 3) | |
2211 | return; | |
2212 | rm = modrm & 7; | |
2213 | ||
2214 | if (s->aflag) { | |
2215 | ||
2216 | base = rm; | |
3b46e624 | 2217 | |
e17a36ce | 2218 | if (base == 4) { |
92fc4b58 | 2219 | code = cpu_ldub_code(cpu_single_env, s->pc++); |
e17a36ce FB |
2220 | base = (code & 7); |
2221 | } | |
3b46e624 | 2222 | |
e17a36ce FB |
2223 | switch (mod) { |
2224 | case 0: | |
2225 | if (base == 5) { | |
2226 | s->pc += 4; | |
2227 | } | |
2228 | break; | |
2229 | case 1: | |
2230 | s->pc++; | |
2231 | break; | |
2232 | default: | |
2233 | case 2: | |
2234 | s->pc += 4; | |
2235 | break; | |
2236 | } | |
2237 | } else { | |
2238 | switch (mod) { | |
2239 | case 0: | |
2240 | if (rm == 6) { | |
2241 | s->pc += 2; | |
2242 | } | |
2243 | break; | |
2244 | case 1: | |
2245 | s->pc++; | |
2246 | break; | |
2247 | default: | |
2248 | case 2: | |
2249 | s->pc += 2; | |
2250 | break; | |
2251 | } | |
2252 | } | |
2253 | } | |
2254 | ||
664e0f19 FB |
2255 | /* used for LEA and MOV AX, mem */ |
2256 | static void gen_add_A0_ds_seg(DisasContext *s) | |
2257 | { | |
2258 | int override, must_add_seg; | |
2259 | must_add_seg = s->addseg; | |
2260 | override = R_DS; | |
2261 | if (s->override >= 0) { | |
2262 | override = s->override; | |
2263 | must_add_seg = 1; | |
664e0f19 FB |
2264 | } |
2265 | if (must_add_seg) { | |
8f091a59 FB |
2266 | #ifdef TARGET_X86_64 |
2267 | if (CODE64(s)) { | |
57fec1fe | 2268 | gen_op_addq_A0_seg(override); |
5fafdf24 | 2269 | } else |
8f091a59 FB |
2270 | #endif |
2271 | { | |
7162ab21 | 2272 | gen_op_addl_A0_seg(s, override); |
8f091a59 | 2273 | } |
664e0f19 FB |
2274 | } |
2275 | } | |
2276 | ||
222a3336 | 2277 | /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == |
2c0262af FB |
2278 | OR_TMP0 */ |
2279 | static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) | |
2280 | { | |
2281 | int mod, rm, opreg, disp; | |
2282 | ||
2283 | mod = (modrm >> 6) & 3; | |
14ce26e7 | 2284 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
2285 | if (mod == 3) { |
2286 | if (is_store) { | |
2287 | if (reg != OR_TMP0) | |
57fec1fe FB |
2288 | gen_op_mov_TN_reg(ot, 0, reg); |
2289 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af | 2290 | } else { |
57fec1fe | 2291 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 2292 | if (reg != OR_TMP0) |
57fec1fe | 2293 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2294 | } |
2295 | } else { | |
2296 | gen_lea_modrm(s, modrm, &opreg, &disp); | |
2297 | if (is_store) { | |
2298 | if (reg != OR_TMP0) | |
57fec1fe FB |
2299 | gen_op_mov_TN_reg(ot, 0, reg); |
2300 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 2301 | } else { |
57fec1fe | 2302 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 2303 | if (reg != OR_TMP0) |
57fec1fe | 2304 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
2305 | } |
2306 | } | |
2307 | } | |
2308 | ||
2309 | static inline uint32_t insn_get(DisasContext *s, int ot) | |
2310 | { | |
2311 | uint32_t ret; | |
2312 | ||
2313 | switch(ot) { | |
2314 | case OT_BYTE: | |
92fc4b58 | 2315 | ret = cpu_ldub_code(cpu_single_env, s->pc); |
2c0262af FB |
2316 | s->pc++; |
2317 | break; | |
2318 | case OT_WORD: | |
92fc4b58 | 2319 | ret = cpu_lduw_code(cpu_single_env, s->pc); |
2c0262af FB |
2320 | s->pc += 2; |
2321 | break; | |
2322 | default: | |
2323 | case OT_LONG: | |
92fc4b58 | 2324 | ret = cpu_ldl_code(cpu_single_env, s->pc); |
2c0262af FB |
2325 | s->pc += 4; |
2326 | break; | |
2327 | } | |
2328 | return ret; | |
2329 | } | |
2330 | ||
14ce26e7 FB |
2331 | static inline int insn_const_size(unsigned int ot) |
2332 | { | |
2333 | if (ot <= OT_LONG) | |
2334 | return 1 << ot; | |
2335 | else | |
2336 | return 4; | |
2337 | } | |
2338 | ||
6e256c93 FB |
2339 | static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) |
2340 | { | |
2341 | TranslationBlock *tb; | |
2342 | target_ulong pc; | |
2343 | ||
2344 | pc = s->cs_base + eip; | |
2345 | tb = s->tb; | |
2346 | /* NOTE: we handle the case where the TB spans two pages here */ | |
2347 | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) || | |
2348 | (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { | |
2349 | /* jump to same page: we can use a direct jump */ | |
57fec1fe | 2350 | tcg_gen_goto_tb(tb_num); |
6e256c93 | 2351 | gen_jmp_im(eip); |
4b4a72e5 | 2352 | tcg_gen_exit_tb((tcg_target_long)tb + tb_num); |
6e256c93 FB |
2353 | } else { |
2354 | /* jump to another page: currently not optimized */ | |
2355 | gen_jmp_im(eip); | |
2356 | gen_eob(s); | |
2357 | } | |
2358 | } | |
2359 | ||
5fafdf24 | 2360 | static inline void gen_jcc(DisasContext *s, int b, |
14ce26e7 | 2361 | target_ulong val, target_ulong next_eip) |
2c0262af | 2362 | { |
8e1c85e3 | 2363 | int l1, l2, cc_op; |
3b46e624 | 2364 | |
8e1c85e3 | 2365 | cc_op = s->cc_op; |
728d803b | 2366 | gen_update_cc_op(s); |
2c0262af | 2367 | if (s->jmp_opt) { |
14ce26e7 | 2368 | l1 = gen_new_label(); |
8e1c85e3 FB |
2369 | gen_jcc1(s, cc_op, b, l1); |
2370 | ||
6e256c93 | 2371 | gen_goto_tb(s, 0, next_eip); |
14ce26e7 FB |
2372 | |
2373 | gen_set_label(l1); | |
6e256c93 | 2374 | gen_goto_tb(s, 1, val); |
5779406a | 2375 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2376 | } else { |
14ce26e7 | 2377 | |
14ce26e7 FB |
2378 | l1 = gen_new_label(); |
2379 | l2 = gen_new_label(); | |
8e1c85e3 FB |
2380 | gen_jcc1(s, cc_op, b, l1); |
2381 | ||
14ce26e7 | 2382 | gen_jmp_im(next_eip); |
8e1c85e3 FB |
2383 | tcg_gen_br(l2); |
2384 | ||
14ce26e7 FB |
2385 | gen_set_label(l1); |
2386 | gen_jmp_im(val); | |
2387 | gen_set_label(l2); | |
2c0262af FB |
2388 | gen_eob(s); |
2389 | } | |
2390 | } | |
2391 | ||
2392 | static void gen_setcc(DisasContext *s, int b) | |
2393 | { | |
8e1c85e3 | 2394 | int inv, jcc_op, l1; |
1e4840bf | 2395 | TCGv t0; |
14ce26e7 | 2396 | |
8e1c85e3 FB |
2397 | if (is_fast_jcc_case(s, b)) { |
2398 | /* nominal case: we use a jump */ | |
1e4840bf | 2399 | /* XXX: make it faster by adding new instructions in TCG */ |
a7812ae4 | 2400 | t0 = tcg_temp_local_new(); |
1e4840bf | 2401 | tcg_gen_movi_tl(t0, 0); |
8e1c85e3 FB |
2402 | l1 = gen_new_label(); |
2403 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
1e4840bf | 2404 | tcg_gen_movi_tl(t0, 1); |
8e1c85e3 | 2405 | gen_set_label(l1); |
1e4840bf FB |
2406 | tcg_gen_mov_tl(cpu_T[0], t0); |
2407 | tcg_temp_free(t0); | |
8e1c85e3 FB |
2408 | } else { |
2409 | /* slow case: it is more efficient not to generate a jump, | |
2410 | although it is questionnable whether this optimization is | |
2411 | worth to */ | |
2412 | inv = b & 1; | |
2413 | jcc_op = (b >> 1) & 7; | |
1e4840bf | 2414 | gen_setcc_slow_T0(s, jcc_op); |
8e1c85e3 FB |
2415 | if (inv) { |
2416 | tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); | |
2417 | } | |
2c0262af FB |
2418 | } |
2419 | } | |
2420 | ||
3bd7da9e FB |
2421 | static inline void gen_op_movl_T0_seg(int seg_reg) |
2422 | { | |
2423 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, | |
2424 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2425 | } | |
2426 | ||
2427 | static inline void gen_op_movl_seg_T0_vm(int seg_reg) | |
2428 | { | |
2429 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); | |
2430 | tcg_gen_st32_tl(cpu_T[0], cpu_env, | |
2431 | offsetof(CPUX86State,segs[seg_reg].selector)); | |
2432 | tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); | |
2433 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
2434 | offsetof(CPUX86State,segs[seg_reg].base)); | |
2435 | } | |
2436 | ||
2c0262af FB |
2437 | /* move T0 to seg_reg and compute if the CPU state may change. Never |
2438 | call this function with seg_reg == R_CS */ | |
14ce26e7 | 2439 | static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) |
2c0262af | 2440 | { |
3415a4dd FB |
2441 | if (s->pe && !s->vm86) { |
2442 | /* XXX: optimize by finding processor state dynamically */ | |
2443 | if (s->cc_op != CC_OP_DYNAMIC) | |
2444 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2445 | gen_jmp_im(cur_eip); |
b6abf97d | 2446 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 2447 | gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32); |
dc196a57 FB |
2448 | /* abort translation because the addseg value may change or |
2449 | because ss32 may change. For R_SS, translation must always | |
2450 | stop as a special handling must be done to disable hardware | |
2451 | interrupts for the next instruction */ | |
2452 | if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) | |
5779406a | 2453 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2454 | } else { |
3bd7da9e | 2455 | gen_op_movl_seg_T0_vm(seg_reg); |
dc196a57 | 2456 | if (seg_reg == R_SS) |
5779406a | 2457 | s->is_jmp = DISAS_TB_JUMP; |
3415a4dd | 2458 | } |
2c0262af FB |
2459 | } |
2460 | ||
0573fbfc TS |
2461 | static inline int svm_is_rep(int prefixes) |
2462 | { | |
2463 | return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); | |
2464 | } | |
2465 | ||
872929aa | 2466 | static inline void |
0573fbfc | 2467 | gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, |
b8b6a50b | 2468 | uint32_t type, uint64_t param) |
0573fbfc | 2469 | { |
872929aa FB |
2470 | /* no SVM activated; fast case */ |
2471 | if (likely(!(s->flags & HF_SVMI_MASK))) | |
2472 | return; | |
2473 | if (s->cc_op != CC_OP_DYNAMIC) | |
2474 | gen_op_set_cc_op(s->cc_op); | |
2475 | gen_jmp_im(pc_start - s->cs_base); | |
052e80d5 | 2476 | gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type), |
a7812ae4 | 2477 | tcg_const_i64(param)); |
0573fbfc TS |
2478 | } |
2479 | ||
872929aa | 2480 | static inline void |
0573fbfc TS |
2481 | gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) |
2482 | { | |
872929aa | 2483 | gen_svm_check_intercept_param(s, pc_start, type, 0); |
0573fbfc TS |
2484 | } |
2485 | ||
4f31916f FB |
2486 | static inline void gen_stack_update(DisasContext *s, int addend) |
2487 | { | |
14ce26e7 FB |
2488 | #ifdef TARGET_X86_64 |
2489 | if (CODE64(s)) { | |
6e0d8677 | 2490 | gen_op_add_reg_im(2, R_ESP, addend); |
14ce26e7 FB |
2491 | } else |
2492 | #endif | |
4f31916f | 2493 | if (s->ss32) { |
6e0d8677 | 2494 | gen_op_add_reg_im(1, R_ESP, addend); |
4f31916f | 2495 | } else { |
6e0d8677 | 2496 | gen_op_add_reg_im(0, R_ESP, addend); |
4f31916f FB |
2497 | } |
2498 | } | |
2499 | ||
2c0262af FB |
2500 | /* generate a push. It depends on ss32, addseg and dflag */ |
2501 | static void gen_push_T0(DisasContext *s) | |
2502 | { | |
14ce26e7 FB |
2503 | #ifdef TARGET_X86_64 |
2504 | if (CODE64(s)) { | |
57fec1fe | 2505 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2506 | if (s->dflag) { |
57fec1fe FB |
2507 | gen_op_addq_A0_im(-8); |
2508 | gen_op_st_T0_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2509 | } else { |
57fec1fe FB |
2510 | gen_op_addq_A0_im(-2); |
2511 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2512 | } |
57fec1fe | 2513 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2514 | } else |
14ce26e7 FB |
2515 | #endif |
2516 | { | |
57fec1fe | 2517 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2518 | if (!s->dflag) |
57fec1fe | 2519 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2520 | else |
57fec1fe | 2521 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2522 | if (s->ss32) { |
2523 | if (s->addseg) { | |
bbf662ee | 2524 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2525 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2526 | } |
2527 | } else { | |
2528 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2529 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
7162ab21 | 2530 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2531 | } |
57fec1fe | 2532 | gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); |
14ce26e7 | 2533 | if (s->ss32 && !s->addseg) |
57fec1fe | 2534 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 | 2535 | else |
57fec1fe | 2536 | gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); |
2c0262af FB |
2537 | } |
2538 | } | |
2539 | ||
4f31916f FB |
2540 | /* generate a push. It depends on ss32, addseg and dflag */ |
2541 | /* slower version for T1, only used for call Ev */ | |
2542 | static void gen_push_T1(DisasContext *s) | |
2c0262af | 2543 | { |
14ce26e7 FB |
2544 | #ifdef TARGET_X86_64 |
2545 | if (CODE64(s)) { | |
57fec1fe | 2546 | gen_op_movq_A0_reg(R_ESP); |
8f091a59 | 2547 | if (s->dflag) { |
57fec1fe FB |
2548 | gen_op_addq_A0_im(-8); |
2549 | gen_op_st_T1_A0(OT_QUAD + s->mem_index); | |
8f091a59 | 2550 | } else { |
57fec1fe FB |
2551 | gen_op_addq_A0_im(-2); |
2552 | gen_op_st_T0_A0(OT_WORD + s->mem_index); | |
8f091a59 | 2553 | } |
57fec1fe | 2554 | gen_op_mov_reg_A0(2, R_ESP); |
5fafdf24 | 2555 | } else |
14ce26e7 FB |
2556 | #endif |
2557 | { | |
57fec1fe | 2558 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 | 2559 | if (!s->dflag) |
57fec1fe | 2560 | gen_op_addl_A0_im(-2); |
14ce26e7 | 2561 | else |
57fec1fe | 2562 | gen_op_addl_A0_im(-4); |
14ce26e7 FB |
2563 | if (s->ss32) { |
2564 | if (s->addseg) { | |
7162ab21 | 2565 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2566 | } |
2567 | } else { | |
2568 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2569 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2570 | } |
57fec1fe | 2571 | gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); |
3b46e624 | 2572 | |
14ce26e7 | 2573 | if (s->ss32 && !s->addseg) |
57fec1fe | 2574 | gen_op_mov_reg_A0(1, R_ESP); |
14ce26e7 FB |
2575 | else |
2576 | gen_stack_update(s, (-2) << s->dflag); | |
2c0262af FB |
2577 | } |
2578 | } | |
2579 | ||
4f31916f FB |
2580 | /* two step pop is necessary for precise exceptions */ |
2581 | static void gen_pop_T0(DisasContext *s) | |
2c0262af | 2582 | { |
14ce26e7 FB |
2583 | #ifdef TARGET_X86_64 |
2584 | if (CODE64(s)) { | |
57fec1fe FB |
2585 | gen_op_movq_A0_reg(R_ESP); |
2586 | gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); | |
5fafdf24 | 2587 | } else |
14ce26e7 FB |
2588 | #endif |
2589 | { | |
57fec1fe | 2590 | gen_op_movl_A0_reg(R_ESP); |
14ce26e7 FB |
2591 | if (s->ss32) { |
2592 | if (s->addseg) | |
7162ab21 | 2593 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 FB |
2594 | } else { |
2595 | gen_op_andl_A0_ffff(); | |
7162ab21 | 2596 | gen_op_addl_A0_seg(s, R_SS); |
14ce26e7 | 2597 | } |
57fec1fe | 2598 | gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); |
2c0262af FB |
2599 | } |
2600 | } | |
2601 | ||
2602 | static void gen_pop_update(DisasContext *s) | |
2603 | { | |
14ce26e7 | 2604 | #ifdef TARGET_X86_64 |
8f091a59 | 2605 | if (CODE64(s) && s->dflag) { |
14ce26e7 FB |
2606 | gen_stack_update(s, 8); |
2607 | } else | |
2608 | #endif | |
2609 | { | |
2610 | gen_stack_update(s, 2 << s->dflag); | |
2611 | } | |
2c0262af FB |
2612 | } |
2613 | ||
2614 | static void gen_stack_A0(DisasContext *s) | |
2615 | { | |
57fec1fe | 2616 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2617 | if (!s->ss32) |
2618 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2619 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2620 | if (s->addseg) |
7162ab21 | 2621 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2622 | } |
2623 | ||
2624 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2625 | static void gen_pusha(DisasContext *s) | |
2626 | { | |
2627 | int i; | |
57fec1fe | 2628 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2629 | gen_op_addl_A0_im(-16 << s->dflag); |
2630 | if (!s->ss32) | |
2631 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2632 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2c0262af | 2633 | if (s->addseg) |
7162ab21 | 2634 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af | 2635 | for(i = 0;i < 8; i++) { |
57fec1fe FB |
2636 | gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); |
2637 | gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); | |
2c0262af FB |
2638 | gen_op_addl_A0_im(2 << s->dflag); |
2639 | } | |
57fec1fe | 2640 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2641 | } |
2642 | ||
2643 | /* NOTE: wrap around in 16 bit not fully handled */ | |
2644 | static void gen_popa(DisasContext *s) | |
2645 | { | |
2646 | int i; | |
57fec1fe | 2647 | gen_op_movl_A0_reg(R_ESP); |
2c0262af FB |
2648 | if (!s->ss32) |
2649 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
2650 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
2651 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag); | |
2c0262af | 2652 | if (s->addseg) |
7162ab21 | 2653 | gen_op_addl_A0_seg(s, R_SS); |
2c0262af FB |
2654 | for(i = 0;i < 8; i++) { |
2655 | /* ESP is not reloaded */ | |
2656 | if (i != 3) { | |
57fec1fe FB |
2657 | gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); |
2658 | gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); | |
2c0262af FB |
2659 | } |
2660 | gen_op_addl_A0_im(2 << s->dflag); | |
2661 | } | |
57fec1fe | 2662 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af FB |
2663 | } |
2664 | ||
2c0262af FB |
2665 | static void gen_enter(DisasContext *s, int esp_addend, int level) |
2666 | { | |
61a8c4ec | 2667 | int ot, opsize; |
2c0262af | 2668 | |
2c0262af | 2669 | level &= 0x1f; |
8f091a59 FB |
2670 | #ifdef TARGET_X86_64 |
2671 | if (CODE64(s)) { | |
2672 | ot = s->dflag ? OT_QUAD : OT_WORD; | |
2673 | opsize = 1 << ot; | |
3b46e624 | 2674 | |
57fec1fe | 2675 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 | 2676 | gen_op_addq_A0_im(-opsize); |
bbf662ee | 2677 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 FB |
2678 | |
2679 | /* push bp */ | |
57fec1fe FB |
2680 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2681 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2682 | if (level) { |
b5b38f61 | 2683 | /* XXX: must save state */ |
2999a0b2 | 2684 | gen_helper_enter64_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2685 | tcg_const_i32((ot == OT_QUAD)), |
2686 | cpu_T[1]); | |
8f091a59 | 2687 | } |
57fec1fe | 2688 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2689 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2690 | gen_op_mov_reg_T1(OT_QUAD, R_ESP); |
5fafdf24 | 2691 | } else |
8f091a59 FB |
2692 | #endif |
2693 | { | |
2694 | ot = s->dflag + OT_WORD; | |
2695 | opsize = 2 << s->dflag; | |
3b46e624 | 2696 | |
57fec1fe | 2697 | gen_op_movl_A0_reg(R_ESP); |
8f091a59 FB |
2698 | gen_op_addl_A0_im(-opsize); |
2699 | if (!s->ss32) | |
2700 | gen_op_andl_A0_ffff(); | |
bbf662ee | 2701 | tcg_gen_mov_tl(cpu_T[1], cpu_A0); |
8f091a59 | 2702 | if (s->addseg) |
7162ab21 | 2703 | gen_op_addl_A0_seg(s, R_SS); |
8f091a59 | 2704 | /* push bp */ |
57fec1fe FB |
2705 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
2706 | gen_op_st_T0_A0(ot + s->mem_index); | |
8f091a59 | 2707 | if (level) { |
b5b38f61 | 2708 | /* XXX: must save state */ |
2999a0b2 | 2709 | gen_helper_enter_level(cpu_env, tcg_const_i32(level), |
a7812ae4 PB |
2710 | tcg_const_i32(s->dflag), |
2711 | cpu_T[1]); | |
8f091a59 | 2712 | } |
57fec1fe | 2713 | gen_op_mov_reg_T1(ot, R_EBP); |
bbf662ee | 2714 | tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); |
57fec1fe | 2715 | gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); |
2c0262af | 2716 | } |
2c0262af FB |
2717 | } |
2718 | ||
14ce26e7 | 2719 | static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) |
2c0262af FB |
2720 | { |
2721 | if (s->cc_op != CC_OP_DYNAMIC) | |
2722 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2723 | gen_jmp_im(cur_eip); |
77b2bc2c | 2724 | gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); |
5779406a | 2725 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2726 | } |
2727 | ||
2728 | /* an interrupt is different from an exception because of the | |
7f75ffd3 | 2729 | privilege checks */ |
5fafdf24 | 2730 | static void gen_interrupt(DisasContext *s, int intno, |
14ce26e7 | 2731 | target_ulong cur_eip, target_ulong next_eip) |
2c0262af FB |
2732 | { |
2733 | if (s->cc_op != CC_OP_DYNAMIC) | |
2734 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2735 | gen_jmp_im(cur_eip); |
77b2bc2c | 2736 | gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), |
a7812ae4 | 2737 | tcg_const_i32(next_eip - cur_eip)); |
5779406a | 2738 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2739 | } |
2740 | ||
14ce26e7 | 2741 | static void gen_debug(DisasContext *s, target_ulong cur_eip) |
2c0262af FB |
2742 | { |
2743 | if (s->cc_op != CC_OP_DYNAMIC) | |
2744 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 2745 | gen_jmp_im(cur_eip); |
4a7443be | 2746 | gen_helper_debug(cpu_env); |
5779406a | 2747 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2748 | } |
2749 | ||
2750 | /* generate a generic end of block. Trace exception is also generated | |
2751 | if needed */ | |
2752 | static void gen_eob(DisasContext *s) | |
2753 | { | |
2754 | if (s->cc_op != CC_OP_DYNAMIC) | |
2755 | gen_op_set_cc_op(s->cc_op); | |
a2cc3b24 | 2756 | if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { |
f0967a1a | 2757 | gen_helper_reset_inhibit_irq(cpu_env); |
a2cc3b24 | 2758 | } |
a2397807 | 2759 | if (s->tb->flags & HF_RF_MASK) { |
f0967a1a | 2760 | gen_helper_reset_rf(cpu_env); |
a2397807 | 2761 | } |
34865134 | 2762 | if (s->singlestep_enabled) { |
4a7443be | 2763 | gen_helper_debug(cpu_env); |
34865134 | 2764 | } else if (s->tf) { |
4a7443be | 2765 | gen_helper_single_step(cpu_env); |
2c0262af | 2766 | } else { |
57fec1fe | 2767 | tcg_gen_exit_tb(0); |
2c0262af | 2768 | } |
5779406a | 2769 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
2770 | } |
2771 | ||
2772 | /* generate a jump to eip. No segment change must happen before as a | |
2773 | direct call to the next block may occur */ | |
14ce26e7 | 2774 | static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) |
2c0262af | 2775 | { |
2c0262af | 2776 | if (s->jmp_opt) { |
728d803b | 2777 | gen_update_cc_op(s); |
6e256c93 | 2778 | gen_goto_tb(s, tb_num, eip); |
5779406a | 2779 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af | 2780 | } else { |
14ce26e7 | 2781 | gen_jmp_im(eip); |
2c0262af FB |
2782 | gen_eob(s); |
2783 | } | |
2784 | } | |
2785 | ||
14ce26e7 FB |
2786 | static void gen_jmp(DisasContext *s, target_ulong eip) |
2787 | { | |
2788 | gen_jmp_tb(s, eip, 0); | |
2789 | } | |
2790 | ||
8686c490 FB |
2791 | static inline void gen_ldq_env_A0(int idx, int offset) |
2792 | { | |
2793 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2794 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2795 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); | |
8686c490 | 2796 | } |
664e0f19 | 2797 | |
8686c490 FB |
2798 | static inline void gen_stq_env_A0(int idx, int offset) |
2799 | { | |
2800 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2801 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); |
2802 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2803 | } |
664e0f19 | 2804 | |
8686c490 FB |
2805 | static inline void gen_ldo_env_A0(int idx, int offset) |
2806 | { | |
2807 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2808 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); |
2809 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); | |
8686c490 | 2810 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2811 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index); |
2812 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); | |
8686c490 | 2813 | } |
14ce26e7 | 2814 | |
8686c490 FB |
2815 | static inline void gen_sto_env_A0(int idx, int offset) |
2816 | { | |
2817 | int mem_index = (idx >> 2) - 1; | |
b6abf97d FB |
2818 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
2819 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); | |
8686c490 | 2820 | tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
b6abf97d FB |
2821 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
2822 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index); | |
8686c490 | 2823 | } |
14ce26e7 | 2824 | |
5af45186 FB |
2825 | static inline void gen_op_movo(int d_offset, int s_offset) |
2826 | { | |
b6abf97d FB |
2827 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2828 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
2829 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8); | |
2830 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8); | |
5af45186 FB |
2831 | } |
2832 | ||
2833 | static inline void gen_op_movq(int d_offset, int s_offset) | |
2834 | { | |
b6abf97d FB |
2835 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset); |
2836 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 FB |
2837 | } |
2838 | ||
2839 | static inline void gen_op_movl(int d_offset, int s_offset) | |
2840 | { | |
b6abf97d FB |
2841 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset); |
2842 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset); | |
5af45186 FB |
2843 | } |
2844 | ||
2845 | static inline void gen_op_movq_env_0(int d_offset) | |
2846 | { | |
b6abf97d FB |
2847 | tcg_gen_movi_i64(cpu_tmp1_i64, 0); |
2848 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset); | |
5af45186 | 2849 | } |
664e0f19 | 2850 | |
d3eb5eae BS |
2851 | typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); |
2852 | typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); | |
2853 | typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val); | |
2854 | typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val); | |
2855 | typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); | |
2856 | typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, | |
2857 | TCGv_i32 val); | |
c4baa050 | 2858 | typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); |
d3eb5eae BS |
2859 | typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, |
2860 | TCGv val); | |
c4baa050 | 2861 | |
5af45186 FB |
2862 | #define SSE_SPECIAL ((void *)1) |
2863 | #define SSE_DUMMY ((void *)2) | |
664e0f19 | 2864 | |
a7812ae4 PB |
2865 | #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } |
2866 | #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ | |
2867 | gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } | |
5af45186 | 2868 | |
d3eb5eae | 2869 | static const SSEFunc_0_epp sse_op_table1[256][4] = { |
a35f3ec7 AJ |
2870 | /* 3DNow! extensions */ |
2871 | [0x0e] = { SSE_DUMMY }, /* femms */ | |
2872 | [0x0f] = { SSE_DUMMY }, /* pf... */ | |
664e0f19 FB |
2873 | /* pure SSE operations */ |
2874 | [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
2875 | [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ | |
465e9838 | 2876 | [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ |
664e0f19 | 2877 | [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ |
a7812ae4 PB |
2878 | [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, |
2879 | [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2880 | [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ |
2881 | [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ | |
2882 | ||
2883 | [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2884 | [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ | |
2885 | [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ | |
d9f4bb27 | 2886 | [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ |
664e0f19 FB |
2887 | [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ |
2888 | [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ | |
a7812ae4 PB |
2889 | [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, |
2890 | [0x2f] = { gen_helper_comiss, gen_helper_comisd }, | |
664e0f19 FB |
2891 | [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ |
2892 | [0x51] = SSE_FOP(sqrt), | |
a7812ae4 PB |
2893 | [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, |
2894 | [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, | |
2895 | [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ | |
2896 | [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ | |
2897 | [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ | |
2898 | [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ | |
664e0f19 FB |
2899 | [0x58] = SSE_FOP(add), |
2900 | [0x59] = SSE_FOP(mul), | |
a7812ae4 PB |
2901 | [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, |
2902 | gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, | |
2903 | [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, | |
664e0f19 FB |
2904 | [0x5c] = SSE_FOP(sub), |
2905 | [0x5d] = SSE_FOP(min), | |
2906 | [0x5e] = SSE_FOP(div), | |
2907 | [0x5f] = SSE_FOP(max), | |
2908 | ||
2909 | [0xc2] = SSE_FOP(cmpeq), | |
d3eb5eae BS |
2910 | [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, |
2911 | (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ | |
664e0f19 | 2912 | |
222a3336 AZ |
2913 | [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ |
2914 | [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ | |
4242b1bd | 2915 | |
664e0f19 FB |
2916 | /* MMX ops and their SSE extensions */ |
2917 | [0x60] = MMX_OP2(punpcklbw), | |
2918 | [0x61] = MMX_OP2(punpcklwd), | |
2919 | [0x62] = MMX_OP2(punpckldq), | |
2920 | [0x63] = MMX_OP2(packsswb), | |
2921 | [0x64] = MMX_OP2(pcmpgtb), | |
2922 | [0x65] = MMX_OP2(pcmpgtw), | |
2923 | [0x66] = MMX_OP2(pcmpgtl), | |
2924 | [0x67] = MMX_OP2(packuswb), | |
2925 | [0x68] = MMX_OP2(punpckhbw), | |
2926 | [0x69] = MMX_OP2(punpckhwd), | |
2927 | [0x6a] = MMX_OP2(punpckhdq), | |
2928 | [0x6b] = MMX_OP2(packssdw), | |
a7812ae4 PB |
2929 | [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, |
2930 | [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, | |
664e0f19 FB |
2931 | [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ |
2932 | [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ | |
d3eb5eae BS |
2933 | [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, |
2934 | (SSEFunc_0_epp)gen_helper_pshufd_xmm, | |
2935 | (SSEFunc_0_epp)gen_helper_pshufhw_xmm, | |
2936 | (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2937 | [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ |
2938 | [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ | |
2939 | [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ | |
2940 | [0x74] = MMX_OP2(pcmpeqb), | |
2941 | [0x75] = MMX_OP2(pcmpeqw), | |
2942 | [0x76] = MMX_OP2(pcmpeql), | |
a35f3ec7 | 2943 | [0x77] = { SSE_DUMMY }, /* emms */ |
d9f4bb27 AP |
2944 | [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ |
2945 | [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, | |
a7812ae4 PB |
2946 | [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, |
2947 | [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, | |
664e0f19 FB |
2948 | [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ |
2949 | [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ | |
2950 | [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ | |
2951 | [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ | |
a7812ae4 | 2952 | [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, |
664e0f19 FB |
2953 | [0xd1] = MMX_OP2(psrlw), |
2954 | [0xd2] = MMX_OP2(psrld), | |
2955 | [0xd3] = MMX_OP2(psrlq), | |
2956 | [0xd4] = MMX_OP2(paddq), | |
2957 | [0xd5] = MMX_OP2(pmullw), | |
2958 | [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, | |
2959 | [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ | |
2960 | [0xd8] = MMX_OP2(psubusb), | |
2961 | [0xd9] = MMX_OP2(psubusw), | |
2962 | [0xda] = MMX_OP2(pminub), | |
2963 | [0xdb] = MMX_OP2(pand), | |
2964 | [0xdc] = MMX_OP2(paddusb), | |
2965 | [0xdd] = MMX_OP2(paddusw), | |
2966 | [0xde] = MMX_OP2(pmaxub), | |
2967 | [0xdf] = MMX_OP2(pandn), | |
2968 | [0xe0] = MMX_OP2(pavgb), | |
2969 | [0xe1] = MMX_OP2(psraw), | |
2970 | [0xe2] = MMX_OP2(psrad), | |
2971 | [0xe3] = MMX_OP2(pavgw), | |
2972 | [0xe4] = MMX_OP2(pmulhuw), | |
2973 | [0xe5] = MMX_OP2(pmulhw), | |
a7812ae4 | 2974 | [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, |
664e0f19 FB |
2975 | [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ |
2976 | [0xe8] = MMX_OP2(psubsb), | |
2977 | [0xe9] = MMX_OP2(psubsw), | |
2978 | [0xea] = MMX_OP2(pminsw), | |
2979 | [0xeb] = MMX_OP2(por), | |
2980 | [0xec] = MMX_OP2(paddsb), | |
2981 | [0xed] = MMX_OP2(paddsw), | |
2982 | [0xee] = MMX_OP2(pmaxsw), | |
2983 | [0xef] = MMX_OP2(pxor), | |
465e9838 | 2984 | [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ |
664e0f19 FB |
2985 | [0xf1] = MMX_OP2(psllw), |
2986 | [0xf2] = MMX_OP2(pslld), | |
2987 | [0xf3] = MMX_OP2(psllq), | |
2988 | [0xf4] = MMX_OP2(pmuludq), | |
2989 | [0xf5] = MMX_OP2(pmaddwd), | |
2990 | [0xf6] = MMX_OP2(psadbw), | |
d3eb5eae BS |
2991 | [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, |
2992 | (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ | |
664e0f19 FB |
2993 | [0xf8] = MMX_OP2(psubb), |
2994 | [0xf9] = MMX_OP2(psubw), | |
2995 | [0xfa] = MMX_OP2(psubl), | |
2996 | [0xfb] = MMX_OP2(psubq), | |
2997 | [0xfc] = MMX_OP2(paddb), | |
2998 | [0xfd] = MMX_OP2(paddw), | |
2999 | [0xfe] = MMX_OP2(paddl), | |
3000 | }; | |
3001 | ||
d3eb5eae | 3002 | static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { |
664e0f19 FB |
3003 | [0 + 2] = MMX_OP2(psrlw), |
3004 | [0 + 4] = MMX_OP2(psraw), | |
3005 | [0 + 6] = MMX_OP2(psllw), | |
3006 | [8 + 2] = MMX_OP2(psrld), | |
3007 | [8 + 4] = MMX_OP2(psrad), | |
3008 | [8 + 6] = MMX_OP2(pslld), | |
3009 | [16 + 2] = MMX_OP2(psrlq), | |
a7812ae4 | 3010 | [16 + 3] = { NULL, gen_helper_psrldq_xmm }, |
664e0f19 | 3011 | [16 + 6] = MMX_OP2(psllq), |
a7812ae4 | 3012 | [16 + 7] = { NULL, gen_helper_pslldq_xmm }, |
664e0f19 FB |
3013 | }; |
3014 | ||
d3eb5eae | 3015 | static const SSEFunc_0_epi sse_op_table3ai[] = { |
a7812ae4 | 3016 | gen_helper_cvtsi2ss, |
11f8cdbc | 3017 | gen_helper_cvtsi2sd |
c4baa050 | 3018 | }; |
a7812ae4 | 3019 | |
11f8cdbc | 3020 | #ifdef TARGET_X86_64 |
d3eb5eae | 3021 | static const SSEFunc_0_epl sse_op_table3aq[] = { |
11f8cdbc SW |
3022 | gen_helper_cvtsq2ss, |
3023 | gen_helper_cvtsq2sd | |
3024 | }; | |
3025 | #endif | |
3026 | ||
d3eb5eae | 3027 | static const SSEFunc_i_ep sse_op_table3bi[] = { |
a7812ae4 | 3028 | gen_helper_cvttss2si, |
a7812ae4 | 3029 | gen_helper_cvtss2si, |
bedc2ac1 | 3030 | gen_helper_cvttsd2si, |
11f8cdbc | 3031 | gen_helper_cvtsd2si |
664e0f19 | 3032 | }; |
3b46e624 | 3033 | |
11f8cdbc | 3034 | #ifdef TARGET_X86_64 |
d3eb5eae | 3035 | static const SSEFunc_l_ep sse_op_table3bq[] = { |
11f8cdbc | 3036 | gen_helper_cvttss2sq, |
11f8cdbc | 3037 | gen_helper_cvtss2sq, |
bedc2ac1 | 3038 | gen_helper_cvttsd2sq, |
11f8cdbc SW |
3039 | gen_helper_cvtsd2sq |
3040 | }; | |
3041 | #endif | |
3042 | ||
d3eb5eae | 3043 | static const SSEFunc_0_epp sse_op_table4[8][4] = { |
664e0f19 FB |
3044 | SSE_FOP(cmpeq), |
3045 | SSE_FOP(cmplt), | |
3046 | SSE_FOP(cmple), | |
3047 | SSE_FOP(cmpunord), | |
3048 | SSE_FOP(cmpneq), | |
3049 | SSE_FOP(cmpnlt), | |
3050 | SSE_FOP(cmpnle), | |
3051 | SSE_FOP(cmpord), | |
3052 | }; | |
3b46e624 | 3053 | |
d3eb5eae | 3054 | static const SSEFunc_0_epp sse_op_table5[256] = { |
a7812ae4 PB |
3055 | [0x0c] = gen_helper_pi2fw, |
3056 | [0x0d] = gen_helper_pi2fd, | |
3057 | [0x1c] = gen_helper_pf2iw, | |
3058 | [0x1d] = gen_helper_pf2id, | |
3059 | [0x8a] = gen_helper_pfnacc, | |
3060 | [0x8e] = gen_helper_pfpnacc, | |
3061 | [0x90] = gen_helper_pfcmpge, | |
3062 | [0x94] = gen_helper_pfmin, | |
3063 | [0x96] = gen_helper_pfrcp, | |
3064 | [0x97] = gen_helper_pfrsqrt, | |
3065 | [0x9a] = gen_helper_pfsub, | |
3066 | [0x9e] = gen_helper_pfadd, | |
3067 | [0xa0] = gen_helper_pfcmpgt, | |
3068 | [0xa4] = gen_helper_pfmax, | |
3069 | [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ | |
3070 | [0xa7] = gen_helper_movq, /* pfrsqit1 */ | |
3071 | [0xaa] = gen_helper_pfsubr, | |
3072 | [0xae] = gen_helper_pfacc, | |
3073 | [0xb0] = gen_helper_pfcmpeq, | |
3074 | [0xb4] = gen_helper_pfmul, | |
3075 | [0xb6] = gen_helper_movq, /* pfrcpit2 */ | |
3076 | [0xb7] = gen_helper_pmulhrw_mmx, | |
3077 | [0xbb] = gen_helper_pswapd, | |
3078 | [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ | |
a35f3ec7 AJ |
3079 | }; |
3080 | ||
d3eb5eae BS |
3081 | struct SSEOpHelper_epp { |
3082 | SSEFunc_0_epp op[2]; | |
c4baa050 BS |
3083 | uint32_t ext_mask; |
3084 | }; | |
3085 | ||
d3eb5eae BS |
3086 | struct SSEOpHelper_eppi { |
3087 | SSEFunc_0_eppi op[2]; | |
c4baa050 | 3088 | uint32_t ext_mask; |
222a3336 | 3089 | }; |
c4baa050 | 3090 | |
222a3336 | 3091 | #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } |
a7812ae4 PB |
3092 | #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } |
3093 | #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } | |
222a3336 | 3094 | #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } |
c4baa050 | 3095 | |
d3eb5eae | 3096 | static const struct SSEOpHelper_epp sse_op_table6[256] = { |
222a3336 AZ |
3097 | [0x00] = SSSE3_OP(pshufb), |
3098 | [0x01] = SSSE3_OP(phaddw), | |
3099 | [0x02] = SSSE3_OP(phaddd), | |
3100 | [0x03] = SSSE3_OP(phaddsw), | |
3101 | [0x04] = SSSE3_OP(pmaddubsw), | |
3102 | [0x05] = SSSE3_OP(phsubw), | |
3103 | [0x06] = SSSE3_OP(phsubd), | |
3104 | [0x07] = SSSE3_OP(phsubsw), | |
3105 | [0x08] = SSSE3_OP(psignb), | |
3106 | [0x09] = SSSE3_OP(psignw), | |
3107 | [0x0a] = SSSE3_OP(psignd), | |
3108 | [0x0b] = SSSE3_OP(pmulhrsw), | |
3109 | [0x10] = SSE41_OP(pblendvb), | |
3110 | [0x14] = SSE41_OP(blendvps), | |
3111 | [0x15] = SSE41_OP(blendvpd), | |
3112 | [0x17] = SSE41_OP(ptest), | |
3113 | [0x1c] = SSSE3_OP(pabsb), | |
3114 | [0x1d] = SSSE3_OP(pabsw), | |
3115 | [0x1e] = SSSE3_OP(pabsd), | |
3116 | [0x20] = SSE41_OP(pmovsxbw), | |
3117 | [0x21] = SSE41_OP(pmovsxbd), | |
3118 | [0x22] = SSE41_OP(pmovsxbq), | |
3119 | [0x23] = SSE41_OP(pmovsxwd), | |
3120 | [0x24] = SSE41_OP(pmovsxwq), | |
3121 | [0x25] = SSE41_OP(pmovsxdq), | |
3122 | [0x28] = SSE41_OP(pmuldq), | |
3123 | [0x29] = SSE41_OP(pcmpeqq), | |
3124 | [0x2a] = SSE41_SPECIAL, /* movntqda */ | |
3125 | [0x2b] = SSE41_OP(packusdw), | |
3126 | [0x30] = SSE41_OP(pmovzxbw), | |
3127 | [0x31] = SSE41_OP(pmovzxbd), | |
3128 | [0x32] = SSE41_OP(pmovzxbq), | |
3129 | [0x33] = SSE41_OP(pmovzxwd), | |
3130 | [0x34] = SSE41_OP(pmovzxwq), | |
3131 | [0x35] = SSE41_OP(pmovzxdq), | |
3132 | [0x37] = SSE42_OP(pcmpgtq), | |
3133 | [0x38] = SSE41_OP(pminsb), | |
3134 | [0x39] = SSE41_OP(pminsd), | |
3135 | [0x3a] = SSE41_OP(pminuw), | |
3136 | [0x3b] = SSE41_OP(pminud), | |
3137 | [0x3c] = SSE41_OP(pmaxsb), | |
3138 | [0x3d] = SSE41_OP(pmaxsd), | |
3139 | [0x3e] = SSE41_OP(pmaxuw), | |
3140 | [0x3f] = SSE41_OP(pmaxud), | |
3141 | [0x40] = SSE41_OP(pmulld), | |
3142 | [0x41] = SSE41_OP(phminposuw), | |
4242b1bd AZ |
3143 | }; |
3144 | ||
d3eb5eae | 3145 | static const struct SSEOpHelper_eppi sse_op_table7[256] = { |
222a3336 AZ |
3146 | [0x08] = SSE41_OP(roundps), |
3147 | [0x09] = SSE41_OP(roundpd), | |
3148 | [0x0a] = SSE41_OP(roundss), | |
3149 | [0x0b] = SSE41_OP(roundsd), | |
3150 | [0x0c] = SSE41_OP(blendps), | |
3151 | [0x0d] = SSE41_OP(blendpd), | |
3152 | [0x0e] = SSE41_OP(pblendw), | |
3153 | [0x0f] = SSSE3_OP(palignr), | |
3154 | [0x14] = SSE41_SPECIAL, /* pextrb */ | |
3155 | [0x15] = SSE41_SPECIAL, /* pextrw */ | |
3156 | [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ | |
3157 | [0x17] = SSE41_SPECIAL, /* extractps */ | |
3158 | [0x20] = SSE41_SPECIAL, /* pinsrb */ | |
3159 | [0x21] = SSE41_SPECIAL, /* insertps */ | |
3160 | [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ | |
3161 | [0x40] = SSE41_OP(dpps), | |
3162 | [0x41] = SSE41_OP(dppd), | |
3163 | [0x42] = SSE41_OP(mpsadbw), | |
3164 | [0x60] = SSE42_OP(pcmpestrm), | |
3165 | [0x61] = SSE42_OP(pcmpestri), | |
3166 | [0x62] = SSE42_OP(pcmpistrm), | |
3167 | [0x63] = SSE42_OP(pcmpistri), | |
4242b1bd AZ |
3168 | }; |
3169 | ||
664e0f19 FB |
3170 | static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) |
3171 | { | |
3172 | int b1, op1_offset, op2_offset, is_xmm, val, ot; | |
3173 | int modrm, mod, rm, reg, reg_addr, offset_addr; | |
d3eb5eae BS |
3174 | SSEFunc_0_epp sse_fn_epp; |
3175 | SSEFunc_0_eppi sse_fn_eppi; | |
c4baa050 | 3176 | SSEFunc_0_ppi sse_fn_ppi; |
d3eb5eae | 3177 | SSEFunc_0_eppt sse_fn_eppt; |
664e0f19 FB |
3178 | |
3179 | b &= 0xff; | |
5fafdf24 | 3180 | if (s->prefix & PREFIX_DATA) |
664e0f19 | 3181 | b1 = 1; |
5fafdf24 | 3182 | else if (s->prefix & PREFIX_REPZ) |
664e0f19 | 3183 | b1 = 2; |
5fafdf24 | 3184 | else if (s->prefix & PREFIX_REPNZ) |
664e0f19 FB |
3185 | b1 = 3; |
3186 | else | |
3187 | b1 = 0; | |
d3eb5eae BS |
3188 | sse_fn_epp = sse_op_table1[b][b1]; |
3189 | if (!sse_fn_epp) { | |
664e0f19 | 3190 | goto illegal_op; |
c4baa050 | 3191 | } |
a35f3ec7 | 3192 | if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) { |
664e0f19 FB |
3193 | is_xmm = 1; |
3194 | } else { | |
3195 | if (b1 == 0) { | |
3196 | /* MMX case */ | |
3197 | is_xmm = 0; | |
3198 | } else { | |
3199 | is_xmm = 1; | |
3200 | } | |
3201 | } | |
3202 | /* simple MMX/SSE operation */ | |
3203 | if (s->flags & HF_TS_MASK) { | |
3204 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
3205 | return; | |
3206 | } | |
3207 | if (s->flags & HF_EM_MASK) { | |
3208 | illegal_op: | |
3209 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
3210 | return; | |
3211 | } | |
3212 | if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) | |
4242b1bd AZ |
3213 | if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) |
3214 | goto illegal_op; | |
e771edab AJ |
3215 | if (b == 0x0e) { |
3216 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) | |
3217 | goto illegal_op; | |
3218 | /* femms */ | |
d3eb5eae | 3219 | gen_helper_emms(cpu_env); |
e771edab AJ |
3220 | return; |
3221 | } | |
3222 | if (b == 0x77) { | |
3223 | /* emms */ | |
d3eb5eae | 3224 | gen_helper_emms(cpu_env); |
664e0f19 FB |
3225 | return; |
3226 | } | |
3227 | /* prepare MMX state (XXX: optimize by storing fptt and fptags in | |
3228 | the static cpu state) */ | |
3229 | if (!is_xmm) { | |
d3eb5eae | 3230 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3231 | } |
3232 | ||
92fc4b58 | 3233 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
3234 | reg = ((modrm >> 3) & 7); |
3235 | if (is_xmm) | |
3236 | reg |= rex_r; | |
3237 | mod = (modrm >> 6) & 3; | |
d3eb5eae | 3238 | if (sse_fn_epp == SSE_SPECIAL) { |
664e0f19 FB |
3239 | b |= (b1 << 8); |
3240 | switch(b) { | |
3241 | case 0x0e7: /* movntq */ | |
5fafdf24 | 3242 | if (mod == 3) |
664e0f19 FB |
3243 | goto illegal_op; |
3244 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3245 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3246 | break; |
3247 | case 0x1e7: /* movntdq */ | |
3248 | case 0x02b: /* movntps */ | |
3249 | case 0x12b: /* movntps */ | |
2e21e749 T |
3250 | if (mod == 3) |
3251 | goto illegal_op; | |
3252 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3253 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); | |
3254 | break; | |
465e9838 FB |
3255 | case 0x3f0: /* lddqu */ |
3256 | if (mod == 3) | |
664e0f19 FB |
3257 | goto illegal_op; |
3258 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
c2254920 | 3259 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 | 3260 | break; |
d9f4bb27 AP |
3261 | case 0x22b: /* movntss */ |
3262 | case 0x32b: /* movntsd */ | |
3263 | if (mod == 3) | |
3264 | goto illegal_op; | |
3265 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3266 | if (b1 & 1) { | |
3267 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, | |
3268 | xmm_regs[reg])); | |
3269 | } else { | |
3270 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3271 | xmm_regs[reg].XMM_L(0))); | |
3272 | gen_op_st_T0_A0(OT_LONG + s->mem_index); | |
3273 | } | |
3274 | break; | |
664e0f19 | 3275 | case 0x6e: /* movd mm, ea */ |
dabd98dd FB |
3276 | #ifdef TARGET_X86_64 |
3277 | if (s->dflag == 2) { | |
3278 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); | |
5af45186 | 3279 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); |
5fafdf24 | 3280 | } else |
dabd98dd FB |
3281 | #endif |
3282 | { | |
3283 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); | |
5af45186 FB |
3284 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3285 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
a7812ae4 PB |
3286 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
3287 | gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); | |
dabd98dd | 3288 | } |
664e0f19 FB |
3289 | break; |
3290 | case 0x16e: /* movd xmm, ea */ | |
dabd98dd FB |
3291 | #ifdef TARGET_X86_64 |
3292 | if (s->dflag == 2) { | |
3293 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); | |
5af45186 FB |
3294 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3295 | offsetof(CPUX86State,xmm_regs[reg])); | |
a7812ae4 | 3296 | gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); |
5fafdf24 | 3297 | } else |
dabd98dd FB |
3298 | #endif |
3299 | { | |
3300 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); | |
5af45186 FB |
3301 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3302 | offsetof(CPUX86State,xmm_regs[reg])); | |
b6abf97d | 3303 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 3304 | gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); |
dabd98dd | 3305 | } |
664e0f19 FB |
3306 | break; |
3307 | case 0x6f: /* movq mm, ea */ | |
3308 | if (mod != 3) { | |
3309 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3310 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3311 | } else { |
3312 | rm = (modrm & 7); | |
b6abf97d | 3313 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3314 | offsetof(CPUX86State,fpregs[rm].mmx)); |
b6abf97d | 3315 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, |
5af45186 | 3316 | offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3317 | } |
3318 | break; | |
3319 | case 0x010: /* movups */ | |
3320 | case 0x110: /* movupd */ | |
3321 | case 0x028: /* movaps */ | |
3322 | case 0x128: /* movapd */ | |
3323 | case 0x16f: /* movdqa xmm, ea */ | |
3324 | case 0x26f: /* movdqu xmm, ea */ | |
3325 | if (mod != 3) { | |
3326 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3327 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3328 | } else { |
3329 | rm = (modrm & 7) | REX_B(s); | |
3330 | gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), | |
3331 | offsetof(CPUX86State,xmm_regs[rm])); | |
3332 | } | |
3333 | break; | |
3334 | case 0x210: /* movss xmm, ea */ | |
3335 | if (mod != 3) { | |
3336 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 3337 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3338 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
664e0f19 | 3339 | gen_op_movl_T0_0(); |
651ba608 FB |
3340 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); |
3341 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3342 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3343 | } else { |
3344 | rm = (modrm & 7) | REX_B(s); | |
3345 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3346 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3347 | } | |
3348 | break; | |
3349 | case 0x310: /* movsd xmm, ea */ | |
3350 | if (mod != 3) { | |
3351 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3352 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 | 3353 | gen_op_movl_T0_0(); |
651ba608 FB |
3354 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); |
3355 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
664e0f19 FB |
3356 | } else { |
3357 | rm = (modrm & 7) | REX_B(s); | |
3358 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3359 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3360 | } | |
3361 | break; | |
3362 | case 0x012: /* movlps */ | |
3363 | case 0x112: /* movlpd */ | |
3364 | if (mod != 3) { | |
3365 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3366 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3367 | } else { |
3368 | /* movhlps */ | |
3369 | rm = (modrm & 7) | REX_B(s); | |
3370 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3371 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3372 | } | |
3373 | break; | |
465e9838 FB |
3374 | case 0x212: /* movsldup */ |
3375 | if (mod != 3) { | |
3376 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3377 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
465e9838 FB |
3378 | } else { |
3379 | rm = (modrm & 7) | REX_B(s); | |
3380 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3381 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); | |
3382 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3383 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); | |
3384 | } | |
3385 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3386 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3387 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3388 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); | |
3389 | break; | |
3390 | case 0x312: /* movddup */ | |
3391 | if (mod != 3) { | |
3392 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3393 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 FB |
3394 | } else { |
3395 | rm = (modrm & 7) | REX_B(s); | |
3396 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3397 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3398 | } | |
3399 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
ba6526df | 3400 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
465e9838 | 3401 | break; |
664e0f19 FB |
3402 | case 0x016: /* movhps */ |
3403 | case 0x116: /* movhpd */ | |
3404 | if (mod != 3) { | |
3405 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3406 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3407 | } else { |
3408 | /* movlhps */ | |
3409 | rm = (modrm & 7) | REX_B(s); | |
3410 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), | |
3411 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3412 | } | |
3413 | break; | |
3414 | case 0x216: /* movshdup */ | |
3415 | if (mod != 3) { | |
3416 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3417 | gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3418 | } else { |
3419 | rm = (modrm & 7) | REX_B(s); | |
3420 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), | |
3421 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); | |
3422 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), | |
3423 | offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); | |
3424 | } | |
3425 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), | |
3426 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); | |
3427 | gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), | |
3428 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); | |
3429 | break; | |
d9f4bb27 AP |
3430 | case 0x178: |
3431 | case 0x378: | |
3432 | { | |
3433 | int bit_index, field_length; | |
3434 | ||
3435 | if (b1 == 1 && reg != 0) | |
3436 | goto illegal_op; | |
92fc4b58 BS |
3437 | field_length = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F; |
3438 | bit_index = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F; | |
d9f4bb27 AP |
3439 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3440 | offsetof(CPUX86State,xmm_regs[reg])); | |
3441 | if (b1 == 1) | |
d3eb5eae BS |
3442 | gen_helper_extrq_i(cpu_env, cpu_ptr0, |
3443 | tcg_const_i32(bit_index), | |
3444 | tcg_const_i32(field_length)); | |
d9f4bb27 | 3445 | else |
d3eb5eae BS |
3446 | gen_helper_insertq_i(cpu_env, cpu_ptr0, |
3447 | tcg_const_i32(bit_index), | |
3448 | tcg_const_i32(field_length)); | |
d9f4bb27 AP |
3449 | } |
3450 | break; | |
664e0f19 | 3451 | case 0x7e: /* movd ea, mm */ |
dabd98dd FB |
3452 | #ifdef TARGET_X86_64 |
3453 | if (s->dflag == 2) { | |
5af45186 FB |
3454 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3455 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
dabd98dd | 3456 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3457 | } else |
dabd98dd FB |
3458 | #endif |
3459 | { | |
5af45186 FB |
3460 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3461 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); | |
dabd98dd FB |
3462 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); |
3463 | } | |
664e0f19 FB |
3464 | break; |
3465 | case 0x17e: /* movd ea, xmm */ | |
dabd98dd FB |
3466 | #ifdef TARGET_X86_64 |
3467 | if (s->dflag == 2) { | |
5af45186 FB |
3468 | tcg_gen_ld_i64(cpu_T[0], cpu_env, |
3469 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
dabd98dd | 3470 | gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); |
5fafdf24 | 3471 | } else |
dabd98dd FB |
3472 | #endif |
3473 | { | |
5af45186 FB |
3474 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, |
3475 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
dabd98dd FB |
3476 | gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); |
3477 | } | |
664e0f19 FB |
3478 | break; |
3479 | case 0x27e: /* movq xmm, ea */ | |
3480 | if (mod != 3) { | |
3481 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3482 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3483 | } else { |
3484 | rm = (modrm & 7) | REX_B(s); | |
3485 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3486 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
3487 | } | |
3488 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
3489 | break; | |
3490 | case 0x7f: /* movq ea, mm */ | |
3491 | if (mod != 3) { | |
3492 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3493 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
664e0f19 FB |
3494 | } else { |
3495 | rm = (modrm & 7); | |
3496 | gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), | |
3497 | offsetof(CPUX86State,fpregs[reg].mmx)); | |
3498 | } | |
3499 | break; | |
3500 | case 0x011: /* movups */ | |
3501 | case 0x111: /* movupd */ | |
3502 | case 0x029: /* movaps */ | |
3503 | case 0x129: /* movapd */ | |
3504 | case 0x17f: /* movdqa ea, xmm */ | |
3505 | case 0x27f: /* movdqu ea, xmm */ | |
3506 | if (mod != 3) { | |
3507 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3508 | gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); |
664e0f19 FB |
3509 | } else { |
3510 | rm = (modrm & 7) | REX_B(s); | |
3511 | gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), | |
3512 | offsetof(CPUX86State,xmm_regs[reg])); | |
3513 | } | |
3514 | break; | |
3515 | case 0x211: /* movss ea, xmm */ | |
3516 | if (mod != 3) { | |
3517 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
651ba608 | 3518 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); |
57fec1fe | 3519 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
664e0f19 FB |
3520 | } else { |
3521 | rm = (modrm & 7) | REX_B(s); | |
3522 | gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), | |
3523 | offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); | |
3524 | } | |
3525 | break; | |
3526 | case 0x311: /* movsd ea, xmm */ | |
3527 | if (mod != 3) { | |
3528 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3529 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3530 | } else { |
3531 | rm = (modrm & 7) | REX_B(s); | |
3532 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3533 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3534 | } | |
3535 | break; | |
3536 | case 0x013: /* movlps */ | |
3537 | case 0x113: /* movlpd */ | |
3538 | if (mod != 3) { | |
3539 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3540 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3541 | } else { |
3542 | goto illegal_op; | |
3543 | } | |
3544 | break; | |
3545 | case 0x017: /* movhps */ | |
3546 | case 0x117: /* movhpd */ | |
3547 | if (mod != 3) { | |
3548 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3549 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); |
664e0f19 FB |
3550 | } else { |
3551 | goto illegal_op; | |
3552 | } | |
3553 | break; | |
3554 | case 0x71: /* shift mm, im */ | |
3555 | case 0x72: | |
3556 | case 0x73: | |
3557 | case 0x171: /* shift xmm, im */ | |
3558 | case 0x172: | |
3559 | case 0x173: | |
c045af25 AK |
3560 | if (b1 >= 2) { |
3561 | goto illegal_op; | |
3562 | } | |
92fc4b58 | 3563 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
3564 | if (is_xmm) { |
3565 | gen_op_movl_T0_im(val); | |
651ba608 | 3566 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 | 3567 | gen_op_movl_T0_0(); |
651ba608 | 3568 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); |
664e0f19 FB |
3569 | op1_offset = offsetof(CPUX86State,xmm_t0); |
3570 | } else { | |
3571 | gen_op_movl_T0_im(val); | |
651ba608 | 3572 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); |
664e0f19 | 3573 | gen_op_movl_T0_0(); |
651ba608 | 3574 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); |
664e0f19 FB |
3575 | op1_offset = offsetof(CPUX86State,mmx_t0); |
3576 | } | |
d3eb5eae BS |
3577 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
3578 | (((modrm >> 3)) & 7)][b1]; | |
3579 | if (!sse_fn_epp) { | |
664e0f19 | 3580 | goto illegal_op; |
c4baa050 | 3581 | } |
664e0f19 FB |
3582 | if (is_xmm) { |
3583 | rm = (modrm & 7) | REX_B(s); | |
3584 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3585 | } else { | |
3586 | rm = (modrm & 7); | |
3587 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3588 | } | |
5af45186 FB |
3589 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3590 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); | |
d3eb5eae | 3591 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3592 | break; |
3593 | case 0x050: /* movmskps */ | |
664e0f19 | 3594 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3595 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3596 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3597 | gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3598 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3599 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3600 | break; |
3601 | case 0x150: /* movmskpd */ | |
664e0f19 | 3602 | rm = (modrm & 7) | REX_B(s); |
5af45186 FB |
3603 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
3604 | offsetof(CPUX86State,xmm_regs[rm])); | |
d3eb5eae | 3605 | gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3606 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
57fec1fe | 3607 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 FB |
3608 | break; |
3609 | case 0x02a: /* cvtpi2ps */ | |
3610 | case 0x12a: /* cvtpi2pd */ | |
d3eb5eae | 3611 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3612 | if (mod != 3) { |
3613 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3614 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
8686c490 | 3615 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3616 | } else { |
3617 | rm = (modrm & 7); | |
3618 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3619 | } | |
3620 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 FB |
3621 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3622 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3623 | switch(b >> 8) { |
3624 | case 0x0: | |
d3eb5eae | 3625 | gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3626 | break; |
3627 | default: | |
3628 | case 0x1: | |
d3eb5eae | 3629 | gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3630 | break; |
3631 | } | |
3632 | break; | |
3633 | case 0x22a: /* cvtsi2ss */ | |
3634 | case 0x32a: /* cvtsi2sd */ | |
3635 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3636 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
3637 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
5af45186 | 3638 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
28e10711 | 3639 | if (ot == OT_LONG) { |
d3eb5eae | 3640 | SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1]; |
28e10711 | 3641 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 3642 | sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32); |
28e10711 | 3643 | } else { |
11f8cdbc | 3644 | #ifdef TARGET_X86_64 |
d3eb5eae BS |
3645 | SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1]; |
3646 | sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]); | |
11f8cdbc SW |
3647 | #else |
3648 | goto illegal_op; | |
3649 | #endif | |
28e10711 | 3650 | } |
664e0f19 FB |
3651 | break; |
3652 | case 0x02c: /* cvttps2pi */ | |
3653 | case 0x12c: /* cvttpd2pi */ | |
3654 | case 0x02d: /* cvtps2pi */ | |
3655 | case 0x12d: /* cvtpd2pi */ | |
d3eb5eae | 3656 | gen_helper_enter_mmx(cpu_env); |
664e0f19 FB |
3657 | if (mod != 3) { |
3658 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3659 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
8686c490 | 3660 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
3661 | } else { |
3662 | rm = (modrm & 7) | REX_B(s); | |
3663 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3664 | } | |
3665 | op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx); | |
5af45186 FB |
3666 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3667 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
664e0f19 FB |
3668 | switch(b) { |
3669 | case 0x02c: | |
d3eb5eae | 3670 | gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3671 | break; |
3672 | case 0x12c: | |
d3eb5eae | 3673 | gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3674 | break; |
3675 | case 0x02d: | |
d3eb5eae | 3676 | gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3677 | break; |
3678 | case 0x12d: | |
d3eb5eae | 3679 | gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
3680 | break; |
3681 | } | |
3682 | break; | |
3683 | case 0x22c: /* cvttss2si */ | |
3684 | case 0x32c: /* cvttsd2si */ | |
3685 | case 0x22d: /* cvtss2si */ | |
3686 | case 0x32d: /* cvtsd2si */ | |
3687 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
31313213 FB |
3688 | if (mod != 3) { |
3689 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3690 | if ((b >> 8) & 1) { | |
8686c490 | 3691 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); |
31313213 | 3692 | } else { |
57fec1fe | 3693 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 3694 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
31313213 FB |
3695 | } |
3696 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3697 | } else { | |
3698 | rm = (modrm & 7) | REX_B(s); | |
3699 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
3700 | } | |
5af45186 FB |
3701 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
3702 | if (ot == OT_LONG) { | |
d3eb5eae | 3703 | SSEFunc_i_ep sse_fn_i_ep = |
bedc2ac1 | 3704 | sse_op_table3bi[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3705 | sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
b6abf97d | 3706 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
5af45186 | 3707 | } else { |
11f8cdbc | 3708 | #ifdef TARGET_X86_64 |
d3eb5eae | 3709 | SSEFunc_l_ep sse_fn_l_ep = |
bedc2ac1 | 3710 | sse_op_table3bq[((b >> 7) & 2) | (b & 1)]; |
d3eb5eae | 3711 | sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0); |
11f8cdbc SW |
3712 | #else |
3713 | goto illegal_op; | |
3714 | #endif | |
5af45186 | 3715 | } |
57fec1fe | 3716 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3717 | break; |
3718 | case 0xc4: /* pinsrw */ | |
5fafdf24 | 3719 | case 0x1c4: |
d1e42c5c | 3720 | s->rip_offset = 1; |
664e0f19 | 3721 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
92fc4b58 | 3722 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
3723 | if (b1) { |
3724 | val &= 7; | |
5af45186 FB |
3725 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3726 | offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); | |
664e0f19 FB |
3727 | } else { |
3728 | val &= 3; | |
5af45186 FB |
3729 | tcg_gen_st16_tl(cpu_T[0], cpu_env, |
3730 | offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val))); | |
664e0f19 FB |
3731 | } |
3732 | break; | |
3733 | case 0xc5: /* pextrw */ | |
5fafdf24 | 3734 | case 0x1c5: |
664e0f19 FB |
3735 | if (mod != 3) |
3736 | goto illegal_op; | |
6dc2d0da | 3737 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
92fc4b58 | 3738 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
3739 | if (b1) { |
3740 | val &= 7; | |
3741 | rm = (modrm & 7) | REX_B(s); | |
5af45186 FB |
3742 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3743 | offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); | |
664e0f19 FB |
3744 | } else { |
3745 | val &= 3; | |
3746 | rm = (modrm & 7); | |
5af45186 FB |
3747 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, |
3748 | offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); | |
664e0f19 FB |
3749 | } |
3750 | reg = ((modrm >> 3) & 7) | rex_r; | |
6dc2d0da | 3751 | gen_op_mov_reg_T0(ot, reg); |
664e0f19 FB |
3752 | break; |
3753 | case 0x1d6: /* movq ea, xmm */ | |
3754 | if (mod != 3) { | |
3755 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
8686c490 | 3756 | gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); |
664e0f19 FB |
3757 | } else { |
3758 | rm = (modrm & 7) | REX_B(s); | |
3759 | gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), | |
3760 | offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); | |
3761 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); | |
3762 | } | |
3763 | break; | |
3764 | case 0x2d6: /* movq2dq */ | |
d3eb5eae | 3765 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3766 | rm = (modrm & 7); |
3767 | gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), | |
3768 | offsetof(CPUX86State,fpregs[rm].mmx)); | |
3769 | gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); | |
664e0f19 FB |
3770 | break; |
3771 | case 0x3d6: /* movdq2q */ | |
d3eb5eae | 3772 | gen_helper_enter_mmx(cpu_env); |
480c1cdb FB |
3773 | rm = (modrm & 7) | REX_B(s); |
3774 | gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), | |
3775 | offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); | |
664e0f19 FB |
3776 | break; |
3777 | case 0xd7: /* pmovmskb */ | |
3778 | case 0x1d7: | |
3779 | if (mod != 3) | |
3780 | goto illegal_op; | |
3781 | if (b1) { | |
3782 | rm = (modrm & 7) | REX_B(s); | |
5af45186 | 3783 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
d3eb5eae | 3784 | gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 FB |
3785 | } else { |
3786 | rm = (modrm & 7); | |
5af45186 | 3787 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
d3eb5eae | 3788 | gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0); |
664e0f19 | 3789 | } |
b6abf97d | 3790 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
664e0f19 | 3791 | reg = ((modrm >> 3) & 7) | rex_r; |
57fec1fe | 3792 | gen_op_mov_reg_T0(OT_LONG, reg); |
664e0f19 | 3793 | break; |
4242b1bd | 3794 | case 0x138: |
000cacf6 AZ |
3795 | if (s->prefix & PREFIX_REPNZ) |
3796 | goto crc32; | |
3797 | case 0x038: | |
4242b1bd | 3798 | b = modrm; |
92fc4b58 | 3799 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
4242b1bd AZ |
3800 | rm = modrm & 7; |
3801 | reg = ((modrm >> 3) & 7) | rex_r; | |
3802 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3803 | if (b1 >= 2) { |
3804 | goto illegal_op; | |
3805 | } | |
4242b1bd | 3806 | |
d3eb5eae BS |
3807 | sse_fn_epp = sse_op_table6[b].op[b1]; |
3808 | if (!sse_fn_epp) { | |
4242b1bd | 3809 | goto illegal_op; |
c4baa050 | 3810 | } |
222a3336 AZ |
3811 | if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) |
3812 | goto illegal_op; | |
4242b1bd AZ |
3813 | |
3814 | if (b1) { | |
3815 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
3816 | if (mod == 3) { | |
3817 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
3818 | } else { | |
3819 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
3820 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
222a3336 AZ |
3821 | switch (b) { |
3822 | case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ | |
3823 | case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ | |
3824 | case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ | |
3825 | gen_ldq_env_A0(s->mem_index, op2_offset + | |
3826 | offsetof(XMMReg, XMM_Q(0))); | |
3827 | break; | |
3828 | case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ | |
3829 | case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ | |
a7812ae4 | 3830 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 3831 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3832 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
3833 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + |
3834 | offsetof(XMMReg, XMM_L(0))); | |
3835 | break; | |
3836 | case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ | |
3837 | tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, | |
3838 | (s->mem_index >> 2) - 1); | |
3839 | tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + | |
3840 | offsetof(XMMReg, XMM_W(0))); | |
3841 | break; | |
3842 | case 0x2a: /* movntqda */ | |
3843 | gen_ldo_env_A0(s->mem_index, op1_offset); | |
3844 | return; | |
3845 | default: | |
3846 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
3847 | } | |
4242b1bd AZ |
3848 | } |
3849 | } else { | |
3850 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
3851 | if (mod == 3) { | |
3852 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
3853 | } else { | |
3854 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
3855 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3856 | gen_ldq_env_A0(s->mem_index, op2_offset); | |
3857 | } | |
3858 | } | |
d3eb5eae | 3859 | if (sse_fn_epp == SSE_SPECIAL) { |
222a3336 | 3860 | goto illegal_op; |
c4baa050 | 3861 | } |
222a3336 | 3862 | |
4242b1bd AZ |
3863 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
3864 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 3865 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
222a3336 AZ |
3866 | |
3867 | if (b == 0x17) | |
3868 | s->cc_op = CC_OP_EFLAGS; | |
4242b1bd | 3869 | break; |
222a3336 AZ |
3870 | case 0x338: /* crc32 */ |
3871 | crc32: | |
3872 | b = modrm; | |
92fc4b58 | 3873 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
222a3336 AZ |
3874 | reg = ((modrm >> 3) & 7) | rex_r; |
3875 | ||
3876 | if (b != 0xf0 && b != 0xf1) | |
3877 | goto illegal_op; | |
3878 | if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) | |
4242b1bd AZ |
3879 | goto illegal_op; |
3880 | ||
222a3336 AZ |
3881 | if (b == 0xf0) |
3882 | ot = OT_BYTE; | |
3883 | else if (b == 0xf1 && s->dflag != 2) | |
3884 | if (s->prefix & PREFIX_DATA) | |
3885 | ot = OT_WORD; | |
3886 | else | |
3887 | ot = OT_LONG; | |
3888 | else | |
3889 | ot = OT_QUAD; | |
3890 | ||
3891 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
3892 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); | |
3893 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
a7812ae4 PB |
3894 | gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, |
3895 | cpu_T[0], tcg_const_i32(8 << ot)); | |
222a3336 AZ |
3896 | |
3897 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; | |
3898 | gen_op_mov_reg_T0(ot, reg); | |
3899 | break; | |
3900 | case 0x03a: | |
3901 | case 0x13a: | |
4242b1bd | 3902 | b = modrm; |
92fc4b58 | 3903 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
4242b1bd AZ |
3904 | rm = modrm & 7; |
3905 | reg = ((modrm >> 3) & 7) | rex_r; | |
3906 | mod = (modrm >> 6) & 3; | |
c045af25 AK |
3907 | if (b1 >= 2) { |
3908 | goto illegal_op; | |
3909 | } | |
4242b1bd | 3910 | |
d3eb5eae BS |
3911 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
3912 | if (!sse_fn_eppi) { | |
4242b1bd | 3913 | goto illegal_op; |
c4baa050 | 3914 | } |
222a3336 AZ |
3915 | if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) |
3916 | goto illegal_op; | |
3917 | ||
d3eb5eae | 3918 | if (sse_fn_eppi == SSE_SPECIAL) { |
222a3336 AZ |
3919 | ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; |
3920 | rm = (modrm & 7) | REX_B(s); | |
3921 | if (mod != 3) | |
3922 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
3923 | reg = ((modrm >> 3) & 7) | rex_r; | |
92fc4b58 | 3924 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
222a3336 AZ |
3925 | switch (b) { |
3926 | case 0x14: /* pextrb */ | |
3927 | tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3928 | xmm_regs[reg].XMM_B(val & 15))); | |
3929 | if (mod == 3) | |
3930 | gen_op_mov_reg_T0(ot, rm); | |
3931 | else | |
3932 | tcg_gen_qemu_st8(cpu_T[0], cpu_A0, | |
3933 | (s->mem_index >> 2) - 1); | |
3934 | break; | |
3935 | case 0x15: /* pextrw */ | |
3936 | tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3937 | xmm_regs[reg].XMM_W(val & 7))); | |
3938 | if (mod == 3) | |
3939 | gen_op_mov_reg_T0(ot, rm); | |
3940 | else | |
3941 | tcg_gen_qemu_st16(cpu_T[0], cpu_A0, | |
3942 | (s->mem_index >> 2) - 1); | |
3943 | break; | |
3944 | case 0x16: | |
3945 | if (ot == OT_LONG) { /* pextrd */ | |
3946 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, | |
3947 | offsetof(CPUX86State, | |
3948 | xmm_regs[reg].XMM_L(val & 3))); | |
a7812ae4 | 3949 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
222a3336 | 3950 | if (mod == 3) |
a7812ae4 | 3951 | gen_op_mov_reg_v(ot, rm, cpu_T[0]); |
222a3336 | 3952 | else |
a7812ae4 | 3953 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, |
222a3336 AZ |
3954 | (s->mem_index >> 2) - 1); |
3955 | } else { /* pextrq */ | |
a7812ae4 | 3956 | #ifdef TARGET_X86_64 |
222a3336 AZ |
3957 | tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, |
3958 | offsetof(CPUX86State, | |
3959 | xmm_regs[reg].XMM_Q(val & 1))); | |
3960 | if (mod == 3) | |
3961 | gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); | |
3962 | else | |
3963 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, | |
3964 | (s->mem_index >> 2) - 1); | |
a7812ae4 PB |
3965 | #else |
3966 | goto illegal_op; | |
3967 | #endif | |
222a3336 AZ |
3968 | } |
3969 | break; | |
3970 | case 0x17: /* extractps */ | |
3971 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, | |
3972 | xmm_regs[reg].XMM_L(val & 3))); | |
3973 | if (mod == 3) | |
3974 | gen_op_mov_reg_T0(ot, rm); | |
3975 | else | |
3976 | tcg_gen_qemu_st32(cpu_T[0], cpu_A0, | |
3977 | (s->mem_index >> 2) - 1); | |
3978 | break; | |
3979 | case 0x20: /* pinsrb */ | |
3980 | if (mod == 3) | |
3981 | gen_op_mov_TN_reg(OT_LONG, 0, rm); | |
3982 | else | |
a7812ae4 | 3983 | tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, |
222a3336 | 3984 | (s->mem_index >> 2) - 1); |
a7812ae4 | 3985 | tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, |
222a3336 AZ |
3986 | xmm_regs[reg].XMM_B(val & 15))); |
3987 | break; | |
3988 | case 0x21: /* insertps */ | |
a7812ae4 | 3989 | if (mod == 3) { |
222a3336 AZ |
3990 | tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, |
3991 | offsetof(CPUX86State,xmm_regs[rm] | |
3992 | .XMM_L((val >> 6) & 3))); | |
a7812ae4 PB |
3993 | } else { |
3994 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, | |
222a3336 | 3995 | (s->mem_index >> 2) - 1); |
a7812ae4 PB |
3996 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
3997 | } | |
222a3336 AZ |
3998 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
3999 | offsetof(CPUX86State,xmm_regs[reg] | |
4000 | .XMM_L((val >> 4) & 3))); | |
4001 | if ((val >> 0) & 1) | |
4002 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4003 | cpu_env, offsetof(CPUX86State, | |
4004 | xmm_regs[reg].XMM_L(0))); | |
4005 | if ((val >> 1) & 1) | |
4006 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4007 | cpu_env, offsetof(CPUX86State, | |
4008 | xmm_regs[reg].XMM_L(1))); | |
4009 | if ((val >> 2) & 1) | |
4010 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4011 | cpu_env, offsetof(CPUX86State, | |
4012 | xmm_regs[reg].XMM_L(2))); | |
4013 | if ((val >> 3) & 1) | |
4014 | tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), | |
4015 | cpu_env, offsetof(CPUX86State, | |
4016 | xmm_regs[reg].XMM_L(3))); | |
4017 | break; | |
4018 | case 0x22: | |
4019 | if (ot == OT_LONG) { /* pinsrd */ | |
4020 | if (mod == 3) | |
a7812ae4 | 4021 | gen_op_mov_v_reg(ot, cpu_tmp0, rm); |
222a3336 | 4022 | else |
a7812ae4 | 4023 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, |
222a3336 | 4024 | (s->mem_index >> 2) - 1); |
a7812ae4 | 4025 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); |
222a3336 AZ |
4026 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, |
4027 | offsetof(CPUX86State, | |
4028 | xmm_regs[reg].XMM_L(val & 3))); | |
4029 | } else { /* pinsrq */ | |
a7812ae4 | 4030 | #ifdef TARGET_X86_64 |
222a3336 AZ |
4031 | if (mod == 3) |
4032 | gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); | |
4033 | else | |
4034 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, | |
4035 | (s->mem_index >> 2) - 1); | |
4036 | tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, | |
4037 | offsetof(CPUX86State, | |
4038 | xmm_regs[reg].XMM_Q(val & 1))); | |
a7812ae4 PB |
4039 | #else |
4040 | goto illegal_op; | |
4041 | #endif | |
222a3336 AZ |
4042 | } |
4043 | break; | |
4044 | } | |
4045 | return; | |
4046 | } | |
4242b1bd AZ |
4047 | |
4048 | if (b1) { | |
4049 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4050 | if (mod == 3) { | |
4051 | op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); | |
4052 | } else { | |
4053 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
4054 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4055 | gen_ldo_env_A0(s->mem_index, op2_offset); | |
4056 | } | |
4057 | } else { | |
4058 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4059 | if (mod == 3) { | |
4060 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4061 | } else { | |
4062 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
4063 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4064 | gen_ldq_env_A0(s->mem_index, op2_offset); | |
4065 | } | |
4066 | } | |
92fc4b58 | 4067 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
4242b1bd | 4068 | |
222a3336 AZ |
4069 | if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ |
4070 | s->cc_op = CC_OP_EFLAGS; | |
4071 | ||
4072 | if (s->dflag == 2) | |
4073 | /* The helper must use entire 64-bit gp registers */ | |
4074 | val |= 1 << 8; | |
4075 | } | |
4076 | ||
4242b1bd AZ |
4077 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4078 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4079 | sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
4242b1bd | 4080 | break; |
664e0f19 FB |
4081 | default: |
4082 | goto illegal_op; | |
4083 | } | |
4084 | } else { | |
4085 | /* generic MMX or SSE operation */ | |
d1e42c5c | 4086 | switch(b) { |
d1e42c5c FB |
4087 | case 0x70: /* pshufx insn */ |
4088 | case 0xc6: /* pshufx insn */ | |
4089 | case 0xc2: /* compare insns */ | |
4090 | s->rip_offset = 1; | |
4091 | break; | |
4092 | default: | |
4093 | break; | |
664e0f19 FB |
4094 | } |
4095 | if (is_xmm) { | |
4096 | op1_offset = offsetof(CPUX86State,xmm_regs[reg]); | |
4097 | if (mod != 3) { | |
4098 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4099 | op2_offset = offsetof(CPUX86State,xmm_t0); | |
480c1cdb | 4100 | if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || |
664e0f19 FB |
4101 | b == 0xc2)) { |
4102 | /* specific case for SSE single instructions */ | |
4103 | if (b1 == 2) { | |
4104 | /* 32 bit access */ | |
57fec1fe | 4105 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
651ba608 | 4106 | tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); |
664e0f19 FB |
4107 | } else { |
4108 | /* 64 bit access */ | |
8686c490 | 4109 | gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); |
664e0f19 FB |
4110 | } |
4111 | } else { | |
8686c490 | 4112 | gen_ldo_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4113 | } |
4114 | } else { | |
4115 | rm = (modrm & 7) | REX_B(s); | |
4116 | op2_offset = offsetof(CPUX86State,xmm_regs[rm]); | |
4117 | } | |
4118 | } else { | |
4119 | op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); | |
4120 | if (mod != 3) { | |
4121 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4122 | op2_offset = offsetof(CPUX86State,mmx_t0); | |
8686c490 | 4123 | gen_ldq_env_A0(s->mem_index, op2_offset); |
664e0f19 FB |
4124 | } else { |
4125 | rm = (modrm & 7); | |
4126 | op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); | |
4127 | } | |
4128 | } | |
4129 | switch(b) { | |
a35f3ec7 | 4130 | case 0x0f: /* 3DNow! data insns */ |
e771edab AJ |
4131 | if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) |
4132 | goto illegal_op; | |
92fc4b58 | 4133 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
d3eb5eae BS |
4134 | sse_fn_epp = sse_op_table5[val]; |
4135 | if (!sse_fn_epp) { | |
a35f3ec7 | 4136 | goto illegal_op; |
c4baa050 | 4137 | } |
5af45186 FB |
4138 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4139 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4140 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
a35f3ec7 | 4141 | break; |
664e0f19 FB |
4142 | case 0x70: /* pshufx insn */ |
4143 | case 0xc6: /* pshufx insn */ | |
92fc4b58 | 4144 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
5af45186 FB |
4145 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4146 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4147 | /* XXX: introduce a new table? */ |
d3eb5eae | 4148 | sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp; |
c4baa050 | 4149 | sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); |
664e0f19 FB |
4150 | break; |
4151 | case 0xc2: | |
4152 | /* compare insns */ | |
92fc4b58 | 4153 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
4154 | if (val >= 8) |
4155 | goto illegal_op; | |
d3eb5eae | 4156 | sse_fn_epp = sse_op_table4[val][b1]; |
c4baa050 | 4157 | |
5af45186 FB |
4158 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4159 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4160 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 | 4161 | break; |
b8b6a50b FB |
4162 | case 0xf7: |
4163 | /* maskmov : we must prepare A0 */ | |
4164 | if (mod != 3) | |
4165 | goto illegal_op; | |
4166 | #ifdef TARGET_X86_64 | |
4167 | if (s->aflag == 2) { | |
4168 | gen_op_movq_A0_reg(R_EDI); | |
4169 | } else | |
4170 | #endif | |
4171 | { | |
4172 | gen_op_movl_A0_reg(R_EDI); | |
4173 | if (s->aflag == 0) | |
4174 | gen_op_andl_A0_ffff(); | |
4175 | } | |
4176 | gen_add_A0_ds_seg(s); | |
4177 | ||
4178 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); | |
4179 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
c4baa050 | 4180 | /* XXX: introduce a new table? */ |
d3eb5eae BS |
4181 | sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp; |
4182 | sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0); | |
b8b6a50b | 4183 | break; |
664e0f19 | 4184 | default: |
5af45186 FB |
4185 | tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
4186 | tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); | |
d3eb5eae | 4187 | sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1); |
664e0f19 FB |
4188 | break; |
4189 | } | |
4190 | if (b == 0x2e || b == 0x2f) { | |
4191 | s->cc_op = CC_OP_EFLAGS; | |
4192 | } | |
4193 | } | |
4194 | } | |
4195 | ||
2c0262af FB |
4196 | /* convert one instruction. s->is_jmp is set if the translation must |
4197 | be stopped. Return the next pc value */ | |
14ce26e7 | 4198 | static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) |
2c0262af FB |
4199 | { |
4200 | int b, prefixes, aflag, dflag; | |
4201 | int shift, ot; | |
4202 | int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val; | |
14ce26e7 FB |
4203 | target_ulong next_eip, tval; |
4204 | int rex_w, rex_r; | |
2c0262af | 4205 | |
fdefe51c | 4206 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
70cff25e | 4207 | tcg_gen_debug_insn_start(pc_start); |
fdefe51c | 4208 | } |
2c0262af FB |
4209 | s->pc = pc_start; |
4210 | prefixes = 0; | |
4211 | aflag = s->code32; | |
4212 | dflag = s->code32; | |
4213 | s->override = -1; | |
14ce26e7 FB |
4214 | rex_w = -1; |
4215 | rex_r = 0; | |
4216 | #ifdef TARGET_X86_64 | |
4217 | s->rex_x = 0; | |
4218 | s->rex_b = 0; | |
5fafdf24 | 4219 | x86_64_hregs = 0; |
14ce26e7 FB |
4220 | #endif |
4221 | s->rip_offset = 0; /* for relative ip address */ | |
2c0262af | 4222 | next_byte: |
92fc4b58 | 4223 | b = cpu_ldub_code(cpu_single_env, s->pc); |
2c0262af FB |
4224 | s->pc++; |
4225 | /* check prefixes */ | |
14ce26e7 FB |
4226 | #ifdef TARGET_X86_64 |
4227 | if (CODE64(s)) { | |
4228 | switch (b) { | |
4229 | case 0xf3: | |
4230 | prefixes |= PREFIX_REPZ; | |
4231 | goto next_byte; | |
4232 | case 0xf2: | |
4233 | prefixes |= PREFIX_REPNZ; | |
4234 | goto next_byte; | |
4235 | case 0xf0: | |
4236 | prefixes |= PREFIX_LOCK; | |
4237 | goto next_byte; | |
4238 | case 0x2e: | |
4239 | s->override = R_CS; | |
4240 | goto next_byte; | |
4241 | case 0x36: | |
4242 | s->override = R_SS; | |
4243 | goto next_byte; | |
4244 | case 0x3e: | |
4245 | s->override = R_DS; | |
4246 | goto next_byte; | |
4247 | case 0x26: | |
4248 | s->override = R_ES; | |
4249 | goto next_byte; | |
4250 | case 0x64: | |
4251 | s->override = R_FS; | |
4252 | goto next_byte; | |
4253 | case 0x65: | |
4254 | s->override = R_GS; | |
4255 | goto next_byte; | |
4256 | case 0x66: | |
4257 | prefixes |= PREFIX_DATA; | |
4258 | goto next_byte; | |
4259 | case 0x67: | |
4260 | prefixes |= PREFIX_ADR; | |
4261 | goto next_byte; | |
4262 | case 0x40 ... 0x4f: | |
4263 | /* REX prefix */ | |
4264 | rex_w = (b >> 3) & 1; | |
4265 | rex_r = (b & 0x4) << 1; | |
4266 | s->rex_x = (b & 0x2) << 2; | |
4267 | REX_B(s) = (b & 0x1) << 3; | |
4268 | x86_64_hregs = 1; /* select uniform byte register addressing */ | |
4269 | goto next_byte; | |
4270 | } | |
4271 | if (rex_w == 1) { | |
4272 | /* 0x66 is ignored if rex.w is set */ | |
4273 | dflag = 2; | |
4274 | } else { | |
4275 | if (prefixes & PREFIX_DATA) | |
4276 | dflag ^= 1; | |
4277 | } | |
4278 | if (!(prefixes & PREFIX_ADR)) | |
4279 | aflag = 2; | |
5fafdf24 | 4280 | } else |
14ce26e7 FB |
4281 | #endif |
4282 | { | |
4283 | switch (b) { | |
4284 | case 0xf3: | |
4285 | prefixes |= PREFIX_REPZ; | |
4286 | goto next_byte; | |
4287 | case 0xf2: | |
4288 | prefixes |= PREFIX_REPNZ; | |
4289 | goto next_byte; | |
4290 | case 0xf0: | |
4291 | prefixes |= PREFIX_LOCK; | |
4292 | goto next_byte; | |
4293 | case 0x2e: | |
4294 | s->override = R_CS; | |
4295 | goto next_byte; | |
4296 | case 0x36: | |
4297 | s->override = R_SS; | |
4298 | goto next_byte; | |
4299 | case 0x3e: | |
4300 | s->override = R_DS; | |
4301 | goto next_byte; | |
4302 | case 0x26: | |
4303 | s->override = R_ES; | |
4304 | goto next_byte; | |
4305 | case 0x64: | |
4306 | s->override = R_FS; | |
4307 | goto next_byte; | |
4308 | case 0x65: | |
4309 | s->override = R_GS; | |
4310 | goto next_byte; | |
4311 | case 0x66: | |
4312 | prefixes |= PREFIX_DATA; | |
4313 | goto next_byte; | |
4314 | case 0x67: | |
4315 | prefixes |= PREFIX_ADR; | |
4316 | goto next_byte; | |
4317 | } | |
4318 | if (prefixes & PREFIX_DATA) | |
4319 | dflag ^= 1; | |
4320 | if (prefixes & PREFIX_ADR) | |
4321 | aflag ^= 1; | |
2c0262af FB |
4322 | } |
4323 | ||
2c0262af FB |
4324 | s->prefix = prefixes; |
4325 | s->aflag = aflag; | |
4326 | s->dflag = dflag; | |
4327 | ||
4328 | /* lock generation */ | |
4329 | if (prefixes & PREFIX_LOCK) | |
a7812ae4 | 4330 | gen_helper_lock(); |
2c0262af FB |
4331 | |
4332 | /* now check op code */ | |
4333 | reswitch: | |
4334 | switch(b) { | |
4335 | case 0x0f: | |
4336 | /**************************/ | |
4337 | /* extended op code */ | |
92fc4b58 | 4338 | b = cpu_ldub_code(cpu_single_env, s->pc++) | 0x100; |
2c0262af | 4339 | goto reswitch; |
3b46e624 | 4340 | |
2c0262af FB |
4341 | /**************************/ |
4342 | /* arith & logic */ | |
4343 | case 0x00 ... 0x05: | |
4344 | case 0x08 ... 0x0d: | |
4345 | case 0x10 ... 0x15: | |
4346 | case 0x18 ... 0x1d: | |
4347 | case 0x20 ... 0x25: | |
4348 | case 0x28 ... 0x2d: | |
4349 | case 0x30 ... 0x35: | |
4350 | case 0x38 ... 0x3d: | |
4351 | { | |
4352 | int op, f, val; | |
4353 | op = (b >> 3) & 7; | |
4354 | f = (b >> 1) & 3; | |
4355 | ||
4356 | if ((b & 1) == 0) | |
4357 | ot = OT_BYTE; | |
4358 | else | |
14ce26e7 | 4359 | ot = dflag + OT_WORD; |
3b46e624 | 4360 | |
2c0262af FB |
4361 | switch(f) { |
4362 | case 0: /* OP Ev, Gv */ | |
92fc4b58 | 4363 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 4364 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 4365 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4366 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4367 | if (mod != 3) { |
4368 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4369 | opreg = OR_TMP0; | |
4370 | } else if (op == OP_XORL && rm == reg) { | |
4371 | xor_zero: | |
4372 | /* xor reg, reg optimisation */ | |
4373 | gen_op_movl_T0_0(); | |
4374 | s->cc_op = CC_OP_LOGICB + ot; | |
57fec1fe | 4375 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
4376 | gen_op_update1_cc(); |
4377 | break; | |
4378 | } else { | |
4379 | opreg = rm; | |
4380 | } | |
57fec1fe | 4381 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4382 | gen_op(s, op, ot, opreg); |
4383 | break; | |
4384 | case 1: /* OP Gv, Ev */ | |
92fc4b58 | 4385 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 4386 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
4387 | reg = ((modrm >> 3) & 7) | rex_r; |
4388 | rm = (modrm & 7) | REX_B(s); | |
2c0262af FB |
4389 | if (mod != 3) { |
4390 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 4391 | gen_op_ld_T1_A0(ot + s->mem_index); |
2c0262af FB |
4392 | } else if (op == OP_XORL && rm == reg) { |
4393 | goto xor_zero; | |
4394 | } else { | |
57fec1fe | 4395 | gen_op_mov_TN_reg(ot, 1, rm); |
2c0262af FB |
4396 | } |
4397 | gen_op(s, op, ot, reg); | |
4398 | break; | |
4399 | case 2: /* OP A, Iv */ | |
4400 | val = insn_get(s, ot); | |
4401 | gen_op_movl_T1_im(val); | |
4402 | gen_op(s, op, ot, OR_EAX); | |
4403 | break; | |
4404 | } | |
4405 | } | |
4406 | break; | |
4407 | ||
ec9d6075 FB |
4408 | case 0x82: |
4409 | if (CODE64(s)) | |
4410 | goto illegal_op; | |
2c0262af FB |
4411 | case 0x80: /* GRP1 */ |
4412 | case 0x81: | |
4413 | case 0x83: | |
4414 | { | |
4415 | int val; | |
4416 | ||
4417 | if ((b & 1) == 0) | |
4418 | ot = OT_BYTE; | |
4419 | else | |
14ce26e7 | 4420 | ot = dflag + OT_WORD; |
3b46e624 | 4421 | |
92fc4b58 | 4422 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 4423 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4424 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 4425 | op = (modrm >> 3) & 7; |
3b46e624 | 4426 | |
2c0262af | 4427 | if (mod != 3) { |
14ce26e7 FB |
4428 | if (b == 0x83) |
4429 | s->rip_offset = 1; | |
4430 | else | |
4431 | s->rip_offset = insn_const_size(ot); | |
2c0262af FB |
4432 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
4433 | opreg = OR_TMP0; | |
4434 | } else { | |
14ce26e7 | 4435 | opreg = rm; |
2c0262af FB |
4436 | } |
4437 | ||
4438 | switch(b) { | |
4439 | default: | |
4440 | case 0x80: | |
4441 | case 0x81: | |
d64477af | 4442 | case 0x82: |
2c0262af FB |
4443 | val = insn_get(s, ot); |
4444 | break; | |
4445 | case 0x83: | |
4446 | val = (int8_t)insn_get(s, OT_BYTE); | |
4447 | break; | |
4448 | } | |
4449 | gen_op_movl_T1_im(val); | |
4450 | gen_op(s, op, ot, opreg); | |
4451 | } | |
4452 | break; | |
4453 | ||
4454 | /**************************/ | |
4455 | /* inc, dec, and other misc arith */ | |
4456 | case 0x40 ... 0x47: /* inc Gv */ | |
4457 | ot = dflag ? OT_LONG : OT_WORD; | |
4458 | gen_inc(s, ot, OR_EAX + (b & 7), 1); | |
4459 | break; | |
4460 | case 0x48 ... 0x4f: /* dec Gv */ | |
4461 | ot = dflag ? OT_LONG : OT_WORD; | |
4462 | gen_inc(s, ot, OR_EAX + (b & 7), -1); | |
4463 | break; | |
4464 | case 0xf6: /* GRP3 */ | |
4465 | case 0xf7: | |
4466 | if ((b & 1) == 0) | |
4467 | ot = OT_BYTE; | |
4468 | else | |
14ce26e7 | 4469 | ot = dflag + OT_WORD; |
2c0262af | 4470 | |
92fc4b58 | 4471 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 4472 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4473 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4474 | op = (modrm >> 3) & 7; |
4475 | if (mod != 3) { | |
14ce26e7 FB |
4476 | if (op == 0) |
4477 | s->rip_offset = insn_const_size(ot); | |
2c0262af | 4478 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 4479 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4480 | } else { |
57fec1fe | 4481 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4482 | } |
4483 | ||
4484 | switch(op) { | |
4485 | case 0: /* test */ | |
4486 | val = insn_get(s, ot); | |
4487 | gen_op_movl_T1_im(val); | |
4488 | gen_op_testl_T0_T1_cc(); | |
4489 | s->cc_op = CC_OP_LOGICB + ot; | |
4490 | break; | |
4491 | case 2: /* not */ | |
b6abf97d | 4492 | tcg_gen_not_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4493 | if (mod != 3) { |
57fec1fe | 4494 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4495 | } else { |
57fec1fe | 4496 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4497 | } |
4498 | break; | |
4499 | case 3: /* neg */ | |
b6abf97d | 4500 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); |
2c0262af | 4501 | if (mod != 3) { |
57fec1fe | 4502 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 4503 | } else { |
57fec1fe | 4504 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
4505 | } |
4506 | gen_op_update_neg_cc(); | |
4507 | s->cc_op = CC_OP_SUBB + ot; | |
4508 | break; | |
4509 | case 4: /* mul */ | |
4510 | switch(ot) { | |
4511 | case OT_BYTE: | |
0211e5af FB |
4512 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4513 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); | |
4514 | tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); | |
4515 | /* XXX: use 32 bit mul which could be faster */ | |
4516 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4517 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4518 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4519 | tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); | |
d36cd60e | 4520 | s->cc_op = CC_OP_MULB; |
2c0262af FB |
4521 | break; |
4522 | case OT_WORD: | |
0211e5af FB |
4523 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4524 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); | |
4525 | tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); | |
4526 | /* XXX: use 32 bit mul which could be faster */ | |
4527 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4528 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4529 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4530 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4531 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4532 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
d36cd60e | 4533 | s->cc_op = CC_OP_MULW; |
2c0262af FB |
4534 | break; |
4535 | default: | |
4536 | case OT_LONG: | |
0211e5af FB |
4537 | #ifdef TARGET_X86_64 |
4538 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4539 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); | |
4540 | tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); | |
4541 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4542 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4543 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4544 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4545 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4546 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4547 | #else | |
4548 | { | |
a7812ae4 PB |
4549 | TCGv_i64 t0, t1; |
4550 | t0 = tcg_temp_new_i64(); | |
4551 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4552 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4553 | tcg_gen_extu_i32_i64(t0, cpu_T[0]); | |
4554 | tcg_gen_extu_i32_i64(t1, cpu_T[1]); | |
4555 | tcg_gen_mul_i64(t0, t0, t1); | |
4556 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4557 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4558 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4559 | tcg_gen_shri_i64(t0, t0, 32); | |
4560 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4561 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4562 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | |
4563 | } | |
4564 | #endif | |
d36cd60e | 4565 | s->cc_op = CC_OP_MULL; |
2c0262af | 4566 | break; |
14ce26e7 FB |
4567 | #ifdef TARGET_X86_64 |
4568 | case OT_QUAD: | |
7923057b | 4569 | gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4570 | s->cc_op = CC_OP_MULQ; |
4571 | break; | |
4572 | #endif | |
2c0262af | 4573 | } |
2c0262af FB |
4574 | break; |
4575 | case 5: /* imul */ | |
4576 | switch(ot) { | |
4577 | case OT_BYTE: | |
0211e5af FB |
4578 | gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); |
4579 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4580 | tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); | |
4581 | /* XXX: use 32 bit mul which could be faster */ | |
4582 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4583 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4584 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4585 | tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); | |
4586 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
d36cd60e | 4587 | s->cc_op = CC_OP_MULB; |
2c0262af FB |
4588 | break; |
4589 | case OT_WORD: | |
0211e5af FB |
4590 | gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); |
4591 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4592 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4593 | /* XXX: use 32 bit mul which could be faster */ | |
4594 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4595 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4596 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4597 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4598 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4599 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); | |
4600 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
d36cd60e | 4601 | s->cc_op = CC_OP_MULW; |
2c0262af FB |
4602 | break; |
4603 | default: | |
4604 | case OT_LONG: | |
0211e5af FB |
4605 | #ifdef TARGET_X86_64 |
4606 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); | |
4607 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4608 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4609 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4610 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4611 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4612 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4613 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4614 | tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); | |
4615 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4616 | #else | |
4617 | { | |
a7812ae4 PB |
4618 | TCGv_i64 t0, t1; |
4619 | t0 = tcg_temp_new_i64(); | |
4620 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4621 | gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); |
4622 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); | |
4623 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4624 | tcg_gen_mul_i64(t0, t0, t1); | |
4625 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4626 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4627 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4628 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4629 | tcg_gen_shri_i64(t0, t0, 32); | |
4630 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4631 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4632 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4633 | } | |
4634 | #endif | |
d36cd60e | 4635 | s->cc_op = CC_OP_MULL; |
2c0262af | 4636 | break; |
14ce26e7 FB |
4637 | #ifdef TARGET_X86_64 |
4638 | case OT_QUAD: | |
7923057b | 4639 | gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4640 | s->cc_op = CC_OP_MULQ; |
4641 | break; | |
4642 | #endif | |
2c0262af | 4643 | } |
2c0262af FB |
4644 | break; |
4645 | case 6: /* div */ | |
4646 | switch(ot) { | |
4647 | case OT_BYTE: | |
14ce26e7 | 4648 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4649 | gen_helper_divb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4650 | break; |
4651 | case OT_WORD: | |
14ce26e7 | 4652 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4653 | gen_helper_divw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4654 | break; |
4655 | default: | |
4656 | case OT_LONG: | |
14ce26e7 | 4657 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4658 | gen_helper_divl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4659 | break; |
4660 | #ifdef TARGET_X86_64 | |
4661 | case OT_QUAD: | |
4662 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4663 | gen_helper_divq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4664 | break; |
14ce26e7 | 4665 | #endif |
2c0262af FB |
4666 | } |
4667 | break; | |
4668 | case 7: /* idiv */ | |
4669 | switch(ot) { | |
4670 | case OT_BYTE: | |
14ce26e7 | 4671 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4672 | gen_helper_idivb_AL(cpu_env, cpu_T[0]); |
2c0262af FB |
4673 | break; |
4674 | case OT_WORD: | |
14ce26e7 | 4675 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4676 | gen_helper_idivw_AX(cpu_env, cpu_T[0]); |
2c0262af FB |
4677 | break; |
4678 | default: | |
4679 | case OT_LONG: | |
14ce26e7 | 4680 | gen_jmp_im(pc_start - s->cs_base); |
7923057b | 4681 | gen_helper_idivl_EAX(cpu_env, cpu_T[0]); |
14ce26e7 FB |
4682 | break; |
4683 | #ifdef TARGET_X86_64 | |
4684 | case OT_QUAD: | |
4685 | gen_jmp_im(pc_start - s->cs_base); | |
7923057b | 4686 | gen_helper_idivq_EAX(cpu_env, cpu_T[0]); |
2c0262af | 4687 | break; |
14ce26e7 | 4688 | #endif |
2c0262af FB |
4689 | } |
4690 | break; | |
4691 | default: | |
4692 | goto illegal_op; | |
4693 | } | |
4694 | break; | |
4695 | ||
4696 | case 0xfe: /* GRP4 */ | |
4697 | case 0xff: /* GRP5 */ | |
4698 | if ((b & 1) == 0) | |
4699 | ot = OT_BYTE; | |
4700 | else | |
14ce26e7 | 4701 | ot = dflag + OT_WORD; |
2c0262af | 4702 | |
92fc4b58 | 4703 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 4704 | mod = (modrm >> 6) & 3; |
14ce26e7 | 4705 | rm = (modrm & 7) | REX_B(s); |
2c0262af FB |
4706 | op = (modrm >> 3) & 7; |
4707 | if (op >= 2 && b == 0xfe) { | |
4708 | goto illegal_op; | |
4709 | } | |
14ce26e7 | 4710 | if (CODE64(s)) { |
aba9d61e | 4711 | if (op == 2 || op == 4) { |
14ce26e7 FB |
4712 | /* operand size for jumps is 64 bit */ |
4713 | ot = OT_QUAD; | |
aba9d61e | 4714 | } else if (op == 3 || op == 5) { |
41b1e61f | 4715 | ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD; |
14ce26e7 FB |
4716 | } else if (op == 6) { |
4717 | /* default push size is 64 bit */ | |
4718 | ot = dflag ? OT_QUAD : OT_WORD; | |
4719 | } | |
4720 | } | |
2c0262af FB |
4721 | if (mod != 3) { |
4722 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4723 | if (op >= 2 && op != 3 && op != 5) | |
57fec1fe | 4724 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 4725 | } else { |
57fec1fe | 4726 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
4727 | } |
4728 | ||
4729 | switch(op) { | |
4730 | case 0: /* inc Ev */ | |
4731 | if (mod != 3) | |
4732 | opreg = OR_TMP0; | |
4733 | else | |
4734 | opreg = rm; | |
4735 | gen_inc(s, ot, opreg, 1); | |
4736 | break; | |
4737 | case 1: /* dec Ev */ | |
4738 | if (mod != 3) | |
4739 | opreg = OR_TMP0; | |
4740 | else | |
4741 | opreg = rm; | |
4742 | gen_inc(s, ot, opreg, -1); | |
4743 | break; | |
4744 | case 2: /* call Ev */ | |
4f31916f | 4745 | /* XXX: optimize if memory (no 'and' is necessary) */ |
2c0262af FB |
4746 | if (s->dflag == 0) |
4747 | gen_op_andl_T0_ffff(); | |
2c0262af | 4748 | next_eip = s->pc - s->cs_base; |
1ef38687 | 4749 | gen_movtl_T1_im(next_eip); |
4f31916f FB |
4750 | gen_push_T1(s); |
4751 | gen_op_jmp_T0(); | |
2c0262af FB |
4752 | gen_eob(s); |
4753 | break; | |
61382a50 | 4754 | case 3: /* lcall Ev */ |
57fec1fe | 4755 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4756 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4757 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4758 | do_lcall: |
4759 | if (s->pe && !s->vm86) { | |
4760 | if (s->cc_op != CC_OP_DYNAMIC) | |
4761 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4762 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4763 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4764 | gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4765 | tcg_const_i32(dflag), | |
a7812ae4 | 4766 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4767 | } else { |
b6abf97d | 4768 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 BS |
4769 | gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1], |
4770 | tcg_const_i32(dflag), | |
a7812ae4 | 4771 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
4772 | } |
4773 | gen_eob(s); | |
4774 | break; | |
4775 | case 4: /* jmp Ev */ | |
4776 | if (s->dflag == 0) | |
4777 | gen_op_andl_T0_ffff(); | |
4778 | gen_op_jmp_T0(); | |
4779 | gen_eob(s); | |
4780 | break; | |
4781 | case 5: /* ljmp Ev */ | |
57fec1fe | 4782 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 4783 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
57fec1fe | 4784 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
4785 | do_ljmp: |
4786 | if (s->pe && !s->vm86) { | |
4787 | if (s->cc_op != CC_OP_DYNAMIC) | |
4788 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 4789 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 4790 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 4791 | gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1], |
a7812ae4 | 4792 | tcg_const_i32(s->pc - pc_start)); |
2c0262af | 4793 | } else { |
3bd7da9e | 4794 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
4795 | gen_op_movl_T0_T1(); |
4796 | gen_op_jmp_T0(); | |
4797 | } | |
4798 | gen_eob(s); | |
4799 | break; | |
4800 | case 6: /* push Ev */ | |
4801 | gen_push_T0(s); | |
4802 | break; | |
4803 | default: | |
4804 | goto illegal_op; | |
4805 | } | |
4806 | break; | |
4807 | ||
4808 | case 0x84: /* test Ev, Gv */ | |
5fafdf24 | 4809 | case 0x85: |
2c0262af FB |
4810 | if ((b & 1) == 0) |
4811 | ot = OT_BYTE; | |
4812 | else | |
14ce26e7 | 4813 | ot = dflag + OT_WORD; |
2c0262af | 4814 | |
92fc4b58 | 4815 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 4816 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 4817 | |
2c0262af | 4818 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 4819 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4820 | gen_op_testl_T0_T1_cc(); |
4821 | s->cc_op = CC_OP_LOGICB + ot; | |
4822 | break; | |
3b46e624 | 4823 | |
2c0262af FB |
4824 | case 0xa8: /* test eAX, Iv */ |
4825 | case 0xa9: | |
4826 | if ((b & 1) == 0) | |
4827 | ot = OT_BYTE; | |
4828 | else | |
14ce26e7 | 4829 | ot = dflag + OT_WORD; |
2c0262af FB |
4830 | val = insn_get(s, ot); |
4831 | ||
57fec1fe | 4832 | gen_op_mov_TN_reg(ot, 0, OR_EAX); |
2c0262af FB |
4833 | gen_op_movl_T1_im(val); |
4834 | gen_op_testl_T0_T1_cc(); | |
4835 | s->cc_op = CC_OP_LOGICB + ot; | |
4836 | break; | |
3b46e624 | 4837 | |
2c0262af | 4838 | case 0x98: /* CWDE/CBW */ |
14ce26e7 FB |
4839 | #ifdef TARGET_X86_64 |
4840 | if (dflag == 2) { | |
e108dd01 FB |
4841 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
4842 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4843 | gen_op_mov_reg_T0(OT_QUAD, R_EAX); | |
14ce26e7 FB |
4844 | } else |
4845 | #endif | |
e108dd01 FB |
4846 | if (dflag == 1) { |
4847 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4848 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4849 | gen_op_mov_reg_T0(OT_LONG, R_EAX); | |
4850 | } else { | |
4851 | gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX); | |
4852 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); | |
4853 | gen_op_mov_reg_T0(OT_WORD, R_EAX); | |
4854 | } | |
2c0262af FB |
4855 | break; |
4856 | case 0x99: /* CDQ/CWD */ | |
14ce26e7 FB |
4857 | #ifdef TARGET_X86_64 |
4858 | if (dflag == 2) { | |
e108dd01 FB |
4859 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
4860 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63); | |
4861 | gen_op_mov_reg_T0(OT_QUAD, R_EDX); | |
14ce26e7 FB |
4862 | } else |
4863 | #endif | |
e108dd01 FB |
4864 | if (dflag == 1) { |
4865 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); | |
4866 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4867 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31); | |
4868 | gen_op_mov_reg_T0(OT_LONG, R_EDX); | |
4869 | } else { | |
4870 | gen_op_mov_TN_reg(OT_WORD, 0, R_EAX); | |
4871 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); | |
4872 | tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15); | |
4873 | gen_op_mov_reg_T0(OT_WORD, R_EDX); | |
4874 | } | |
2c0262af FB |
4875 | break; |
4876 | case 0x1af: /* imul Gv, Ev */ | |
4877 | case 0x69: /* imul Gv, Ev, I */ | |
4878 | case 0x6b: | |
14ce26e7 | 4879 | ot = dflag + OT_WORD; |
92fc4b58 | 4880 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 FB |
4881 | reg = ((modrm >> 3) & 7) | rex_r; |
4882 | if (b == 0x69) | |
4883 | s->rip_offset = insn_const_size(ot); | |
4884 | else if (b == 0x6b) | |
4885 | s->rip_offset = 1; | |
2c0262af FB |
4886 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
4887 | if (b == 0x69) { | |
4888 | val = insn_get(s, ot); | |
4889 | gen_op_movl_T1_im(val); | |
4890 | } else if (b == 0x6b) { | |
d64477af | 4891 | val = (int8_t)insn_get(s, OT_BYTE); |
2c0262af FB |
4892 | gen_op_movl_T1_im(val); |
4893 | } else { | |
57fec1fe | 4894 | gen_op_mov_TN_reg(ot, 1, reg); |
2c0262af FB |
4895 | } |
4896 | ||
14ce26e7 FB |
4897 | #ifdef TARGET_X86_64 |
4898 | if (ot == OT_QUAD) { | |
7923057b | 4899 | gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); |
14ce26e7 FB |
4900 | } else |
4901 | #endif | |
2c0262af | 4902 | if (ot == OT_LONG) { |
0211e5af FB |
4903 | #ifdef TARGET_X86_64 |
4904 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); | |
4905 | tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); | |
4906 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4907 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4908 | tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); | |
4909 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
4910 | #else | |
4911 | { | |
a7812ae4 PB |
4912 | TCGv_i64 t0, t1; |
4913 | t0 = tcg_temp_new_i64(); | |
4914 | t1 = tcg_temp_new_i64(); | |
0211e5af FB |
4915 | tcg_gen_ext_i32_i64(t0, cpu_T[0]); |
4916 | tcg_gen_ext_i32_i64(t1, cpu_T[1]); | |
4917 | tcg_gen_mul_i64(t0, t0, t1); | |
4918 | tcg_gen_trunc_i64_i32(cpu_T[0], t0); | |
4919 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4920 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); | |
4921 | tcg_gen_shri_i64(t0, t0, 32); | |
4922 | tcg_gen_trunc_i64_i32(cpu_T[1], t0); | |
4923 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); | |
4924 | } | |
4925 | #endif | |
2c0262af | 4926 | } else { |
0211e5af FB |
4927 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
4928 | tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); | |
4929 | /* XXX: use 32 bit mul which could be faster */ | |
4930 | tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | |
4931 | tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); | |
4932 | tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); | |
4933 | tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); | |
2c0262af | 4934 | } |
57fec1fe | 4935 | gen_op_mov_reg_T0(ot, reg); |
d36cd60e | 4936 | s->cc_op = CC_OP_MULB + ot; |
2c0262af FB |
4937 | break; |
4938 | case 0x1c0: | |
4939 | case 0x1c1: /* xadd Ev, Gv */ | |
4940 | if ((b & 1) == 0) | |
4941 | ot = OT_BYTE; | |
4942 | else | |
14ce26e7 | 4943 | ot = dflag + OT_WORD; |
92fc4b58 | 4944 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 4945 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
4946 | mod = (modrm >> 6) & 3; |
4947 | if (mod == 3) { | |
14ce26e7 | 4948 | rm = (modrm & 7) | REX_B(s); |
57fec1fe FB |
4949 | gen_op_mov_TN_reg(ot, 0, reg); |
4950 | gen_op_mov_TN_reg(ot, 1, rm); | |
2c0262af | 4951 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4952 | gen_op_mov_reg_T1(ot, reg); |
4953 | gen_op_mov_reg_T0(ot, rm); | |
2c0262af FB |
4954 | } else { |
4955 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe FB |
4956 | gen_op_mov_TN_reg(ot, 0, reg); |
4957 | gen_op_ld_T1_A0(ot + s->mem_index); | |
2c0262af | 4958 | gen_op_addl_T0_T1(); |
57fec1fe FB |
4959 | gen_op_st_T0_A0(ot + s->mem_index); |
4960 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
4961 | } |
4962 | gen_op_update2_cc(); | |
4963 | s->cc_op = CC_OP_ADDB + ot; | |
4964 | break; | |
4965 | case 0x1b0: | |
4966 | case 0x1b1: /* cmpxchg Ev, Gv */ | |
cad3a37d | 4967 | { |
1130328e | 4968 | int label1, label2; |
1e4840bf | 4969 | TCGv t0, t1, t2, a0; |
cad3a37d FB |
4970 | |
4971 | if ((b & 1) == 0) | |
4972 | ot = OT_BYTE; | |
4973 | else | |
4974 | ot = dflag + OT_WORD; | |
92fc4b58 | 4975 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
cad3a37d FB |
4976 | reg = ((modrm >> 3) & 7) | rex_r; |
4977 | mod = (modrm >> 6) & 3; | |
a7812ae4 PB |
4978 | t0 = tcg_temp_local_new(); |
4979 | t1 = tcg_temp_local_new(); | |
4980 | t2 = tcg_temp_local_new(); | |
4981 | a0 = tcg_temp_local_new(); | |
1e4840bf | 4982 | gen_op_mov_v_reg(ot, t1, reg); |
cad3a37d FB |
4983 | if (mod == 3) { |
4984 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 4985 | gen_op_mov_v_reg(ot, t0, rm); |
cad3a37d FB |
4986 | } else { |
4987 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf FB |
4988 | tcg_gen_mov_tl(a0, cpu_A0); |
4989 | gen_op_ld_v(ot + s->mem_index, t0, a0); | |
cad3a37d FB |
4990 | rm = 0; /* avoid warning */ |
4991 | } | |
4992 | label1 = gen_new_label(); | |
cc739bb0 | 4993 | tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0); |
1e4840bf FB |
4994 | gen_extu(ot, t2); |
4995 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); | |
f7e80adf | 4996 | label2 = gen_new_label(); |
cad3a37d | 4997 | if (mod == 3) { |
1e4840bf | 4998 | gen_op_mov_reg_v(ot, R_EAX, t0); |
1130328e FB |
4999 | tcg_gen_br(label2); |
5000 | gen_set_label(label1); | |
1e4840bf | 5001 | gen_op_mov_reg_v(ot, rm, t1); |
cad3a37d | 5002 | } else { |
f7e80adf AG |
5003 | /* perform no-op store cycle like physical cpu; must be |
5004 | before changing accumulator to ensure idempotency if | |
5005 | the store faults and the instruction is restarted */ | |
5006 | gen_op_st_v(ot + s->mem_index, t0, a0); | |
1e4840bf | 5007 | gen_op_mov_reg_v(ot, R_EAX, t0); |
f7e80adf | 5008 | tcg_gen_br(label2); |
1130328e | 5009 | gen_set_label(label1); |
1e4840bf | 5010 | gen_op_st_v(ot + s->mem_index, t1, a0); |
cad3a37d | 5011 | } |
f7e80adf | 5012 | gen_set_label(label2); |
1e4840bf FB |
5013 | tcg_gen_mov_tl(cpu_cc_src, t0); |
5014 | tcg_gen_mov_tl(cpu_cc_dst, t2); | |
cad3a37d | 5015 | s->cc_op = CC_OP_SUBB + ot; |
1e4840bf FB |
5016 | tcg_temp_free(t0); |
5017 | tcg_temp_free(t1); | |
5018 | tcg_temp_free(t2); | |
5019 | tcg_temp_free(a0); | |
2c0262af | 5020 | } |
2c0262af FB |
5021 | break; |
5022 | case 0x1c7: /* cmpxchg8b */ | |
92fc4b58 | 5023 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 5024 | mod = (modrm >> 6) & 3; |
71c3558e | 5025 | if ((mod == 3) || ((modrm & 0x38) != 0x8)) |
2c0262af | 5026 | goto illegal_op; |
1b9d9ebb FB |
5027 | #ifdef TARGET_X86_64 |
5028 | if (dflag == 2) { | |
5029 | if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) | |
5030 | goto illegal_op; | |
5031 | gen_jmp_im(pc_start - s->cs_base); | |
5032 | if (s->cc_op != CC_OP_DYNAMIC) | |
5033 | gen_op_set_cc_op(s->cc_op); | |
5034 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
92fc4b58 | 5035 | gen_helper_cmpxchg16b(cpu_env, cpu_A0); |
1b9d9ebb FB |
5036 | } else |
5037 | #endif | |
5038 | { | |
5039 | if (!(s->cpuid_features & CPUID_CX8)) | |
5040 | goto illegal_op; | |
5041 | gen_jmp_im(pc_start - s->cs_base); | |
5042 | if (s->cc_op != CC_OP_DYNAMIC) | |
5043 | gen_op_set_cc_op(s->cc_op); | |
5044 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
92fc4b58 | 5045 | gen_helper_cmpxchg8b(cpu_env, cpu_A0); |
1b9d9ebb | 5046 | } |
2c0262af FB |
5047 | s->cc_op = CC_OP_EFLAGS; |
5048 | break; | |
3b46e624 | 5049 | |
2c0262af FB |
5050 | /**************************/ |
5051 | /* push/pop */ | |
5052 | case 0x50 ... 0x57: /* push */ | |
57fec1fe | 5053 | gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s)); |
2c0262af FB |
5054 | gen_push_T0(s); |
5055 | break; | |
5056 | case 0x58 ... 0x5f: /* pop */ | |
14ce26e7 FB |
5057 | if (CODE64(s)) { |
5058 | ot = dflag ? OT_QUAD : OT_WORD; | |
5059 | } else { | |
5060 | ot = dflag + OT_WORD; | |
5061 | } | |
2c0262af | 5062 | gen_pop_T0(s); |
77729c24 | 5063 | /* NOTE: order is important for pop %sp */ |
2c0262af | 5064 | gen_pop_update(s); |
57fec1fe | 5065 | gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s)); |
2c0262af FB |
5066 | break; |
5067 | case 0x60: /* pusha */ | |
14ce26e7 FB |
5068 | if (CODE64(s)) |
5069 | goto illegal_op; | |
2c0262af FB |
5070 | gen_pusha(s); |
5071 | break; | |
5072 | case 0x61: /* popa */ | |
14ce26e7 FB |
5073 | if (CODE64(s)) |
5074 | goto illegal_op; | |
2c0262af FB |
5075 | gen_popa(s); |
5076 | break; | |
5077 | case 0x68: /* push Iv */ | |
5078 | case 0x6a: | |
14ce26e7 FB |
5079 | if (CODE64(s)) { |
5080 | ot = dflag ? OT_QUAD : OT_WORD; | |
5081 | } else { | |
5082 | ot = dflag + OT_WORD; | |
5083 | } | |
2c0262af FB |
5084 | if (b == 0x68) |
5085 | val = insn_get(s, ot); | |
5086 | else | |
5087 | val = (int8_t)insn_get(s, OT_BYTE); | |
5088 | gen_op_movl_T0_im(val); | |
5089 | gen_push_T0(s); | |
5090 | break; | |
5091 | case 0x8f: /* pop Ev */ | |
14ce26e7 FB |
5092 | if (CODE64(s)) { |
5093 | ot = dflag ? OT_QUAD : OT_WORD; | |
5094 | } else { | |
5095 | ot = dflag + OT_WORD; | |
5096 | } | |
92fc4b58 | 5097 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
77729c24 | 5098 | mod = (modrm >> 6) & 3; |
2c0262af | 5099 | gen_pop_T0(s); |
77729c24 FB |
5100 | if (mod == 3) { |
5101 | /* NOTE: order is important for pop %sp */ | |
5102 | gen_pop_update(s); | |
14ce26e7 | 5103 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 5104 | gen_op_mov_reg_T0(ot, rm); |
77729c24 FB |
5105 | } else { |
5106 | /* NOTE: order is important too for MMU exceptions */ | |
14ce26e7 | 5107 | s->popl_esp_hack = 1 << ot; |
77729c24 FB |
5108 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); |
5109 | s->popl_esp_hack = 0; | |
5110 | gen_pop_update(s); | |
5111 | } | |
2c0262af FB |
5112 | break; |
5113 | case 0xc8: /* enter */ | |
5114 | { | |
5115 | int level; | |
92fc4b58 | 5116 | val = cpu_lduw_code(cpu_single_env, s->pc); |
2c0262af | 5117 | s->pc += 2; |
92fc4b58 | 5118 | level = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
5119 | gen_enter(s, val, level); |
5120 | } | |
5121 | break; | |
5122 | case 0xc9: /* leave */ | |
5123 | /* XXX: exception not precise (ESP is updated before potential exception) */ | |
14ce26e7 | 5124 | if (CODE64(s)) { |
57fec1fe FB |
5125 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP); |
5126 | gen_op_mov_reg_T0(OT_QUAD, R_ESP); | |
14ce26e7 | 5127 | } else if (s->ss32) { |
57fec1fe FB |
5128 | gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
5129 | gen_op_mov_reg_T0(OT_LONG, R_ESP); | |
2c0262af | 5130 | } else { |
57fec1fe FB |
5131 | gen_op_mov_TN_reg(OT_WORD, 0, R_EBP); |
5132 | gen_op_mov_reg_T0(OT_WORD, R_ESP); | |
2c0262af FB |
5133 | } |
5134 | gen_pop_T0(s); | |
14ce26e7 FB |
5135 | if (CODE64(s)) { |
5136 | ot = dflag ? OT_QUAD : OT_WORD; | |
5137 | } else { | |
5138 | ot = dflag + OT_WORD; | |
5139 | } | |
57fec1fe | 5140 | gen_op_mov_reg_T0(ot, R_EBP); |
2c0262af FB |
5141 | gen_pop_update(s); |
5142 | break; | |
5143 | case 0x06: /* push es */ | |
5144 | case 0x0e: /* push cs */ | |
5145 | case 0x16: /* push ss */ | |
5146 | case 0x1e: /* push ds */ | |
14ce26e7 FB |
5147 | if (CODE64(s)) |
5148 | goto illegal_op; | |
2c0262af FB |
5149 | gen_op_movl_T0_seg(b >> 3); |
5150 | gen_push_T0(s); | |
5151 | break; | |
5152 | case 0x1a0: /* push fs */ | |
5153 | case 0x1a8: /* push gs */ | |
5154 | gen_op_movl_T0_seg((b >> 3) & 7); | |
5155 | gen_push_T0(s); | |
5156 | break; | |
5157 | case 0x07: /* pop es */ | |
5158 | case 0x17: /* pop ss */ | |
5159 | case 0x1f: /* pop ds */ | |
14ce26e7 FB |
5160 | if (CODE64(s)) |
5161 | goto illegal_op; | |
2c0262af FB |
5162 | reg = b >> 3; |
5163 | gen_pop_T0(s); | |
5164 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5165 | gen_pop_update(s); | |
5166 | if (reg == R_SS) { | |
a2cc3b24 FB |
5167 | /* if reg == SS, inhibit interrupts/trace. */ |
5168 | /* If several instructions disable interrupts, only the | |
5169 | _first_ does it */ | |
5170 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5171 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5172 | s->tf = 0; |
5173 | } | |
5174 | if (s->is_jmp) { | |
14ce26e7 | 5175 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5176 | gen_eob(s); |
5177 | } | |
5178 | break; | |
5179 | case 0x1a1: /* pop fs */ | |
5180 | case 0x1a9: /* pop gs */ | |
5181 | gen_pop_T0(s); | |
5182 | gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base); | |
5183 | gen_pop_update(s); | |
5184 | if (s->is_jmp) { | |
14ce26e7 | 5185 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5186 | gen_eob(s); |
5187 | } | |
5188 | break; | |
5189 | ||
5190 | /**************************/ | |
5191 | /* mov */ | |
5192 | case 0x88: | |
5193 | case 0x89: /* mov Gv, Ev */ | |
5194 | if ((b & 1) == 0) | |
5195 | ot = OT_BYTE; | |
5196 | else | |
14ce26e7 | 5197 | ot = dflag + OT_WORD; |
92fc4b58 | 5198 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 5199 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5200 | |
2c0262af | 5201 | /* generate a generic store */ |
14ce26e7 | 5202 | gen_ldst_modrm(s, modrm, ot, reg, 1); |
2c0262af FB |
5203 | break; |
5204 | case 0xc6: | |
5205 | case 0xc7: /* mov Ev, Iv */ | |
5206 | if ((b & 1) == 0) | |
5207 | ot = OT_BYTE; | |
5208 | else | |
14ce26e7 | 5209 | ot = dflag + OT_WORD; |
92fc4b58 | 5210 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 5211 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5212 | if (mod != 3) { |
5213 | s->rip_offset = insn_const_size(ot); | |
2c0262af | 5214 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 5215 | } |
2c0262af FB |
5216 | val = insn_get(s, ot); |
5217 | gen_op_movl_T0_im(val); | |
5218 | if (mod != 3) | |
57fec1fe | 5219 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 5220 | else |
57fec1fe | 5221 | gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); |
2c0262af FB |
5222 | break; |
5223 | case 0x8a: | |
5224 | case 0x8b: /* mov Ev, Gv */ | |
5225 | if ((b & 1) == 0) | |
5226 | ot = OT_BYTE; | |
5227 | else | |
14ce26e7 | 5228 | ot = OT_WORD + dflag; |
92fc4b58 | 5229 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 5230 | reg = ((modrm >> 3) & 7) | rex_r; |
3b46e624 | 5231 | |
2c0262af | 5232 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); |
57fec1fe | 5233 | gen_op_mov_reg_T0(ot, reg); |
2c0262af FB |
5234 | break; |
5235 | case 0x8e: /* mov seg, Gv */ | |
92fc4b58 | 5236 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
5237 | reg = (modrm >> 3) & 7; |
5238 | if (reg >= 6 || reg == R_CS) | |
5239 | goto illegal_op; | |
5240 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
5241 | gen_movl_seg_T0(s, reg, pc_start - s->cs_base); | |
5242 | if (reg == R_SS) { | |
5243 | /* if reg == SS, inhibit interrupts/trace */ | |
a2cc3b24 FB |
5244 | /* If several instructions disable interrupts, only the |
5245 | _first_ does it */ | |
5246 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 5247 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af FB |
5248 | s->tf = 0; |
5249 | } | |
5250 | if (s->is_jmp) { | |
14ce26e7 | 5251 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5252 | gen_eob(s); |
5253 | } | |
5254 | break; | |
5255 | case 0x8c: /* mov Gv, seg */ | |
92fc4b58 | 5256 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
5257 | reg = (modrm >> 3) & 7; |
5258 | mod = (modrm >> 6) & 3; | |
5259 | if (reg >= 6) | |
5260 | goto illegal_op; | |
5261 | gen_op_movl_T0_seg(reg); | |
14ce26e7 FB |
5262 | if (mod == 3) |
5263 | ot = OT_WORD + dflag; | |
5264 | else | |
5265 | ot = OT_WORD; | |
2c0262af FB |
5266 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); |
5267 | break; | |
5268 | ||
5269 | case 0x1b6: /* movzbS Gv, Eb */ | |
5270 | case 0x1b7: /* movzwS Gv, Eb */ | |
5271 | case 0x1be: /* movsbS Gv, Eb */ | |
5272 | case 0x1bf: /* movswS Gv, Eb */ | |
5273 | { | |
5274 | int d_ot; | |
5275 | /* d_ot is the size of destination */ | |
5276 | d_ot = dflag + OT_WORD; | |
5277 | /* ot is the size of source */ | |
5278 | ot = (b & 1) + OT_BYTE; | |
92fc4b58 | 5279 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 5280 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 5281 | mod = (modrm >> 6) & 3; |
14ce26e7 | 5282 | rm = (modrm & 7) | REX_B(s); |
3b46e624 | 5283 | |
2c0262af | 5284 | if (mod == 3) { |
57fec1fe | 5285 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
5286 | switch(ot | (b & 8)) { |
5287 | case OT_BYTE: | |
e108dd01 | 5288 | tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5289 | break; |
5290 | case OT_BYTE | 8: | |
e108dd01 | 5291 | tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5292 | break; |
5293 | case OT_WORD: | |
e108dd01 | 5294 | tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5295 | break; |
5296 | default: | |
5297 | case OT_WORD | 8: | |
e108dd01 | 5298 | tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
2c0262af FB |
5299 | break; |
5300 | } | |
57fec1fe | 5301 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5302 | } else { |
5303 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5304 | if (b & 8) { | |
57fec1fe | 5305 | gen_op_lds_T0_A0(ot + s->mem_index); |
2c0262af | 5306 | } else { |
57fec1fe | 5307 | gen_op_ldu_T0_A0(ot + s->mem_index); |
2c0262af | 5308 | } |
57fec1fe | 5309 | gen_op_mov_reg_T0(d_ot, reg); |
2c0262af FB |
5310 | } |
5311 | } | |
5312 | break; | |
5313 | ||
5314 | case 0x8d: /* lea */ | |
14ce26e7 | 5315 | ot = dflag + OT_WORD; |
92fc4b58 | 5316 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
3a1d9b8b FB |
5317 | mod = (modrm >> 6) & 3; |
5318 | if (mod == 3) | |
5319 | goto illegal_op; | |
14ce26e7 | 5320 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5321 | /* we must ensure that no segment is added */ |
5322 | s->override = -1; | |
5323 | val = s->addseg; | |
5324 | s->addseg = 0; | |
5325 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5326 | s->addseg = val; | |
57fec1fe | 5327 | gen_op_mov_reg_A0(ot - OT_WORD, reg); |
2c0262af | 5328 | break; |
3b46e624 | 5329 | |
2c0262af FB |
5330 | case 0xa0: /* mov EAX, Ov */ |
5331 | case 0xa1: | |
5332 | case 0xa2: /* mov Ov, EAX */ | |
5333 | case 0xa3: | |
2c0262af | 5334 | { |
14ce26e7 FB |
5335 | target_ulong offset_addr; |
5336 | ||
5337 | if ((b & 1) == 0) | |
5338 | ot = OT_BYTE; | |
5339 | else | |
5340 | ot = dflag + OT_WORD; | |
5341 | #ifdef TARGET_X86_64 | |
8f091a59 | 5342 | if (s->aflag == 2) { |
92fc4b58 | 5343 | offset_addr = cpu_ldq_code(cpu_single_env, s->pc); |
14ce26e7 | 5344 | s->pc += 8; |
57fec1fe | 5345 | gen_op_movq_A0_im(offset_addr); |
5fafdf24 | 5346 | } else |
14ce26e7 FB |
5347 | #endif |
5348 | { | |
5349 | if (s->aflag) { | |
5350 | offset_addr = insn_get(s, OT_LONG); | |
5351 | } else { | |
5352 | offset_addr = insn_get(s, OT_WORD); | |
5353 | } | |
5354 | gen_op_movl_A0_im(offset_addr); | |
5355 | } | |
664e0f19 | 5356 | gen_add_A0_ds_seg(s); |
14ce26e7 | 5357 | if ((b & 2) == 0) { |
57fec1fe FB |
5358 | gen_op_ld_T0_A0(ot + s->mem_index); |
5359 | gen_op_mov_reg_T0(ot, R_EAX); | |
14ce26e7 | 5360 | } else { |
57fec1fe FB |
5361 | gen_op_mov_TN_reg(ot, 0, R_EAX); |
5362 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af FB |
5363 | } |
5364 | } | |
2c0262af FB |
5365 | break; |
5366 | case 0xd7: /* xlat */ | |
14ce26e7 | 5367 | #ifdef TARGET_X86_64 |
8f091a59 | 5368 | if (s->aflag == 2) { |
57fec1fe | 5369 | gen_op_movq_A0_reg(R_EBX); |
bbf662ee FB |
5370 | gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX); |
5371 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5372 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
5fafdf24 | 5373 | } else |
14ce26e7 FB |
5374 | #endif |
5375 | { | |
57fec1fe | 5376 | gen_op_movl_A0_reg(R_EBX); |
bbf662ee FB |
5377 | gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); |
5378 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff); | |
5379 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]); | |
14ce26e7 FB |
5380 | if (s->aflag == 0) |
5381 | gen_op_andl_A0_ffff(); | |
bbf662ee FB |
5382 | else |
5383 | tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); | |
14ce26e7 | 5384 | } |
664e0f19 | 5385 | gen_add_A0_ds_seg(s); |
57fec1fe FB |
5386 | gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); |
5387 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
5388 | break; |
5389 | case 0xb0 ... 0xb7: /* mov R, Ib */ | |
5390 | val = insn_get(s, OT_BYTE); | |
5391 | gen_op_movl_T0_im(val); | |
57fec1fe | 5392 | gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); |
2c0262af FB |
5393 | break; |
5394 | case 0xb8 ... 0xbf: /* mov R, Iv */ | |
14ce26e7 FB |
5395 | #ifdef TARGET_X86_64 |
5396 | if (dflag == 2) { | |
5397 | uint64_t tmp; | |
5398 | /* 64 bit case */ | |
92fc4b58 | 5399 | tmp = cpu_ldq_code(cpu_single_env, s->pc); |
14ce26e7 FB |
5400 | s->pc += 8; |
5401 | reg = (b & 7) | REX_B(s); | |
5402 | gen_movtl_T0_im(tmp); | |
57fec1fe | 5403 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 5404 | } else |
14ce26e7 FB |
5405 | #endif |
5406 | { | |
5407 | ot = dflag ? OT_LONG : OT_WORD; | |
5408 | val = insn_get(s, ot); | |
5409 | reg = (b & 7) | REX_B(s); | |
5410 | gen_op_movl_T0_im(val); | |
57fec1fe | 5411 | gen_op_mov_reg_T0(ot, reg); |
14ce26e7 | 5412 | } |
2c0262af FB |
5413 | break; |
5414 | ||
5415 | case 0x91 ... 0x97: /* xchg R, EAX */ | |
7418027e | 5416 | do_xchg_reg_eax: |
14ce26e7 FB |
5417 | ot = dflag + OT_WORD; |
5418 | reg = (b & 7) | REX_B(s); | |
2c0262af FB |
5419 | rm = R_EAX; |
5420 | goto do_xchg_reg; | |
5421 | case 0x86: | |
5422 | case 0x87: /* xchg Ev, Gv */ | |
5423 | if ((b & 1) == 0) | |
5424 | ot = OT_BYTE; | |
5425 | else | |
14ce26e7 | 5426 | ot = dflag + OT_WORD; |
92fc4b58 | 5427 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 5428 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5429 | mod = (modrm >> 6) & 3; |
5430 | if (mod == 3) { | |
14ce26e7 | 5431 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 5432 | do_xchg_reg: |
57fec1fe FB |
5433 | gen_op_mov_TN_reg(ot, 0, reg); |
5434 | gen_op_mov_TN_reg(ot, 1, rm); | |
5435 | gen_op_mov_reg_T0(ot, rm); | |
5436 | gen_op_mov_reg_T1(ot, reg); | |
2c0262af FB |
5437 | } else { |
5438 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 5439 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af FB |
5440 | /* for xchg, lock is implicit */ |
5441 | if (!(prefixes & PREFIX_LOCK)) | |
a7812ae4 | 5442 | gen_helper_lock(); |
57fec1fe FB |
5443 | gen_op_ld_T1_A0(ot + s->mem_index); |
5444 | gen_op_st_T0_A0(ot + s->mem_index); | |
2c0262af | 5445 | if (!(prefixes & PREFIX_LOCK)) |
a7812ae4 | 5446 | gen_helper_unlock(); |
57fec1fe | 5447 | gen_op_mov_reg_T1(ot, reg); |
2c0262af FB |
5448 | } |
5449 | break; | |
5450 | case 0xc4: /* les Gv */ | |
14ce26e7 FB |
5451 | if (CODE64(s)) |
5452 | goto illegal_op; | |
2c0262af FB |
5453 | op = R_ES; |
5454 | goto do_lxx; | |
5455 | case 0xc5: /* lds Gv */ | |
14ce26e7 FB |
5456 | if (CODE64(s)) |
5457 | goto illegal_op; | |
2c0262af FB |
5458 | op = R_DS; |
5459 | goto do_lxx; | |
5460 | case 0x1b2: /* lss Gv */ | |
5461 | op = R_SS; | |
5462 | goto do_lxx; | |
5463 | case 0x1b4: /* lfs Gv */ | |
5464 | op = R_FS; | |
5465 | goto do_lxx; | |
5466 | case 0x1b5: /* lgs Gv */ | |
5467 | op = R_GS; | |
5468 | do_lxx: | |
5469 | ot = dflag ? OT_LONG : OT_WORD; | |
92fc4b58 | 5470 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 5471 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af FB |
5472 | mod = (modrm >> 6) & 3; |
5473 | if (mod == 3) | |
5474 | goto illegal_op; | |
5475 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
57fec1fe | 5476 | gen_op_ld_T1_A0(ot + s->mem_index); |
aba9d61e | 5477 | gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); |
2c0262af | 5478 | /* load the segment first to handle exceptions properly */ |
57fec1fe | 5479 | gen_op_ldu_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5480 | gen_movl_seg_T0(s, op, pc_start - s->cs_base); |
5481 | /* then put the data */ | |
57fec1fe | 5482 | gen_op_mov_reg_T1(ot, reg); |
2c0262af | 5483 | if (s->is_jmp) { |
14ce26e7 | 5484 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
5485 | gen_eob(s); |
5486 | } | |
5487 | break; | |
3b46e624 | 5488 | |
2c0262af FB |
5489 | /************************/ |
5490 | /* shifts */ | |
5491 | case 0xc0: | |
5492 | case 0xc1: | |
5493 | /* shift Ev,Ib */ | |
5494 | shift = 2; | |
5495 | grp2: | |
5496 | { | |
5497 | if ((b & 1) == 0) | |
5498 | ot = OT_BYTE; | |
5499 | else | |
14ce26e7 | 5500 | ot = dflag + OT_WORD; |
3b46e624 | 5501 | |
92fc4b58 | 5502 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 5503 | mod = (modrm >> 6) & 3; |
2c0262af | 5504 | op = (modrm >> 3) & 7; |
3b46e624 | 5505 | |
2c0262af | 5506 | if (mod != 3) { |
14ce26e7 FB |
5507 | if (shift == 2) { |
5508 | s->rip_offset = 1; | |
5509 | } | |
2c0262af FB |
5510 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
5511 | opreg = OR_TMP0; | |
5512 | } else { | |
14ce26e7 | 5513 | opreg = (modrm & 7) | REX_B(s); |
2c0262af FB |
5514 | } |
5515 | ||
5516 | /* simpler op */ | |
5517 | if (shift == 0) { | |
5518 | gen_shift(s, op, ot, opreg, OR_ECX); | |
5519 | } else { | |
5520 | if (shift == 2) { | |
92fc4b58 | 5521 | shift = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
5522 | } |
5523 | gen_shifti(s, op, ot, opreg, shift); | |
5524 | } | |
5525 | } | |
5526 | break; | |
5527 | case 0xd0: | |
5528 | case 0xd1: | |
5529 | /* shift Ev,1 */ | |
5530 | shift = 1; | |
5531 | goto grp2; | |
5532 | case 0xd2: | |
5533 | case 0xd3: | |
5534 | /* shift Ev,cl */ | |
5535 | shift = 0; | |
5536 | goto grp2; | |
5537 | ||
5538 | case 0x1a4: /* shld imm */ | |
5539 | op = 0; | |
5540 | shift = 1; | |
5541 | goto do_shiftd; | |
5542 | case 0x1a5: /* shld cl */ | |
5543 | op = 0; | |
5544 | shift = 0; | |
5545 | goto do_shiftd; | |
5546 | case 0x1ac: /* shrd imm */ | |
5547 | op = 1; | |
5548 | shift = 1; | |
5549 | goto do_shiftd; | |
5550 | case 0x1ad: /* shrd cl */ | |
5551 | op = 1; | |
5552 | shift = 0; | |
5553 | do_shiftd: | |
14ce26e7 | 5554 | ot = dflag + OT_WORD; |
92fc4b58 | 5555 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af | 5556 | mod = (modrm >> 6) & 3; |
14ce26e7 FB |
5557 | rm = (modrm & 7) | REX_B(s); |
5558 | reg = ((modrm >> 3) & 7) | rex_r; | |
2c0262af FB |
5559 | if (mod != 3) { |
5560 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
b6abf97d | 5561 | opreg = OR_TMP0; |
2c0262af | 5562 | } else { |
b6abf97d | 5563 | opreg = rm; |
2c0262af | 5564 | } |
57fec1fe | 5565 | gen_op_mov_TN_reg(ot, 1, reg); |
3b46e624 | 5566 | |
2c0262af | 5567 | if (shift) { |
92fc4b58 | 5568 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
b6abf97d | 5569 | tcg_gen_movi_tl(cpu_T3, val); |
2c0262af | 5570 | } else { |
cc739bb0 | 5571 | tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); |
2c0262af | 5572 | } |
b6abf97d | 5573 | gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
2c0262af FB |
5574 | break; |
5575 | ||
5576 | /************************/ | |
5577 | /* floats */ | |
5fafdf24 | 5578 | case 0xd8 ... 0xdf: |
7eee2a50 FB |
5579 | if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { |
5580 | /* if CR0.EM or CR0.TS are set, generate an FPU exception */ | |
5581 | /* XXX: what to do if illegal op ? */ | |
5582 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
5583 | break; | |
5584 | } | |
92fc4b58 | 5585 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
5586 | mod = (modrm >> 6) & 3; |
5587 | rm = modrm & 7; | |
5588 | op = ((b & 7) << 3) | ((modrm >> 3) & 7); | |
2c0262af FB |
5589 | if (mod != 3) { |
5590 | /* memory op */ | |
5591 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
5592 | switch(op) { | |
5593 | case 0x00 ... 0x07: /* fxxxs */ | |
5594 | case 0x10 ... 0x17: /* fixxxl */ | |
5595 | case 0x20 ... 0x27: /* fxxxl */ | |
5596 | case 0x30 ... 0x37: /* fixxx */ | |
5597 | { | |
5598 | int op1; | |
5599 | op1 = op & 7; | |
5600 | ||
5601 | switch(op >> 4) { | |
5602 | case 0: | |
ba7cd150 | 5603 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5604 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5605 | gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5606 | break; |
5607 | case 1: | |
ba7cd150 | 5608 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5609 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5610 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5611 | break; |
5612 | case 2: | |
b6abf97d | 5613 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5614 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5615 | gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5616 | break; |
5617 | case 3: | |
5618 | default: | |
ba7cd150 | 5619 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5620 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5621 | gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5622 | break; |
5623 | } | |
3b46e624 | 5624 | |
a7812ae4 | 5625 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5626 | if (op1 == 3) { |
5627 | /* fcomp needs pop */ | |
d3eb5eae | 5628 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5629 | } |
5630 | } | |
5631 | break; | |
5632 | case 0x08: /* flds */ | |
5633 | case 0x0a: /* fsts */ | |
5634 | case 0x0b: /* fstps */ | |
465e9838 FB |
5635 | case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ |
5636 | case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ | |
5637 | case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ | |
2c0262af FB |
5638 | switch(op & 7) { |
5639 | case 0: | |
5640 | switch(op >> 4) { | |
5641 | case 0: | |
ba7cd150 | 5642 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5643 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5644 | gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5645 | break; |
5646 | case 1: | |
ba7cd150 | 5647 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
b6abf97d | 5648 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5649 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5650 | break; |
5651 | case 2: | |
b6abf97d | 5652 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5653 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5654 | gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5655 | break; |
5656 | case 3: | |
5657 | default: | |
ba7cd150 | 5658 | gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5659 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5660 | gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5661 | break; |
5662 | } | |
5663 | break; | |
465e9838 | 5664 | case 1: |
19e6c4b8 | 5665 | /* XXX: the corresponding CPUID bit must be tested ! */ |
465e9838 FB |
5666 | switch(op >> 4) { |
5667 | case 1: | |
d3eb5eae | 5668 | gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5669 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5670 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
465e9838 FB |
5671 | break; |
5672 | case 2: | |
d3eb5eae | 5673 | gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5674 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5675 | (s->mem_index >> 2) - 1); |
465e9838 FB |
5676 | break; |
5677 | case 3: | |
5678 | default: | |
d3eb5eae | 5679 | gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5680 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5681 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
19e6c4b8 | 5682 | break; |
465e9838 | 5683 | } |
d3eb5eae | 5684 | gen_helper_fpop(cpu_env); |
465e9838 | 5685 | break; |
2c0262af FB |
5686 | default: |
5687 | switch(op >> 4) { | |
5688 | case 0: | |
d3eb5eae | 5689 | gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5690 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5691 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5692 | break; |
5693 | case 1: | |
d3eb5eae | 5694 | gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5695 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5696 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
2c0262af FB |
5697 | break; |
5698 | case 2: | |
d3eb5eae | 5699 | gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5700 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5701 | (s->mem_index >> 2) - 1); |
2c0262af FB |
5702 | break; |
5703 | case 3: | |
5704 | default: | |
d3eb5eae | 5705 | gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5706 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
ba7cd150 | 5707 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5708 | break; |
5709 | } | |
5710 | if ((op & 7) == 3) | |
d3eb5eae | 5711 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5712 | break; |
5713 | } | |
5714 | break; | |
5715 | case 0x0c: /* fldenv mem */ | |
19e6c4b8 FB |
5716 | if (s->cc_op != CC_OP_DYNAMIC) |
5717 | gen_op_set_cc_op(s->cc_op); | |
5718 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5719 | gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5720 | break; |
5721 | case 0x0d: /* fldcw mem */ | |
19e6c4b8 | 5722 | gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
b6abf97d | 5723 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 5724 | gen_helper_fldcw(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
5725 | break; |
5726 | case 0x0e: /* fnstenv mem */ | |
19e6c4b8 FB |
5727 | if (s->cc_op != CC_OP_DYNAMIC) |
5728 | gen_op_set_cc_op(s->cc_op); | |
5729 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5730 | gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5731 | break; |
5732 | case 0x0f: /* fnstcw mem */ | |
d3eb5eae | 5733 | gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5734 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5735 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5736 | break; |
5737 | case 0x1d: /* fldt mem */ | |
19e6c4b8 FB |
5738 | if (s->cc_op != CC_OP_DYNAMIC) |
5739 | gen_op_set_cc_op(s->cc_op); | |
5740 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5741 | gen_helper_fldt_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5742 | break; |
5743 | case 0x1f: /* fstpt mem */ | |
19e6c4b8 FB |
5744 | if (s->cc_op != CC_OP_DYNAMIC) |
5745 | gen_op_set_cc_op(s->cc_op); | |
5746 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae BS |
5747 | gen_helper_fstt_ST0(cpu_env, cpu_A0); |
5748 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5749 | break; |
5750 | case 0x2c: /* frstor mem */ | |
19e6c4b8 FB |
5751 | if (s->cc_op != CC_OP_DYNAMIC) |
5752 | gen_op_set_cc_op(s->cc_op); | |
5753 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5754 | gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5755 | break; |
5756 | case 0x2e: /* fnsave mem */ | |
19e6c4b8 FB |
5757 | if (s->cc_op != CC_OP_DYNAMIC) |
5758 | gen_op_set_cc_op(s->cc_op); | |
5759 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5760 | gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); |
2c0262af FB |
5761 | break; |
5762 | case 0x2f: /* fnstsw mem */ | |
d3eb5eae | 5763 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 5764 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 5765 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
2c0262af FB |
5766 | break; |
5767 | case 0x3c: /* fbld */ | |
19e6c4b8 FB |
5768 | if (s->cc_op != CC_OP_DYNAMIC) |
5769 | gen_op_set_cc_op(s->cc_op); | |
5770 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 5771 | gen_helper_fbld_ST0(cpu_env, cpu_A0); |
2c0262af FB |
5772 | break; |
5773 | case 0x3e: /* fbstp */ | |
19e6c4b8 FB |
5774 | if (s->cc_op != CC_OP_DYNAMIC) |
5775 | gen_op_set_cc_op(s->cc_op); | |
5776 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae BS |
5777 | gen_helper_fbst_ST0(cpu_env, cpu_A0); |
5778 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5779 | break; |
5780 | case 0x3d: /* fildll */ | |
b6abf97d | 5781 | tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5782 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5783 | gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64); |
2c0262af FB |
5784 | break; |
5785 | case 0x3f: /* fistpll */ | |
d3eb5eae | 5786 | gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env); |
b6abf97d | 5787 | tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, |
19e6c4b8 | 5788 | (s->mem_index >> 2) - 1); |
d3eb5eae | 5789 | gen_helper_fpop(cpu_env); |
2c0262af FB |
5790 | break; |
5791 | default: | |
5792 | goto illegal_op; | |
5793 | } | |
5794 | } else { | |
5795 | /* register float ops */ | |
5796 | opreg = rm; | |
5797 | ||
5798 | switch(op) { | |
5799 | case 0x08: /* fld sti */ | |
d3eb5eae BS |
5800 | gen_helper_fpush(cpu_env); |
5801 | gen_helper_fmov_ST0_STN(cpu_env, | |
5802 | tcg_const_i32((opreg + 1) & 7)); | |
2c0262af FB |
5803 | break; |
5804 | case 0x09: /* fxchg sti */ | |
c169c906 FB |
5805 | case 0x29: /* fxchg4 sti, undocumented op */ |
5806 | case 0x39: /* fxchg7 sti, undocumented op */ | |
d3eb5eae | 5807 | gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
5808 | break; |
5809 | case 0x0a: /* grp d9/2 */ | |
5810 | switch(rm) { | |
5811 | case 0: /* fnop */ | |
023fe10d FB |
5812 | /* check exceptions (FreeBSD FPU probe) */ |
5813 | if (s->cc_op != CC_OP_DYNAMIC) | |
5814 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 5815 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 5816 | gen_helper_fwait(cpu_env); |
2c0262af FB |
5817 | break; |
5818 | default: | |
5819 | goto illegal_op; | |
5820 | } | |
5821 | break; | |
5822 | case 0x0c: /* grp d9/4 */ | |
5823 | switch(rm) { | |
5824 | case 0: /* fchs */ | |
d3eb5eae | 5825 | gen_helper_fchs_ST0(cpu_env); |
2c0262af FB |
5826 | break; |
5827 | case 1: /* fabs */ | |
d3eb5eae | 5828 | gen_helper_fabs_ST0(cpu_env); |
2c0262af FB |
5829 | break; |
5830 | case 4: /* ftst */ | |
d3eb5eae BS |
5831 | gen_helper_fldz_FT0(cpu_env); |
5832 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5833 | break; |
5834 | case 5: /* fxam */ | |
d3eb5eae | 5835 | gen_helper_fxam_ST0(cpu_env); |
2c0262af FB |
5836 | break; |
5837 | default: | |
5838 | goto illegal_op; | |
5839 | } | |
5840 | break; | |
5841 | case 0x0d: /* grp d9/5 */ | |
5842 | { | |
5843 | switch(rm) { | |
5844 | case 0: | |
d3eb5eae BS |
5845 | gen_helper_fpush(cpu_env); |
5846 | gen_helper_fld1_ST0(cpu_env); | |
2c0262af FB |
5847 | break; |
5848 | case 1: | |
d3eb5eae BS |
5849 | gen_helper_fpush(cpu_env); |
5850 | gen_helper_fldl2t_ST0(cpu_env); | |
2c0262af FB |
5851 | break; |
5852 | case 2: | |
d3eb5eae BS |
5853 | gen_helper_fpush(cpu_env); |
5854 | gen_helper_fldl2e_ST0(cpu_env); | |
2c0262af FB |
5855 | break; |
5856 | case 3: | |
d3eb5eae BS |
5857 | gen_helper_fpush(cpu_env); |
5858 | gen_helper_fldpi_ST0(cpu_env); | |
2c0262af FB |
5859 | break; |
5860 | case 4: | |
d3eb5eae BS |
5861 | gen_helper_fpush(cpu_env); |
5862 | gen_helper_fldlg2_ST0(cpu_env); | |
2c0262af FB |
5863 | break; |
5864 | case 5: | |
d3eb5eae BS |
5865 | gen_helper_fpush(cpu_env); |
5866 | gen_helper_fldln2_ST0(cpu_env); | |
2c0262af FB |
5867 | break; |
5868 | case 6: | |
d3eb5eae BS |
5869 | gen_helper_fpush(cpu_env); |
5870 | gen_helper_fldz_ST0(cpu_env); | |
2c0262af FB |
5871 | break; |
5872 | default: | |
5873 | goto illegal_op; | |
5874 | } | |
5875 | } | |
5876 | break; | |
5877 | case 0x0e: /* grp d9/6 */ | |
5878 | switch(rm) { | |
5879 | case 0: /* f2xm1 */ | |
d3eb5eae | 5880 | gen_helper_f2xm1(cpu_env); |
2c0262af FB |
5881 | break; |
5882 | case 1: /* fyl2x */ | |
d3eb5eae | 5883 | gen_helper_fyl2x(cpu_env); |
2c0262af FB |
5884 | break; |
5885 | case 2: /* fptan */ | |
d3eb5eae | 5886 | gen_helper_fptan(cpu_env); |
2c0262af FB |
5887 | break; |
5888 | case 3: /* fpatan */ | |
d3eb5eae | 5889 | gen_helper_fpatan(cpu_env); |
2c0262af FB |
5890 | break; |
5891 | case 4: /* fxtract */ | |
d3eb5eae | 5892 | gen_helper_fxtract(cpu_env); |
2c0262af FB |
5893 | break; |
5894 | case 5: /* fprem1 */ | |
d3eb5eae | 5895 | gen_helper_fprem1(cpu_env); |
2c0262af FB |
5896 | break; |
5897 | case 6: /* fdecstp */ | |
d3eb5eae | 5898 | gen_helper_fdecstp(cpu_env); |
2c0262af FB |
5899 | break; |
5900 | default: | |
5901 | case 7: /* fincstp */ | |
d3eb5eae | 5902 | gen_helper_fincstp(cpu_env); |
2c0262af FB |
5903 | break; |
5904 | } | |
5905 | break; | |
5906 | case 0x0f: /* grp d9/7 */ | |
5907 | switch(rm) { | |
5908 | case 0: /* fprem */ | |
d3eb5eae | 5909 | gen_helper_fprem(cpu_env); |
2c0262af FB |
5910 | break; |
5911 | case 1: /* fyl2xp1 */ | |
d3eb5eae | 5912 | gen_helper_fyl2xp1(cpu_env); |
2c0262af FB |
5913 | break; |
5914 | case 2: /* fsqrt */ | |
d3eb5eae | 5915 | gen_helper_fsqrt(cpu_env); |
2c0262af FB |
5916 | break; |
5917 | case 3: /* fsincos */ | |
d3eb5eae | 5918 | gen_helper_fsincos(cpu_env); |
2c0262af FB |
5919 | break; |
5920 | case 5: /* fscale */ | |
d3eb5eae | 5921 | gen_helper_fscale(cpu_env); |
2c0262af FB |
5922 | break; |
5923 | case 4: /* frndint */ | |
d3eb5eae | 5924 | gen_helper_frndint(cpu_env); |
2c0262af FB |
5925 | break; |
5926 | case 6: /* fsin */ | |
d3eb5eae | 5927 | gen_helper_fsin(cpu_env); |
2c0262af FB |
5928 | break; |
5929 | default: | |
5930 | case 7: /* fcos */ | |
d3eb5eae | 5931 | gen_helper_fcos(cpu_env); |
2c0262af FB |
5932 | break; |
5933 | } | |
5934 | break; | |
5935 | case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ | |
5936 | case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ | |
5937 | case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ | |
5938 | { | |
5939 | int op1; | |
3b46e624 | 5940 | |
2c0262af FB |
5941 | op1 = op & 7; |
5942 | if (op >= 0x20) { | |
a7812ae4 | 5943 | gen_helper_fp_arith_STN_ST0(op1, opreg); |
2c0262af | 5944 | if (op >= 0x30) |
d3eb5eae | 5945 | gen_helper_fpop(cpu_env); |
2c0262af | 5946 | } else { |
d3eb5eae | 5947 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
a7812ae4 | 5948 | gen_helper_fp_arith_ST0_FT0(op1); |
2c0262af FB |
5949 | } |
5950 | } | |
5951 | break; | |
5952 | case 0x02: /* fcom */ | |
c169c906 | 5953 | case 0x22: /* fcom2, undocumented op */ |
d3eb5eae BS |
5954 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5955 | gen_helper_fcom_ST0_FT0(cpu_env); | |
2c0262af FB |
5956 | break; |
5957 | case 0x03: /* fcomp */ | |
c169c906 FB |
5958 | case 0x23: /* fcomp3, undocumented op */ |
5959 | case 0x32: /* fcomp5, undocumented op */ | |
d3eb5eae BS |
5960 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5961 | gen_helper_fcom_ST0_FT0(cpu_env); | |
5962 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5963 | break; |
5964 | case 0x15: /* da/5 */ | |
5965 | switch(rm) { | |
5966 | case 1: /* fucompp */ | |
d3eb5eae BS |
5967 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
5968 | gen_helper_fucom_ST0_FT0(cpu_env); | |
5969 | gen_helper_fpop(cpu_env); | |
5970 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
5971 | break; |
5972 | default: | |
5973 | goto illegal_op; | |
5974 | } | |
5975 | break; | |
5976 | case 0x1c: | |
5977 | switch(rm) { | |
5978 | case 0: /* feni (287 only, just do nop here) */ | |
5979 | break; | |
5980 | case 1: /* fdisi (287 only, just do nop here) */ | |
5981 | break; | |
5982 | case 2: /* fclex */ | |
d3eb5eae | 5983 | gen_helper_fclex(cpu_env); |
2c0262af FB |
5984 | break; |
5985 | case 3: /* fninit */ | |
d3eb5eae | 5986 | gen_helper_fninit(cpu_env); |
2c0262af FB |
5987 | break; |
5988 | case 4: /* fsetpm (287 only, just do nop here) */ | |
5989 | break; | |
5990 | default: | |
5991 | goto illegal_op; | |
5992 | } | |
5993 | break; | |
5994 | case 0x1d: /* fucomi */ | |
5995 | if (s->cc_op != CC_OP_DYNAMIC) | |
5996 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
5997 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
5998 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
2c0262af FB |
5999 | s->cc_op = CC_OP_EFLAGS; |
6000 | break; | |
6001 | case 0x1e: /* fcomi */ | |
6002 | if (s->cc_op != CC_OP_DYNAMIC) | |
6003 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
6004 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6005 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
2c0262af FB |
6006 | s->cc_op = CC_OP_EFLAGS; |
6007 | break; | |
658c8bda | 6008 | case 0x28: /* ffree sti */ |
d3eb5eae | 6009 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
5fafdf24 | 6010 | break; |
2c0262af | 6011 | case 0x2a: /* fst sti */ |
d3eb5eae | 6012 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
2c0262af FB |
6013 | break; |
6014 | case 0x2b: /* fstp sti */ | |
c169c906 FB |
6015 | case 0x0b: /* fstp1 sti, undocumented op */ |
6016 | case 0x3a: /* fstp8 sti, undocumented op */ | |
6017 | case 0x3b: /* fstp9 sti, undocumented op */ | |
d3eb5eae BS |
6018 | gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); |
6019 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6020 | break; |
6021 | case 0x2c: /* fucom st(i) */ | |
d3eb5eae BS |
6022 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6023 | gen_helper_fucom_ST0_FT0(cpu_env); | |
2c0262af FB |
6024 | break; |
6025 | case 0x2d: /* fucomp st(i) */ | |
d3eb5eae BS |
6026 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6027 | gen_helper_fucom_ST0_FT0(cpu_env); | |
6028 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6029 | break; |
6030 | case 0x33: /* de/3 */ | |
6031 | switch(rm) { | |
6032 | case 1: /* fcompp */ | |
d3eb5eae BS |
6033 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); |
6034 | gen_helper_fcom_ST0_FT0(cpu_env); | |
6035 | gen_helper_fpop(cpu_env); | |
6036 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6037 | break; |
6038 | default: | |
6039 | goto illegal_op; | |
6040 | } | |
6041 | break; | |
c169c906 | 6042 | case 0x38: /* ffreep sti, undocumented op */ |
d3eb5eae BS |
6043 | gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); |
6044 | gen_helper_fpop(cpu_env); | |
c169c906 | 6045 | break; |
2c0262af FB |
6046 | case 0x3c: /* df/4 */ |
6047 | switch(rm) { | |
6048 | case 0: | |
d3eb5eae | 6049 | gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); |
b6abf97d | 6050 | tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); |
19e6c4b8 | 6051 | gen_op_mov_reg_T0(OT_WORD, R_EAX); |
2c0262af FB |
6052 | break; |
6053 | default: | |
6054 | goto illegal_op; | |
6055 | } | |
6056 | break; | |
6057 | case 0x3d: /* fucomip */ | |
6058 | if (s->cc_op != CC_OP_DYNAMIC) | |
6059 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
6060 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6061 | gen_helper_fucomi_ST0_FT0(cpu_env); | |
6062 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6063 | s->cc_op = CC_OP_EFLAGS; |
6064 | break; | |
6065 | case 0x3e: /* fcomip */ | |
6066 | if (s->cc_op != CC_OP_DYNAMIC) | |
6067 | gen_op_set_cc_op(s->cc_op); | |
d3eb5eae BS |
6068 | gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); |
6069 | gen_helper_fcomi_ST0_FT0(cpu_env); | |
6070 | gen_helper_fpop(cpu_env); | |
2c0262af FB |
6071 | s->cc_op = CC_OP_EFLAGS; |
6072 | break; | |
a2cc3b24 FB |
6073 | case 0x10 ... 0x13: /* fcmovxx */ |
6074 | case 0x18 ... 0x1b: | |
6075 | { | |
19e6c4b8 | 6076 | int op1, l1; |
d70040bc | 6077 | static const uint8_t fcmov_cc[8] = { |
a2cc3b24 FB |
6078 | (JCC_B << 1), |
6079 | (JCC_Z << 1), | |
6080 | (JCC_BE << 1), | |
6081 | (JCC_P << 1), | |
6082 | }; | |
1e4840bf | 6083 | op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); |
19e6c4b8 | 6084 | l1 = gen_new_label(); |
1e4840bf | 6085 | gen_jcc1(s, s->cc_op, op1, l1); |
d3eb5eae | 6086 | gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); |
19e6c4b8 | 6087 | gen_set_label(l1); |
a2cc3b24 FB |
6088 | } |
6089 | break; | |
2c0262af FB |
6090 | default: |
6091 | goto illegal_op; | |
6092 | } | |
6093 | } | |
6094 | break; | |
6095 | /************************/ | |
6096 | /* string ops */ | |
6097 | ||
6098 | case 0xa4: /* movsS */ | |
6099 | case 0xa5: | |
6100 | if ((b & 1) == 0) | |
6101 | ot = OT_BYTE; | |
6102 | else | |
14ce26e7 | 6103 | ot = dflag + OT_WORD; |
2c0262af FB |
6104 | |
6105 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6106 | gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6107 | } else { | |
6108 | gen_movs(s, ot); | |
6109 | } | |
6110 | break; | |
3b46e624 | 6111 | |
2c0262af FB |
6112 | case 0xaa: /* stosS */ |
6113 | case 0xab: | |
6114 | if ((b & 1) == 0) | |
6115 | ot = OT_BYTE; | |
6116 | else | |
14ce26e7 | 6117 | ot = dflag + OT_WORD; |
2c0262af FB |
6118 | |
6119 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { | |
6120 | gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6121 | } else { | |
6122 | gen_stos(s, ot); | |
6123 | } | |
6124 | break; | |
6125 | case 0xac: /* lodsS */ | |
6126 | case 0xad: | |
6127 | if ((b & 1) == 0) | |
6128 | ot = OT_BYTE; | |
6129 | else | |
14ce26e7 | 6130 | ot = dflag + OT_WORD; |
2c0262af FB |
6131 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6132 | gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
6133 | } else { | |
6134 | gen_lods(s, ot); | |
6135 | } | |
6136 | break; | |
6137 | case 0xae: /* scasS */ | |
6138 | case 0xaf: | |
6139 | if ((b & 1) == 0) | |
6140 | ot = OT_BYTE; | |
6141 | else | |
14ce26e7 | 6142 | ot = dflag + OT_WORD; |
2c0262af FB |
6143 | if (prefixes & PREFIX_REPNZ) { |
6144 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6145 | } else if (prefixes & PREFIX_REPZ) { | |
6146 | gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6147 | } else { | |
6148 | gen_scas(s, ot); | |
6149 | s->cc_op = CC_OP_SUBB + ot; | |
6150 | } | |
6151 | break; | |
6152 | ||
6153 | case 0xa6: /* cmpsS */ | |
6154 | case 0xa7: | |
6155 | if ((b & 1) == 0) | |
6156 | ot = OT_BYTE; | |
6157 | else | |
14ce26e7 | 6158 | ot = dflag + OT_WORD; |
2c0262af FB |
6159 | if (prefixes & PREFIX_REPNZ) { |
6160 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); | |
6161 | } else if (prefixes & PREFIX_REPZ) { | |
6162 | gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); | |
6163 | } else { | |
6164 | gen_cmps(s, ot); | |
6165 | s->cc_op = CC_OP_SUBB + ot; | |
6166 | } | |
6167 | break; | |
6168 | case 0x6c: /* insS */ | |
6169 | case 0x6d: | |
f115e911 FB |
6170 | if ((b & 1) == 0) |
6171 | ot = OT_BYTE; | |
6172 | else | |
6173 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6174 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6175 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6176 | gen_check_io(s, ot, pc_start - s->cs_base, |
6177 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6178 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6179 | gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6180 | } else { |
f115e911 | 6181 | gen_ins(s, ot); |
2e70f6ef PB |
6182 | if (use_icount) { |
6183 | gen_jmp(s, s->pc - s->cs_base); | |
6184 | } | |
2c0262af FB |
6185 | } |
6186 | break; | |
6187 | case 0x6e: /* outsS */ | |
6188 | case 0x6f: | |
f115e911 FB |
6189 | if ((b & 1) == 0) |
6190 | ot = OT_BYTE; | |
6191 | else | |
6192 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6193 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
0573fbfc | 6194 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6195 | gen_check_io(s, ot, pc_start - s->cs_base, |
6196 | svm_is_rep(prefixes) | 4); | |
f115e911 FB |
6197 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { |
6198 | gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); | |
2c0262af | 6199 | } else { |
f115e911 | 6200 | gen_outs(s, ot); |
2e70f6ef PB |
6201 | if (use_icount) { |
6202 | gen_jmp(s, s->pc - s->cs_base); | |
6203 | } | |
2c0262af FB |
6204 | } |
6205 | break; | |
6206 | ||
6207 | /************************/ | |
6208 | /* port I/O */ | |
0573fbfc | 6209 | |
2c0262af FB |
6210 | case 0xe4: |
6211 | case 0xe5: | |
f115e911 FB |
6212 | if ((b & 1) == 0) |
6213 | ot = OT_BYTE; | |
6214 | else | |
6215 | ot = dflag ? OT_LONG : OT_WORD; | |
92fc4b58 | 6216 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
f115e911 | 6217 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6218 | gen_check_io(s, ot, pc_start - s->cs_base, |
6219 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6220 | if (use_icount) |
6221 | gen_io_start(); | |
b6abf97d | 6222 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6223 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6224 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6225 | if (use_icount) { |
6226 | gen_io_end(); | |
6227 | gen_jmp(s, s->pc - s->cs_base); | |
6228 | } | |
2c0262af FB |
6229 | break; |
6230 | case 0xe6: | |
6231 | case 0xe7: | |
f115e911 FB |
6232 | if ((b & 1) == 0) |
6233 | ot = OT_BYTE; | |
6234 | else | |
6235 | ot = dflag ? OT_LONG : OT_WORD; | |
92fc4b58 | 6236 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
f115e911 | 6237 | gen_op_movl_T0_im(val); |
b8b6a50b FB |
6238 | gen_check_io(s, ot, pc_start - s->cs_base, |
6239 | svm_is_rep(prefixes)); | |
57fec1fe | 6240 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6241 | |
2e70f6ef PB |
6242 | if (use_icount) |
6243 | gen_io_start(); | |
b6abf97d | 6244 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6245 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6246 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6247 | if (use_icount) { |
6248 | gen_io_end(); | |
6249 | gen_jmp(s, s->pc - s->cs_base); | |
6250 | } | |
2c0262af FB |
6251 | break; |
6252 | case 0xec: | |
6253 | case 0xed: | |
f115e911 FB |
6254 | if ((b & 1) == 0) |
6255 | ot = OT_BYTE; | |
6256 | else | |
6257 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6258 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6259 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6260 | gen_check_io(s, ot, pc_start - s->cs_base, |
6261 | SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); | |
2e70f6ef PB |
6262 | if (use_icount) |
6263 | gen_io_start(); | |
b6abf97d | 6264 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
a7812ae4 | 6265 | gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); |
57fec1fe | 6266 | gen_op_mov_reg_T1(ot, R_EAX); |
2e70f6ef PB |
6267 | if (use_icount) { |
6268 | gen_io_end(); | |
6269 | gen_jmp(s, s->pc - s->cs_base); | |
6270 | } | |
2c0262af FB |
6271 | break; |
6272 | case 0xee: | |
6273 | case 0xef: | |
f115e911 FB |
6274 | if ((b & 1) == 0) |
6275 | ot = OT_BYTE; | |
6276 | else | |
6277 | ot = dflag ? OT_LONG : OT_WORD; | |
57fec1fe | 6278 | gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); |
4f31916f | 6279 | gen_op_andl_T0_ffff(); |
b8b6a50b FB |
6280 | gen_check_io(s, ot, pc_start - s->cs_base, |
6281 | svm_is_rep(prefixes)); | |
57fec1fe | 6282 | gen_op_mov_TN_reg(ot, 1, R_EAX); |
b8b6a50b | 6283 | |
2e70f6ef PB |
6284 | if (use_icount) |
6285 | gen_io_start(); | |
b6abf97d | 6286 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
b6abf97d | 6287 | tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); |
a7812ae4 | 6288 | gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); |
2e70f6ef PB |
6289 | if (use_icount) { |
6290 | gen_io_end(); | |
6291 | gen_jmp(s, s->pc - s->cs_base); | |
6292 | } | |
2c0262af FB |
6293 | break; |
6294 | ||
6295 | /************************/ | |
6296 | /* control */ | |
6297 | case 0xc2: /* ret im */ | |
92fc4b58 | 6298 | val = cpu_ldsw_code(cpu_single_env, s->pc); |
2c0262af FB |
6299 | s->pc += 2; |
6300 | gen_pop_T0(s); | |
8f091a59 FB |
6301 | if (CODE64(s) && s->dflag) |
6302 | s->dflag = 2; | |
2c0262af FB |
6303 | gen_stack_update(s, val + (2 << s->dflag)); |
6304 | if (s->dflag == 0) | |
6305 | gen_op_andl_T0_ffff(); | |
6306 | gen_op_jmp_T0(); | |
6307 | gen_eob(s); | |
6308 | break; | |
6309 | case 0xc3: /* ret */ | |
6310 | gen_pop_T0(s); | |
6311 | gen_pop_update(s); | |
6312 | if (s->dflag == 0) | |
6313 | gen_op_andl_T0_ffff(); | |
6314 | gen_op_jmp_T0(); | |
6315 | gen_eob(s); | |
6316 | break; | |
6317 | case 0xca: /* lret im */ | |
92fc4b58 | 6318 | val = cpu_ldsw_code(cpu_single_env, s->pc); |
2c0262af FB |
6319 | s->pc += 2; |
6320 | do_lret: | |
6321 | if (s->pe && !s->vm86) { | |
6322 | if (s->cc_op != CC_OP_DYNAMIC) | |
6323 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6324 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6325 | gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6326 | tcg_const_i32(val)); |
2c0262af FB |
6327 | } else { |
6328 | gen_stack_A0(s); | |
6329 | /* pop offset */ | |
57fec1fe | 6330 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
2c0262af FB |
6331 | if (s->dflag == 0) |
6332 | gen_op_andl_T0_ffff(); | |
6333 | /* NOTE: keeping EIP updated is not a problem in case of | |
6334 | exception */ | |
6335 | gen_op_jmp_T0(); | |
6336 | /* pop selector */ | |
6337 | gen_op_addl_A0_im(2 << s->dflag); | |
57fec1fe | 6338 | gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); |
3bd7da9e | 6339 | gen_op_movl_seg_T0_vm(R_CS); |
2c0262af FB |
6340 | /* add stack offset */ |
6341 | gen_stack_update(s, val + (4 << s->dflag)); | |
6342 | } | |
6343 | gen_eob(s); | |
6344 | break; | |
6345 | case 0xcb: /* lret */ | |
6346 | val = 0; | |
6347 | goto do_lret; | |
6348 | case 0xcf: /* iret */ | |
872929aa | 6349 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); |
2c0262af FB |
6350 | if (!s->pe) { |
6351 | /* real mode */ | |
2999a0b2 | 6352 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
2c0262af | 6353 | s->cc_op = CC_OP_EFLAGS; |
f115e911 FB |
6354 | } else if (s->vm86) { |
6355 | if (s->iopl != 3) { | |
6356 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6357 | } else { | |
2999a0b2 | 6358 | gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag)); |
f115e911 FB |
6359 | s->cc_op = CC_OP_EFLAGS; |
6360 | } | |
2c0262af FB |
6361 | } else { |
6362 | if (s->cc_op != CC_OP_DYNAMIC) | |
6363 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6364 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 6365 | gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag), |
a7812ae4 | 6366 | tcg_const_i32(s->pc - s->cs_base)); |
2c0262af FB |
6367 | s->cc_op = CC_OP_EFLAGS; |
6368 | } | |
6369 | gen_eob(s); | |
6370 | break; | |
6371 | case 0xe8: /* call im */ | |
6372 | { | |
14ce26e7 FB |
6373 | if (dflag) |
6374 | tval = (int32_t)insn_get(s, OT_LONG); | |
6375 | else | |
6376 | tval = (int16_t)insn_get(s, OT_WORD); | |
2c0262af | 6377 | next_eip = s->pc - s->cs_base; |
14ce26e7 | 6378 | tval += next_eip; |
2c0262af | 6379 | if (s->dflag == 0) |
14ce26e7 | 6380 | tval &= 0xffff; |
99596385 AJ |
6381 | else if(!CODE64(s)) |
6382 | tval &= 0xffffffff; | |
14ce26e7 | 6383 | gen_movtl_T0_im(next_eip); |
2c0262af | 6384 | gen_push_T0(s); |
14ce26e7 | 6385 | gen_jmp(s, tval); |
2c0262af FB |
6386 | } |
6387 | break; | |
6388 | case 0x9a: /* lcall im */ | |
6389 | { | |
6390 | unsigned int selector, offset; | |
3b46e624 | 6391 | |
14ce26e7 FB |
6392 | if (CODE64(s)) |
6393 | goto illegal_op; | |
2c0262af FB |
6394 | ot = dflag ? OT_LONG : OT_WORD; |
6395 | offset = insn_get(s, ot); | |
6396 | selector = insn_get(s, OT_WORD); | |
3b46e624 | 6397 | |
2c0262af | 6398 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6399 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6400 | } |
6401 | goto do_lcall; | |
ecada8a2 | 6402 | case 0xe9: /* jmp im */ |
14ce26e7 FB |
6403 | if (dflag) |
6404 | tval = (int32_t)insn_get(s, OT_LONG); | |
6405 | else | |
6406 | tval = (int16_t)insn_get(s, OT_WORD); | |
6407 | tval += s->pc - s->cs_base; | |
2c0262af | 6408 | if (s->dflag == 0) |
14ce26e7 | 6409 | tval &= 0xffff; |
32938e12 AJ |
6410 | else if(!CODE64(s)) |
6411 | tval &= 0xffffffff; | |
14ce26e7 | 6412 | gen_jmp(s, tval); |
2c0262af FB |
6413 | break; |
6414 | case 0xea: /* ljmp im */ | |
6415 | { | |
6416 | unsigned int selector, offset; | |
6417 | ||
14ce26e7 FB |
6418 | if (CODE64(s)) |
6419 | goto illegal_op; | |
2c0262af FB |
6420 | ot = dflag ? OT_LONG : OT_WORD; |
6421 | offset = insn_get(s, ot); | |
6422 | selector = insn_get(s, OT_WORD); | |
3b46e624 | 6423 | |
2c0262af | 6424 | gen_op_movl_T0_im(selector); |
14ce26e7 | 6425 | gen_op_movl_T1_imu(offset); |
2c0262af FB |
6426 | } |
6427 | goto do_ljmp; | |
6428 | case 0xeb: /* jmp Jb */ | |
14ce26e7 FB |
6429 | tval = (int8_t)insn_get(s, OT_BYTE); |
6430 | tval += s->pc - s->cs_base; | |
2c0262af | 6431 | if (s->dflag == 0) |
14ce26e7 FB |
6432 | tval &= 0xffff; |
6433 | gen_jmp(s, tval); | |
2c0262af FB |
6434 | break; |
6435 | case 0x70 ... 0x7f: /* jcc Jb */ | |
14ce26e7 | 6436 | tval = (int8_t)insn_get(s, OT_BYTE); |
2c0262af FB |
6437 | goto do_jcc; |
6438 | case 0x180 ... 0x18f: /* jcc Jv */ | |
6439 | if (dflag) { | |
14ce26e7 | 6440 | tval = (int32_t)insn_get(s, OT_LONG); |
2c0262af | 6441 | } else { |
5fafdf24 | 6442 | tval = (int16_t)insn_get(s, OT_WORD); |
2c0262af FB |
6443 | } |
6444 | do_jcc: | |
6445 | next_eip = s->pc - s->cs_base; | |
14ce26e7 | 6446 | tval += next_eip; |
2c0262af | 6447 | if (s->dflag == 0) |
14ce26e7 FB |
6448 | tval &= 0xffff; |
6449 | gen_jcc(s, b, tval, next_eip); | |
2c0262af FB |
6450 | break; |
6451 | ||
6452 | case 0x190 ... 0x19f: /* setcc Gv */ | |
92fc4b58 | 6453 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
6454 | gen_setcc(s, b); |
6455 | gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1); | |
6456 | break; | |
6457 | case 0x140 ... 0x14f: /* cmov Gv, Ev */ | |
8e1c85e3 FB |
6458 | { |
6459 | int l1; | |
1e4840bf FB |
6460 | TCGv t0; |
6461 | ||
8e1c85e3 | 6462 | ot = dflag + OT_WORD; |
92fc4b58 | 6463 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
8e1c85e3 FB |
6464 | reg = ((modrm >> 3) & 7) | rex_r; |
6465 | mod = (modrm >> 6) & 3; | |
a7812ae4 | 6466 | t0 = tcg_temp_local_new(); |
8e1c85e3 FB |
6467 | if (mod != 3) { |
6468 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf | 6469 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
8e1c85e3 FB |
6470 | } else { |
6471 | rm = (modrm & 7) | REX_B(s); | |
1e4840bf | 6472 | gen_op_mov_v_reg(ot, t0, rm); |
8e1c85e3 | 6473 | } |
8e1c85e3 FB |
6474 | #ifdef TARGET_X86_64 |
6475 | if (ot == OT_LONG) { | |
6476 | /* XXX: specific Intel behaviour ? */ | |
6477 | l1 = gen_new_label(); | |
6478 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
cc739bb0 | 6479 | tcg_gen_mov_tl(cpu_regs[reg], t0); |
8e1c85e3 | 6480 | gen_set_label(l1); |
cc739bb0 | 6481 | tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]); |
8e1c85e3 FB |
6482 | } else |
6483 | #endif | |
6484 | { | |
6485 | l1 = gen_new_label(); | |
6486 | gen_jcc1(s, s->cc_op, b ^ 1, l1); | |
1e4840bf | 6487 | gen_op_mov_reg_v(ot, reg, t0); |
8e1c85e3 FB |
6488 | gen_set_label(l1); |
6489 | } | |
1e4840bf | 6490 | tcg_temp_free(t0); |
2c0262af | 6491 | } |
2c0262af | 6492 | break; |
3b46e624 | 6493 | |
2c0262af FB |
6494 | /************************/ |
6495 | /* flags */ | |
6496 | case 0x9c: /* pushf */ | |
872929aa | 6497 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); |
2c0262af FB |
6498 | if (s->vm86 && s->iopl != 3) { |
6499 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6500 | } else { | |
6501 | if (s->cc_op != CC_OP_DYNAMIC) | |
6502 | gen_op_set_cc_op(s->cc_op); | |
f0967a1a | 6503 | gen_helper_read_eflags(cpu_T[0], cpu_env); |
2c0262af FB |
6504 | gen_push_T0(s); |
6505 | } | |
6506 | break; | |
6507 | case 0x9d: /* popf */ | |
872929aa | 6508 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); |
2c0262af FB |
6509 | if (s->vm86 && s->iopl != 3) { |
6510 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6511 | } else { | |
6512 | gen_pop_T0(s); | |
6513 | if (s->cpl == 0) { | |
6514 | if (s->dflag) { | |
f0967a1a BS |
6515 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6516 | tcg_const_i32((TF_MASK | AC_MASK | | |
6517 | ID_MASK | NT_MASK | | |
6518 | IF_MASK | | |
6519 | IOPL_MASK))); | |
2c0262af | 6520 | } else { |
f0967a1a BS |
6521 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6522 | tcg_const_i32((TF_MASK | AC_MASK | | |
6523 | ID_MASK | NT_MASK | | |
6524 | IF_MASK | IOPL_MASK) | |
6525 | & 0xffff)); | |
2c0262af FB |
6526 | } |
6527 | } else { | |
4136f33c FB |
6528 | if (s->cpl <= s->iopl) { |
6529 | if (s->dflag) { | |
f0967a1a BS |
6530 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6531 | tcg_const_i32((TF_MASK | | |
6532 | AC_MASK | | |
6533 | ID_MASK | | |
6534 | NT_MASK | | |
6535 | IF_MASK))); | |
4136f33c | 6536 | } else { |
f0967a1a BS |
6537 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6538 | tcg_const_i32((TF_MASK | | |
6539 | AC_MASK | | |
6540 | ID_MASK | | |
6541 | NT_MASK | | |
6542 | IF_MASK) | |
6543 | & 0xffff)); | |
4136f33c | 6544 | } |
2c0262af | 6545 | } else { |
4136f33c | 6546 | if (s->dflag) { |
f0967a1a BS |
6547 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6548 | tcg_const_i32((TF_MASK | AC_MASK | | |
6549 | ID_MASK | NT_MASK))); | |
4136f33c | 6550 | } else { |
f0967a1a BS |
6551 | gen_helper_write_eflags(cpu_env, cpu_T[0], |
6552 | tcg_const_i32((TF_MASK | AC_MASK | | |
6553 | ID_MASK | NT_MASK) | |
6554 | & 0xffff)); | |
4136f33c | 6555 | } |
2c0262af FB |
6556 | } |
6557 | } | |
6558 | gen_pop_update(s); | |
6559 | s->cc_op = CC_OP_EFLAGS; | |
a9321a4d | 6560 | /* abort translation because TF/AC flag may change */ |
14ce26e7 | 6561 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6562 | gen_eob(s); |
6563 | } | |
6564 | break; | |
6565 | case 0x9e: /* sahf */ | |
12e26b75 | 6566 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6567 | goto illegal_op; |
57fec1fe | 6568 | gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); |
2c0262af FB |
6569 | if (s->cc_op != CC_OP_DYNAMIC) |
6570 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6571 | gen_compute_eflags(cpu_cc_src); |
6572 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); | |
6573 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); | |
6574 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); | |
2c0262af FB |
6575 | s->cc_op = CC_OP_EFLAGS; |
6576 | break; | |
6577 | case 0x9f: /* lahf */ | |
12e26b75 | 6578 | if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) |
14ce26e7 | 6579 | goto illegal_op; |
2c0262af FB |
6580 | if (s->cc_op != CC_OP_DYNAMIC) |
6581 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6582 | gen_compute_eflags(cpu_T[0]); |
6583 | /* Note: gen_compute_eflags() only gives the condition codes */ | |
6584 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); | |
57fec1fe | 6585 | gen_op_mov_reg_T0(OT_BYTE, R_AH); |
2c0262af FB |
6586 | break; |
6587 | case 0xf5: /* cmc */ | |
6588 | if (s->cc_op != CC_OP_DYNAMIC) | |
6589 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6590 | gen_compute_eflags(cpu_cc_src); |
6591 | tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); | |
2c0262af FB |
6592 | s->cc_op = CC_OP_EFLAGS; |
6593 | break; | |
6594 | case 0xf8: /* clc */ | |
6595 | if (s->cc_op != CC_OP_DYNAMIC) | |
6596 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6597 | gen_compute_eflags(cpu_cc_src); |
6598 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); | |
2c0262af FB |
6599 | s->cc_op = CC_OP_EFLAGS; |
6600 | break; | |
6601 | case 0xf9: /* stc */ | |
6602 | if (s->cc_op != CC_OP_DYNAMIC) | |
6603 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6604 | gen_compute_eflags(cpu_cc_src); |
6605 | tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); | |
2c0262af FB |
6606 | s->cc_op = CC_OP_EFLAGS; |
6607 | break; | |
6608 | case 0xfc: /* cld */ | |
b6abf97d | 6609 | tcg_gen_movi_i32(cpu_tmp2_i32, 1); |
317ac620 | 6610 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6611 | break; |
6612 | case 0xfd: /* std */ | |
b6abf97d | 6613 | tcg_gen_movi_i32(cpu_tmp2_i32, -1); |
317ac620 | 6614 | tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df)); |
2c0262af FB |
6615 | break; |
6616 | ||
6617 | /************************/ | |
6618 | /* bit operations */ | |
6619 | case 0x1ba: /* bt/bts/btr/btc Gv, im */ | |
14ce26e7 | 6620 | ot = dflag + OT_WORD; |
92fc4b58 | 6621 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
33698e5f | 6622 | op = (modrm >> 3) & 7; |
2c0262af | 6623 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6624 | rm = (modrm & 7) | REX_B(s); |
2c0262af | 6625 | if (mod != 3) { |
14ce26e7 | 6626 | s->rip_offset = 1; |
2c0262af | 6627 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 6628 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6629 | } else { |
57fec1fe | 6630 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af FB |
6631 | } |
6632 | /* load shift */ | |
92fc4b58 | 6633 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
6634 | gen_op_movl_T1_im(val); |
6635 | if (op < 4) | |
6636 | goto illegal_op; | |
6637 | op -= 4; | |
f484d386 | 6638 | goto bt_op; |
2c0262af FB |
6639 | case 0x1a3: /* bt Gv, Ev */ |
6640 | op = 0; | |
6641 | goto do_btx; | |
6642 | case 0x1ab: /* bts */ | |
6643 | op = 1; | |
6644 | goto do_btx; | |
6645 | case 0x1b3: /* btr */ | |
6646 | op = 2; | |
6647 | goto do_btx; | |
6648 | case 0x1bb: /* btc */ | |
6649 | op = 3; | |
6650 | do_btx: | |
14ce26e7 | 6651 | ot = dflag + OT_WORD; |
92fc4b58 | 6652 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 | 6653 | reg = ((modrm >> 3) & 7) | rex_r; |
2c0262af | 6654 | mod = (modrm >> 6) & 3; |
14ce26e7 | 6655 | rm = (modrm & 7) | REX_B(s); |
57fec1fe | 6656 | gen_op_mov_TN_reg(OT_LONG, 1, reg); |
2c0262af FB |
6657 | if (mod != 3) { |
6658 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
6659 | /* specific case: we need to add a displacement */ | |
f484d386 FB |
6660 | gen_exts(ot, cpu_T[1]); |
6661 | tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); | |
6662 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); | |
6663 | tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); | |
57fec1fe | 6664 | gen_op_ld_T0_A0(ot + s->mem_index); |
2c0262af | 6665 | } else { |
57fec1fe | 6666 | gen_op_mov_TN_reg(ot, 0, rm); |
2c0262af | 6667 | } |
f484d386 FB |
6668 | bt_op: |
6669 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1); | |
6670 | switch(op) { | |
6671 | case 0: | |
6672 | tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]); | |
6673 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6674 | break; | |
6675 | case 1: | |
6676 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6677 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6678 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6679 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6680 | break; | |
6681 | case 2: | |
6682 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6683 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6684 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6685 | tcg_gen_not_tl(cpu_tmp0, cpu_tmp0); | |
6686 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6687 | break; | |
6688 | default: | |
6689 | case 3: | |
6690 | tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]); | |
6691 | tcg_gen_movi_tl(cpu_tmp0, 1); | |
6692 | tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]); | |
6693 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | |
6694 | break; | |
6695 | } | |
2c0262af FB |
6696 | s->cc_op = CC_OP_SARB + ot; |
6697 | if (op != 0) { | |
6698 | if (mod != 3) | |
57fec1fe | 6699 | gen_op_st_T0_A0(ot + s->mem_index); |
2c0262af | 6700 | else |
57fec1fe | 6701 | gen_op_mov_reg_T0(ot, rm); |
f484d386 FB |
6702 | tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); |
6703 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
2c0262af FB |
6704 | } |
6705 | break; | |
6706 | case 0x1bc: /* bsf */ | |
6707 | case 0x1bd: /* bsr */ | |
6191b059 FB |
6708 | { |
6709 | int label1; | |
1e4840bf FB |
6710 | TCGv t0; |
6711 | ||
6191b059 | 6712 | ot = dflag + OT_WORD; |
92fc4b58 | 6713 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
6191b059 | 6714 | reg = ((modrm >> 3) & 7) | rex_r; |
31501a71 | 6715 | gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0); |
6191b059 | 6716 | gen_extu(ot, cpu_T[0]); |
a7812ae4 | 6717 | t0 = tcg_temp_local_new(); |
1e4840bf | 6718 | tcg_gen_mov_tl(t0, cpu_T[0]); |
31501a71 AP |
6719 | if ((b & 1) && (prefixes & PREFIX_REPZ) && |
6720 | (s->cpuid_ext3_features & CPUID_EXT3_ABM)) { | |
6721 | switch(ot) { | |
6722 | case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0, | |
6723 | tcg_const_i32(16)); break; | |
6724 | case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0, | |
6725 | tcg_const_i32(32)); break; | |
6726 | case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0, | |
6727 | tcg_const_i32(64)); break; | |
6728 | } | |
6729 | gen_op_mov_reg_T0(ot, reg); | |
6191b059 | 6730 | } else { |
31501a71 AP |
6731 | label1 = gen_new_label(); |
6732 | tcg_gen_movi_tl(cpu_cc_dst, 0); | |
6733 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); | |
6734 | if (b & 1) { | |
6735 | gen_helper_bsr(cpu_T[0], t0); | |
6736 | } else { | |
6737 | gen_helper_bsf(cpu_T[0], t0); | |
6738 | } | |
6739 | gen_op_mov_reg_T0(ot, reg); | |
6740 | tcg_gen_movi_tl(cpu_cc_dst, 1); | |
6741 | gen_set_label(label1); | |
6742 | tcg_gen_discard_tl(cpu_cc_src); | |
6743 | s->cc_op = CC_OP_LOGICB + ot; | |
6191b059 | 6744 | } |
1e4840bf | 6745 | tcg_temp_free(t0); |
6191b059 | 6746 | } |
2c0262af FB |
6747 | break; |
6748 | /************************/ | |
6749 | /* bcd */ | |
6750 | case 0x27: /* daa */ | |
14ce26e7 FB |
6751 | if (CODE64(s)) |
6752 | goto illegal_op; | |
2c0262af FB |
6753 | if (s->cc_op != CC_OP_DYNAMIC) |
6754 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6755 | gen_helper_daa(cpu_env); |
2c0262af FB |
6756 | s->cc_op = CC_OP_EFLAGS; |
6757 | break; | |
6758 | case 0x2f: /* das */ | |
14ce26e7 FB |
6759 | if (CODE64(s)) |
6760 | goto illegal_op; | |
2c0262af FB |
6761 | if (s->cc_op != CC_OP_DYNAMIC) |
6762 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6763 | gen_helper_das(cpu_env); |
2c0262af FB |
6764 | s->cc_op = CC_OP_EFLAGS; |
6765 | break; | |
6766 | case 0x37: /* aaa */ | |
14ce26e7 FB |
6767 | if (CODE64(s)) |
6768 | goto illegal_op; | |
2c0262af FB |
6769 | if (s->cc_op != CC_OP_DYNAMIC) |
6770 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6771 | gen_helper_aaa(cpu_env); |
2c0262af FB |
6772 | s->cc_op = CC_OP_EFLAGS; |
6773 | break; | |
6774 | case 0x3f: /* aas */ | |
14ce26e7 FB |
6775 | if (CODE64(s)) |
6776 | goto illegal_op; | |
2c0262af FB |
6777 | if (s->cc_op != CC_OP_DYNAMIC) |
6778 | gen_op_set_cc_op(s->cc_op); | |
7923057b | 6779 | gen_helper_aas(cpu_env); |
2c0262af FB |
6780 | s->cc_op = CC_OP_EFLAGS; |
6781 | break; | |
6782 | case 0xd4: /* aam */ | |
14ce26e7 FB |
6783 | if (CODE64(s)) |
6784 | goto illegal_op; | |
92fc4b58 | 6785 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
b6d7c3db TS |
6786 | if (val == 0) { |
6787 | gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); | |
6788 | } else { | |
7923057b | 6789 | gen_helper_aam(cpu_env, tcg_const_i32(val)); |
b6d7c3db TS |
6790 | s->cc_op = CC_OP_LOGICB; |
6791 | } | |
2c0262af FB |
6792 | break; |
6793 | case 0xd5: /* aad */ | |
14ce26e7 FB |
6794 | if (CODE64(s)) |
6795 | goto illegal_op; | |
92fc4b58 | 6796 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
7923057b | 6797 | gen_helper_aad(cpu_env, tcg_const_i32(val)); |
2c0262af FB |
6798 | s->cc_op = CC_OP_LOGICB; |
6799 | break; | |
6800 | /************************/ | |
6801 | /* misc */ | |
6802 | case 0x90: /* nop */ | |
ab1f142b | 6803 | /* XXX: correct lock test for all insn */ |
7418027e | 6804 | if (prefixes & PREFIX_LOCK) { |
ab1f142b | 6805 | goto illegal_op; |
7418027e RH |
6806 | } |
6807 | /* If REX_B is set, then this is xchg eax, r8d, not a nop. */ | |
6808 | if (REX_B(s)) { | |
6809 | goto do_xchg_reg_eax; | |
6810 | } | |
0573fbfc TS |
6811 | if (prefixes & PREFIX_REPZ) { |
6812 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE); | |
6813 | } | |
2c0262af FB |
6814 | break; |
6815 | case 0x9b: /* fwait */ | |
5fafdf24 | 6816 | if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == |
7eee2a50 FB |
6817 | (HF_MP_MASK | HF_TS_MASK)) { |
6818 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
2ee73ac3 FB |
6819 | } else { |
6820 | if (s->cc_op != CC_OP_DYNAMIC) | |
6821 | gen_op_set_cc_op(s->cc_op); | |
14ce26e7 | 6822 | gen_jmp_im(pc_start - s->cs_base); |
d3eb5eae | 6823 | gen_helper_fwait(cpu_env); |
7eee2a50 | 6824 | } |
2c0262af FB |
6825 | break; |
6826 | case 0xcc: /* int3 */ | |
6827 | gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); | |
6828 | break; | |
6829 | case 0xcd: /* int N */ | |
92fc4b58 | 6830 | val = cpu_ldub_code(cpu_single_env, s->pc++); |
f115e911 | 6831 | if (s->vm86 && s->iopl != 3) { |
5fafdf24 | 6832 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
f115e911 FB |
6833 | } else { |
6834 | gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); | |
6835 | } | |
2c0262af FB |
6836 | break; |
6837 | case 0xce: /* into */ | |
14ce26e7 FB |
6838 | if (CODE64(s)) |
6839 | goto illegal_op; | |
2c0262af FB |
6840 | if (s->cc_op != CC_OP_DYNAMIC) |
6841 | gen_op_set_cc_op(s->cc_op); | |
a8ede8ba | 6842 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 6843 | gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); |
2c0262af | 6844 | break; |
0b97134b | 6845 | #ifdef WANT_ICEBP |
2c0262af | 6846 | case 0xf1: /* icebp (undocumented, exits to external debugger) */ |
872929aa | 6847 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); |
aba9d61e | 6848 | #if 1 |
2c0262af | 6849 | gen_debug(s, pc_start - s->cs_base); |
aba9d61e FB |
6850 | #else |
6851 | /* start debug */ | |
6852 | tb_flush(cpu_single_env); | |
6853 | cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); | |
6854 | #endif | |
2c0262af | 6855 | break; |
0b97134b | 6856 | #endif |
2c0262af FB |
6857 | case 0xfa: /* cli */ |
6858 | if (!s->vm86) { | |
6859 | if (s->cpl <= s->iopl) { | |
f0967a1a | 6860 | gen_helper_cli(cpu_env); |
2c0262af FB |
6861 | } else { |
6862 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6863 | } | |
6864 | } else { | |
6865 | if (s->iopl == 3) { | |
f0967a1a | 6866 | gen_helper_cli(cpu_env); |
2c0262af FB |
6867 | } else { |
6868 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6869 | } | |
6870 | } | |
6871 | break; | |
6872 | case 0xfb: /* sti */ | |
6873 | if (!s->vm86) { | |
6874 | if (s->cpl <= s->iopl) { | |
6875 | gen_sti: | |
f0967a1a | 6876 | gen_helper_sti(cpu_env); |
2c0262af | 6877 | /* interruptions are enabled only the first insn after sti */ |
a2cc3b24 FB |
6878 | /* If several instructions disable interrupts, only the |
6879 | _first_ does it */ | |
6880 | if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) | |
f0967a1a | 6881 | gen_helper_set_inhibit_irq(cpu_env); |
2c0262af | 6882 | /* give a chance to handle pending irqs */ |
14ce26e7 | 6883 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
6884 | gen_eob(s); |
6885 | } else { | |
6886 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6887 | } | |
6888 | } else { | |
6889 | if (s->iopl == 3) { | |
6890 | goto gen_sti; | |
6891 | } else { | |
6892 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6893 | } | |
6894 | } | |
6895 | break; | |
6896 | case 0x62: /* bound */ | |
14ce26e7 FB |
6897 | if (CODE64(s)) |
6898 | goto illegal_op; | |
2c0262af | 6899 | ot = dflag ? OT_LONG : OT_WORD; |
92fc4b58 | 6900 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
6901 | reg = (modrm >> 3) & 7; |
6902 | mod = (modrm >> 6) & 3; | |
6903 | if (mod == 3) | |
6904 | goto illegal_op; | |
57fec1fe | 6905 | gen_op_mov_TN_reg(ot, 0, reg); |
2c0262af | 6906 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
14ce26e7 | 6907 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 6908 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
92fc4b58 BS |
6909 | if (ot == OT_WORD) { |
6910 | gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6911 | } else { | |
6912 | gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32); | |
6913 | } | |
2c0262af FB |
6914 | break; |
6915 | case 0x1c8 ... 0x1cf: /* bswap reg */ | |
14ce26e7 FB |
6916 | reg = (b & 7) | REX_B(s); |
6917 | #ifdef TARGET_X86_64 | |
6918 | if (dflag == 2) { | |
57fec1fe | 6919 | gen_op_mov_TN_reg(OT_QUAD, 0, reg); |
66896cb8 | 6920 | tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); |
57fec1fe | 6921 | gen_op_mov_reg_T0(OT_QUAD, reg); |
5fafdf24 | 6922 | } else |
8777643e | 6923 | #endif |
57fec1fe FB |
6924 | { |
6925 | gen_op_mov_TN_reg(OT_LONG, 0, reg); | |
8777643e AJ |
6926 | tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
6927 | tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); | |
57fec1fe | 6928 | gen_op_mov_reg_T0(OT_LONG, reg); |
14ce26e7 | 6929 | } |
2c0262af FB |
6930 | break; |
6931 | case 0xd6: /* salc */ | |
14ce26e7 FB |
6932 | if (CODE64(s)) |
6933 | goto illegal_op; | |
2c0262af FB |
6934 | if (s->cc_op != CC_OP_DYNAMIC) |
6935 | gen_op_set_cc_op(s->cc_op); | |
bd7a7b33 FB |
6936 | gen_compute_eflags_c(cpu_T[0]); |
6937 | tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); | |
6938 | gen_op_mov_reg_T0(OT_BYTE, R_EAX); | |
2c0262af FB |
6939 | break; |
6940 | case 0xe0: /* loopnz */ | |
6941 | case 0xe1: /* loopz */ | |
2c0262af FB |
6942 | case 0xe2: /* loop */ |
6943 | case 0xe3: /* jecxz */ | |
14ce26e7 | 6944 | { |
6e0d8677 | 6945 | int l1, l2, l3; |
14ce26e7 FB |
6946 | |
6947 | tval = (int8_t)insn_get(s, OT_BYTE); | |
6948 | next_eip = s->pc - s->cs_base; | |
6949 | tval += next_eip; | |
6950 | if (s->dflag == 0) | |
6951 | tval &= 0xffff; | |
3b46e624 | 6952 | |
14ce26e7 FB |
6953 | l1 = gen_new_label(); |
6954 | l2 = gen_new_label(); | |
6e0d8677 | 6955 | l3 = gen_new_label(); |
14ce26e7 | 6956 | b &= 3; |
6e0d8677 FB |
6957 | switch(b) { |
6958 | case 0: /* loopnz */ | |
6959 | case 1: /* loopz */ | |
6960 | if (s->cc_op != CC_OP_DYNAMIC) | |
6961 | gen_op_set_cc_op(s->cc_op); | |
6962 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6963 | gen_op_jz_ecx(s->aflag, l3); | |
6964 | gen_compute_eflags(cpu_tmp0); | |
6965 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z); | |
6966 | if (b == 0) { | |
cb63669a | 6967 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); |
6e0d8677 | 6968 | } else { |
cb63669a | 6969 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1); |
6e0d8677 FB |
6970 | } |
6971 | break; | |
6972 | case 2: /* loop */ | |
6973 | gen_op_add_reg_im(s->aflag, R_ECX, -1); | |
6974 | gen_op_jnz_ecx(s->aflag, l1); | |
6975 | break; | |
6976 | default: | |
6977 | case 3: /* jcxz */ | |
6978 | gen_op_jz_ecx(s->aflag, l1); | |
6979 | break; | |
14ce26e7 FB |
6980 | } |
6981 | ||
6e0d8677 | 6982 | gen_set_label(l3); |
14ce26e7 | 6983 | gen_jmp_im(next_eip); |
8e1c85e3 | 6984 | tcg_gen_br(l2); |
6e0d8677 | 6985 | |
14ce26e7 FB |
6986 | gen_set_label(l1); |
6987 | gen_jmp_im(tval); | |
6988 | gen_set_label(l2); | |
6989 | gen_eob(s); | |
6990 | } | |
2c0262af FB |
6991 | break; |
6992 | case 0x130: /* wrmsr */ | |
6993 | case 0x132: /* rdmsr */ | |
6994 | if (s->cpl != 0) { | |
6995 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
6996 | } else { | |
872929aa FB |
6997 | if (s->cc_op != CC_OP_DYNAMIC) |
6998 | gen_op_set_cc_op(s->cc_op); | |
6999 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc | 7000 | if (b & 2) { |
4a7443be | 7001 | gen_helper_rdmsr(cpu_env); |
0573fbfc | 7002 | } else { |
4a7443be | 7003 | gen_helper_wrmsr(cpu_env); |
0573fbfc | 7004 | } |
2c0262af FB |
7005 | } |
7006 | break; | |
7007 | case 0x131: /* rdtsc */ | |
872929aa FB |
7008 | if (s->cc_op != CC_OP_DYNAMIC) |
7009 | gen_op_set_cc_op(s->cc_op); | |
ecada8a2 | 7010 | gen_jmp_im(pc_start - s->cs_base); |
efade670 PB |
7011 | if (use_icount) |
7012 | gen_io_start(); | |
4a7443be | 7013 | gen_helper_rdtsc(cpu_env); |
efade670 PB |
7014 | if (use_icount) { |
7015 | gen_io_end(); | |
7016 | gen_jmp(s, s->pc - s->cs_base); | |
7017 | } | |
2c0262af | 7018 | break; |
df01e0fc | 7019 | case 0x133: /* rdpmc */ |
872929aa FB |
7020 | if (s->cc_op != CC_OP_DYNAMIC) |
7021 | gen_op_set_cc_op(s->cc_op); | |
df01e0fc | 7022 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7023 | gen_helper_rdpmc(cpu_env); |
df01e0fc | 7024 | break; |
023fe10d | 7025 | case 0x134: /* sysenter */ |
2436b61a AZ |
7026 | /* For Intel SYSENTER is valid on 64-bit */ |
7027 | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) | |
14ce26e7 | 7028 | goto illegal_op; |
023fe10d FB |
7029 | if (!s->pe) { |
7030 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7031 | } else { | |
728d803b | 7032 | gen_update_cc_op(s); |
14ce26e7 | 7033 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7034 | gen_helper_sysenter(cpu_env); |
023fe10d FB |
7035 | gen_eob(s); |
7036 | } | |
7037 | break; | |
7038 | case 0x135: /* sysexit */ | |
2436b61a AZ |
7039 | /* For Intel SYSEXIT is valid on 64-bit */ |
7040 | if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) | |
14ce26e7 | 7041 | goto illegal_op; |
023fe10d FB |
7042 | if (!s->pe) { |
7043 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7044 | } else { | |
728d803b | 7045 | gen_update_cc_op(s); |
14ce26e7 | 7046 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7047 | gen_helper_sysexit(cpu_env, tcg_const_i32(dflag)); |
023fe10d FB |
7048 | gen_eob(s); |
7049 | } | |
7050 | break; | |
14ce26e7 FB |
7051 | #ifdef TARGET_X86_64 |
7052 | case 0x105: /* syscall */ | |
7053 | /* XXX: is it usable in real mode ? */ | |
728d803b | 7054 | gen_update_cc_op(s); |
14ce26e7 | 7055 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7056 | gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); |
14ce26e7 FB |
7057 | gen_eob(s); |
7058 | break; | |
7059 | case 0x107: /* sysret */ | |
7060 | if (!s->pe) { | |
7061 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7062 | } else { | |
728d803b | 7063 | gen_update_cc_op(s); |
14ce26e7 | 7064 | gen_jmp_im(pc_start - s->cs_base); |
2999a0b2 | 7065 | gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag)); |
aba9d61e FB |
7066 | /* condition codes are modified only in long mode */ |
7067 | if (s->lma) | |
7068 | s->cc_op = CC_OP_EFLAGS; | |
14ce26e7 FB |
7069 | gen_eob(s); |
7070 | } | |
7071 | break; | |
7072 | #endif | |
2c0262af | 7073 | case 0x1a2: /* cpuid */ |
9575cb94 FB |
7074 | if (s->cc_op != CC_OP_DYNAMIC) |
7075 | gen_op_set_cc_op(s->cc_op); | |
7076 | gen_jmp_im(pc_start - s->cs_base); | |
4a7443be | 7077 | gen_helper_cpuid(cpu_env); |
2c0262af FB |
7078 | break; |
7079 | case 0xf4: /* hlt */ | |
7080 | if (s->cpl != 0) { | |
7081 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7082 | } else { | |
7083 | if (s->cc_op != CC_OP_DYNAMIC) | |
7084 | gen_op_set_cc_op(s->cc_op); | |
94451178 | 7085 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7086 | gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); |
5779406a | 7087 | s->is_jmp = DISAS_TB_JUMP; |
2c0262af FB |
7088 | } |
7089 | break; | |
7090 | case 0x100: | |
92fc4b58 | 7091 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
7092 | mod = (modrm >> 6) & 3; |
7093 | op = (modrm >> 3) & 7; | |
7094 | switch(op) { | |
7095 | case 0: /* sldt */ | |
f115e911 FB |
7096 | if (!s->pe || s->vm86) |
7097 | goto illegal_op; | |
872929aa | 7098 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); |
651ba608 | 7099 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); |
2c0262af FB |
7100 | ot = OT_WORD; |
7101 | if (mod == 3) | |
7102 | ot += s->dflag; | |
7103 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); | |
7104 | break; | |
7105 | case 2: /* lldt */ | |
f115e911 FB |
7106 | if (!s->pe || s->vm86) |
7107 | goto illegal_op; | |
2c0262af FB |
7108 | if (s->cpl != 0) { |
7109 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7110 | } else { | |
872929aa | 7111 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); |
2c0262af | 7112 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 7113 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7114 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7115 | gen_helper_lldt(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7116 | } |
7117 | break; | |
7118 | case 1: /* str */ | |
f115e911 FB |
7119 | if (!s->pe || s->vm86) |
7120 | goto illegal_op; | |
872929aa | 7121 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); |
651ba608 | 7122 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); |
2c0262af FB |
7123 | ot = OT_WORD; |
7124 | if (mod == 3) | |
7125 | ot += s->dflag; | |
7126 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); | |
7127 | break; | |
7128 | case 3: /* ltr */ | |
f115e911 FB |
7129 | if (!s->pe || s->vm86) |
7130 | goto illegal_op; | |
2c0262af FB |
7131 | if (s->cpl != 0) { |
7132 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7133 | } else { | |
872929aa | 7134 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); |
2c0262af | 7135 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
14ce26e7 | 7136 | gen_jmp_im(pc_start - s->cs_base); |
b6abf97d | 7137 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
2999a0b2 | 7138 | gen_helper_ltr(cpu_env, cpu_tmp2_i32); |
2c0262af FB |
7139 | } |
7140 | break; | |
7141 | case 4: /* verr */ | |
7142 | case 5: /* verw */ | |
f115e911 FB |
7143 | if (!s->pe || s->vm86) |
7144 | goto illegal_op; | |
7145 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
7146 | if (s->cc_op != CC_OP_DYNAMIC) | |
7147 | gen_op_set_cc_op(s->cc_op); | |
2999a0b2 BS |
7148 | if (op == 4) { |
7149 | gen_helper_verr(cpu_env, cpu_T[0]); | |
7150 | } else { | |
7151 | gen_helper_verw(cpu_env, cpu_T[0]); | |
7152 | } | |
f115e911 FB |
7153 | s->cc_op = CC_OP_EFLAGS; |
7154 | break; | |
2c0262af FB |
7155 | default: |
7156 | goto illegal_op; | |
7157 | } | |
7158 | break; | |
7159 | case 0x101: | |
92fc4b58 | 7160 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
7161 | mod = (modrm >> 6) & 3; |
7162 | op = (modrm >> 3) & 7; | |
3d7374c5 | 7163 | rm = modrm & 7; |
2c0262af FB |
7164 | switch(op) { |
7165 | case 0: /* sgdt */ | |
2c0262af FB |
7166 | if (mod == 3) |
7167 | goto illegal_op; | |
872929aa | 7168 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); |
2c0262af | 7169 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
651ba608 | 7170 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); |
57fec1fe | 7171 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
aba9d61e | 7172 | gen_add_A0_im(s, 2); |
651ba608 | 7173 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); |
2c0262af FB |
7174 | if (!s->dflag) |
7175 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7176 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af | 7177 | break; |
3d7374c5 FB |
7178 | case 1: |
7179 | if (mod == 3) { | |
7180 | switch (rm) { | |
7181 | case 0: /* monitor */ | |
7182 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7183 | s->cpl != 0) | |
7184 | goto illegal_op; | |
94451178 FB |
7185 | if (s->cc_op != CC_OP_DYNAMIC) |
7186 | gen_op_set_cc_op(s->cc_op); | |
3d7374c5 FB |
7187 | gen_jmp_im(pc_start - s->cs_base); |
7188 | #ifdef TARGET_X86_64 | |
7189 | if (s->aflag == 2) { | |
bbf662ee | 7190 | gen_op_movq_A0_reg(R_EAX); |
5fafdf24 | 7191 | } else |
3d7374c5 FB |
7192 | #endif |
7193 | { | |
bbf662ee | 7194 | gen_op_movl_A0_reg(R_EAX); |
3d7374c5 FB |
7195 | if (s->aflag == 0) |
7196 | gen_op_andl_A0_ffff(); | |
7197 | } | |
7198 | gen_add_A0_ds_seg(s); | |
4a7443be | 7199 | gen_helper_monitor(cpu_env, cpu_A0); |
3d7374c5 FB |
7200 | break; |
7201 | case 1: /* mwait */ | |
7202 | if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || | |
7203 | s->cpl != 0) | |
7204 | goto illegal_op; | |
728d803b | 7205 | gen_update_cc_op(s); |
94451178 | 7206 | gen_jmp_im(pc_start - s->cs_base); |
4a7443be | 7207 | gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); |
3d7374c5 FB |
7208 | gen_eob(s); |
7209 | break; | |
a9321a4d PA |
7210 | case 2: /* clac */ |
7211 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7212 | s->cpl != 0) { | |
7213 | goto illegal_op; | |
7214 | } | |
7215 | gen_helper_clac(cpu_env); | |
7216 | gen_jmp_im(s->pc - s->cs_base); | |
7217 | gen_eob(s); | |
7218 | break; | |
7219 | case 3: /* stac */ | |
7220 | if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) || | |
7221 | s->cpl != 0) { | |
7222 | goto illegal_op; | |
7223 | } | |
7224 | gen_helper_stac(cpu_env); | |
7225 | gen_jmp_im(s->pc - s->cs_base); | |
7226 | gen_eob(s); | |
7227 | break; | |
3d7374c5 FB |
7228 | default: |
7229 | goto illegal_op; | |
7230 | } | |
7231 | } else { /* sidt */ | |
872929aa | 7232 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); |
3d7374c5 | 7233 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
651ba608 | 7234 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); |
57fec1fe | 7235 | gen_op_st_T0_A0(OT_WORD + s->mem_index); |
3d7374c5 | 7236 | gen_add_A0_im(s, 2); |
651ba608 | 7237 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); |
3d7374c5 FB |
7238 | if (!s->dflag) |
7239 | gen_op_andl_T0_im(0xffffff); | |
57fec1fe | 7240 | gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
3d7374c5 FB |
7241 | } |
7242 | break; | |
2c0262af FB |
7243 | case 2: /* lgdt */ |
7244 | case 3: /* lidt */ | |
0573fbfc | 7245 | if (mod == 3) { |
872929aa FB |
7246 | if (s->cc_op != CC_OP_DYNAMIC) |
7247 | gen_op_set_cc_op(s->cc_op); | |
7248 | gen_jmp_im(pc_start - s->cs_base); | |
0573fbfc TS |
7249 | switch(rm) { |
7250 | case 0: /* VMRUN */ | |
872929aa FB |
7251 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7252 | goto illegal_op; | |
7253 | if (s->cpl != 0) { | |
7254 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
0573fbfc | 7255 | break; |
872929aa | 7256 | } else { |
052e80d5 | 7257 | gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag), |
a7812ae4 | 7258 | tcg_const_i32(s->pc - pc_start)); |
db620f46 | 7259 | tcg_gen_exit_tb(0); |
5779406a | 7260 | s->is_jmp = DISAS_TB_JUMP; |
872929aa | 7261 | } |
0573fbfc TS |
7262 | break; |
7263 | case 1: /* VMMCALL */ | |
872929aa FB |
7264 | if (!(s->flags & HF_SVME_MASK)) |
7265 | goto illegal_op; | |
052e80d5 | 7266 | gen_helper_vmmcall(cpu_env); |
0573fbfc TS |
7267 | break; |
7268 | case 2: /* VMLOAD */ | |
872929aa FB |
7269 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7270 | goto illegal_op; | |
7271 | if (s->cpl != 0) { | |
7272 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7273 | break; | |
7274 | } else { | |
052e80d5 | 7275 | gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7276 | } |
0573fbfc TS |
7277 | break; |
7278 | case 3: /* VMSAVE */ | |
872929aa FB |
7279 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7280 | goto illegal_op; | |
7281 | if (s->cpl != 0) { | |
7282 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7283 | break; | |
7284 | } else { | |
052e80d5 | 7285 | gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7286 | } |
0573fbfc TS |
7287 | break; |
7288 | case 4: /* STGI */ | |
872929aa FB |
7289 | if ((!(s->flags & HF_SVME_MASK) && |
7290 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7291 | !s->pe) | |
7292 | goto illegal_op; | |
7293 | if (s->cpl != 0) { | |
7294 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7295 | break; | |
7296 | } else { | |
052e80d5 | 7297 | gen_helper_stgi(cpu_env); |
872929aa | 7298 | } |
0573fbfc TS |
7299 | break; |
7300 | case 5: /* CLGI */ | |
872929aa FB |
7301 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7302 | goto illegal_op; | |
7303 | if (s->cpl != 0) { | |
7304 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7305 | break; | |
7306 | } else { | |
052e80d5 | 7307 | gen_helper_clgi(cpu_env); |
872929aa | 7308 | } |
0573fbfc TS |
7309 | break; |
7310 | case 6: /* SKINIT */ | |
872929aa FB |
7311 | if ((!(s->flags & HF_SVME_MASK) && |
7312 | !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || | |
7313 | !s->pe) | |
7314 | goto illegal_op; | |
052e80d5 | 7315 | gen_helper_skinit(cpu_env); |
0573fbfc TS |
7316 | break; |
7317 | case 7: /* INVLPGA */ | |
872929aa FB |
7318 | if (!(s->flags & HF_SVME_MASK) || !s->pe) |
7319 | goto illegal_op; | |
7320 | if (s->cpl != 0) { | |
7321 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7322 | break; | |
7323 | } else { | |
052e80d5 | 7324 | gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag)); |
872929aa | 7325 | } |
0573fbfc TS |
7326 | break; |
7327 | default: | |
7328 | goto illegal_op; | |
7329 | } | |
7330 | } else if (s->cpl != 0) { | |
2c0262af FB |
7331 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
7332 | } else { | |
872929aa FB |
7333 | gen_svm_check_intercept(s, pc_start, |
7334 | op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); | |
2c0262af | 7335 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
57fec1fe | 7336 | gen_op_ld_T1_A0(OT_WORD + s->mem_index); |
aba9d61e | 7337 | gen_add_A0_im(s, 2); |
57fec1fe | 7338 | gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); |
2c0262af FB |
7339 | if (!s->dflag) |
7340 | gen_op_andl_T0_im(0xffffff); | |
7341 | if (op == 2) { | |
651ba608 FB |
7342 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); |
7343 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); | |
2c0262af | 7344 | } else { |
651ba608 FB |
7345 | tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); |
7346 | tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); | |
2c0262af FB |
7347 | } |
7348 | } | |
7349 | break; | |
7350 | case 4: /* smsw */ | |
872929aa | 7351 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); |
e2542fe2 | 7352 | #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN |
f60d2728 | 7353 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); |
7354 | #else | |
651ba608 | 7355 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); |
f60d2728 | 7356 | #endif |
2c0262af FB |
7357 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1); |
7358 | break; | |
7359 | case 6: /* lmsw */ | |
7360 | if (s->cpl != 0) { | |
7361 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7362 | } else { | |
872929aa | 7363 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
2c0262af | 7364 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
4a7443be | 7365 | gen_helper_lmsw(cpu_env, cpu_T[0]); |
14ce26e7 | 7366 | gen_jmp_im(s->pc - s->cs_base); |
d71b9a8b | 7367 | gen_eob(s); |
2c0262af FB |
7368 | } |
7369 | break; | |
1b050077 AP |
7370 | case 7: |
7371 | if (mod != 3) { /* invlpg */ | |
7372 | if (s->cpl != 0) { | |
7373 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7374 | } else { | |
7375 | if (s->cc_op != CC_OP_DYNAMIC) | |
7376 | gen_op_set_cc_op(s->cc_op); | |
7377 | gen_jmp_im(pc_start - s->cs_base); | |
7378 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
4a7443be | 7379 | gen_helper_invlpg(cpu_env, cpu_A0); |
1b050077 AP |
7380 | gen_jmp_im(s->pc - s->cs_base); |
7381 | gen_eob(s); | |
7382 | } | |
2c0262af | 7383 | } else { |
1b050077 AP |
7384 | switch (rm) { |
7385 | case 0: /* swapgs */ | |
14ce26e7 | 7386 | #ifdef TARGET_X86_64 |
1b050077 AP |
7387 | if (CODE64(s)) { |
7388 | if (s->cpl != 0) { | |
7389 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7390 | } else { | |
7391 | tcg_gen_ld_tl(cpu_T[0], cpu_env, | |
7392 | offsetof(CPUX86State,segs[R_GS].base)); | |
7393 | tcg_gen_ld_tl(cpu_T[1], cpu_env, | |
7394 | offsetof(CPUX86State,kernelgsbase)); | |
7395 | tcg_gen_st_tl(cpu_T[1], cpu_env, | |
7396 | offsetof(CPUX86State,segs[R_GS].base)); | |
7397 | tcg_gen_st_tl(cpu_T[0], cpu_env, | |
7398 | offsetof(CPUX86State,kernelgsbase)); | |
7399 | } | |
5fafdf24 | 7400 | } else |
14ce26e7 FB |
7401 | #endif |
7402 | { | |
7403 | goto illegal_op; | |
7404 | } | |
1b050077 AP |
7405 | break; |
7406 | case 1: /* rdtscp */ | |
7407 | if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP)) | |
7408 | goto illegal_op; | |
9575cb94 FB |
7409 | if (s->cc_op != CC_OP_DYNAMIC) |
7410 | gen_op_set_cc_op(s->cc_op); | |
7411 | gen_jmp_im(pc_start - s->cs_base); | |
1b050077 AP |
7412 | if (use_icount) |
7413 | gen_io_start(); | |
4a7443be | 7414 | gen_helper_rdtscp(cpu_env); |
1b050077 AP |
7415 | if (use_icount) { |
7416 | gen_io_end(); | |
7417 | gen_jmp(s, s->pc - s->cs_base); | |
7418 | } | |
7419 | break; | |
7420 | default: | |
7421 | goto illegal_op; | |
14ce26e7 | 7422 | } |
2c0262af FB |
7423 | } |
7424 | break; | |
7425 | default: | |
7426 | goto illegal_op; | |
7427 | } | |
7428 | break; | |
3415a4dd FB |
7429 | case 0x108: /* invd */ |
7430 | case 0x109: /* wbinvd */ | |
7431 | if (s->cpl != 0) { | |
7432 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7433 | } else { | |
872929aa | 7434 | gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); |
3415a4dd FB |
7435 | /* nothing to do */ |
7436 | } | |
7437 | break; | |
14ce26e7 FB |
7438 | case 0x63: /* arpl or movslS (x86_64) */ |
7439 | #ifdef TARGET_X86_64 | |
7440 | if (CODE64(s)) { | |
7441 | int d_ot; | |
7442 | /* d_ot is the size of destination */ | |
7443 | d_ot = dflag + OT_WORD; | |
7444 | ||
92fc4b58 | 7445 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 FB |
7446 | reg = ((modrm >> 3) & 7) | rex_r; |
7447 | mod = (modrm >> 6) & 3; | |
7448 | rm = (modrm & 7) | REX_B(s); | |
3b46e624 | 7449 | |
14ce26e7 | 7450 | if (mod == 3) { |
57fec1fe | 7451 | gen_op_mov_TN_reg(OT_LONG, 0, rm); |
14ce26e7 FB |
7452 | /* sign extend */ |
7453 | if (d_ot == OT_QUAD) | |
e108dd01 | 7454 | tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
57fec1fe | 7455 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 FB |
7456 | } else { |
7457 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7458 | if (d_ot == OT_QUAD) { | |
57fec1fe | 7459 | gen_op_lds_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7460 | } else { |
57fec1fe | 7461 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7462 | } |
57fec1fe | 7463 | gen_op_mov_reg_T0(d_ot, reg); |
14ce26e7 | 7464 | } |
5fafdf24 | 7465 | } else |
14ce26e7 FB |
7466 | #endif |
7467 | { | |
3bd7da9e | 7468 | int label1; |
49d9fdcc | 7469 | TCGv t0, t1, t2, a0; |
1e4840bf | 7470 | |
14ce26e7 FB |
7471 | if (!s->pe || s->vm86) |
7472 | goto illegal_op; | |
a7812ae4 PB |
7473 | t0 = tcg_temp_local_new(); |
7474 | t1 = tcg_temp_local_new(); | |
7475 | t2 = tcg_temp_local_new(); | |
3bd7da9e | 7476 | ot = OT_WORD; |
92fc4b58 | 7477 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
14ce26e7 FB |
7478 | reg = (modrm >> 3) & 7; |
7479 | mod = (modrm >> 6) & 3; | |
7480 | rm = modrm & 7; | |
7481 | if (mod != 3) { | |
7482 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
1e4840bf | 7483 | gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); |
49d9fdcc LD |
7484 | a0 = tcg_temp_local_new(); |
7485 | tcg_gen_mov_tl(a0, cpu_A0); | |
14ce26e7 | 7486 | } else { |
1e4840bf | 7487 | gen_op_mov_v_reg(ot, t0, rm); |
49d9fdcc | 7488 | TCGV_UNUSED(a0); |
14ce26e7 | 7489 | } |
1e4840bf FB |
7490 | gen_op_mov_v_reg(ot, t1, reg); |
7491 | tcg_gen_andi_tl(cpu_tmp0, t0, 3); | |
7492 | tcg_gen_andi_tl(t1, t1, 3); | |
7493 | tcg_gen_movi_tl(t2, 0); | |
3bd7da9e | 7494 | label1 = gen_new_label(); |
1e4840bf FB |
7495 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); |
7496 | tcg_gen_andi_tl(t0, t0, ~3); | |
7497 | tcg_gen_or_tl(t0, t0, t1); | |
7498 | tcg_gen_movi_tl(t2, CC_Z); | |
3bd7da9e | 7499 | gen_set_label(label1); |
14ce26e7 | 7500 | if (mod != 3) { |
49d9fdcc LD |
7501 | gen_op_st_v(ot + s->mem_index, t0, a0); |
7502 | tcg_temp_free(a0); | |
7503 | } else { | |
1e4840bf | 7504 | gen_op_mov_reg_v(ot, rm, t0); |
14ce26e7 | 7505 | } |
3bd7da9e FB |
7506 | if (s->cc_op != CC_OP_DYNAMIC) |
7507 | gen_op_set_cc_op(s->cc_op); | |
7508 | gen_compute_eflags(cpu_cc_src); | |
7509 | tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); | |
1e4840bf | 7510 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); |
3bd7da9e | 7511 | s->cc_op = CC_OP_EFLAGS; |
1e4840bf FB |
7512 | tcg_temp_free(t0); |
7513 | tcg_temp_free(t1); | |
7514 | tcg_temp_free(t2); | |
f115e911 | 7515 | } |
f115e911 | 7516 | break; |
2c0262af FB |
7517 | case 0x102: /* lar */ |
7518 | case 0x103: /* lsl */ | |
cec6843e FB |
7519 | { |
7520 | int label1; | |
1e4840bf | 7521 | TCGv t0; |
cec6843e FB |
7522 | if (!s->pe || s->vm86) |
7523 | goto illegal_op; | |
7524 | ot = dflag ? OT_LONG : OT_WORD; | |
92fc4b58 | 7525 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
cec6843e FB |
7526 | reg = ((modrm >> 3) & 7) | rex_r; |
7527 | gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); | |
a7812ae4 | 7528 | t0 = tcg_temp_local_new(); |
cec6843e FB |
7529 | if (s->cc_op != CC_OP_DYNAMIC) |
7530 | gen_op_set_cc_op(s->cc_op); | |
2999a0b2 BS |
7531 | if (b == 0x102) { |
7532 | gen_helper_lar(t0, cpu_env, cpu_T[0]); | |
7533 | } else { | |
7534 | gen_helper_lsl(t0, cpu_env, cpu_T[0]); | |
7535 | } | |
cec6843e FB |
7536 | tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); |
7537 | label1 = gen_new_label(); | |
cb63669a | 7538 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); |
1e4840bf | 7539 | gen_op_mov_reg_v(ot, reg, t0); |
cec6843e FB |
7540 | gen_set_label(label1); |
7541 | s->cc_op = CC_OP_EFLAGS; | |
1e4840bf | 7542 | tcg_temp_free(t0); |
cec6843e | 7543 | } |
2c0262af FB |
7544 | break; |
7545 | case 0x118: | |
92fc4b58 | 7546 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
2c0262af FB |
7547 | mod = (modrm >> 6) & 3; |
7548 | op = (modrm >> 3) & 7; | |
7549 | switch(op) { | |
7550 | case 0: /* prefetchnta */ | |
7551 | case 1: /* prefetchnt0 */ | |
7552 | case 2: /* prefetchnt0 */ | |
7553 | case 3: /* prefetchnt0 */ | |
7554 | if (mod == 3) | |
7555 | goto illegal_op; | |
7556 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7557 | /* nothing more to do */ | |
7558 | break; | |
e17a36ce FB |
7559 | default: /* nop (multi byte) */ |
7560 | gen_nop_modrm(s, modrm); | |
7561 | break; | |
2c0262af FB |
7562 | } |
7563 | break; | |
e17a36ce | 7564 | case 0x119 ... 0x11f: /* nop (multi byte) */ |
92fc4b58 | 7565 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
e17a36ce FB |
7566 | gen_nop_modrm(s, modrm); |
7567 | break; | |
2c0262af FB |
7568 | case 0x120: /* mov reg, crN */ |
7569 | case 0x122: /* mov crN, reg */ | |
7570 | if (s->cpl != 0) { | |
7571 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7572 | } else { | |
92fc4b58 | 7573 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
5c73b757 MO |
7574 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7575 | * AMD documentation (24594.pdf) and testing of | |
7576 | * intel 386 and 486 processors all show that the mod bits | |
7577 | * are assumed to be 1's, regardless of actual values. | |
7578 | */ | |
14ce26e7 FB |
7579 | rm = (modrm & 7) | REX_B(s); |
7580 | reg = ((modrm >> 3) & 7) | rex_r; | |
7581 | if (CODE64(s)) | |
7582 | ot = OT_QUAD; | |
7583 | else | |
7584 | ot = OT_LONG; | |
ccd59d09 AP |
7585 | if ((prefixes & PREFIX_LOCK) && (reg == 0) && |
7586 | (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { | |
7587 | reg = 8; | |
7588 | } | |
2c0262af FB |
7589 | switch(reg) { |
7590 | case 0: | |
7591 | case 2: | |
7592 | case 3: | |
7593 | case 4: | |
9230e66e | 7594 | case 8: |
872929aa FB |
7595 | if (s->cc_op != CC_OP_DYNAMIC) |
7596 | gen_op_set_cc_op(s->cc_op); | |
7597 | gen_jmp_im(pc_start - s->cs_base); | |
2c0262af | 7598 | if (b & 2) { |
57fec1fe | 7599 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be BS |
7600 | gen_helper_write_crN(cpu_env, tcg_const_i32(reg), |
7601 | cpu_T[0]); | |
14ce26e7 | 7602 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7603 | gen_eob(s); |
7604 | } else { | |
4a7443be | 7605 | gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); |
57fec1fe | 7606 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7607 | } |
7608 | break; | |
7609 | default: | |
7610 | goto illegal_op; | |
7611 | } | |
7612 | } | |
7613 | break; | |
7614 | case 0x121: /* mov reg, drN */ | |
7615 | case 0x123: /* mov drN, reg */ | |
7616 | if (s->cpl != 0) { | |
7617 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7618 | } else { | |
92fc4b58 | 7619 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
5c73b757 MO |
7620 | /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). |
7621 | * AMD documentation (24594.pdf) and testing of | |
7622 | * intel 386 and 486 processors all show that the mod bits | |
7623 | * are assumed to be 1's, regardless of actual values. | |
7624 | */ | |
14ce26e7 FB |
7625 | rm = (modrm & 7) | REX_B(s); |
7626 | reg = ((modrm >> 3) & 7) | rex_r; | |
7627 | if (CODE64(s)) | |
7628 | ot = OT_QUAD; | |
7629 | else | |
7630 | ot = OT_LONG; | |
2c0262af | 7631 | /* XXX: do it dynamically with CR4.DE bit */ |
14ce26e7 | 7632 | if (reg == 4 || reg == 5 || reg >= 8) |
2c0262af FB |
7633 | goto illegal_op; |
7634 | if (b & 2) { | |
0573fbfc | 7635 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); |
57fec1fe | 7636 | gen_op_mov_TN_reg(ot, 0, rm); |
4a7443be | 7637 | gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); |
14ce26e7 | 7638 | gen_jmp_im(s->pc - s->cs_base); |
2c0262af FB |
7639 | gen_eob(s); |
7640 | } else { | |
0573fbfc | 7641 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); |
651ba608 | 7642 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); |
57fec1fe | 7643 | gen_op_mov_reg_T0(ot, rm); |
2c0262af FB |
7644 | } |
7645 | } | |
7646 | break; | |
7647 | case 0x106: /* clts */ | |
7648 | if (s->cpl != 0) { | |
7649 | gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); | |
7650 | } else { | |
0573fbfc | 7651 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); |
f0967a1a | 7652 | gen_helper_clts(cpu_env); |
7eee2a50 | 7653 | /* abort block because static cpu state changed */ |
14ce26e7 | 7654 | gen_jmp_im(s->pc - s->cs_base); |
7eee2a50 | 7655 | gen_eob(s); |
2c0262af FB |
7656 | } |
7657 | break; | |
222a3336 | 7658 | /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ |
664e0f19 FB |
7659 | case 0x1c3: /* MOVNTI reg, mem */ |
7660 | if (!(s->cpuid_features & CPUID_SSE2)) | |
14ce26e7 | 7661 | goto illegal_op; |
664e0f19 | 7662 | ot = s->dflag == 2 ? OT_QUAD : OT_LONG; |
92fc4b58 | 7663 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
7664 | mod = (modrm >> 6) & 3; |
7665 | if (mod == 3) | |
7666 | goto illegal_op; | |
7667 | reg = ((modrm >> 3) & 7) | rex_r; | |
7668 | /* generate a generic store */ | |
7669 | gen_ldst_modrm(s, modrm, ot, reg, 1); | |
14ce26e7 | 7670 | break; |
664e0f19 | 7671 | case 0x1ae: |
92fc4b58 | 7672 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
664e0f19 FB |
7673 | mod = (modrm >> 6) & 3; |
7674 | op = (modrm >> 3) & 7; | |
7675 | switch(op) { | |
7676 | case 0: /* fxsave */ | |
5fafdf24 | 7677 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7678 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7679 | goto illegal_op; |
09d85fb8 | 7680 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7681 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7682 | break; | |
7683 | } | |
664e0f19 | 7684 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7685 | if (s->cc_op != CC_OP_DYNAMIC) |
7686 | gen_op_set_cc_op(s->cc_op); | |
7687 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae | 7688 | gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2))); |
664e0f19 FB |
7689 | break; |
7690 | case 1: /* fxrstor */ | |
5fafdf24 | 7691 | if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || |
09d85fb8 | 7692 | (s->prefix & PREFIX_LOCK)) |
14ce26e7 | 7693 | goto illegal_op; |
09d85fb8 | 7694 | if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { |
0fd14b72 FB |
7695 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); |
7696 | break; | |
7697 | } | |
664e0f19 | 7698 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
19e6c4b8 FB |
7699 | if (s->cc_op != CC_OP_DYNAMIC) |
7700 | gen_op_set_cc_op(s->cc_op); | |
7701 | gen_jmp_im(pc_start - s->cs_base); | |
d3eb5eae BS |
7702 | gen_helper_fxrstor(cpu_env, cpu_A0, |
7703 | tcg_const_i32((s->dflag == 2))); | |
664e0f19 FB |
7704 | break; |
7705 | case 2: /* ldmxcsr */ | |
7706 | case 3: /* stmxcsr */ | |
7707 | if (s->flags & HF_TS_MASK) { | |
7708 | gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); | |
7709 | break; | |
14ce26e7 | 7710 | } |
664e0f19 FB |
7711 | if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || |
7712 | mod == 3) | |
14ce26e7 | 7713 | goto illegal_op; |
664e0f19 FB |
7714 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7715 | if (op == 2) { | |
57fec1fe | 7716 | gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
20f8bd48 | 7717 | tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); |
d3eb5eae | 7718 | gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); |
14ce26e7 | 7719 | } else { |
651ba608 | 7720 | tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); |
57fec1fe | 7721 | gen_op_st_T0_A0(OT_LONG + s->mem_index); |
14ce26e7 | 7722 | } |
664e0f19 FB |
7723 | break; |
7724 | case 5: /* lfence */ | |
7725 | case 6: /* mfence */ | |
8001c294 | 7726 | if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) |
664e0f19 FB |
7727 | goto illegal_op; |
7728 | break; | |
8f091a59 FB |
7729 | case 7: /* sfence / clflush */ |
7730 | if ((modrm & 0xc7) == 0xc0) { | |
7731 | /* sfence */ | |
a35f3ec7 | 7732 | /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */ |
8f091a59 FB |
7733 | if (!(s->cpuid_features & CPUID_SSE)) |
7734 | goto illegal_op; | |
7735 | } else { | |
7736 | /* clflush */ | |
7737 | if (!(s->cpuid_features & CPUID_CLFLUSH)) | |
7738 | goto illegal_op; | |
7739 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); | |
7740 | } | |
7741 | break; | |
664e0f19 | 7742 | default: |
14ce26e7 FB |
7743 | goto illegal_op; |
7744 | } | |
7745 | break; | |
a35f3ec7 | 7746 | case 0x10d: /* 3DNow! prefetch(w) */ |
92fc4b58 | 7747 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
a35f3ec7 AJ |
7748 | mod = (modrm >> 6) & 3; |
7749 | if (mod == 3) | |
7750 | goto illegal_op; | |
8f091a59 FB |
7751 | gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
7752 | /* ignore for now */ | |
7753 | break; | |
3b21e03e | 7754 | case 0x1aa: /* rsm */ |
872929aa | 7755 | gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); |
3b21e03e FB |
7756 | if (!(s->flags & HF_SMM_MASK)) |
7757 | goto illegal_op; | |
728d803b | 7758 | gen_update_cc_op(s); |
3b21e03e | 7759 | gen_jmp_im(s->pc - s->cs_base); |
608badfc | 7760 | gen_helper_rsm(cpu_env); |
3b21e03e FB |
7761 | gen_eob(s); |
7762 | break; | |
222a3336 AZ |
7763 | case 0x1b8: /* SSE4.2 popcnt */ |
7764 | if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != | |
7765 | PREFIX_REPZ) | |
7766 | goto illegal_op; | |
7767 | if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) | |
7768 | goto illegal_op; | |
7769 | ||
92fc4b58 | 7770 | modrm = cpu_ldub_code(cpu_single_env, s->pc++); |
8b4a3df8 | 7771 | reg = ((modrm >> 3) & 7) | rex_r; |
222a3336 AZ |
7772 | |
7773 | if (s->prefix & PREFIX_DATA) | |
7774 | ot = OT_WORD; | |
7775 | else if (s->dflag != 2) | |
7776 | ot = OT_LONG; | |
7777 | else | |
7778 | ot = OT_QUAD; | |
7779 | ||
7780 | gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); | |
d3eb5eae | 7781 | gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); |
222a3336 | 7782 | gen_op_mov_reg_T0(ot, reg); |
fdb0d09d AZ |
7783 | |
7784 | s->cc_op = CC_OP_EFLAGS; | |
222a3336 | 7785 | break; |
a35f3ec7 AJ |
7786 | case 0x10e ... 0x10f: |
7787 | /* 3DNow! instructions, ignore prefixes */ | |
7788 | s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); | |
664e0f19 FB |
7789 | case 0x110 ... 0x117: |
7790 | case 0x128 ... 0x12f: | |
4242b1bd | 7791 | case 0x138 ... 0x13a: |
d9f4bb27 | 7792 | case 0x150 ... 0x179: |
664e0f19 FB |
7793 | case 0x17c ... 0x17f: |
7794 | case 0x1c2: | |
7795 | case 0x1c4 ... 0x1c6: | |
7796 | case 0x1d0 ... 0x1fe: | |
7797 | gen_sse(s, b, pc_start, rex_r); | |
7798 | break; | |
2c0262af FB |
7799 | default: |
7800 | goto illegal_op; | |
7801 | } | |
7802 | /* lock generation */ | |
7803 | if (s->prefix & PREFIX_LOCK) | |
a7812ae4 | 7804 | gen_helper_unlock(); |
2c0262af FB |
7805 | return s->pc; |
7806 | illegal_op: | |
ab1f142b | 7807 | if (s->prefix & PREFIX_LOCK) |
a7812ae4 | 7808 | gen_helper_unlock(); |
2c0262af FB |
7809 | /* XXX: ensure that no lock was generated */ |
7810 | gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); | |
7811 | return s->pc; | |
7812 | } | |
7813 | ||
2c0262af FB |
7814 | void optimize_flags_init(void) |
7815 | { | |
a7812ae4 PB |
7816 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7817 | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 AF |
7818 | offsetof(CPUX86State, cc_op), "cc_op"); |
7819 | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src), | |
a7812ae4 | 7820 | "cc_src"); |
317ac620 | 7821 | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst), |
a7812ae4 | 7822 | "cc_dst"); |
317ac620 | 7823 | cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_tmp), |
a7812ae4 | 7824 | "cc_tmp"); |
437a88a5 | 7825 | |
cc739bb0 LD |
7826 | #ifdef TARGET_X86_64 |
7827 | cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, | |
317ac620 | 7828 | offsetof(CPUX86State, regs[R_EAX]), "rax"); |
cc739bb0 | 7829 | cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7830 | offsetof(CPUX86State, regs[R_ECX]), "rcx"); |
cc739bb0 | 7831 | cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7832 | offsetof(CPUX86State, regs[R_EDX]), "rdx"); |
cc739bb0 | 7833 | cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7834 | offsetof(CPUX86State, regs[R_EBX]), "rbx"); |
cc739bb0 | 7835 | cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7836 | offsetof(CPUX86State, regs[R_ESP]), "rsp"); |
cc739bb0 | 7837 | cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7838 | offsetof(CPUX86State, regs[R_EBP]), "rbp"); |
cc739bb0 | 7839 | cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7840 | offsetof(CPUX86State, regs[R_ESI]), "rsi"); |
cc739bb0 | 7841 | cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7842 | offsetof(CPUX86State, regs[R_EDI]), "rdi"); |
cc739bb0 | 7843 | cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7844 | offsetof(CPUX86State, regs[8]), "r8"); |
cc739bb0 | 7845 | cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7846 | offsetof(CPUX86State, regs[9]), "r9"); |
cc739bb0 | 7847 | cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7848 | offsetof(CPUX86State, regs[10]), "r10"); |
cc739bb0 | 7849 | cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7850 | offsetof(CPUX86State, regs[11]), "r11"); |
cc739bb0 | 7851 | cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7852 | offsetof(CPUX86State, regs[12]), "r12"); |
cc739bb0 | 7853 | cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7854 | offsetof(CPUX86State, regs[13]), "r13"); |
cc739bb0 | 7855 | cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7856 | offsetof(CPUX86State, regs[14]), "r14"); |
cc739bb0 | 7857 | cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, |
317ac620 | 7858 | offsetof(CPUX86State, regs[15]), "r15"); |
cc739bb0 LD |
7859 | #else |
7860 | cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, | |
317ac620 | 7861 | offsetof(CPUX86State, regs[R_EAX]), "eax"); |
cc739bb0 | 7862 | cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7863 | offsetof(CPUX86State, regs[R_ECX]), "ecx"); |
cc739bb0 | 7864 | cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7865 | offsetof(CPUX86State, regs[R_EDX]), "edx"); |
cc739bb0 | 7866 | cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7867 | offsetof(CPUX86State, regs[R_EBX]), "ebx"); |
cc739bb0 | 7868 | cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7869 | offsetof(CPUX86State, regs[R_ESP]), "esp"); |
cc739bb0 | 7870 | cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7871 | offsetof(CPUX86State, regs[R_EBP]), "ebp"); |
cc739bb0 | 7872 | cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7873 | offsetof(CPUX86State, regs[R_ESI]), "esi"); |
cc739bb0 | 7874 | cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, |
317ac620 | 7875 | offsetof(CPUX86State, regs[R_EDI]), "edi"); |
cc739bb0 LD |
7876 | #endif |
7877 | ||
437a88a5 | 7878 | /* register helpers */ |
a7812ae4 | 7879 | #define GEN_HELPER 2 |
437a88a5 | 7880 | #include "helper.h" |
2c0262af FB |
7881 | } |
7882 | ||
7883 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for | |
7884 | basic block 'tb'. If search_pc is TRUE, also generate PC | |
7885 | information for each intermediate instruction. */ | |
317ac620 | 7886 | static inline void gen_intermediate_code_internal(CPUX86State *env, |
2cfc5f17 TS |
7887 | TranslationBlock *tb, |
7888 | int search_pc) | |
2c0262af FB |
7889 | { |
7890 | DisasContext dc1, *dc = &dc1; | |
14ce26e7 | 7891 | target_ulong pc_ptr; |
2c0262af | 7892 | uint16_t *gen_opc_end; |
a1d1bb31 | 7893 | CPUBreakpoint *bp; |
7f5b7d3e | 7894 | int j, lj; |
c068688b | 7895 | uint64_t flags; |
14ce26e7 FB |
7896 | target_ulong pc_start; |
7897 | target_ulong cs_base; | |
2e70f6ef PB |
7898 | int num_insns; |
7899 | int max_insns; | |
3b46e624 | 7900 | |
2c0262af | 7901 | /* generate intermediate code */ |
14ce26e7 FB |
7902 | pc_start = tb->pc; |
7903 | cs_base = tb->cs_base; | |
2c0262af | 7904 | flags = tb->flags; |
3a1d9b8b | 7905 | |
4f31916f | 7906 | dc->pe = (flags >> HF_PE_SHIFT) & 1; |
2c0262af FB |
7907 | dc->code32 = (flags >> HF_CS32_SHIFT) & 1; |
7908 | dc->ss32 = (flags >> HF_SS32_SHIFT) & 1; | |
7909 | dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1; | |
7910 | dc->f_st = 0; | |
7911 | dc->vm86 = (flags >> VM_SHIFT) & 1; | |
7912 | dc->cpl = (flags >> HF_CPL_SHIFT) & 3; | |
7913 | dc->iopl = (flags >> IOPL_SHIFT) & 3; | |
7914 | dc->tf = (flags >> TF_SHIFT) & 1; | |
34865134 | 7915 | dc->singlestep_enabled = env->singlestep_enabled; |
2c0262af FB |
7916 | dc->cc_op = CC_OP_DYNAMIC; |
7917 | dc->cs_base = cs_base; | |
7918 | dc->tb = tb; | |
7919 | dc->popl_esp_hack = 0; | |
7920 | /* select memory access functions */ | |
7921 | dc->mem_index = 0; | |
7922 | if (flags & HF_SOFTMMU_MASK) { | |
a9321a4d | 7923 | dc->mem_index = (cpu_mmu_index(env) + 1) << 2; |
2c0262af | 7924 | } |
14ce26e7 | 7925 | dc->cpuid_features = env->cpuid_features; |
3d7374c5 | 7926 | dc->cpuid_ext_features = env->cpuid_ext_features; |
e771edab | 7927 | dc->cpuid_ext2_features = env->cpuid_ext2_features; |
12e26b75 | 7928 | dc->cpuid_ext3_features = env->cpuid_ext3_features; |
a9321a4d | 7929 | dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features; |
14ce26e7 FB |
7930 | #ifdef TARGET_X86_64 |
7931 | dc->lma = (flags >> HF_LMA_SHIFT) & 1; | |
7932 | dc->code64 = (flags >> HF_CS64_SHIFT) & 1; | |
7933 | #endif | |
7eee2a50 | 7934 | dc->flags = flags; |
a2cc3b24 FB |
7935 | dc->jmp_opt = !(dc->tf || env->singlestep_enabled || |
7936 | (flags & HF_INHIBIT_IRQ_MASK) | |
415fa2ea | 7937 | #ifndef CONFIG_SOFTMMU |
2c0262af FB |
7938 | || (flags & HF_SOFTMMU_MASK) |
7939 | #endif | |
7940 | ); | |
4f31916f FB |
7941 | #if 0 |
7942 | /* check addseg logic */ | |
dc196a57 | 7943 | if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) |
4f31916f FB |
7944 | printf("ERROR addseg\n"); |
7945 | #endif | |
7946 | ||
a7812ae4 PB |
7947 | cpu_T[0] = tcg_temp_new(); |
7948 | cpu_T[1] = tcg_temp_new(); | |
7949 | cpu_A0 = tcg_temp_new(); | |
7950 | cpu_T3 = tcg_temp_new(); | |
7951 | ||
7952 | cpu_tmp0 = tcg_temp_new(); | |
7953 | cpu_tmp1_i64 = tcg_temp_new_i64(); | |
7954 | cpu_tmp2_i32 = tcg_temp_new_i32(); | |
7955 | cpu_tmp3_i32 = tcg_temp_new_i32(); | |
7956 | cpu_tmp4 = tcg_temp_new(); | |
7957 | cpu_tmp5 = tcg_temp_new(); | |
a7812ae4 PB |
7958 | cpu_ptr0 = tcg_temp_new_ptr(); |
7959 | cpu_ptr1 = tcg_temp_new_ptr(); | |
57fec1fe | 7960 | |
2c0262af | 7961 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2c0262af FB |
7962 | |
7963 | dc->is_jmp = DISAS_NEXT; | |
7964 | pc_ptr = pc_start; | |
7965 | lj = -1; | |
2e70f6ef PB |
7966 | num_insns = 0; |
7967 | max_insns = tb->cflags & CF_COUNT_MASK; | |
7968 | if (max_insns == 0) | |
7969 | max_insns = CF_COUNT_MASK; | |
2c0262af | 7970 | |
2e70f6ef | 7971 | gen_icount_start(); |
2c0262af | 7972 | for(;;) { |
72cf2d4f BS |
7973 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
7974 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a2397807 JK |
7975 | if (bp->pc == pc_ptr && |
7976 | !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { | |
2c0262af FB |
7977 | gen_debug(dc, pc_ptr - dc->cs_base); |
7978 | break; | |
7979 | } | |
7980 | } | |
7981 | } | |
7982 | if (search_pc) { | |
7983 | j = gen_opc_ptr - gen_opc_buf; | |
7984 | if (lj < j) { | |
7985 | lj++; | |
7986 | while (lj < j) | |
7987 | gen_opc_instr_start[lj++] = 0; | |
7988 | } | |
14ce26e7 | 7989 | gen_opc_pc[lj] = pc_ptr; |
2c0262af FB |
7990 | gen_opc_cc_op[lj] = dc->cc_op; |
7991 | gen_opc_instr_start[lj] = 1; | |
2e70f6ef | 7992 | gen_opc_icount[lj] = num_insns; |
2c0262af | 7993 | } |
2e70f6ef PB |
7994 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
7995 | gen_io_start(); | |
7996 | ||
2c0262af | 7997 | pc_ptr = disas_insn(dc, pc_ptr); |
2e70f6ef | 7998 | num_insns++; |
2c0262af FB |
7999 | /* stop translation if indicated */ |
8000 | if (dc->is_jmp) | |
8001 | break; | |
8002 | /* if single step mode, we generate only one instruction and | |
8003 | generate an exception */ | |
a2cc3b24 FB |
8004 | /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear |
8005 | the flag and abort the translation to give the irqs a | |
8006 | change to be happen */ | |
5fafdf24 | 8007 | if (dc->tf || dc->singlestep_enabled || |
2e70f6ef | 8008 | (flags & HF_INHIBIT_IRQ_MASK)) { |
14ce26e7 | 8009 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
8010 | gen_eob(dc); |
8011 | break; | |
8012 | } | |
8013 | /* if too long translation, stop generation too */ | |
8014 | if (gen_opc_ptr >= gen_opc_end || | |
2e70f6ef PB |
8015 | (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || |
8016 | num_insns >= max_insns) { | |
14ce26e7 | 8017 | gen_jmp_im(pc_ptr - dc->cs_base); |
2c0262af FB |
8018 | gen_eob(dc); |
8019 | break; | |
8020 | } | |
1b530a6d AJ |
8021 | if (singlestep) { |
8022 | gen_jmp_im(pc_ptr - dc->cs_base); | |
8023 | gen_eob(dc); | |
8024 | break; | |
8025 | } | |
2c0262af | 8026 | } |
2e70f6ef PB |
8027 | if (tb->cflags & CF_LAST_IO) |
8028 | gen_io_end(); | |
8029 | gen_icount_end(tb, num_insns); | |
2c0262af FB |
8030 | *gen_opc_ptr = INDEX_op_end; |
8031 | /* we don't forget to fill the last values */ | |
8032 | if (search_pc) { | |
8033 | j = gen_opc_ptr - gen_opc_buf; | |
8034 | lj++; | |
8035 | while (lj <= j) | |
8036 | gen_opc_instr_start[lj++] = 0; | |
8037 | } | |
3b46e624 | 8038 | |
2c0262af | 8039 | #ifdef DEBUG_DISAS |
8fec2b8c | 8040 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
14ce26e7 | 8041 | int disas_flags; |
93fcfe39 AL |
8042 | qemu_log("----------------\n"); |
8043 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
14ce26e7 FB |
8044 | #ifdef TARGET_X86_64 |
8045 | if (dc->code64) | |
8046 | disas_flags = 2; | |
8047 | else | |
8048 | #endif | |
8049 | disas_flags = !dc->code32; | |
93fcfe39 AL |
8050 | log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); |
8051 | qemu_log("\n"); | |
2c0262af FB |
8052 | } |
8053 | #endif | |
8054 | ||
2e70f6ef | 8055 | if (!search_pc) { |
2c0262af | 8056 | tb->size = pc_ptr - pc_start; |
2e70f6ef PB |
8057 | tb->icount = num_insns; |
8058 | } | |
2c0262af FB |
8059 | } |
8060 | ||
317ac620 | 8061 | void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 8062 | { |
2cfc5f17 | 8063 | gen_intermediate_code_internal(env, tb, 0); |
2c0262af FB |
8064 | } |
8065 | ||
317ac620 | 8066 | void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb) |
2c0262af | 8067 | { |
2cfc5f17 | 8068 | gen_intermediate_code_internal(env, tb, 1); |
2c0262af FB |
8069 | } |
8070 | ||
317ac620 | 8071 | void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) |
d2856f1a AJ |
8072 | { |
8073 | int cc_op; | |
8074 | #ifdef DEBUG_DISAS | |
8fec2b8c | 8075 | if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { |
d2856f1a | 8076 | int i; |
93fcfe39 | 8077 | qemu_log("RESTORE:\n"); |
d2856f1a AJ |
8078 | for(i = 0;i <= pc_pos; i++) { |
8079 | if (gen_opc_instr_start[i]) { | |
93fcfe39 | 8080 | qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); |
d2856f1a AJ |
8081 | } |
8082 | } | |
e87b7cb0 SW |
8083 | qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", |
8084 | pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, | |
d2856f1a AJ |
8085 | (uint32_t)tb->cs_base); |
8086 | } | |
8087 | #endif | |
8088 | env->eip = gen_opc_pc[pc_pos] - tb->cs_base; | |
8089 | cc_op = gen_opc_cc_op[pc_pos]; | |
8090 | if (cc_op != CC_OP_DYNAMIC) | |
8091 | env->cc_op = cc_op; | |
8092 | } |