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Fix conversions from pointer to tcg_target_long
[qemu.git] / target-lm32 / translate.c
CommitLineData
17c0fa3d
MW		 1/*
2 * LatticeMico32 main translation routines.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <assert.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
30#include "helper.h"
31#include "tcg-op.h"
17c0fa3d
MW		 32#include "qemu-common.h"
33
34#include "hw/lm32_pic.h"
35
36#define GEN_HELPER 1
37#include "helper.h"
38
39#define DISAS_LM32 1
40#if DISAS_LM32
41# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
42#else
43# define LOG_DIS(...) do { } while (0)
44#endif
45
46#define EXTRACT_FIELD(src, start, end) \
47 (((src) >> start) & ((1 << (end - start + 1)) - 1))
48
49#define MEM_INDEX 0
50
51static TCGv_ptr cpu_env;
52static TCGv cpu_R[32];
53static TCGv cpu_pc;
54static TCGv cpu_ie;
55static TCGv cpu_icc;
56static TCGv cpu_dcc;
57static TCGv cpu_cc;
58static TCGv cpu_cfg;
59static TCGv cpu_eba;
60static TCGv cpu_dc;
61static TCGv cpu_deba;
62static TCGv cpu_bp[4];
63static TCGv cpu_wp[4];
64
65#include "gen-icount.h"
66
67enum {
68 OP_FMT_RI,
69 OP_FMT_RR,
70 OP_FMT_CR,
71 OP_FMT_I
72};
73
74/* This is the state at translation time. */
75typedef struct DisasContext {
76 CPUState *env;
77 target_ulong pc;
78
79 /* Decoder. */
80 int format;
81 uint32_t ir;
82 uint8_t opcode;
83 uint8_t r0, r1, r2, csr;
84 uint16_t imm5;
85 uint16_t imm16;
86 uint32_t imm26;
87
88 unsigned int delayed_branch;
89 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
90 int is_jmp;
91
92 int nr_nops;
93 struct TranslationBlock *tb;
94 int singlestep_enabled;
95} DisasContext;
96
97static const char *regnames[] = {
98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
101 "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
102 "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
103 "wp1", "wp2", "wp3"
104};
105
106static inline int zero_extend(unsigned int val, int width)
107{
108 return val & ((1 << width) - 1);
109}
110
111static inline int sign_extend(unsigned int val, int width)
112{
113 int sval;
114
115 /* LSL. */
116 val <<= 32 - width;
117 sval = val;
118 /* ASR. */
119 sval >>= 32 - width;
120
121 return sval;
122}
123
124static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
125{
126 TCGv_i32 tmp = tcg_const_i32(index);
127
128 gen_helper_raise_exception(tmp);
129 tcg_temp_free_i32(tmp);
130}
131
132static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
133{
134 TranslationBlock *tb;
135
136 tb = dc->tb;
137 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
138 likely(!dc->singlestep_enabled)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_pc, dest);
4b4a72e5 141 tcg_gen_exit_tb((tcg_target_long)tb + n);
17c0fa3d
MW		 142 } else {
143 tcg_gen_movi_tl(cpu_pc, dest);
144 if (dc->singlestep_enabled) {
145 t_gen_raise_exception(dc, EXCP_DEBUG);
146 }
147 tcg_gen_exit_tb(0);
148 }
149}
150
151static void dec_add(DisasContext *dc)
152{
153 if (dc->format == OP_FMT_RI) {
154 if (dc->r0 == R_R0) {
155 if (dc->r1 == R_R0 && dc->imm16 == 0) {
156 LOG_DIS("nop\n");
157 } else {
158 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
159 }
160 } else {
161 LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
162 sign_extend(dc->imm16, 16));
163 }
164 } else {
165 LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
166 }
167
168 if (dc->format == OP_FMT_RI) {
169 tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
170 sign_extend(dc->imm16, 16));
171 } else {
172 tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
173 }
174}
175
176static void dec_and(DisasContext *dc)
177{
178 if (dc->format == OP_FMT_RI) {
179 LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
180 zero_extend(dc->imm16, 16));
181 } else {
182 LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
183 }
184
185 if (dc->format == OP_FMT_RI) {
186 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
187 zero_extend(dc->imm16, 16));
188 } else {
189 if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
190 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
191 gen_helper_hlt();
192 } else {
193 tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
194 }
195 }
196}
197
198static void dec_andhi(DisasContext *dc)
199{
200 LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
201
202 tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
203}
204
205static void dec_b(DisasContext *dc)
206{
207 if (dc->r0 == R_RA) {
208 LOG_DIS("ret\n");
209 } else if (dc->r0 == R_EA) {
210 LOG_DIS("eret\n");
211 } else if (dc->r0 == R_BA) {
212 LOG_DIS("bret\n");
213 } else {
214 LOG_DIS("b r%d\n", dc->r0);
215 }
216
217 /* restore IE.IE in case of an eret */
218 if (dc->r0 == R_EA) {
219 TCGv t0 = tcg_temp_new();
220 int l1 = gen_new_label();
221 tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
222 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
223 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
224 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
225 gen_set_label(l1);
226 tcg_temp_free(t0);
227 } else if (dc->r0 == R_BA) {
228 TCGv t0 = tcg_temp_new();
229 int l1 = gen_new_label();
230 tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
231 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
232 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
233 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
234 gen_set_label(l1);
235 tcg_temp_free(t0);
236 }
237 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
238
239 dc->is_jmp = DISAS_JUMP;
240}
241
242static void dec_bi(DisasContext *dc)
243{
244 LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
245
246 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
247
248 dc->is_jmp = DISAS_TB_JUMP;
249}
250
251static inline void gen_cond_branch(DisasContext *dc, int cond)
252{
253 int l1;
254
255 l1 = gen_new_label();
256 tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
257 gen_goto_tb(dc, 0, dc->pc + 4);
258 gen_set_label(l1);
259 gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
260 dc->is_jmp = DISAS_TB_JUMP;
261}
262
263static void dec_be(DisasContext *dc)
264{
265 LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
266 sign_extend(dc->imm16, 16) * 4);
267
268 gen_cond_branch(dc, TCG_COND_EQ);
269}
270
271static void dec_bg(DisasContext *dc)
272{
273 LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
274 sign_extend(dc->imm16, 16 * 4));
275
276 gen_cond_branch(dc, TCG_COND_GT);
277}
278
279static void dec_bge(DisasContext *dc)
280{
281 LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
282 sign_extend(dc->imm16, 16) * 4);
283
284 gen_cond_branch(dc, TCG_COND_GE);
285}
286
287static void dec_bgeu(DisasContext *dc)
288{
289 LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
290 sign_extend(dc->imm16, 16) * 4);
291
292 gen_cond_branch(dc, TCG_COND_GEU);
293}
294
295static void dec_bgu(DisasContext *dc)
296{
297 LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
298 sign_extend(dc->imm16, 16) * 4);
299
300 gen_cond_branch(dc, TCG_COND_GTU);
301}
302
303static void dec_bne(DisasContext *dc)
304{
305 LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
306 sign_extend(dc->imm16, 16) * 4);
307
308 gen_cond_branch(dc, TCG_COND_NE);
309}
310
311static void dec_call(DisasContext *dc)
312{
313 LOG_DIS("call r%d\n", dc->r0);
314
315 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
316 tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
317
318 dc->is_jmp = DISAS_JUMP;
319}
320
321static void dec_calli(DisasContext *dc)
322{
323 LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
324
325 tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
326 gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
327
328 dc->is_jmp = DISAS_TB_JUMP;
329}
330
331static inline void gen_compare(DisasContext *dc, int cond)
332{
333 int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
334 int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
335 int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
336
337 if (dc->format == OP_FMT_RI) {
338 tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY],
339 sign_extend(dc->imm16, 16));
340 } else {
341 tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
342 }
343}
344
345static void dec_cmpe(DisasContext *dc)
346{
347 if (dc->format == OP_FMT_RI) {
348 LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
349 sign_extend(dc->imm16, 16));
350 } else {
351 LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
352 }
353
354 gen_compare(dc, TCG_COND_EQ);
355}
356
357static void dec_cmpg(DisasContext *dc)
358{
359 if (dc->format == OP_FMT_RI) {
360 LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
361 sign_extend(dc->imm16, 16));
362 } else {
363 LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
364 }
365
366 gen_compare(dc, TCG_COND_GT);
367}
368
369static void dec_cmpge(DisasContext *dc)
370{
371 if (dc->format == OP_FMT_RI) {
372 LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
373 sign_extend(dc->imm16, 16));
374 } else {
375 LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
376 }
377
378 gen_compare(dc, TCG_COND_GE);
379}
380
381static void dec_cmpgeu(DisasContext *dc)
382{
383 if (dc->format == OP_FMT_RI) {
384 LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
385 sign_extend(dc->imm16, 16));
386 } else {
387 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
388 }
389
390 gen_compare(dc, TCG_COND_GEU);
391}
392
393static void dec_cmpgu(DisasContext *dc)
394{
395 if (dc->format == OP_FMT_RI) {
396 LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
397 sign_extend(dc->imm16, 16));
398 } else {
399 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
400 }
401
402 gen_compare(dc, TCG_COND_GTU);
403}
404
405static void dec_cmpne(DisasContext *dc)
406{
407 if (dc->format == OP_FMT_RI) {
408 LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
409 sign_extend(dc->imm16, 16));
410 } else {
411 LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
412 }
413
414 gen_compare(dc, TCG_COND_NE);
415}
416
417static void dec_divu(DisasContext *dc)
418{
419 int l1;
420
421 LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
422
423 if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
424 cpu_abort(dc->env, "hardware divider is not available\n");
425 }
426
427 l1 = gen_new_label();
428 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
429 tcg_gen_movi_tl(cpu_pc, dc->pc);
430 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
431 gen_set_label(l1);
432 tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
433}
434
435static void dec_lb(DisasContext *dc)
436{
437 TCGv t0;
438
439 LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
440
441 t0 = tcg_temp_new();
442 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
443 tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
444 tcg_temp_free(t0);
445}
446
447static void dec_lbu(DisasContext *dc)
448{
449 TCGv t0;
450
451 LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
452
453 t0 = tcg_temp_new();
454 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
455 tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
456 tcg_temp_free(t0);
457}
458
459static void dec_lh(DisasContext *dc)
460{
461 TCGv t0;
462
463 LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
464
465 t0 = tcg_temp_new();
466 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
467 tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
468 tcg_temp_free(t0);
469}
470
471static void dec_lhu(DisasContext *dc)
472{
473 TCGv t0;
474
475 LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
476
477 t0 = tcg_temp_new();
478 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
479 tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
480 tcg_temp_free(t0);
481}
482
483static void dec_lw(DisasContext *dc)
484{
485 TCGv t0;
486
487 LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
488
489 t0 = tcg_temp_new();
490 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
491 tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
492 tcg_temp_free(t0);
493}
494
495static void dec_modu(DisasContext *dc)
496{
497 int l1;
498
499 LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
500
501 if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
502 cpu_abort(dc->env, "hardware divider is not available\n");
503 }
504
505 l1 = gen_new_label();
506 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
507 tcg_gen_movi_tl(cpu_pc, dc->pc);
508 t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
509 gen_set_label(l1);
510 tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
511}
512
513static void dec_mul(DisasContext *dc)
514{
515 if (dc->format == OP_FMT_RI) {
516 LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
517 sign_extend(dc->imm16, 16));
518 } else {
519 LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
520 }
521
522 if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
523 cpu_abort(dc->env, "hardware multiplier is not available\n");
524 }
525
526 if (dc->format == OP_FMT_RI) {
527 tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
528 sign_extend(dc->imm16, 16));
529 } else {
530 tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
531 }
532}
533
534static void dec_nor(DisasContext *dc)
535{
536 if (dc->format == OP_FMT_RI) {
537 LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
538 zero_extend(dc->imm16, 16));
539 } else {
540 LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
541 }
542
543 if (dc->format == OP_FMT_RI) {
544 TCGv t0 = tcg_temp_new();
545 tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
546 tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
547 tcg_temp_free(t0);
548 } else {
549 tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
550 }
551}
552
553static void dec_or(DisasContext *dc)
554{
555 if (dc->format == OP_FMT_RI) {
556 LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
557 zero_extend(dc->imm16, 16));
558 } else {
559 if (dc->r1 == R_R0) {
560 LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
561 } else {
562 LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
563 }
564 }
565
566 if (dc->format == OP_FMT_RI) {
567 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
568 zero_extend(dc->imm16, 16));
569 } else {
570 tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
571 }
572}
573
574static void dec_orhi(DisasContext *dc)
575{
576 if (dc->r0 == R_R0) {
577 LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
578 } else {
579 LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
580 }
581
582 tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
583}
584
fcda9863 585static void dec_scall(DisasContext *dc)
17c0fa3d
MW		 586{
587 TCGv t0;
588 int l1;
589
590 if (dc->imm5 == 7) {
591 LOG_DIS("scall\n");
592 } else if (dc->imm5 == 2) {
593 LOG_DIS("break\n");
594 } else {
595 cpu_abort(dc->env, "invalid opcode\n");
596 }
597
598 t0 = tcg_temp_new();
599 l1 = gen_new_label();
600
601 /* save IE.IE */
602 tcg_gen_andi_tl(t0, cpu_ie, IE_IE);
603
604 /* IE.IE = 0 */
605 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
606
607 if (dc->imm5 == 7) {
608 /* IE.EIE = IE.IE */
609 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_EIE);
610 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_IE, l1);
611 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_EIE);
612 gen_set_label(l1);
613
614 /* gpr[ea] = PC */
615 tcg_gen_movi_tl(cpu_R[R_EA], dc->pc);
616 tcg_temp_free(t0);
617
618 tcg_gen_movi_tl(cpu_pc, dc->pc);
619 t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
620 } else {
621 /* IE.BIE = IE.IE */
622 tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_BIE);
623 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_IE, l1);
624 tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_BIE);
625 gen_set_label(l1);
626
627 /* gpr[ba] = PC */
628 tcg_gen_movi_tl(cpu_R[R_BA], dc->pc);
629 tcg_temp_free(t0);
630
631 tcg_gen_movi_tl(cpu_pc, dc->pc);
632 t_gen_raise_exception(dc, EXCP_BREAKPOINT);
633 }
634}
635
636static void dec_rcsr(DisasContext *dc)
637{
638 LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
639
640 switch (dc->csr) {
641 case CSR_IE:
642 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
643 break;
644 case CSR_IM:
645 gen_helper_rcsr_im(cpu_R[dc->r2]);
646 break;
647 case CSR_IP:
648 gen_helper_rcsr_ip(cpu_R[dc->r2]);
649 break;
650 case CSR_CC:
651 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
652 break;
653 case CSR_CFG:
654 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
655 break;
656 case CSR_EBA:
657 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
658 break;
659 case CSR_DC:
660 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
661 break;
662 case CSR_DEBA:
663 tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
664 break;
665 case CSR_JTX:
666 gen_helper_rcsr_jtx(cpu_R[dc->r2]);
667 break;
668 case CSR_JRX:
669 gen_helper_rcsr_jrx(cpu_R[dc->r2]);
670 break;
671 case CSR_ICC:
672 case CSR_DCC:
673 case CSR_BP0:
674 case CSR_BP1:
675 case CSR_BP2:
676 case CSR_BP3:
677 case CSR_WP0:
678 case CSR_WP1:
679 case CSR_WP2:
680 case CSR_WP3:
681 cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
682 break;
683 default:
684 cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
685 break;
686 }
687}
688
689static void dec_sb(DisasContext *dc)
690{
691 TCGv t0;
692
693 LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
694
695 t0 = tcg_temp_new();
696 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
697 tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
698 tcg_temp_free(t0);
699}
700
701static void dec_sextb(DisasContext *dc)
702{
703 LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
704
705 if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
706 cpu_abort(dc->env, "hardware sign extender is not available\n");
707 }
708
709 tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
710}
711
712static void dec_sexth(DisasContext *dc)
713{
714 LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
715
716 if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
717 cpu_abort(dc->env, "hardware sign extender is not available\n");
718 }
719
720 tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
721}
722
723static void dec_sh(DisasContext *dc)
724{
725 TCGv t0;
726
727 LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
728
729 t0 = tcg_temp_new();
730 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
731 tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
732 tcg_temp_free(t0);
733}
734
735static void dec_sl(DisasContext *dc)
736{
737 if (dc->format == OP_FMT_RI) {
738 LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
739 } else {
740 LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
741 }
742
743 if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
744 cpu_abort(dc->env, "hardware shifter is not available\n");
745 }
746
747 if (dc->format == OP_FMT_RI) {
748 tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
749 } else {
750 TCGv t0 = tcg_temp_new();
751 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
752 tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
753 tcg_temp_free(t0);
754 }
755}
756
757static void dec_sr(DisasContext *dc)
758{
759 if (dc->format == OP_FMT_RI) {
760 LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
761 } else {
762 LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
763 }
764
765 if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
766 if (dc->format == OP_FMT_RI) {
767 /* TODO: check r1 == 1 during runtime */
768 } else {
769 if (dc->imm5 != 1) {
770 cpu_abort(dc->env, "hardware shifter is not available\n");
771 }
772 }
773 }
774
775 if (dc->format == OP_FMT_RI) {
776 tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
777 } else {
778 TCGv t0 = tcg_temp_new();
779 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
780 tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
781 tcg_temp_free(t0);
782 }
783}
784
785static void dec_sru(DisasContext *dc)
786{
787 if (dc->format == OP_FMT_RI) {
788 LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
789 } else {
790 LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
791 }
792
793 if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
794 if (dc->format == OP_FMT_RI) {
795 /* TODO: check r1 == 1 during runtime */
796 } else {
797 if (dc->imm5 != 1) {
798 cpu_abort(dc->env, "hardware shifter is not available\n");
799 }
800 }
801 }
802
803 if (dc->format == OP_FMT_RI) {
804 tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
805 } else {
806 TCGv t0 = tcg_temp_new();
807 tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
808 tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
809 tcg_temp_free(t0);
810 }
811}
812
813static void dec_sub(DisasContext *dc)
814{
815 LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
816
817 tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
818}
819
820static void dec_sw(DisasContext *dc)
821{
822 TCGv t0;
823
824 LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
825
826 t0 = tcg_temp_new();
827 tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
828 tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
829 tcg_temp_free(t0);
830}
831
832static void dec_user(DisasContext *dc)
833{
834 LOG_DIS("user");
835
836 cpu_abort(dc->env, "user insn undefined\n");
837}
838
839static void dec_wcsr(DisasContext *dc)
840{
841 int no;
842
843 LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
844
845 switch (dc->csr) {
846 case CSR_IE:
847 tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
848 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
849 dc->is_jmp = DISAS_UPDATE;
850 break;
851 case CSR_IM:
852 /* mark as an io operation because it could cause an interrupt */
853 if (use_icount) {
854 gen_io_start();
855 }
856 gen_helper_wcsr_im(cpu_R[dc->r1]);
857 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
858 if (use_icount) {
859 gen_io_end();
860 }
861 dc->is_jmp = DISAS_UPDATE;
862 break;
863 case CSR_IP:
864 /* mark as an io operation because it could cause an interrupt */
865 if (use_icount) {
866 gen_io_start();
867 }
868 gen_helper_wcsr_ip(cpu_R[dc->r1]);
869 tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
870 if (use_icount) {
871 gen_io_end();
872 }
873 dc->is_jmp = DISAS_UPDATE;
874 break;
875 case CSR_ICC:
876 /* TODO */
877 break;
878 case CSR_DCC:
879 /* TODO */
880 break;
881 case CSR_EBA:
882 tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
883 break;
884 case CSR_DEBA:
885 tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
886 break;
887 case CSR_JTX:
888 gen_helper_wcsr_jtx(cpu_R[dc->r1]);
889 break;
890 case CSR_JRX:
891 gen_helper_wcsr_jrx(cpu_R[dc->r1]);
892 break;
893 case CSR_DC:
894 tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
895 break;
896 case CSR_BP0:
897 case CSR_BP1:
898 case CSR_BP2:
899 case CSR_BP3:
900 no = dc->csr - CSR_BP0;
901 if (dc->env->num_bps <= no) {
902 cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
903 }
904 tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
905 break;
906 case CSR_WP0:
907 case CSR_WP1:
908 case CSR_WP2:
909 case CSR_WP3:
910 no = dc->csr - CSR_WP0;
911 if (dc->env->num_wps <= no) {
912 cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
913 }
914 tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
915 break;
916 case CSR_CC:
917 case CSR_CFG:
918 cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
919 break;
920 default:
921 cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
922 break;
923 }
924}
925
926static void dec_xnor(DisasContext *dc)
927{
928 if (dc->format == OP_FMT_RI) {
929 LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
930 zero_extend(dc->imm16, 16));
931 } else {
932 if (dc->r1 == R_R0) {
933 LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
934 } else {
935 LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
936 }
937 }
938
939 if (dc->format == OP_FMT_RI) {
940 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
941 zero_extend(dc->imm16, 16));
942 tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
943 } else {
944 tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
945 }
946}
947
948static void dec_xor(DisasContext *dc)
949{
950 if (dc->format == OP_FMT_RI) {
951 LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
952 zero_extend(dc->imm16, 16));
953 } else {
954 LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
955 }
956
957 if (dc->format == OP_FMT_RI) {
958 tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
959 zero_extend(dc->imm16, 16));
960 } else {
961 tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
962 }
963}
964
a5086f95
MW		 965static void dec_ill(DisasContext *dc)
966{
967 cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
968}
17c0fa3d 969
a5086f95 970typedef void (*DecoderInfo)(DisasContext *dc);
17c0fa3d 971static const DecoderInfo decinfo[] = {
a5086f95
MW		 972 dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
973 dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
974 dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
975 dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
976 dec_cmpne,
977 dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
978 dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
979 dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
980 dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
981 dec_cmpne
17c0fa3d
MW		 982};
983
984static inline void decode(DisasContext *dc)
985{
986 uint32_t ir;
17c0fa3d
MW		 987
988 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
989 tcg_gen_debug_insn_start(dc->pc);
990 }
991
992 dc->ir = ir = ldl_code(dc->pc);
993 LOG_DIS("%8.8x\t", dc->ir);
994
995 /* try guessing 'empty' instruction memory, although it may be a valid
996 * instruction sequence (eg. srui r0, r0, 0) */
997 if (dc->ir) {
998 dc->nr_nops = 0;
999 } else {
1000 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1001 dc->nr_nops++;
1002 if (dc->nr_nops > 4) {
1003 cpu_abort(dc->env, "fetching nop sequence\n");
1004 }
1005 }
1006
1007 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1008
1009 dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
1010 dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
1011 dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
1012
1013 dc->csr = EXTRACT_FIELD(ir, 21, 25);
1014 dc->r0 = EXTRACT_FIELD(ir, 21, 25);
1015 dc->r1 = EXTRACT_FIELD(ir, 16, 20);
1016 dc->r2 = EXTRACT_FIELD(ir, 11, 15);
1017
1018 /* bit 31 seems to indicate insn type. */
1019 if (ir & (1 << 31)) {
1020 dc->format = OP_FMT_RR;
1021 } else {
1022 dc->format = OP_FMT_RI;
1023 }
1024
a5086f95
MW		 1025 assert(ARRAY_SIZE(decinfo) == 64);
1026 assert(dc->opcode < 64);
17c0fa3d 1027
a5086f95 1028 decinfo[dc->opcode](dc);
17c0fa3d
MW		 1029}
1030
1031static void check_breakpoint(CPUState *env, DisasContext *dc)
1032{
1033 CPUBreakpoint *bp;
1034
1035 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1036 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1037 if (bp->pc == dc->pc) {
1038 tcg_gen_movi_tl(cpu_pc, dc->pc);
1039 t_gen_raise_exception(dc, EXCP_DEBUG);
1040 dc->is_jmp = DISAS_UPDATE;
1041 }
1042 }
1043 }
1044}
1045
1046/* generate intermediate code for basic block 'tb'. */
1047static void gen_intermediate_code_internal(CPUState *env,
1048 TranslationBlock *tb, int search_pc)
1049{
1050 struct DisasContext ctx, *dc = &ctx;
1051 uint16_t *gen_opc_end;
1052 uint32_t pc_start;
1053 int j, lj;
1054 uint32_t next_page_start;
1055 int num_insns;
1056 int max_insns;
1057
1058 qemu_log_try_set_file(stderr);
1059
1060 pc_start = tb->pc;
1061 dc->env = env;
1062 dc->tb = tb;
1063
1064 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1065
1066 dc->is_jmp = DISAS_NEXT;
1067 dc->pc = pc_start;
1068 dc->singlestep_enabled = env->singlestep_enabled;
1069 dc->nr_nops = 0;
1070
1071 if (pc_start & 3) {
1072 cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
1073 }
1074
1075 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1076 qemu_log("-----------------------------------------\n");
1077 log_cpu_state(env, 0);
1078 }
1079
1080 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1081 lj = -1;
1082 num_insns = 0;
1083 max_insns = tb->cflags & CF_COUNT_MASK;
1084 if (max_insns == 0) {
1085 max_insns = CF_COUNT_MASK;
1086 }
1087
1088 gen_icount_start();
1089 do {
1090 check_breakpoint(env, dc);
1091
1092 if (search_pc) {
1093 j = gen_opc_ptr - gen_opc_buf;
1094 if (lj < j) {
1095 lj++;
1096 while (lj < j) {
1097 gen_opc_instr_start[lj++] = 0;
1098 }
1099 }
1100 gen_opc_pc[lj] = dc->pc;
1101 gen_opc_instr_start[lj] = 1;
1102 gen_opc_icount[lj] = num_insns;
1103 }
1104
1105 /* Pretty disas. */
1106 LOG_DIS("%8.8x:\t", dc->pc);
1107
1108 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1109 gen_io_start();
1110 }
1111
1112 decode(dc);
1113 dc->pc += 4;
1114 num_insns++;
1115
1116 } while (!dc->is_jmp
1117 && gen_opc_ptr < gen_opc_end
1118 && !env->singlestep_enabled
1119 && !singlestep
1120 && (dc->pc < next_page_start)
1121 && num_insns < max_insns);
1122
1123 if (tb->cflags & CF_LAST_IO) {
1124 gen_io_end();
1125 }
1126
1127 if (unlikely(env->singlestep_enabled)) {
1128 if (dc->is_jmp == DISAS_NEXT) {
1129 tcg_gen_movi_tl(cpu_pc, dc->pc);
1130 }
1131 t_gen_raise_exception(dc, EXCP_DEBUG);
1132 } else {
1133 switch (dc->is_jmp) {
1134 case DISAS_NEXT:
1135 gen_goto_tb(dc, 1, dc->pc);
1136 break;
1137 default:
1138 case DISAS_JUMP:
1139 case DISAS_UPDATE:
1140 /* indicate that the hash table must be used
1141 to find the next TB */
1142 tcg_gen_exit_tb(0);
1143 break;
1144 case DISAS_TB_JUMP:
1145 /* nothing more to generate */
1146 break;
1147 }
1148 }
1149
1150 gen_icount_end(tb, num_insns);
1151 *gen_opc_ptr = INDEX_op_end;
1152 if (search_pc) {
1153 j = gen_opc_ptr - gen_opc_buf;
1154 lj++;
1155 while (lj <= j) {
1156 gen_opc_instr_start[lj++] = 0;
1157 }
1158 } else {
1159 tb->size = dc->pc - pc_start;
1160 tb->icount = num_insns;
1161 }
1162
1163#ifdef DEBUG_DISAS
1164 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1165 qemu_log("\n");
1166 log_target_disas(pc_start, dc->pc - pc_start, 0);
1167 qemu_log("\nisize=%d osize=%zd\n",
1168 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1169 }
1170#endif
1171}
1172
1173void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb)
1174{
1175 gen_intermediate_code_internal(env, tb, 0);
1176}
1177
1178void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb)
1179{
1180 gen_intermediate_code_internal(env, tb, 1);
1181}
1182
1183void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1184 int flags)
1185{
1186 int i;
1187
1188 if (!env || !f) {
1189 return;
1190 }
1191
1192 cpu_fprintf(f, "IN: PC=%x %s\n",
1193 env->pc, lookup_symbol(env->pc));
1194
1195 cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1196 env->ie,
1197 (env->ie & IE_IE) ? 1 : 0,
1198 (env->ie & IE_EIE) ? 1 : 0,
1199 (env->ie & IE_BIE) ? 1 : 0,
1200 lm32_pic_get_im(env->pic_state),
1201 lm32_pic_get_ip(env->pic_state));
1202 cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1203 env->eba,
1204 env->deba);
1205
1206 for (i = 0; i < 32; i++) {
1207 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1208 if ((i + 1) % 4 == 0) {
1209 cpu_fprintf(f, "\n");
1210 }
1211 }
1212 cpu_fprintf(f, "\n\n");
1213}
1214
1215void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1216 unsigned long searched_pc, int pc_pos, void *puc)
1217{
1218 env->pc = gen_opc_pc[pc_pos];
1219}
1220
1221void lm32_translate_init(void)
1222{
1223 int i;
1224
1225 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1226
1227 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1228 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1229 offsetof(CPUState, regs[i]),
1230 regnames[i]);
1231 }
1232
1233 for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1234 cpu_bp[i] = tcg_global_mem_new(TCG_AREG0,
1235 offsetof(CPUState, bp[i]),
1236 regnames[32+i]);
1237 }
1238
1239 for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1240 cpu_wp[i] = tcg_global_mem_new(TCG_AREG0,
1241 offsetof(CPUState, wp[i]),
1242 regnames[36+i]);
1243 }
1244
1245 cpu_pc = tcg_global_mem_new(TCG_AREG0,
1246 offsetof(CPUState, pc),
1247 "pc");
1248 cpu_ie = tcg_global_mem_new(TCG_AREG0,
1249 offsetof(CPUState, ie),
1250 "ie");
1251 cpu_icc = tcg_global_mem_new(TCG_AREG0,
1252 offsetof(CPUState, icc),
1253 "icc");
1254 cpu_dcc = tcg_global_mem_new(TCG_AREG0,
1255 offsetof(CPUState, dcc),
1256 "dcc");
1257 cpu_cc = tcg_global_mem_new(TCG_AREG0,
1258 offsetof(CPUState, cc),
1259 "cc");
1260 cpu_cfg = tcg_global_mem_new(TCG_AREG0,
1261 offsetof(CPUState, cfg),
1262 "cfg");
1263 cpu_eba = tcg_global_mem_new(TCG_AREG0,
1264 offsetof(CPUState, eba),
1265 "eba");
1266 cpu_dc = tcg_global_mem_new(TCG_AREG0,
1267 offsetof(CPUState, dc),
1268 "dc");
1269 cpu_deba = tcg_global_mem_new(TCG_AREG0,
1270 offsetof(CPUState, deba),
1271 "deba");
1272}
1273
Qemu copy for testing