]> git.proxmox.com Git - qemu.git/blame - target-m68k/op_helper.c
cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / target-m68k / op_helper.c
CommitLineData
0633879f
PB
1/*
2 * M68K helper routines
5fafdf24 3 *
0633879f
PB
4 * Copyright (c) 2007 CodeSourcery
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
0633879f 18 */
3e457172 19#include "cpu.h"
e1f3808e 20#include "helpers.h"
0633879f
PB
21
22#if defined(CONFIG_USER_ONLY)
23
31871141 24void do_interrupt(CPUM68KState *env)
3c688828 25{
31871141 26 env->exception_index = -1;
3c688828
BS
27}
28
31871141 29void do_interrupt_m68k_hardirq(CPUM68KState *env)
0633879f 30{
0633879f
PB
31}
32
33#else
34
a87295e8
PB
35extern int semihosting_enabled;
36
022c62cb 37#include "exec/softmmu_exec.h"
3e457172 38
0633879f 39#define MMUSUFFIX _mmu
0633879f
PB
40
41#define SHIFT 0
022c62cb 42#include "exec/softmmu_template.h"
0633879f
PB
43
44#define SHIFT 1
022c62cb 45#include "exec/softmmu_template.h"
0633879f
PB
46
47#define SHIFT 2
022c62cb 48#include "exec/softmmu_template.h"
0633879f
PB
49
50#define SHIFT 3
022c62cb 51#include "exec/softmmu_template.h"
0633879f
PB
52
53/* Try to fill the TLB and return an exception if error. If retaddr is
54 NULL, it means that the function was called in C code (i.e. not
55 from generated code or from helper.c) */
31871141 56void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
20503968 57 uintptr_t retaddr)
0633879f 58{
0633879f
PB
59 int ret;
60
97b348e7 61 ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
551bd27f 62 if (unlikely(ret)) {
0633879f
PB
63 if (retaddr) {
64 /* now we have a real cpu fault */
a8a826a3 65 cpu_restore_state(env, retaddr);
0633879f 66 }
1162c041 67 cpu_loop_exit(env);
0633879f 68 }
0633879f
PB
69}
70
31871141 71static void do_rte(CPUM68KState *env)
0633879f
PB
72{
73 uint32_t sp;
74 uint32_t fmt;
75
76 sp = env->aregs[7];
31871141
BS
77 fmt = cpu_ldl_kernel(env, sp);
78 env->pc = cpu_ldl_kernel(env, sp + 4);
0633879f
PB
79 sp |= (fmt >> 28) & 3;
80 env->sr = fmt & 0xffff;
20dcee94 81 m68k_switch_sp(env);
0633879f
PB
82 env->aregs[7] = sp + 8;
83}
84
31871141 85static void do_interrupt_all(CPUM68KState *env, int is_hw)
0633879f 86{
259186a7 87 CPUState *cs;
0633879f
PB
88 uint32_t sp;
89 uint32_t fmt;
90 uint32_t retaddr;
91 uint32_t vector;
92
93 fmt = 0;
94 retaddr = env->pc;
95
96 if (!is_hw) {
97 switch (env->exception_index) {
98 case EXCP_RTE:
99 /* Return from an exception. */
31871141 100 do_rte(env);
0633879f 101 return;
a87295e8
PB
102 case EXCP_HALT_INSN:
103 if (semihosting_enabled
104 && (env->sr & SR_S) != 0
105 && (env->pc & 3) == 0
31871141
BS
106 && cpu_lduw_code(env, env->pc - 4) == 0x4e71
107 && cpu_ldl_code(env, env->pc) == 0x4e7bf000) {
a87295e8
PB
108 env->pc += 4;
109 do_m68k_semihosting(env, env->dregs[0]);
110 return;
111 }
259186a7
AF
112 cs = CPU(m68k_env_get_cpu(env));
113 cs->halted = 1;
a87295e8 114 env->exception_index = EXCP_HLT;
1162c041 115 cpu_loop_exit(env);
a87295e8 116 return;
0633879f
PB
117 }
118 if (env->exception_index >= EXCP_TRAP0
119 && env->exception_index <= EXCP_TRAP15) {
120 /* Move the PC after the trap instruction. */
121 retaddr += 2;
122 }
123 }
124
0633879f
PB
125 vector = env->exception_index << 2;
126
0cf5c677
PB
127 sp = env->aregs[7];
128
0633879f
PB
129 fmt |= 0x40000000;
130 fmt |= (sp & 3) << 28;
131 fmt |= vector << 16;
132 fmt |= env->sr;
133
20dcee94
PB
134 env->sr |= SR_S;
135 if (is_hw) {
136 env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
137 env->sr &= ~SR_M;
138 }
139 m68k_switch_sp(env);
140
0633879f
PB
141 /* ??? This could cause MMU faults. */
142 sp &= ~3;
143 sp -= 4;
31871141 144 cpu_stl_kernel(env, sp, retaddr);
0633879f 145 sp -= 4;
31871141 146 cpu_stl_kernel(env, sp, fmt);
0633879f 147 env->aregs[7] = sp;
0633879f 148 /* Jump to vector. */
31871141 149 env->pc = cpu_ldl_kernel(env, env->vbr + vector);
0633879f
PB
150}
151
31871141 152void do_interrupt(CPUM68KState *env)
3c688828 153{
31871141 154 do_interrupt_all(env, 0);
3c688828
BS
155}
156
31871141 157void do_interrupt_m68k_hardirq(CPUM68KState *env)
3c688828 158{
31871141 159 do_interrupt_all(env, 1);
3c688828 160}
0633879f 161#endif
e1f3808e 162
31871141 163static void raise_exception(CPUM68KState *env, int tt)
e1f3808e
PB
164{
165 env->exception_index = tt;
1162c041 166 cpu_loop_exit(env);
e1f3808e
PB
167}
168
31871141 169void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
e1f3808e 170{
31871141 171 raise_exception(env, tt);
e1f3808e
PB
172}
173
2b3e3cfe 174void HELPER(divu)(CPUM68KState *env, uint32_t word)
e1f3808e
PB
175{
176 uint32_t num;
177 uint32_t den;
178 uint32_t quot;
179 uint32_t rem;
180 uint32_t flags;
181
182 num = env->div1;
183 den = env->div2;
184 /* ??? This needs to make sure the throwing location is accurate. */
31871141
BS
185 if (den == 0) {
186 raise_exception(env, EXCP_DIV0);
187 }
e1f3808e
PB
188 quot = num / den;
189 rem = num % den;
190 flags = 0;
e1f3808e
PB
191 if (word && quot > 0xffff)
192 flags |= CCF_V;
193 if (quot == 0)
194 flags |= CCF_Z;
195 else if ((int32_t)quot < 0)
196 flags |= CCF_N;
197 env->div1 = quot;
198 env->div2 = rem;
199 env->cc_dest = flags;
200}
201
2b3e3cfe 202void HELPER(divs)(CPUM68KState *env, uint32_t word)
e1f3808e
PB
203{
204 int32_t num;
205 int32_t den;
206 int32_t quot;
207 int32_t rem;
208 int32_t flags;
209
210 num = env->div1;
211 den = env->div2;
31871141
BS
212 if (den == 0) {
213 raise_exception(env, EXCP_DIV0);
214 }
e1f3808e
PB
215 quot = num / den;
216 rem = num % den;
217 flags = 0;
218 if (word && quot != (int16_t)quot)
219 flags |= CCF_V;
220 if (quot == 0)
221 flags |= CCF_Z;
222 else if (quot < 0)
223 flags |= CCF_N;
224 env->div1 = quot;
225 env->div2 = rem;
226 env->cc_dest = flags;
227}