[qemu.git] / target-microblaze / helper.c

/*
 *  MicroBlaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "qemu/host-utils.h"

#define D(x)
#define DMMU(x)

#if defined(CONFIG_USER_ONLY)

void mb_cpu_do_interrupt(CPUState *cs)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;

    env->exception_index = -1;
    env->res_addr = RES_ADDR_NONE;
    env->regs[14] = env->sregs[SR_PC];
}

int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
                            int mmu_idx)
{
    env->exception_index = 0xaa;
    cpu_dump_state(env, stderr, fprintf, 0);
    return 1;
}

#else /* !CONFIG_USER_ONLY */

int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
                             int mmu_idx)
{
    unsigned int hit;
    unsigned int mmu_available;
    int r = 1;
    int prot;

    mmu_available = 0;
    if (env->pvr.regs[0] & PVR0_USE_MMU) {
        mmu_available = 1;
        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
            mmu_available = 0;
        }
    }

    /* Translate if the MMU is available and enabled.  */
    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
        target_ulong vaddr, paddr;
        struct microblaze_mmu_lookup lu;

        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
        if (hit) {
            vaddr = address & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;

            DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
                     mmu_idx, vaddr, paddr, lu.prot));
            tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
            r = 0;
        } else {
            env->sregs[SR_EAR] = address;
            DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));

            switch (lu.err) {
                case ERR_PROT:
                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                case ERR_MISS:
                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                default:
                    abort();
                    break;
            }

            if (env->exception_index == EXCP_MMU) {
                cpu_abort(env, "recursive faults\n");
            }

            /* TLB miss.  */
            env->exception_index = EXCP_MMU;
        }
    } else {
        /* MMU disabled or not available.  */
        address &= TARGET_PAGE_MASK;
        prot = PAGE_BITS;
        tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
        r = 0;
    }
    return r;
}

void mb_cpu_do_interrupt(CPUState *cs)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    uint32_t t;

    /* IMM flag cannot propagate across a branch and into the dslot.  */
    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
    env->res_addr = RES_ADDR_NONE;
    switch (env->exception_index) {
        case EXCP_HW_EXCP:
            if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
                qemu_log("Exception raised on system without exceptions!\n");
                return;
            }

            env->regs[17] = env->sregs[SR_PC] + 4;
            env->sregs[SR_ESR] &= ~(1 << 12);

            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR],
                          env->sregs[SR_ESR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, env, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = 0x20;
            break;

        case EXCP_MMU:
            env->regs[17] = env->sregs[SR_PC];

            env->sregs[SR_ESR] &= ~(1 << 12);
            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;

                /* Reexecute the branch.  */
                env->regs[17] -= 4;
                /* was the branch immprefixed?.  */
                if (env->bimm) {
                    qemu_log_mask(CPU_LOG_INT,
                                  "bimm exception at pc=%x iflags=%x\n",
                                  env->sregs[SR_PC], env->iflags);
                    env->regs[17] -= 4;
                    log_cpu_state_mask(CPU_LOG_INT, env, 0);
                }
            } else if (env->iflags & IMM_FLAG) {
                D(qemu_log("IMM_FLAG set at exception\n"));
                env->regs[17] -= 4;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "exception at pc=%x ear=%x iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, env, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = 0x20;
            break;

        case EXCP_IRQ:
            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
            assert(env->sregs[SR_MSR] & MSR_IE);
            assert(!(env->iflags & D_FLAG));

            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;

#if 0
#include "disas/disas.h"

/* Useful instrumentation when debugging interrupt issues in either
   the models or in sw.  */
            {
                const char *sym;

                sym = lookup_symbol(env->sregs[SR_PC]);
                if (sym
                    && (!strcmp("netif_rx", sym)
                        || !strcmp("process_backlog", sym))) {

                    qemu_log(
                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
                         sym);

                    log_cpu_state(env, 0);
                }
            }
#endif
            qemu_log_mask(CPU_LOG_INT,
                         "interrupt at pc=%x msr=%x %x iflags=%x\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);

            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
                                    | MSR_UM | MSR_IE);
            env->sregs[SR_MSR] |= t;

            env->regs[14] = env->sregs[SR_PC];
            env->sregs[SR_PC] = 0x10;
            //log_cpu_state_mask(CPU_LOG_INT, env, 0);
            break;

        case EXCP_BREAK:
        case EXCP_HW_BREAK:
            assert(!(env->iflags & IMM_FLAG));
            assert(!(env->iflags & D_FLAG));
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            qemu_log_mask(CPU_LOG_INT,
                        "break at pc=%x msr=%x %x iflags=%x\n",
                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, env, 0);
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            env->sregs[SR_MSR] |= MSR_BIP;
            if (env->exception_index == EXCP_HW_BREAK) {
                env->regs[16] = env->sregs[SR_PC];
                env->sregs[SR_MSR] |= MSR_BIP;
                env->sregs[SR_PC] = 0x18;
            } else
                env->sregs[SR_PC] = env->btarget;
            break;
        default:
            cpu_abort(env, "unhandled exception type=%d\n",
                      env->exception_index);
            break;
    }
}

hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
{
    target_ulong vaddr, paddr = 0;
    struct microblaze_mmu_lookup lu;
    unsigned int hit;

    if (env->sregs[SR_MSR] & MSR_VM) {
        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
        if (hit) {
            vaddr = addr & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;
        } else
            paddr = 0; /* ???.  */
    } else
        paddr = addr & TARGET_PAGE_MASK;

    return paddr;
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
4acb54ba EI	20
4acb54ba	21	#include "cpu.h"
1de7afc9	22	#include "qemu/host-utils.h"
4acb54ba EI	23
	24	#define D(x)
	25	#define DMMU(x)
	26
	27	#if defined(CONFIG_USER_ONLY)
	28
97a8ea5a	29	void mb_cpu_do_interrupt(CPUState *cs)
4acb54ba	30	{
97a8ea5a AF	31	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
	32	CPUMBState *env = &cpu->env;
	33
4acb54ba	34	env->exception_index = -1;
8cc9b43f	35	env->res_addr = RES_ADDR_NONE;
4acb54ba EI	36	env->regs[14] = env->sregs[SR_PC];
	37	}
	38
68cee38a	39	int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
97b348e7	40	int mmu_idx)
4acb54ba EI	41	{
	42	env->exception_index = 0xaa;
	43	cpu_dump_state(env, stderr, fprintf, 0);
	44	return 1;
	45	}
	46
4acb54ba EI	47	#else /* !CONFIG_USER_ONLY */
4acb54ba EI	48
68cee38a	49	int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
97b348e7	50	int mmu_idx)
4acb54ba EI	51	{
	52	unsigned int hit;
	53	unsigned int mmu_available;
	54	int r = 1;
	55	int prot;
	56
	57	mmu_available = 0;
	58	if (env->pvr.regs[0] & PVR0_USE_MMU) {
	59	mmu_available = 1;
	60	if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
	61	&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
	62	mmu_available = 0;
	63	}
	64	}
	65
	66	/* Translate if the MMU is available and enabled. */
	67	if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
	68	target_ulong vaddr, paddr;
	69	struct microblaze_mmu_lookup lu;
	70
	71	hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
	72	if (hit) {
	73	vaddr = address & TARGET_PAGE_MASK;
	74	paddr = lu.paddr + vaddr - lu.vaddr;
	75
	76	DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
	77	mmu_idx, vaddr, paddr, lu.prot));
d4c430a8 PB	78	tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8 PB	79	r = 0;
4acb54ba EI	80	} else {
4acb54ba EI	81	env->sregs[SR_EAR] = address;
21d20636	82	DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
4acb54ba EI	83
	84	switch (lu.err) {
	85	case ERR_PROT:
	86	env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
	87	env->sregs[SR_ESR] \|= (rw == 1) << 10;
	88	break;
	89	case ERR_MISS:
	90	env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
	91	env->sregs[SR_ESR] \|= (rw == 1) << 10;
	92	break;
	93	default:
	94	abort();
	95	break;
	96	}
	97
	98	if (env->exception_index == EXCP_MMU) {
	99	cpu_abort(env, "recursive faults\n");
	100	}
	101
	102	/* TLB miss. */
	103	env->exception_index = EXCP_MMU;
	104	}
	105	} else {
	106	/* MMU disabled or not available. */
	107	address &= TARGET_PAGE_MASK;
	108	prot = PAGE_BITS;
d4c430a8 PB	109	tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8 PB	110	r = 0;
4acb54ba EI	111	}
	112	return r;
	113	}
	114
97a8ea5a	115	void mb_cpu_do_interrupt(CPUState *cs)
4acb54ba	116	{
97a8ea5a AF	117	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
97a8ea5a AF	118	CPUMBState *env = &cpu->env;
4acb54ba EI	119	uint32_t t;
4acb54ba EI	120
5225d669	121	/* IMM flag cannot propagate across a branch and into the dslot. */
4acb54ba EI	122	assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
	123	assert(!(env->iflags & (DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)));
	124	/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
8cc9b43f	125	env->res_addr = RES_ADDR_NONE;
4acb54ba	126	switch (env->exception_index) {
cedb936b EI	127	case EXCP_HW_EXCP:
	128	if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
	129	qemu_log("Exception raised on system without exceptions!\n");
	130	return;
	131	}
	132
	133	env->regs[17] = env->sregs[SR_PC] + 4;
	134	env->sregs[SR_ESR] &= ~(1 << 12);
	135
	136	/* Exception breaks branch + dslot sequence? */
	137	if (env->iflags & D_FLAG) {
	138	env->sregs[SR_ESR] \|= 1 << 12 ;
	139	env->sregs[SR_BTR] = env->btarget;
	140	}
	141
	142	/* Disable the MMU. */
	143	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	144	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	145	env->sregs[SR_MSR] \|= t;
	146	/* Exception in progress. */
	147	env->sregs[SR_MSR] \|= MSR_EIP;
	148
	149	qemu_log_mask(CPU_LOG_INT,
	150	"hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
	151	env->sregs[SR_PC], env->sregs[SR_EAR],
	152	env->sregs[SR_ESR], env->iflags);
	153	log_cpu_state_mask(CPU_LOG_INT, env, 0);
	154	env->iflags &= ~(IMM_FLAG \| D_FLAG);
	155	env->sregs[SR_PC] = 0x20;
	156	break;
	157
4acb54ba EI	158	case EXCP_MMU:
	159	env->regs[17] = env->sregs[SR_PC];
	160
a75cf0c5	161	env->sregs[SR_ESR] &= ~(1 << 12);
4acb54ba EI	162	/* Exception breaks branch + dslot sequence? */
	163	if (env->iflags & D_FLAG) {
	164	D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
	165	env->sregs[SR_ESR] \|= 1 << 12 ;
	166	env->sregs[SR_BTR] = env->btarget;
	167
	168	/* Reexecute the branch. */
	169	env->regs[17] -= 4;
	170	/* was the branch immprefixed?. */
	171	if (env->bimm) {
	172	qemu_log_mask(CPU_LOG_INT,
	173	"bimm exception at pc=%x iflags=%x\n",
	174	env->sregs[SR_PC], env->iflags);
	175	env->regs[17] -= 4;
	176	log_cpu_state_mask(CPU_LOG_INT, env, 0);
	177	}
	178	} else if (env->iflags & IMM_FLAG) {
	179	D(qemu_log("IMM_FLAG set at exception\n"));
	180	env->regs[17] -= 4;
	181	}
	182
	183	/* Disable the MMU. */
	184	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	185	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	186	env->sregs[SR_MSR] \|= t;
	187	/* Exception in progress. */
	188	env->sregs[SR_MSR] \|= MSR_EIP;
	189
	190	qemu_log_mask(CPU_LOG_INT,
	191	"exception at pc=%x ear=%x iflags=%x\n",
	192	env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
	193	log_cpu_state_mask(CPU_LOG_INT, env, 0);
	194	env->iflags &= ~(IMM_FLAG \| D_FLAG);
	195	env->sregs[SR_PC] = 0x20;
	196	break;
	197
	198	case EXCP_IRQ:
	199	assert(!(env->sregs[SR_MSR] & (MSR_EIP \| MSR_BIP)));
	200	assert(env->sregs[SR_MSR] & MSR_IE);
	201	assert(!(env->iflags & D_FLAG));
	202
	203	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	204
	205	#if 0
76cad711	206	#include "disas/disas.h"
4acb54ba EI	207
	208	/* Useful instrumentation when debugging interrupt issues in either
	209	the models or in sw. */
	210	{
	211	const char *sym;
	212
	213	sym = lookup_symbol(env->sregs[SR_PC]);
	214	if (sym
	215	&& (!strcmp("netif_rx", sym)
	216	\|\| !strcmp("process_backlog", sym))) {
	217
	218	qemu_log(
	219	"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
	220	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
	221	sym);
	222
	223	log_cpu_state(env, 0);
	224	}
	225	}
	226	#endif
	227	qemu_log_mask(CPU_LOG_INT,
	228	"interrupt at pc=%x msr=%x %x iflags=%x\n",
	229	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
	230
	231	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \
	232	\| MSR_UM \| MSR_IE);
	233	env->sregs[SR_MSR] \|= t;
	234
	235	env->regs[14] = env->sregs[SR_PC];
	236	env->sregs[SR_PC] = 0x10;
	237	//log_cpu_state_mask(CPU_LOG_INT, env, 0);
	238	break;
	239
	240	case EXCP_BREAK:
	241	case EXCP_HW_BREAK:
	242	assert(!(env->iflags & IMM_FLAG));
	243	assert(!(env->iflags & D_FLAG));
	244	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	245	qemu_log_mask(CPU_LOG_INT,
	246	"break at pc=%x msr=%x %x iflags=%x\n",
	247	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
	248	log_cpu_state_mask(CPU_LOG_INT, env, 0);
	249	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	250	env->sregs[SR_MSR] \|= t;
	251	env->sregs[SR_MSR] \|= MSR_BIP;
	252	if (env->exception_index == EXCP_HW_BREAK) {
	253	env->regs[16] = env->sregs[SR_PC];
	254	env->sregs[SR_MSR] \|= MSR_BIP;
	255	env->sregs[SR_PC] = 0x18;
	256	} else
	257	env->sregs[SR_PC] = env->btarget;
	258	break;
	259	default:
	260	cpu_abort(env, "unhandled exception type=%d\n",
	261	env->exception_index);
	262	break;
	263	}
	264	}
	265
a8170e5e	266	hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
4acb54ba EI	267	{
	268	target_ulong vaddr, paddr = 0;
	269	struct microblaze_mmu_lookup lu;
	270	unsigned int hit;
	271
	272	if (env->sregs[SR_MSR] & MSR_VM) {
	273	hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
	274	if (hit) {
	275	vaddr = addr & TARGET_PAGE_MASK;
	276	paddr = lu.paddr + vaddr - lu.vaddr;
	277	} else
	278	paddr = 0; /* ???. */
	279	} else
	280	paddr = addr & TARGET_PAGE_MASK;
	281
	282	return paddr;
	283	}
	284	#endif