[qemu.git] / target-microblaze / helper.c

/*
 *  MicroBlaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
 */

#include <stdio.h>
#include <string.h>
#include <assert.h>

#include "config.h"
#include "cpu.h"
#include "exec-all.h"
#include "host-utils.h"

#define D(x)
#define DMMU(x)

#if defined(CONFIG_USER_ONLY)

void do_interrupt (CPUState *env)
{
    env->exception_index = -1;
    env->regs[14] = env->sregs[SR_PC];
}

int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
                             int mmu_idx, int is_softmmu)
{
    env->exception_index = 0xaa;
    cpu_dump_state(env, stderr, fprintf, 0);
    return 1;
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    return addr;
}

#else /* !CONFIG_USER_ONLY */

int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu)
{
    unsigned int hit;
    unsigned int mmu_available;
    int r = 1;
    int prot;

    mmu_available = 0;
    if (env->pvr.regs[0] & PVR0_USE_MMU) {
        mmu_available = 1;
        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
            mmu_available = 0;
        }
    }

    /* Translate if the MMU is available and enabled.  */
    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
        target_ulong vaddr, paddr;
        struct microblaze_mmu_lookup lu;

        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
        if (hit) {
            vaddr = address & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;

            DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
                     mmu_idx, vaddr, paddr, lu.prot));
            r = tlb_set_page(env, vaddr,
                             paddr, lu.prot, mmu_idx, is_softmmu);
        } else {
            env->sregs[SR_EAR] = address;
            DMMU(qemu_log("mmu=%d miss addr=%x\n", mmu_idx, vaddr));

            switch (lu.err) {
                case ERR_PROT:
                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                case ERR_MISS:
                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                default:
                    abort();
                    break;
            }

            if (env->exception_index == EXCP_MMU) {
                cpu_abort(env, "recursive faults\n");
            }

            /* TLB miss.  */
            env->exception_index = EXCP_MMU;
        }
    } else {
        /* MMU disabled or not available.  */
        address &= TARGET_PAGE_MASK;
        prot = PAGE_BITS;
        r = tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);
    }
    return r;
}

void do_interrupt(CPUState *env)
{
    uint32_t t;

    /* IMM flag cannot propagate accross a branch and into the dslot.  */
    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
    switch (env->exception_index) {
        case EXCP_MMU:
            env->regs[17] = env->sregs[SR_PC];

            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;

                /* Reexecute the branch.  */
                env->regs[17] -= 4;
                /* was the branch immprefixed?.  */
                if (env->bimm) {
                    qemu_log_mask(CPU_LOG_INT,
                                  "bimm exception at pc=%x iflags=%x\n",
                                  env->sregs[SR_PC], env->iflags);
                    env->regs[17] -= 4;
                    log_cpu_state_mask(CPU_LOG_INT, env, 0);
                }
            } else if (env->iflags & IMM_FLAG) {
                D(qemu_log("IMM_FLAG set at exception\n"));
                env->regs[17] -= 4;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "exception at pc=%x ear=%x iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, env, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = 0x20;
            break;

        case EXCP_IRQ:
            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
            assert(env->sregs[SR_MSR] & MSR_IE);
            assert(!(env->iflags & D_FLAG));

            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;

#if 0
#include "disas.h"

/* Useful instrumentation when debugging interrupt issues in either
   the models or in sw.  */
            {
                const char *sym;

                sym = lookup_symbol(env->sregs[SR_PC]);
                if (sym
                    && (!strcmp("netif_rx", sym)
                        || !strcmp("process_backlog", sym))) {

                    qemu_log(
                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
                         sym);

                    log_cpu_state(env, 0);
                }
            }
#endif
            qemu_log_mask(CPU_LOG_INT,
                         "interrupt at pc=%x msr=%x %x iflags=%x\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);

            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
                                    | MSR_UM | MSR_IE);
            env->sregs[SR_MSR] |= t;

            env->regs[14] = env->sregs[SR_PC];
            env->sregs[SR_PC] = 0x10;
            //log_cpu_state_mask(CPU_LOG_INT, env, 0);
            break;

        case EXCP_BREAK:
        case EXCP_HW_BREAK:
            assert(!(env->iflags & IMM_FLAG));
            assert(!(env->iflags & D_FLAG));
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            qemu_log_mask(CPU_LOG_INT,
                        "break at pc=%x msr=%x %x iflags=%x\n",
                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, env, 0);
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            env->sregs[SR_MSR] |= MSR_BIP;
            if (env->exception_index == EXCP_HW_BREAK) {
                env->regs[16] = env->sregs[SR_PC];
                env->sregs[SR_MSR] |= MSR_BIP;
                env->sregs[SR_PC] = 0x18;
            } else
                env->sregs[SR_PC] = env->btarget;
            break;
        default:
            cpu_abort(env, "unhandled exception type=%d\n",
                      env->exception_index);
            break;
    }
}

target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
    target_ulong vaddr, paddr = 0;
    struct microblaze_mmu_lookup lu;
    unsigned int hit;

    if (env->sregs[SR_MSR] & MSR_VM) {
        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
        if (hit) {
            vaddr = addr & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;
        } else
            paddr = 0; /* ???.  */
    } else
        paddr = addr & TARGET_PAGE_MASK;

    return paddr;
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
	19	*/
	20
	21	#include <stdio.h>
	22	#include <string.h>
	23	#include <assert.h>
	24
	25	#include "config.h"
	26	#include "cpu.h"
	27	#include "exec-all.h"
	28	#include "host-utils.h"
	29
	30	#define D(x)
	31	#define DMMU(x)
	32
	33	#if defined(CONFIG_USER_ONLY)
	34
	35	void do_interrupt (CPUState *env)
	36	{
	37	env->exception_index = -1;
	38	env->regs[14] = env->sregs[SR_PC];
	39	}
	40
	41	int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
	42	int mmu_idx, int is_softmmu)
	43	{
	44	env->exception_index = 0xaa;
	45	cpu_dump_state(env, stderr, fprintf, 0);
	46	return 1;
	47	}
	48
	49	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
	50	{
	51	return addr;
	52	}
	53
	54	#else /* !CONFIG_USER_ONLY */
	55
	56	int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	57	int mmu_idx, int is_softmmu)
	58	{
	59	unsigned int hit;
	60	unsigned int mmu_available;
	61	int r = 1;
	62	int prot;
	63
	64	mmu_available = 0;
65	if (env->pvr.regs[0] & PVR0_USE_MMU) {
66	mmu_available = 1;
67	if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
68	&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
69	mmu_available = 0;
70	}
71	}
72
73	/* Translate if the MMU is available and enabled. */
74	if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
75	target_ulong vaddr, paddr;
76	struct microblaze_mmu_lookup lu;
77
78	hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
79	if (hit) {
80	vaddr = address & TARGET_PAGE_MASK;
81	paddr = lu.paddr + vaddr - lu.vaddr;
82
83	DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
84	mmu_idx, vaddr, paddr, lu.prot));
85	r = tlb_set_page(env, vaddr,
86	paddr, lu.prot, mmu_idx, is_softmmu);
87	} else {
88	env->sregs[SR_EAR] = address;
89	DMMU(qemu_log("mmu=%d miss addr=%x\n", mmu_idx, vaddr));
90
91	switch (lu.err) {
92	case ERR_PROT:
93	env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
94	env->sregs[SR_ESR] \|= (rw == 1) << 10;
95	break;
96	case ERR_MISS:
97	env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
98	env->sregs[SR_ESR] \|= (rw == 1) << 10;
99	break;
100	default:
101	abort();
102	break;
103	}
104
105	if (env->exception_index == EXCP_MMU) {
106	cpu_abort(env, "recursive faults\n");
107	}
108
109	/* TLB miss. */
110	env->exception_index = EXCP_MMU;
111	}
112	} else {
113	/* MMU disabled or not available. */
114	address &= TARGET_PAGE_MASK;
115	prot = PAGE_BITS;
116	r = tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);
117	}
118	return r;
119	}
120
121	void do_interrupt(CPUState *env)
122	{
123	uint32_t t;
124
125	/* IMM flag cannot propagate accross a branch and into the dslot. */
126	assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
127	assert(!(env->iflags & (DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)));
128	/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
129	switch (env->exception_index) {
130	case EXCP_MMU:
131	env->regs[17] = env->sregs[SR_PC];
132
133	/* Exception breaks branch + dslot sequence? */
134	if (env->iflags & D_FLAG) {
135	D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
136	env->sregs[SR_ESR] \|= 1 << 12 ;
137	env->sregs[SR_BTR] = env->btarget;
138
139	/* Reexecute the branch. */
140	env->regs[17] -= 4;
141	/* was the branch immprefixed?. */
142	if (env->bimm) {
143	qemu_log_mask(CPU_LOG_INT,
144	"bimm exception at pc=%x iflags=%x\n",
145	env->sregs[SR_PC], env->iflags);
146	env->regs[17] -= 4;
147	log_cpu_state_mask(CPU_LOG_INT, env, 0);
148	}
149	} else if (env->iflags & IMM_FLAG) {
150	D(qemu_log("IMM_FLAG set at exception\n"));
151	env->regs[17] -= 4;
152	}
153
154	/* Disable the MMU. */
155	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
156	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
157	env->sregs[SR_MSR] \|= t;
158	/* Exception in progress. */
159	env->sregs[SR_MSR] \|= MSR_EIP;
160
161	qemu_log_mask(CPU_LOG_INT,
162	"exception at pc=%x ear=%x iflags=%x\n",
163	env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
164	log_cpu_state_mask(CPU_LOG_INT, env, 0);
165	env->iflags &= ~(IMM_FLAG \| D_FLAG);
166	env->sregs[SR_PC] = 0x20;
167	break;
168
169	case EXCP_IRQ:
170	assert(!(env->sregs[SR_MSR] & (MSR_EIP \| MSR_BIP)));
171	assert(env->sregs[SR_MSR] & MSR_IE);
172	assert(!(env->iflags & D_FLAG));
173
174	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
175
176	#if 0
177	#include "disas.h"
178
179	/* Useful instrumentation when debugging interrupt issues in either
180	the models or in sw. */
181	{
182	const char *sym;
183
184	sym = lookup_symbol(env->sregs[SR_PC]);
185	if (sym
186	&& (!strcmp("netif_rx", sym)
187	\|\| !strcmp("process_backlog", sym))) {
188
189	qemu_log(
190	"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
191	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
192	sym);
193
194	log_cpu_state(env, 0);
195	}
196	}
197	#endif
198	qemu_log_mask(CPU_LOG_INT,
199	"interrupt at pc=%x msr=%x %x iflags=%x\n",
200	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
201
202	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \
203	\| MSR_UM \| MSR_IE);
204	env->sregs[SR_MSR] \|= t;
205
206	env->regs[14] = env->sregs[SR_PC];
207	env->sregs[SR_PC] = 0x10;
208	//log_cpu_state_mask(CPU_LOG_INT, env, 0);
209	break;
210
211	case EXCP_BREAK:
212	case EXCP_HW_BREAK:
213	assert(!(env->iflags & IMM_FLAG));
214	assert(!(env->iflags & D_FLAG));
215	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
216	qemu_log_mask(CPU_LOG_INT,
217	"break at pc=%x msr=%x %x iflags=%x\n",
218	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
219	log_cpu_state_mask(CPU_LOG_INT, env, 0);
220	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
221	env->sregs[SR_MSR] \|= t;
222	env->sregs[SR_MSR] \|= MSR_BIP;
223	if (env->exception_index == EXCP_HW_BREAK) {
224	env->regs[16] = env->sregs[SR_PC];
225	env->sregs[SR_MSR] \|= MSR_BIP;
226	env->sregs[SR_PC] = 0x18;
227	} else
228	env->sregs[SR_PC] = env->btarget;
229	break;
230	default:
231	cpu_abort(env, "unhandled exception type=%d\n",
232	env->exception_index);
233	break;
234	}
235	}
236
237	target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
238	{
239	target_ulong vaddr, paddr = 0;
240	struct microblaze_mmu_lookup lu;
241	unsigned int hit;
242
243	if (env->sregs[SR_MSR] & MSR_VM) {
244	hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
245	if (hit) {
246	vaddr = addr & TARGET_PAGE_MASK;
247	paddr = lu.paddr + vaddr - lu.vaddr;
248	} else
249	paddr = 0; /* ???. */
250	} else
251	paddr = addr & TARGET_PAGE_MASK;
252
253	return paddr;
254	}
255	#endif