[qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <assert.h>
#include "cpu.h"
#include "dyngen-exec.h"
#include "helper.h"
#include "host-utils.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc);
            }
        }
        cpu_loop_exit(env);
    }
    env = saved_env;
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(uint32_t index)
{
    env->exception_index = index;
    cpu_loop_exit(env);
}

void helper_debug(void)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    uint32_t ncf;
    ncf = compute_carry(a, b, cf);
    return ncf;
}

static inline int div_prepare(uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(void)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(EXCP_HW_EXCP);
}

static void update_fpu_flags(int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception();
    }
}

uint32_t helper_fadd(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_frsub(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_fmul(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fdiv(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return r;
}

uint32_t helper_fsqrt(uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
                           int is_write, int is_exec, int is_asi, int size)
{
    CPUState *saved_env;

    saved_env = env;
    env = env1;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write, is_exec);
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        env = saved_env;
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    }
    env = saved_env;
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	18	*/
	19
	20	#include <assert.h>
3e457172 BS	21	#include "cpu.h"
3e457172 BS	22	#include "dyngen-exec.h"
4acb54ba EI	23	#include "helper.h"
	24	#include "host-utils.h"
	25
	26	#define D(x)
	27
	28	#if !defined(CONFIG_USER_ONLY)
3e457172 BS	29	#include "softmmu_exec.h"
3e457172 BS	30
4acb54ba EI	31	#define MMUSUFFIX _mmu
	32	#define SHIFT 0
	33	#include "softmmu_template.h"
	34	#define SHIFT 1
	35	#include "softmmu_template.h"
	36	#define SHIFT 2
	37	#include "softmmu_template.h"
	38	#define SHIFT 3
	39	#include "softmmu_template.h"
	40
	41	/* Try to fill the TLB and return an exception if error. If retaddr is
	42	NULL, it means that the function was called in C code (i.e. not
	43	from generated code or from helper.c) */
	44	/* XXX: fix it to restore all registers */
	45	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
	46	{
	47	TranslationBlock *tb;
	48	CPUState *saved_env;
	49	unsigned long pc;
	50	int ret;
	51
	52	/* XXX: hack to restore env in all cases, even if not called from
	53	generated code */
	54	saved_env = env;
	55	env = cpu_single_env;
	56
	57	ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
	58	if (unlikely(ret)) {
	59	if (retaddr) {
	60	/* now we have a real cpu fault */
	61	pc = (unsigned long)retaddr;
	62	tb = tb_find_pc(pc);
	63	if (tb) {
	64	/* the PC is inside the translated code. It means that we have
	65	a virtual CPU fault */
618ba8e6	66	cpu_restore_state(tb, env, pc);
4acb54ba EI	67	}
4acb54ba EI	68	}
1162c041	69	cpu_loop_exit(env);
4acb54ba EI	70	}
	71	env = saved_env;
	72	}
	73	#endif
	74
6d76d23e EI	75	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	76	{
	77	int test = ctrl & STREAM_TEST;
	78	int atomic = ctrl & STREAM_ATOMIC;
	79	int control = ctrl & STREAM_CONTROL;
	80	int nonblock = ctrl & STREAM_NONBLOCK;
	81	int exception = ctrl & STREAM_EXCEPTION;
	82
	83	qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
	84	id, data,
	85	test ? "t" : "",
	86	nonblock ? "n" : "",
	87	exception ? "e" : "",
	88	control ? "c" : "",
	89	atomic ? "a" : "");
	90	}
	91
	92	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	93	{
	94	int test = ctrl & STREAM_TEST;
	95	int atomic = ctrl & STREAM_ATOMIC;
	96	int control = ctrl & STREAM_CONTROL;
	97	int nonblock = ctrl & STREAM_NONBLOCK;
	98	int exception = ctrl & STREAM_EXCEPTION;
	99
	100	qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
	101	id,
	102	test ? "t" : "",
	103	nonblock ? "n" : "",
	104	exception ? "e" : "",
	105	control ? "c" : "",
	106	atomic ? "a" : "");
	107	return 0xdead0000 \| id;
	108	}
	109
4acb54ba EI	110	void helper_raise_exception(uint32_t index)
	111	{
	112	env->exception_index = index;
1162c041	113	cpu_loop_exit(env);
4acb54ba EI	114	}
	115
	116	void helper_debug(void)
	117	{
	118	int i;
	119
	120	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	121	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	122	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	123	env->debug, env->imm, env->iflags);
	124	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	125	env->btaken, env->btarget,
	126	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	127	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	128	(env->sregs[SR_MSR] & MSR_EIP),
	129	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	130	for (i = 0; i < 32; i++) {
	131	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	132	if ((i + 1) % 4 == 0)
	133	qemu_log("\n");
	134	}
	135	qemu_log("\n\n");
	136	}
	137
	138	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	139	{
	140	uint32_t cout = 0;
	141
	142	if ((b == ~0) && cin)
	143	cout = 1;
	144	else if ((~0 - a) < (b + cin))
	145	cout = 1;
	146	return cout;
	147	}
	148
	149	uint32_t helper_cmp(uint32_t a, uint32_t b)
	150	{
	151	uint32_t t;
	152
	153	t = b + ~a + 1;
	154	if ((b & 0x80000000) ^ (a & 0x80000000))
	155	t = (t & 0x7fffffff) \| (b & 0x80000000);
	156	return t;
	157	}
	158
	159	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	160	{
	161	uint32_t t;
	162
	163	t = b + ~a + 1;
	164	if ((b & 0x80000000) ^ (a & 0x80000000))
	165	t = (t & 0x7fffffff) \| (a & 0x80000000);
	166	return t;
	167	}
	168
5d0bb823	169	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	170	{
5d0bb823	171	uint32_t ncf;
40cbf5b7 EI	172	ncf = compute_carry(a, b, cf);
40cbf5b7 EI	173	return ncf;
4acb54ba EI	174	}
4acb54ba EI	175
4acb54ba EI	176	static inline int div_prepare(uint32_t a, uint32_t b)
	177	{
	178	if (b == 0) {
	179	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	180
	181	if ((env->sregs[SR_MSR] & MSR_EE)
	182	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	183	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
	184	helper_raise_exception(EXCP_HW_EXCP);
	185	}
4acb54ba EI	186	return 0;
	187	}
	188	env->sregs[SR_MSR] &= ~MSR_DZ;
	189	return 1;
	190	}
	191
	192	uint32_t helper_divs(uint32_t a, uint32_t b)
	193	{
	194	if (!div_prepare(a, b))
	195	return 0;
	196	return (int32_t)a / (int32_t)b;
	197	}
	198
	199	uint32_t helper_divu(uint32_t a, uint32_t b)
	200	{
	201	if (!div_prepare(a, b))
	202	return 0;
	203	return a / b;
	204	}
	205
97694c57 EI	206	/* raise FPU exception. */
	207	static void raise_fpu_exception(void)
	208	{
	209	env->sregs[SR_ESR] = ESR_EC_FPU;
	210	helper_raise_exception(EXCP_HW_EXCP);
	211	}
	212
	213	static void update_fpu_flags(int flags)
	214	{
	215	int raise = 0;
	216
	217	if (flags & float_flag_invalid) {
	218	env->sregs[SR_FSR] \|= FSR_IO;
	219	raise = 1;
	220	}
	221	if (flags & float_flag_divbyzero) {
	222	env->sregs[SR_FSR] \|= FSR_DZ;
	223	raise = 1;
	224	}
	225	if (flags & float_flag_overflow) {
	226	env->sregs[SR_FSR] \|= FSR_OF;
	227	raise = 1;
	228	}
	229	if (flags & float_flag_underflow) {
	230	env->sregs[SR_FSR] \|= FSR_UF;
	231	raise = 1;
	232	}
	233	if (raise
	234	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	235	&& (env->sregs[SR_MSR] & MSR_EE)) {
	236	raise_fpu_exception();
	237	}
	238	}
	239
	240	uint32_t helper_fadd(uint32_t a, uint32_t b)
	241	{
	242	CPU_FloatU fd, fa, fb;
	243	int flags;
	244
	245	set_float_exception_flags(0, &env->fp_status);
	246	fa.l = a;
	247	fb.l = b;
	248	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	249
	250	flags = get_float_exception_flags(&env->fp_status);
	251	update_fpu_flags(flags);
	252	return fd.l;
	253	}
	254
	255	uint32_t helper_frsub(uint32_t a, uint32_t b)
	256	{
	257	CPU_FloatU fd, fa, fb;
	258	int flags;
	259
	260	set_float_exception_flags(0, &env->fp_status);
	261	fa.l = a;
	262	fb.l = b;
	263	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	264	flags = get_float_exception_flags(&env->fp_status);
	265	update_fpu_flags(flags);
	266	return fd.l;
	267	}
	268
	269	uint32_t helper_fmul(uint32_t a, uint32_t b)
270	{
271	CPU_FloatU fd, fa, fb;
272	int flags;
273
274	set_float_exception_flags(0, &env->fp_status);
275	fa.l = a;
276	fb.l = b;
277	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
278	flags = get_float_exception_flags(&env->fp_status);
279	update_fpu_flags(flags);
280
281	return fd.l;
282	}
283
284	uint32_t helper_fdiv(uint32_t a, uint32_t b)
285	{
286	CPU_FloatU fd, fa, fb;
287	int flags;
288
289	set_float_exception_flags(0, &env->fp_status);
290	fa.l = a;
291	fb.l = b;
292	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
293	flags = get_float_exception_flags(&env->fp_status);
294	update_fpu_flags(flags);
295
296	return fd.l;
297	}
298
299	uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
300	{
ef9d48da EI	301	CPU_FloatU fa, fb;
	302	uint32_t r = 0;
	303
	304	fa.l = a;
	305	fb.l = b;
	306
	307	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
	308	update_fpu_flags(float_flag_invalid);
	309	r = 1;
	310	}
	311
18569871	312	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	313	r = 1;
	314	}
	315
	316	return r;
97694c57 EI	317	}
	318
	319	uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
	320	{
	321	CPU_FloatU fa, fb;
	322	int r;
	323	int flags;
	324
	325	set_float_exception_flags(0, &env->fp_status);
	326	fa.l = a;
	327	fb.l = b;
	328	r = float32_lt(fb.f, fa.f, &env->fp_status);
	329	flags = get_float_exception_flags(&env->fp_status);
	330	update_fpu_flags(flags & float_flag_invalid);
	331
	332	return r;
	333	}
	334
	335	uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
	336	{
	337	CPU_FloatU fa, fb;
	338	int flags;
	339	int r;
	340
	341	set_float_exception_flags(0, &env->fp_status);
	342	fa.l = a;
	343	fb.l = b;
211315fb	344	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57 EI	345	flags = get_float_exception_flags(&env->fp_status);
	346	update_fpu_flags(flags & float_flag_invalid);
	347
	348	return r;
	349	}
	350
	351	uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
	352	{
	353	CPU_FloatU fa, fb;
	354	int flags;
	355	int r;
	356
	357	fa.l = a;
	358	fb.l = b;
	359	set_float_exception_flags(0, &env->fp_status);
	360	r = float32_le(fa.f, fb.f, &env->fp_status);
	361	flags = get_float_exception_flags(&env->fp_status);
	362	update_fpu_flags(flags & float_flag_invalid);
	363
	364
	365	return r;
	366	}
	367
	368	uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
	369	{
	370	CPU_FloatU fa, fb;
	371	int flags, r;
	372
	373	fa.l = a;
	374	fb.l = b;
	375	set_float_exception_flags(0, &env->fp_status);
	376	r = float32_lt(fa.f, fb.f, &env->fp_status);
	377	flags = get_float_exception_flags(&env->fp_status);
	378	update_fpu_flags(flags & float_flag_invalid);
	379	return r;
	380	}
	381
	382	uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
	383	{
	384	CPU_FloatU fa, fb;
	385	int flags, r;
	386
	387	fa.l = a;
	388	fb.l = b;
	389	set_float_exception_flags(0, &env->fp_status);
211315fb	390	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57 EI	391	flags = get_float_exception_flags(&env->fp_status);
	392	update_fpu_flags(flags & float_flag_invalid);
	393
	394	return r;
	395	}
	396
	397	uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
	398	{
	399	CPU_FloatU fa, fb;
	400	int flags, r;
	401
	402	fa.l = a;
	403	fb.l = b;
	404	set_float_exception_flags(0, &env->fp_status);
	405	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	406	flags = get_float_exception_flags(&env->fp_status);
	407	update_fpu_flags(flags & float_flag_invalid);
	408
	409	return r;
	410	}
	411
	412	uint32_t helper_flt(uint32_t a)
	413	{
	414	CPU_FloatU fd, fa;
	415
	416	fa.l = a;
	417	fd.f = int32_to_float32(fa.l, &env->fp_status);
	418	return fd.l;
	419	}
	420
	421	uint32_t helper_fint(uint32_t a)
	422	{
	423	CPU_FloatU fa;
	424	uint32_t r;
	425	int flags;
	426
	427	set_float_exception_flags(0, &env->fp_status);
	428	fa.l = a;
	429	r = float32_to_int32(fa.f, &env->fp_status);
	430	flags = get_float_exception_flags(&env->fp_status);
	431	update_fpu_flags(flags);
	432
	433	return r;
	434	}
	435
	436	uint32_t helper_fsqrt(uint32_t a)
	437	{
	438	CPU_FloatU fd, fa;
	439	int flags;
	440
	441	set_float_exception_flags(0, &env->fp_status);
	442	fa.l = a;
	443	fd.l = float32_sqrt(fa.f, &env->fp_status);
	444	flags = get_float_exception_flags(&env->fp_status);
	445	update_fpu_flags(flags);
	446
	447	return fd.l;
	448	}
	449
4acb54ba EI	450	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	451	{
	452	unsigned int i;
	453	uint32_t mask = 0xff000000;
	454
	455	for (i = 0; i < 4; i++) {
	456	if ((a & mask) == (b & mask))
	457	return i + 1;
	458	mask >>= 8;
	459	}
	460	return 0;
	461	}
	462
3aa80988	463	void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
968a40f6	464	{
968a40f6	465	if (addr & mask) {
97f90cbf EI	466	qemu_log_mask(CPU_LOG_INT,
	467	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	468	addr, mask, wr, dr);
	469	env->sregs[SR_EAR] = addr;
968a40f6 EI	470	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	471	\| (dr & 31) << 5;
3aa80988	472	if (mask == 3) {
968a40f6 EI	473	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	474	}
97f90cbf EI	475	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	476	return;
	477	}
968a40f6 EI	478	helper_raise_exception(EXCP_HW_EXCP);
	479	}
	480	}
	481
4acb54ba EI	482	#if !defined(CONFIG_USER_ONLY)
	483	/* Writes/reads to the MMU's special regs end up here. */
	484	uint32_t helper_mmu_read(uint32_t rn)
	485	{
	486	return mmu_read(env, rn);
	487	}
	488
	489	void helper_mmu_write(uint32_t rn, uint32_t v)
	490	{
	491	mmu_write(env, rn, v);
	492	}
faed1c2a	493
b14ef7c9 BS	494	void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
b14ef7c9 BS	495	int is_write, int is_exec, int is_asi, int size)
faed1c2a EI	496	{
faed1c2a EI	497	CPUState *saved_env;
e1aa3254	498
faed1c2a	499	saved_env = env;
b14ef7c9 BS	500	env = env1;
b14ef7c9 BS	501
97f90cbf	502	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
faed1c2a EI	503	addr, is_write, is_exec);
faed1c2a EI	504	if (!(env->sregs[SR_MSR] & MSR_EE)) {
95b279de	505	env = saved_env;
faed1c2a EI	506	return;
	507	}
	508
97f90cbf	509	env->sregs[SR_EAR] = addr;
faed1c2a	510	if (is_exec) {
97f90cbf	511	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a EI	512	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
	513	helper_raise_exception(EXCP_HW_EXCP);
	514	}
	515	} else {
97f90cbf	516	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a EI	517	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
	518	helper_raise_exception(EXCP_HW_EXCP);
	519	}
	520	}
95b279de	521	env = saved_env;
faed1c2a	522	}
3c7b48b7	523	#endif