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4acb54ba EI |
1 | /* |
2 | * Microblaze helper routines. | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4acb54ba EI |
18 | */ |
19 | ||
20 | #include <assert.h> | |
21 | #include "exec.h" | |
22 | #include "helper.h" | |
23 | #include "host-utils.h" | |
24 | ||
25 | #define D(x) | |
26 | ||
27 | #if !defined(CONFIG_USER_ONLY) | |
28 | #define MMUSUFFIX _mmu | |
29 | #define SHIFT 0 | |
30 | #include "softmmu_template.h" | |
31 | #define SHIFT 1 | |
32 | #include "softmmu_template.h" | |
33 | #define SHIFT 2 | |
34 | #include "softmmu_template.h" | |
35 | #define SHIFT 3 | |
36 | #include "softmmu_template.h" | |
37 | ||
38 | /* Try to fill the TLB and return an exception if error. If retaddr is | |
39 | NULL, it means that the function was called in C code (i.e. not | |
40 | from generated code or from helper.c) */ | |
41 | /* XXX: fix it to restore all registers */ | |
42 | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) | |
43 | { | |
44 | TranslationBlock *tb; | |
45 | CPUState *saved_env; | |
46 | unsigned long pc; | |
47 | int ret; | |
48 | ||
49 | /* XXX: hack to restore env in all cases, even if not called from | |
50 | generated code */ | |
51 | saved_env = env; | |
52 | env = cpu_single_env; | |
53 | ||
54 | ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); | |
55 | if (unlikely(ret)) { | |
56 | if (retaddr) { | |
57 | /* now we have a real cpu fault */ | |
58 | pc = (unsigned long)retaddr; | |
59 | tb = tb_find_pc(pc); | |
60 | if (tb) { | |
61 | /* the PC is inside the translated code. It means that we have | |
62 | a virtual CPU fault */ | |
63 | cpu_restore_state(tb, env, pc, NULL); | |
64 | } | |
65 | } | |
66 | cpu_loop_exit(); | |
67 | } | |
68 | env = saved_env; | |
69 | } | |
70 | #endif | |
71 | ||
72 | void helper_raise_exception(uint32_t index) | |
73 | { | |
74 | env->exception_index = index; | |
75 | cpu_loop_exit(); | |
76 | } | |
77 | ||
78 | void helper_debug(void) | |
79 | { | |
80 | int i; | |
81 | ||
82 | qemu_log("PC=%8.8x\n", env->sregs[SR_PC]); | |
4c24aa0a MS |
83 | qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n", |
84 | env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], | |
17c52a43 EI |
85 | env->debug, env->imm, env->iflags); |
86 | qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", | |
87 | env->btaken, env->btarget, | |
88 | (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", | |
89 | (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", | |
90 | (env->sregs[SR_MSR] & MSR_EIP), | |
91 | (env->sregs[SR_MSR] & MSR_IE)); | |
4acb54ba EI |
92 | for (i = 0; i < 32; i++) { |
93 | qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); | |
94 | if ((i + 1) % 4 == 0) | |
95 | qemu_log("\n"); | |
96 | } | |
97 | qemu_log("\n\n"); | |
98 | } | |
99 | ||
100 | static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin) | |
101 | { | |
102 | uint32_t cout = 0; | |
103 | ||
104 | if ((b == ~0) && cin) | |
105 | cout = 1; | |
106 | else if ((~0 - a) < (b + cin)) | |
107 | cout = 1; | |
108 | return cout; | |
109 | } | |
110 | ||
111 | uint32_t helper_cmp(uint32_t a, uint32_t b) | |
112 | { | |
113 | uint32_t t; | |
114 | ||
115 | t = b + ~a + 1; | |
116 | if ((b & 0x80000000) ^ (a & 0x80000000)) | |
117 | t = (t & 0x7fffffff) | (b & 0x80000000); | |
118 | return t; | |
119 | } | |
120 | ||
121 | uint32_t helper_cmpu(uint32_t a, uint32_t b) | |
122 | { | |
123 | uint32_t t; | |
124 | ||
125 | t = b + ~a + 1; | |
126 | if ((b & 0x80000000) ^ (a & 0x80000000)) | |
127 | t = (t & 0x7fffffff) | (a & 0x80000000); | |
128 | return t; | |
129 | } | |
130 | ||
131 | uint32_t helper_addkc(uint32_t a, uint32_t b, uint32_t k, uint32_t c) | |
132 | { | |
133 | uint32_t d, cf = 0, ncf; | |
134 | ||
135 | if (c) | |
136 | cf = env->sregs[SR_MSR] >> 31; | |
137 | assert(cf == 0 || cf == 1); | |
138 | d = a + b + cf; | |
139 | ||
140 | if (!k) { | |
141 | ncf = compute_carry(a, b, cf); | |
142 | assert(ncf == 0 || ncf == 1); | |
143 | if (ncf) | |
144 | env->sregs[SR_MSR] |= MSR_C | MSR_CC; | |
145 | else | |
146 | env->sregs[SR_MSR] &= ~(MSR_C | MSR_CC); | |
147 | } | |
148 | D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n", | |
149 | d, a, b, cf, ncf, k, c)); | |
150 | return d; | |
151 | } | |
152 | ||
153 | uint32_t helper_subkc(uint32_t a, uint32_t b, uint32_t k, uint32_t c) | |
154 | { | |
155 | uint32_t d, cf = 1, ncf; | |
156 | ||
157 | if (c) | |
158 | cf = env->sregs[SR_MSR] >> 31; | |
159 | assert(cf == 0 || cf == 1); | |
160 | d = b + ~a + cf; | |
161 | ||
162 | if (!k) { | |
163 | ncf = compute_carry(b, ~a, cf); | |
164 | assert(ncf == 0 || ncf == 1); | |
165 | if (ncf) | |
166 | env->sregs[SR_MSR] |= MSR_C | MSR_CC; | |
167 | else | |
168 | env->sregs[SR_MSR] &= ~(MSR_C | MSR_CC); | |
169 | } | |
170 | D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n", | |
171 | d, a, b, cf, ncf, k, c)); | |
172 | return d; | |
173 | } | |
174 | ||
175 | static inline int div_prepare(uint32_t a, uint32_t b) | |
176 | { | |
177 | if (b == 0) { | |
178 | env->sregs[SR_MSR] |= MSR_DZ; | |
821ebb33 EI |
179 | |
180 | if ((env->sregs[SR_MSR] & MSR_EE) | |
181 | && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { | |
182 | env->sregs[SR_ESR] = ESR_EC_DIVZERO; | |
183 | helper_raise_exception(EXCP_HW_EXCP); | |
184 | } | |
4acb54ba EI |
185 | return 0; |
186 | } | |
187 | env->sregs[SR_MSR] &= ~MSR_DZ; | |
188 | return 1; | |
189 | } | |
190 | ||
191 | uint32_t helper_divs(uint32_t a, uint32_t b) | |
192 | { | |
193 | if (!div_prepare(a, b)) | |
194 | return 0; | |
195 | return (int32_t)a / (int32_t)b; | |
196 | } | |
197 | ||
198 | uint32_t helper_divu(uint32_t a, uint32_t b) | |
199 | { | |
200 | if (!div_prepare(a, b)) | |
201 | return 0; | |
202 | return a / b; | |
203 | } | |
204 | ||
97694c57 EI |
205 | /* raise FPU exception. */ |
206 | static void raise_fpu_exception(void) | |
207 | { | |
208 | env->sregs[SR_ESR] = ESR_EC_FPU; | |
209 | helper_raise_exception(EXCP_HW_EXCP); | |
210 | } | |
211 | ||
212 | static void update_fpu_flags(int flags) | |
213 | { | |
214 | int raise = 0; | |
215 | ||
216 | if (flags & float_flag_invalid) { | |
217 | env->sregs[SR_FSR] |= FSR_IO; | |
218 | raise = 1; | |
219 | } | |
220 | if (flags & float_flag_divbyzero) { | |
221 | env->sregs[SR_FSR] |= FSR_DZ; | |
222 | raise = 1; | |
223 | } | |
224 | if (flags & float_flag_overflow) { | |
225 | env->sregs[SR_FSR] |= FSR_OF; | |
226 | raise = 1; | |
227 | } | |
228 | if (flags & float_flag_underflow) { | |
229 | env->sregs[SR_FSR] |= FSR_UF; | |
230 | raise = 1; | |
231 | } | |
232 | if (raise | |
233 | && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK) | |
234 | && (env->sregs[SR_MSR] & MSR_EE)) { | |
235 | raise_fpu_exception(); | |
236 | } | |
237 | } | |
238 | ||
239 | uint32_t helper_fadd(uint32_t a, uint32_t b) | |
240 | { | |
241 | CPU_FloatU fd, fa, fb; | |
242 | int flags; | |
243 | ||
244 | set_float_exception_flags(0, &env->fp_status); | |
245 | fa.l = a; | |
246 | fb.l = b; | |
247 | fd.f = float32_add(fa.f, fb.f, &env->fp_status); | |
248 | ||
249 | flags = get_float_exception_flags(&env->fp_status); | |
250 | update_fpu_flags(flags); | |
251 | return fd.l; | |
252 | } | |
253 | ||
254 | uint32_t helper_frsub(uint32_t a, uint32_t b) | |
255 | { | |
256 | CPU_FloatU fd, fa, fb; | |
257 | int flags; | |
258 | ||
259 | set_float_exception_flags(0, &env->fp_status); | |
260 | fa.l = a; | |
261 | fb.l = b; | |
262 | fd.f = float32_sub(fb.f, fa.f, &env->fp_status); | |
263 | flags = get_float_exception_flags(&env->fp_status); | |
264 | update_fpu_flags(flags); | |
265 | return fd.l; | |
266 | } | |
267 | ||
268 | uint32_t helper_fmul(uint32_t a, uint32_t b) | |
269 | { | |
270 | CPU_FloatU fd, fa, fb; | |
271 | int flags; | |
272 | ||
273 | set_float_exception_flags(0, &env->fp_status); | |
274 | fa.l = a; | |
275 | fb.l = b; | |
276 | fd.f = float32_mul(fa.f, fb.f, &env->fp_status); | |
277 | flags = get_float_exception_flags(&env->fp_status); | |
278 | update_fpu_flags(flags); | |
279 | ||
280 | return fd.l; | |
281 | } | |
282 | ||
283 | uint32_t helper_fdiv(uint32_t a, uint32_t b) | |
284 | { | |
285 | CPU_FloatU fd, fa, fb; | |
286 | int flags; | |
287 | ||
288 | set_float_exception_flags(0, &env->fp_status); | |
289 | fa.l = a; | |
290 | fb.l = b; | |
291 | fd.f = float32_div(fb.f, fa.f, &env->fp_status); | |
292 | flags = get_float_exception_flags(&env->fp_status); | |
293 | update_fpu_flags(flags); | |
294 | ||
295 | return fd.l; | |
296 | } | |
297 | ||
298 | uint32_t helper_fcmp_un(uint32_t a, uint32_t b) | |
299 | { | |
ef9d48da EI |
300 | CPU_FloatU fa, fb; |
301 | uint32_t r = 0; | |
302 | ||
303 | fa.l = a; | |
304 | fb.l = b; | |
305 | ||
306 | if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) { | |
307 | update_fpu_flags(float_flag_invalid); | |
308 | r = 1; | |
309 | } | |
310 | ||
18569871 | 311 | if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) { |
ef9d48da EI |
312 | r = 1; |
313 | } | |
314 | ||
315 | return r; | |
97694c57 EI |
316 | } |
317 | ||
318 | uint32_t helper_fcmp_lt(uint32_t a, uint32_t b) | |
319 | { | |
320 | CPU_FloatU fa, fb; | |
321 | int r; | |
322 | int flags; | |
323 | ||
324 | set_float_exception_flags(0, &env->fp_status); | |
325 | fa.l = a; | |
326 | fb.l = b; | |
327 | r = float32_lt(fb.f, fa.f, &env->fp_status); | |
328 | flags = get_float_exception_flags(&env->fp_status); | |
329 | update_fpu_flags(flags & float_flag_invalid); | |
330 | ||
331 | return r; | |
332 | } | |
333 | ||
334 | uint32_t helper_fcmp_eq(uint32_t a, uint32_t b) | |
335 | { | |
336 | CPU_FloatU fa, fb; | |
337 | int flags; | |
338 | int r; | |
339 | ||
340 | set_float_exception_flags(0, &env->fp_status); | |
341 | fa.l = a; | |
342 | fb.l = b; | |
343 | r = float32_eq(fa.f, fb.f, &env->fp_status); | |
344 | flags = get_float_exception_flags(&env->fp_status); | |
345 | update_fpu_flags(flags & float_flag_invalid); | |
346 | ||
347 | return r; | |
348 | } | |
349 | ||
350 | uint32_t helper_fcmp_le(uint32_t a, uint32_t b) | |
351 | { | |
352 | CPU_FloatU fa, fb; | |
353 | int flags; | |
354 | int r; | |
355 | ||
356 | fa.l = a; | |
357 | fb.l = b; | |
358 | set_float_exception_flags(0, &env->fp_status); | |
359 | r = float32_le(fa.f, fb.f, &env->fp_status); | |
360 | flags = get_float_exception_flags(&env->fp_status); | |
361 | update_fpu_flags(flags & float_flag_invalid); | |
362 | ||
363 | ||
364 | return r; | |
365 | } | |
366 | ||
367 | uint32_t helper_fcmp_gt(uint32_t a, uint32_t b) | |
368 | { | |
369 | CPU_FloatU fa, fb; | |
370 | int flags, r; | |
371 | ||
372 | fa.l = a; | |
373 | fb.l = b; | |
374 | set_float_exception_flags(0, &env->fp_status); | |
375 | r = float32_lt(fa.f, fb.f, &env->fp_status); | |
376 | flags = get_float_exception_flags(&env->fp_status); | |
377 | update_fpu_flags(flags & float_flag_invalid); | |
378 | return r; | |
379 | } | |
380 | ||
381 | uint32_t helper_fcmp_ne(uint32_t a, uint32_t b) | |
382 | { | |
383 | CPU_FloatU fa, fb; | |
384 | int flags, r; | |
385 | ||
386 | fa.l = a; | |
387 | fb.l = b; | |
388 | set_float_exception_flags(0, &env->fp_status); | |
389 | r = !float32_eq(fa.f, fb.f, &env->fp_status); | |
390 | flags = get_float_exception_flags(&env->fp_status); | |
391 | update_fpu_flags(flags & float_flag_invalid); | |
392 | ||
393 | return r; | |
394 | } | |
395 | ||
396 | uint32_t helper_fcmp_ge(uint32_t a, uint32_t b) | |
397 | { | |
398 | CPU_FloatU fa, fb; | |
399 | int flags, r; | |
400 | ||
401 | fa.l = a; | |
402 | fb.l = b; | |
403 | set_float_exception_flags(0, &env->fp_status); | |
404 | r = !float32_lt(fa.f, fb.f, &env->fp_status); | |
405 | flags = get_float_exception_flags(&env->fp_status); | |
406 | update_fpu_flags(flags & float_flag_invalid); | |
407 | ||
408 | return r; | |
409 | } | |
410 | ||
411 | uint32_t helper_flt(uint32_t a) | |
412 | { | |
413 | CPU_FloatU fd, fa; | |
414 | ||
415 | fa.l = a; | |
416 | fd.f = int32_to_float32(fa.l, &env->fp_status); | |
417 | return fd.l; | |
418 | } | |
419 | ||
420 | uint32_t helper_fint(uint32_t a) | |
421 | { | |
422 | CPU_FloatU fa; | |
423 | uint32_t r; | |
424 | int flags; | |
425 | ||
426 | set_float_exception_flags(0, &env->fp_status); | |
427 | fa.l = a; | |
428 | r = float32_to_int32(fa.f, &env->fp_status); | |
429 | flags = get_float_exception_flags(&env->fp_status); | |
430 | update_fpu_flags(flags); | |
431 | ||
432 | return r; | |
433 | } | |
434 | ||
435 | uint32_t helper_fsqrt(uint32_t a) | |
436 | { | |
437 | CPU_FloatU fd, fa; | |
438 | int flags; | |
439 | ||
440 | set_float_exception_flags(0, &env->fp_status); | |
441 | fa.l = a; | |
442 | fd.l = float32_sqrt(fa.f, &env->fp_status); | |
443 | flags = get_float_exception_flags(&env->fp_status); | |
444 | update_fpu_flags(flags); | |
445 | ||
446 | return fd.l; | |
447 | } | |
448 | ||
4acb54ba EI |
449 | uint32_t helper_pcmpbf(uint32_t a, uint32_t b) |
450 | { | |
451 | unsigned int i; | |
452 | uint32_t mask = 0xff000000; | |
453 | ||
454 | for (i = 0; i < 4; i++) { | |
455 | if ((a & mask) == (b & mask)) | |
456 | return i + 1; | |
457 | mask >>= 8; | |
458 | } | |
459 | return 0; | |
460 | } | |
461 | ||
3aa80988 | 462 | void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask) |
968a40f6 | 463 | { |
968a40f6 | 464 | if (addr & mask) { |
97f90cbf EI |
465 | qemu_log_mask(CPU_LOG_INT, |
466 | "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n", | |
467 | addr, mask, wr, dr); | |
468 | env->sregs[SR_EAR] = addr; | |
968a40f6 EI |
469 | env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ |
470 | | (dr & 31) << 5; | |
3aa80988 | 471 | if (mask == 3) { |
968a40f6 EI |
472 | env->sregs[SR_ESR] |= 1 << 11; |
473 | } | |
97f90cbf EI |
474 | if (!(env->sregs[SR_MSR] & MSR_EE)) { |
475 | return; | |
476 | } | |
968a40f6 EI |
477 | helper_raise_exception(EXCP_HW_EXCP); |
478 | } | |
479 | } | |
480 | ||
4acb54ba EI |
481 | #if !defined(CONFIG_USER_ONLY) |
482 | /* Writes/reads to the MMU's special regs end up here. */ | |
483 | uint32_t helper_mmu_read(uint32_t rn) | |
484 | { | |
485 | return mmu_read(env, rn); | |
486 | } | |
487 | ||
488 | void helper_mmu_write(uint32_t rn, uint32_t v) | |
489 | { | |
490 | mmu_write(env, rn, v); | |
491 | } | |
faed1c2a | 492 | |
c227f099 | 493 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
faed1c2a EI |
494 | int is_asi, int size) |
495 | { | |
496 | CPUState *saved_env; | |
e1aa3254 EI |
497 | |
498 | if (!cpu_single_env) { | |
499 | /* XXX: ??? */ | |
500 | return; | |
501 | } | |
502 | ||
faed1c2a EI |
503 | /* XXX: hack to restore env in all cases, even if not called from |
504 | generated code */ | |
505 | saved_env = env; | |
506 | env = cpu_single_env; | |
97f90cbf | 507 | qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", |
faed1c2a EI |
508 | addr, is_write, is_exec); |
509 | if (!(env->sregs[SR_MSR] & MSR_EE)) { | |
95b279de | 510 | env = saved_env; |
faed1c2a EI |
511 | return; |
512 | } | |
513 | ||
97f90cbf | 514 | env->sregs[SR_EAR] = addr; |
faed1c2a | 515 | if (is_exec) { |
97f90cbf | 516 | if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { |
faed1c2a EI |
517 | env->sregs[SR_ESR] = ESR_EC_INSN_BUS; |
518 | helper_raise_exception(EXCP_HW_EXCP); | |
519 | } | |
520 | } else { | |
97f90cbf | 521 | if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { |
faed1c2a EI |
522 | env->sregs[SR_ESR] = ESR_EC_DATA_BUS; |
523 | helper_raise_exception(EXCP_HW_EXCP); | |
524 | } | |
525 | } | |
95b279de | 526 | env = saved_env; |
faed1c2a | 527 | } |
3c7b48b7 | 528 | #endif |