[qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <assert.h>
#include "exec.h"
#include "helper.h"
#include "host-utils.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc, NULL);
            }
        }
        cpu_loop_exit();
    }
    env = saved_env;
}
#endif

void helper_raise_exception(uint32_t index)
{
    env->exception_index = index;
    cpu_loop_exit();
}

void helper_debug(void)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_addkc(uint32_t a, uint32_t b, uint32_t cf)
{
    uint32_t d, ncf;

    d = a + b + cf;

    ncf = compute_carry(a, b, cf);
    return ncf;
}

uint32_t helper_subkc(uint32_t a, uint32_t b, uint32_t k, uint32_t c)
{
    uint32_t d, cf = 1, ncf;

    if (c)
        cf = env->sregs[SR_MSR] >> 31; 
    assert(cf == 0 || cf == 1);
    d = b + ~a + cf;

    if (!k) {
        ncf = compute_carry(b, ~a, cf);
        assert(ncf == 0 || ncf == 1);
        if (ncf)
            env->sregs[SR_MSR] |= MSR_C | MSR_CC;
        else
            env->sregs[SR_MSR] &= ~(MSR_C | MSR_CC);
    }
    D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n",
               d, a, b, cf, ncf, k, c));
    return d;
}

static inline int div_prepare(uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(void)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(EXCP_HW_EXCP);
}

static void update_fpu_flags(int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception();
    }
}

uint32_t helper_fadd(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_frsub(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_fmul(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fdiv(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return r;
}

uint32_t helper_fsqrt(uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int is_asi, int size)
{
    CPUState *saved_env;

    if (!cpu_single_env) {
        /* XXX: ???   */
        return;
    }

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;
    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write, is_exec);
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        env = saved_env;
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    }
    env = saved_env;
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	18	*/
	19
	20	#include <assert.h>
	21	#include "exec.h"
	22	#include "helper.h"
	23	#include "host-utils.h"
	24
	25	#define D(x)
	26
	27	#if !defined(CONFIG_USER_ONLY)
	28	#define MMUSUFFIX _mmu
	29	#define SHIFT 0
	30	#include "softmmu_template.h"
	31	#define SHIFT 1
	32	#include "softmmu_template.h"
	33	#define SHIFT 2
	34	#include "softmmu_template.h"
	35	#define SHIFT 3
	36	#include "softmmu_template.h"
	37
	38	/* Try to fill the TLB and return an exception if error. If retaddr is
	39	NULL, it means that the function was called in C code (i.e. not
	40	from generated code or from helper.c) */
	41	/* XXX: fix it to restore all registers */
	42	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
	43	{
	44	TranslationBlock *tb;
	45	CPUState *saved_env;
	46	unsigned long pc;
	47	int ret;
	48
	49	/* XXX: hack to restore env in all cases, even if not called from
	50	generated code */
	51	saved_env = env;
	52	env = cpu_single_env;
	53
	54	ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
	55	if (unlikely(ret)) {
	56	if (retaddr) {
	57	/* now we have a real cpu fault */
	58	pc = (unsigned long)retaddr;
	59	tb = tb_find_pc(pc);
	60	if (tb) {
	61	/* the PC is inside the translated code. It means that we have
	62	a virtual CPU fault */
	63	cpu_restore_state(tb, env, pc, NULL);
	64	}
	65	}
	66	cpu_loop_exit();
	67	}
	68	env = saved_env;
	69	}
	70	#endif
	71
	72	void helper_raise_exception(uint32_t index)
	73	{
	74	env->exception_index = index;
	75	cpu_loop_exit();
	76	}
	77
	78	void helper_debug(void)
	79	{
	80	int i;
	81
82	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	83	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	84	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	85	env->debug, env->imm, env->iflags);
	86	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	87	env->btaken, env->btarget,
	88	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	89	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	90	(env->sregs[SR_MSR] & MSR_EIP),
	91	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	92	for (i = 0; i < 32; i++) {
	93	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	94	if ((i + 1) % 4 == 0)
	95	qemu_log("\n");
	96	}
	97	qemu_log("\n\n");
	98	}
	99
	100	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	101	{
	102	uint32_t cout = 0;
	103
	104	if ((b == ~0) && cin)
	105	cout = 1;
	106	else if ((~0 - a) < (b + cin))
	107	cout = 1;
	108	return cout;
	109	}
	110
	111	uint32_t helper_cmp(uint32_t a, uint32_t b)
	112	{
	113	uint32_t t;
	114
	115	t = b + ~a + 1;
	116	if ((b & 0x80000000) ^ (a & 0x80000000))
	117	t = (t & 0x7fffffff) \| (b & 0x80000000);
	118	return t;
	119	}
	120
	121	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	122	{
	123	uint32_t t;
	124
	125	t = b + ~a + 1;
	126	if ((b & 0x80000000) ^ (a & 0x80000000))
	127	t = (t & 0x7fffffff) \| (a & 0x80000000);
	128	return t;
	129	}
	130
40cbf5b7	131	uint32_t helper_addkc(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	132	{
40cbf5b7	133	uint32_t d, ncf;
4acb54ba	134
4acb54ba EI	135	d = a + b + cf;
4acb54ba EI	136
40cbf5b7 EI	137	ncf = compute_carry(a, b, cf);
40cbf5b7 EI	138	return ncf;
4acb54ba EI	139	}
	140
	141	uint32_t helper_subkc(uint32_t a, uint32_t b, uint32_t k, uint32_t c)
	142	{
	143	uint32_t d, cf = 1, ncf;
	144
	145	if (c)
	146	cf = env->sregs[SR_MSR] >> 31;
	147	assert(cf == 0 \|\| cf == 1);
	148	d = b + ~a + cf;
	149
	150	if (!k) {
	151	ncf = compute_carry(b, ~a, cf);
	152	assert(ncf == 0 \|\| ncf == 1);
	153	if (ncf)
	154	env->sregs[SR_MSR] \|= MSR_C \| MSR_CC;
	155	else
	156	env->sregs[SR_MSR] &= ~(MSR_C \| MSR_CC);
	157	}
	158	D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n",
	159	d, a, b, cf, ncf, k, c));
	160	return d;
	161	}
	162
	163	static inline int div_prepare(uint32_t a, uint32_t b)
	164	{
	165	if (b == 0) {
	166	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	167
	168	if ((env->sregs[SR_MSR] & MSR_EE)
	169	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	170	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
	171	helper_raise_exception(EXCP_HW_EXCP);
	172	}
4acb54ba EI	173	return 0;
	174	}
	175	env->sregs[SR_MSR] &= ~MSR_DZ;
	176	return 1;
	177	}
	178
	179	uint32_t helper_divs(uint32_t a, uint32_t b)
	180	{
	181	if (!div_prepare(a, b))
	182	return 0;
	183	return (int32_t)a / (int32_t)b;
	184	}
	185
	186	uint32_t helper_divu(uint32_t a, uint32_t b)
	187	{
	188	if (!div_prepare(a, b))
	189	return 0;
	190	return a / b;
	191	}
	192
97694c57 EI	193	/* raise FPU exception. */
	194	static void raise_fpu_exception(void)
	195	{
	196	env->sregs[SR_ESR] = ESR_EC_FPU;
	197	helper_raise_exception(EXCP_HW_EXCP);
	198	}
	199
	200	static void update_fpu_flags(int flags)
	201	{
	202	int raise = 0;
	203
	204	if (flags & float_flag_invalid) {
	205	env->sregs[SR_FSR] \|= FSR_IO;
	206	raise = 1;
	207	}
	208	if (flags & float_flag_divbyzero) {
	209	env->sregs[SR_FSR] \|= FSR_DZ;
	210	raise = 1;
	211	}
	212	if (flags & float_flag_overflow) {
	213	env->sregs[SR_FSR] \|= FSR_OF;
	214	raise = 1;
	215	}
	216	if (flags & float_flag_underflow) {
	217	env->sregs[SR_FSR] \|= FSR_UF;
	218	raise = 1;
	219	}
	220	if (raise
	221	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	222	&& (env->sregs[SR_MSR] & MSR_EE)) {
	223	raise_fpu_exception();
	224	}
	225	}
	226
	227	uint32_t helper_fadd(uint32_t a, uint32_t b)
	228	{
	229	CPU_FloatU fd, fa, fb;
	230	int flags;
	231
	232	set_float_exception_flags(0, &env->fp_status);
	233	fa.l = a;
	234	fb.l = b;
	235	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	236
	237	flags = get_float_exception_flags(&env->fp_status);
	238	update_fpu_flags(flags);
	239	return fd.l;
	240	}
	241
	242	uint32_t helper_frsub(uint32_t a, uint32_t b)
	243	{
	244	CPU_FloatU fd, fa, fb;
	245	int flags;
	246
	247	set_float_exception_flags(0, &env->fp_status);
	248	fa.l = a;
	249	fb.l = b;
	250	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	251	flags = get_float_exception_flags(&env->fp_status);
	252	update_fpu_flags(flags);
	253	return fd.l;
	254	}
	255
	256	uint32_t helper_fmul(uint32_t a, uint32_t b)
257	{
258	CPU_FloatU fd, fa, fb;
259	int flags;
260
261	set_float_exception_flags(0, &env->fp_status);
262	fa.l = a;
263	fb.l = b;
264	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
265	flags = get_float_exception_flags(&env->fp_status);
266	update_fpu_flags(flags);
267
268	return fd.l;
269	}
270
271	uint32_t helper_fdiv(uint32_t a, uint32_t b)
272	{
273	CPU_FloatU fd, fa, fb;
274	int flags;
275
276	set_float_exception_flags(0, &env->fp_status);
277	fa.l = a;
278	fb.l = b;
279	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
280	flags = get_float_exception_flags(&env->fp_status);
281	update_fpu_flags(flags);
282
283	return fd.l;
284	}
285
286	uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
287	{
ef9d48da EI	288	CPU_FloatU fa, fb;
	289	uint32_t r = 0;
	290
	291	fa.l = a;
	292	fb.l = b;
	293
	294	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
	295	update_fpu_flags(float_flag_invalid);
	296	r = 1;
	297	}
	298
18569871	299	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	300	r = 1;
	301	}
	302
	303	return r;
97694c57 EI	304	}
	305
	306	uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
	307	{
	308	CPU_FloatU fa, fb;
	309	int r;
	310	int flags;
	311
	312	set_float_exception_flags(0, &env->fp_status);
	313	fa.l = a;
	314	fb.l = b;
	315	r = float32_lt(fb.f, fa.f, &env->fp_status);
	316	flags = get_float_exception_flags(&env->fp_status);
	317	update_fpu_flags(flags & float_flag_invalid);
	318
	319	return r;
	320	}
	321
	322	uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
	323	{
	324	CPU_FloatU fa, fb;
	325	int flags;
	326	int r;
	327
	328	set_float_exception_flags(0, &env->fp_status);
	329	fa.l = a;
	330	fb.l = b;
	331	r = float32_eq(fa.f, fb.f, &env->fp_status);
	332	flags = get_float_exception_flags(&env->fp_status);
	333	update_fpu_flags(flags & float_flag_invalid);
	334
	335	return r;
	336	}
	337
	338	uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
	339	{
	340	CPU_FloatU fa, fb;
	341	int flags;
	342	int r;
	343
	344	fa.l = a;
	345	fb.l = b;
	346	set_float_exception_flags(0, &env->fp_status);
	347	r = float32_le(fa.f, fb.f, &env->fp_status);
	348	flags = get_float_exception_flags(&env->fp_status);
	349	update_fpu_flags(flags & float_flag_invalid);
	350
	351
	352	return r;
	353	}
	354
	355	uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
	356	{
	357	CPU_FloatU fa, fb;
	358	int flags, r;
	359
	360	fa.l = a;
	361	fb.l = b;
	362	set_float_exception_flags(0, &env->fp_status);
	363	r = float32_lt(fa.f, fb.f, &env->fp_status);
	364	flags = get_float_exception_flags(&env->fp_status);
	365	update_fpu_flags(flags & float_flag_invalid);
	366	return r;
	367	}
368
369	uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
370	{
371	CPU_FloatU fa, fb;
372	int flags, r;
373
374	fa.l = a;
375	fb.l = b;
376	set_float_exception_flags(0, &env->fp_status);
377	r = !float32_eq(fa.f, fb.f, &env->fp_status);
378	flags = get_float_exception_flags(&env->fp_status);
379	update_fpu_flags(flags & float_flag_invalid);
380
381	return r;
382	}
383
384	uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
385	{
386	CPU_FloatU fa, fb;
387	int flags, r;
388
389	fa.l = a;
390	fb.l = b;
391	set_float_exception_flags(0, &env->fp_status);
392	r = !float32_lt(fa.f, fb.f, &env->fp_status);
393	flags = get_float_exception_flags(&env->fp_status);
394	update_fpu_flags(flags & float_flag_invalid);
395
396	return r;
397	}
398
399	uint32_t helper_flt(uint32_t a)
400	{
401	CPU_FloatU fd, fa;
402
403	fa.l = a;
404	fd.f = int32_to_float32(fa.l, &env->fp_status);
405	return fd.l;
406	}
407
408	uint32_t helper_fint(uint32_t a)
409	{
410	CPU_FloatU fa;
411	uint32_t r;
412	int flags;
413
414	set_float_exception_flags(0, &env->fp_status);
415	fa.l = a;
416	r = float32_to_int32(fa.f, &env->fp_status);
417	flags = get_float_exception_flags(&env->fp_status);
418	update_fpu_flags(flags);
419
420	return r;
421	}
422
423	uint32_t helper_fsqrt(uint32_t a)
424	{
425	CPU_FloatU fd, fa;
426	int flags;
427
428	set_float_exception_flags(0, &env->fp_status);
429	fa.l = a;
430	fd.l = float32_sqrt(fa.f, &env->fp_status);
431	flags = get_float_exception_flags(&env->fp_status);
432	update_fpu_flags(flags);
433
434	return fd.l;
435	}
436
4acb54ba EI	437	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	438	{
	439	unsigned int i;
	440	uint32_t mask = 0xff000000;
	441
	442	for (i = 0; i < 4; i++) {
	443	if ((a & mask) == (b & mask))
	444	return i + 1;
	445	mask >>= 8;
	446	}
	447	return 0;
	448	}
	449
3aa80988	450	void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
968a40f6	451	{
968a40f6	452	if (addr & mask) {
97f90cbf EI	453	qemu_log_mask(CPU_LOG_INT,
	454	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	455	addr, mask, wr, dr);
	456	env->sregs[SR_EAR] = addr;
968a40f6 EI	457	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	458	\| (dr & 31) << 5;
3aa80988	459	if (mask == 3) {
968a40f6 EI	460	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	461	}
97f90cbf EI	462	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	463	return;
	464	}
968a40f6 EI	465	helper_raise_exception(EXCP_HW_EXCP);
	466	}
	467	}
	468
4acb54ba EI	469	#if !defined(CONFIG_USER_ONLY)
	470	/* Writes/reads to the MMU's special regs end up here. */
	471	uint32_t helper_mmu_read(uint32_t rn)
	472	{
	473	return mmu_read(env, rn);
	474	}
	475
	476	void helper_mmu_write(uint32_t rn, uint32_t v)
	477	{
	478	mmu_write(env, rn, v);
	479	}
faed1c2a	480
c227f099	481	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
faed1c2a EI	482	int is_asi, int size)
	483	{
	484	CPUState *saved_env;
e1aa3254 EI	485
	486	if (!cpu_single_env) {
	487	/* XXX: ??? */
	488	return;
	489	}
	490
faed1c2a EI	491	/* XXX: hack to restore env in all cases, even if not called from
	492	generated code */
	493	saved_env = env;
	494	env = cpu_single_env;
97f90cbf	495	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
faed1c2a EI	496	addr, is_write, is_exec);
faed1c2a EI	497	if (!(env->sregs[SR_MSR] & MSR_EE)) {
95b279de	498	env = saved_env;
faed1c2a EI	499	return;
	500	}
	501
97f90cbf	502	env->sregs[SR_EAR] = addr;
faed1c2a	503	if (is_exec) {
97f90cbf	504	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a EI	505	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
	506	helper_raise_exception(EXCP_HW_EXCP);
	507	}
	508	} else {
97f90cbf	509	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a EI	510	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
	511	helper_raise_exception(EXCP_HW_EXCP);
	512	}
	513	}
95b279de	514	env = saved_env;
faed1c2a	515	}
3c7b48b7	516	#endif